Syzbot CI

Subject	riscv: Generate riscv instruction functions
Author	devnull@kernel.org
Date	2026-06-22 04:01:19 +0000 UTC
Version
Cc	akpm@linux-foundation.org alex@ghiti.fr anup@brainfault.org atish.patra@linux.dev conor@kernel.org devnull@kernel.org kvm-riscv@lists.infradead.org kvm@vger.kernel.org linux-kernel@vger.kernel.org linux-kselftest@vger.kernel.org linux-riscv@lists.infradead.org namcao@linutronix.de palmer@dabbelt.com pbonzini@redhat.com pjw@kernel.org radim.krcmar@oss.qualcomm.com shuah@kernel.org thecharlesjenkins@gmail.com

Subject

Author

devnull@kernel.org

Date

2026-06-22 04:01:19 +0000 UTC

Version

akpm@linux-foundation.org alex@ghiti.fr anup@brainfault.org atish.patra@linux.dev conor@kernel.org devnull@kernel.org kvm-riscv@lists.infradead.org kvm@vger.kernel.org linux-kernel@vger.kernel.org linux-kselftest@vger.kernel.org linux-riscv@lists.infradead.org namcao@linutronix.de palmer@dabbelt.com pbonzini@redhat.com pjw@kernel.org radim.krcmar@oss.qualcomm.com shuah@kernel.org thecharlesjenkins@gmail.com

Name	Content [All]
[PATCH v2 01/16] riscv: Introduce instruction table generation	[Body]
[PATCH v2 02/16] riscv: alternatives: Use generated instruction headers for patching code	[Body]
[PATCH v2 03/16] riscv: kgdb: Use generated instruction headers	[Body]
[PATCH v2 04/16] riscv: Add kprobes instruction simulation KUnit	[Body]
[PATCH v2 05/16] riscv: kprobes: Use generated instruction headers	[Body]
[PATCH v2 06/16] riscv: cfi: Use generated instruction headers	[Body]
[PATCH v2 07/16] riscv: Use generated instruction headers for misaligned loads/stores	[Body]
[PATCH v2 08/16] riscv: kvm: Use generated instruction headers for csr code	[Body]
[PATCH v2 09/16] KVM: device: Add test device	[Body]
[PATCH v2 10/16] KVM: riscv: selftests: Add mmio test	[Body]
[PATCH v2 11/16] riscv: kvm: Use generated instruction headers for mmio emulation	[Body]
[PATCH v2 12/16] riscv: kvm: Add emulated test csr	[Body]
[PATCH v2 13/16] KVM: riscv: selftests: Add csr emulation test	[Body]
[PATCH v2 14/16] riscv: kvm: Use generated instruction headers for csr emulation	[Body]
[PATCH v2 15/16] riscv: kexec: Use generated instruction headers for kexec relocations	[Body]
[PATCH v2 16/16] riscv: Remove unused instruction headers	[Body]

Name

Content [All]

Passed

Test	Base	Patched	Verdict
[KASAN] Build Base	8cd9520d35a6c38db6567e97dd93b1f11f185dc6 [Config]		passed [Log]
[KASAN] Boot test: Base	8cd9520d35a6c38db6567e97dd93b1f11f185dc6 [Config]		passed [Log]
[KASAN] Build Patched		8cd9520d35a6c38db6567e97dd93b1f11f185dc6 [Config] [patched]	passed [Log]
[KASAN] Boot test: Patched		8cd9520d35a6c38db6567e97dd93b1f11f185dc6 [Config] [patched]	passed [Log]
[KASAN] Fuzz	8cd9520d35a6c38db6567e97dd93b1f11f185dc6 [Config]	8cd9520d35a6c38db6567e97dd93b1f11f185dc6 [Config] [patched]	passed [Log] [Artifacts]