| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/06/22 04:18 | flow | patch-triage |
0mArgs:null Results: {
"EnableConfigs": null,
"FocusSymbols": [
"handle_scalar_misaligned_load",
"handle_scalar_misaligned_store",
"kvm_riscv_vcpu_mmio_load",
"kvm_riscv_vcpu_mmio_store",
"csr_insn",
"get_step_address",
"riscv_alternative_fix_auipc_jalr",
"decode_cfi_insn",
"simulate_jal",
"simulate_jalr",
"simulate_auipc",
"simulate_beq",
"simulate_bne",
"simulate_blt",
"simulate_bge",
"simulate_bltu",
"simulate_bgeu",
"simulate_c_j",
"simulate_c_jr",
"simulate_c_jalr",
"simulate_c_bnez",
"simulate_c_beqz"
],
"Reasoning": "The patch refactors RISC-V instruction decoding and encoding across core kernel subsystems including KVM, Kprobes, KGDB, alternative patching, and misaligned trap handling. These changes modify reachable core logic and should be fuzzed to ensure instruction decoding correctness.",
"WorthFuzzing": true
} |
| 1/1 | 2026/06/22 04:18 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit 4a3bc94d033b3e483aba144516c48bbef82e9be3\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Mon Jun 22 04:18:45 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug\nindex eafe17ebf7102c..be202267da6db9 100644\n--- a/arch/riscv/Kconfig.debug\n+++ b/arch/riscv/Kconfig.debug\n@@ -1 +1,2 @@\n source \"arch/riscv/kernel/tests/Kconfig.debug\"\n+source \"arch/riscv/kvm/Kconfig.debug\"\ndiff --git a/arch/riscv/Makefile b/arch/riscv/Makefile\nindex ce0cc737f87096..d14caa8720f858 100644\n--- a/arch/riscv/Makefile\n+++ b/arch/riscv/Makefile\n@@ -176,6 +176,9 @@ BOOT_TARGETS := Image Image.gz Image.bz2 Image.lz4 Image.lzma Image.lzo Image.zs\n \n all:\t$(notdir $(KBUILD_IMAGE))\n \n+archprepare:\n+\t$(Q)$(MAKE) $(build)=arch/riscv/tools insn\n+\n loader.bin: loader\n Image.gz Image.bz2 Image.lz4 Image.lzma Image.lzo Image.zst Image.xz loader xipImage vmlinuz.efi: Image\n \ndiff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild\nindex 7721b63642f413..16be4de3d0b1ec 100644\n--- a/arch/riscv/include/asm/Kbuild\n+++ b/arch/riscv/include/asm/Kbuild\n@@ -2,6 +2,7 @@\n syscall-y += syscall_table_32.h\n syscall-y += syscall_table_64.h\n \n+generated-y += insn_gen.h\n generic-y += early_ioremap.h\n generic-y += flat.h\n generic-y += fprobe.h\ndiff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h\nindex c3005573e8c999..ea1f139d6d9047 100644\n--- a/arch/riscv/include/asm/insn.h\n+++ b/arch/riscv/include/asm/insn.h\n@@ -8,151 +8,52 @@\n \n #include \u003clinux/bits.h\u003e\n \n-#define RV_INSN_FUNCT3_MASK\tGENMASK(14, 12)\n-#define RV_INSN_FUNCT3_OPOFF\t12\n-#define RV_INSN_OPCODE_MASK\tGENMASK(6, 0)\n-#define RV_INSN_OPCODE_OPOFF\t0\n-#define RV_INSN_FUNCT12_OPOFF\t20\n-\n-#define RV_ENCODE_FUNCT3(f_)\t(RVG_FUNCT3_##f_ \u003c\u003c RV_INSN_FUNCT3_OPOFF)\n-#define RV_ENCODE_FUNCT12(f_)\t(RVG_FUNCT12_##f_ \u003c\u003c RV_INSN_FUNCT12_OPOFF)\n-\n-/* The bit field of immediate value in I-type instruction */\n-#define RV_I_IMM_SIGN_OPOFF\t31\n-#define RV_I_IMM_11_0_OPOFF\t20\n-#define RV_I_IMM_SIGN_OFF\t12\n-#define RV_I_IMM_11_0_OFF\t0\n-#define RV_I_IMM_11_0_MASK\tGENMASK(11, 0)\n-\n-/* The bit field of immediate value in J-type instruction */\n-#define RV_J_IMM_SIGN_OPOFF\t31\n-#define RV_J_IMM_10_1_OPOFF\t21\n-#define RV_J_IMM_11_OPOFF\t20\n-#define RV_J_IMM_19_12_OPOFF\t12\n-#define RV_J_IMM_SIGN_OFF\t20\n-#define RV_J_IMM_10_1_OFF\t1\n-#define RV_J_IMM_11_OFF\t\t11\n-#define RV_J_IMM_19_12_OFF\t12\n-#define RV_J_IMM_10_1_MASK\tGENMASK(9, 0)\n-#define RV_J_IMM_11_MASK\tGENMASK(0, 0)\n-#define RV_J_IMM_19_12_MASK\tGENMASK(7, 0)\n-\n /*\n- * U-type IMMs contain the upper 20bits [31:20] of an immediate with\n- * the rest filled in by zeros, so no shifting required. Similarly,\n- * bit31 contains the signed state, so no sign extension necessary.\n+ * Generate a function to check if a sequence of bits matches an instruction\n */\n-#define RV_U_IMM_SIGN_OPOFF\t31\n-#define RV_U_IMM_31_12_OPOFF\t0\n-#define RV_U_IMM_31_12_MASK\tGENMASK(31, 12)\n-\n-/* The bit field of immediate value in B-type instruction */\n-#define RV_B_IMM_SIGN_OPOFF\t31\n-#define RV_B_IMM_10_5_OPOFF\t25\n-#define RV_B_IMM_4_1_OPOFF\t8\n-#define RV_B_IMM_11_OPOFF\t7\n-#define RV_B_IMM_SIGN_OFF\t12\n-#define RV_B_IMM_10_5_OFF\t5\n-#define RV_B_IMM_4_1_OFF\t1\n-#define RV_B_IMM_11_OFF\t\t11\n-#define RV_B_IMM_10_5_MASK\tGENMASK(5, 0)\n-#define RV_B_IMM_4_1_MASK\tGENMASK(3, 0)\n-#define RV_B_IMM_11_MASK\tGENMASK(0, 0)\n-\n-/* The register offset in RVG instruction */\n-#define RVG_RS1_OPOFF\t\t15\n-#define RVG_RS2_OPOFF\t\t20\n-#define RVG_RD_OPOFF\t\t7\n-#define RVG_RS1_MASK\t\tGENMASK(4, 0)\n-#define RVG_RS2_MASK\t\tGENMASK(4, 0)\n-#define RVG_RD_MASK\t\tGENMASK(4, 0)\n-\n-/* The bit field of immediate value in RVC J instruction */\n-#define RVC_J_IMM_SIGN_OPOFF\t12\n-#define RVC_J_IMM_4_OPOFF\t11\n-#define RVC_J_IMM_9_8_OPOFF\t9\n-#define RVC_J_IMM_10_OPOFF\t8\n-#define RVC_J_IMM_6_OPOFF\t7\n-#define RVC_J_IMM_7_OPOFF\t6\n-#define RVC_J_IMM_3_1_OPOFF\t3\n-#define RVC_J_IMM_5_OPOFF\t2\n-#define RVC_J_IMM_SIGN_OFF\t11\n-#define RVC_J_IMM_4_OFF\t\t4\n-#define RVC_J_IMM_9_8_OFF\t8\n-#define RVC_J_IMM_10_OFF\t10\n-#define RVC_J_IMM_6_OFF\t\t6\n-#define RVC_J_IMM_7_OFF\t\t7\n-#define RVC_J_IMM_3_1_OFF\t1\n-#define RVC_J_IMM_5_OFF\t\t5\n-#define RVC_J_IMM_4_MASK\tGENMASK(0, 0)\n-#define RVC_J_IMM_9_8_MASK\tGENMASK(1, 0)\n-#define RVC_J_IMM_10_MASK\tGENMASK(0, 0)\n-#define RVC_J_IMM_6_MASK\tGENMASK(0, 0)\n-#define RVC_J_IMM_7_MASK\tGENMASK(0, 0)\n-#define RVC_J_IMM_3_1_MASK\tGENMASK(2, 0)\n-#define RVC_J_IMM_5_MASK\tGENMASK(0, 0)\n-\n-/* The bit field of immediate value in RVC B instruction */\n-#define RVC_B_IMM_SIGN_OPOFF\t12\n-#define RVC_B_IMM_4_3_OPOFF\t10\n-#define RVC_B_IMM_7_6_OPOFF\t5\n-#define RVC_B_IMM_2_1_OPOFF\t3\n-#define RVC_B_IMM_5_OPOFF\t2\n-#define RVC_B_IMM_SIGN_OFF\t8\n-#define RVC_B_IMM_4_3_OFF\t3\n-#define RVC_B_IMM_7_6_OFF\t6\n-#define RVC_B_IMM_2_1_OFF\t1\n-#define RVC_B_IMM_5_OFF\t\t5\n-#define RVC_B_IMM_4_3_MASK\tGENMASK(1, 0)\n-#define RVC_B_IMM_7_6_MASK\tGENMASK(1, 0)\n-#define RVC_B_IMM_2_1_MASK\tGENMASK(1, 0)\n-#define RVC_B_IMM_5_MASK\tGENMASK(0, 0)\n+#define __RISCV_INSN_FUNCS(name)\t\t\t\t\t\t\t\\\n+static __always_inline bool riscv_insn_is_##name(u32 _insn)\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\t\t\\\n+\tBUILD_BUG_ON(~(riscv_insn_##name##_MASK) \u0026 (riscv_insn_##name##_MATCH));\t\\\n+\treturn (_insn \u0026 (riscv_insn_##name##_MASK)) == (riscv_insn_##name##_MATCH);\t\\\n+}\n \n-#define RVC_INSN_FUNCT4_MASK\tGENMASK(15, 12)\n-#define RVC_INSN_FUNCT4_OPOFF\t12\n-#define RVC_INSN_FUNCT3_MASK\tGENMASK(15, 13)\n-#define RVC_INSN_FUNCT3_OPOFF\t13\n-#define RVC_INSN_J_RS1_MASK\tGENMASK(11, 7)\n-#define RVC_INSN_J_RS2_MASK\tGENMASK(6, 2)\n-#define RVC_INSN_OPCODE_MASK\tGENMASK(1, 0)\n-#define RVC_ENCODE_FUNCT3(f_)\t(RVC_FUNCT3_##f_ \u003c\u003c RVC_INSN_FUNCT3_OPOFF)\n-#define RVC_ENCODE_FUNCT4(f_)\t(RVC_FUNCT4_##f_ \u003c\u003c RVC_INSN_FUNCT4_OPOFF)\n+/*\n+ * Generate a function to check if a sequence of bits matches an instruction\n+ * with constraints. Some instructions require inputs to be specific values.\n+ */\n+#define __RISCV_INSN_FUNCS_CONSTRAINED(name, constraints)\t\t\t\t\\\n+static __always_inline bool riscv_insn_is_##name(u32 _insn)\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\t\t\\\n+\tBUILD_BUG_ON(~(riscv_insn_##name##_MASK) \u0026 (riscv_insn_##name##_MATCH));\t\\\n+\treturn ((_insn \u0026 (riscv_insn_##name##_MASK)) == (riscv_insn_##name##_MATCH)) \u0026\u0026 \\\n+\t (constraints);\t\t\t\t\t\t\t\t\\\n+}\n \n-/* The register offset in RVC op=C0 instruction */\n-#define RVC_C0_RS1_OPOFF\t7\n-#define RVC_C0_RS2_OPOFF\t2\n-#define RVC_C0_RD_OPOFF\t\t2\n+#define __RISCV_INSN_FUNCS_UNSUPPORTED(name)\t\t\t\t\\\n+static __always_inline bool riscv_insn_is_##name(u32 _insn)\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\treturn 0;\t\t\t\t\t\t\t\\\n+}\n \n-/* The register offset in RVC op=C1 instruction */\n-#define RVC_C1_RS1_OPOFF\t7\n-#define RVC_C1_RS2_OPOFF\t2\n-#define RVC_C1_RD_OPOFF\t\t7\n+#include \u003casm/insn_gen.h\u003e\n \n-/* The register offset in RVC op=C2 instruction */\n-#define RVC_C2_RS1_OPOFF\t7\n-#define RVC_C2_RS2_OPOFF\t2\n-#define RVC_C2_RD_OPOFF\t\t7\n-#define RVC_C2_RS1_MASK\t\tGENMASK(4, 0)\n+#define RV_INSN_OPCODE_MASK\tGENMASK(6, 0)\n \n /* parts of opcode for RVG*/\n-#define RVG_OPCODE_FENCE\t0x0f\n-#define RVG_OPCODE_AUIPC\t0x17\n #define RVG_OPCODE_BRANCH\t0x63\n-#define RVG_OPCODE_JALR\t\t0x67\n-#define RVG_OPCODE_JAL\t\t0x6f\n #define RVG_OPCODE_SYSTEM\t0x73\n #define RVG_SYSTEM_CSR_OFF\t20\n #define RVG_SYSTEM_CSR_MASK\tGENMASK(12, 0)\n \n+// THESE ARE ALL ACTUALLY USED\n /* parts of opcode for RVF, RVD and RVQ */\n #define RVFDQ_FL_FS_WIDTH_OFF\t12\n #define RVFDQ_FL_FS_WIDTH_MASK\tGENMASK(2, 0)\n-#define RVFDQ_FL_FS_WIDTH_W\t2\n-#define RVFDQ_FL_FS_WIDTH_D\t3\n-#define RVFDQ_LS_FS_WIDTH_Q\t4\n #define RVFDQ_OPCODE_FL\t\t0x07\n #define RVFDQ_OPCODE_FS\t\t0x27\n \n+// THESE ARE ALL ACTUALLY USED\n /* parts of opcode for RVV */\n #define RVV_OPCODE_VECTOR\t0x57\n #define RVV_VL_VS_WIDTH_8\t0\n@@ -162,107 +63,11 @@\n #define RVV_OPCODE_VL\t\tRVFDQ_OPCODE_FL\n #define RVV_OPCODE_VS\t\tRVFDQ_OPCODE_FS\n \n-/* parts of opcode for RVC*/\n-#define RVC_OPCODE_C0\t\t0x0\n-#define RVC_OPCODE_C1\t\t0x1\n-#define RVC_OPCODE_C2\t\t0x2\n-\n-/* parts of funct3 code for I, M, A extension*/\n-#define RVG_FUNCT3_JALR\t\t0x0\n-#define RVG_FUNCT3_BEQ\t\t0x0\n-#define RVG_FUNCT3_BNE\t\t0x1\n-#define RVG_FUNCT3_BLT\t\t0x4\n-#define RVG_FUNCT3_BGE\t\t0x5\n-#define RVG_FUNCT3_BLTU\t\t0x6\n-#define RVG_FUNCT3_BGEU\t\t0x7\n-\n-/* parts of funct3 code for C extension*/\n-#define RVC_FUNCT3_C_BEQZ\t0x6\n-#define RVC_FUNCT3_C_BNEZ\t0x7\n-#define RVC_FUNCT3_C_J\t\t0x5\n-#define RVC_FUNCT3_C_JAL\t0x1\n-#define RVC_FUNCT4_C_JR\t\t0x8\n-#define RVC_FUNCT4_C_JALR\t0x9\n-#define RVC_FUNCT4_C_EBREAK\t0x9\n-\n-#define RVG_FUNCT12_EBREAK\t0x1\n-#define RVG_FUNCT12_SRET\t0x102\n-\n-#define RVG_MATCH_AUIPC\t\t(RVG_OPCODE_AUIPC)\n-#define RVG_MATCH_JALR\t\t(RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)\n-#define RVG_MATCH_JAL\t\t(RVG_OPCODE_JAL)\n-#define RVG_MATCH_FENCE\t\t(RVG_OPCODE_FENCE)\n-#define RVG_MATCH_BEQ\t\t(RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BNE\t\t(RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BLT\t\t(RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BGE\t\t(RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BLTU\t\t(RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BGEU\t\t(RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_EBREAK\t(RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM)\n-#define RVG_MATCH_SRET\t\t(RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM)\n-#define RVC_MATCH_C_BEQZ\t(RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1)\n-#define RVC_MATCH_C_BNEZ\t(RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1)\n-#define RVC_MATCH_C_J\t\t(RVC_ENCODE_FUNCT3(C_J) | RVC_OPCODE_C1)\n-#define RVC_MATCH_C_JAL\t\t(RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1)\n-#define RVC_MATCH_C_JR\t\t(RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2)\n-#define RVC_MATCH_C_JALR\t(RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)\n-#define RVC_MATCH_C_EBREAK\t(RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)\n-\n-#define RVG_MASK_AUIPC\t\t(RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_JALR\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_JAL\t\t(RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_FENCE\t\t(RV_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_JALR\t\t(RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_JR\t\t(RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_JAL\t\t(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_J\t\t(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVG_MASK_BEQ\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BNE\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BLT\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BGE\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BLTU\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BGEU\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_BEQZ\t\t(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_BNEZ\t\t(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_EBREAK\t0xffff\n-#define RVG_MASK_EBREAK\t\t0xffffffff\n-#define RVG_MASK_SRET\t\t0xffffffff\n-\n #define __INSN_LENGTH_MASK\t_UL(0x3)\n #define __INSN_LENGTH_GE_32\t_UL(0x3)\n #define __INSN_OPCODE_MASK\t_UL(0x7F)\n #define __INSN_BRANCH_OPCODE\t_UL(RVG_OPCODE_BRANCH)\n \n-#define __RISCV_INSN_FUNCS(name, mask, val)\t\t\t\t\\\n-static __always_inline bool riscv_insn_is_##name(u32 code)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tBUILD_BUG_ON(~(mask) \u0026 (val));\t\t\t\t\t\\\n-\treturn (code \u0026 (mask)) == (val);\t\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\n-#if __riscv_xlen == 32\n-/* C.JAL is an RV32C-only instruction */\n-__RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)\n-#else\n-#define riscv_insn_is_c_jal(opcode) 0\n-#endif\n-__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)\n-__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)\n-__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)\n-__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)\n-__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)\n-__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)\n-__RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT)\n-__RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE)\n-__RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU)\n-__RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU)\n-__RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ)\n-__RISCV_INSN_FUNCS(c_bnez, RVC_MASK_C_BNEZ, RVC_MATCH_C_BNEZ)\n-__RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK)\n-__RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK)\n-__RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET)\n-__RISCV_INSN_FUNCS(fence, RVG_MASK_FENCE, RVG_MATCH_FENCE);\n-\n /* special case to catch _any_ system instruction */\n static __always_inline bool riscv_insn_is_system(u32 code)\n {\n@@ -275,248 +80,26 @@ static __always_inline bool riscv_insn_is_branch(u32 code)\n \treturn (code \u0026 RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;\n }\n \n-static __always_inline bool riscv_insn_is_c_jr(u32 code)\n-{\n-\treturn (code \u0026 RVC_MASK_C_JR) == RVC_MATCH_C_JR \u0026\u0026\n-\t (code \u0026 RVC_INSN_J_RS1_MASK) != 0;\n-}\n-\n-static __always_inline bool riscv_insn_is_c_jalr(u32 code)\n-{\n-\treturn (code \u0026 RVC_MASK_C_JALR) == RVC_MATCH_C_JALR \u0026\u0026\n-\t (code \u0026 RVC_INSN_J_RS1_MASK) != 0;\n-}\n-\n-#define INSN_MATCH_LB\t\t0x3\n-#define INSN_MASK_LB\t\t0x707f\n-#define INSN_MATCH_LH\t\t0x1003\n-#define INSN_MASK_LH\t\t0x707f\n-#define INSN_MATCH_LW\t\t0x2003\n-#define INSN_MASK_LW\t\t0x707f\n-#define INSN_MATCH_LD\t\t0x3003\n-#define INSN_MASK_LD\t\t0x707f\n-#define INSN_MATCH_LBU\t\t0x4003\n-#define INSN_MASK_LBU\t\t0x707f\n-#define INSN_MATCH_LHU\t\t0x5003\n-#define INSN_MASK_LHU\t\t0x707f\n-#define INSN_MATCH_LWU\t\t0x6003\n-#define INSN_MASK_LWU\t\t0x707f\n-#define INSN_MATCH_SB\t\t0x23\n-#define INSN_MASK_SB\t\t0x707f\n-#define INSN_MATCH_SH\t\t0x1023\n-#define INSN_MASK_SH\t\t0x707f\n-#define INSN_MATCH_SW\t\t0x2023\n-#define INSN_MASK_SW\t\t0x707f\n-#define INSN_MATCH_SD\t\t0x3023\n-#define INSN_MASK_SD\t\t0x707f\n-\n-#define INSN_MATCH_C_LD\t\t0x6000\n-#define INSN_MASK_C_LD\t\t0xe003\n-#define INSN_MATCH_C_SD\t\t0xe000\n-#define INSN_MASK_C_SD\t\t0xe003\n-#define INSN_MATCH_C_LW\t\t0x4000\n-#define INSN_MASK_C_LW\t\t0xe003\n-#define INSN_MATCH_C_SW\t\t0xc000\n-#define INSN_MASK_C_SW\t\t0xe003\n-#define INSN_MATCH_C_LDSP\t0x6002\n-#define INSN_MASK_C_LDSP\t0xe003\n-#define INSN_MATCH_C_SDSP\t0xe002\n-#define INSN_MASK_C_SDSP\t0xe003\n-#define INSN_MATCH_C_LWSP\t0x4002\n-#define INSN_MASK_C_LWSP\t0xe003\n-#define INSN_MATCH_C_SWSP\t0xc002\n-#define INSN_MASK_C_SWSP\t0xe003\n-\n #define INSN_OPCODE_MASK\t0x007c\n #define INSN_OPCODE_SHIFT\t2\n #define INSN_OPCODE_SYSTEM\t28\n \n-#define INSN_MASK_WFI\t\t0xffffffff\n-#define INSN_MATCH_WFI\t\t0x10500073\n-\n-#define INSN_MASK_WRS\t\t0xffffffff\n-#define INSN_MATCH_WRS\t\t0x00d00073\n-\n-#define INSN_MATCH_CSRRW\t0x1073\n-#define INSN_MASK_CSRRW\t\t0x707f\n-#define INSN_MATCH_CSRRS\t0x2073\n-#define INSN_MASK_CSRRS\t\t0x707f\n-#define INSN_MATCH_CSRRC\t0x3073\n-#define INSN_MASK_CSRRC\t\t0x707f\n-#define INSN_MATCH_CSRRWI\t0x5073\n-#define INSN_MASK_CSRRWI\t0x707f\n-#define INSN_MATCH_CSRRSI\t0x6073\n-#define INSN_MASK_CSRRSI\t0x707f\n-#define INSN_MATCH_CSRRCI\t0x7073\n-#define INSN_MASK_CSRRCI\t0x707f\n-\n-#define INSN_MATCH_FLW\t\t0x2007\n-#define INSN_MASK_FLW\t\t0x707f\n-#define INSN_MATCH_FLD\t\t0x3007\n-#define INSN_MASK_FLD\t\t0x707f\n-#define INSN_MATCH_FLQ\t\t0x4007\n-#define INSN_MASK_FLQ\t\t0x707f\n-#define INSN_MATCH_FSW\t\t0x2027\n-#define INSN_MASK_FSW\t\t0x707f\n-#define INSN_MATCH_FSD\t\t0x3027\n-#define INSN_MASK_FSD\t\t0x707f\n-#define INSN_MATCH_FSQ\t\t0x4027\n-#define INSN_MASK_FSQ\t\t0x707f\n-\n-#define INSN_MATCH_C_FLD\t0x2000\n-#define INSN_MASK_C_FLD\t\t0xe003\n-#define INSN_MATCH_C_FLW\t0x6000\n-#define INSN_MASK_C_FLW\t\t0xe003\n-#define INSN_MATCH_C_FSD\t0xa000\n-#define INSN_MASK_C_FSD\t\t0xe003\n-#define INSN_MATCH_C_FSW\t0xe000\n-#define INSN_MASK_C_FSW\t\t0xe003\n-#define INSN_MATCH_C_FLDSP\t0x2002\n-#define INSN_MASK_C_FLDSP\t0xe003\n-#define INSN_MATCH_C_FSDSP\t0xa002\n-#define INSN_MASK_C_FSDSP\t0xe003\n-#define INSN_MATCH_C_FLWSP\t0x6002\n-#define INSN_MASK_C_FLWSP\t0xe003\n-#define INSN_MATCH_C_FSWSP\t0xe002\n-#define INSN_MASK_C_FSWSP\t0xe003\n-\n-#define INSN_MATCH_C_LHU\t\t0x8400\n-#define INSN_MASK_C_LHU\t\t\t0xfc43\n-#define INSN_MATCH_C_LH\t\t\t0x8440\n-#define INSN_MASK_C_LH\t\t\t0xfc43\n-#define INSN_MATCH_C_SH\t\t\t0x8c00\n-#define INSN_MASK_C_SH\t\t\t0xfc43\n-\n #define INSN_16BIT_MASK\t\t0x3\n #define INSN_IS_16BIT(insn)\t(((insn) \u0026 INSN_16BIT_MASK) != INSN_16BIT_MASK)\n #define INSN_LEN(insn)\t\t(INSN_IS_16BIT(insn) ? 2 : 4)\n \n-#define SHIFT_RIGHT(x, y)\t\t\\\n-\t((y) \u003c 0 ? ((x) \u003c\u003c -(y)) : ((x) \u003e\u003e (y)))\n-\n #define REG_MASK\t\t\t\\\n \t((1 \u003c\u003c (5 + LOG_REGBYTES)) - (1 \u003c\u003c LOG_REGBYTES))\n \n-#define REG_OFFSET(insn, pos)\t\t\\\n-\t(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) \u0026 REG_MASK)\n-\n-#define REG_PTR(insn, pos, regs)\t\\\n-\t((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))\n-\n-#define GET_RS1(insn, regs)\t(*REG_PTR(insn, SH_RS1, regs))\n-#define GET_RS2(insn, regs)\t(*REG_PTR(insn, SH_RS2, regs))\n-#define GET_RS1S(insn, regs)\t(*REG_PTR(RVC_RS1S(insn), 0, regs))\n-#define GET_RS2S(insn, regs)\t(*REG_PTR(RVC_RS2S(insn), 0, regs))\n-#define GET_RS2C(insn, regs)\t(*REG_PTR(insn, SH_RS2C, regs))\n-#define GET_SP(regs)\t\t(*REG_PTR(2, 0, regs))\n-#define SET_RD(insn, regs, val)\t(*REG_PTR(insn, SH_RD, regs) = (val))\n-#define IMM_I(insn)\t\t((s32)(insn) \u003e\u003e 20)\n-#define IMM_S(insn)\t\t(((s32)(insn) \u003e\u003e 25 \u003c\u003c 5) | \\\n-\t\t\t\t (s32)(((insn) \u003e\u003e 7) \u0026 0x1f))\n-\n-#define SH_RD\t\t\t7\n-#define SH_RS1\t\t\t15\n-#define SH_RS2\t\t\t20\n-#define SH_RS2C\t\t\t2\n-#define MASK_RX\t\t\t0x1f\n-\n #if defined(CONFIG_64BIT)\n #define LOG_REGBYTES\t\t3\n #else\n #define LOG_REGBYTES\t\t2\n #endif\n \n-#define MASK_FUNCT3\t\t0x7000\n-\n-#define GET_FUNCT3(insn)\t(((insn) \u003e\u003e 12) \u0026 7)\n-\n-#define RV_IMM_SIGN(x)\t\t(-(((x) \u003e\u003e 31) \u0026 1))\n-#define RVC_IMM_SIGN(x)\t\t(-(((x) \u003e\u003e 12) \u0026 1))\n-#define RV_X_MASK(X, s, mask)\t(((X) \u003e\u003e (s)) \u0026 (mask))\n-#define RV_X(X, s, n)\t\tRV_X_MASK(X, s, ((1 \u003c\u003c (n)) - 1))\n-#define RVC_LW_IMM(x)\t\t((RV_X(x, 6, 1) \u003c\u003c 2) | \\\n-\t\t\t\t (RV_X(x, 10, 3) \u003c\u003c 3) | \\\n-\t\t\t\t (RV_X(x, 5, 1) \u003c\u003c 6))\n-#define RVC_LD_IMM(x)\t\t((RV_X(x, 10, 3) \u003c\u003c 3) | \\\n-\t\t\t\t (RV_X(x, 5, 2) \u003c\u003c 6))\n-#define RVC_LWSP_IMM(x)\t\t((RV_X(x, 4, 3) \u003c\u003c 2) | \\\n-\t\t\t\t (RV_X(x, 12, 1) \u003c\u003c 5) | \\\n-\t\t\t\t (RV_X(x, 2, 2) \u003c\u003c 6))\n-#define RVC_LDSP_IMM(x)\t\t((RV_X(x, 5, 2) \u003c\u003c 3) | \\\n-\t\t\t\t (RV_X(x, 12, 1) \u003c\u003c 5) | \\\n-\t\t\t\t (RV_X(x, 2, 3) \u003c\u003c 6))\n-#define RVC_SWSP_IMM(x)\t\t((RV_X(x, 9, 4) \u003c\u003c 2) | \\\n-\t\t\t\t (RV_X(x, 7, 2) \u003c\u003c 6))\n-#define RVC_SDSP_IMM(x)\t\t((RV_X(x, 10, 3) \u003c\u003c 3) | \\\n-\t\t\t\t (RV_X(x, 7, 3) \u003c\u003c 6))\n-#define RVC_RS1S(insn)\t\t(8 + RV_X(insn, SH_RD, 3))\n-#define RVC_RS2S(insn)\t\t(8 + RV_X(insn, SH_RS2C, 3))\n-#define RVC_RS2(insn)\t\tRV_X(insn, SH_RS2C, 5)\n-#define RVC_X(X, s, mask)\tRV_X_MASK(X, s, mask)\n-\n-#define RV_EXTRACT_FUNCT3(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_INSN_FUNCT3_OPOFF, \\\n-\t\t RV_INSN_FUNCT3_MASK \u003e\u003e RV_INSN_FUNCT3_OPOFF)); })\n-\n-#define RV_EXTRACT_RS1_REG(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })\n-\n-#define RV_EXTRACT_RS2_REG(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RVG_RS2_OPOFF, RVG_RS2_MASK)); })\n-\n-#define RV_EXTRACT_RD_REG(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })\n-\n-#define RV_EXTRACT_UTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })\n-\n-#define RV_EXTRACT_JTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) \u003c\u003c RV_J_IMM_10_1_OFF) | \\\n-\t(RV_X_MASK(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) \u003c\u003c RV_J_IMM_11_OFF) | \\\n-\t(RV_X_MASK(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) \u003c\u003c RV_J_IMM_19_12_OFF) | \\\n-\t(RV_IMM_SIGN(x_) \u003c\u003c RV_J_IMM_SIGN_OFF); })\n-\n-#define RV_EXTRACT_ITYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \\\n-\t(RV_IMM_SIGN(x_) \u003c\u003c RV_I_IMM_SIGN_OFF); })\n-\n-#define RV_EXTRACT_BTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) \u003c\u003c RV_B_IMM_4_1_OFF) | \\\n-\t(RV_X_MASK(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) \u003c\u003c RV_B_IMM_10_5_OFF) | \\\n-\t(RV_X_MASK(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) \u003c\u003c RV_B_IMM_11_OFF) | \\\n-\t(RV_IMM_SIGN(x_) \u003c\u003c RV_B_IMM_SIGN_OFF); })\n-\n-#define RVC_EXTRACT_C2_RS1_REG(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })\n-\n-#define RVC_EXTRACT_JTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) \u003c\u003c RVC_J_IMM_3_1_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) \u003c\u003c RVC_J_IMM_4_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) \u003c\u003c RVC_J_IMM_5_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) \u003c\u003c RVC_J_IMM_6_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) \u003c\u003c RVC_J_IMM_7_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) \u003c\u003c RVC_J_IMM_9_8_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) \u003c\u003c RVC_J_IMM_10_OFF) | \\\n-\t(RVC_IMM_SIGN(x_) \u003c\u003c RVC_J_IMM_SIGN_OFF); })\n-\n-#define RVC_EXTRACT_BTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) \u003c\u003c RVC_B_IMM_2_1_OFF) | \\\n-\t(RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) \u003c\u003c RVC_B_IMM_4_3_OFF) | \\\n-\t(RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) \u003c\u003c RVC_B_IMM_5_OFF) | \\\n-\t(RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) \u003c\u003c RVC_B_IMM_7_6_OFF) | \\\n-\t(RVC_IMM_SIGN(x_) \u003c\u003c RVC_B_IMM_SIGN_OFF); })\n+#define RV_X_MASK(X, s, mask) (((X) \u003e\u003e (s)) \u0026 (mask))\n \n+// These three are used by vector stuff\n #define RVG_EXTRACT_SYSTEM_CSR(x) \\\n \t({typeof(x) x_ = (x); RV_X_MASK(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })\n \n@@ -526,78 +109,32 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)\n \n #define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)\n \n-/*\n- * Get the immediate from a J-type instruction.\n- *\n- * @insn: instruction to process\n- * Return: immediate\n- */\n-static inline s32 riscv_insn_extract_jtype_imm(u32 insn)\n-{\n-\treturn RV_EXTRACT_JTYPE_IMM(insn);\n-}\n-\n-/*\n- * Update a J-type instruction with an immediate value.\n- *\n- * @insn: pointer to the jtype instruction\n- * @imm: the immediate to insert into the instruction\n- */\n-static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm)\n+static inline unsigned long riscv_insn_reg_get_val(unsigned long *regs, u32 index)\n {\n-\t/* drop the old IMMs, all jal IMM bits sit at 31:12 */\n-\t*insn \u0026= ~GENMASK(31, 12);\n-\t*insn |= (RV_X_MASK(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) \u003c\u003c RV_J_IMM_10_1_OPOFF) |\n-\t\t (RV_X_MASK(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) \u003c\u003c RV_J_IMM_11_OPOFF) |\n-\t\t (RV_X_MASK(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) \u003c\u003c RV_J_IMM_19_12_OPOFF) |\n-\t\t (RV_X_MASK(imm, RV_J_IMM_SIGN_OFF, 1) \u003c\u003c RV_J_IMM_SIGN_OPOFF);\n+\t/* register 0 is always 0 and not stored in the register struct */\n+\treturn index ? *(regs + index) : 0;\n }\n \n-/*\n- * Put together one immediate from a U-type and I-type instruction pair.\n- *\n- * The U-type contains an upper immediate, meaning bits[31:12] with [11:0]\n- * being zero, while the I-type contains a 12bit immediate.\n- * Combined these can encode larger 32bit values and are used for example\n- * in auipc + jalr pairs to allow larger jumps.\n- *\n- * @utype_insn: instruction containing the upper immediate\n- * @itype_insn: instruction\n- * Return: combined immediate\n- */\n-static inline s32 riscv_insn_extract_utype_itype_imm(u32 utype_insn, u32 itype_insn)\n+static inline void riscv_insn_reg_set_val(unsigned long *regs, u32 index, unsigned long val)\n {\n-\ts32 imm;\n-\n-\timm = RV_EXTRACT_UTYPE_IMM(utype_insn);\n-\timm += RV_EXTRACT_ITYPE_IMM(itype_insn);\n-\n-\treturn imm;\n+\t/* register 0 is always 0 and not stored in the register struct */\n+\tif (index != 0)\n+\t\t*(regs + index) = val;\n }\n \n-/*\n- * Update a set of two instructions (U-type + I-type) with an immediate value.\n- *\n- * Used for example in auipc+jalrs pairs the U-type instructions contains\n- * a 20bit upper immediate representing bits[31:12], while the I-type\n- * instruction contains a 12bit immediate representing bits[11:0].\n- *\n- * This also takes into account that both separate immediates are\n- * considered as signed values, so if the I-type immediate becomes\n- * negative (BIT(11) set) the U-type part gets adjusted.\n- *\n- * @utype_insn: pointer to the utype instruction of the pair\n- * @itype_insn: pointer to the itype instruction of the pair\n- * @imm: the immediate to insert into the two instructions\n- */\n-static inline void riscv_insn_insert_utype_itype_imm(u32 *utype_insn, u32 *itype_insn, s32 imm)\n-{\n-\t/* drop possible old IMM values */\n-\t*utype_insn \u0026= ~(RV_U_IMM_31_12_MASK);\n-\t*itype_insn \u0026= ~(RV_I_IMM_11_0_MASK \u003c\u003c RV_I_IMM_11_0_OPOFF);\n+#define riscv_insn_branch(_insn, regs_ptr, _opcode, _pc, _comparison, type) \\\n+\t({ \\\n+\t\tunsigned long _ret; \\\n+\t\tif ((type)riscv_insn_reg_get_val( \\\n+\t\t\t regs_ptr, \\\n+\t\t\t riscv_insn_##_insn##_extract_xs1(_opcode)) \\\n+\t\t\t _comparison(type) riscv_insn_reg_get_val( \\\n+\t\t\t\t regs_ptr, \\\n+\t\t\t\t riscv_insn_##_insn##_extract_xs2(_opcode))) \\\n+\t\t\t_ret = _pc + riscv_insn_##_insn##_extract_imm(_opcode); \\\n+\t\telse \\\n+\t\t\t_ret = _pc + 4; \\\n+\t\t_ret; \\\n+\t})\n \n-\t/* add the adapted IMMs */\n-\t*utype_insn |= (imm \u0026 RV_U_IMM_31_12_MASK) + ((imm \u0026 BIT(11)) \u003c\u003c 1);\n-\t*itype_insn |= ((imm \u0026 RV_I_IMM_11_0_MASK) \u003c\u003c RV_I_IMM_11_0_OPOFF);\n-}\n #endif /* _ASM_RISCV_INSN_H */\ndiff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h\nindex 75b0a951c1bc6f..4d30d30ebefc73 100644\n--- a/arch/riscv/include/asm/kvm_host.h\n+++ b/arch/riscv/include/asm/kvm_host.h\n@@ -167,6 +167,12 @@ struct kvm_vcpu_reset_state {\n \tunsigned long a1;\n };\n \n+#ifdef CONFIG_RISCV_KVM_TEST_CSR\n+struct kvm_test_csr {\n+\tunsigned long val;\n+};\n+#endif\n+\n struct kvm_vcpu_arch {\n \t/* VCPU ran at least once */\n \tbool ran_atleast_once;\n@@ -265,6 +271,10 @@ struct kvm_vcpu_arch {\n \t\tgpa_t shmem;\n \t\tu64 last_steal;\n \t} sta;\n+\n+#ifdef CONFIG_RISCV_KVM_TEST_CSR\n+\tstruct kvm_test_csr test_csr;\n+#endif\n };\n \n /*\ndiff --git a/arch/riscv/include/asm/kvm_vcpu_insn.h b/arch/riscv/include/asm/kvm_vcpu_insn.h\nindex 350011c83581cb..01efdaaede217b 100644\n--- a/arch/riscv/include/asm/kvm_vcpu_insn.h\n+++ b/arch/riscv/include/asm/kvm_vcpu_insn.h\n@@ -11,7 +11,7 @@ struct kvm_run;\n struct kvm_cpu_trap;\n \n struct kvm_mmio_decode {\n-\tunsigned long insn;\n+\tunsigned long rd;\n \tint insn_len;\n \tint len;\n \tint shift;\n@@ -19,7 +19,8 @@ struct kvm_mmio_decode {\n };\n \n struct kvm_csr_decode {\n-\tunsigned long insn;\n+\tunsigned long rd;\n+\tunsigned long insn_len;\n \tint return_handled;\n };\n \ndiff --git a/arch/riscv/include/asm/kvm_vcpu_test_csr.h b/arch/riscv/include/asm/kvm_vcpu_test_csr.h\nnew file mode 100644\nindex 00000000000000..a844fccaafc346\n--- /dev/null\n+++ b/arch/riscv/include/asm/kvm_vcpu_test_csr.h\n@@ -0,0 +1,15 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+\n+#ifndef __KVM_VCPU_RISCV_TEST_CSR_H\n+#define __KVM_VCPU_RISCV_TEST_CSR_H\n+\n+#include \u003casm/kvm_vcpu_insn.h\u003e\n+\n+#define KVM_RISCV_VCPU_TEST_CSR_FUNCS \\\n+\t{.base = CSR_VSSCRATCH,\t.count = 1,\t.func = kvm_riscv_vcpu_test_csr },\n+\n+int kvm_riscv_vcpu_test_csr(struct kvm_vcpu *vcpu, unsigned int csr_num,\n+\t\t\t unsigned long *val, unsigned long new_val,\n+\t\t\t unsigned long wr_mask);\n+\n+#endif /* !__KVM_VCPU_RISCV_TEST_CSR_H */\ndiff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c\nindex 7642704c7f1841..b26a90eb65ccac 100644\n--- a/arch/riscv/kernel/alternative.c\n+++ b/arch/riscv/kernel/alternative.c\n@@ -11,6 +11,7 @@\n #include \u003clinux/cpu.h\u003e\n #include \u003clinux/uaccess.h\u003e\n #include \u003casm/alternative.h\u003e\n+#include \u003casm/insn.h\u003e\n #include \u003casm/module.h\u003e\n #include \u003casm/sections.h\u003e\n #include \u003casm/vdso.h\u003e\n@@ -78,14 +79,24 @@ static void riscv_alternative_fix_auipc_jalr(void *ptr, u32 auipc_insn,\n \t\t\t\t\t u32 jalr_insn, int patch_offset)\n {\n \tu32 call[2] = { auipc_insn, jalr_insn };\n+\tu32 auipc_imm;\n \ts32 imm;\n \n \t/* get and adjust new target address */\n-\timm = riscv_insn_extract_utype_itype_imm(auipc_insn, jalr_insn);\n+\timm = riscv_insn_auipc_extract_imm(auipc_insn) + riscv_insn_jalr_extract_imm(jalr_insn);\n \timm -= patch_offset;\n \n+\t/*\n+\t * When the 32-bit immediate is split across auipc and jalr, the\n+\t * constructed immediates need to be treated as individually sign\n+\t * extended numbers. Add the sign bit of the lower 12 bits to the upper\n+\t * 20 bits to undo the bleeding of the sign.\n+\t */\n+\tauipc_imm = imm + (BIT(11) \u003c\u003c 1);\n+\n \t/* update instructions */\n-\triscv_insn_insert_utype_itype_imm(\u0026call[0], \u0026call[1], imm);\n+\triscv_insn_auipc_insert_imm(\u0026call[0], auipc_imm);\n+\triscv_insn_jalr_insert_imm(\u0026call[1], imm);\n \n \t/* patch the call place again */\n \tpatch_text_nosync(ptr, call, sizeof(u32) * 2);\n@@ -96,11 +107,11 @@ static void riscv_alternative_fix_jal(void *ptr, u32 jal_insn, int patch_offset)\n \ts32 imm;\n \n \t/* get and adjust new target address */\n-\timm = riscv_insn_extract_jtype_imm(jal_insn);\n+\timm = riscv_insn_jal_extract_imm(jal_insn);\n \timm -= patch_offset;\n \n \t/* update instruction */\n-\triscv_insn_insert_jtype_imm(\u0026jal_insn, imm);\n+\triscv_insn_jal_insert_imm(\u0026jal_insn, imm);\n \n \t/* patch the call place again */\n \tpatch_text_nosync(ptr, \u0026jal_insn, sizeof(u32));\n@@ -127,7 +138,7 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len,\n \t\t\t\tcontinue;\n \n \t\t\t/* if instruction pair is a call, it will use the ra register */\n-\t\t\tif (RV_EXTRACT_RD_REG(insn) != 1)\n+\t\t\tif (riscv_insn_jalr_extract_xd(insn) != 1)\n \t\t\t\tcontinue;\n \n \t\t\triscv_alternative_fix_auipc_jalr(alt_ptr + i * sizeof(u32),\n@@ -136,7 +147,7 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len,\n \t\t}\n \n \t\tif (riscv_insn_is_jal(insn)) {\n-\t\t\ts32 imm = riscv_insn_extract_jtype_imm(insn);\n+\t\t\ts32 imm = riscv_insn_jal_extract_imm(insn);\n \n \t\t\t/* Don't modify jumps inside the alternative block */\n \t\t\tif ((alt_ptr + i * sizeof(u32) + imm) \u003e= alt_ptr \u0026\u0026\ndiff --git a/arch/riscv/kernel/cfi.c b/arch/riscv/kernel/cfi.c\nindex 6ec9dbd7292eec..e38d5f863747af 100644\n--- a/arch/riscv/kernel/cfi.c\n+++ b/arch/riscv/kernel/cfi.c\n@@ -40,16 +40,16 @@ static bool decode_cfi_insn(struct pt_regs *regs, unsigned long *target,\n \tif (!riscv_insn_is_beq(insn))\n \t\treturn false;\n \n-\t*type = (u32)regs_ptr[RV_EXTRACT_RS1_REG(insn)];\n+\t*type = (u32)regs_ptr[riscv_insn_beq_extract_xs1(insn)];\n \n \tif (get_kernel_nofault(insn, (void *)regs-\u003eepc) ||\n \t get_kernel_nofault(insn, (void *)regs-\u003eepc + GET_INSN_LENGTH(insn)))\n \t\treturn false;\n \n \tif (riscv_insn_is_jalr(insn))\n-\t\trs1_num = RV_EXTRACT_RS1_REG(insn);\n+\t\trs1_num = riscv_insn_jalr_extract_xs1(insn);\n \telse if (riscv_insn_is_c_jalr(insn))\n-\t\trs1_num = RVC_EXTRACT_C2_RS1_REG(insn);\n+\t\trs1_num = riscv_insn_c_jalr_extract_xs1(insn);\n \telse\n \t\treturn false;\n \ndiff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c\nindex 0bf629204c76a4..fcf7cda3cc33fb 100644\n--- a/arch/riscv/kernel/kgdb.c\n+++ b/arch/riscv/kernel/kgdb.c\n@@ -23,97 +23,73 @@ enum {\n static unsigned long stepped_address;\n static unsigned int stepped_opcode;\n \n-static int decode_register_index(unsigned long opcode, int offset)\n-{\n-\treturn (opcode \u003e\u003e offset) \u0026 0x1F;\n-}\n-\n-static int decode_register_index_short(unsigned long opcode, int offset)\n-{\n-\treturn ((opcode \u003e\u003e offset) \u0026 0x7) + 8;\n-}\n-\n-/* Calculate the new address for after a step */\n static int get_step_address(struct pt_regs *regs, unsigned long *next_addr)\n {\n \tunsigned long pc = regs-\u003eepc;\n \tunsigned long *regs_ptr = (unsigned long *)regs;\n-\tunsigned int rs1_num, rs2_num;\n+\tunsigned int rs1_num;\n \tint op_code;\n \n \tif (get_kernel_nofault(op_code, (void *)pc))\n \t\treturn -EINVAL;\n+\n \tif ((op_code \u0026 __INSN_LENGTH_MASK) != __INSN_LENGTH_GE_32) {\n-\t\tif (riscv_insn_is_c_jalr(op_code) ||\n-\t\t riscv_insn_is_c_jr(op_code)) {\n-\t\t\trs1_num = decode_register_index(op_code, RVC_C2_RS1_OPOFF);\n-\t\t\t*next_addr = regs_ptr[rs1_num];\n-\t\t} else if (riscv_insn_is_c_j(op_code) ||\n-\t\t\t riscv_insn_is_c_jal(op_code)) {\n-\t\t\t*next_addr = RVC_EXTRACT_JTYPE_IMM(op_code) + pc;\n+\t\tif (riscv_insn_is_c_jalr(op_code)) {\n+\t\t\t*next_addr = regs_ptr[riscv_insn_c_jalr_extract_xs1(op_code)];\n+\t\t} else if (riscv_insn_is_c_jr(op_code)) {\n+\t\t\t*next_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(op_code)];\n+\t\t} else if (riscv_insn_is_c_j(op_code)) {\n+\t\t\t*next_addr = riscv_insn_c_j_extract_imm(op_code) + pc;\n+\t\t} else if (riscv_insn_is_c_jal(op_code)) {\n+\t\t\t*next_addr = riscv_insn_c_jal_extract_imm(op_code) + pc;\n \t\t} else if (riscv_insn_is_c_beqz(op_code)) {\n-\t\t\trs1_num = decode_register_index_short(op_code,\n-\t\t\t\t\t\t\t RVC_C1_RS1_OPOFF);\n-\t\t\tif (!rs1_num || regs_ptr[rs1_num] == 0)\n-\t\t\t\t*next_addr = RVC_EXTRACT_BTYPE_IMM(op_code) + pc;\n+\t\t\trs1_num = riscv_insn_c_beqz_extract_xs1(op_code);\n+\t\t\tif (regs_ptr[8 + rs1_num] == 0)\n+\t\t\t\t*next_addr = riscv_insn_c_beqz_extract_imm(op_code) + pc;\n \t\t\telse\n \t\t\t\t*next_addr = pc + 2;\n \t\t} else if (riscv_insn_is_c_bnez(op_code)) {\n-\t\t\trs1_num =\n-\t\t\t decode_register_index_short(op_code, RVC_C1_RS1_OPOFF);\n-\t\t\tif (rs1_num \u0026\u0026 regs_ptr[rs1_num] != 0)\n-\t\t\t\t*next_addr = RVC_EXTRACT_BTYPE_IMM(op_code) + pc;\n+\t\t\trs1_num = riscv_insn_c_bnez_extract_xs1(op_code);\n+\t\t\tif (regs_ptr[8 + rs1_num] != 0)\n+\t\t\t\t*next_addr = riscv_insn_c_bnez_extract_imm(op_code) + pc;\n \t\t\telse\n \t\t\t\t*next_addr = pc + 2;\n \t\t} else {\n \t\t\t*next_addr = pc + 2;\n \t\t}\n \t} else {\n-\t\tif ((op_code \u0026 __INSN_OPCODE_MASK) == __INSN_BRANCH_OPCODE) {\n-\t\t\tbool result = false;\n-\t\t\tlong imm = RV_EXTRACT_BTYPE_IMM(op_code);\n-\t\t\tunsigned long rs1_val = 0, rs2_val = 0;\n-\n-\t\t\trs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);\n-\t\t\trs2_num = decode_register_index(op_code, RVG_RS2_OPOFF);\n-\t\t\tif (rs1_num)\n-\t\t\t\trs1_val = regs_ptr[rs1_num];\n-\t\t\tif (rs2_num)\n-\t\t\t\trs2_val = regs_ptr[rs2_num];\n-\n-\t\t\tif (riscv_insn_is_beq(op_code))\n-\t\t\t\tresult = (rs1_val == rs2_val) ? true : false;\n-\t\t\telse if (riscv_insn_is_bne(op_code))\n-\t\t\t\tresult = (rs1_val != rs2_val) ? true : false;\n-\t\t\telse if (riscv_insn_is_blt(op_code))\n-\t\t\t\tresult =\n-\t\t\t\t ((long)rs1_val \u003c\n-\t\t\t\t (long)rs2_val) ? true : false;\n-\t\t\telse if (riscv_insn_is_bge(op_code))\n-\t\t\t\tresult =\n-\t\t\t\t ((long)rs1_val \u003e=\n-\t\t\t\t (long)rs2_val) ? true : false;\n-\t\t\telse if (riscv_insn_is_bltu(op_code))\n-\t\t\t\tresult = (rs1_val \u003c rs2_val) ? true : false;\n-\t\t\telse if (riscv_insn_is_bgeu(op_code))\n-\t\t\t\tresult = (rs1_val \u003e= rs2_val) ? true : false;\n-\t\t\tif (result)\n-\t\t\t\t*next_addr = imm + pc;\n-\t\t\telse\n-\t\t\t\t*next_addr = pc + 4;\n+\t\tif (riscv_insn_is_beq(op_code)) {\n+\t\t\t*next_addr = riscv_insn_branch(beq, regs_ptr, op_code,\n+\t\t\t\t\t\t pc, ==, unsigned long);\n+\t\t} else if (riscv_insn_is_bne(op_code)) {\n+\t\t\t*next_addr = riscv_insn_branch(bne, regs_ptr, op_code,\n+\t\t\t\t\t\t pc, !=, unsigned long);\n+\t\t} else if (riscv_insn_is_blt(op_code)) {\n+\t\t\t*next_addr = riscv_insn_branch(blt, regs_ptr, op_code,\n+\t\t\t\t\t\t pc, \u003c, long);\n+\t\t} else if (riscv_insn_is_bge(op_code)) {\n+\t\t\t*next_addr = riscv_insn_branch(bge, regs_ptr, op_code,\n+\t\t\t\t\t\t pc, \u003e=, long);\n+\t\t} else if (riscv_insn_is_bltu(op_code)) {\n+\t\t\t*next_addr = riscv_insn_branch(bltu, regs_ptr, op_code,\n+\t\t\t\t\t\t pc, \u003c, unsigned long);\n+\t\t} else if (riscv_insn_is_bgeu(op_code)) {\n+\t\t\t*next_addr = riscv_insn_branch(bgeu, regs_ptr, op_code,\n+\t\t\t\t\t\t pc, \u003e=, unsigned long);\n \t\t} else if (riscv_insn_is_jal(op_code)) {\n-\t\t\t*next_addr = RV_EXTRACT_JTYPE_IMM(op_code) + pc;\n+\t\t\t*next_addr = riscv_insn_jal_extract_imm(op_code) + pc;\n \t\t} else if (riscv_insn_is_jalr(op_code)) {\n-\t\t\trs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);\n+\t\t\trs1_num = riscv_insn_jalr_extract_xs1(op_code);\n \t\t\tif (rs1_num)\n-\t\t\t\t*next_addr = ((unsigned long *)regs)[rs1_num];\n-\t\t\t*next_addr += RV_EXTRACT_ITYPE_IMM(op_code);\n+\t\t\t\t*next_addr = regs_ptr[rs1_num];\n+\t\t\t*next_addr += riscv_insn_jalr_extract_imm(op_code);\n \t\t} else if (riscv_insn_is_sret(op_code)) {\n \t\t\t*next_addr = pc;\n \t\t} else {\n \t\t\t*next_addr = pc + 4;\n \t\t}\n \t}\n+\n \treturn 0;\n }\n \ndiff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c\nindex 54e2d9552e930d..cad40e4afd8678 100644\n--- a/arch/riscv/kernel/machine_kexec_file.c\n+++ b/arch/riscv/kernel/machine_kexec_file.c\n@@ -116,32 +116,6 @@ static char *setup_kdump_cmdline(struct kimage *image, char *cmdline,\n \t(((x) + (RISCV_IMM_REACH \u003e\u003e 1)) \u0026 ~(RISCV_IMM_REACH - 1))\n #define RISCV_CONST_LOW_PART(x) ((x) - RISCV_CONST_HIGH_PART(x))\n \n-#define ENCODE_ITYPE_IMM(x) \\\n-\t(RV_X(x, 0, 12) \u003c\u003c 20)\n-#define ENCODE_BTYPE_IMM(x) \\\n-\t((RV_X(x, 1, 4) \u003c\u003c 8) | (RV_X(x, 5, 6) \u003c\u003c 25) | \\\n-\t(RV_X(x, 11, 1) \u003c\u003c 7) | (RV_X(x, 12, 1) \u003c\u003c 31))\n-#define ENCODE_UTYPE_IMM(x) \\\n-\t(RV_X(x, 12, 20) \u003c\u003c 12)\n-#define ENCODE_JTYPE_IMM(x) \\\n-\t((RV_X(x, 1, 10) \u003c\u003c 21) | (RV_X(x, 11, 1) \u003c\u003c 20) | \\\n-\t(RV_X(x, 12, 8) \u003c\u003c 12) | (RV_X(x, 20, 1) \u003c\u003c 31))\n-#define ENCODE_CBTYPE_IMM(x) \\\n-\t((RV_X(x, 1, 2) \u003c\u003c 3) | (RV_X(x, 3, 2) \u003c\u003c 10) | (RV_X(x, 5, 1) \u003c\u003c 2) | \\\n-\t(RV_X(x, 6, 2) \u003c\u003c 5) | (RV_X(x, 8, 1) \u003c\u003c 12))\n-#define ENCODE_CJTYPE_IMM(x) \\\n-\t((RV_X(x, 1, 3) \u003c\u003c 3) | (RV_X(x, 4, 1) \u003c\u003c 11) | (RV_X(x, 5, 1) \u003c\u003c 2) | \\\n-\t(RV_X(x, 6, 1) \u003c\u003c 7) | (RV_X(x, 7, 1) \u003c\u003c 6) | (RV_X(x, 8, 2) \u003c\u003c 9) | \\\n-\t(RV_X(x, 10, 1) \u003c\u003c 8) | (RV_X(x, 11, 1) \u003c\u003c 12))\n-#define ENCODE_UJTYPE_IMM(x) \\\n-\t(ENCODE_UTYPE_IMM(RISCV_CONST_HIGH_PART(x)) | \\\n-\t(ENCODE_ITYPE_IMM(RISCV_CONST_LOW_PART(x)) \u003c\u003c 32))\n-#define ENCODE_UITYPE_IMM(x) \\\n-\t(ENCODE_UTYPE_IMM(x) | (ENCODE_ITYPE_IMM(x) \u003c\u003c 32))\n-\n-#define CLEAN_IMM(type, x) \\\n-\t((~ENCODE_##type##_IMM((uint64_t)(-1))) \u0026 (x))\n-\n int arch_kexec_apply_relocations_add(struct purgatory_info *pi,\n \t\t\t\t Elf_Shdr *section,\n \t\t\t\t const Elf_Shdr *relsec,\n@@ -197,12 +171,14 @@ int arch_kexec_apply_relocations_add(struct purgatory_info *pi,\n \n \t\tswitch (r_type) {\n \t\tcase R_RISCV_BRANCH:\n-\t\t\t*(u32 *)loc = CLEAN_IMM(BTYPE, *(u32 *)loc) |\n-\t\t\t\t ENCODE_BTYPE_IMM(val - addr);\n+\t\t\t/*\n+\t\t\t * For simplicity, use beq as represenative of all\n+\t\t\t * branches (they all have the same imm encoding)\n+\t\t\t */\n+\t\t\triscv_insn_beq_insert_imm((u32 *)loc, val - addr);\n \t\t\tbreak;\n \t\tcase R_RISCV_JAL:\n-\t\t\t*(u32 *)loc = CLEAN_IMM(JTYPE, *(u32 *)loc) |\n-\t\t\t\t ENCODE_JTYPE_IMM(val - addr);\n+\t\t\triscv_insn_jal_insert_imm((u32 *)loc, val - addr);\n \t\t\tbreak;\n \t\t/*\n \t\t * With no R_RISCV_PCREL_LO12_S, R_RISCV_PCREL_LO12_I\n@@ -213,16 +189,23 @@ int arch_kexec_apply_relocations_add(struct purgatory_info *pi,\n \t\tcase R_RISCV_PCREL_HI20:\n \t\tcase R_RISCV_CALL_PLT:\n \t\tcase R_RISCV_CALL:\n-\t\t\t*(u64 *)loc = CLEAN_IMM(UITYPE, *(u64 *)loc) |\n-\t\t\t\t ENCODE_UJTYPE_IMM(val - addr);\n+\t\t\triscv_insn_auipc_insert_imm((u32 *)loc, RISCV_CONST_HIGH_PART(val - addr));\n+\t\t\triscv_insn_jalr_insert_imm((u32 *)loc + 1,\n+\t\t\t\t\t\t RISCV_CONST_LOW_PART(val - addr));\n \t\t\tbreak;\n \t\tcase R_RISCV_RVC_BRANCH:\n-\t\t\t*(u32 *)loc = CLEAN_IMM(CBTYPE, *(u32 *)loc) |\n-\t\t\t\t ENCODE_CBTYPE_IMM(val - addr);\n+\t\t\t/*\n+\t\t\t * For simplicity, use c.beqz as represenative of all\n+\t\t\t * compressed branches (they all have the same imm encoding)\n+\t\t\t */\n+\t\t\triscv_insn_c_beqz_insert_imm((u16 *)loc, val - addr);\n \t\t\tbreak;\n \t\tcase R_RISCV_RVC_JUMP:\n-\t\t\t*(u32 *)loc = CLEAN_IMM(CJTYPE, *(u32 *)loc) |\n-\t\t\t\t ENCODE_CJTYPE_IMM(val - addr);\n+\t\t\t/*\n+\t\t\t * For simplicity, use c.j as represenative of all\n+\t\t\t * compressed jumps (they all have the same imm encoding)\n+\t\t\t */\n+\t\t\triscv_insn_c_j_insert_imm((u16 *)loc, val - addr);\n \t\t\tbreak;\n \t\tcase R_RISCV_ADD16:\n \t\t\t*(u16 *)loc += val;\ndiff --git a/arch/riscv/kernel/probes/decode-insn.c b/arch/riscv/kernel/probes/decode-insn.c\nindex 65d9590bfb9ff5..0d70c8301a451f 100644\n--- a/arch/riscv/kernel/probes/decode-insn.c\n+++ b/arch/riscv/kernel/probes/decode-insn.c\n@@ -42,7 +42,12 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)\n \tRISCV_INSN_SET_SIMULATE(jal,\t\tinsn);\n \tRISCV_INSN_SET_SIMULATE(jalr,\t\tinsn);\n \tRISCV_INSN_SET_SIMULATE(auipc,\t\tinsn);\n-\tRISCV_INSN_SET_SIMULATE(branch,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(beq,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(bne,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(blt,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(bge,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(bltu,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(bgeu,\t\tinsn);\n \n \treturn INSN_GOOD;\n }\ndiff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c\nindex fa581590c1f8b2..a443883c323706 100644\n--- a/arch/riscv/kernel/probes/simulate-insn.c\n+++ b/arch/riscv/kernel/probes/simulate-insn.c\n@@ -4,222 +4,152 @@\n #include \u003clinux/kernel.h\u003e\n #include \u003clinux/kprobes.h\u003e\n \n-#include \"decode-insn.h\"\n+#include \u003casm/insn.h\u003e\n #include \"simulate-insn.h\"\n \n-static inline bool rv_insn_reg_get_val(struct pt_regs *regs, u32 index,\n-\t\t\t\t unsigned long *ptr)\n+bool __kprobes simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\tif (index == 0)\n-\t\t*ptr = 0;\n-\telse if (index \u003c= 31)\n-\t\t*ptr = *((unsigned long *)regs + index);\n-\telse\n-\t\treturn false;\n+\ts32 imm = riscv_insn_jal_extract_imm(opcode);\n+\tu32 index = riscv_insn_jal_extract_xd(opcode);\n \n-\treturn true;\n-}\n+\triscv_insn_reg_set_val((unsigned long *)regs, index, addr + 4);\n \n-static inline bool rv_insn_reg_set_val(struct pt_regs *regs, u32 index,\n-\t\t\t\t unsigned long val)\n-{\n-\tif (index == 0)\n-\t\treturn true;\n-\telse if (index \u003c= 31)\n-\t\t*((unsigned long *)regs + index) = val;\n-\telse\n-\t\treturn false;\n+\tinstruction_pointer_set(regs, addr + imm);\n \n \treturn true;\n }\n \n-bool __kprobes simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * 31 30 21 20 19 12 11 7 6 0\n-\t * imm [20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode\n-\t * 1 10 1 8 5 JAL/J\n-\t */\n-\tbool ret;\n-\ts32 imm;\n-\tu32 index = RV_EXTRACT_RD_REG(opcode);\n+\tunsigned long base_addr;\n+\ts32 imm = riscv_insn_jalr_extract_imm(opcode);\n+\tu32 rd_index = riscv_insn_jalr_extract_xd(opcode);\n+\tu32 rs1_index = riscv_insn_jalr_extract_xs1(opcode);\n \n-\tret = rv_insn_reg_set_val(regs, index, addr + 4);\n-\tif (!ret)\n-\t\treturn ret;\n+\tbase_addr = riscv_insn_reg_get_val((unsigned long *)regs, rs1_index);\n \n-\timm = RV_EXTRACT_JTYPE_IMM(opcode);\n+\triscv_insn_reg_set_val((unsigned long *)regs, rd_index, addr + 4);\n \n-\tinstruction_pointer_set(regs, addr + imm);\n+\tinstruction_pointer_set(regs, (base_addr + imm) \u0026 ~1);\n \n-\treturn ret;\n+\treturn true;\n }\n \n-bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * 31 20 19 15 14 12 11 7 6 0\n-\t * offset[11:0] | rs1 | 010 | rd | opcode\n-\t * 12 5 3 5 JALR/JR\n-\t */\n-\tbool ret;\n-\tunsigned long base_addr;\n-\tu32 imm = RV_EXTRACT_ITYPE_IMM(opcode);\n-\tu32 rd_index = RV_EXTRACT_RD_REG(opcode);\n-\tu32 rs1_index = RV_EXTRACT_RS1_REG(opcode);\n+\tu32 rd_index = riscv_insn_auipc_extract_xd(opcode);\n+\tunsigned long rd_val = addr + (s32)riscv_insn_auipc_extract_imm(opcode);\n \n-\tret = rv_insn_reg_get_val(regs, rs1_index, \u0026base_addr);\n-\tif (!ret)\n-\t\treturn ret;\n+\triscv_insn_reg_set_val((unsigned long *)regs, rd_index, rd_val);\n \n-\tret = rv_insn_reg_set_val(regs, rd_index, addr + 4);\n-\tif (!ret)\n-\t\treturn ret;\n-\n-\tinstruction_pointer_set(regs, (base_addr + sign_extend32((imm), 11))\u0026~1);\n+\tinstruction_pointer_set(regs, addr + 4);\n \n-\treturn ret;\n+\treturn true;\n }\n \n-bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+bool __kprobes simulate_beq(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * auipc instruction:\n-\t * 31 12 11 7 6 0\n-\t * | imm[31:12] | rd | opcode |\n-\t * 20 5 7\n-\t */\n+\tunsigned long next_addr;\n \n-\tu32 rd_idx = RV_EXTRACT_RD_REG(opcode);\n-\tunsigned long rd_val = addr + (s32)RV_EXTRACT_UTYPE_IMM(opcode);\n+\tnext_addr = riscv_insn_branch(beq, (unsigned long *)regs, opcode, addr, ==, unsigned long);\n+\tinstruction_pointer_set(regs, next_addr);\n \n-\tif (!rv_insn_reg_set_val(regs, rd_idx, rd_val))\n-\t\treturn false;\n+\treturn true;\n+}\n \n-\tinstruction_pointer_set(regs, addr + 4);\n+bool __kprobes simulate_bne(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+{\n+\tunsigned long next_addr;\n+\n+\tnext_addr = riscv_insn_branch(bne, (unsigned long *)regs, opcode, addr, !=, unsigned long);\n+\tinstruction_pointer_set(regs, next_addr);\n \n \treturn true;\n }\n \n-bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+bool __kprobes simulate_blt(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * branch instructions:\n-\t * 31 30 25 24 20 19 15 14 12 11 8 7 6 0\n-\t * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |\n-\t * 1 6 5 5 3 4 1 7\n-\t * imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 BEQ\n-\t * imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 BNE\n-\t * imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 BLT\n-\t * imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 BGE\n-\t * imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 BLTU\n-\t * imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 BGEU\n-\t */\n-\n-\ts32 offset;\n-\ts32 offset_tmp;\n-\tunsigned long rs1_val;\n-\tunsigned long rs2_val;\n-\n-\tif (!rv_insn_reg_get_val(regs, RV_EXTRACT_RS1_REG(opcode), \u0026rs1_val) ||\n-\t !rv_insn_reg_get_val(regs, RV_EXTRACT_RS2_REG(opcode), \u0026rs2_val))\n-\t\treturn false;\n-\n-\toffset_tmp = RV_EXTRACT_BTYPE_IMM(opcode);\n-\tswitch (RV_EXTRACT_FUNCT3(opcode)) {\n-\tcase RVG_FUNCT3_BEQ:\n-\t\toffset = (rs1_val == rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BNE:\n-\t\toffset = (rs1_val != rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BLT:\n-\t\toffset = ((long)rs1_val \u003c (long)rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BGE:\n-\t\toffset = ((long)rs1_val \u003e= (long)rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BLTU:\n-\t\toffset = (rs1_val \u003c rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BGEU:\n-\t\toffset = (rs1_val \u003e= rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn false;\n-\t}\n+\tunsigned long next_addr;\n \n-\tinstruction_pointer_set(regs, addr + offset);\n+\tnext_addr = riscv_insn_branch(blt, (unsigned long *)regs, opcode, addr, \u003c, long);\n+\tinstruction_pointer_set(regs, next_addr);\n \n \treturn true;\n }\n \n-bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+bool __kprobes simulate_bge(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\ts32 offset = RVC_EXTRACT_JTYPE_IMM(opcode);\n+\tunsigned long next_addr;\n \n-\tinstruction_pointer_set(regs, addr + offset);\n+\tnext_addr = riscv_insn_branch(bge, (unsigned long *)regs, opcode, addr, \u003e=, long);\n+\tinstruction_pointer_set(regs, next_addr);\n \n \treturn true;\n }\n \n-static bool __kprobes simulate_c_jr_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs,\n-\t\t\t\t\t bool is_jalr)\n+bool __kprobes simulate_bltu(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * 15 12 11 7 6 2 1 0\n-\t * | funct4 | rs1 | rs2 | op |\n-\t * 4 5 5 2\n-\t */\n+\tunsigned long next_addr;\n+\n+\tnext_addr = riscv_insn_branch(bltu, (unsigned long *)regs, opcode, addr, \u003c, unsigned long);\n+\tinstruction_pointer_set(regs, next_addr);\n \n-\tunsigned long jump_addr;\n+\treturn true;\n+}\n \n-\tu32 rs1 = RVC_EXTRACT_C2_RS1_REG(opcode);\n+bool __kprobes simulate_bgeu(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+{\n+\tunsigned long next_addr;\n \n-\tif (rs1 == 0) /* C.JR is only valid when rs1 != x0 */\n-\t\treturn false;\n+\tnext_addr = riscv_insn_branch(bgeu, (unsigned long *)regs, opcode, addr, \u003e=, unsigned long);\n+\tinstruction_pointer_set(regs, next_addr);\n \n-\tif (!rv_insn_reg_get_val(regs, rs1, \u0026jump_addr))\n-\t\treturn false;\n+\treturn true;\n+}\n \n-\tif (is_jalr \u0026\u0026 !rv_insn_reg_set_val(regs, 1, addr + 2))\n-\t\treturn false;\n+bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+{\n+\ts32 offset = riscv_insn_c_j_extract_imm(opcode);\n \n-\tinstruction_pointer_set(regs, jump_addr);\n+\tinstruction_pointer_set(regs, addr + offset);\n \n \treturn true;\n }\n \n bool __kprobes simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\treturn simulate_c_jr_jalr(opcode, addr, regs, false);\n+\tunsigned long next_addr;\n+\tunsigned long *regs_ptr = (unsigned long *)regs;\n+\n+\t/* xs1 == 0 is invalid so riscv_insn_reg_get_val() isn't needed */\n+\tnext_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(opcode)];\n+\tinstruction_pointer_set(regs, next_addr);\n+\n+\treturn true;\n }\n \n bool __kprobes simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\treturn simulate_c_jr_jalr(opcode, addr, regs, true);\n+\tunsigned long next_addr;\n+\tunsigned long *regs_ptr = (unsigned long *)regs;\n+\n+\t/* xs1 == 0 is invalid so riscv_insn_reg_get_val() isn't needed */\n+\tnext_addr = regs_ptr[riscv_insn_c_jalr_extract_xs1(opcode)];\n+\tinstruction_pointer_set(regs, next_addr);\n+\n+\tregs-\u003era = addr + 2;\n+\treturn true;\n }\n \n-static bool __kprobes simulate_c_bnez_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs,\n-\t\t\t\t\t bool is_bnez)\n+bool __kprobes simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * 15 13 12 10 9 7 6 2 1 0\n-\t * | funct3 | offset[8|4:3] | rs1' | offset[7:6|2:1|5] | op |\n-\t * 3 3 3 5 2\n-\t */\n-\n-\ts32 offset;\n \tu32 rs1;\n-\tunsigned long rs1_val;\n+\tunsigned long offset;\n+\tunsigned long *regs_ptr = (unsigned long *)regs;\n \n-\trs1 = 0x8 | ((opcode \u003e\u003e 7) \u0026 0x7);\n-\n-\tif (!rv_insn_reg_get_val(regs, rs1, \u0026rs1_val))\n-\t\treturn false;\n-\n-\tif ((rs1_val != 0 \u0026\u0026 is_bnez) || (rs1_val == 0 \u0026\u0026 !is_bnez))\n-\t\toffset = RVC_EXTRACT_BTYPE_IMM(opcode);\n+\trs1 = riscv_insn_c_bnez_extract_xs1(opcode);\n+\tif (regs_ptr[8 + rs1] != 0)\n+\t\toffset = riscv_insn_c_bnez_extract_imm(opcode);\n \telse\n \t\toffset = 2;\n \n@@ -228,12 +158,19 @@ static bool __kprobes simulate_c_bnez_beqz(u32 opcode, unsigned long addr, struc\n \treturn true;\n }\n \n-bool __kprobes simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs)\n-{\n-\treturn simulate_c_bnez_beqz(opcode, addr, regs, true);\n-}\n-\n bool __kprobes simulate_c_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\treturn simulate_c_bnez_beqz(opcode, addr, regs, false);\n+\tu32 rs1;\n+\tunsigned long offset;\n+\tunsigned long *regs_ptr = (unsigned long *)regs;\n+\n+\trs1 = riscv_insn_c_beqz_extract_xs1(opcode);\n+\tif (regs_ptr[8 + rs1] == 0)\n+\t\toffset = riscv_insn_c_beqz_extract_imm(opcode);\n+\telse\n+\t\toffset = 2;\n+\n+\tinstruction_pointer_set(regs, addr + offset);\n+\n+\treturn true;\n }\ndiff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h\nindex 44ebbc444db9da..f2f707e92dee3e 100644\n--- a/arch/riscv/kernel/probes/simulate-insn.h\n+++ b/arch/riscv/kernel/probes/simulate-insn.h\n@@ -21,7 +21,12 @@\n \t} while (0)\n \n bool simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs);\n-bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_beq(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_bne(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_blt(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_bge(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_bltu(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_bgeu(u32 opcode, unsigned long addr, struct pt_regs *regs);\n bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);\n bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);\n bool simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs);\ndiff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/tests/Kconfig.debug\nindex 40f8dafffa0ab6..9eda8938ec15b1 100644\n--- a/arch/riscv/kernel/tests/Kconfig.debug\n+++ b/arch/riscv/kernel/tests/Kconfig.debug\n@@ -42,6 +42,19 @@ config RISCV_KPROBES_KUNIT\n \n If unsure, say N.\n \n+config RISCV_KPROBES_SIMULATE_KUNIT\n+ tristate \"KUnit test for riscv kprobes instruction simulation\" if !KUNIT_ALL_TESTS\n+ depends on KUNIT\n+ depends on KPROBES\n+ default KUNIT_ALL_TESTS\n+ help\n+ Enable testing for riscv kprobes instruction simulation. Useful for\n+ riscv and/or kprobes development. The test verifies that kprobes\n+ instruction simulation properly simulates the instructions. These tests\n+ are very slow.\n+\n+ If unsure, say N.\n+\n endif # RUNTIME_TESTING_MENU\n \n endmenu # \"arch/riscv/kernel runtime Testing\"\ndiff --git a/arch/riscv/kernel/tests/kprobes/Makefile b/arch/riscv/kernel/tests/kprobes/Makefile\nindex df7256f62313e2..34db6044e87f48 100644\n--- a/arch/riscv/kernel/tests/kprobes/Makefile\n+++ b/arch/riscv/kernel/tests/kprobes/Makefile\n@@ -1,3 +1,5 @@\n obj-$(CONFIG_RISCV_KPROBES_KUNIT) += kprobes_riscv_kunit.o\n+obj-$(CONFIG_RISCV_KPROBES_SIMULATE_KUNIT) += kprobes_simulate_riscv_kunit.o\n \n kprobes_riscv_kunit-objs := test-kprobes.o test-kprobes-asm.o\n+kprobes_simulate_riscv_kunit-objs := test-kprobes-simulate.o\ndiff --git a/arch/riscv/kernel/tests/kprobes/test-kprobes-simulate.c b/arch/riscv/kernel/tests/kprobes/test-kprobes-simulate.c\nnew file mode 100644\nindex 00000000000000..d82706685823d2\n--- /dev/null\n+++ b/arch/riscv/kernel/tests/kprobes/test-kprobes-simulate.c\n@@ -0,0 +1,250 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+\n+#include \u003clinux/kernel.h\u003e\n+#include \u003clinux/kprobes.h\u003e\n+#include \u003ckunit/test.h\u003e\n+\n+#include \"../../probes/simulate-insn.h\"\n+\n+#include \u003casm/insn.h\u003e\n+#include \u003casm/text-patching.h\u003e\n+\n+static void test_kprobe_simulate_riscv(struct kunit *test)\n+{\n+\tunsigned int addr = 0xdeadbeef;\n+\tunsigned int i = 0;\n+\n+\tdo {\n+\t\tstruct pt_regs regs = { 0 };\n+\n+\t\tif (riscv_insn_is_jal(i)) {\n+\t\t\ts32 offset = riscv_insn_jal_extract_imm(i);\n+\t\t\tu32 xd_index = riscv_insn_jal_extract_xd(i);\n+\n+\t\t\tsimulate_jal(i, addr, \u0026regs);\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t \"jal instruction (0x%x) incorrectly simulated\", i);\n+\n+\t\t\tif (xd_index)\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(\n+\t\t\t\t\ttest,\n+\t\t\t\t\triscv_insn_reg_get_val((unsigned long *)\u0026regs, xd_index),\n+\t\t\t\t\taddr + 4, \"jal instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\ti);\n+\t\t}\n+\t\tif (riscv_insn_is_jalr(i)) {\n+\t\t\tunsigned long reg_addr = 0xffff;\n+\t\t\ts32 offset = riscv_insn_jalr_extract_imm(i);\n+\t\t\tu32 rd_index = riscv_insn_jalr_extract_xd(i);\n+\t\t\tu32 rs1_index = riscv_insn_jalr_extract_xs1(i);\n+\n+\t\t\tif (rs1_index)\n+\t\t\t\triscv_insn_reg_set_val((unsigned long *)\u0026regs, rs1_index, reg_addr);\n+\t\t\telse\n+\t\t\t\treg_addr = 0;\n+\n+\t\t\tsimulate_jalr(i, addr, \u0026regs);\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, (reg_addr + offset) \u0026 ~1,\n+\t\t\t\t\t \"jalr instruction (0x%x) incorrectly simulated\", i);\n+\n+\t\t\tif (rd_index)\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(\n+\t\t\t\t\ttest,\n+\t\t\t\t\triscv_insn_reg_get_val((unsigned long *)\u0026regs, rd_index),\n+\t\t\t\t\taddr + 4, \"jalr instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\ti);\n+\t\t} else if (riscv_insn_is_auipc(i)) {\n+\t\t\ts32 offset = riscv_insn_auipc_extract_imm(i);\n+\t\t\tu32 rd_index = riscv_insn_auipc_extract_xd(i);\n+\n+\t\t\tsimulate_auipc(i, addr, \u0026regs);\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,\n+\t\t\t\t\t \"auipc instruction (0x%x) incorrectly simulated\", i);\n+\n+\t\t\tif (rd_index)\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(\n+\t\t\t\t\ttest,\n+\t\t\t\t\triscv_insn_reg_get_val((unsigned long *)\u0026regs, rd_index),\n+\t\t\t\t\t(unsigned long)addr + offset,\n+\t\t\t\t\t\"auipc instruction (0x%x) incorrectly simulated\", i);\n+\t\t} else if (riscv_insn_is_beq(i)) {\n+\t\t\ts32 offset = riscv_insn_beq_extract_imm(i);\n+\t\t\tu32 rs1_index = riscv_insn_beq_extract_xs1(i);\n+\t\t\tu32 rs2_index = riscv_insn_beq_extract_xs2(i);\n+\n+\t\t\tsimulate_beq(i, addr, \u0026regs);\n+\n+\t\t\tif (riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs1_index) ==\n+\t\t\t riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs2_index)) {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t\t \"beq instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t} else {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,\n+\t\t\t\t\t\t \"beq instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t}\n+\t\t} else if (riscv_insn_is_bne(i)) {\n+\t\t\ts32 offset = riscv_insn_bne_extract_imm(i);\n+\t\t\tu32 rs1_index = riscv_insn_bne_extract_xs1(i);\n+\t\t\tu32 rs2_index = riscv_insn_bne_extract_xs2(i);\n+\n+\t\t\tsimulate_bne(i, addr, \u0026regs);\n+\n+\t\t\tif (riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs1_index) !=\n+\t\t\t riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs2_index)) {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t\t \"bne instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t} else {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,\n+\t\t\t\t\t\t \"bne instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t}\n+\t\t} else if (riscv_insn_is_blt(i)) {\n+\t\t\ts32 offset = riscv_insn_blt_extract_imm(i);\n+\t\t\tu32 rs1_index = riscv_insn_blt_extract_xs1(i);\n+\t\t\tu32 rs2_index = riscv_insn_blt_extract_xs2(i);\n+\n+\t\t\tsimulate_blt(i, addr, \u0026regs);\n+\n+\t\t\tif ((long)riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs1_index) \u003c\n+\t\t\t (long)riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs2_index)) {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t\t \"blt instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t} else {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,\n+\t\t\t\t\t\t \"blt instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t}\n+\t\t} else if (riscv_insn_is_bge(i)) {\n+\t\t\ts32 offset = riscv_insn_bge_extract_imm(i);\n+\t\t\tu32 rs1_index = riscv_insn_bge_extract_xs1(i);\n+\t\t\tu32 rs2_index = riscv_insn_bge_extract_xs2(i);\n+\n+\t\t\tsimulate_bge(i, addr, \u0026regs);\n+\n+\t\t\tif ((long)riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs1_index) \u003e=\n+\t\t\t (long)riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs2_index)) {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t\t \"bge instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t} else {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,\n+\t\t\t\t\t\t \"bge instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t}\n+\t\t} else if (riscv_insn_is_bltu(i)) {\n+\t\t\ts32 offset = riscv_insn_bltu_extract_imm(i);\n+\t\t\tu32 rs1_index = riscv_insn_bltu_extract_xs1(i);\n+\t\t\tu32 rs2_index = riscv_insn_bltu_extract_xs2(i);\n+\n+\t\t\tsimulate_bltu(i, addr, \u0026regs);\n+\n+\t\t\tif (riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs1_index) \u003c\n+\t\t\t riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs2_index)) {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t\t \"bltu instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t} else {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,\n+\t\t\t\t\t\t \"bltu instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t}\n+\t\t} else if (riscv_insn_is_bgeu(i)) {\n+\t\t\ts32 offset = riscv_insn_bgeu_extract_imm(i);\n+\t\t\tu32 rs1_index = riscv_insn_bgeu_extract_xs1(i);\n+\t\t\tu32 rs2_index = riscv_insn_bgeu_extract_xs2(i);\n+\n+\t\t\tsimulate_bgeu(i, addr, \u0026regs);\n+\n+\t\t\tif (riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs1_index) \u003e=\n+\t\t\t riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs2_index)) {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t\t \"bgeu instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t} else {\n+\t\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,\n+\t\t\t\t\t\t \"bgeu instruction (0x%x) incorrectly simulated\",\n+\t\t\t\t\t\t i);\n+\t\t\t}\n+\t\t} else if (riscv_insn_is_c_j(i)) {\n+\t\t\ts32 offset = riscv_insn_c_j_extract_imm(i);\n+\n+\t\t\tsimulate_c_j(i, addr, \u0026regs);\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t \"c.j instruction (0x%x) incorrectly simulated\", i);\n+\t\t} else if (riscv_insn_is_c_jr(i)) {\n+\t\t\tu32 rs1_index = riscv_insn_c_jr_extract_xs1(i);\n+\n+\t\t\tsimulate_c_jr(i, addr, \u0026regs);\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc,\n+\t\t\t\t\t riscv_insn_reg_get_val((unsigned long *)\u0026regs,\n+\t\t\t\t\t\t\t\t rs1_index),\n+\t\t\t\t\t \"c.jr instruction (0x%x) incorrectly simulated\", i);\n+\t\t} else if (riscv_insn_is_c_jalr(i)) {\n+\t\t\tunsigned long reg_addr = 0xffff;\n+\t\t\tu32 rs1_index = riscv_insn_c_jalr_extract_xs1(i);\n+\n+\t\t\tif (rs1_index)\n+\t\t\t\triscv_insn_reg_set_val((unsigned long *)\u0026regs, rs1_index, reg_addr);\n+\t\t\telse\n+\t\t\t\treg_addr = 0;\n+\n+\t\t\tsimulate_c_jalr(i, addr, \u0026regs);\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, reg_addr,\n+\t\t\t\t\t \"c.jalr instruction (0x%x) incorrectly simulated\", i);\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.ra, addr + 2,\n+\t\t\t\t\t \"c.jalr instruction (0x%x) incorrectly simulated\", i);\n+\t\t} else if (riscv_insn_is_c_bnez(i)) {\n+\t\t\tu32 offset;\n+\t\t\tu32 rs1_index = riscv_insn_c_bnez_extract_xs1(i);\n+\n+\t\t\tsimulate_c_bnez(i, addr, \u0026regs);\n+\n+\t\t\tif (riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs1_index + 8) != 0)\n+\t\t\t\toffset = riscv_insn_c_bnez_extract_imm(i);\n+\t\t\telse\n+\t\t\t\toffset = 2;\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t \"c.bnez instruction (0x%x) incorrectly simulated\", i);\n+\t\t} else if (riscv_insn_is_c_beqz(i)) {\n+\t\t\tu32 offset;\n+\t\t\tu32 rs1_index = riscv_insn_c_beqz_extract_xs1(i);\n+\n+\t\t\tsimulate_c_beqz(i, addr, \u0026regs);\n+\n+\t\t\tif (riscv_insn_reg_get_val((unsigned long *)\u0026regs, rs1_index + 8) == 0)\n+\t\t\t\toffset = riscv_insn_c_beqz_extract_imm(i);\n+\t\t\telse\n+\t\t\t\toffset = 2;\n+\n+\t\t\tKUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,\n+\t\t\t\t\t \"c.beqz instruction (0x%x) incorrectly simulated\", i);\n+\t\t}\n+\t} while (++i \u003e 0);\n+}\n+\n+static struct kunit_case kprobes_simulate_testcases[] = {\n+\tKUNIT_CASE_SLOW(test_kprobe_simulate_riscv),\n+\t{}\n+};\n+\n+static struct kunit_suite kprobes_simulate_test_suite = {\n+\t.name = \"kprobes_simulate_riscv\",\n+\t.test_cases = kprobes_simulate_testcases,\n+};\n+\n+kunit_test_suites(\u0026kprobes_simulate_test_suite);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"KUnit test for riscv kprobes instruction simulatation\");\ndiff --git a/arch/riscv/kernel/tests/kprobes/test-kprobes.h b/arch/riscv/kernel/tests/kprobes/test-kprobes.h\nindex 537f44aa9d3f00..7a672de8f130f6 100644\n--- a/arch/riscv/kernel/tests/kprobes/test-kprobes.h\n+++ b/arch/riscv/kernel/tests/kprobes/test-kprobes.h\n@@ -19,6 +19,12 @@ extern void *test_kprobes_addresses[];\n /* array of functions that return KPROBE_TEST_MAGIC */\n extern long (*test_kprobes_functions[])(void);\n \n+void test_kprobes_arbitrary(void);\n+\n+extern unsigned int *test_kprobes_arbitrary_addr;\n+\n+extern unsigned int *test_kprobes_c_bnez_addr1;\n+\n #endif /* __ASSEMBLER__ */\n \n #endif /* TEST_KPROBES_H */\ndiff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c\nindex 81b7682e6c6dbc..4d2a2432e0c45f 100644\n--- a/arch/riscv/kernel/traps_misaligned.c\n+++ b/arch/riscv/kernel/traps_misaligned.c\n@@ -22,15 +22,11 @@\n \n #ifdef CONFIG_FPU\n \n-#define FP_GET_RD(insn)\t\t(insn \u003e\u003e 7 \u0026 0x1F)\n-\n extern void put_f32_reg(unsigned long fp_reg, unsigned long value);\n \n-static int set_f32_rd(unsigned long insn, struct pt_regs *regs,\n+static int set_f32_rd(unsigned long fp_reg, struct pt_regs *regs,\n \t\t unsigned long val)\n {\n-\tunsigned long fp_reg = FP_GET_RD(insn);\n-\n \tput_f32_reg(fp_reg, val);\n \tregs-\u003estatus |= SR_FS_DIRTY;\n \n@@ -39,9 +35,8 @@ static int set_f32_rd(unsigned long insn, struct pt_regs *regs,\n \n extern void put_f64_reg(unsigned long fp_reg, unsigned long value);\n \n-static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val)\n+static int set_f64_rd(unsigned long fp_reg, struct pt_regs *regs, u64 val)\n {\n-\tunsigned long fp_reg = FP_GET_RD(insn);\n \tunsigned long value;\n \n #if __riscv_xlen == 32\n@@ -58,10 +53,8 @@ static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val)\n #if __riscv_xlen == 32\n extern void get_f64_reg(unsigned long fp_reg, u64 *value);\n \n-static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t struct pt_regs *regs)\n+static u64 get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n-\tunsigned long fp_reg = (insn \u003e\u003e fp_reg_offset) \u0026 0x1F;\n \tu64 val;\n \n \tget_f64_reg(fp_reg, \u0026val);\n@@ -73,10 +66,8 @@ static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n \n extern unsigned long get_f64_reg(unsigned long fp_reg);\n \n-static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t\t\tstruct pt_regs *regs)\n+static unsigned long get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n-\tunsigned long fp_reg = (insn \u003e\u003e fp_reg_offset) \u0026 0x1F;\n \tunsigned long val;\n \n \tval = get_f64_reg(fp_reg);\n@@ -89,10 +80,8 @@ static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n \n extern unsigned long get_f32_reg(unsigned long fp_reg);\n \n-static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t\t\tstruct pt_regs *regs)\n+static unsigned long get_f32_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n-\tunsigned long fp_reg = (insn \u003e\u003e fp_reg_offset) \u0026 0x1F;\n \tunsigned long val;\n \n \tval = get_f32_reg(fp_reg);\n@@ -107,28 +96,18 @@ static void set_f32_rd(unsigned long insn, struct pt_regs *regs,\n \n static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) {}\n \n-static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t\t\tstruct pt_regs *regs)\n+static unsigned long get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n \treturn 0;\n }\n \n-static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t\t\tstruct pt_regs *regs)\n+static unsigned long get_f32_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n \treturn 0;\n }\n \n #endif\n \n-#define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs))\n-#define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs))\n-#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs))\n-\n-#define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs))\n-#define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs))\n-#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs))\n-\n #define __read_insn(regs, insn, insn_addr, type)\t\\\n ({\t\t\t\t\t\t\t\\\n \tint __ret;\t\t\t\t\t\\\n@@ -217,13 +196,13 @@ static int handle_vector_misaligned_load(struct pt_regs *regs)\n }\n #endif\n \n-static int handle_scalar_misaligned_load(struct pt_regs *regs)\n+static noinline int handle_scalar_misaligned_load(struct pt_regs *regs)\n {\n \tunion reg_data val;\n \tunsigned long epc = regs-\u003eepc;\n \tunsigned long insn;\n \tunsigned long addr = regs-\u003ebadaddr;\n-\tint fp = 0, shift = 0, len = 0;\n+\tint fp = 0, shift = 0, len = 0, rd = 0;\n \n \tperf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);\n \n@@ -240,68 +219,71 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)\n \n \tregs-\u003eepc = 0;\n \n-\tif ((insn \u0026 INSN_MASK_LW) == INSN_MATCH_LW) {\n+\tif (riscv_insn_is_lw(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-#if defined(CONFIG_64BIT)\n-\t} else if ((insn \u0026 INSN_MASK_LD) == INSN_MATCH_LD) {\n+\t\trd = riscv_insn_lw_extract_xd(insn);\n+\t} else if (riscv_insn_is_ld(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t} else if ((insn \u0026 INSN_MASK_LWU) == INSN_MATCH_LWU) {\n+\t\trd = riscv_insn_ld_extract_xd(insn);\n+\t} else if (riscv_insn_is_lwu(insn)) {\n \t\tlen = 4;\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_FLD) == INSN_MATCH_FLD) {\n+\t\trd = riscv_insn_lwu_extract_xd(insn);\n+\t} else if (riscv_insn_is_fld(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t} else if ((insn \u0026 INSN_MASK_FLW) == INSN_MATCH_FLW) {\n+\t\trd = riscv_insn_fld_extract_fd(insn);\n+\t} else if (riscv_insn_is_flw(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t} else if ((insn \u0026 INSN_MASK_LH) == INSN_MATCH_LH) {\n+\t\trd = riscv_insn_flw_extract_fd(insn);\n+\t} else if (riscv_insn_is_lh(insn)) {\n \t\tlen = 2;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t} else if ((insn \u0026 INSN_MASK_LHU) == INSN_MATCH_LHU) {\n+\t\trd = riscv_insn_lh_extract_xd(insn);\n+\t} else if (riscv_insn_is_lhu(insn)) {\n \t\tlen = 2;\n-#if defined(CONFIG_64BIT)\n-\t} else if ((insn \u0026 INSN_MASK_C_LD) == INSN_MATCH_C_LD) {\n+\t\trd = riscv_insn_lhu_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_ld(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t\tinsn = RVC_RS2S(insn) \u003c\u003c SH_RD;\n-\t} else if ((insn \u0026 INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP \u0026\u0026\n-\t\t ((insn \u003e\u003e SH_RD) \u0026 0x1f)) {\n+\t\trd = (8 + riscv_insn_c_ld_extract_xd(insn));\n+\t} else if (riscv_insn_is_c_ldsp(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_C_LW) == INSN_MATCH_C_LW) {\n+\t\trd = riscv_insn_c_ldsp_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_lw(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t\tinsn = RVC_RS2S(insn) \u003c\u003c SH_RD;\n-\t} else if ((insn \u0026 INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP \u0026\u0026\n-\t\t ((insn \u003e\u003e SH_RD) \u0026 0x1f)) {\n+\t\trd = (8 + riscv_insn_c_lw_extract_xd(insn));\n+\t} else if (riscv_insn_is_c_lwsp(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t} else if ((insn \u0026 INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) {\n+\t\trd = riscv_insn_c_lwsp_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_fld(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t\tinsn = RVC_RS2S(insn) \u003c\u003c SH_RD;\n-\t} else if ((insn \u0026 INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) {\n+\t\trd = (8 + riscv_insn_c_fld_extract_fd(insn));\n+\t} else if (riscv_insn_is_c_fldsp(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-#if defined(CONFIG_32BIT)\n-\t} else if ((insn \u0026 INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) {\n+\t\trd = riscv_insn_c_fldsp_extract_fd(insn);\n+\t} else if (riscv_insn_is_c_flw(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t\tinsn = RVC_RS2S(insn) \u003c\u003c SH_RD;\n-\t} else if ((insn \u0026 INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) {\n+\t\trd = (8 + riscv_insn_c_flw_extract_fd(insn));\n+\t} else if (riscv_insn_is_c_flwsp(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_C_LHU) == INSN_MATCH_C_LHU) {\n+\t\trd = riscv_insn_c_flwsp_extract_fd(insn);\n+\t} else if (riscv_insn_is_c_lhu(insn)) {\n \t\tlen = 2;\n-\t\tinsn = RVC_RS2S(insn) \u003c\u003c SH_RD;\n-\t} else if ((insn \u0026 INSN_MASK_C_LH) == INSN_MATCH_C_LH) {\n+\t\trd = (8 + riscv_insn_c_lhu_extract_xd(insn));\n+\t} else if (riscv_insn_is_c_lh(insn)) {\n \t\tlen = 2;\n-\t\tshift = 8 * (sizeof(ulong) - len);\n-\t\tinsn = RVC_RS2S(insn) \u003c\u003c SH_RD;\n+\t\tshift = 8 * (sizeof(unsigned long) - len);\n+\t\trd = (8 + riscv_insn_c_lh_extract_xd(insn));\n \t} else {\n \t\tregs-\u003eepc = epc;\n \t\treturn -1;\n@@ -319,11 +301,11 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)\n \t}\n \n \tif (!fp)\n-\t\tSET_RD(insn, regs, (long)(val.data_ulong \u003c\u003c shift) \u003e\u003e shift);\n+\t\t*(unsigned long *)((unsigned long *)regs + rd) = val.data_ulong \u003c\u003c shift;\n \telse if (len == 8)\n-\t\tset_f64_rd(insn, regs, val.data_u64);\n+\t\tset_f64_rd(rd, regs, val.data_u64);\n \telse\n-\t\tset_f32_rd(insn, regs, val.data_ulong);\n+\t\tset_f32_rd(rd, regs, val.data_ulong);\n \n \tregs-\u003eepc = epc + INSN_LEN(insn);\n \n@@ -336,7 +318,7 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)\n \tunsigned long epc = regs-\u003eepc;\n \tunsigned long insn;\n \tunsigned long addr = regs-\u003ebadaddr;\n-\tint len = 0, fp = 0;\n+\tint fp = 0, len = 0, rd = 0;\n \n \tperf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);\n \n@@ -351,67 +333,68 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)\n \n \tregs-\u003eepc = 0;\n \n-\tval.data_ulong = GET_RS2(insn, regs);\n-\n-\tif ((insn \u0026 INSN_MASK_SW) == INSN_MATCH_SW) {\n+\tif (riscv_insn_is_sw(insn)) {\n \t\tlen = 4;\n-#if defined(CONFIG_64BIT)\n-\t} else if ((insn \u0026 INSN_MASK_SD) == INSN_MATCH_SD) {\n+\t\trd = riscv_insn_sw_extract_xs2(insn);\n+\t} else if (riscv_insn_is_sd(insn)) {\n \t\tlen = 8;\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_FSD) == INSN_MATCH_FSD) {\n+\t\trd = riscv_insn_sd_extract_xs2(insn);\n+\t} else if (riscv_insn_is_fsd(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t\tval.data_u64 = GET_F64_RS2(insn, regs);\n-\t} else if ((insn \u0026 INSN_MASK_FSW) == INSN_MATCH_FSW) {\n+\t\trd = riscv_insn_fsd_extract_fs2(insn);\n+\t} else if (riscv_insn_is_fsw(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_F32_RS2(insn, regs);\n-\t} else if ((insn \u0026 INSN_MASK_SH) == INSN_MATCH_SH) {\n+\t\trd = riscv_insn_fsw_extract_fs2(insn);\n+\t} else if (riscv_insn_is_sh(insn)) {\n \t\tlen = 2;\n-#if defined(CONFIG_64BIT)\n-\t} else if ((insn \u0026 INSN_MASK_C_SD) == INSN_MATCH_C_SD) {\n+\t\trd = riscv_insn_sh_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sd(insn)) {\n \t\tlen = 8;\n-\t\tval.data_ulong = GET_RS2S(insn, regs);\n-\t} else if ((insn \u0026 INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) {\n+\t\trd = riscv_insn_c_sd_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sdsp(insn)) {\n \t\tlen = 8;\n-\t\tval.data_ulong = GET_RS2C(insn, regs);\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_C_SW) == INSN_MATCH_C_SW) {\n+\t\trd = riscv_insn_c_sdsp_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sw(insn)) {\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_RS2S(insn, regs);\n-\t} else if ((insn \u0026 INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) {\n+\t\trd = riscv_insn_c_sw_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_swsp(insn)) {\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_RS2C(insn, regs);\n-\t} else if ((insn \u0026 INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) {\n+\t\trd = riscv_insn_c_swsp_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_fsd(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t\tval.data_u64 = GET_F64_RS2S(insn, regs);\n-\t} else if ((insn \u0026 INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) {\n+\t\trd = riscv_insn_c_fsd_extract_fs2(insn);\n+\t} else if (riscv_insn_is_c_fsdsp(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t\tval.data_u64 = GET_F64_RS2C(insn, regs);\n-#if !defined(CONFIG_64BIT)\n-\t} else if ((insn \u0026 INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) {\n+\t\trd = riscv_insn_c_fsdsp_extract_fs2(insn);\n+\t} else if (riscv_insn_is_c_fsw(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_F32_RS2S(insn, regs);\n-\t} else if ((insn \u0026 INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) {\n+\t\trd = riscv_insn_c_fsw_extract_fs2(insn);\n+\t} else if (riscv_insn_is_c_fswsp(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_F32_RS2C(insn, regs);\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_C_SH) == INSN_MATCH_C_SH) {\n+\t\trd = riscv_insn_c_fswsp_extract_fs2(insn);\n+\t} else if (riscv_insn_is_c_sh(insn)) {\n \t\tlen = 2;\n-\t\tval.data_ulong = GET_RS2S(insn, regs);\n+\t\trd = riscv_insn_c_sh_extract_xs2(insn);\n \t} else {\n-\t\tregs-\u003eepc = epc;\n \t\treturn -1;\n \t}\n \n \tif (!IS_ENABLED(CONFIG_FPU) \u0026\u0026 fp)\n \t\treturn -EOPNOTSUPP;\n \n+\tif (!fp)\n+\t\tval.data_ulong = *(unsigned long *)((unsigned long *)regs + rd);\n+\telse if (len == 8)\n+\t\tval.data_u64 = get_f64_rs(rd, regs);\n+\telse\n+\t\tval.data_ulong = get_f32_rs(rd, regs);\n+\n \tif (user_mode(regs)) {\n \t\tif (copy_to_user((u8 __user *)addr, \u0026val, len))\n \t\t\treturn -1;\ndiff --git a/arch/riscv/kvm/Kconfig.debug b/arch/riscv/kvm/Kconfig.debug\nnew file mode 100644\nindex 00000000000000..dc76e02120a32c\n--- /dev/null\n+++ b/arch/riscv/kvm/Kconfig.debug\n@@ -0,0 +1,16 @@\n+# SPDX-License-Identifier: GPL-2.0-only\n+menu \"arch/riscv/kvm testing\"\n+\n+config RISCV_KVM_TEST_CSR\n+ bool \"Test KVM CSR emulation\"\n+ depends on KVM\n+ default n\n+ help\n+ Enable this option to enable the emulation of a test hypervisor csr.\n+ The KVM test csr is the vsscratch register. Once this is enabled,\n+ reading/writing to the vsscratch register will trap into the host\n+ supervisor and reflect the change.\n+\n+ If unsure, say N.\n+\n+endmenu # \"arch/riscv/kvm testing\"\ndiff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile\nindex 296c2ba05089ac..5092b86751c4c5 100644\n--- a/arch/riscv/kvm/Makefile\n+++ b/arch/riscv/kvm/Makefile\n@@ -38,6 +38,7 @@ kvm-y += vcpu_sbi_sta.o\n kvm-y += vcpu_sbi_system.o\n kvm-$(CONFIG_RISCV_SBI_V01) += vcpu_sbi_v01.o\n kvm-y += vcpu_switch.o\n+kvm-$(CONFIG_RISCV_KVM_TEST_CSR) += vcpu_test_csr.o\n kvm-y += vcpu_timer.o\n kvm-y += vcpu_vector.o\n kvm-y += vm.o\ndiff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c\nindex f09f9251d1f0a0..d666cd24f8c0e9 100644\n--- a/arch/riscv/kvm/vcpu_insn.c\n+++ b/arch/riscv/kvm/vcpu_insn.c\n@@ -10,9 +10,10 @@\n #include \u003casm/cpufeature.h\u003e\n #include \u003casm/insn.h\u003e\n \n+#include \u003casm/kvm_vcpu_test_csr.h\u003e\n+\n struct insn_func {\n-\tunsigned long mask;\n-\tunsigned long match;\n+\tbool (*cmp)(u32 insn);\n \t/*\n \t * Possible return values are as follows:\n \t * 1) Returns \u003c 0 for error case\n@@ -112,6 +113,9 @@ static int seed_csr_rmw(struct kvm_vcpu *vcpu, unsigned int csr_num,\n static const struct csr_func csr_funcs[] = {\n \tKVM_RISCV_VCPU_AIA_CSR_FUNCS\n \tKVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS\n+#ifdef CONFIG_RISCV_KVM_TEST_CSR\n+\tKVM_RISCV_VCPU_TEST_CSR_FUNCS\n+#endif\n \t{ .base = CSR_SEED, .count = 1, .func = seed_csr_rmw },\n };\n \n@@ -126,65 +130,70 @@ static const struct csr_func csr_funcs[] = {\n */\n int kvm_riscv_vcpu_csr_return(struct kvm_vcpu *vcpu, struct kvm_run *run)\n {\n-\tulong insn;\n-\n \tif (vcpu-\u003earch.csr_decode.return_handled)\n \t\treturn 0;\n \tvcpu-\u003earch.csr_decode.return_handled = 1;\n \n \t/* Update destination register for CSR reads */\n-\tinsn = vcpu-\u003earch.csr_decode.insn;\n-\tif ((insn \u003e\u003e SH_RD) \u0026 MASK_RX)\n-\t\tSET_RD(insn, \u0026vcpu-\u003earch.guest_context,\n-\t\t run-\u003eriscv_csr.ret_value);\n+\tif (vcpu-\u003earch.csr_decode.rd)\n+\t\t*((ulong *)\u0026vcpu-\u003earch.guest_context +\n+\t\t vcpu-\u003earch.csr_decode.rd) = run-\u003eriscv_csr.ret_value;\n \n \t/* Move to next instruction */\n-\tvcpu-\u003earch.guest_context.sepc += INSN_LEN(insn);\n+\tvcpu-\u003earch.guest_context.sepc += vcpu-\u003earch.csr_decode.insn_len;\n \n \treturn 0;\n }\n \n static int csr_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, ulong insn)\n {\n+\t#define GET_REG(_rd) (*((unsigned long *)(\u0026vcpu-\u003earch.guest_context) + _rd))\n+\n \tint i, rc = KVM_INSN_ILLEGAL_TRAP;\n-\tunsigned int csr_num = insn \u003e\u003e SH_RS2;\n-\tunsigned int rs1_num = (insn \u003e\u003e SH_RS1) \u0026 MASK_RX;\n-\tulong rs1_val = GET_RS1(insn, \u0026vcpu-\u003earch.guest_context);\n+\tunsigned int csr_num, rd;\n \tconst struct csr_func *tcfn, *cfn = NULL;\n \tulong val = 0, wr_mask = 0, new_val = 0;\n \n \t/* Decode the CSR instruction */\n-\tswitch (GET_FUNCT3(insn)) {\n-\tcase GET_FUNCT3(INSN_MATCH_CSRRW):\n+\tif (riscv_insn_is_csrrw(insn)) {\n \t\twr_mask = -1UL;\n-\t\tnew_val = rs1_val;\n-\t\tbreak;\n-\tcase GET_FUNCT3(INSN_MATCH_CSRRS):\n-\t\twr_mask = rs1_val;\n+\t\tnew_val = GET_REG(riscv_insn_csrrw_extract_xs1(insn));\n+\t\tcsr_num = riscv_insn_csrrw_extract_csr(insn);\n+\t\trd = riscv_insn_csrrw_extract_xd(insn);\n+\t} else if (riscv_insn_is_csrrs(insn)) {\n+\t\twr_mask = GET_REG(riscv_insn_csrrs_extract_xs1(insn));\n \t\tnew_val = -1UL;\n-\t\tbreak;\n-\tcase GET_FUNCT3(INSN_MATCH_CSRRC):\n-\t\twr_mask = rs1_val;\n+\t\tcsr_num = riscv_insn_csrrs_extract_csr(insn);\n+\t\trd = riscv_insn_csrrs_extract_xd(insn);\n+\t} else if (riscv_insn_is_csrrc(insn)) {\n+\t\twr_mask = GET_REG(riscv_insn_csrrc_extract_xs1(insn));\n \t\tnew_val = 0;\n-\t\tbreak;\n-\tcase GET_FUNCT3(INSN_MATCH_CSRRWI):\n+\t\tcsr_num = riscv_insn_csrrc_extract_csr(insn);\n+\t\trd = riscv_insn_csrrc_extract_xd(insn);\n+\t} else if (riscv_insn_is_csrrwi(insn)) {\n \t\twr_mask = -1UL;\n-\t\tnew_val = rs1_num;\n-\t\tbreak;\n-\tcase GET_FUNCT3(INSN_MATCH_CSRRSI):\n-\t\twr_mask = rs1_num;\n+\t\tnew_val = riscv_insn_csrrwi_extract_imm(insn);\n+\t\tcsr_num = riscv_insn_csrrwi_extract_csr(insn);\n+\t\trd = riscv_insn_csrrwi_extract_xd(insn);\n+\t} else if (riscv_insn_is_csrrsi(insn)) {\n+\t\twr_mask = riscv_insn_csrrwi_extract_imm(insn);\n \t\tnew_val = -1UL;\n-\t\tbreak;\n-\tcase GET_FUNCT3(INSN_MATCH_CSRRCI):\n-\t\twr_mask = rs1_num;\n+\t\tcsr_num = riscv_insn_csrrsi_extract_csr(insn);\n+\t\trd = riscv_insn_csrrsi_extract_xd(insn);\n+\t} else if (riscv_insn_is_csrrci(insn)) {\n+\t\twr_mask = riscv_insn_csrrci_extract_imm(insn);\n \t\tnew_val = 0;\n-\t\tbreak;\n-\tdefault:\n+\t\tcsr_num = riscv_insn_csrrci_extract_csr(insn);\n+\t\trd = riscv_insn_csrrci_extract_xd(insn);\n+\t} else {\n \t\treturn rc;\n \t}\n \n+\t#undef GET_REG\n+\n \t/* Save instruction decode info */\n-\tvcpu-\u003earch.csr_decode.insn = insn;\n+\tvcpu-\u003earch.csr_decode.rd = rd;\n+\tvcpu-\u003earch.csr_decode.insn_len = INSN_LEN(insn);\n \tvcpu-\u003earch.csr_decode.return_handled = 0;\n \n \t/* Update CSR details in kvm_run struct */\n@@ -228,43 +237,39 @@ static int csr_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, ulong insn)\n \n static const struct insn_func system_opcode_funcs[] = {\n \t{\n-\t\t.mask = INSN_MASK_CSRRW,\n-\t\t.match = INSN_MATCH_CSRRW,\n+\t\t.cmp = riscv_insn_is_csrrw,\n \t\t.func = csr_insn,\n \t},\n \t{\n-\t\t.mask = INSN_MASK_CSRRS,\n-\t\t.match = INSN_MATCH_CSRRS,\n+\t\t.cmp = riscv_insn_is_csrrs,\n \t\t.func = csr_insn,\n \t},\n \t{\n-\t\t.mask = INSN_MASK_CSRRC,\n-\t\t.match = INSN_MATCH_CSRRC,\n+\t\t.cmp = riscv_insn_is_csrrc,\n \t\t.func = csr_insn,\n \t},\n \t{\n-\t\t.mask = INSN_MASK_CSRRWI,\n-\t\t.match = INSN_MATCH_CSRRWI,\n+\t\t.cmp = riscv_insn_is_csrrwi,\n \t\t.func = csr_insn,\n \t},\n \t{\n-\t\t.mask = INSN_MASK_CSRRSI,\n-\t\t.match = INSN_MATCH_CSRRSI,\n+\t\t.cmp = riscv_insn_is_csrrsi,\n \t\t.func = csr_insn,\n \t},\n \t{\n-\t\t.mask = INSN_MASK_CSRRCI,\n-\t\t.match = INSN_MATCH_CSRRCI,\n+\t\t.cmp = riscv_insn_is_csrrci,\n \t\t.func = csr_insn,\n \t},\n \t{\n-\t\t.mask = INSN_MASK_WFI,\n-\t\t.match = INSN_MATCH_WFI,\n+\t\t.cmp = riscv_insn_is_wfi,\n \t\t.func = wfi_insn,\n \t},\n \t{\n-\t\t.mask = INSN_MASK_WRS,\n-\t\t.match = INSN_MATCH_WRS,\n+\t\t.cmp = riscv_insn_is_wrs_nto,\n+\t\t.func = wrs_insn,\n+\t},\n+\t{\n+\t\t.cmp = riscv_insn_is_wrs_sto,\n \t\t.func = wrs_insn,\n \t},\n };\n@@ -277,7 +282,7 @@ static int system_opcode_insn(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \n \tfor (i = 0; i \u003c ARRAY_SIZE(system_opcode_funcs); i++) {\n \t\tifn = \u0026system_opcode_funcs[i];\n-\t\tif ((insn \u0026 ifn-\u003emask) == ifn-\u003ematch) {\n+\t\tif (ifn-\u003ecmp(insn)) {\n \t\t\trc = ifn-\u003efunc(vcpu, run, insn);\n \t\t\tbreak;\n \t\t}\n@@ -375,7 +380,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t\t\t unsigned long htinst)\n {\n \tu8 data_buf[8];\n-\tunsigned long insn;\n+\tunsigned long insn, rd;\n \tint shift = 0, len = 0, insn_len = 0;\n \tstruct kvm_cpu_trap utrap = { 0 };\n \tstruct kvm_cpu_context *ct = \u0026vcpu-\u003earch.guest_context;\n@@ -407,44 +412,47 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t}\n \n \t/* Decode length of MMIO and shift */\n-\tif ((insn \u0026 INSN_MASK_LW) == INSN_MATCH_LW) {\n+\tif (riscv_insn_is_lw(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t} else if ((insn \u0026 INSN_MASK_LB) == INSN_MATCH_LB) {\n+\t\trd = riscv_insn_lw_extract_xd(insn);\n+\t} else if (riscv_insn_is_lb(insn)) {\n \t\tlen = 1;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t} else if ((insn \u0026 INSN_MASK_LBU) == INSN_MATCH_LBU) {\n+\t\trd = riscv_insn_lb_extract_xd(insn);\n+\t} else if (riscv_insn_is_lbu(insn)) {\n \t\tlen = 1;\n-#ifdef CONFIG_64BIT\n-\t} else if ((insn \u0026 INSN_MASK_LD) == INSN_MATCH_LD) {\n+\t\trd = riscv_insn_lbu_extract_xd(insn);\n+\t} else if (riscv_insn_is_ld(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t} else if ((insn \u0026 INSN_MASK_LWU) == INSN_MATCH_LWU) {\n+\t\trd = riscv_insn_ld_extract_xd(insn);\n+\t} else if (riscv_insn_is_lwu(insn)) {\n \t\tlen = 4;\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_LH) == INSN_MATCH_LH) {\n+\t\trd = riscv_insn_lwu_extract_xd(insn);\n+\t} else if (riscv_insn_is_lh(insn)) {\n \t\tlen = 2;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t} else if ((insn \u0026 INSN_MASK_LHU) == INSN_MATCH_LHU) {\n+\t\trd = riscv_insn_lh_extract_xd(insn);\n+\t} else if (riscv_insn_is_lhu(insn)) {\n \t\tlen = 2;\n-#ifdef CONFIG_64BIT\n-\t} else if ((insn \u0026 INSN_MASK_C_LD) == INSN_MATCH_C_LD) {\n+\t\trd = riscv_insn_lhu_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_ld(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t\tinsn = RVC_RS2S(insn) \u003c\u003c SH_RD;\n-\t} else if ((insn \u0026 INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP \u0026\u0026\n-\t\t ((insn \u003e\u003e SH_RD) \u0026 0x1f)) {\n+\t\trd = riscv_insn_c_ld_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_ldsp(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_C_LW) == INSN_MATCH_C_LW) {\n+\t\trd = riscv_insn_c_ldsp_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_lw(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t\tinsn = RVC_RS2S(insn) \u003c\u003c SH_RD;\n-\t} else if ((insn \u0026 INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP \u0026\u0026\n-\t\t ((insn \u003e\u003e SH_RD) \u0026 0x1f)) {\n+\t\trd = riscv_insn_c_lw_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_lwsp(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(ulong) - len);\n+\t\trd = riscv_insn_c_lwsp_extract_xd(insn);\n \t} else {\n \t\treturn -EOPNOTSUPP;\n \t}\n@@ -454,7 +462,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t\treturn -EIO;\n \n \t/* Save instruction decode info */\n-\tvcpu-\u003earch.mmio_decode.insn = insn;\n+\tvcpu-\u003earch.mmio_decode.rd = rd;\n \tvcpu-\u003earch.mmio_decode.insn_len = insn_len;\n \tvcpu-\u003earch.mmio_decode.shift = shift;\n \tvcpu-\u003earch.mmio_decode.len = len;\n@@ -497,11 +505,7 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t\t\t unsigned long fault_addr,\n \t\t\t unsigned long htinst)\n {\n-\tu8 data8;\n-\tu16 data16;\n-\tu32 data32;\n-\tu64 data64;\n-\tulong data;\n+\tulong data, rs2;\n \tunsigned long insn;\n \tint len = 0, insn_len = 0;\n \tstruct kvm_cpu_trap utrap = { 0 };\n@@ -533,35 +537,30 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t\tinsn_len = INSN_LEN(insn);\n \t}\n \n-\tdata = GET_RS2(insn, \u0026vcpu-\u003earch.guest_context);\n-\tdata8 = data16 = data32 = data64 = data;\n-\n-\tif ((insn \u0026 INSN_MASK_SW) == INSN_MATCH_SW) {\n+\tif (riscv_insn_is_sw(insn)) {\n \t\tlen = 4;\n-\t} else if ((insn \u0026 INSN_MASK_SB) == INSN_MATCH_SB) {\n+\t\trs2 = riscv_insn_sw_extract_xs2(insn);\n+\t} else if (riscv_insn_is_sb(insn)) {\n \t\tlen = 1;\n-#ifdef CONFIG_64BIT\n-\t} else if ((insn \u0026 INSN_MASK_SD) == INSN_MATCH_SD) {\n+\t\trs2 = riscv_insn_sb_extract_xs2(insn);\n+\t} else if (riscv_insn_is_sd(insn)) {\n \t\tlen = 8;\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_SH) == INSN_MATCH_SH) {\n+\t\trs2 = riscv_insn_sd_extract_xs2(insn);\n+\t} else if (riscv_insn_is_sh(insn)) {\n \t\tlen = 2;\n-#ifdef CONFIG_64BIT\n-\t} else if ((insn \u0026 INSN_MASK_C_SD) == INSN_MATCH_C_SD) {\n+\t\trs2 = riscv_insn_sh_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sd(insn)) {\n \t\tlen = 8;\n-\t\tdata64 = GET_RS2S(insn, \u0026vcpu-\u003earch.guest_context);\n-\t} else if ((insn \u0026 INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP \u0026\u0026\n-\t\t ((insn \u003e\u003e SH_RD) \u0026 0x1f)) {\n+\t\trs2 = riscv_insn_c_sd_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sdsp(insn)) {\n \t\tlen = 8;\n-\t\tdata64 = GET_RS2C(insn, \u0026vcpu-\u003earch.guest_context);\n-#endif\n-\t} else if ((insn \u0026 INSN_MASK_C_SW) == INSN_MATCH_C_SW) {\n+\t\trs2 = riscv_insn_c_sdsp_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sw(insn)) {\n \t\tlen = 4;\n-\t\tdata32 = GET_RS2S(insn, \u0026vcpu-\u003earch.guest_context);\n-\t} else if ((insn \u0026 INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP \u0026\u0026\n-\t\t ((insn \u003e\u003e SH_RD) \u0026 0x1f)) {\n+\t\trs2 = riscv_insn_c_sw_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_swsp(insn)) {\n \t\tlen = 4;\n-\t\tdata32 = GET_RS2C(insn, \u0026vcpu-\u003earch.guest_context);\n+\t\trs2 = riscv_insn_c_swsp_extract_xs2(insn);\n \t} else {\n \t\treturn -EOPNOTSUPP;\n \t}\n@@ -570,26 +569,24 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \tif (fault_addr \u0026 (len - 1))\n \t\treturn -EIO;\n \n-\t/* Save instruction decode info */\n-\tvcpu-\u003earch.mmio_decode.insn = insn;\n \tvcpu-\u003earch.mmio_decode.insn_len = insn_len;\n-\tvcpu-\u003earch.mmio_decode.shift = 0;\n-\tvcpu-\u003earch.mmio_decode.len = len;\n \tvcpu-\u003earch.mmio_decode.return_handled = 0;\n \n+\tdata = *((ulong *)(\u0026vcpu-\u003earch.guest_context) + rs2);\n+\n \t/* Copy data to kvm_run instance */\n \tswitch (len) {\n \tcase 1:\n-\t\t*((u8 *)run-\u003emmio.data) = data8;\n+\t\t*((u8 *)run-\u003emmio.data) = data;\n \t\tbreak;\n \tcase 2:\n-\t\t*((u16 *)run-\u003emmio.data) = data16;\n+\t\t*((u16 *)run-\u003emmio.data) = data;\n \t\tbreak;\n \tcase 4:\n-\t\t*((u32 *)run-\u003emmio.data) = data32;\n+\t\t*((u32 *)run-\u003emmio.data) = data;\n \t\tbreak;\n \tcase 8:\n-\t\t*((u64 *)run-\u003emmio.data) = data64;\n+\t\t*((u64 *)run-\u003emmio.data) = data;\n \t\tbreak;\n \tdefault:\n \t\treturn -EOPNOTSUPP;\n@@ -625,18 +622,13 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,\n */\n int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)\n {\n-\tu8 data8;\n-\tu16 data16;\n-\tu32 data32;\n-\tu64 data64;\n-\tulong insn;\n \tint len, shift;\n+\tunsigned long data;\n \n \tif (vcpu-\u003earch.mmio_decode.return_handled)\n \t\treturn 0;\n \n \tvcpu-\u003earch.mmio_decode.return_handled = 1;\n-\tinsn = vcpu-\u003earch.mmio_decode.insn;\n \n \tif (run-\u003emmio.is_write)\n \t\tgoto done;\n@@ -646,29 +638,23 @@ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)\n \n \tswitch (len) {\n \tcase 1:\n-\t\tdata8 = *((u8 *)run-\u003emmio.data);\n-\t\tSET_RD(insn, \u0026vcpu-\u003earch.guest_context,\n-\t\t\t(long)((ulong)data8 \u003c\u003c shift) \u003e\u003e shift);\n+\t\tdata = *((u8 *)run-\u003emmio.data);\n \t\tbreak;\n \tcase 2:\n-\t\tdata16 = *((u16 *)run-\u003emmio.data);\n-\t\tSET_RD(insn, \u0026vcpu-\u003earch.guest_context,\n-\t\t\t(long)((ulong)data16 \u003c\u003c shift) \u003e\u003e shift);\n+\t\tdata = *((u16 *)run-\u003emmio.data);\n \t\tbreak;\n \tcase 4:\n-\t\tdata32 = *((u32 *)run-\u003emmio.data);\n-\t\tSET_RD(insn, \u0026vcpu-\u003earch.guest_context,\n-\t\t\t(long)((ulong)data32 \u003c\u003c shift) \u003e\u003e shift);\n+\t\tdata = *((u32 *)run-\u003emmio.data);\n \t\tbreak;\n \tcase 8:\n-\t\tdata64 = *((u64 *)run-\u003emmio.data);\n-\t\tSET_RD(insn, \u0026vcpu-\u003earch.guest_context,\n-\t\t\t(long)((ulong)data64 \u003c\u003c shift) \u003e\u003e shift);\n+\t\tdata = *((u64 *)run-\u003emmio.data);\n \t\tbreak;\n \tdefault:\n \t\treturn -EOPNOTSUPP;\n \t}\n \n+\t*((ulong *)(\u0026vcpu-\u003earch.guest_context) + vcpu-\u003earch.mmio_decode.rd) =\n+\t\t(long)data \u003c\u003c shift \u003e\u003e shift;\n done:\n \t/* Move to next instruction */\n \tvcpu-\u003earch.guest_context.sepc += vcpu-\u003earch.mmio_decode.insn_len;\ndiff --git a/arch/riscv/kvm/vcpu_test_csr.c b/arch/riscv/kvm/vcpu_test_csr.c\nnew file mode 100644\nindex 00000000000000..b8aa503cdaba76\n--- /dev/null\n+++ b/arch/riscv/kvm/vcpu_test_csr.c\n@@ -0,0 +1,21 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+#include \u003clinux/kvm_host.h\u003e\n+#include \u003casm/kvm_vcpu_insn.h\u003e\n+#include \u003casm/kvm_vcpu_test_csr.h\u003e\n+\n+#define vcpu_to_test_csr(vcpu) (\u0026(vcpu)-\u003earch.test_csr)\n+\n+int kvm_riscv_vcpu_test_csr(struct kvm_vcpu *vcpu, unsigned int csr_num,\n+\t\t\t unsigned long *val, unsigned long new_val,\n+\t\t\t unsigned long wr_mask)\n+{\n+\tstruct kvm_test_csr *test_csr = vcpu_to_test_csr(vcpu);\n+\n+\t*val = test_csr-\u003eval;\n+\n+\tif (wr_mask)\n+\t\ttest_csr-\u003eval = (test_csr-\u003eval \u0026 ~wr_mask) | (new_val \u0026 wr_mask);\n+\n+\treturn KVM_INSN_CONTINUE_NEXT_SEPC;\n+}\ndiff --git a/arch/riscv/tools/Makefile b/arch/riscv/tools/Makefile\nnew file mode 100644\nindex 00000000000000..5f40439c12e9c1\n--- /dev/null\n+++ b/arch/riscv/tools/Makefile\n@@ -0,0 +1,22 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+gen := arch/$(ARCH)/include/generated/asm\n+insn_tbl := $(src)/insn_tbl.sh\n+insn := $(src)/insn.tbl\n+\n+gen-y := $(gen)/insn_gen.h\n+\n+targets += $(addprefix ../../../,$(gen-y))\n+\n+PHONY += insn\n+\n+insn:\t$(gen-y)\n+\n+# Create output directory if not already present\n+$(shell mkdir -p $(gen))\n+\n+quiet_cmd_insn_tbl = INST_TBL $@\n+ cmd_insn_tbl = $(CONFIG_SHELL) $(insn_tbl) $\u003c $@\n+\n+$(gen)/insn_gen.h: $(insn) $(insn_tbl) FORCE\n+\t$(call if_changed,insn_tbl)\ndiff --git a/arch/riscv/tools/insn.tbl b/arch/riscv/tools/insn.tbl\nnew file mode 100644\nindex 00000000000000..5dc3392a5543c8\n--- /dev/null\n+++ b/arch/riscv/tools/insn.tbl\n@@ -0,0 +1,1392 @@\n+# SPDX-License-Identifier: BSD-3-Clause-Clear\n+#\n+# GENERATED WITH https://github.com/riscv-software-src/riscv-unified-db\n+# \"./bin/generate inst-table -o test_table.txt\"\n+#\n+# Each line of the instruction table should have the following format:\n+# NAME BASE FIXED_BITS [VARIABLE_LIST]\n+# NAME instruction name\n+# BASE instruction base size (common[,(32|64)])\n+# \"common\" means the instruction is valid on both architecture sizes\n+# \"32\" or \"64\" means the instruction is valid on that size\n+# if the instruction is valid on both architectures but has unique\n+# encodings, use a 32-bit entry \"common,32\" and 64-bit entry\n+# FIXED_BITS bitfields of the fixed bits of an instruction concatenated with '|'\n+# continuous grouping of fixed bits are in the form of 'bits\u003coffset'\n+# VARIABLE_LIST a variable sized list of all variables in the instruction definition\n+# in the form of name[~][\u003cnum][!num...]=(high[-low])|...\n+# symbols after the name represent different modifiers:\n+# ~ sign extension, can only appear once\n+# \u003c left shift by 'num' amount on extraction, can only appear once\n+# ! mark 'num' as an invalid input for this variable\n+andn common 0100000\u003c25|111\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+clmul common 0000101\u003c25|001\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+clmulh common 0000101\u003c25|011\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+orn common 0100000\u003c25|110\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+rev8 common,32 011010011000\u003c20|101\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+rev8 common,64 011010111000\u003c20|101\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+rol common 0110000\u003c25|001\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+rolw 64 0110000\u003c25|001\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+ror common 0110000\u003c25|101\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+rori common,32 0110000\u003c25|101\u003c12|0010011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+rori common,64 011000\u003c26|101\u003c12|0010011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+roriw 64 0110000\u003c25|101\u003c12|0011011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+rorw 64 0110000\u003c25|101\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+xnor common 0100000\u003c25|100\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+c.add common 1001\u003c12|10\u003c0 xs2!0=6-2 xd!0=11-7\n+c.addi common 000\u003c13|01\u003c0 imm~!0=12|6-2 xd!0=11-7\n+c.addi16sp common 011\u003c13|00010\u003c7|01\u003c0 imm~!0\u003c4=12|4-3|5|2|6\n+c.addi4spn common 000\u003c13|00\u003c0 imm!0\u003c2=10-7|12-11|5|6 xd=4-2\n+c.addiw 64 001\u003c13|01\u003c0 imm~=12|6-2 xd!0=11-7\n+c.addw 64 100111\u003c10|01\u003c5|01\u003c0 xs2=4-2 xd=9-7\n+c.and common 100011\u003c10|11\u003c5|01\u003c0 xs2=4-2 xd=9-7\n+c.andi common 100\u003c13|10\u003c10|01\u003c0 imm~=12|6-2 xd=9-7\n+c.beqz common 110\u003c13|01\u003c0 imm~\u003c1=12|6-5|2|11-10|4-3 xs1=9-7\n+c.bnez common 111\u003c13|01\u003c0 imm~\u003c1=12|6-5|2|11-10|4-3 xs1=9-7\n+c.ebreak common 1001000000000010\u003c0\n+c.j common 101\u003c13|01\u003c0 imm~\u003c1=12|8|10-9|6|7|2|11|5-3\n+c.jal 32 001\u003c13|01\u003c0 imm~\u003c1=12|8|10-9|6|7|2|11|5-3\n+c.jalr common 1001\u003c12|0000010\u003c0 xs1!0=11-7\n+c.jr common 1000\u003c12|0000010\u003c0 xs1!0=11-7\n+c.ld common,32 011\u003c13|00\u003c0 imm\u003c3=6-5|12-10 xd!1!3!5!7=4-2 xs1=9-7\n+c.ld common,64 011\u003c13|00\u003c0 imm\u003c3=6-5|12-10 xd=4-2 xs1=9-7\n+c.ldsp common,32 011\u003c13|10\u003c0 imm\u003c3=4-2|12|6-5 xd!0!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=11-7\n+c.ldsp common,64 011\u003c13|10\u003c0 imm\u003c3=4-2|12|6-5 xd=11-7\n+c.li common 010\u003c13|01\u003c0 imm~=12|6-2 xd!0=11-7\n+c.lui common 011\u003c13|01\u003c0 imm~\u003c12=12|6-2 xd!0!2=11-7\n+c.lw common 010\u003c13|00\u003c0 imm\u003c2=5|12-10|6 xd=4-2 xs1=9-7\n+c.lwsp common 010\u003c13|10\u003c0 imm\u003c2=3-2|12|6-4 xd!0=11-7\n+c.mv common 1000\u003c12|10\u003c0 xd!0=11-7 xs2!0=6-2\n+c.nop common 0000000000000001\u003c0\n+c.or common 100011\u003c10|10\u003c5|01\u003c0 xs2=4-2 xd=9-7\n+c.sd common,32 111\u003c13|00\u003c0 imm\u003c3=6-5|12-10 xs2!1!3!5!7=4-2 xs1=9-7\n+c.sd common,64 111\u003c13|00\u003c0 imm\u003c3=6-5|12-10 xs2=4-2 xs1=9-7\n+c.sdsp common,32 111\u003c13|10\u003c0 xs2!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=6-2 imm\u003c3=9-7|12-10\n+c.sdsp common,64 111\u003c13|10\u003c0 xs2=6-2 imm\u003c3=9-7|12-10\n+c.slli common,32 0000\u003c12|10\u003c0 shamt!0=6-2 xd=11-7\n+c.slli common,64 000\u003c13|10\u003c0 shamt!0=12|6-2 xd=11-7\n+c.srai common,32 100001\u003c10|01\u003c0 shamt!0=6-2 xd=9-7\n+c.srai common,64 100\u003c13|01\u003c10|01\u003c0 shamt!0=12|6-2 xd=9-7\n+c.srli common,32 100000\u003c10|01\u003c0 shamt!0=6-2 xd=9-7\n+c.srli common,64 100\u003c13|00\u003c10|01\u003c0 shamt!0=12|6-2 xd=9-7\n+c.sub common 100011\u003c10|00\u003c5|01\u003c0 xs2=4-2 xd=9-7\n+c.subw 64 100111\u003c10|00\u003c5|01\u003c0 xs2=4-2 xd=9-7\n+c.sw common 110\u003c13|00\u003c0 imm\u003c2=5|12-10|6 xs2=4-2 xs1=9-7\n+c.swsp common 110\u003c13|10\u003c0 imm\u003c2=8-7|12-9 xs2=6-2\n+c.xor common 100011\u003c10|01\u003c5|01\u003c0 xs2=4-2 xd=9-7\n+fadd.d common 0000001\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fclass.d common 111000100000\u003c20|001\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fcvt.d.l 64 110100100010\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.d.lu 64 110100100011\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.d.s common 010000100000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.d.w common 110100100000\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.d.wu common 110100100001\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.l.d 64 110000100010\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.lu.d 64 110000100011\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.s.d common 010000000001\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.w.d common 110000100000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.wu.d common 110000100001\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvtmod.w.d common 110000101000\u003c20|1010011\u003c0 fs1=19-15 rm!0!2!3!4!5!6!7=14-12 xd=11-7\n+fdiv.d common 0001101\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+feq.d common 1010001\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fld common 011\u003c12|0000111\u003c0 imm=31-20 xs1=19-15 fd=11-7\n+fle.d common 1010001\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fleq.d common 1010001\u003c25|100\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fli.d common 111100100001\u003c20|000\u003c12|1010011\u003c0 xs1=19-15 fd=11-7\n+flt.d common 1010001\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fltq.d common 1010001\u003c25|101\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fmadd.d common 01\u003c25|1000011\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmax.d common 0010101\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmaxm.d common 0010101\u003c25|011\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmin.d common 0010101\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fminm.d common 0010101\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmsub.d common 01\u003c25|1000111\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmul.d common 0001001\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmv.d.x 64 111100100000\u003c20|000\u003c12|1010011\u003c0 xs1=19-15 fd=11-7\n+fmv.x.d 64 111000100000\u003c20|000\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fmvh.x.d 32 111000100001\u003c20|000\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fmvp.d.x 32 1011001\u003c25|000\u003c12|1010011\u003c0 xs2=24-20 xs1=19-15 fd=11-7\n+fnmadd.d common 01\u003c25|1001111\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fnmsub.d common 01\u003c25|1001011\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fround.d common 010000100100\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+froundnx.d common 010000100101\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fsd common 011\u003c12|0100111\u003c0 imm=31-25|11-7 fs2=24-20 xs1=19-15\n+fsgnj.d common 0010001\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsgnjn.d common 0010001\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsgnjx.d common 0010001\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsqrt.d common 010110100000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fsub.d common 0000101\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fadd.s common 0000000\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fclass.s common 111000000000\u003c20|001\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fcvt.l.s 64 110000000010\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.lu.s 64 110000000011\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.s.l 64 110100000010\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.s.lu 64 110100000011\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.s.w common 110100000000\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.s.wu common 110100000001\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.w.s common 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fd=11-7\n+fmsub.s common 00\u003c25|1000111\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmul.s common 0001000\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmv.w.x common 111100000000\u003c20|000\u003c12|1010011\u003c0 xs1=19-15 fd=11-7\n+fmv.x.w common 111000000000\u003c20|000\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fnmadd.s common 00\u003c25|1001111\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fnmsub.s common 00\u003c25|1001011\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fsgnj.s common 0010000\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsgnjn.s common 0010000\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsgnjx.s common 0010000\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsqrt.s common 010110000000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fsub.s common 0000100\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fsw common 010\u003c12|0100111\u003c0 imm=31-25|11-7 fs2=24-20 xs1=19-15\n+hfence.gvma common 0110001\u003c25|000000001110011\u003c0 xs2=24-20 xs1=19-15\n+hfence.vvma common 0010001\u003c25|000000001110011\u003c0 xs2=24-20 xs1=19-15\n+hlv.b common 011000000000\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hlv.bu common 011000000001\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hlv.d 64 011011000000\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hlv.h common 011001000000\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hlv.hu common 011001000001\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hlv.w common 011010000000\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hlv.wu 64 011010000001\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hlvx.hu common 011001000011\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hlvx.wu common 011010000011\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+hsv.b common 0110001\u003c25|100000001110011\u003c0 xs2=24-20 xs1=19-15\n+hsv.d 64 0110111\u003c25|100000001110011\u003c0 xs2=24-20 xs1=19-15\n+hsv.h common 0110011\u003c25|100000001110011\u003c0 xs2=24-20 xs1=19-15\n+hsv.w common 0110101\u003c25|100000001110011\u003c0 xs2=24-20 xs1=19-15\n+add common 0000000\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+addi common 000\u003c12|0010011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+addiw 64 000\u003c12|0011011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+addw 64 0000000\u003c25|000\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+and common 0000000\u003c25|111\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+andi common 111\u003c12|0010011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+auipc common 0010111\u003c0 imm~\u003c12=31-12 xd=11-7\n+beq common 000\u003c12|1100011\u003c0 imm~\u003c1=31|7|30-25|11-8 xs2=24-20 xs1=19-15\n+bge common 101\u003c12|1100011\u003c0 imm~\u003c1=31|7|30-25|11-8 xs2=24-20 xs1=19-15\n+bgeu common 111\u003c12|1100011\u003c0 imm~\u003c1=31|7|30-25|11-8 xs2=24-20 xs1=19-15\n+blt common 100\u003c12|1100011\u003c0 imm~\u003c1=31|7|30-25|11-8 xs2=24-20 xs1=19-15\n+bltu common 110\u003c12|1100011\u003c0 imm~\u003c1=31|7|30-25|11-8 xs2=24-20 xs1=19-15\n+bne common 001\u003c12|1100011\u003c0 imm~\u003c1=31|7|30-25|11-8 xs2=24-20 xs1=19-15\n+ebreak common 00000000000100000000000001110011\u003c0\n+ecall common 00000000000000000000000001110011\u003c0\n+fence.tso common 100000110011\u003c20|000\u003c12|0001111\u003c0 xs1=19-15 xd=11-7\n+fence common 000\u003c12|0001111\u003c0 fm=31-28 pred=27-24 succ=23-20 xs1=19-15 xd=11-7\n+jal common 1101111\u003c0 imm~\u003c1=31|19-12|20|30-21 xd=11-7\n+jalr common 000\u003c12|1100111\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+lb common 000\u003c12|0000011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+lbu common 100\u003c12|0000011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+ld common,32 011\u003c12|0000011\u003c0 imm~=31-20 xs1=19-15 xd!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=11-7\n+ld common,64 011\u003c12|0000011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+lh common 001\u003c12|0000011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+lhu common 101\u003c12|0000011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+lui common 0110111\u003c0 imm~\u003c12=31-12 xd=11-7\n+lw common 010\u003c12|0000011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+lwu 64 110\u003c12|0000011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+mret common 00110000001000000000000001110011\u003c0\n+or common 0000000\u003c25|110\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+ori common 110\u003c12|0010011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+sb common 000\u003c12|0100011\u003c0 imm~=31-25|11-7 xs2=24-20 xs1=19-15\n+sd common,32 011\u003c12|0100011\u003c0 imm~=31-25|11-7 xs2!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=24-20 xs1=19-15\n+sd common,64 011\u003c12|0100011\u003c0 imm~=31-25|11-7 xs2=24-20 xs1=19-15\n+sh common 001\u003c12|0100011\u003c0 imm~=31-25|11-7 xs2=24-20 xs1=19-15\n+sll common 0000000\u003c25|001\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+slli common,32 0000000\u003c25|001\u003c12|0010011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+slli common,64 000000\u003c26|001\u003c12|0010011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+slliw 64 0000000\u003c25|001\u003c12|0011011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+sllw 64 0000000\u003c25|001\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+slt common 0000000\u003c25|010\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+slti common 010\u003c12|0010011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+sltiu common 011\u003c12|0010011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+sltu common 0000000\u003c25|011\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sra common 0100000\u003c25|101\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+srai common,32 0100000\u003c25|101\u003c12|0010011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+srai common,64 010000\u003c26|101\u003c12|0010011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+sraiw 64 0100000\u003c25|101\u003c12|0011011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+sraw 64 0100000\u003c25|101\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+srl common 0000000\u003c25|101\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+srli common,32 0000000\u003c25|101\u003c12|0010011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+srli common,64 000000\u003c26|101\u003c12|0010011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+srliw 64 0000000\u003c25|101\u003c12|0011011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+srlw 64 0000000\u003c25|101\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sub common 0100000\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+subw 64 0100000\u003c25|000\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sw common 010\u003c12|0100011\u003c0 imm~=31-25|11-7 xs2=24-20 xs1=19-15\n+wfi common 00010000010100000000000001110011\u003c0\n+xor common 0000000\u003c25|100\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+xori common 100\u003c12|0010011\u003c0 imm~=31-20 xs1=19-15 xd=11-7\n+div common 0000001\u003c25|100\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+divu common 0000001\u003c25|101\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+divuw 64 0000001\u003c25|101\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+divw 64 0000001\u003c25|100\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mul common 0000001\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mulh common 0000001\u003c25|001\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mulhsu common 0000001\u003c25|010\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mulhu common 0000001\u003c25|011\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mulw 64 0000001\u003c25|000\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+rem common 0000001\u003c25|110\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+remu common 0000001\u003c25|111\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+remuw 64 0000001\u003c25|111\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+remw 64 0000001\u003c25|110\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+fadd.q common 0000011\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fclass.q common 111001100000\u003c20|001\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fcvt.d.q common 010000100011\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.h.q common 010001000011\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.l.q 64 110001100010\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.lu.q 64 110001100011\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.q.d common 010001100001\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.q.h common 010001100010\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.q.l 64 110101100010\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.q.lu 64 110101100011\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.q.s common 010001100000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.q.w common 110101100000\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.q.wu common 110101100001\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.s.q common 010000000011\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.w.q common 110001100000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.wu.q common 110001100001\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fdiv.q common 0001111\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+feq.q common 1010011\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fle.q common 1010011\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fleq.q common 1010011\u003c25|100\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fli.q common 111101100001\u003c20|000\u003c12|1010011\u003c0 xs1=19-15 fd=11-7\n+flq common 100\u003c12|0000111\u003c0 imm=31-20 xs1=19-15 fd=11-7\n+flt.q common 1010011\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fltq.q common 1010011\u003c25|101\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmadd.q common 11\u003c25|1000011\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmax.q common 0010111\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmaxm.q common 0010111\u003c25|011\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmin.q common 0010111\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fminm.q common 0010111\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmsub.q common 11\u003c25|1000111\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmul.q common 0001011\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmvh.x.q 64 111001100001\u003c20|000\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fmvp.q.x 64 1011011\u003c25|000\u003c12|1010011\u003c0 xs2=24-20 xs1=19-15 fd=11-7\n+fnmadd.q common 11\u003c25|1001111\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fnmsub.q common 11\u003c25|1001011\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fround.q common 010001100100\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+froundnx.q common 010001100101\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fsgnj.q common 0010011\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsgnjn.q common 0010011\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsgnjx.q common 0010011\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsq common 100\u003c12|0100111\u003c0 imm=31-25|11-7 fs2=24-20 xs1=19-15\n+fsqrt.q common 010111100000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fsub.q common 0000111\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+sfence.vma common 0001001\u003c25|000000001110011\u003c0 xs2=24-20 xs1=19-15\n+sret common 00010000001000000000000001110011\u003c0\n+dret common 01111011001000000000000001110011\u003c0\n+sctrclr common 00010000010000000000000001110011\u003c0\n+mnret common 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110000\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwaddu.wv common 110100\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwaddu.wx common 110100\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwmacc.vv common 111101\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwmacc.vx common 111101\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwmaccsu.vv common 111111\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwmaccsu.vx common 111111\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwmaccu.vv common 111100\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwmaccu.vx common 111100\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwmaccus.vx common 111110\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwmul.vv common 111011\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwmul.vx common 111011\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwmulsu.vv common 111010\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwmulsu.vx common 111010\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwmulu.vv common 111000\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwmulu.vx common 111000\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwredsum.vs common 110001\u003c26|000\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwredsumu.vs common 110000\u003c26|000\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwsub.vv common 110011\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwsub.vx common 110011\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwsub.wv common 110111\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwsub.wx common 110111\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwsubu.vv common 110010\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwsubu.vx common 110010\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwsubu.wv common 110110\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwsubu.wx common 110110\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vxor.vi common 001011\u003c26|011\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 imm~=19-15 vd=11-7\n+vxor.vv common 001011\u003c26|000\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vxor.vx common 001011\u003c26|100\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vzext.vf2 common 010010\u003c26|00110010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vzext.vf4 common 010010\u003c26|00100010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vzext.vf8 common 010010\u003c26|00010010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+amoadd.d.aq 64 0000010\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.d.aqrl 64 0000011\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.d.rl 64 0000001\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.d 64 0000000\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.w.aq common 0000010\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.w.aqrl common 0000011\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.w.rl common 0000001\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.w common 0000000\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.d.aq 64 0110010\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.d.aqrl 64 0110011\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.d.rl 64 0110001\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.d 64 0110000\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.w.aq common 0110010\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.w.aqrl common 0110011\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.w.rl common 0110001\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.w common 0110000\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.d.aq 64 1010010\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.d.aqrl 64 1010011\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.d.rl 64 1010001\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.d 64 1010000\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.w.aq common 1010010\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.w.aqrl common 1010011\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.w.rl common 1010001\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.w common 1010000\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.d.aq 64 1110010\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.d.aqrl 64 1110011\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.d.rl 64 1110001\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.d 64 1110000\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.w.aq common 1110010\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.w.aqrl common 1110011\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.w.rl common 1110001\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.w common 1110000\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.d.aq 64 1000010\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.d.aqrl 64 1000011\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.d.rl 64 1000001\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.d 64 1000000\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.w.aq common 1000010\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.w.aqrl common 1000011\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.w.rl common 1000001\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.w common 1000000\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.d.aq 64 1100010\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.d.aqrl 64 1100011\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.d.rl 64 1100001\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.d 64 1100000\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.w.aq common 1100010\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.w.aqrl common 1100011\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.w.rl common 1100001\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.w common 1100000\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.d.aq 64 0100010\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.d.aqrl 64 0100011\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.d.rl 64 0100001\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.d 64 0100000\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.w.aq common 0100010\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.w.aqrl common 0100011\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.w.rl common 0100001\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.w common 0100000\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.d.aq 64 0000110\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.d.aqrl 64 0000111\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.d.rl 64 0000101\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.d 64 0000100\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.w.aq common 0000110\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.w.aqrl common 0000111\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.w.rl common 0000101\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.w common 0000100\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.d.aq 64 0010010\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.d.aqrl 64 0010011\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.d.rl 64 0010001\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.d 64 0010000\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.w.aq common 0010010\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.w.aqrl common 0010011\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.w.rl common 0010001\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.w common 0010000\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.b.aq common 0000010\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.b.aqrl common 0000011\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.b.rl common 0000001\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.b common 0000000\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.h.aq common 0000010\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.h.aqrl common 0000011\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.h.rl common 0000001\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoadd.h common 0000000\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.b.aq common 0110010\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.b.aqrl common 0110011\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.b.rl common 0110001\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.b common 0110000\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.h.aq common 0110010\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.h.aqrl common 0110011\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.h.rl common 0110001\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoand.h common 0110000\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.b.aq common 0010110\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.b.aqrl common 0010111\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.b.rl common 0010101\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.b common 0010100\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.h.aq common 0010110\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.h.aqrl common 0010111\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.h.rl common 0010101\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.h common 0010100\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.b.aq common 1010010\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.b.aqrl common 1010011\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.b.rl common 1010001\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.b common 1010000\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.h.aq common 1010010\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.h.aqrl common 1010011\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.h.rl common 1010001\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomax.h common 1010000\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.b.aq common 1110010\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.b.aqrl common 1110011\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.b.rl common 1110001\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.b common 1110000\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.h.aq common 1110010\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.h.aqrl common 1110011\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.h.rl common 1110001\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomaxu.h common 1110000\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.b.aq common 1000010\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.b.aqrl common 1000011\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.b.rl common 1000001\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.b common 1000000\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.h.aq common 1000010\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.h.aqrl common 1000011\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.h.rl common 1000001\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amomin.h common 1000000\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.b.aq common 1100010\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.b.aqrl common 1100011\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.b.rl common 1100001\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.b common 1100000\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.h.aq common 1100010\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.h.aqrl common 1100011\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.h.rl common 1100001\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amominu.h common 1100000\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.b.aq common 0100010\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.b.aqrl common 0100011\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.b.rl common 0100001\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.b common 0100000\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.h.aq common 0100010\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.h.aqrl common 0100011\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.h.rl common 0100001\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoor.h common 0100000\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.b.aq common 0000110\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.b.aqrl common 0000111\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.b.rl common 0000101\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.b common 0000100\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.h.aq common 0000110\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.h.aqrl common 0000111\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.h.rl common 0000101\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoswap.h common 0000100\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.b.aq common 0010010\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.b.aqrl common 0010011\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.b.rl common 0010001\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.b common 0010000\u003c25|000\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.h.aq common 0010010\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.h.aqrl common 0010011\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.h.rl common 0010001\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amoxor.h common 0010000\u003c25|001\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.d.aq common 0010110\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.d.aqrl common 0010111\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.d.rl common 0010101\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.d common 0010100\u003c25|011\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.q.aq 64 0010110\u003c25|100\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.q.aqrl 64 0010111\u003c25|100\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.q.rl 64 0010101\u003c25|100\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.q 64 0010100\u003c25|100\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.w.aq common 0010110\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.w.aqrl common 0010111\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.w.rl common 0010101\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+amocas.w common 0010100\u003c25|010\u003c12|0101111\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+lb.aq common 001101000000\u003c20|000\u003c12|0101111\u003c0 xs1=19-15 xd=11-7\n+lb.aqrl common 001101100000\u003c20|000\u003c12|0101111\u003c0 xs1=19-15 xd=11-7\n+ld.aq common 001101000000\u003c20|011\u003c12|0101111\u003c0 xs1=19-15 xd=11-7\n+ld.aqrl common 001101100000\u003c20|011\u003c12|0101111\u003c0 xs1=19-15 xd=11-7\n+lh.aq common 001101000000\u003c20|001\u003c12|0101111\u003c0 xs1=19-15 xd=11-7\n+lh.aqrl common 001101100000\u003c20|001\u003c12|0101111\u003c0 xs1=19-15 xd=11-7\n+lw.aq common 001101000000\u003c20|010\u003c12|0101111\u003c0 xs1=19-15 xd=11-7\n+lw.aqrl common 001101100000\u003c20|010\u003c12|0101111\u003c0 xs1=19-15 xd=11-7\n+sb.aqrl common 0011111\u003c25|000000000101111\u003c0 xs2=24-20 xs1=19-15\n+sb.rl common 0011101\u003c25|000000000101111\u003c0 xs2=24-20 xs1=19-15\n+sd.aqrl common 0011111\u003c25|011000000101111\u003c0 xs2=24-20 xs1=19-15\n+sd.rl common 0011101\u003c25|011000000101111\u003c0 xs2=24-20 xs1=19-15\n+sh.aqrl common 0011111\u003c25|001000000101111\u003c0 xs2=24-20 xs1=19-15\n+sh.rl common 0011101\u003c25|001000000101111\u003c0 xs2=24-20 xs1=19-15\n+sw.aqrl common 0011111\u003c25|010000000101111\u003c0 xs2=24-20 xs1=19-15\n+sw.rl common 0011101\u003c25|010000000101111\u003c0 xs2=24-20 xs1=19-15\n+lr.d.aq 64 00010\u003c27|00000\u003c20|011\u003c12|0101111\u003c0 aq!0=26 rl!1=25 xs1=19-15 xd=11-7\n+lr.d.aqrl 64 00010\u003c27|00000\u003c20|011\u003c12|0101111\u003c0 aq!0=26 rl!0=25 xs1=19-15 xd=11-7\n+lr.d.rl 64 00010\u003c27|00000\u003c20|011\u003c12|0101111\u003c0 aq!1=26 rl!0=25 xs1=19-15 xd=11-7\n+lr.d 64 00010\u003c27|00000\u003c20|011\u003c12|0101111\u003c0 aq!1=26 rl!1=25 xs1=19-15 xd=11-7\n+lr.w.aq common 00010\u003c27|00000\u003c20|010\u003c12|0101111\u003c0 aq!0=26 rl!1=25 xs1=19-15 xd=11-7\n+lr.w.aqrl common 00010\u003c27|00000\u003c20|010\u003c12|0101111\u003c0 aq!0=26 rl!0=25 xs1=19-15 xd=11-7\n+lr.w.rl common 00010\u003c27|00000\u003c20|010\u003c12|0101111\u003c0 aq!1=26 rl!0=25 xs1=19-15 xd=11-7\n+lr.w common 00010\u003c27|00000\u003c20|010\u003c12|0101111\u003c0 aq!1=26 rl!1=25 xs1=19-15 xd=11-7\n+sc.d.aq 64 00011\u003c27|011\u003c12|0101111\u003c0 aq!0=26 rl!1=25 xs2=24-20 xs1=19-15 xd=11-7\n+sc.d.aqrl 64 00011\u003c27|011\u003c12|0101111\u003c0 aq!0=26 rl!0=25 xs2=24-20 xs1=19-15 xd=11-7\n+sc.d.rl 64 00011\u003c27|011\u003c12|0101111\u003c0 aq!1=26 rl!0=25 xs2=24-20 xs1=19-15 xd=11-7\n+sc.d 64 00011\u003c27|011\u003c12|0101111\u003c0 aq!1=26 rl!1=25 xs2=24-20 xs1=19-15 xd=11-7\n+sc.w.aq common 00011\u003c27|010\u003c12|0101111\u003c0 aq!0=26 rl!1=25 xs2=24-20 xs1=19-15 xd=11-7\n+sc.w.aqrl common 00011\u003c27|010\u003c12|0101111\u003c0 aq!0=26 rl!0=25 xs2=24-20 xs1=19-15 xd=11-7\n+sc.w.rl common 00011\u003c27|010\u003c12|0101111\u003c0 aq!1=26 rl!0=25 xs2=24-20 xs1=19-15 xd=11-7\n+sc.w common 00011\u003c27|010\u003c12|0101111\u003c0 aq!1=26 rl!1=25 xs2=24-20 xs1=19-15 xd=11-7\n+wrs.nto common 00000000110100000000000001110011\u003c0\n+wrs.sto common 00000001110100000000000001110011\u003c0\n+add.uw 64 0000100\u003c25|000\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sh1add.uw 64 0010000\u003c25|010\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sh1add common 0010000\u003c25|010\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sh2add.uw 64 0010000\u003c25|100\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sh2add common 0010000\u003c25|100\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sh3add.uw 64 0010000\u003c25|110\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sh3add common 0010000\u003c25|110\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+slli.uw 64 000010\u003c26|001\u003c12|0011011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+clz common 011000000000\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+clzw 64 011000000000\u003c20|001\u003c12|0011011\u003c0 xs1=19-15 xd=11-7\n+cpop common 011000000010\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+cpopw 64 011000000010\u003c20|001\u003c12|0011011\u003c0 xs1=19-15 xd=11-7\n+ctz common 011000000001\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+ctzw 64 011000000001\u003c20|001\u003c12|0011011\u003c0 xs1=19-15 xd=11-7\n+max common 0000101\u003c25|110\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+maxu common 0000101\u003c25|111\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+min common 0000101\u003c25|100\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+minu common 0000101\u003c25|101\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+orc.b common 001010000111\u003c20|101\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sext.b common 011000000100\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sext.h common 011000000101\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+zext.h common,32 000010000000\u003c20|100\u003c12|0110011\u003c0 xs1=19-15 xd=11-7\n+zext.h common,64 000010000000\u003c20|100\u003c12|0111011\u003c0 xs1=19-15 xd=11-7\n+clmulr common 0000101\u003c25|010\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+brev8 common 011010000111\u003c20|101\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+pack common 0000100\u003c25|100\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+packh common 0000100\u003c25|111\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+packw 64 0000100\u003c25|100\u003c12|0111011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+unzip 32 000010001111\u003c20|101\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+zip 32 000010001111\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+xperm4 common 0010100\u003c25|010\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+xperm8 common 0010100\u003c25|100\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+bclr common 0100100\u003c25|001\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+bclri common,32 0100100\u003c25|001\u003c12|0010011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+bclri common,64 010010\u003c26|001\u003c12|0010011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+bext common 0100100\u003c25|101\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+bexti common,32 0100100\u003c25|101\u003c12|0010011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+bexti common,64 010010\u003c26|101\u003c12|0010011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+binv common 0110100\u003c25|001\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+binvi common,32 0110100\u003c25|001\u003c12|0010011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+binvi common,64 011010\u003c26|001\u003c12|0010011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+bset common 0010100\u003c25|001\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+bseti common,32 0010100\u003c25|001\u003c12|0010011\u003c0 shamt=24-20 xs1=19-15 xd=11-7\n+bseti common,64 001010\u003c26|001\u003c12|0010011\u003c0 shamt=25-20 xs1=19-15 xd=11-7\n+c.lbu common 100000\u003c10|00\u003c0 imm=5|6 xd=4-2 xs1=9-7\n+c.lh common 100001\u003c10|1\u003c6|00\u003c0 imm\u003c1=5 xd=4-2 xs1=9-7\n+c.lhu common 100001\u003c10|0\u003c6|00\u003c0 imm\u003c1=5 xd=4-2 xs1=9-7\n+c.mul common 100111\u003c10|10\u003c5|01\u003c0 xd=9-7 xs2=4-2\n+c.not common 100111\u003c10|1110101\u003c0 xd=9-7\n+c.sb common 100010\u003c10|00\u003c0 imm=5|6 xs2=4-2 xs1=9-7\n+c.sext.b common 100111\u003c10|1100101\u003c0 xd=9-7\n+c.sext.h common 100111\u003c10|1101101\u003c0 xd=9-7\n+c.sh common 100011\u003c10|0\u003c6|00\u003c0 imm\u003c1=5 xs2=4-2 xs1=9-7\n+c.zext.b common 100111\u003c10|1100001\u003c0 xd=9-7\n+c.zext.h common 100111\u003c10|1101001\u003c0 xd=9-7\n+c.zext.w 64 100111\u003c10|1110001\u003c0 xd=9-7\n+c.fld common 001\u003c13|00\u003c0 imm\u003c3=6-5|12-10 fd=4-2 xs1=9-7\n+c.fldsp common 001\u003c13|10\u003c0 imm\u003c3=4-2|12|6-5 fd=11-7\n+c.fsd common 101\u003c13|00\u003c0 imm\u003c3=6-5|12-10 fs2=4-2 xs1=9-7\n+c.fsdsp common 101\u003c13|10\u003c0 imm\u003c3=9-7|12-10 fs2=6-2\n+c.flw 32 011\u003c13|00\u003c0 imm\u003c2=5|12-10|6 fd=4-2 xs1=9-7\n+c.flwsp 32 011\u003c13|10\u003c0 imm\u003c2=3-2|12|6-4 fd=11-7\n+c.fsw 32 111\u003c13|00\u003c0 imm\u003c2=5|12-10|6 fs2=4-2 xs1=9-7\n+c.fswsp 32 111\u003c13|10\u003c0 imm\u003c2=8-7|12-9 fs2=6-2\n+c.mop.1 common 0110000010000001\u003c0\n+c.mop.11 common 0110010110000001\u003c0\n+c.mop.13 common 0110011010000001\u003c0\n+c.mop.15 common 0110011110000001\u003c0\n+c.mop.3 common 0110000110000001\u003c0\n+c.mop.5 common 0110001010000001\u003c0\n+c.mop.7 common 0110001110000001\u003c0\n+c.mop.9 common 0110010010000001\u003c0\n+cm.mva01s common 101011\u003c10|11\u003c5|10\u003c0 r1s=9-7 r2s=4-2\n+cm.mvsa01 common 101011\u003c10|01\u003c5|10\u003c0 r1s=9-7 r2s=4-2\n+cm.pop common 10111010\u003c8|10\u003c0 rlist!0!1!2!3=7-4 spimm\u003c4=3-2\n+cm.popret common 10111110\u003c8|10\u003c0 rlist!0!1!2!3=7-4 spimm\u003c4=3-2\n+cm.popretz common 10111100\u003c8|10\u003c0 rlist!0!1!2!3=7-4 spimm\u003c4=3-2\n+cm.push common 10111000\u003c8|10\u003c0 rlist!0!1!2!3=7-4 spimm=3-2\n+cm.jalt common 101000\u003c10|10\u003c0 index!0!1!2!3!4!5!6!7!8!9!10!11!12!13!14!15!16!17!18!19!20!21!22!23!24!25!26!27!28!29!30!31=9-2\n+cm.jt common 101000000\u003c7|10\u003c0 index=6-2\n+fli.s common 111100000001\u003c20|000\u003c12|1010011\u003c0 xs1=19-15 fd=11-7\n+fmaxm.s common 0010100\u003c25|011\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fminm.s common 0010100\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fround.s common 010000000100\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+froundnx.s common 010000000101\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.bf16.s common 010001001000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.s.bf16 common 010000000110\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fadd.h common 0000010\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fclass.h common 111001000000\u003c20|001\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fcvt.d.h common 010000100010\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.h.d common 010001000001\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.h.l 64 110101000010\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.h.lu 64 110101000011\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.h.s common 010001000000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.h.w common 110101000000\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.h.wu common 110101000001\u003c20|1010011\u003c0 xs1=19-15 rm=14-12 fd=11-7\n+fcvt.l.h 64 110001000010\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.lu.h 64 110001000011\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.s.h common 010000000010\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fcvt.w.h common 110001000000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fcvt.wu.h common 110001000001\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 xd=11-7\n+fdiv.h common 0001110\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+feq.h common 1010010\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fle.h common 1010010\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fleq.h common 1010010\u003c25|100\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+flh common 001\u003c12|0000111\u003c0 imm=31-20 xs1=19-15 fd=11-7\n+fli.h common 111101000001\u003c20|000\u003c12|1010011\u003c0 xs1=19-15 fd=11-7\n+flt.h common 1010010\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fltq.h common 1010010\u003c25|101\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 xd=11-7\n+fmadd.h common 10\u003c25|1000011\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmax.h common 0010110\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmaxm.h common 0010110\u003c25|011\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmin.h common 0010110\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fminm.h common 0010110\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fmsub.h common 10\u003c25|1000111\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmul.h common 0001010\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fmv.h.x common 111101000000\u003c20|000\u003c12|1010011\u003c0 xs1=19-15 fd=11-7\n+fmv.x.h common 111001000000\u003c20|000\u003c12|1010011\u003c0 fs1=19-15 xd=11-7\n+fnmadd.h common 10\u003c25|1001111\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fnmsub.h common 10\u003c25|1001011\u003c0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+fround.h common 010001000100\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+froundnx.h common 010001000101\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fsgnj.h common 0010010\u003c25|000\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsgnjn.h common 0010010\u003c25|001\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsgnjx.h common 0010010\u003c25|010\u003c12|1010011\u003c0 fs2=24-20 fs1=19-15 fd=11-7\n+fsh common 001\u003c12|0100111\u003c0 imm=31-25|11-7 xs1=19-15 fs2=24-20\n+fsqrt.h common 010111000000\u003c20|1010011\u003c0 fs1=19-15 rm=14-12 fd=11-7\n+fsub.h common 0000110\u003c25|1010011\u003c0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7\n+cbo.clean common 000000000001\u003c20|010000000001111\u003c0 xs1=19-15\n+cbo.flush common 000000000010\u003c20|010000000001111\u003c0 xs1=19-15\n+cbo.inval common 000000000000\u003c20|010000000001111\u003c0 xs1=19-15\n+prefetch.i common 00000\u003c20|110000000010011\u003c0 imm~\u003c5=31-25 xs1=19-15\n+prefetch.r common 00001\u003c20|110000000010011\u003c0 imm~\u003c5=31-25 xs1=19-15\n+prefetch.w common 00011\u003c20|110000000010011\u003c0 imm~\u003c5=31-25 xs1=19-15\n+cbo.zero common 000000000100\u003c20|010000000001111\u003c0 xs1=19-15\n+lpad common 000000010111\u003c0 imm\u003c12=31-12\n+ssamoswap.d common 01001\u003c27|011\u003c12|0101111\u003c0 aq=26-26 rl=25-25 xs2=24-20 xs1=19-15 xd=11-7\n+ssamoswap.w common 01001\u003c27|010\u003c12|0101111\u003c0 aq=26-26 rl=25-25 xs2=24-20 xs1=19-15 xd=11-7\n+sspopchk.x1 common 11001101110000001100000001110011\u003c0\n+sspopchk.x5 common 11001101110000101100000001110011\u003c0\n+sspush.x1 common 11001110000100000100000001110011\u003c0\n+sspush.x5 common 11001110010100000100000001110011\u003c0\n+ssrdp common 11001101110000000100\u003c12|1110011\u003c0 xd!0=11-7\n+czero.eqz common 0000111\u003c25|101\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+czero.nez common 0000111\u003c25|111\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+csrrc common 011\u003c12|1110011\u003c0 csr=31-20 xs1=19-15 xd=11-7\n+csrrci common 111\u003c12|1110011\u003c0 csr=31-20 imm=19-15 xd=11-7\n+csrrs common 010\u003c12|1110011\u003c0 csr=31-20 xs1=19-15 xd=11-7\n+csrrsi common 110\u003c12|1110011\u003c0 csr=31-20 imm=19-15 xd=11-7\n+csrrw common 001\u003c12|1110011\u003c0 csr=31-20 xs1=19-15 xd=11-7\n+csrrwi common 101\u003c12|1110011\u003c0 csr=31-20 imm=19-15 xd=11-7\n+fence.i common 001\u003c12|0001111\u003c0 imm=31-20 xs1=19-15 xd=11-7\n+c.ntl.all common 1001000000010110\u003c0\n+c.ntl.p1 common 1001000000001010\u003c0\n+c.ntl.pall common 1001000000001110\u003c0\n+c.ntl.s1 common 1001000000010010\u003c0\n+ntl.all common 00000000010100000000000000110011\u003c0\n+ntl.p1 common 00000000001000000000000000110011\u003c0\n+ntl.pall common 00000000001100000000000000110011\u003c0\n+ntl.s1 common 00000000010000000000000000110011\u003c0\n+pause common 00000001000000000000000000001111\u003c0\n+mop.r.0 common 100000011100\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.1 common 100000011101\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.10 common 100010011110\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.11 common 100010011111\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.12 common 100011011100\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.13 common 100011011101\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.14 common 100011011110\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.15 common 100011011111\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.16 common 110000011100\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.17 common 110000011101\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.18 common 110000011110\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.19 common 110000011111\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.2 common 100000011110\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.20 common 110001011100\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.21 common 110001011101\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.22 common 110001011110\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.23 common 110001011111\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.24 common 110010011100\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.25 common 110010011101\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.26 common 110010011110\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.27 common 110010011111\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.28 common 110011011100\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.29 common 110011011101\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.3 common 100000011111\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.30 common 110011011110\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.31 common 110011011111\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.4 common 100001011100\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.5 common 100001011101\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.6 common 100001011110\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.7 common 100001011111\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.8 common 100010011100\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.r.9 common 100010011101\u003c20|100\u003c12|1110011\u003c0 xs1=19-15 xd=11-7\n+mop.rr.0 common 1000001\u003c25|100\u003c12|1110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mop.rr.1 common 1000011\u003c25|100\u003c12|1110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mop.rr.2 common 1000101\u003c25|100\u003c12|1110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mop.rr.3 common 1000111\u003c25|100\u003c12|1110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mop.rr.4 common 1100001\u003c25|100\u003c12|1110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mop.rr.5 common 1100011\u003c25|100\u003c12|1110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mop.rr.6 common 1100101\u003c25|100\u003c12|1110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+mop.rr.7 common 1100111\u003c25|100\u003c12|1110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+aes64ks1i 64 00110001\u003c24|001\u003c12|0010011\u003c0 rnum=23-20 xs1=19-15 xd=11-7\n+aes64ks2 64 0111111\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+aes32dsi 32 10101\u003c25|000\u003c12|0110011\u003c0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7\n+aes32dsmi 32 10111\u003c25|000\u003c12|0110011\u003c0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7\n+aes64ds 64 0011101\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+aes64dsm 64 0011111\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+aes64im 64 001100000000\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+aes32esi 32 10001\u003c25|000\u003c12|0110011\u003c0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7\n+aes32esmi 32 10011\u003c25|000\u003c12|0110011\u003c0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7\n+aes64es 64 0011001\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+aes64esm 64 0011011\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sha256sig0 common 000100000010\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sha256sig1 common 000100000011\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sha256sum0 common 000100000000\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sha256sum1 common 000100000001\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sha512sig0 64 000100000110\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sha512sig0h 32 0101110\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sha512sig0l 32 0101010\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sha512sig1 64 000100000111\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sha512sig1h 32 0101111\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sha512sig1l 32 0101011\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sha512sum0 64 000100000100\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sha512sum0r 32 0101000\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sha512sum1 64 000100000101\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sha512sum1r 32 0101001\u003c25|000\u003c12|0110011\u003c0 xs2=24-20 xs1=19-15 xd=11-7\n+sm3p0 common 000100001000\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sm3p1 common 000100001001\u003c20|001\u003c12|0010011\u003c0 xs1=19-15 xd=11-7\n+sm4ed common 11000\u003c25|000\u003c12|0110011\u003c0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7\n+sm4ks common 11010\u003c25|000\u003c12|0110011\u003c0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7\n+vandn.vv common 000001\u003c26|000\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vandn.vx common 000001\u003c26|100\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vbrev.v common 010010\u003c26|01010010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vbrev8.v common 010010\u003c26|01000010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vclz.v common 010010\u003c26|01100010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vcpop.v common 010010\u003c26|01110010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vctz.v common 010010\u003c26|01101010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vrev8.v common 010010\u003c26|01001010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vrol.vv common 010101\u003c26|000\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vrol.vx common 010101\u003c26|100\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vror.vi common 01010\u003c27|011\u003c12|1010111\u003c0 imm=26|19-15 vm=25-25 vs2=24-20 vd=11-7\n+vror.vv common 010100\u003c26|000\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vror.vx common 010100\u003c26|100\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vwsll.vi common 110101\u003c26|011\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 imm=19-15 vd=11-7\n+vwsll.vv common 110101\u003c26|000\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vwsll.vx common 110101\u003c26|100\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vclmul.vv common 001100\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vclmul.vx common 001100\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vclmulh.vv common 001101\u003c26|010\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vclmulh.vx common 001101\u003c26|110\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7\n+vfncvtbf16.f.f.w common 010010\u003c26|11101001\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vfwcvtbf16.f.f.v common 010010\u003c26|01101001\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vd=11-7\n+vfwmaccbf16.vf common 111011\u003c26|101\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7\n+vfwmaccbf16.vv common 111011\u003c26|001\u003c12|1010111\u003c0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7\n+vghsh.vv common 1011001\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 vs1=19-15 vd=11-7\n+vgmul.vv common 1010001\u003c25|10001010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaesdf.vs common 1010011\u003c25|00001010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaesdf.vv common 1010001\u003c25|00001010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaesdm.vs common 1010011\u003c25|00000010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaesdm.vv common 1010001\u003c25|00000010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaesef.vs common 1010011\u003c25|00011010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaesef.vv common 1010001\u003c25|00011010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaesem.vs common 1010011\u003c25|00010010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaesem.vv common 1010001\u003c25|00010010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vaeskf1.vi common 1000101\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 imm=19-15 vd=11-7\n+vaeskf2.vi common 1010101\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 imm=19-15 vd=11-7\n+vaesz.vs common 1010011\u003c25|00111010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vsha2ch.vv common 1011101\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 vs1=19-15 vd=11-7\n+vsha2cl.vv common 1011111\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 vs1=19-15 vd=11-7\n+vsha2ms.vv common 1011011\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 vs1=19-15 vd=11-7\n+vsm3c.vi common 1010111\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 imm=19-15 vd=11-7\n+vsm3me.vv common 1000001\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 vs1=19-15 vd=11-7\n+vsm4k.vi common 1000011\u003c25|010\u003c12|1110111\u003c0 vs2=24-20 imm=19-15 vd=11-7\n+vsm4r.vs common 1010011\u003c25|10000010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+vsm4r.vv common 1010001\u003c25|10000010\u003c12|1110111\u003c0 vs2=24-20 vd=11-7\n+\ndiff --git a/arch/riscv/tools/insn_tbl.sh b/arch/riscv/tools/insn_tbl.sh\nnew file mode 100755\nindex 00000000000000..aede14c80146fa\n--- /dev/null\n+++ b/arch/riscv/tools/insn_tbl.sh\n@@ -0,0 +1,256 @@\n+#!/bin/sh\n+# SPDX-License-Identifier: GPL-2.0-only\n+#\n+# Generate riscv instruction helper header.\n+# The generated helpers for each instruction are:\n+# - riscv_insn_\u003cinsn\u003e_MASK useful to help check if arbitrary binary is \u003cinsn\u003e\n+# - riscv_insn_\u003cinsn\u003e_MATCH useful to help check if arbitrary binary is \u003cinsn\u003e\n+# - riscv_insn_\u003cinsn\u003e useful to construct \u003cinsn\u003e\n+# - riscv_insn_\u003cinsn\u003e_\u003cvar\u003e useful to extract \u003cvar\u003e from \u003cinsn\u003e\n+#\n+# Each line of the instruction table should have the following format:\n+# NAME BASE FIXED_BITS [VARIABLE_LIST]\n+# NAME instruction name\n+# BASE instruction base size (common[,(32|64)])\n+# \"common\" means the instruction is valid on both architecture sizes\n+# \"32\" or \"64\" means the instruction is valid on that size\n+# if the instruction is valid on both architectures but has unique\n+# encodings, use a 32-bit entry \"common,32\" and 64-bit entry\n+# FIXED_BITS bitfields of the fixed bits of an instruction concatenated with '|'\n+# continuous grouping of fixed bits are in the form of 'bits\u003coffset'\n+# VARIABLE_LIST a variable sized list of all variables in the instruction definition\n+# in the form of name[~][\u003cnum][!num...]=(high[-low])|...\n+# symbols after the name represent different modifiers:\n+# ~ sign extension, can only appear once\n+# \u003c left shift by 'num' amount on extraction, can only appear once\n+# ! mark 'num' as an invalid input for this variable#\n+\n+set -e\n+\n+usage() {\n+\techo \u003e\u00262 \"usage: $0 BASE INFILE OUTFILE\" \u003e\u00262\n+\techo \u003e\u00262\n+\techo \u003e\u00262 \" INFILE input instruction table\"\n+\techo \u003e\u00262 \" OUTFILE output header file\"\n+\texit 1\n+}\n+\n+if [ $# -ne 2 ]; then\n+\tusage\n+fi\n+\n+infile=\"$1\"\n+outfile=\"$2\"\n+\n+file=$(readlink -f $0)\n+\n+echo \"/* Auto-generated rv${base} header from script arch/${file#*arch/} */\" \u003e $outfile\n+\n+echo \"#ifndef RISCV_INSN_GEN_H\" \u003e\u003e $outfile\n+echo \"#define RISCV_INSN_GEN_H\" \u003e\u003e $outfile\n+echo \u003e\u003e $outfile\n+\n+printf \"#include \u003clinux/bits.h\u003e\" \u003e\u003e $outfile\n+echo \u003e\u003e $outfile\n+\n+grep -E \"^[a-z\\.0-9]+[[:space:]]+\" \"$infile\" | {\n+ while read name base fixed variables; do\n+ echo \"/* $name */\"\n+\n+ non_compressed_insn=${name##c.*}\n+ invalid_inst_functions=\"\"\n+ variable_params=\"\"\n+ constraints=\"\"\n+ match=\"\"\n+ mask=\"\"\n+ make=\"\"\n+\n+ # All compressed instructions start with \"c.\"\n+ size=${non_compressed_insn:+32};\n+ size=${size:-16};\n+\n+ # Replace all . with _\n+ formatted_inst_name=$name\n+ while [ ! ${formatted_inst_name##*.*} ]; do\n+ prefix=${formatted_inst_name%.*}\n+ suffix=${formatted_inst_name##*.}\n+ contains_dot=${formatted_inst_name##*.*}\n+ formatted_inst_name=${contains_dot:-${prefix}_${suffix}}\n+ done\n+\n+ # Collect all fixed bits of an instruction\n+ OLD_IFS=$IFS\n+ IFS='|'\n+ for segment in $fixed; do\n+ bits=${segment%\u003c*}\n+ offset=${segment#*\u003c}\n+\n+ len=${#bits}\n+\n+ mask=\"${mask} | 0b\"\n+\n+ while [ $len -gt 0 ]; do\n+ len=$((len - 1))\n+ mask=${mask}1\n+ done\n+\n+ if [ ${offset} -gt 0 ]; then\n+ s=\" \u003c\u003c ${offset}\"\n+ else\n+ s=\"\"\n+ fi\n+\n+ mask=\"${mask}${s}\"\n+\n+ match=\"${match} | 0b${bits}${s}\"\n+ done\n+ IFS=$OLD_IFS\n+\n+ # Instruction only appears in one base\n+ only_base=\n+ if [ \"${base}\" != \"${base%32}\" ]; then\n+ echo \"#if __riscv_xlen == 32\"\n+ only_base=32\n+ elif [ \"${base}\" != \"${base%64}\" ]; then\n+ echo \"#if __riscv_xlen == 64\"\n+ only_base=64\n+ fi\n+\n+ # Standard name for the instruction parameter in generated functions\n+ insn=\"_insn\"\n+\n+ for variable in ${variables}; do\n+ variable_name=\"${variable%%[\u003c~=!]*}\"\n+ parts=\"${variable#*=}\"\n+ insert_mask=\"\"\n+ sign_extend=\"\"\n+ left_shift=\"\"\n+ extract=\"\"\n+ insert=\"\"\n+\n+ # Standard name for the variable parameter in generated functions\n+ var=\"_${variable_name}\"\n+ variable_params=\"${variable_params}u32 ${var}, \"\n+\n+ if [ \"${variable}\" != \"${variable#*~}\" ]; then\n+ sign_extend=\"1\"\n+ fi\n+\n+ if [ \"${variable}\" != \"${variable#*\u003c}\" ]; then\n+ left_shift=\"${variable#*\u003c}\"\n+ left_shift=\"${left_shift%%[=\u003c~!]*}\"\n+ else\n+ left_shift=\"0\"\n+ fi\n+\n+ if [ \"${variable}\" != \"${variable#*!}\" ]; then\n+ raw_constraints=\"${variable#*!}\"\n+ raw_constraints=\"${raw_constraints%%[=\u003c~!]**}\"\n+\n+ OLD_IFS=$IFS\n+ IFS='!'\n+ for constraint in $raw_constraints; do\n+ constraints=\"${constraints}(riscv_insn_${formatted_inst_name}_extract_${variable_name}(${insn}) != ${constraint}) \u0026\u0026 \"\n+ done\n+ IFS=$OLD_IFS\n+ fi\n+\n+ offset=0\n+ while true; do\n+ part=${parts##*|}\n+\n+ if [ \"${part#*-}\" = \"${part}\" ]; then\n+ high=\"${part}\"\n+ low=\"${part}\"\n+ len=1\n+ else\n+ high=\"${part%-*}\"\n+ low=\"${part#*-}\"\n+ len=$((high - low + 1))\n+ fi\n+\n+ # Don't emit shift if 0\n+ first_shift=${low}\n+ if [ \"${first_shift}\" = \"0\" ]; then\n+ first_shift=\n+ fi\n+\n+ second_shift=$((offset + left_shift))\n+ if [ \"${second_shift}\" = \"0\" ]; then\n+ second_shift=\n+ fi\n+\n+ extract=\"${extract} | ((${insn}${first_shift:+ \u003e\u003e }${first_shift} \u0026 GENMASK($((len - 1)), 0))${second_shift:+ \u003c\u003c }${second_shift})\"\n+ insert_mask=\"${insert_mask} \u0026 ~GENMASK(${high}, ${low})\"\n+ insert=\"${insert} | (((${var}${second_shift:+ \u003e\u003e }${second_shift}) \u0026 GENMASK($((len - 1)), 0))${first_shift:+ \u003c\u003c }${first_shift})\"\n+ offset=$((offset + len))\n+\n+ if [ \"${parts}\" = \"${part}\" ]; then\n+ # Processed all parts of variable\n+ break\n+ fi\n+\n+ parts=${parts%|*}\n+ done\n+\n+ extract=\"${extract# | }\"\n+\n+ if [ ${sign_extend} ]; then\n+ extract=\"sign_extend32(${extract}, $((offset + left_shift - 1)))\"\n+ type=\"s\"\n+ else\n+ type=\"u\"\n+ fi\n+\n+ printf \"static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn})\\n\"\n+ printf \"{\\n\"\n+ printf \"\\treturn ${extract};\\n\"\n+ printf \"}\\n\"\n+ printf \"static __always_inline void riscv_insn_${formatted_inst_name}_insert_${variable_name}(u${size} *${insn}, ${type}32 ${var})\\n\"\n+ printf \"{\\n\"\n+ printf \"\\t*_insn \u0026= ${insert_mask# \u0026 };\\n\"\n+ printf \"\\t*_insn |= ${insert# | };\\n\"\n+ printf \"}\\n\"\n+\n+ if [ \"${only_base}\" ]; then\n+ invalid_inst_functions=\"${invalid_inst_functions}static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn}) {\\n\\tBUILD_BUG_ON_MSG(1, \\\"${name} is not supported on non ${only_base}-bit systems.\\\");\\n}\\n\"\n+ fi\n+\n+ make=\"${make}\triscv_insn_${formatted_inst_name}_insert_${variable_name}(\u0026${insn}, ${var});\\n\"\n+ done\n+\n+ variable_params=\"${variable_params%, }\"\n+ variable_params=\"${variable_params:-void}\"\n+\n+ printf \"#define riscv_insn_${formatted_inst_name}_MASK (${mask# | })\\n\"\n+ printf \"#define riscv_insn_${formatted_inst_name}_MATCH (${match# | })\\n\"\n+ printf \"static __always_inline u${size} riscv_insn_${formatted_inst_name}(${variable_params})\\n\"\n+ printf \"{\\n\"\n+ printf \"\\tu${size} ${insn} = riscv_insn_${formatted_inst_name}_MATCH;\\n\"\n+ printf \"${make}\treturn ${insn};\\n\"\n+ printf \"}\\n\"\n+\n+ # Check against instructions that have a variable that may contain invalid values\n+ if [ \"$constraints\" ]; then\n+ printf \"__RISCV_INSN_FUNCS_CONSTRAINED(${formatted_inst_name}, ${constraints% \u0026\u0026 });\\n\"\n+ else\n+ printf \"__RISCV_INSN_FUNCS(${formatted_inst_name});\\n\"\n+ fi\n+\n+ # If common does not appear in the base, then this instruction only appears in one base\n+ if [ \"$base\" = \"${base#common}\" ]; then\n+ printf \"#else\\n\"\n+ printf \"__RISCV_INSN_FUNCS_UNSUPPORTED(${formatted_inst_name});\\n\"\n+ printf \"${invalid_inst_functions%\\\\n}\\n\"\n+ fi\n+\n+ # Instruction has a base variant\n+ if [ \"$base\" != \"${base%[24]}\" ]; then\n+ echo \"#endif\"\n+ fi\n+\n+ echo\n+ done\n+\n+ echo \"#endif /* RISCV_INST_GEN_H */\"\n+} \u003e\u003e $outfile\ndiff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h\nindex 6c8afa2047bf33..abbbf74627a24d 100644\n--- a/include/uapi/linux/kvm.h\n+++ b/include/uapi/linux/kvm.h\n@@ -1235,6 +1235,8 @@ enum kvm_device_type {\n #define KVM_DEV_TYPE_LOONGARCH_DMSINTC\tKVM_DEV_TYPE_LOONGARCH_DMSINTC\n \tKVM_DEV_TYPE_ARM_VGIC_V5,\n #define KVM_DEV_TYPE_ARM_VGIC_V5\tKVM_DEV_TYPE_ARM_VGIC_V5\n+\tKVM_DEV_TYPE_TEST,\n+#define KVM_DEV_TYPE_TEST\t\tKVM_DEV_TYPE_TEST\n \n \tKVM_DEV_TYPE_MAX,\n \ndiff --git a/lib/Kconfig.debug b/lib/Kconfig.debug\nindex 8ff5adcfe1e0a2..0d235bdc94ec38 100644\n--- a/lib/Kconfig.debug\n+++ b/lib/Kconfig.debug\n@@ -754,6 +754,12 @@ source \"net/Kconfig.debug\"\n \n endmenu # \"Networking Debugging\"\n \n+menu \"KVM Debugging\"\n+\n+source \"virt/kvm/Kconfig.debug\"\n+\n+endmenu # \"KVM Debugging\"\n+\n menu \"Memory Debugging\"\n \n source \"mm/Kconfig.debug\"\ndiff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selftests/kvm/Makefile.kvm\nindex 9118a5a51b89fd..88ccd15e8f9415 100644\n--- a/tools/testing/selftests/kvm/Makefile.kvm\n+++ b/tools/testing/selftests/kvm/Makefile.kvm\n@@ -212,8 +212,10 @@ TEST_GEN_PROGS_s390 += s390/irq_routing\n TEST_GEN_PROGS_s390 += mmu_stress_test\n \n TEST_GEN_PROGS_riscv = $(TEST_GEN_PROGS_COMMON)\n+TEST_GEN_PROGS_riscv += riscv/csr_test\n TEST_GEN_PROGS_riscv += riscv/sbi_pmu_test\n TEST_GEN_PROGS_riscv += riscv/ebreak_test\n+TEST_GEN_PROGS_riscv += riscv/mmio_test\n TEST_GEN_PROGS_riscv += access_tracking_perf_test\n TEST_GEN_PROGS_riscv += arch_timer\n TEST_GEN_PROGS_riscv += coalesced_io_test\ndiff --git a/tools/testing/selftests/kvm/riscv/csr_test.c b/tools/testing/selftests/kvm/riscv/csr_test.c\nnew file mode 100644\nindex 00000000000000..b3e8b99b6e9236\n--- /dev/null\n+++ b/tools/testing/selftests/kvm/riscv/csr_test.c\n@@ -0,0 +1,126 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * csr_test.c - Tests the csr functionality.\n+ */\n+#include \"kvm_util.h\"\n+#include \"ucall_common.h\"\n+\n+#define CSR_TEST 0x240\n+#define FP 0x00006000\n+\n+/*\n+ * Use the fcsr as a U-mode accesible csr and compare against the custom 'test'\n+ * hypervisor csr (currently using vsscratch)\n+ */\n+#define test_csr(write, initial, mode)\t\t\t\t\t\t\t\t\\\n+static void test_##write(void)\t\t\t\t\t\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long hypervisor_result, reference_result, old_hypervisor;\t\t\t\\\n+\tunsigned long mask = 0x15;\t\t\t\t\t\t\t\t\\\n+\tasm volatile (\t\t\t\t\t\t\t\t\t\t\\\n+\t\t\"csrs\tsstatus, %[enable_fp]\\n\"\t\t\t\t\t\t\\\n+\t\t\"csrw\tfcsr, %[init]\\n\"\t\t\t\t\t\t\t\\\n+\t\t#write\"\tzero, fcsr, %[mask]\\n\"\t\t\t\t\t\t\t\\\n+\t\t\"csrr\t%[ref_res], fcsr\\n\"\t\t\t\t\t\t\t\\\n+\t\t: [ref_res] \"=\u0026r\" (reference_result)\t\t\t\t\t\t\\\n+\t\t: [enable_fp] \"r\" (FP), [mask] #mode(mask), [init] \"r\" (initial)\t\t\\\n+\t\t: \"memory\"\t\t\t\t\t\t\t\t\t\\\n+\t);\t\t\t\t\t\t\t\t\t\t\t\\\n+\tasm volatile (\t\t\t\t\t\t\t\t\t\t\\\n+\t\t\"csrw\t%[test_csr], %[init]\\n\"\t\t\t\t\t\t\t\\\n+\t\t#write\"\t%[old], %[test_csr], %[mask]\\n\"\t\t\t\t\t\t\\\n+\t\t\"csrr\t%[hyp_res], %[test_csr]\\n\"\t\t\t\t\t\t\\\n+\t\t: [hyp_res] \"=\u0026r\" (hypervisor_result), [old] \"=\u0026r\" (old_hypervisor)\t\t\\\n+\t\t: [test_csr] \"i\"(CSR_TEST), [mask] #mode(mask), [init] \"r\" (initial)\t\t\\\n+\t\t: \"memory\"\t\t\t\t\t\t\t\t\t\\\n+\t);\t\t\t\t\t\t\t\t\t\t\t\\\n+\t/* Check that writing works */\t\t\t\t\t\t\t\t\\\n+\tGUEST_ASSERT_EQ(reference_result, hypervisor_result);\t\t\t\t\t\\\n+\t/* Check that reading works */\t\t\t\t\t\t\t\t\\\n+\tGUEST_ASSERT_EQ(old_hypervisor, initial);\t\t\t\t\t\t\\\n+\tGUEST_DONE();\t\t\t\t\t\t\t\t\t\t\\\n+}\n+\n+test_csr(csrrw, 0x0, r)\n+test_csr(csrrs, 0x0, r)\n+test_csr(csrrc, 0x15, r)\n+test_csr(csrrwi, 0x0, i)\n+test_csr(csrrsi, 0x0, i)\n+test_csr(csrrci, 0x15, i)\n+\n+static void run(void *guest_code, char *instruction)\n+{\n+\tstruct ucall uc;\n+\tstruct kvm_vm *vm;\n+\tstruct kvm_vcpu *vcpu;\n+\n+\tvm = vm_create_with_one_vcpu(\u0026vcpu, guest_code);\n+\n+\tkvm_create_device(vm, KVM_DEV_TYPE_TEST);\n+\n+\tvcpu_run(vcpu);\n+\n+\tTEST_ASSERT(get_ucall(vcpu, \u0026uc) == UCALL_DONE,\n+\t\t \"CSR instruction '%s' failed: '%s'\", instruction,\n+\t\t uc.buffer);\n+\n+\tkvm_vm_free(vm);\n+}\n+\n+static void check_test_csr_guest(void)\n+{\n+\tunsigned long scause, stvec;\n+\n+\tasm volatile(\n+\t\t\"la\t%[stvec], 1f\\n\"\n+\t\t\"csrw\tstvec, %[stvec]\\n\"\n+\t\t\"csrwi\t%[test_csr], 0x0\\n\"\n+\t\t\"1:\\n\"\n+\t\t\"csrr\t%[scause], scause\\n\"\n+\t\t: [scause] \"=\u0026r\" (scause), [stvec] \"=\u0026r\" (stvec)\n+\t\t: [test_csr] \"i\" (CSR_TEST)\n+\t);\n+\n+\t/* An illegal instruction will be generated if CONFIG_RISCV_KVM_TEST_CSR is not enabled. */\n+\tif (scause == 2)\n+\t\tGUEST_FAIL(\"CONFIG_RISCV_KVM_TEST_CSR not enabled.\\n\");\n+\tGUEST_DONE();\n+}\n+\n+static int check_test_csr(void)\n+{\n+\tstruct ucall uc;\n+\tstruct kvm_vm *vm;\n+\tstruct kvm_vcpu *vcpu;\n+\tint success;\n+\n+\tvm = vm_create_with_one_vcpu(\u0026vcpu, check_test_csr_guest);\n+\n+\t/* Skip if CONFIG_KVM_MMIO_TEST not enabled */\n+\tif (!kvm_create_device(vm, KVM_DEV_TYPE_TEST))\n+\t\texit(KSFT_SKIP);\n+\n+\tvcpu_run(vcpu);\n+\n+\tsuccess = get_ucall(vcpu, \u0026uc) == UCALL_DONE;\n+\n+\tkvm_vm_free(vm);\n+\n+\treturn success;\n+}\n+\n+int main(void)\n+{\n+\t/* Skip if CONFIG_RISCV_KVM_TEST_CSR not enabled */\n+\tif (!check_test_csr())\n+\t\texit(KSFT_SKIP);\n+\n+\trun(test_csrrw, \"csrrw\");\n+\trun(test_csrrs, \"csrrs\");\n+\trun(test_csrrc, \"csrrc\");\n+\trun(test_csrrwi, \"csrrwi\");\n+\trun(test_csrrsi, \"csrrsi\");\n+\trun(test_csrrci, \"csrrci\");\n+\n+\treturn 0;\n+}\ndiff --git a/tools/testing/selftests/kvm/riscv/mmio_test.c b/tools/testing/selftests/kvm/riscv/mmio_test.c\nnew file mode 100644\nindex 00000000000000..9726860a269a3f\n--- /dev/null\n+++ b/tools/testing/selftests/kvm/riscv/mmio_test.c\n@@ -0,0 +1,184 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * mmio_test.c - Tests the mmio functionality.\n+ */\n+#include \"kvm_util.h\"\n+#include \"ucall_common.h\"\n+\n+#define MMIO_TEST_REGION 0x20000000\n+\n+#define test_standard_read(len, instruction, name, options)\t\t\t\t\t\\\n+static void test_##name(void)\t\t\t\t\t\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long mmio_result, reference_result;\t\t\t\t\t\t\\\n+\t/* Configure the MMIO to return 0xff for each byte to check sign extension */\t\t\\\n+\tunsigned long reference = ((unsigned long)-1 \u003e\u003e ((sizeof(long) - len) * 8));\t\t\\\n+\t*((unsigned long *)MMIO_TEST_REGION) = reference;\t\t\t\t\t\\\n+\t/* Check that reads through MMIO are equivalent to standard reads. */\t\t\t\\\n+\tasm volatile (\t\t\t\t\t\t\t\t\t\t\\\n+\t\t\".option push\\n\"\t\t\t\t\t\t\t\t\\\n+\t\toptions\t\t\t\t\t\t\t\t\t\t\\\n+\t\t#instruction \"\t%[mmio_res], 0(%[region])\\n\"\t\t\t\t\t\\\n+\t\t#instruction \"\t%[ref_res], 0(%[ref])\\n\"\t\t\t\t\t\\\n+\t\t\".option pop\\n\"\t\t\t\t\t\t\t\t\t\\\n+\t\t: [mmio_res] \"=\u0026cr\" (mmio_result), [ref_res] \"=\u0026cr\" (reference_result)\t\t\\\n+\t\t: [region] \"cr\" (MMIO_TEST_REGION), [ref] \"cr\" (\u0026reference)\t\t\t\\\n+\t);\t\t\t\t\t\t\t\t\t\t\t\\\n+\tGUEST_ASSERT_EQ(mmio_result, reference_result);\t\t\t\t\t\t\\\n+\tGUEST_DONE();\t\t\t\t\t\t\t\t\t\t\\\n+}\n+\n+#define test_sp_read(len, instruction, name)\t\t\t\t\t\t\t\\\n+static void test_##name(void)\t\t\t\t\t\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long mmio_result, reference_result;\t\t\t\t\t\t\\\n+\tunsigned long tmp;\t\t\t\t\t\t\t\t\t\\\n+\t/* Configure the MMIO to return 0xff for each byte to check sign extension */\t\t\\\n+\tunsigned long reference = ((unsigned long)-1 \u003e\u003e ((sizeof(long) - len) * 8));\t\t\\\n+\t*(((unsigned long *)MMIO_TEST_REGION)) = reference;\t\t\t\t\t\\\n+\t/* Check that reads through MMIO are equivalent to standard reads. */\t\t\t\\\n+\tasm volatile (\t\t\t\t\t\t\t\t\t\t\\\n+\t\t\"mv\t%[tmp], sp\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t\"mv\tsp, %[region]\\n\"\t\t\t\t\t\t\t\\\n+\t\t\".option push\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t\".option arch,+c\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t#instruction \"\t%[mmio_res], 0(sp)\\n\"\t\t\t\t\t\t\\\n+\t\t\"mv\tsp, %[ref]\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t#instruction \"\t%[ref_res], 0(sp)\\n\"\t\t\t\t\t\t\\\n+\t\t\".option pop\\n\"\t\t\t\t\t\t\t\t\t\\\n+\t\t\"mv\tsp, %[tmp]\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t: [mmio_res] \"=\u0026cr\" (mmio_result), [ref_res] \"=\u0026cr\" (reference_result),\t\\\n+\t\t [tmp] \"=\u0026r\" (tmp)\t\t\t\t\t\t\t\t\\\n+\t\t: [region] \"r\" (MMIO_TEST_REGION), [ref] \"cr\" (\u0026reference)\t\t\t\\\n+\t);\t\t\t\t\t\t\t\t\t\t\t\\\n+\tGUEST_ASSERT_EQ(mmio_result, reference_result);\t\t\t\t\t\t\\\n+\tGUEST_DONE();\t\t\t\t\t\t\t\t\t\t\\\n+}\n+\n+test_standard_read(1, lb, lb, \"\")\n+test_standard_read(1, lbu, lbu, \"\")\n+test_standard_read(4, lw, lw, \"\")\n+test_standard_read(4, c.lw, c_lw, \".option arch,+c\\n\")\n+test_sp_read(4, c.lwsp, c_lwsp)\n+\n+#if __riscv_xlen == 64\n+test_standard_read(2, lh, lh, \"\")\n+test_standard_read(2, lhu, lhu, \"\")\n+test_standard_read(4, lwu, lwu, \"\")\n+test_standard_read(8, ld, ld, \"\")\n+test_standard_read(8, c.ld, c_ld, \".option arch,+c\\n\")\n+test_sp_read(8, c.ldsp, c_ldsp)\n+#endif\n+\n+#define test_standard_write(len, write, read, name, options)\t\t\t\t\t\\\n+static void test_##name(void)\t\t\t\t\t\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long result;\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long reference = (0x55555555UL \u003e\u003e ((sizeof(long) - len) * 8));\t\t\t\\\n+\t/* Check that we can write and then read the same value. */\t\t\t\t\\\n+\tasm volatile (\t\t\t\t\t\t\t\t\t\t\\\n+\t\t\".option push\\n\"\t\t\t\t\t\t\t\t\\\n+\t\toptions\t\t\t\t\t\t\t\t\t\t\\\n+\t\t#write \"\t%[ref], 0(%[region])\\n\"\t\t\t\t\t\t\\\n+\t\t#read \"\t\t%[res], 0(%[region])\\n\"\t\t\t\t\t\t\\\n+\t\t\".option pop\\n\"\t\t\t\t\t\t\t\t\t\\\n+\t\t: [res] \"=\u0026cr\" (result)\t\t\t\t\t\t\t\t\\\n+\t\t: [region] \"cr\" (MMIO_TEST_REGION), [ref] \"cr\" (reference)\t\t\t\\\n+\t);\t\t\t\t\t\t\t\t\t\t\t\\\n+\tGUEST_ASSERT_EQ(result, reference);\t\t\t\t\t\t\t\\\n+\tGUEST_DONE();\t\t\t\t\t\t\t\t\t\t\\\n+}\n+\n+#define test_sp_write(len, write, read, name)\t\t\t\t\t\t\t\\\n+static void test_##name(void)\t\t\t\t\t\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long result;\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long tmp;\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long reference = (0x55555555UL \u003e\u003e ((sizeof(long) - len) * 8));\t\t\t\\\n+\t/* Check that we can write and then read the same value. */\t\t\t\t\\\n+\tasm volatile (\t\t\t\t\t\t\t\t\t\t\\\n+\t\t\"mv\t%[tmp], sp\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t\"mv\tsp, %[region]\\n\"\t\t\t\t\t\t\t\\\n+\t\t\".option push\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t\".option arch,+c\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t#write \"\t%[ref], 0(sp)\\n\"\t\t\t\t\t\t\\\n+\t\t#read \"\t\t%[res], 0(sp)\\n\"\t\t\t\t\t\t\\\n+\t\t\".option pop\\n\"\t\t\t\t\t\t\t\t\t\\\n+\t\t\"mv\tsp, %[tmp]\\n\"\t\t\t\t\t\t\t\t\\\n+\t\t: [res] \"=\u0026cr\" (result), [tmp] \"=\u0026r\" (tmp)\t\t\t\t\t\\\n+\t\t: [region] \"cr\" (MMIO_TEST_REGION), [ref] \"cr\" (reference)\t\t\t\\\n+\t);\t\t\t\t\t\t\t\t\t\t\t\\\n+\tGUEST_ASSERT_EQ(result, reference);\t\t\t\t\t\t\t\\\n+\tGUEST_DONE();\t\t\t\t\t\t\t\t\t\t\\\n+}\n+\n+test_standard_write(1, sb, lb, sb, \"\")\n+test_standard_write(2, sh, lh, sh, \"\")\n+test_standard_write(4, sw, lw, sw, \"\")\n+test_standard_write(4, c.sw, c.lw, c_sw, \".option arch,+c\\n\")\n+test_sp_write(4, c.swsp, c.lwsp, c_swsp)\n+\n+#if __riscv_xlen == 64\n+test_standard_write(8, sd, ld, sd, \"\")\n+test_standard_write(8, c.sd, c.ld, c_sd, \".option arch,+c\\n\")\n+#endif\n+\n+static void run(void *guest_code, char *instruction)\n+{\n+\tstruct ucall uc;\n+\tstruct kvm_vm *vm;\n+\tstruct kvm_vcpu *vcpu;\n+\n+\tvm = vm_create_with_one_vcpu(\u0026vcpu, guest_code);\n+\tkvm_create_device(vm, KVM_DEV_TYPE_TEST);\n+\n+\tvirt_map(vm, (unsigned long)MMIO_TEST_REGION, MMIO_TEST_REGION, 1);\n+\n+\tvcpu_run(vcpu);\n+\n+\tTEST_ASSERT(get_ucall(vcpu, \u0026uc) == UCALL_DONE,\n+\t\t \"MMIO with instruction '%s' failed: '%s'\", instruction,\n+\t\t uc.buffer);\n+\n+\tkvm_vm_free(vm);\n+}\n+\n+void test_mmio_read_sign_extension(void)\n+{\n+\trun(test_lb, \"lb\");\n+\trun(test_lbu, \"lbu\");\n+\trun(test_lw, \"lw\");\n+\trun(test_c_lw, \"c.lw\");\n+\trun(test_c_lwsp, \"c.lwsp\");\n+\n+#if __riscv_xlen == 64\n+\trun(test_lh, \"lh\");\n+\trun(test_lhu, \"lhu\");\n+\trun(test_lwu, \"lwu\");\n+\trun(test_ld, \"ld\");\n+\trun(test_c_ld, \"c.ld\");\n+\trun(test_c_ldsp, \"c.ldsp\");\n+#endif\n+}\n+\n+void test_mmio_write(void)\n+{\n+\trun(test_sb, \"sb\");\n+\trun(test_sh, \"sh\");\n+\trun(test_sw, \"sw\");\n+\trun(test_c_sw, \"c.sw\");\n+\trun(test_c_swsp, \"c.swsp\");\n+\n+#if __riscv_xlen == 64\n+\trun(test_sd, \"sd\");\n+\trun(test_c_sd, \"c.sd\");\n+#endif\n+}\n+\n+int main(void)\n+{\n+\ttest_mmio_read_sign_extension();\n+\ttest_mmio_write();\n+\n+\treturn 0;\n+}\ndiff --git a/virt/kvm/Kconfig.debug b/virt/kvm/Kconfig.debug\nnew file mode 100644\nindex 00000000000000..d24709f5bcbffc\n--- /dev/null\n+++ b/virt/kvm/Kconfig.debug\n@@ -0,0 +1,16 @@\n+# SPDX-License-Identifier: GPL-2.0-only\n+\n+config KVM_MMIO_TEST\n+ bool \"Enable kvm mmio testing\"\n+ depends on KVM\n+ depends on KVM_MMIO\n+ default n\n+ help\n+ Enable testing for kvm mmio. This is a test-only mmio device that\n+ stores writes in a buffer and returns the buffered data on a read.\n+ \n+ This is useful for testing the kvm mmio emulation code. Enabling\n+ this does not run any tests, just builds in the support for the test\n+ device into the kernel.\n+\n+ If unsure, say N.\ndiff --git a/virt/kvm/Makefile.kvm b/virt/kvm/Makefile.kvm\nindex d047d4cf58c9fd..bd4da8c2392346 100644\n--- a/virt/kvm/Makefile.kvm\n+++ b/virt/kvm/Makefile.kvm\n@@ -8,6 +8,7 @@ KVM ?= ../../../virt/kvm\n kvm-y := $(KVM)/kvm_main.o $(KVM)/eventfd.o $(KVM)/binary_stats.o\n kvm-$(CONFIG_KVM_VFIO) += $(KVM)/vfio.o\n kvm-$(CONFIG_KVM_MMIO) += $(KVM)/coalesced_mmio.o\n+kvm-$(CONFIG_KVM_MMIO_TEST) += $(KVM)/mmio_test.o\n kvm-$(CONFIG_KVM_ASYNC_PF) += $(KVM)/async_pf.o\n kvm-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o\n kvm-$(CONFIG_HAVE_KVM_DIRTY_RING) += $(KVM)/dirty_ring.o\ndiff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c\nindex 881f92d7a469e7..d9bbe570eddd55 100644\n--- a/virt/kvm/kvm_main.c\n+++ b/virt/kvm/kvm_main.c\n@@ -58,6 +58,7 @@\n #include \"async_pf.h\"\n #include \"kvm_mm.h\"\n #include \"vfio.h\"\n+#include \"mmio_test.h\"\n \n #include \u003ctrace/events/ipi.h\u003e\n \n@@ -6532,6 +6533,10 @@ int kvm_init(unsigned vcpu_size, unsigned vcpu_align, struct module *module)\n \tif (WARN_ON_ONCE(r))\n \t\tgoto err_vfio;\n \n+\tr = kvm_mmio_test_ops_init();\n+\tif (WARN_ON_ONCE(r))\n+\t\tgoto err_mmio_test;\n+\n \tr = kvm_gmem_init(module);\n \tif (r)\n \t\tgoto err_gmem;\n@@ -6559,6 +6564,8 @@ int kvm_init(unsigned vcpu_size, unsigned vcpu_align, struct module *module)\n err_gmem:\n \tkvm_vfio_ops_exit();\n err_vfio:\n+\tkvm_mmio_test_ops_exit();\n+err_mmio_test:\n \tkvm_async_pf_deinit();\n err_async_pf:\n \tkvm_irqfd_exit();\n@@ -6589,6 +6596,7 @@ void kvm_exit(void)\n \t\tfree_cpumask_var(per_cpu(cpu_kick_mask, cpu));\n \tkmem_cache_destroy(kvm_vcpu_cache);\n \tkvm_gmem_exit();\n+\tkvm_mmio_test_ops_exit();\n \tkvm_vfio_ops_exit();\n \tkvm_async_pf_deinit();\n \tkvm_irqfd_exit();\ndiff --git a/virt/kvm/mmio_test.c b/virt/kvm/mmio_test.c\nnew file mode 100644\nindex 00000000000000..fa84c2b4c5fcfe\n--- /dev/null\n+++ b/virt/kvm/mmio_test.c\n@@ -0,0 +1,95 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * mmio_test.c - Kernel module side for testing the KVM riscv mmio functionality.\n+ */\n+\n+#include \u003clinux/kvm_host.h\u003e\n+\n+#include \u003ckvm/iodev.h\u003e\n+#include \"mmio_test.h\"\n+\n+struct mmio_test {\n+\tstruct kvm *kvm;\n+\tstruct kvm_io_device dev;\n+\tunsigned long start;\n+\tunsigned long size;\n+\tchar cache[16];\n+};\n+\n+static struct mmio_test *kvm_to_mmio_test_dev(const struct kvm_io_device *dev)\n+{\n+\treturn container_of(dev, struct mmio_test, dev);\n+}\n+\n+static int mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,\n+\t\t gpa_t addr, int len, void *val)\n+{\n+\tstruct mmio_test *mmio_test = kvm_to_mmio_test_dev(dev);\n+\n+\tif ((addr - mmio_test-\u003estart) \u003e= mmio_test-\u003esize)\n+\t\treturn -1;\n+\n+\t/* Write back cached value */\n+\tmemcpy(val, \u0026mmio_test-\u003ecache[(addr - mmio_test-\u003estart)], len);\n+\treturn 0;\n+}\n+\n+static int mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,\n+\t\t gpa_t addr, int len, const void *val)\n+{\n+\tstruct mmio_test *mmio_test = kvm_to_mmio_test_dev(dev);\n+\n+\tif ((addr - mmio_test-\u003estart) \u003e= mmio_test-\u003esize)\n+\t\treturn -1;\n+\n+\t/* Cache value */\n+\tmemcpy(\u0026mmio_test-\u003ecache[(addr - mmio_test-\u003estart)], val, len);\n+\treturn 0;\n+}\n+\n+static const struct kvm_io_device_ops mmio_ops = {\n+\t.read = mmio_read,\n+\t.write = mmio_write,\n+};\n+\n+static int mmio_test_create(struct kvm_device *dev, u32 type)\n+{\n+\tstruct mmio_test *mmio_test;\n+\n+\tmmio_test = kzalloc(sizeof(*mmio_test), GFP_KERNEL);\n+\tif (!mmio_test)\n+\t\treturn -ENOMEM;\n+\n+\tmmio_test-\u003estart = 0x20000000;\n+\tmmio_test-\u003esize = 0x16;\n+\n+\tdev-\u003eprivate = mmio_test;\n+\n+\tkvm_iodevice_init(\u0026mmio_test-\u003edev, \u0026mmio_ops);\n+\tkvm_io_bus_register_dev(dev-\u003ekvm, KVM_MMIO_BUS, mmio_test-\u003estart,\n+\t\t\t\tmmio_test-\u003esize, \u0026mmio_test-\u003edev);\n+\n+\treturn 0;\n+}\n+\n+static void mmio_test_release(struct kvm_device *dev)\n+{\n+\tkfree(dev-\u003eprivate);\n+}\n+\n+struct kvm_device_ops kvm_riscv_mmio_test_device_ops = {\n+\t.name = \"kvm-riscv-mmio_test\",\n+\t.create = mmio_test_create,\n+\t.release = mmio_test_release,\n+};\n+\n+int kvm_mmio_test_ops_init(void)\n+{\n+\treturn kvm_register_device_ops(\u0026kvm_riscv_mmio_test_device_ops,\n+\t\t\t\t\tKVM_DEV_TYPE_TEST);\n+}\n+\n+void kvm_mmio_test_ops_exit(void)\n+{\n+\tkvm_unregister_device_ops(KVM_DEV_TYPE_TEST);\n+}\ndiff --git a/virt/kvm/mmio_test.h b/virt/kvm/mmio_test.h\nnew file mode 100644\nindex 00000000000000..49a6e900eec9ab\n--- /dev/null\n+++ b/virt/kvm/mmio_test.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+#ifndef __KVM_MMIO_TEST_H\n+#define __KVM_MMIO_TEST_H\n+\n+#ifdef CONFIG_KVM_MMIO_TEST\n+int kvm_mmio_test_ops_init(void);\n+void kvm_mmio_test_ops_exit(void);\n+#else\n+static inline int kvm_mmio_test_ops_init(void)\n+{\n+\treturn 0;\n+}\n+static inline void kvm_mmio_test_ops_exit(void)\n+{\n+}\n+#endif\n+\n+#endif\n"
} |
| 2/1 | 2026/06/22 04:18 | agent | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: {
"EnableConfigs": null,
"FocusSymbols": [
"handle_scalar_misaligned_load",
"handle_scalar_misaligned_store",
"kvm_riscv_vcpu_mmio_load",
"kvm_riscv_vcpu_mmio_store",
"csr_insn",
"get_step_address",
"riscv_alternative_fix_auipc_jalr",
"decode_cfi_insn",
"simulate_jal",
"simulate_jalr",
"simulate_auipc",
"simulate_beq",
"simulate_bne",
"simulate_blt",
"simulate_bge",
"simulate_bltu",
"simulate_bgeu",
"simulate_c_j",
"simulate_c_jr",
"simulate_c_jalr",
"simulate_c_bnez",
"simulate_c_beqz"
],
"Reasoning": "The patch refactors RISC-V instruction decoding and encoding across core kernel subsystems including KVM, Kprobes, KGDB, alternative patching, and misaligned trap handling. These changes modify reachable core logic and should be fuzzed to ensure instruction decoding correctness.",
"WorthFuzzing": true
}Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Do not list too generic configs (we already have them enabled). Only list those that specifically cover the modified code. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes:
commit 4a3bc94d033b3e483aba144516c48bbef82e9be3
Author: syz-cluster <triage@syzkaller.com>
Date: Mon Jun 22 04:18:45 2026 +0000
syz-cluster: applied patch under review
diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug
index eafe17ebf7102c..be202267da6db9 100644
--- a/arch/riscv/Kconfig.debug
+++ b/arch/riscv/Kconfig.debug
@@ -1 +1,2 @@
source "arch/riscv/kernel/tests/Kconfig.debug"
+source "arch/riscv/kvm/Kconfig.debug"
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index ce0cc737f87096..d14caa8720f858 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -176,6 +176,9 @@ BOOT_TARGETS := Image Image.gz Image.bz2 Image.lz4 Image.lzma Image.lzo Image.zs
all: $(notdir $(KBUILD_IMAGE))
+archprepare:
+ $(Q)$(MAKE) $(build)=arch/riscv/tools insn
+
loader.bin: loader
Image.gz Image.bz2 Image.lz4 Image.lzma Image.lzo Image.zst Image.xz loader xipImage vmlinuz.efi: Image
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 7721b63642f413..16be4de3d0b1ec 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -2,6 +2,7 @@
syscall-y += syscall_table_32.h
syscall-y += syscall_table_64.h
+generated-y += insn_gen.h
generic-y += early_ioremap.h
generic-y += flat.h
generic-y += fprobe.h
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index c3005573e8c999..ea1f139d6d9047 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -8,151 +8,52 @@
#include <linux/bits.h>
-#define RV_INSN_FUNCT3_MASK GENMASK(14, 12)
-#define RV_INSN_FUNCT3_OPOFF 12
-#define RV_INSN_OPCODE_MASK GENMASK(6, 0)
-#define RV_INSN_OPCODE_OPOFF 0
-#define RV_INSN_FUNCT12_OPOFF 20
-
-#define RV_ENCODE_FUNCT3(f_) (RVG_FUNCT3_##f_ << RV_INSN_FUNCT3_OPOFF)
-#define RV_ENCODE_FUNCT12(f_) (RVG_FUNCT12_##f_ << RV_INSN_FUNCT12_OPOFF)
-
-/* The bit field of immediate value in I-type instruction */
-#define RV_I_IMM_SIGN_OPOFF 31
-#define RV_I_IMM_11_0_OPOFF 20
-#define RV_I_IMM_SIGN_OFF 12
-#define RV_I_IMM_11_0_OFF 0
-#define RV_I_IMM_11_0_MASK GENMASK(11, 0)
-
-/* The bit field of immediate value in J-type instruction */
-#define RV_J_IMM_SIGN_OPOFF 31
-#define RV_J_IMM_10_1_OPOFF 21
-#define RV_J_IMM_11_OPOFF 20
-#define RV_J_IMM_19_12_OPOFF 12
-#define RV_J_IMM_SIGN_OFF 20
-#define RV_J_IMM_10_1_OFF 1
-#define RV_J_IMM_11_OFF 11
-#define RV_J_IMM_19_12_OFF 12
-#define RV_J_IMM_10_1_MASK GENMASK(9, 0)
-#define RV_J_IMM_11_MASK GENMASK(0, 0)
-#define RV_J_IMM_19_12_MASK GENMASK(7, 0)
-
/*
- * U-type IMMs contain the upper 20bits [31:20] of an immediate with
- * the rest filled in by zeros, so no shifting required. Similarly,
- * bit31 contains the signed state, so no sign extension necessary.
+ * Generate a function to check if a sequence of bits matches an instruction
*/
-#define RV_U_IMM_SIGN_OPOFF 31
-#define RV_U_IMM_31_12_OPOFF 0
-#define RV_U_IMM_31_12_MASK GENMASK(31, 12)
-
-/* The bit field of immediate value in B-type instruction */
-#define RV_B_IMM_SIGN_OPOFF 31
-#define RV_B_IMM_10_5_OPOFF 25
-#define RV_B_IMM_4_1_OPOFF 8
-#define RV_B_IMM_11_OPOFF 7
-#define RV_B_IMM_SIGN_OFF 12
-#define RV_B_IMM_10_5_OFF 5
-#define RV_B_IMM_4_1_OFF 1
-#define RV_B_IMM_11_OFF 11
-#define RV_B_IMM_10_5_MASK GENMASK(5, 0)
-#define RV_B_IMM_4_1_MASK GENMASK(3, 0)
-#define RV_B_IMM_11_MASK GENMASK(0, 0)
-
-/* The register offset in RVG instruction */
-#define RVG_RS1_OPOFF 15
-#define RVG_RS2_OPOFF 20
-#define RVG_RD_OPOFF 7
-#define RVG_RS1_MASK GENMASK(4, 0)
-#define RVG_RS2_MASK GENMASK(4, 0)
-#define RVG_RD_MASK GENMASK(4, 0)
-
-/* The bit field of immediate value in RVC J instruction */
-#define RVC_J_IMM_SIGN_OPOFF 12
-#define RVC_J_IMM_4_OPOFF 11
-#define RVC_J_IMM_9_8_OPOFF 9
-#define RVC_J_IMM_10_OPOFF 8
-#define RVC_J_IMM_6_OPOFF 7
-#define RVC_J_IMM_7_OPOFF 6
-#define RVC_J_IMM_3_1_OPOFF 3
-#define RVC_J_IMM_5_OPOFF 2
-#define RVC_J_IMM_SIGN_OFF 11
-#define RVC_J_IMM_4_OFF 4
-#define RVC_J_IMM_9_8_OFF 8
-#define RVC_J_IMM_10_OFF 10
-#define RVC_J_IMM_6_OFF 6
-#define RVC_J_IMM_7_OFF 7
-#define RVC_J_IMM_3_1_OFF 1
-#define RVC_J_IMM_5_OFF 5
-#define RVC_J_IMM_4_MASK GENMASK(0, 0)
-#define RVC_J_IMM_9_8_MASK GENMASK(1, 0)
-#define RVC_J_IMM_10_MASK GENMASK(0, 0)
-#define RVC_J_IMM_6_MASK GENMASK(0, 0)
-#define RVC_J_IMM_7_MASK GENMASK(0, 0)
-#define RVC_J_IMM_3_1_MASK GENMASK(2, 0)
-#define RVC_J_IMM_5_MASK GENMASK(0, 0)
-
-/* The bit field of immediate value in RVC B instruction */
-#define RVC_B_IMM_SIGN_OPOFF 12
-#define RVC_B_IMM_4_3_OPOFF 10
-#define RVC_B_IMM_7_6_OPOFF 5
-#define RVC_B_IMM_2_1_OPOFF 3
-#define RVC_B_IMM_5_OPOFF 2
-#define RVC_B_IMM_SIGN_OFF 8
-#define RVC_B_IMM_4_3_OFF 3
-#define RVC_B_IMM_7_6_OFF 6
-#define RVC_B_IMM_2_1_OFF 1
-#define RVC_B_IMM_5_OFF 5
-#define RVC_B_IMM_4_3_MASK GENMASK(1, 0)
-#define RVC_B_IMM_7_6_MASK GENMASK(1, 0)
-#define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
-#define RVC_B_IMM_5_MASK GENMASK(0, 0)
+#define __RISCV_INSN_FUNCS(name) \
+static __always_inline bool riscv_insn_is_##name(u32 _insn) \
+{ \
+ BUILD_BUG_ON(~(riscv_insn_##name##_MASK) & (riscv_insn_##name##_MATCH)); \
+ return (_insn & (riscv_insn_##name##_MASK)) == (riscv_insn_##name##_MATCH); \
+}
-#define RVC_INSN_FUNCT4_MASK GENMASK(15, 12)
-#define RVC_INSN_FUNCT4_OPOFF 12
-#define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)
-#define RVC_INSN_FUNCT3_OPOFF 13
-#define RVC_INSN_J_RS1_MASK GENMASK(11, 7)
-#define RVC_INSN_J_RS2_MASK GENMASK(6, 2)
-#define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
-#define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
-#define RVC_ENCODE_FUNCT4(f_) (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF)
+/*
+ * Generate a function to check if a sequence of bits matches an instruction
+ * with constraints. Some instructions require inputs to be specific values.
+ */
+#define __RISCV_INSN_FUNCS_CONSTRAINED(name, constraints) \
+static __always_inline bool riscv_insn_is_##name(u32 _insn) \
+{ \
+ BUILD_BUG_ON(~(riscv_insn_##name##_MASK) & (riscv_insn_##name##_MATCH)); \
+ return ((_insn & (riscv_insn_##name##_MASK)) == (riscv_insn_##name##_MATCH)) && \
+ (constraints); \
+}
-/* The register offset in RVC op=C0 instruction */
-#define RVC_C0_RS1_OPOFF 7
-#define RVC_C0_RS2_OPOFF 2
-#define RVC_C0_RD_OPOFF 2
+#define __RISCV_INSN_FUNCS_UNSUPPORTED(name) \
+static __always_inline bool riscv_insn_is_##name(u32 _insn) \
+{ \
+ return 0; \
+}
-/* The register offset in RVC op=C1 instruction */
-#define RVC_C1_RS1_OPOFF 7
-#define RVC_C1_RS2_OPOFF 2
-#define RVC_C1_RD_OPOFF 7
+#include <asm/insn_gen.h>
-/* The register offset in RVC op=C2 instruction */
-#define RVC_C2_RS1_OPOFF 7
-#define RVC_C2_RS2_OPOFF 2
-#define RVC_C2_RD_OPOFF 7
-#define RVC_C2_RS1_MASK GENMASK(4, 0)
+#define RV_INSN_OPCODE_MASK GENMASK(6, 0)
/* parts of opcode for RVG*/
-#define RVG_OPCODE_FENCE 0x0f
-#define RVG_OPCODE_AUIPC 0x17
#define RVG_OPCODE_BRANCH 0x63
-#define RVG_OPCODE_JALR 0x67
-#define RVG_OPCODE_JAL 0x6f
#define RVG_OPCODE_SYSTEM 0x73
#define RVG_SYSTEM_CSR_OFF 20
#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
+// THESE ARE ALL ACTUALLY USED
/* parts of opcode for RVF, RVD and RVQ */
#define RVFDQ_FL_FS_WIDTH_OFF 12
#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0)
-#define RVFDQ_FL_FS_WIDTH_W 2
-#define RVFDQ_FL_FS_WIDTH_D 3
-#define RVFDQ_LS_FS_WIDTH_Q 4
#define RVFDQ_OPCODE_FL 0x07
#define RVFDQ_OPCODE_FS 0x27
+// THESE ARE ALL ACTUALLY USED
/* parts of opcode for RVV */
#define RVV_OPCODE_VECTOR 0x57
#define RVV_VL_VS_WIDTH_8 0
@@ -162,107 +63,11 @@
#define RVV_OPCODE_VL RVFDQ_OPCODE_FL
#define RVV_OPCODE_VS RVFDQ_OPCODE_FS
-/* parts of opcode for RVC*/
-#define RVC_OPCODE_C0 0x0
-#define RVC_OPCODE_C1 0x1
-#define RVC_OPCODE_C2 0x2
-
-/* parts of funct3 code for I, M, A extension*/
-#define RVG_FUNCT3_JALR 0x0
-#define RVG_FUNCT3_BEQ 0x0
-#define RVG_FUNCT3_BNE 0x1
-#define RVG_FUNCT3_BLT 0x4
-#define RVG_FUNCT3_BGE 0x5
-#define RVG_FUNCT3_BLTU 0x6
-#define RVG_FUNCT3_BGEU 0x7
-
-/* parts of funct3 code for C extension*/
-#define RVC_FUNCT3_C_BEQZ 0x6
-#define RVC_FUNCT3_C_BNEZ 0x7
-#define RVC_FUNCT3_C_J 0x5
-#define RVC_FUNCT3_C_JAL 0x1
-#define RVC_FUNCT4_C_JR 0x8
-#define RVC_FUNCT4_C_JALR 0x9
-#define RVC_FUNCT4_C_EBREAK 0x9
-
-#define RVG_FUNCT12_EBREAK 0x1
-#define RVG_FUNCT12_SRET 0x102
-
-#define RVG_MATCH_AUIPC (RVG_OPCODE_AUIPC)
-#define RVG_MATCH_JALR (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)
-#define RVG_MATCH_JAL (RVG_OPCODE_JAL)
-#define RVG_MATCH_FENCE (RVG_OPCODE_FENCE)
-#define RVG_MATCH_BEQ (RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BNE (RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BLT (RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BGE (RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BLTU (RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BGEU (RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_EBREAK (RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM)
-#define RVG_MATCH_SRET (RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM)
-#define RVC_MATCH_C_BEQZ (RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1)
-#define RVC_MATCH_C_BNEZ (RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1)
-#define RVC_MATCH_C_J (RVC_ENCODE_FUNCT3(C_J) | RVC_OPCODE_C1)
-#define RVC_MATCH_C_JAL (RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1)
-#define RVC_MATCH_C_JR (RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2)
-#define RVC_MATCH_C_JALR (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)
-#define RVC_MATCH_C_EBREAK (RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)
-
-#define RVG_MASK_AUIPC (RV_INSN_OPCODE_MASK)
-#define RVG_MASK_JALR (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
-#define RVG_MASK_JAL (RV_INSN_OPCODE_MASK)
-#define RVG_MASK_FENCE (RV_INSN_OPCODE_MASK)
-#define RVC_MASK_C_JALR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
-#define RVC_MASK_C_JR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
-#define RVC_MASK_C_JAL (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
-#define RVC_MASK_C_J (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
-#define RVG_MASK_BEQ (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
-#define RVG_MASK_BNE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
-#define RVG_MASK_BLT (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
-#define RVG_MASK_BGE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
-#define RVG_MASK_BLTU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
-#define RVG_MASK_BGEU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
-#define RVC_MASK_C_BEQZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
-#define RVC_MASK_C_BNEZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
-#define RVC_MASK_C_EBREAK 0xffff
-#define RVG_MASK_EBREAK 0xffffffff
-#define RVG_MASK_SRET 0xffffffff
-
#define __INSN_LENGTH_MASK _UL(0x3)
#define __INSN_LENGTH_GE_32 _UL(0x3)
#define __INSN_OPCODE_MASK _UL(0x7F)
#define __INSN_BRANCH_OPCODE _UL(RVG_OPCODE_BRANCH)
-#define __RISCV_INSN_FUNCS(name, mask, val) \
-static __always_inline bool riscv_insn_is_##name(u32 code) \
-{ \
- BUILD_BUG_ON(~(mask) & (val)); \
- return (code & (mask)) == (val); \
-} \
-
-#if __riscv_xlen == 32
-/* C.JAL is an RV32C-only instruction */
-__RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
-#else
-#define riscv_insn_is_c_jal(opcode) 0
-#endif
-__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
-__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
-__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
-__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
-__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
-__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
-__RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT)
-__RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE)
-__RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU)
-__RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU)
-__RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ)
-__RISCV_INSN_FUNCS(c_bnez, RVC_MASK_C_BNEZ, RVC_MATCH_C_BNEZ)
-__RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK)
-__RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK)
-__RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET)
-__RISCV_INSN_FUNCS(fence, RVG_MASK_FENCE, RVG_MATCH_FENCE);
-
/* special case to catch _any_ system instruction */
static __always_inline bool riscv_insn_is_system(u32 code)
{
@@ -275,248 +80,26 @@ static __always_inline bool riscv_insn_is_branch(u32 code)
return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
}
-static __always_inline bool riscv_insn_is_c_jr(u32 code)
-{
- return (code & RVC_MASK_C_JR) == RVC_MATCH_C_JR &&
- (code & RVC_INSN_J_RS1_MASK) != 0;
-}
-
-static __always_inline bool riscv_insn_is_c_jalr(u32 code)
-{
- return (code & RVC_MASK_C_JALR) == RVC_MATCH_C_JALR &&
- (code & RVC_INSN_J_RS1_MASK) != 0;
-}
-
-#define INSN_MATCH_LB 0x3
-#define INSN_MASK_LB 0x707f
-#define INSN_MATCH_LH 0x1003
-#define INSN_MASK_LH 0x707f
-#define INSN_MATCH_LW 0x2003
-#define INSN_MASK_LW 0x707f
-#define INSN_MATCH_LD 0x3003
-#define INSN_MASK_LD 0x707f
-#define INSN_MATCH_LBU 0x4003
-#define INSN_MASK_LBU 0x707f
-#define INSN_MATCH_LHU 0x5003
-#define INSN_MASK_LHU 0x707f
-#define INSN_MATCH_LWU 0x6003
-#define INSN_MASK_LWU 0x707f
-#define INSN_MATCH_SB 0x23
-#define INSN_MASK_SB 0x707f
-#define INSN_MATCH_SH 0x1023
-#define INSN_MASK_SH 0x707f
-#define INSN_MATCH_SW 0x2023
-#define INSN_MASK_SW 0x707f
-#define INSN_MATCH_SD 0x3023
-#define INSN_MASK_SD 0x707f
-
-#define INSN_MATCH_C_LD 0x6000
-#define INSN_MASK_C_LD 0xe003
-#define INSN_MATCH_C_SD 0xe000
-#define INSN_MASK_C_SD 0xe003
-#define INSN_MATCH_C_LW 0x4000
-#define INSN_MASK_C_LW 0xe003
-#define INSN_MATCH_C_SW 0xc000
-#define INSN_MASK_C_SW 0xe003
-#define INSN_MATCH_C_LDSP 0x6002
-#define INSN_MASK_C_LDSP 0xe003
-#define INSN_MATCH_C_SDSP 0xe002
-#define INSN_MASK_C_SDSP 0xe003
-#define INSN_MATCH_C_LWSP 0x4002
-#define INSN_MASK_C_LWSP 0xe003
-#define INSN_MATCH_C_SWSP 0xc002
-#define INSN_MASK_C_SWSP 0xe003
-
#define INSN_OPCODE_MASK 0x007c
#define INSN_OPCODE_SHIFT 2
#define INSN_OPCODE_SYSTEM 28
-#define INSN_MASK_WFI 0xffffffff
-#define INSN_MATCH_WFI 0x10500073
-
-#define INSN_MASK_WRS 0xffffffff
-#define INSN_MATCH_WRS 0x00d00073
-
-#define INSN_MATCH_CSRRW 0x1073
-#define INSN_MASK_CSRRW 0x707f
-#define INSN_MATCH_CSRRS 0x2073
-#define INSN_MASK_CSRRS 0x707f
-#define INSN_MATCH_CSRRC 0x3073
-#define INSN_MASK_CSRRC 0x707f
-#define INSN_MATCH_CSRRWI 0x5073
-#define INSN_MASK_CSRRWI 0x707f
-#define INSN_MATCH_CSRRSI 0x6073
-#define INSN_MASK_CSRRSI 0x707f
-#define INSN_MATCH_CSRRCI 0x7073
-#define INSN_MASK_CSRRCI 0x707f
-
-#define INSN_MATCH_FLW 0x2007
-#define INSN_MASK_FLW 0x707f
-#define INSN_MATCH_FLD 0x3007
-#define INSN_MASK_FLD 0x707f
-#define INSN_MATCH_FLQ 0x4007
-#define INSN_MASK_FLQ 0x707f
-#define INSN_MATCH_FSW 0x2027
-#define INSN_MASK_FSW 0x707f
-#define INSN_MATCH_FSD 0x3027
-#define INSN_MASK_FSD 0x707f
-#define INSN_MATCH_FSQ 0x4027
-#define INSN_MASK_FSQ 0x707f
-
-#define INSN_MATCH_C_FLD 0x2000
-#define INSN_MASK_C_FLD 0xe003
-#define INSN_MATCH_C_FLW 0x6000
-#define INSN_MASK_C_FLW 0xe003
-#define INSN_MATCH_C_FSD 0xa000
-#define INSN_MASK_C_FSD 0xe003
-#define INSN_MATCH_C_FSW 0xe000
-#define INSN_MASK_C_FSW 0xe003
-#define INSN_MATCH_C_FLDSP 0x2002
-#define INSN_MASK_C_FLDSP 0xe003
-#define INSN_MATCH_C_FSDSP 0xa002
-#define INSN_MASK_C_FSDSP 0xe003
-#define INSN_MATCH_C_FLWSP 0x6002
-#define INSN_MASK_C_FLWSP 0xe003
-#define INSN_MATCH_C_FSWSP 0xe002
-#define INSN_MASK_C_FSWSP 0xe003
-
-#define INSN_MATCH_C_LHU 0x8400
-#define INSN_MASK_C_LHU 0xfc43
-#define INSN_MATCH_C_LH 0x8440
-#define INSN_MASK_C_LH 0xfc43
-#define INSN_MATCH_C_SH 0x8c00
-#define INSN_MASK_C_SH 0xfc43
-
#define INSN_16BIT_MASK 0x3
#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
-#define SHIFT_RIGHT(x, y) \
- ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
-
#define REG_MASK \
((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
-#define REG_OFFSET(insn, pos) \
- (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
-
-#define REG_PTR(insn, pos, regs) \
- ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
-
-#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
-#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
-#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
-#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
-#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
-#define GET_SP(regs) (*REG_PTR(2, 0, regs))
-#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
-#define IMM_I(insn) ((s32)(insn) >> 20)
-#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
- (s32)(((insn) >> 7) & 0x1f))
-
-#define SH_RD 7
-#define SH_RS1 15
-#define SH_RS2 20
-#define SH_RS2C 2
-#define MASK_RX 0x1f
-
#if defined(CONFIG_64BIT)
#define LOG_REGBYTES 3
#else
#define LOG_REGBYTES 2
#endif
-#define MASK_FUNCT3 0x7000
-
-#define GET_FUNCT3(insn) (((insn) >> 12) & 7)
-
-#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
-#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
-#define RV_X_MASK(X, s, mask) (((X) >> (s)) & (mask))
-#define RV_X(X, s, n) RV_X_MASK(X, s, ((1 << (n)) - 1))
-#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
- (RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 5, 1) << 6))
-#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 5, 2) << 6))
-#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
- (RV_X(x, 12, 1) << 5) | \
- (RV_X(x, 2, 2) << 6))
-#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
- (RV_X(x, 12, 1) << 5) | \
- (RV_X(x, 2, 3) << 6))
-#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
- (RV_X(x, 7, 2) << 6))
-#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 7, 3) << 6))
-#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
-#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
-#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
-#define RVC_X(X, s, mask) RV_X_MASK(X, s, mask)
-
-#define RV_EXTRACT_FUNCT3(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RV_INSN_FUNCT3_OPOFF, \
- RV_INSN_FUNCT3_MASK >> RV_INSN_FUNCT3_OPOFF)); })
-
-#define RV_EXTRACT_RS1_REG(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
-
-#define RV_EXTRACT_RS2_REG(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RVG_RS2_OPOFF, RVG_RS2_MASK)); })
-
-#define RV_EXTRACT_RD_REG(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
-
-#define RV_EXTRACT_UTYPE_IMM(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
-
-#define RV_EXTRACT_JTYPE_IMM(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
- (RV_X_MASK(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
- (RV_X_MASK(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
- (RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })
-
-#define RV_EXTRACT_ITYPE_IMM(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
- (RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })
-
-#define RV_EXTRACT_BTYPE_IMM(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
- (RV_X_MASK(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
- (RV_X_MASK(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
- (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
-
-#define RVC_EXTRACT_C2_RS1_REG(x) \
- ({typeof(x) x_ = (x); \
- (RV_X_MASK(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
-
-#define RVC_EXTRACT_JTYPE_IMM(x) \
- ({typeof(x) x_ = (x); \
- (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \
- (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \
- (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \
- (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \
- (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \
- (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \
- (RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \
- (RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); })
-
-#define RVC_EXTRACT_BTYPE_IMM(x) \
- ({typeof(x) x_ = (x); \
- (RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \
- (RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \
- (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \
- (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
- (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
+#define RV_X_MASK(X, s, mask) (((X) >> (s)) & (mask))
+// These three are used by vector stuff
#define RVG_EXTRACT_SYSTEM_CSR(x) \
({typeof(x) x_ = (x); RV_X_MASK(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
@@ -526,78 +109,32 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
#define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
-/*
- * Get the immediate from a J-type instruction.
- *
- * @insn: instruction to process
- * Return: immediate
- */
-static inline s32 riscv_insn_extract_jtype_imm(u32 insn)
-{
- return RV_EXTRACT_JTYPE_IMM(insn);
-}
-
-/*
- * Update a J-type instruction with an immediate value.
- *
- * @insn: pointer to the jtype instruction
- * @imm: the immediate to insert into the instruction
- */
-static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm)
+static inline unsigned long riscv_insn_reg_get_val(unsigned long *regs, u32 index)
{
- /* drop the old IMMs, all jal IMM bits sit at 31:12 */
- *insn &= ~GENMASK(31, 12);
- *insn |= (RV_X_MASK(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
- (RV_X_MASK(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
- (RV_X_MASK(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
- (RV_X_MASK(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
+ /* register 0 is always 0 and not stored in the register struct */
+ return index ? *(regs + index) : 0;
}
-/*
- * Put together one immediate from a U-type and I-type instruction pair.
- *
- * The U-type contains an upper immediate, meaning bits[31:12] with [11:0]
- * being zero, while the I-type contains a 12bit immediate.
- * Combined these can encode larger 32bit values and are used for example
- * in auipc + jalr pairs to allow larger jumps.
- *
- * @utype_insn: instruction containing the upper immediate
- * @itype_insn: instruction
- * Return: combined immediate
- */
-static inline s32 riscv_insn_extract_utype_itype_imm(u32 utype_insn, u32 itype_insn)
+static inline void riscv_insn_reg_set_val(unsigned long *regs, u32 index, unsigned long val)
{
- s32 imm;
-
- imm = RV_EXTRACT_UTYPE_IMM(utype_insn);
- imm += RV_EXTRACT_ITYPE_IMM(itype_insn);
-
- return imm;
+ /* register 0 is always 0 and not stored in the register struct */
+ if (index != 0)
+ *(regs + index) = val;
}
-/*
- * Update a set of two instructions (U-type + I-type) with an immediate value.
- *
- * Used for example in auipc+jalrs pairs the U-type instructions contains
- * a 20bit upper immediate representing bits[31:12], while the I-type
- * instruction contains a 12bit immediate representing bits[11:0].
- *
- * This also takes into account that both separate immediates are
- * considered as signed values, so if the I-type immediate becomes
- * negative (BIT(11) set) the U-type part gets adjusted.
- *
- * @utype_insn: pointer to the utype instruction of the pair
- * @itype_insn: pointer to the itype instruction of the pair
- * @imm: the immediate to insert into the two instructions
- */
-static inline void riscv_insn_insert_utype_itype_imm(u32 *utype_insn, u32 *itype_insn, s32 imm)
-{
- /* drop possible old IMM values */
- *utype_insn &= ~(RV_U_IMM_31_12_MASK);
- *itype_insn &= ~(RV_I_IMM_11_0_MASK << RV_I_IMM_11_0_OPOFF);
+#define riscv_insn_branch(_insn, regs_ptr, _opcode, _pc, _comparison, type) \
+ ({ \
+ unsigned long _ret; \
+ if ((type)riscv_insn_reg_get_val( \
+ regs_ptr, \
+ riscv_insn_##_insn##_extract_xs1(_opcode)) \
+ _comparison(type) riscv_insn_reg_get_val( \
+ regs_ptr, \
+ riscv_insn_##_insn##_extract_xs2(_opcode))) \
+ _ret = _pc + riscv_insn_##_insn##_extract_imm(_opcode); \
+ else \
+ _ret = _pc + 4; \
+ _ret; \
+ })
- /* add the adapted IMMs */
- *utype_insn |= (imm & RV_U_IMM_31_12_MASK) + ((imm & BIT(11)) << 1);
- *itype_insn |= ((imm & RV_I_IMM_11_0_MASK) << RV_I_IMM_11_0_OPOFF);
-}
#endif /* _ASM_RISCV_INSN_H */
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 75b0a951c1bc6f..4d30d30ebefc73 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -167,6 +167,12 @@ struct kvm_vcpu_reset_state {
unsigned long a1;
};
+#ifdef CONFIG_RISCV_KVM_TEST_CSR
+struct kvm_test_csr {
+ unsigned long val;
+};
+#endif
+
struct kvm_vcpu_arch {
/* VCPU ran at least once */
bool ran_atleast_once;
@@ -265,6 +271,10 @@ struct kvm_vcpu_arch {
gpa_t shmem;
u64 last_steal;
} sta;
+
+#ifdef CONFIG_RISCV_KVM_TEST_CSR
+ struct kvm_test_csr test_csr;
+#endif
};
/*
diff --git a/arch/riscv/include/asm/kvm_vcpu_insn.h b/arch/riscv/include/asm/kvm_vcpu_insn.h
index 350011c83581cb..01efdaaede217b 100644
--- a/arch/riscv/include/asm/kvm_vcpu_insn.h
+++ b/arch/riscv/include/asm/kvm_vcpu_insn.h
@@ -11,7 +11,7 @@ struct kvm_run;
struct kvm_cpu_trap;
struct kvm_mmio_decode {
- unsigned long insn;
+ unsigned long rd;
int insn_len;
int len;
int shift;
@@ -19,7 +19,8 @@ struct kvm_mmio_decode {
};
struct kvm_csr_decode {
- unsigned long insn;
+ unsigned long rd;
+ unsigned long insn_len;
int return_handled;
};
diff --git a/arch/riscv/include/asm/kvm_vcpu_test_csr.h b/arch/riscv/include/asm/kvm_vcpu_test_csr.h
new file mode 100644
index 00000000000000..a844fccaafc346
--- /dev/null
+++ b/arch/riscv/include/asm/kvm_vcpu_test_csr.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __KVM_VCPU_RISCV_TEST_CSR_H
+#define __KVM_VCPU_RISCV_TEST_CSR_H
+
+#include <asm/kvm_vcpu_insn.h>
+
+#define KVM_RISCV_VCPU_TEST_CSR_FUNCS \
+ {.base = CSR_VSSCRATCH, .count = 1, .func = kvm_riscv_vcpu_test_csr },
+
+int kvm_riscv_vcpu_test_csr(struct kvm_vcpu *vcpu, unsigned int csr_num,
+ unsigned long *val, unsigned long new_val,
+ unsigned long wr_mask);
+
+#endif /* !__KVM_VCPU_RISCV_TEST_CSR_H */
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 7642704c7f1841..b26a90eb65ccac 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -11,6 +11,7 @@
#include <linux/cpu.h>
#include <linux/uaccess.h>
#include <asm/alternative.h>
+#include <asm/insn.h>
#include <asm/module.h>
#include <asm/sections.h>
#include <asm/vdso.h>
@@ -78,14 +79,24 @@ static void riscv_alternative_fix_auipc_jalr(void *ptr, u32 auipc_insn,
u32 jalr_insn, int patch_offset)
{
u32 call[2] = { auipc_insn, jalr_insn };
+ u32 auipc_imm;
s32 imm;
/* get and adjust new target address */
- imm = riscv_insn_extract_utype_itype_imm(auipc_insn, jalr_insn);
+ imm = riscv_insn_auipc_extract_imm(auipc_insn) + riscv_insn_jalr_extract_imm(jalr_insn);
imm -= patch_offset;
+ /*
+ * When the 32-bit immediate is split across auipc and jalr, the
+ * constructed immediates need to be treated as individually sign
+ * extended numbers. Add the sign bit of the lower 12 bits to the upper
+ * 20 bits to undo the bleeding of the sign.
+ */
+ auipc_imm = imm + (BIT(11) << 1);
+
/* update instructions */
- riscv_insn_insert_utype_itype_imm(&call[0], &call[1], imm);
+ riscv_insn_auipc_insert_imm(&call[0], auipc_imm);
+ riscv_insn_jalr_insert_imm(&call[1], imm);
/* patch the call place again */
patch_text_nosync(ptr, call, sizeof(u32) * 2);
@@ -96,11 +107,11 @@ static void riscv_alternative_fix_jal(void *ptr, u32 jal_insn, int patch_offset)
s32 imm;
/* get and adjust new target address */
- imm = riscv_insn_extract_jtype_imm(jal_insn);
+ imm = riscv_insn_jal_extract_imm(jal_insn);
imm -= patch_offset;
/* update instruction */
- riscv_insn_insert_jtype_imm(&jal_insn, imm);
+ riscv_insn_jal_insert_imm(&jal_insn, imm);
/* patch the call place again */
patch_text_nosync(ptr, &jal_insn, sizeof(u32));
@@ -127,7 +138,7 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len,
continue;
/* if instruction pair is a call, it will use the ra register */
- if (RV_EXTRACT_RD_REG(insn) != 1)
+ if (riscv_insn_jalr_extract_xd(insn) != 1)
continue;
riscv_alternative_fix_auipc_jalr(alt_ptr + i * sizeof(u32),
@@ -136,7 +147,7 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len,
}
if (riscv_insn_is_jal(insn)) {
- s32 imm = riscv_insn_extract_jtype_imm(insn);
+ s32 imm = riscv_insn_jal_extract_imm(insn);
/* Don't modify jumps inside the alternative block */
if ((alt_ptr + i * sizeof(u32) + imm) >= alt_ptr &&
diff --git a/arch/riscv/kernel/cfi.c b/arch/riscv/kernel/cfi.c
index 6ec9dbd7292eec..e38d5f863747af 100644
--- a/arch/riscv/kernel/cfi.c
+++ b/arch/riscv/kernel/cfi.c
@@ -40,16 +40,16 @@ static bool decode_cfi_insn(struct pt_regs *regs, unsigned long *target,
if (!riscv_insn_is_beq(insn))
return false;
- *type = (u32)regs_ptr[RV_EXTRACT_RS1_REG(insn)];
+ *type = (u32)regs_ptr[riscv_insn_beq_extract_xs1(insn)];
if (get_kernel_nofault(insn, (void *)regs->epc) ||
get_kernel_nofault(insn, (void *)regs->epc + GET_INSN_LENGTH(insn)))
return false;
if (riscv_insn_is_jalr(insn))
- rs1_num = RV_EXTRACT_RS1_REG(insn);
+ rs1_num = riscv_insn_jalr_extract_xs1(insn);
else if (riscv_insn_is_c_jalr(insn))
- rs1_num = RVC_EXTRACT_C2_RS1_REG(insn);
+ rs1_num = riscv_insn_c_jalr_extract_xs1(insn);
else
return false;
diff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c
index 0bf629204c76a4..fcf7cda3cc33fb 100644
--- a/arch/riscv/kernel/kgdb.c
+++ b/arch/riscv/kernel/kgdb.c
@@ -23,97 +23,73 @@ enum {
static unsigned long stepped_address;
static unsigned int stepped_opcode;
-static int decode_register_index(unsigned long opcode, int offset)
-{
- return (opcode >> offset) & 0x1F;
-}
-
-static int decode_register_index_short(unsigned long opcode, int offset)
-{
- return ((opcode >> offset) & 0x7) + 8;
-}
-
-/* Calculate the new address for after a step */
static int get_step_address(struct pt_regs *regs, unsigned long *next_addr)
{
unsigned long pc = regs->epc;
unsigned long *regs_ptr = (unsigned long *)regs;
- unsigned int rs1_num, rs2_num;
+ unsigned int rs1_num;
int op_code;
if (get_kernel_nofault(op_code, (void *)pc))
return -EINVAL;
+
if ((op_code & __INSN_LENGTH_MASK) != __INSN_LENGTH_GE_32) {
- if (riscv_insn_is_c_jalr(op_code) ||
- riscv_insn_is_c_jr(op_code)) {
- rs1_num = decode_register_index(op_code, RVC_C2_RS1_OPOFF);
- *next_addr = regs_ptr[rs1_num];
- } else if (riscv_insn_is_c_j(op_code) ||
- riscv_insn_is_c_jal(op_code)) {
- *next_addr = RVC_EXTRACT_JTYPE_IMM(op_code) + pc;
+ if (riscv_insn_is_c_jalr(op_code)) {
+ *next_addr = regs_ptr[riscv_insn_c_jalr_extract_xs1(op_code)];
+ } else if (riscv_insn_is_c_jr(op_code)) {
+ *next_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(op_code)];
+ } else if (riscv_insn_is_c_j(op_code)) {
+ *next_addr = riscv_insn_c_j_extract_imm(op_code) + pc;
+ } else if (riscv_insn_is_c_jal(op_code)) {
+ *next_addr = riscv_insn_c_jal_extract_imm(op_code) + pc;
} else if (riscv_insn_is_c_beqz(op_code)) {
- rs1_num = decode_register_index_short(op_code,
- RVC_C1_RS1_OPOFF);
- if (!rs1_num || regs_ptr[rs1_num] == 0)
- *next_addr = RVC_EXTRACT_BTYPE_IMM(op_code) + pc;
+ rs1_num = riscv_insn_c_beqz_extract_xs1(op_code);
+ if (regs_ptr[8 + rs1_num] == 0)
+ *next_addr = riscv_insn_c_beqz_extract_imm(op_code) + pc;
else
*next_addr = pc + 2;
} else if (riscv_insn_is_c_bnez(op_code)) {
- rs1_num =
- decode_register_index_short(op_code, RVC_C1_RS1_OPOFF);
- if (rs1_num && regs_ptr[rs1_num] != 0)
- *next_addr = RVC_EXTRACT_BTYPE_IMM(op_code) + pc;
+ rs1_num = riscv_insn_c_bnez_extract_xs1(op_code);
+ if (regs_ptr[8 + rs1_num] != 0)
+ *next_addr = riscv_insn_c_bnez_extract_imm(op_code) + pc;
else
*next_addr = pc + 2;
} else {
*next_addr = pc + 2;
}
} else {
- if ((op_code & __INSN_OPCODE_MASK) == __INSN_BRANCH_OPCODE) {
- bool result = false;
- long imm = RV_EXTRACT_BTYPE_IMM(op_code);
- unsigned long rs1_val = 0, rs2_val = 0;
-
- rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);
- rs2_num = decode_register_index(op_code, RVG_RS2_OPOFF);
- if (rs1_num)
- rs1_val = regs_ptr[rs1_num];
- if (rs2_num)
- rs2_val = regs_ptr[rs2_num];
-
- if (riscv_insn_is_beq(op_code))
- result = (rs1_val == rs2_val) ? true : false;
- else if (riscv_insn_is_bne(op_code))
- result = (rs1_val != rs2_val) ? true : false;
- else if (riscv_insn_is_blt(op_code))
- result =
- ((long)rs1_val <
- (long)rs2_val) ? true : false;
- else if (riscv_insn_is_bge(op_code))
- result =
- ((long)rs1_val >=
- (long)rs2_val) ? true : false;
- else if (riscv_insn_is_bltu(op_code))
- result = (rs1_val < rs2_val) ? true : false;
- else if (riscv_insn_is_bgeu(op_code))
- result = (rs1_val >= rs2_val) ? true : false;
- if (result)
- *next_addr = imm + pc;
- else
- *next_addr = pc + 4;
+ if (riscv_insn_is_beq(op_code)) {
+ *next_addr = riscv_insn_branch(beq, regs_ptr, op_code,
+ pc, ==, unsigned long);
+ } else if (riscv_insn_is_bne(op_code)) {
+ *next_addr = riscv_insn_branch(bne, regs_ptr, op_code,
+ pc, !=, unsigned long);
+ } else if (riscv_insn_is_blt(op_code)) {
+ *next_addr = riscv_insn_branch(blt, regs_ptr, op_code,
+ pc, <, long);
+ } else if (riscv_insn_is_bge(op_code)) {
+ *next_addr = riscv_insn_branch(bge, regs_ptr, op_code,
+ pc, >=, long);
+ } else if (riscv_insn_is_bltu(op_code)) {
+ *next_addr = riscv_insn_branch(bltu, regs_ptr, op_code,
+ pc, <, unsigned long);
+ } else if (riscv_insn_is_bgeu(op_code)) {
+ *next_addr = riscv_insn_branch(bgeu, regs_ptr, op_code,
+ pc, >=, unsigned long);
} else if (riscv_insn_is_jal(op_code)) {
- *next_addr = RV_EXTRACT_JTYPE_IMM(op_code) + pc;
+ *next_addr = riscv_insn_jal_extract_imm(op_code) + pc;
} else if (riscv_insn_is_jalr(op_code)) {
- rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF);
+ rs1_num = riscv_insn_jalr_extract_xs1(op_code);
if (rs1_num)
- *next_addr = ((unsigned long *)regs)[rs1_num];
- *next_addr += RV_EXTRACT_ITYPE_IMM(op_code);
+ *next_addr = regs_ptr[rs1_num];
+ *next_addr += riscv_insn_jalr_extract_imm(op_code);
} else if (riscv_insn_is_sret(op_code)) {
*next_addr = pc;
} else {
*next_addr = pc + 4;
}
}
+
return 0;
}
diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c
index 54e2d9552e930d..cad40e4afd8678 100644
--- a/arch/riscv/kernel/machine_kexec_file.c
+++ b/arch/riscv/kernel/machine_kexec_file.c
@@ -116,32 +116,6 @@ static char *setup_kdump_cmdline(struct kimage *image, char *cmdline,
(((x) + (RISCV_IMM_REACH >> 1)) & ~(RISCV_IMM_REACH - 1))
#define RISCV_CONST_LOW_PART(x) ((x) - RISCV_CONST_HIGH_PART(x))
-#define ENCODE_ITYPE_IMM(x) \
- (RV_X(x, 0, 12) << 20)
-#define ENCODE_BTYPE_IMM(x) \
- ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | \
- (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
-#define ENCODE_UTYPE_IMM(x) \
- (RV_X(x, 12, 20) << 12)
-#define ENCODE_JTYPE_IMM(x) \
- ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | \
- (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
-#define ENCODE_CBTYPE_IMM(x) \
- ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | \
- (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
-#define ENCODE_CJTYPE_IMM(x) \
- ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | \
- (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | \
- (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
-#define ENCODE_UJTYPE_IMM(x) \
- (ENCODE_UTYPE_IMM(RISCV_CONST_HIGH_PART(x)) | \
- (ENCODE_ITYPE_IMM(RISCV_CONST_LOW_PART(x)) << 32))
-#define ENCODE_UITYPE_IMM(x) \
- (ENCODE_UTYPE_IMM(x) | (ENCODE_ITYPE_IMM(x) << 32))
-
-#define CLEAN_IMM(type, x) \
- ((~ENCODE_##type##_IMM((uint64_t)(-1))) & (x))
-
int arch_kexec_apply_relocations_add(struct purgatory_info *pi,
Elf_Shdr *section,
const Elf_Shdr *relsec,
@@ -197,12 +171,14 @@ int arch_kexec_apply_relocations_add(struct purgatory_info *pi,
switch (r_type) {
case R_RISCV_BRANCH:
- *(u32 *)loc = CLEAN_IMM(BTYPE, *(u32 *)loc) |
- ENCODE_BTYPE_IMM(val - addr);
+ /*
+ * For simplicity, use beq as represenative of all
+ * branches (they all have the same imm encoding)
+ */
+ riscv_insn_beq_insert_imm((u32 *)loc, val - addr);
break;
case R_RISCV_JAL:
- *(u32 *)loc = CLEAN_IMM(JTYPE, *(u32 *)loc) |
- ENCODE_JTYPE_IMM(val - addr);
+ riscv_insn_jal_insert_imm((u32 *)loc, val - addr);
break;
/*
* With no R_RISCV_PCREL_LO12_S, R_RISCV_PCREL_LO12_I
@@ -213,16 +189,23 @@ int arch_kexec_apply_relocations_add(struct purgatory_info *pi,
case R_RISCV_PCREL_HI20:
case R_RISCV_CALL_PLT:
case R_RISCV_CALL:
- *(u64 *)loc = CLEAN_IMM(UITYPE, *(u64 *)loc) |
- ENCODE_UJTYPE_IMM(val - addr);
+ riscv_insn_auipc_insert_imm((u32 *)loc, RISCV_CONST_HIGH_PART(val - addr));
+ riscv_insn_jalr_insert_imm((u32 *)loc + 1,
+ RISCV_CONST_LOW_PART(val - addr));
break;
case R_RISCV_RVC_BRANCH:
- *(u32 *)loc = CLEAN_IMM(CBTYPE, *(u32 *)loc) |
- ENCODE_CBTYPE_IMM(val - addr);
+ /*
+ * For simplicity, use c.beqz as represenative of all
+ * compressed branches (they all have the same imm encoding)
+ */
+ riscv_insn_c_beqz_insert_imm((u16 *)loc, val - addr);
break;
case R_RISCV_RVC_JUMP:
- *(u32 *)loc = CLEAN_IMM(CJTYPE, *(u32 *)loc) |
- ENCODE_CJTYPE_IMM(val - addr);
+ /*
+ * For simplicity, use c.j as represenative of all
+ * compressed jumps (they all have the same imm encoding)
+ */
+ riscv_insn_c_j_insert_imm((u16 *)loc, val - addr);
break;
case R_RISCV_ADD16:
*(u16 *)loc += val;
diff --git a/arch/riscv/kernel/probes/decode-insn.c b/arch/riscv/kernel/probes/decode-insn.c
index 65d9590bfb9ff5..0d70c8301a451f 100644
--- a/arch/riscv/kernel/probes/decode-insn.c
+++ b/arch/riscv/kernel/probes/decode-insn.c
@@ -42,7 +42,12 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
RISCV_INSN_SET_SIMULATE(jal, insn);
RISCV_INSN_SET_SIMULATE(jalr, insn);
RISCV_INSN_SET_SIMULATE(auipc, insn);
- RISCV_INSN_SET_SIMULATE(branch, insn);
+ RISCV_INSN_SET_SIMULATE(beq, insn);
+ RISCV_INSN_SET_SIMULATE(bne, insn);
+ RISCV_INSN_SET_SIMULATE(blt, insn);
+ RISCV_INSN_SET_SIMULATE(bge, insn);
+ RISCV_INSN_SET_SIMULATE(bltu, insn);
+ RISCV_INSN_SET_SIMULATE(bgeu, insn);
return INSN_GOOD;
}
diff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c
index fa581590c1f8b2..a443883c323706 100644
--- a/arch/riscv/kernel/probes/simulate-insn.c
+++ b/arch/riscv/kernel/probes/simulate-insn.c
@@ -4,222 +4,152 @@
#include <linux/kernel.h>
#include <linux/kprobes.h>
-#include "decode-insn.h"
+#include <asm/insn.h>
#include "simulate-insn.h"
-static inline bool rv_insn_reg_get_val(struct pt_regs *regs, u32 index,
- unsigned long *ptr)
+bool __kprobes simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- if (index == 0)
- *ptr = 0;
- else if (index <= 31)
- *ptr = *((unsigned long *)regs + index);
- else
- return false;
+ s32 imm = riscv_insn_jal_extract_imm(opcode);
+ u32 index = riscv_insn_jal_extract_xd(opcode);
- return true;
-}
+ riscv_insn_reg_set_val((unsigned long *)regs, index, addr + 4);
-static inline bool rv_insn_reg_set_val(struct pt_regs *regs, u32 index,
- unsigned long val)
-{
- if (index == 0)
- return true;
- else if (index <= 31)
- *((unsigned long *)regs + index) = val;
- else
- return false;
+ instruction_pointer_set(regs, addr + imm);
return true;
}
-bool __kprobes simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs)
+bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- /*
- * 31 30 21 20 19 12 11 7 6 0
- * imm [20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode
- * 1 10 1 8 5 JAL/J
- */
- bool ret;
- s32 imm;
- u32 index = RV_EXTRACT_RD_REG(opcode);
+ unsigned long base_addr;
+ s32 imm = riscv_insn_jalr_extract_imm(opcode);
+ u32 rd_index = riscv_insn_jalr_extract_xd(opcode);
+ u32 rs1_index = riscv_insn_jalr_extract_xs1(opcode);
- ret = rv_insn_reg_set_val(regs, index, addr + 4);
- if (!ret)
- return ret;
+ base_addr = riscv_insn_reg_get_val((unsigned long *)regs, rs1_index);
- imm = RV_EXTRACT_JTYPE_IMM(opcode);
+ riscv_insn_reg_set_val((unsigned long *)regs, rd_index, addr + 4);
- instruction_pointer_set(regs, addr + imm);
+ instruction_pointer_set(regs, (base_addr + imm) & ~1);
- return ret;
+ return true;
}
-bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)
+bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- /*
- * 31 20 19 15 14 12 11 7 6 0
- * offset[11:0] | rs1 | 010 | rd | opcode
- * 12 5 3 5 JALR/JR
- */
- bool ret;
- unsigned long base_addr;
- u32 imm = RV_EXTRACT_ITYPE_IMM(opcode);
- u32 rd_index = RV_EXTRACT_RD_REG(opcode);
- u32 rs1_index = RV_EXTRACT_RS1_REG(opcode);
+ u32 rd_index = riscv_insn_auipc_extract_xd(opcode);
+ unsigned long rd_val = addr + (s32)riscv_insn_auipc_extract_imm(opcode);
- ret = rv_insn_reg_get_val(regs, rs1_index, &base_addr);
- if (!ret)
- return ret;
+ riscv_insn_reg_set_val((unsigned long *)regs, rd_index, rd_val);
- ret = rv_insn_reg_set_val(regs, rd_index, addr + 4);
- if (!ret)
- return ret;
-
- instruction_pointer_set(regs, (base_addr + sign_extend32((imm), 11))&~1);
+ instruction_pointer_set(regs, addr + 4);
- return ret;
+ return true;
}
-bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)
+bool __kprobes simulate_beq(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- /*
- * auipc instruction:
- * 31 12 11 7 6 0
- * | imm[31:12] | rd | opcode |
- * 20 5 7
- */
+ unsigned long next_addr;
- u32 rd_idx = RV_EXTRACT_RD_REG(opcode);
- unsigned long rd_val = addr + (s32)RV_EXTRACT_UTYPE_IMM(opcode);
+ next_addr = riscv_insn_branch(beq, (unsigned long *)regs, opcode, addr, ==, unsigned long);
+ instruction_pointer_set(regs, next_addr);
- if (!rv_insn_reg_set_val(regs, rd_idx, rd_val))
- return false;
+ return true;
+}
- instruction_pointer_set(regs, addr + 4);
+bool __kprobes simulate_bne(u32 opcode, unsigned long addr, struct pt_regs *regs)
+{
+ unsigned long next_addr;
+
+ next_addr = riscv_insn_branch(bne, (unsigned long *)regs, opcode, addr, !=, unsigned long);
+ instruction_pointer_set(regs, next_addr);
return true;
}
-bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs)
+bool __kprobes simulate_blt(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- /*
- * branch instructions:
- * 31 30 25 24 20 19 15 14 12 11 8 7 6 0
- * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |
- * 1 6 5 5 3 4 1 7
- * imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 BEQ
- * imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 BNE
- * imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 BLT
- * imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 BGE
- * imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 BLTU
- * imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 BGEU
- */
-
- s32 offset;
- s32 offset_tmp;
- unsigned long rs1_val;
- unsigned long rs2_val;
-
- if (!rv_insn_reg_get_val(regs, RV_EXTRACT_RS1_REG(opcode), &rs1_val) ||
- !rv_insn_reg_get_val(regs, RV_EXTRACT_RS2_REG(opcode), &rs2_val))
- return false;
-
- offset_tmp = RV_EXTRACT_BTYPE_IMM(opcode);
- switch (RV_EXTRACT_FUNCT3(opcode)) {
- case RVG_FUNCT3_BEQ:
- offset = (rs1_val == rs2_val) ? offset_tmp : 4;
- break;
- case RVG_FUNCT3_BNE:
- offset = (rs1_val != rs2_val) ? offset_tmp : 4;
- break;
- case RVG_FUNCT3_BLT:
- offset = ((long)rs1_val < (long)rs2_val) ? offset_tmp : 4;
- break;
- case RVG_FUNCT3_BGE:
- offset = ((long)rs1_val >= (long)rs2_val) ? offset_tmp : 4;
- break;
- case RVG_FUNCT3_BLTU:
- offset = (rs1_val < rs2_val) ? offset_tmp : 4;
- break;
- case RVG_FUNCT3_BGEU:
- offset = (rs1_val >= rs2_val) ? offset_tmp : 4;
- break;
- default:
- return false;
- }
+ unsigned long next_addr;
- instruction_pointer_set(regs, addr + offset);
+ next_addr = riscv_insn_branch(blt, (unsigned long *)regs, opcode, addr, <, long);
+ instruction_pointer_set(regs, next_addr);
return true;
}
-bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs)
+bool __kprobes simulate_bge(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- s32 offset = RVC_EXTRACT_JTYPE_IMM(opcode);
+ unsigned long next_addr;
- instruction_pointer_set(regs, addr + offset);
+ next_addr = riscv_insn_branch(bge, (unsigned long *)regs, opcode, addr, >=, long);
+ instruction_pointer_set(regs, next_addr);
return true;
}
-static bool __kprobes simulate_c_jr_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs,
- bool is_jalr)
+bool __kprobes simulate_bltu(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- /*
- * 15 12 11 7 6 2 1 0
- * | funct4 | rs1 | rs2 | op |
- * 4 5 5 2
- */
+ unsigned long next_addr;
+
+ next_addr = riscv_insn_branch(bltu, (unsigned long *)regs, opcode, addr, <, unsigned long);
+ instruction_pointer_set(regs, next_addr);
- unsigned long jump_addr;
+ return true;
+}
- u32 rs1 = RVC_EXTRACT_C2_RS1_REG(opcode);
+bool __kprobes simulate_bgeu(u32 opcode, unsigned long addr, struct pt_regs *regs)
+{
+ unsigned long next_addr;
- if (rs1 == 0) /* C.JR is only valid when rs1 != x0 */
- return false;
+ next_addr = riscv_insn_branch(bgeu, (unsigned long *)regs, opcode, addr, >=, unsigned long);
+ instruction_pointer_set(regs, next_addr);
- if (!rv_insn_reg_get_val(regs, rs1, &jump_addr))
- return false;
+ return true;
+}
- if (is_jalr && !rv_insn_reg_set_val(regs, 1, addr + 2))
- return false;
+bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs)
+{
+ s32 offset = riscv_insn_c_j_extract_imm(opcode);
- instruction_pointer_set(regs, jump_addr);
+ instruction_pointer_set(regs, addr + offset);
return true;
}
bool __kprobes simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- return simulate_c_jr_jalr(opcode, addr, regs, false);
+ unsigned long next_addr;
+ unsigned long *regs_ptr = (unsigned long *)regs;
+
+ /* xs1 == 0 is invalid so riscv_insn_reg_get_val() isn't needed */
+ next_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(opcode)];
+ instruction_pointer_set(regs, next_addr);
+
+ return true;
}
bool __kprobes simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- return simulate_c_jr_jalr(opcode, addr, regs, true);
+ unsigned long next_addr;
+ unsigned long *regs_ptr = (unsigned long *)regs;
+
+ /* xs1 == 0 is invalid so riscv_insn_reg_get_val() isn't needed */
+ next_addr = regs_ptr[riscv_insn_c_jalr_extract_xs1(opcode)];
+ instruction_pointer_set(regs, next_addr);
+
+ regs->ra = addr + 2;
+ return true;
}
-static bool __kprobes simulate_c_bnez_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs,
- bool is_bnez)
+bool __kprobes simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- /*
- * 15 13 12 10 9 7 6 2 1 0
- * | funct3 | offset[8|4:3] | rs1' | offset[7:6|2:1|5] | op |
- * 3 3 3 5 2
- */
-
- s32 offset;
u32 rs1;
- unsigned long rs1_val;
+ unsigned long offset;
+ unsigned long *regs_ptr = (unsigned long *)regs;
- rs1 = 0x8 | ((opcode >> 7) & 0x7);
-
- if (!rv_insn_reg_get_val(regs, rs1, &rs1_val))
- return false;
-
- if ((rs1_val != 0 && is_bnez) || (rs1_val == 0 && !is_bnez))
- offset = RVC_EXTRACT_BTYPE_IMM(opcode);
+ rs1 = riscv_insn_c_bnez_extract_xs1(opcode);
+ if (regs_ptr[8 + rs1] != 0)
+ offset = riscv_insn_c_bnez_extract_imm(opcode);
else
offset = 2;
@@ -228,12 +158,19 @@ static bool __kprobes simulate_c_bnez_beqz(u32 opcode, unsigned long addr, struc
return true;
}
-bool __kprobes simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs)
-{
- return simulate_c_bnez_beqz(opcode, addr, regs, true);
-}
-
bool __kprobes simulate_c_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
- return simulate_c_bnez_beqz(opcode, addr, regs, false);
+ u32 rs1;
+ unsigned long offset;
+ unsigned long *regs_ptr = (unsigned long *)regs;
+
+ rs1 = riscv_insn_c_beqz_extract_xs1(opcode);
+ if (regs_ptr[8 + rs1] == 0)
+ offset = riscv_insn_c_beqz_extract_imm(opcode);
+ else
+ offset = 2;
+
+ instruction_pointer_set(regs, addr + offset);
+
+ return true;
}
diff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h
index 44ebbc444db9da..f2f707e92dee3e 100644
--- a/arch/riscv/kernel/probes/simulate-insn.h
+++ b/arch/riscv/kernel/probes/simulate-insn.h
@@ -21,7 +21,12 @@
} while (0)
bool simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs);
-bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs);
+bool simulate_beq(u32 opcode, unsigned long addr, struct pt_regs *regs);
+bool simulate_bne(u32 opcode, unsigned long addr, struct pt_regs *regs);
+bool simulate_blt(u32 opcode, unsigned long addr, struct pt_regs *regs);
+bool simulate_bge(u32 opcode, unsigned long addr, struct pt_regs *regs);
+bool simulate_bltu(u32 opcode, unsigned long addr, struct pt_regs *regs);
+bool simulate_bgeu(u32 opcode, unsigned long addr, struct pt_regs *regs);
bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);
bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
bool simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs);
diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/tests/Kconfig.debug
index 40f8dafffa0ab6..9eda8938ec15b1 100644
--- a/arch/riscv/kernel/tests/Kconfig.debug
+++ b/arch/riscv/kernel/tests/Kconfig.debug
@@ -42,6 +42,19 @@ config RISCV_KPROBES_KUNIT
If unsure, say N.
+config RISCV_KPROBES_SIMULATE_KUNIT
+ tristate "KUnit test for riscv kprobes instruction simulation" if !KUNIT_ALL_TESTS
+ depends on KUNIT
+ depends on KPROBES
+ default KUNIT_ALL_TESTS
+ help
+ Enable testing for riscv kprobes instruction simulation. Useful for
+ riscv and/or kprobes development. The test verifies that kprobes
+ instruction simulation properly simulates the instructions. These tests
+ are very slow.
+
+ If unsure, say N.
+
endif # RUNTIME_TESTING_MENU
endmenu # "arch/riscv/kernel runtime Testing"
diff --git a/arch/riscv/kernel/tests/kprobes/Makefile b/arch/riscv/kernel/tests/kprobes/Makefile
index df7256f62313e2..34db6044e87f48 100644
--- a/arch/riscv/kernel/tests/kprobes/Makefile
+++ b/arch/riscv/kernel/tests/kprobes/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_RISCV_KPROBES_KUNIT) += kprobes_riscv_kunit.o
+obj-$(CONFIG_RISCV_KPROBES_SIMULATE_KUNIT) += kprobes_simulate_riscv_kunit.o
kprobes_riscv_kunit-objs := test-kprobes.o test-kprobes-asm.o
+kprobes_simulate_riscv_kunit-objs := test-kprobes-simulate.o
diff --git a/arch/riscv/kernel/tests/kprobes/test-kprobes-simulate.c b/arch/riscv/kernel/tests/kprobes/test-kprobes-simulate.c
new file mode 100644
index 00000000000000..d82706685823d2
--- /dev/null
+++ b/arch/riscv/kernel/tests/kprobes/test-kprobes-simulate.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/kernel.h>
+#include <linux/kprobes.h>
+#include <kunit/test.h>
+
+#include "../../probes/simulate-insn.h"
+
+#include <asm/insn.h>
+#include <asm/text-patching.h>
+
+static void test_kprobe_simulate_riscv(struct kunit *test)
+{
+ unsigned int addr = 0xdeadbeef;
+ unsigned int i = 0;
+
+ do {
+ struct pt_regs regs = { 0 };
+
+ if (riscv_insn_is_jal(i)) {
+ s32 offset = riscv_insn_jal_extract_imm(i);
+ u32 xd_index = riscv_insn_jal_extract_xd(i);
+
+ simulate_jal(i, addr, ®s);
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "jal instruction (0x%x) incorrectly simulated", i);
+
+ if (xd_index)
+ KUNIT_EXPECT_EQ_MSG(
+ test,
+ riscv_insn_reg_get_val((unsigned long *)®s, xd_index),
+ addr + 4, "jal instruction (0x%x) incorrectly simulated",
+ i);
+ }
+ if (riscv_insn_is_jalr(i)) {
+ unsigned long reg_addr = 0xffff;
+ s32 offset = riscv_insn_jalr_extract_imm(i);
+ u32 rd_index = riscv_insn_jalr_extract_xd(i);
+ u32 rs1_index = riscv_insn_jalr_extract_xs1(i);
+
+ if (rs1_index)
+ riscv_insn_reg_set_val((unsigned long *)®s, rs1_index, reg_addr);
+ else
+ reg_addr = 0;
+
+ simulate_jalr(i, addr, ®s);
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, (reg_addr + offset) & ~1,
+ "jalr instruction (0x%x) incorrectly simulated", i);
+
+ if (rd_index)
+ KUNIT_EXPECT_EQ_MSG(
+ test,
+ riscv_insn_reg_get_val((unsigned long *)®s, rd_index),
+ addr + 4, "jalr instruction (0x%x) incorrectly simulated",
+ i);
+ } else if (riscv_insn_is_auipc(i)) {
+ s32 offset = riscv_insn_auipc_extract_imm(i);
+ u32 rd_index = riscv_insn_auipc_extract_xd(i);
+
+ simulate_auipc(i, addr, ®s);
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,
+ "auipc instruction (0x%x) incorrectly simulated", i);
+
+ if (rd_index)
+ KUNIT_EXPECT_EQ_MSG(
+ test,
+ riscv_insn_reg_get_val((unsigned long *)®s, rd_index),
+ (unsigned long)addr + offset,
+ "auipc instruction (0x%x) incorrectly simulated", i);
+ } else if (riscv_insn_is_beq(i)) {
+ s32 offset = riscv_insn_beq_extract_imm(i);
+ u32 rs1_index = riscv_insn_beq_extract_xs1(i);
+ u32 rs2_index = riscv_insn_beq_extract_xs2(i);
+
+ simulate_beq(i, addr, ®s);
+
+ if (riscv_insn_reg_get_val((unsigned long *)®s, rs1_index) ==
+ riscv_insn_reg_get_val((unsigned long *)®s, rs2_index)) {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "beq instruction (0x%x) incorrectly simulated",
+ i);
+ } else {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,
+ "beq instruction (0x%x) incorrectly simulated",
+ i);
+ }
+ } else if (riscv_insn_is_bne(i)) {
+ s32 offset = riscv_insn_bne_extract_imm(i);
+ u32 rs1_index = riscv_insn_bne_extract_xs1(i);
+ u32 rs2_index = riscv_insn_bne_extract_xs2(i);
+
+ simulate_bne(i, addr, ®s);
+
+ if (riscv_insn_reg_get_val((unsigned long *)®s, rs1_index) !=
+ riscv_insn_reg_get_val((unsigned long *)®s, rs2_index)) {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "bne instruction (0x%x) incorrectly simulated",
+ i);
+ } else {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,
+ "bne instruction (0x%x) incorrectly simulated",
+ i);
+ }
+ } else if (riscv_insn_is_blt(i)) {
+ s32 offset = riscv_insn_blt_extract_imm(i);
+ u32 rs1_index = riscv_insn_blt_extract_xs1(i);
+ u32 rs2_index = riscv_insn_blt_extract_xs2(i);
+
+ simulate_blt(i, addr, ®s);
+
+ if ((long)riscv_insn_reg_get_val((unsigned long *)®s, rs1_index) <
+ (long)riscv_insn_reg_get_val((unsigned long *)®s, rs2_index)) {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "blt instruction (0x%x) incorrectly simulated",
+ i);
+ } else {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,
+ "blt instruction (0x%x) incorrectly simulated",
+ i);
+ }
+ } else if (riscv_insn_is_bge(i)) {
+ s32 offset = riscv_insn_bge_extract_imm(i);
+ u32 rs1_index = riscv_insn_bge_extract_xs1(i);
+ u32 rs2_index = riscv_insn_bge_extract_xs2(i);
+
+ simulate_bge(i, addr, ®s);
+
+ if ((long)riscv_insn_reg_get_val((unsigned long *)®s, rs1_index) >=
+ (long)riscv_insn_reg_get_val((unsigned long *)®s, rs2_index)) {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "bge instruction (0x%x) incorrectly simulated",
+ i);
+ } else {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,
+ "bge instruction (0x%x) incorrectly simulated",
+ i);
+ }
+ } else if (riscv_insn_is_bltu(i)) {
+ s32 offset = riscv_insn_bltu_extract_imm(i);
+ u32 rs1_index = riscv_insn_bltu_extract_xs1(i);
+ u32 rs2_index = riscv_insn_bltu_extract_xs2(i);
+
+ simulate_bltu(i, addr, ®s);
+
+ if (riscv_insn_reg_get_val((unsigned long *)®s, rs1_index) <
+ riscv_insn_reg_get_val((unsigned long *)®s, rs2_index)) {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "bltu instruction (0x%x) incorrectly simulated",
+ i);
+ } else {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,
+ "bltu instruction (0x%x) incorrectly simulated",
+ i);
+ }
+ } else if (riscv_insn_is_bgeu(i)) {
+ s32 offset = riscv_insn_bgeu_extract_imm(i);
+ u32 rs1_index = riscv_insn_bgeu_extract_xs1(i);
+ u32 rs2_index = riscv_insn_bgeu_extract_xs2(i);
+
+ simulate_bgeu(i, addr, ®s);
+
+ if (riscv_insn_reg_get_val((unsigned long *)®s, rs1_index) >=
+ riscv_insn_reg_get_val((unsigned long *)®s, rs2_index)) {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "bgeu instruction (0x%x) incorrectly simulated",
+ i);
+ } else {
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + 4,
+ "bgeu instruction (0x%x) incorrectly simulated",
+ i);
+ }
+ } else if (riscv_insn_is_c_j(i)) {
+ s32 offset = riscv_insn_c_j_extract_imm(i);
+
+ simulate_c_j(i, addr, ®s);
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "c.j instruction (0x%x) incorrectly simulated", i);
+ } else if (riscv_insn_is_c_jr(i)) {
+ u32 rs1_index = riscv_insn_c_jr_extract_xs1(i);
+
+ simulate_c_jr(i, addr, ®s);
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc,
+ riscv_insn_reg_get_val((unsigned long *)®s,
+ rs1_index),
+ "c.jr instruction (0x%x) incorrectly simulated", i);
+ } else if (riscv_insn_is_c_jalr(i)) {
+ unsigned long reg_addr = 0xffff;
+ u32 rs1_index = riscv_insn_c_jalr_extract_xs1(i);
+
+ if (rs1_index)
+ riscv_insn_reg_set_val((unsigned long *)®s, rs1_index, reg_addr);
+ else
+ reg_addr = 0;
+
+ simulate_c_jalr(i, addr, ®s);
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, reg_addr,
+ "c.jalr instruction (0x%x) incorrectly simulated", i);
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.ra, addr + 2,
+ "c.jalr instruction (0x%x) incorrectly simulated", i);
+ } else if (riscv_insn_is_c_bnez(i)) {
+ u32 offset;
+ u32 rs1_index = riscv_insn_c_bnez_extract_xs1(i);
+
+ simulate_c_bnez(i, addr, ®s);
+
+ if (riscv_insn_reg_get_val((unsigned long *)®s, rs1_index + 8) != 0)
+ offset = riscv_insn_c_bnez_extract_imm(i);
+ else
+ offset = 2;
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "c.bnez instruction (0x%x) incorrectly simulated", i);
+ } else if (riscv_insn_is_c_beqz(i)) {
+ u32 offset;
+ u32 rs1_index = riscv_insn_c_beqz_extract_xs1(i);
+
+ simulate_c_beqz(i, addr, ®s);
+
+ if (riscv_insn_reg_get_val((unsigned long *)®s, rs1_index + 8) == 0)
+ offset = riscv_insn_c_beqz_extract_imm(i);
+ else
+ offset = 2;
+
+ KUNIT_EXPECT_EQ_MSG(test, regs.epc, addr + offset,
+ "c.beqz instruction (0x%x) incorrectly simulated", i);
+ }
+ } while (++i > 0);
+}
+
+static struct kunit_case kprobes_simulate_testcases[] = {
+ KUNIT_CASE_SLOW(test_kprobe_simulate_riscv),
+ {}
+};
+
+static struct kunit_suite kprobes_simulate_test_suite = {
+ .name = "kprobes_simulate_riscv",
+ .test_cases = kprobes_simulate_testcases,
+};
+
+kunit_test_suites(&kprobes_simulate_test_suite);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("KUnit test for riscv kprobes instruction simulatation");
diff --git a/arch/riscv/kernel/tests/kprobes/test-kprobes.h b/arch/riscv/kernel/tests/kprobes/test-kprobes.h
index 537f44aa9d3f00..7a672de8f130f6 100644
--- a/arch/riscv/kernel/tests/kprobes/test-kprobes.h
+++ b/arch/riscv/kernel/tests/kprobes/test-kprobes.h
@@ -19,6 +19,12 @@ extern void *test_kprobes_addresses[];
/* array of functions that return KPROBE_TEST_MAGIC */
extern long (*test_kprobes_functions[])(void);
+void test_kprobes_arbitrary(void);
+
+extern unsigned int *test_kprobes_arbitrary_addr;
+
+extern unsigned int *test_kprobes_c_bnez_addr1;
+
#endif /* __ASSEMBLER__ */
#endif /* TEST_KPROBES_H */
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 81b7682e6c6dbc..4d2a2432e0c45f 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -22,15 +22,11 @@
#ifdef CONFIG_FPU
-#define FP_GET_RD(insn) (insn >> 7 & 0x1F)
-
extern void put_f32_reg(unsigned long fp_reg, unsigned long value);
-static int set_f32_rd(unsigned long insn, struct pt_regs *regs,
+static int set_f32_rd(unsigned long fp_reg, struct pt_regs *regs,
unsigned long val)
{
- unsigned long fp_reg = FP_GET_RD(insn);
-
put_f32_reg(fp_reg, val);
regs->status |= SR_FS_DIRTY;
@@ -39,9 +35,8 @@ static int set_f32_rd(unsigned long insn, struct pt_regs *regs,
extern void put_f64_reg(unsigned long fp_reg, unsigned long value);
-static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val)
+static int set_f64_rd(unsigned long fp_reg, struct pt_regs *regs, u64 val)
{
- unsigned long fp_reg = FP_GET_RD(insn);
unsigned long value;
#if __riscv_xlen == 32
@@ -58,10 +53,8 @@ static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val)
#if __riscv_xlen == 32
extern void get_f64_reg(unsigned long fp_reg, u64 *value);
-static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset,
- struct pt_regs *regs)
+static u64 get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)
{
- unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;
u64 val;
get_f64_reg(fp_reg, &val);
@@ -73,10 +66,8 @@ static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset,
extern unsigned long get_f64_reg(unsigned long fp_reg);
-static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,
- struct pt_regs *regs)
+static unsigned long get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)
{
- unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;
unsigned long val;
val = get_f64_reg(fp_reg);
@@ -89,10 +80,8 @@ static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,
extern unsigned long get_f32_reg(unsigned long fp_reg);
-static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,
- struct pt_regs *regs)
+static unsigned long get_f32_rs(unsigned long fp_reg, struct pt_regs *regs)
{
- unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;
unsigned long val;
val = get_f32_reg(fp_reg);
@@ -107,28 +96,18 @@ static void set_f32_rd(unsigned long insn, struct pt_regs *regs,
static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) {}
-static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,
- struct pt_regs *regs)
+static unsigned long get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)
{
return 0;
}
-static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,
- struct pt_regs *regs)
+static unsigned long get_f32_rs(unsigned long fp_reg, struct pt_regs *regs)
{
return 0;
}
#endif
-#define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs))
-#define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs))
-#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs))
-
-#define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs))
-#define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs))
-#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs))
-
#define __read_insn(regs, insn, insn_addr, type) \
({ \
int __ret; \
@@ -217,13 +196,13 @@ static int handle_vector_misaligned_load(struct pt_regs *regs)
}
#endif
-static int handle_scalar_misaligned_load(struct pt_regs *regs)
+static noinline int handle_scalar_misaligned_load(struct pt_regs *regs)
{
union reg_data val;
unsigned long epc = regs->epc;
unsigned long insn;
unsigned long addr = regs->badaddr;
- int fp = 0, shift = 0, len = 0;
+ int fp = 0, shift = 0, len = 0, rd = 0;
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
@@ -240,68 +219,71 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
regs->epc = 0;
- if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
+ if (riscv_insn_is_lw(insn)) {
len = 4;
shift = 8 * (sizeof(unsigned long) - len);
-#if defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
+ rd = riscv_insn_lw_extract_xd(insn);
+ } else if (riscv_insn_is_ld(insn)) {
len = 8;
shift = 8 * (sizeof(unsigned long) - len);
- } else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
+ rd = riscv_insn_ld_extract_xd(insn);
+ } else if (riscv_insn_is_lwu(insn)) {
len = 4;
-#endif
- } else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) {
+ rd = riscv_insn_lwu_extract_xd(insn);
+ } else if (riscv_insn_is_fld(insn)) {
fp = 1;
len = 8;
- } else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) {
+ rd = riscv_insn_fld_extract_fd(insn);
+ } else if (riscv_insn_is_flw(insn)) {
fp = 1;
len = 4;
- } else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
+ rd = riscv_insn_flw_extract_fd(insn);
+ } else if (riscv_insn_is_lh(insn)) {
len = 2;
shift = 8 * (sizeof(unsigned long) - len);
- } else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
+ rd = riscv_insn_lh_extract_xd(insn);
+ } else if (riscv_insn_is_lhu(insn)) {
len = 2;
-#if defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
+ rd = riscv_insn_lhu_extract_xd(insn);
+ } else if (riscv_insn_is_c_ld(insn)) {
len = 8;
shift = 8 * (sizeof(unsigned long) - len);
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ rd = (8 + riscv_insn_c_ld_extract_xd(insn));
+ } else if (riscv_insn_is_c_ldsp(insn)) {
len = 8;
shift = 8 * (sizeof(unsigned long) - len);
-#endif
- } else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
+ rd = riscv_insn_c_ldsp_extract_xd(insn);
+ } else if (riscv_insn_is_c_lw(insn)) {
len = 4;
shift = 8 * (sizeof(unsigned long) - len);
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ rd = (8 + riscv_insn_c_lw_extract_xd(insn));
+ } else if (riscv_insn_is_c_lwsp(insn)) {
len = 4;
shift = 8 * (sizeof(unsigned long) - len);
- } else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) {
+ rd = riscv_insn_c_lwsp_extract_xd(insn);
+ } else if (riscv_insn_is_c_fld(insn)) {
fp = 1;
len = 8;
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) {
+ rd = (8 + riscv_insn_c_fld_extract_fd(insn));
+ } else if (riscv_insn_is_c_fldsp(insn)) {
fp = 1;
len = 8;
-#if defined(CONFIG_32BIT)
- } else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) {
+ rd = riscv_insn_c_fldsp_extract_fd(insn);
+ } else if (riscv_insn_is_c_flw(insn)) {
fp = 1;
len = 4;
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) {
+ rd = (8 + riscv_insn_c_flw_extract_fd(insn));
+ } else if (riscv_insn_is_c_flwsp(insn)) {
fp = 1;
len = 4;
-#endif
- } else if ((insn & INSN_MASK_C_LHU) == INSN_MATCH_C_LHU) {
+ rd = riscv_insn_c_flwsp_extract_fd(insn);
+ } else if (riscv_insn_is_c_lhu(insn)) {
len = 2;
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_LH) == INSN_MATCH_C_LH) {
+ rd = (8 + riscv_insn_c_lhu_extract_xd(insn));
+ } else if (riscv_insn_is_c_lh(insn)) {
len = 2;
- shift = 8 * (sizeof(ulong) - len);
- insn = RVC_RS2S(insn) << SH_RD;
+ shift = 8 * (sizeof(unsigned long) - len);
+ rd = (8 + riscv_insn_c_lh_extract_xd(insn));
} else {
regs->epc = epc;
return -1;
@@ -319,11 +301,11 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
}
if (!fp)
- SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
+ *(unsigned long *)((unsigned long *)regs + rd) = val.data_ulong << shift;
else if (len == 8)
- set_f64_rd(insn, regs, val.data_u64);
+ set_f64_rd(rd, regs, val.data_u64);
else
- set_f32_rd(insn, regs, val.data_ulong);
+ set_f32_rd(rd, regs, val.data_ulong);
regs->epc = epc + INSN_LEN(insn);
@@ -336,7 +318,7 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)
unsigned long epc = regs->epc;
unsigned long insn;
unsigned long addr = regs->badaddr;
- int len = 0, fp = 0;
+ int fp = 0, len = 0, rd = 0;
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
@@ -351,67 +333,68 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)
regs->epc = 0;
- val.data_ulong = GET_RS2(insn, regs);
-
- if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {
+ if (riscv_insn_is_sw(insn)) {
len = 4;
-#if defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {
+ rd = riscv_insn_sw_extract_xs2(insn);
+ } else if (riscv_insn_is_sd(insn)) {
len = 8;
-#endif
- } else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) {
+ rd = riscv_insn_sd_extract_xs2(insn);
+ } else if (riscv_insn_is_fsd(insn)) {
fp = 1;
len = 8;
- val.data_u64 = GET_F64_RS2(insn, regs);
- } else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) {
+ rd = riscv_insn_fsd_extract_fs2(insn);
+ } else if (riscv_insn_is_fsw(insn)) {
fp = 1;
len = 4;
- val.data_ulong = GET_F32_RS2(insn, regs);
- } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
+ rd = riscv_insn_fsw_extract_fs2(insn);
+ } else if (riscv_insn_is_sh(insn)) {
len = 2;
-#if defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
+ rd = riscv_insn_sh_extract_xs2(insn);
+ } else if (riscv_insn_is_c_sd(insn)) {
len = 8;
- val.data_ulong = GET_RS2S(insn, regs);
- } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) {
+ rd = riscv_insn_c_sd_extract_xs2(insn);
+ } else if (riscv_insn_is_c_sdsp(insn)) {
len = 8;
- val.data_ulong = GET_RS2C(insn, regs);
-#endif
- } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
+ rd = riscv_insn_c_sdsp_extract_xs2(insn);
+ } else if (riscv_insn_is_c_sw(insn)) {
len = 4;
- val.data_ulong = GET_RS2S(insn, regs);
- } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) {
+ rd = riscv_insn_c_sw_extract_xs2(insn);
+ } else if (riscv_insn_is_c_swsp(insn)) {
len = 4;
- val.data_ulong = GET_RS2C(insn, regs);
- } else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) {
+ rd = riscv_insn_c_swsp_extract_xs2(insn);
+ } else if (riscv_insn_is_c_fsd(insn)) {
fp = 1;
len = 8;
- val.data_u64 = GET_F64_RS2S(insn, regs);
- } else if ((insn & INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) {
+ rd = riscv_insn_c_fsd_extract_fs2(insn);
+ } else if (riscv_insn_is_c_fsdsp(insn)) {
fp = 1;
len = 8;
- val.data_u64 = GET_F64_RS2C(insn, regs);
-#if !defined(CONFIG_64BIT)
- } else if ((insn & INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) {
+ rd = riscv_insn_c_fsdsp_extract_fs2(insn);
+ } else if (riscv_insn_is_c_fsw(insn)) {
fp = 1;
len = 4;
- val.data_ulong = GET_F32_RS2S(insn, regs);
- } else if ((insn & INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) {
+ rd = riscv_insn_c_fsw_extract_fs2(insn);
+ } else if (riscv_insn_is_c_fswsp(insn)) {
fp = 1;
len = 4;
- val.data_ulong = GET_F32_RS2C(insn, regs);
-#endif
- } else if ((insn & INSN_MASK_C_SH) == INSN_MATCH_C_SH) {
+ rd = riscv_insn_c_fswsp_extract_fs2(insn);
+ } else if (riscv_insn_is_c_sh(insn)) {
len = 2;
- val.data_ulong = GET_RS2S(insn, regs);
+ rd = riscv_insn_c_sh_extract_xs2(insn);
} else {
- regs->epc = epc;
return -1;
}
if (!IS_ENABLED(CONFIG_FPU) && fp)
return -EOPNOTSUPP;
+ if (!fp)
+ val.data_ulong = *(unsigned long *)((unsigned long *)regs + rd);
+ else if (len == 8)
+ val.data_u64 = get_f64_rs(rd, regs);
+ else
+ val.data_ulong = get_f32_rs(rd, regs);
+
if (user_mode(regs)) {
if (copy_to_user((u8 __user *)addr, &val, len))
return -1;
diff --git a/arch/riscv/kvm/Kconfig.debug b/arch/riscv/kvm/Kconfig.debug
new file mode 100644
index 00000000000000..dc76e02120a32c
--- /dev/null
+++ b/arch/riscv/kvm/Kconfig.debug
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "arch/riscv/kvm testing"
+
+config RISCV_KVM_TEST_CSR
+ bool "Test KVM CSR emulation"
+ depends on KVM
+ default n
+ help
+ Enable this option to enable the emulation of a test hypervisor csr.
+ The KVM test csr is the vsscratch register. Once this is enabled,
+ reading/writing to the vsscratch register will trap into the host
+ supervisor and reflect the change.
+
+ If unsure, say N.
+
+endmenu # "arch/riscv/kvm testing"
diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile
index 296c2ba05089ac..5092b86751c4c5 100644
--- a/arch/riscv/kvm/Makefile
+++ b/arch/riscv/kvm/Makefile
@@ -38,6 +38,7 @@ kvm-y += vcpu_sbi_sta.o
kvm-y += vcpu_sbi_system.o
kvm-$(CONFIG_RISCV_SBI_V01) += vcpu_sbi_v01.o
kvm-y += vcpu_switch.o
+kvm-$(CONFIG_RISCV_KVM_TEST_CSR) += vcpu_test_csr.o
kvm-y += vcpu_timer.o
kvm-y += vcpu_vector.o
kvm-y += vm.o
diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c
index f09f9251d1f0a0..d666cd24f8c0e9 100644
--- a/arch/riscv/kvm/vcpu_insn.c
+++ b/arch/riscv/kvm/vcpu_insn.c
@@ -10,9 +10,10 @@
#include <asm/cpufeature.h>
#include <asm/insn.h>
+#include <asm/kvm_vcpu_test_csr.h>
+
struct insn_func {
- unsigned long mask;
- unsigned long match;
+ bool (*cmp)(u32 insn);
/*
* Possible return values are as follows:
* 1) Returns < 0 for error case
@@ -112,6 +113,9 @@ static int seed_csr_rmw(struct kvm_vcpu *vcpu, unsigned int csr_num,
static const struct csr_func csr_funcs[] = {
KVM_RISCV_VCPU_AIA_CSR_FUNCS
KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS
+#ifdef CONFIG_RISCV_KVM_TEST_CSR
+ KVM_RISCV_VCPU_TEST_CSR_FUNCS
+#endif
{ .base = CSR_SEED, .count = 1, .func = seed_csr_rmw },
};
@@ -126,65 +130,70 @@ static const struct csr_func csr_funcs[] = {
*/
int kvm_riscv_vcpu_csr_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
- ulong insn;
-
if (vcpu->arch.csr_decode.return_handled)
return 0;
vcpu->arch.csr_decode.return_handled = 1;
/* Update destination register for CSR reads */
- insn = vcpu->arch.csr_decode.insn;
- if ((insn >> SH_RD) & MASK_RX)
- SET_RD(insn, &vcpu->arch.guest_context,
- run->riscv_csr.ret_value);
+ if (vcpu->arch.csr_decode.rd)
+ *((ulong *)&vcpu->arch.guest_context +
+ vcpu->arch.csr_decode.rd) = run->riscv_csr.ret_value;
/* Move to next instruction */
- vcpu->arch.guest_context.sepc += INSN_LEN(insn);
+ vcpu->arch.guest_context.sepc += vcpu->arch.csr_decode.insn_len;
return 0;
}
static int csr_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, ulong insn)
{
+ #define GET_REG(_rd) (*((unsigned long *)(&vcpu->arch.guest_context) + _rd))
+
int i, rc = KVM_INSN_ILLEGAL_TRAP;
- unsigned int csr_num = insn >> SH_RS2;
- unsigned int rs1_num = (insn >> SH_RS1) & MASK_RX;
- ulong rs1_val = GET_RS1(insn, &vcpu->arch.guest_context);
+ unsigned int csr_num, rd;
const struct csr_func *tcfn, *cfn = NULL;
ulong val = 0, wr_mask = 0, new_val = 0;
/* Decode the CSR instruction */
- switch (GET_FUNCT3(insn)) {
- case GET_FUNCT3(INSN_MATCH_CSRRW):
+ if (riscv_insn_is_csrrw(insn)) {
wr_mask = -1UL;
- new_val = rs1_val;
- break;
- case GET_FUNCT3(INSN_MATCH_CSRRS):
- wr_mask = rs1_val;
+ new_val = GET_REG(riscv_insn_csrrw_extract_xs1(insn));
+ csr_num = riscv_insn_csrrw_extract_csr(insn);
+ rd = riscv_insn_csrrw_extract_xd(insn);
+ } else if (riscv_insn_is_csrrs(insn)) {
+ wr_mask = GET_REG(riscv_insn_csrrs_extract_xs1(insn));
new_val = -1UL;
- break;
- case GET_FUNCT3(INSN_MATCH_CSRRC):
- wr_mask = rs1_val;
+ csr_num = riscv_insn_csrrs_extract_csr(insn);
+ rd = riscv_insn_csrrs_extract_xd(insn);
+ } else if (riscv_insn_is_csrrc(insn)) {
+ wr_mask = GET_REG(riscv_insn_csrrc_extract_xs1(insn));
new_val = 0;
- break;
- case GET_FUNCT3(INSN_MATCH_CSRRWI):
+ csr_num = riscv_insn_csrrc_extract_csr(insn);
+ rd = riscv_insn_csrrc_extract_xd(insn);
+ } else if (riscv_insn_is_csrrwi(insn)) {
wr_mask = -1UL;
- new_val = rs1_num;
- break;
- case GET_FUNCT3(INSN_MATCH_CSRRSI):
- wr_mask = rs1_num;
+ new_val = riscv_insn_csrrwi_extract_imm(insn);
+ csr_num = riscv_insn_csrrwi_extract_csr(insn);
+ rd = riscv_insn_csrrwi_extract_xd(insn);
+ } else if (riscv_insn_is_csrrsi(insn)) {
+ wr_mask = riscv_insn_csrrwi_extract_imm(insn);
new_val = -1UL;
- break;
- case GET_FUNCT3(INSN_MATCH_CSRRCI):
- wr_mask = rs1_num;
+ csr_num = riscv_insn_csrrsi_extract_csr(insn);
+ rd = riscv_insn_csrrsi_extract_xd(insn);
+ } else if (riscv_insn_is_csrrci(insn)) {
+ wr_mask = riscv_insn_csrrci_extract_imm(insn);
new_val = 0;
- break;
- default:
+ csr_num = riscv_insn_csrrci_extract_csr(insn);
+ rd = riscv_insn_csrrci_extract_xd(insn);
+ } else {
return rc;
}
+ #undef GET_REG
+
/* Save instruction decode info */
- vcpu->arch.csr_decode.insn = insn;
+ vcpu->arch.csr_decode.rd = rd;
+ vcpu->arch.csr_decode.insn_len = INSN_LEN(insn);
vcpu->arch.csr_decode.return_handled = 0;
/* Update CSR details in kvm_run struct */
@@ -228,43 +237,39 @@ static int csr_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, ulong insn)
static const struct insn_func system_opcode_funcs[] = {
{
- .mask = INSN_MASK_CSRRW,
- .match = INSN_MATCH_CSRRW,
+ .cmp = riscv_insn_is_csrrw,
.func = csr_insn,
},
{
- .mask = INSN_MASK_CSRRS,
- .match = INSN_MATCH_CSRRS,
+ .cmp = riscv_insn_is_csrrs,
.func = csr_insn,
},
{
- .mask = INSN_MASK_CSRRC,
- .match = INSN_MATCH_CSRRC,
+ .cmp = riscv_insn_is_csrrc,
.func = csr_insn,
},
{
- .mask = INSN_MASK_CSRRWI,
- .match = INSN_MATCH_CSRRWI,
+ .cmp = riscv_insn_is_csrrwi,
.func = csr_insn,
},
{
- .mask = INSN_MASK_CSRRSI,
- .match = INSN_MATCH_CSRRSI,
+ .cmp = riscv_insn_is_csrrsi,
.func = csr_insn,
},
{
- .mask = INSN_MASK_CSRRCI,
- .match = INSN_MATCH_CSRRCI,
+ .cmp = riscv_insn_is_csrrci,
.func = csr_insn,
},
{
- .mask = INSN_MASK_WFI,
- .match = INSN_MATCH_WFI,
+ .cmp = riscv_insn_is_wfi,
.func = wfi_insn,
},
{
- .mask = INSN_MASK_WRS,
- .match = INSN_MATCH_WRS,
+ .cmp = riscv_insn_is_wrs_nto,
+ .func = wrs_insn,
+ },
+ {
+ .cmp = riscv_insn_is_wrs_sto,
.func = wrs_insn,
},
};
@@ -277,7 +282,7 @@ static int system_opcode_insn(struct kvm_vcpu *vcpu, struct kvm_run *run,
for (i = 0; i < ARRAY_SIZE(system_opcode_funcs); i++) {
ifn = &system_opcode_funcs[i];
- if ((insn & ifn->mask) == ifn->match) {
+ if (ifn->cmp(insn)) {
rc = ifn->func(vcpu, run, insn);
break;
}
@@ -375,7 +380,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,
unsigned long htinst)
{
u8 data_buf[8];
- unsigned long insn;
+ unsigned long insn, rd;
int shift = 0, len = 0, insn_len = 0;
struct kvm_cpu_trap utrap = { 0 };
struct kvm_cpu_context *ct = &vcpu->arch.guest_context;
@@ -407,44 +412,47 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,
}
/* Decode length of MMIO and shift */
- if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
+ if (riscv_insn_is_lw(insn)) {
len = 4;
shift = 8 * (sizeof(ulong) - len);
- } else if ((insn & INSN_MASK_LB) == INSN_MATCH_LB) {
+ rd = riscv_insn_lw_extract_xd(insn);
+ } else if (riscv_insn_is_lb(insn)) {
len = 1;
shift = 8 * (sizeof(ulong) - len);
- } else if ((insn & INSN_MASK_LBU) == INSN_MATCH_LBU) {
+ rd = riscv_insn_lb_extract_xd(insn);
+ } else if (riscv_insn_is_lbu(insn)) {
len = 1;
-#ifdef CONFIG_64BIT
- } else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
+ rd = riscv_insn_lbu_extract_xd(insn);
+ } else if (riscv_insn_is_ld(insn)) {
len = 8;
shift = 8 * (sizeof(ulong) - len);
- } else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
+ rd = riscv_insn_ld_extract_xd(insn);
+ } else if (riscv_insn_is_lwu(insn)) {
len = 4;
-#endif
- } else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
+ rd = riscv_insn_lwu_extract_xd(insn);
+ } else if (riscv_insn_is_lh(insn)) {
len = 2;
shift = 8 * (sizeof(ulong) - len);
- } else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
+ rd = riscv_insn_lh_extract_xd(insn);
+ } else if (riscv_insn_is_lhu(insn)) {
len = 2;
-#ifdef CONFIG_64BIT
- } else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
+ rd = riscv_insn_lhu_extract_xd(insn);
+ } else if (riscv_insn_is_c_ld(insn)) {
len = 8;
shift = 8 * (sizeof(ulong) - len);
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ rd = riscv_insn_c_ld_extract_xd(insn);
+ } else if (riscv_insn_is_c_ldsp(insn)) {
len = 8;
shift = 8 * (sizeof(ulong) - len);
-#endif
- } else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
+ rd = riscv_insn_c_ldsp_extract_xd(insn);
+ } else if (riscv_insn_is_c_lw(insn)) {
len = 4;
shift = 8 * (sizeof(ulong) - len);
- insn = RVC_RS2S(insn) << SH_RD;
- } else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ rd = riscv_insn_c_lw_extract_xd(insn);
+ } else if (riscv_insn_is_c_lwsp(insn)) {
len = 4;
shift = 8 * (sizeof(ulong) - len);
+ rd = riscv_insn_c_lwsp_extract_xd(insn);
} else {
return -EOPNOTSUPP;
}
@@ -454,7 +462,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,
return -EIO;
/* Save instruction decode info */
- vcpu->arch.mmio_decode.insn = insn;
+ vcpu->arch.mmio_decode.rd = rd;
vcpu->arch.mmio_decode.insn_len = insn_len;
vcpu->arch.mmio_decode.shift = shift;
vcpu->arch.mmio_decode.len = len;
@@ -497,11 +505,7 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,
unsigned long fault_addr,
unsigned long htinst)
{
- u8 data8;
- u16 data16;
- u32 data32;
- u64 data64;
- ulong data;
+ ulong data, rs2;
unsigned long insn;
int len = 0, insn_len = 0;
struct kvm_cpu_trap utrap = { 0 };
@@ -533,35 +537,30 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,
insn_len = INSN_LEN(insn);
}
- data = GET_RS2(insn, &vcpu->arch.guest_context);
- data8 = data16 = data32 = data64 = data;
-
- if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {
+ if (riscv_insn_is_sw(insn)) {
len = 4;
- } else if ((insn & INSN_MASK_SB) == INSN_MATCH_SB) {
+ rs2 = riscv_insn_sw_extract_xs2(insn);
+ } else if (riscv_insn_is_sb(insn)) {
len = 1;
-#ifdef CONFIG_64BIT
- } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {
+ rs2 = riscv_insn_sb_extract_xs2(insn);
+ } else if (riscv_insn_is_sd(insn)) {
len = 8;
-#endif
- } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
+ rs2 = riscv_insn_sd_extract_xs2(insn);
+ } else if (riscv_insn_is_sh(insn)) {
len = 2;
-#ifdef CONFIG_64BIT
- } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
+ rs2 = riscv_insn_sh_extract_xs2(insn);
+ } else if (riscv_insn_is_c_sd(insn)) {
len = 8;
- data64 = GET_RS2S(insn, &vcpu->arch.guest_context);
- } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ rs2 = riscv_insn_c_sd_extract_xs2(insn);
+ } else if (riscv_insn_is_c_sdsp(insn)) {
len = 8;
- data64 = GET_RS2C(insn, &vcpu->arch.guest_context);
-#endif
- } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
+ rs2 = riscv_insn_c_sdsp_extract_xs2(insn);
+ } else if (riscv_insn_is_c_sw(insn)) {
len = 4;
- data32 = GET_RS2S(insn, &vcpu->arch.guest_context);
- } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
- ((insn >> SH_RD) & 0x1f)) {
+ rs2 = riscv_insn_c_sw_extract_xs2(insn);
+ } else if (riscv_insn_is_c_swsp(insn)) {
len = 4;
- data32 = GET_RS2C(insn, &vcpu->arch.guest_context);
+ rs2 = riscv_insn_c_swsp_extract_xs2(insn);
} else {
return -EOPNOTSUPP;
}
@@ -570,26 +569,24 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,
if (fault_addr & (len - 1))
return -EIO;
- /* Save instruction decode info */
- vcpu->arch.mmio_decode.insn = insn;
vcpu->arch.mmio_decode.insn_len = insn_len;
- vcpu->arch.mmio_decode.shift = 0;
- vcpu->arch.mmio_decode.len = len;
vcpu->arch.mmio_decode.return_handled = 0;
+ data = *((ulong *)(&vcpu->arch.guest_context) + rs2);
+
/* Copy data to kvm_run instance */
switch (len) {
case 1:
- *((u8 *)run->mmio.data) = data8;
+ *((u8 *)run->mmio.data) = data;
break;
case 2:
- *((u16 *)run->mmio.data) = data16;
+ *((u16 *)run->mmio.data) = data;
break;
case 4:
- *((u32 *)run->mmio.data) = data32;
+ *((u32 *)run->mmio.data) = data;
break;
case 8:
- *((u64 *)run->mmio.data) = data64;
+ *((u64 *)run->mmio.data) = data;
break;
default:
return -EOPNOTSUPP;
@@ -625,18 +622,13 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,
*/
int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
- u8 data8;
- u16 data16;
- u32 data32;
- u64 data64;
- ulong insn;
int len, shift;
+ unsigned long data;
if (vcpu->arch.mmio_decode.return_handled)
return 0;
vcpu->arch.mmio_decode.return_handled = 1;
- insn = vcpu->arch.mmio_decode.insn;
if (run->mmio.is_write)
goto done;
@@ -646,29 +638,23 @@ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
switch (len) {
case 1:
- data8 = *((u8 *)run->mmio.data);
- SET_RD(insn, &vcpu->arch.guest_context,
- (long)((ulong)data8 << shift) >> shift);
+ data = *((u8 *)run->mmio.data);
break;
case 2:
- data16 = *((u16 *)run->mmio.data);
- SET_RD(insn, &vcpu->arch.guest_context,
- (long)((ulong)data16 << shift) >> shift);
+ data = *((u16 *)run->mmio.data);
break;
case 4:
- data32 = *((u32 *)run->mmio.data);
- SET_RD(insn, &vcpu->arch.guest_context,
- (long)((ulong)data32 << shift) >> shift);
+ data = *((u32 *)run->mmio.data);
break;
case 8:
- data64 = *((u64 *)run->mmio.data);
- SET_RD(insn, &vcpu->arch.guest_context,
- (long)((ulong)data64 << shift) >> shift);
+ data = *((u64 *)run->mmio.data);
break;
default:
return -EOPNOTSUPP;
}
+ *((ulong *)(&vcpu->arch.guest_context) + vcpu->arch.mmio_decode.rd) =
+ (long)data << shift >> shift;
done:
/* Move to next instruction */
vcpu->arch.guest_context.sepc += vcpu->arch.mmio_decode.insn_len;
diff --git a/arch/riscv/kvm/vcpu_test_csr.c b/arch/riscv/kvm/vcpu_test_csr.c
new file mode 100644
index 00000000000000..b8aa503cdaba76
--- /dev/null
+++ b/arch/riscv/kvm/vcpu_test_csr.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_vcpu_insn.h>
+#include <asm/kvm_vcpu_test_csr.h>
+
+#define vcpu_to_test_csr(vcpu) (&(vcpu)->arch.test_csr)
+
+int kvm_riscv_vcpu_test_csr(struct kvm_vcpu *vcpu, unsigned int csr_num,
+ unsigned long *val, unsigned long new_val,
+ unsigned long wr_mask)
+{
+ struct kvm_test_csr *test_csr = vcpu_to_test_csr(vcpu);
+
+ *val = test_csr->val;
+
+ if (wr_mask)
+ test_csr->val = (test_csr->val & ~wr_mask) | (new_val & wr_mask);
+
+ return KVM_INSN_CONTINUE_NEXT_SEPC;
+}
diff --git a/arch/riscv/tools/Makefile b/arch/riscv/tools/Makefile
new file mode 100644
index 00000000000000..5f40439c12e9c1
--- /dev/null
+++ b/arch/riscv/tools/Makefile
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0
+
+gen := arch/$(ARCH)/include/generated/asm
+insn_tbl := $(src)/insn_tbl.sh
+insn := $(src)/insn.tbl
+
+gen-y := $(gen)/insn_gen.h
+
+targets += $(addprefix ../../../,$(gen-y))
+
+PHONY += insn
+
+insn: $(gen-y)
+
+# Create output directory if not already present
+$(shell mkdir -p $(gen))
+
+quiet_cmd_insn_tbl = INST_TBL $@
+ cmd_insn_tbl = $(CONFIG_SHELL) $(insn_tbl) $< $@
+
+$(gen)/insn_gen.h: $(insn) $(insn_tbl) FORCE
+ $(call if_changed,insn_tbl)
diff --git a/arch/riscv/tools/insn.tbl b/arch/riscv/tools/insn.tbl
new file mode 100644
index 00000000000000..5dc3392a5543c8
--- /dev/null
+++ b/arch/riscv/tools/insn.tbl
@@ -0,0 +1,1392 @@
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+#
+# GENERATED WITH https://github.com/riscv-software-src/riscv-unified-db
+# "./bin/generate inst-table -o test_table.txt"
+#
+# Each line of the instruction table should have the following format:
+# NAME BASE FIXED_BITS [VARIABLE_LIST]
+# NAME instruction name
+# BASE instruction base size (common[,(32|64)])
+# "common" means the instruction is valid on both architecture sizes
+# "32" or "64" means the instruction is valid on that size
+# if the instruction is valid on both architectures but has unique
+# encodings, use a 32-bit entry "common,32" and 64-bit entry
+# FIXED_BITS bitfields of the fixed bits of an instruction concatenated with '|'
+# continuous grouping of fixed bits are in the form of 'bits<offset'
+# VARIABLE_LIST a variable sized list of all variables in the instruction definition
+# in the form of name[~][<num][!num...]=(high[-low])|...
+# symbols after the name represent different modifiers:
+# ~ sign extension, can only appear once
+# < left shift by 'num' amount on extraction, can only appear once
+# ! mark 'num' as an invalid input for this variable
+andn common 0100000<25|111<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+clmul common 0000101<25|001<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+clmulh common 0000101<25|011<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+orn common 0100000<25|110<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+rev8 common,32 011010011000<20|101<12|0010011<0 xs1=19-15 xd=11-7
+rev8 common,64 011010111000<20|101<12|0010011<0 xs1=19-15 xd=11-7
+rol common 0110000<25|001<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+rolw 64 0110000<25|001<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+ror common 0110000<25|101<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+rori common,32 0110000<25|101<12|0010011<0 shamt=24-20 xs1=19-15 xd=11-7
+rori common,64 011000<26|101<12|0010011<0 shamt=25-20 xs1=19-15 xd=11-7
+roriw 64 0110000<25|101<12|0011011<0 shamt=24-20 xs1=19-15 xd=11-7
+rorw 64 0110000<25|101<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+xnor common 0100000<25|100<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+c.add common 1001<12|10<0 xs2!0=6-2 xd!0=11-7
+c.addi common 000<13|01<0 imm~!0=12|6-2 xd!0=11-7
+c.addi16sp common 011<13|00010<7|01<0 imm~!0<4=12|4-3|5|2|6
+c.addi4spn common 000<13|00<0 imm!0<2=10-7|12-11|5|6 xd=4-2
+c.addiw 64 001<13|01<0 imm~=12|6-2 xd!0=11-7
+c.addw 64 100111<10|01<5|01<0 xs2=4-2 xd=9-7
+c.and common 100011<10|11<5|01<0 xs2=4-2 xd=9-7
+c.andi common 100<13|10<10|01<0 imm~=12|6-2 xd=9-7
+c.beqz common 110<13|01<0 imm~<1=12|6-5|2|11-10|4-3 xs1=9-7
+c.bnez common 111<13|01<0 imm~<1=12|6-5|2|11-10|4-3 xs1=9-7
+c.ebreak common 1001000000000010<0
+c.j common 101<13|01<0 imm~<1=12|8|10-9|6|7|2|11|5-3
+c.jal 32 001<13|01<0 imm~<1=12|8|10-9|6|7|2|11|5-3
+c.jalr common 1001<12|0000010<0 xs1!0=11-7
+c.jr common 1000<12|0000010<0 xs1!0=11-7
+c.ld common,32 011<13|00<0 imm<3=6-5|12-10 xd!1!3!5!7=4-2 xs1=9-7
+c.ld common,64 011<13|00<0 imm<3=6-5|12-10 xd=4-2 xs1=9-7
+c.ldsp common,32 011<13|10<0 imm<3=4-2|12|6-5 xd!0!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=11-7
+c.ldsp common,64 011<13|10<0 imm<3=4-2|12|6-5 xd=11-7
+c.li common 010<13|01<0 imm~=12|6-2 xd!0=11-7
+c.lui common 011<13|01<0 imm~<12=12|6-2 xd!0!2=11-7
+c.lw common 010<13|00<0 imm<2=5|12-10|6 xd=4-2 xs1=9-7
+c.lwsp common 010<13|10<0 imm<2=3-2|12|6-4 xd!0=11-7
+c.mv common 1000<12|10<0 xd!0=11-7 xs2!0=6-2
+c.nop common 0000000000000001<0
+c.or common 100011<10|10<5|01<0 xs2=4-2 xd=9-7
+c.sd common,32 111<13|00<0 imm<3=6-5|12-10 xs2!1!3!5!7=4-2 xs1=9-7
+c.sd common,64 111<13|00<0 imm<3=6-5|12-10 xs2=4-2 xs1=9-7
+c.sdsp common,32 111<13|10<0 xs2!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=6-2 imm<3=9-7|12-10
+c.sdsp common,64 111<13|10<0 xs2=6-2 imm<3=9-7|12-10
+c.slli common,32 0000<12|10<0 shamt!0=6-2 xd=11-7
+c.slli common,64 000<13|10<0 shamt!0=12|6-2 xd=11-7
+c.srai common,32 100001<10|01<0 shamt!0=6-2 xd=9-7
+c.srai common,64 100<13|01<10|01<0 shamt!0=12|6-2 xd=9-7
+c.srli common,32 100000<10|01<0 shamt!0=6-2 xd=9-7
+c.srli common,64 100<13|00<10|01<0 shamt!0=12|6-2 xd=9-7
+c.sub common 100011<10|00<5|01<0 xs2=4-2 xd=9-7
+c.subw 64 100111<10|00<5|01<0 xs2=4-2 xd=9-7
+c.sw common 110<13|00<0 imm<2=5|12-10|6 xs2=4-2 xs1=9-7
+c.swsp common 110<13|10<0 imm<2=8-7|12-9 xs2=6-2
+c.xor common 100011<10|01<5|01<0 xs2=4-2 xd=9-7
+fadd.d common 0000001<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fclass.d common 111000100000<20|001<12|1010011<0 fs1=19-15 xd=11-7
+fcvt.d.l 64 110100100010<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.d.lu 64 110100100011<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.d.s common 010000100000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.d.w common 110100100000<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.d.wu common 110100100001<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.l.d 64 110000100010<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.lu.d 64 110000100011<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.s.d common 010000000001<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.w.d common 110000100000<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.wu.d common 110000100001<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvtmod.w.d common 110000101000<20|1010011<0 fs1=19-15 rm!0!2!3!4!5!6!7=14-12 xd=11-7
+fdiv.d common 0001101<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+feq.d common 1010001<25|010<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fld common 011<12|0000111<0 imm=31-20 xs1=19-15 fd=11-7
+fle.d common 1010001<25|000<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fleq.d common 1010001<25|100<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fli.d common 111100100001<20|000<12|1010011<0 xs1=19-15 fd=11-7
+flt.d common 1010001<25|001<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fltq.d common 1010001<25|101<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fmadd.d common 01<25|1000011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmax.d common 0010101<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmaxm.d common 0010101<25|011<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmin.d common 0010101<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fminm.d common 0010101<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmsub.d common 01<25|1000111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmul.d common 0001001<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmv.d.x 64 111100100000<20|000<12|1010011<0 xs1=19-15 fd=11-7
+fmv.x.d 64 111000100000<20|000<12|1010011<0 fs1=19-15 xd=11-7
+fmvh.x.d 32 111000100001<20|000<12|1010011<0 fs1=19-15 xd=11-7
+fmvp.d.x 32 1011001<25|000<12|1010011<0 xs2=24-20 xs1=19-15 fd=11-7
+fnmadd.d common 01<25|1001111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fnmsub.d common 01<25|1001011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fround.d common 010000100100<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+froundnx.d common 010000100101<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsd common 011<12|0100111<0 imm=31-25|11-7 fs2=24-20 xs1=19-15
+fsgnj.d common 0010001<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjn.d common 0010001<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjx.d common 0010001<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsqrt.d common 010110100000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsub.d common 0000101<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fadd.s common 0000000<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fclass.s common 111000000000<20|001<12|1010011<0 fs1=19-15 xd=11-7
+fcvt.l.s 64 110000000010<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.lu.s 64 110000000011<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.s.l 64 110100000010<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.s.lu 64 110100000011<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.s.w common 110100000000<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.s.wu common 110100000001<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.w.s common 110000000000<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.wu.s common 110000000001<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fdiv.s common 0001100<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+feq.s common 1010000<25|010<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fle.s common 1010000<25|000<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fleq.s common 1010000<25|100<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+flt.s common 1010000<25|001<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fltq.s common 1010000<25|101<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+flw common 010<12|0000111<0 imm=31-20 xs1=19-15 fd=11-7
+fmadd.s common 00<25|1000011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmax.s common 0010100<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmin.s common 0010100<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmsub.s common 00<25|1000111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmul.s common 0001000<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmv.w.x common 111100000000<20|000<12|1010011<0 xs1=19-15 fd=11-7
+fmv.x.w common 111000000000<20|000<12|1010011<0 fs1=19-15 xd=11-7
+fnmadd.s common 00<25|1001111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fnmsub.s common 00<25|1001011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fsgnj.s common 0010000<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjn.s common 0010000<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjx.s common 0010000<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsqrt.s common 010110000000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsub.s common 0000100<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fsw common 010<12|0100111<0 imm=31-25|11-7 fs2=24-20 xs1=19-15
+hfence.gvma common 0110001<25|000000001110011<0 xs2=24-20 xs1=19-15
+hfence.vvma common 0010001<25|000000001110011<0 xs2=24-20 xs1=19-15
+hlv.b common 011000000000<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.bu common 011000000001<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.d 64 011011000000<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.h common 011001000000<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.hu common 011001000001<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.w common 011010000000<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.wu 64 011010000001<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlvx.hu common 011001000011<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlvx.wu common 011010000011<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hsv.b common 0110001<25|100000001110011<0 xs2=24-20 xs1=19-15
+hsv.d 64 0110111<25|100000001110011<0 xs2=24-20 xs1=19-15
+hsv.h common 0110011<25|100000001110011<0 xs2=24-20 xs1=19-15
+hsv.w common 0110101<25|100000001110011<0 xs2=24-20 xs1=19-15
+add common 0000000<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+addi common 000<12|0010011<0 imm~=31-20 xs1=19-15 xd=11-7
+addiw 64 000<12|0011011<0 imm~=31-20 xs1=19-15 xd=11-7
+addw 64 0000000<25|000<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+and common 0000000<25|111<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+andi common 111<12|0010011<0 imm~=31-20 xs1=19-15 xd=11-7
+auipc common 0010111<0 imm~<12=31-12 xd=11-7
+beq common 000<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+bge common 101<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+bgeu common 111<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+blt common 100<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+bltu common 110<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+bne common 001<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+ebreak common 00000000000100000000000001110011<0
+ecall common 00000000000000000000000001110011<0
+fence.tso common 100000110011<20|000<12|0001111<0 xs1=19-15 xd=11-7
+fence common 000<12|0001111<0 fm=31-28 pred=27-24 succ=23-20 xs1=19-15 xd=11-7
+jal common 1101111<0 imm~<1=31|19-12|20|30-21 xd=11-7
+jalr common 000<12|1100111<0 imm~=31-20 xs1=19-15 xd=11-7
+lb common 000<12|0000011<0 imm~=31-20 xs1=19-15 xd=11-7
+lbu common 100<12|0000011<0 imm~=31-20 xs1=19-15 xd=11-7
+ld common,32 011<12|0000011<0 imm~=31-20 xs1=19-15 xd!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=11-7
+ld common,64 011<12|0000011<0 imm~=31-20 xs1=19-15 xd=11-7
+lh common 001<12|0000011<0 imm~=31-20 xs1=19-15 xd=11-7
+lhu common 101<12|0000011<0 imm~=31-20 xs1=19-15 xd=11-7
+lui common 0110111<0 imm~<12=31-12 xd=11-7
+lw common 010<12|0000011<0 imm~=31-20 xs1=19-15 xd=11-7
+lwu 64 110<12|0000011<0 imm~=31-20 xs1=19-15 xd=11-7
+mret common 00110000001000000000000001110011<0
+or common 0000000<25|110<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+ori common 110<12|0010011<0 imm~=31-20 xs1=19-15 xd=11-7
+sb common 000<12|0100011<0 imm~=31-25|11-7 xs2=24-20 xs1=19-15
+sd common,32 011<12|0100011<0 imm~=31-25|11-7 xs2!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=24-20 xs1=19-15
+sd common,64 011<12|0100011<0 imm~=31-25|11-7 xs2=24-20 xs1=19-15
+sh common 001<12|0100011<0 imm~=31-25|11-7 xs2=24-20 xs1=19-15
+sll common 0000000<25|001<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+slli common,32 0000000<25|001<12|0010011<0 shamt=24-20 xs1=19-15 xd=11-7
+slli common,64 000000<26|001<12|0010011<0 shamt=25-20 xs1=19-15 xd=11-7
+slliw 64 0000000<25|001<12|0011011<0 shamt=24-20 xs1=19-15 xd=11-7
+sllw 64 0000000<25|001<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+slt common 0000000<25|010<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+slti common 010<12|0010011<0 imm~=31-20 xs1=19-15 xd=11-7
+sltiu common 011<12|0010011<0 imm~=31-20 xs1=19-15 xd=11-7
+sltu common 0000000<25|011<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sra common 0100000<25|101<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+srai common,32 0100000<25|101<12|0010011<0 shamt=24-20 xs1=19-15 xd=11-7
+srai common,64 010000<26|101<12|0010011<0 shamt=25-20 xs1=19-15 xd=11-7
+sraiw 64 0100000<25|101<12|0011011<0 shamt=24-20 xs1=19-15 xd=11-7
+sraw 64 0100000<25|101<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+srl common 0000000<25|101<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+srli common,32 0000000<25|101<12|0010011<0 shamt=24-20 xs1=19-15 xd=11-7
+srli common,64 000000<26|101<12|0010011<0 shamt=25-20 xs1=19-15 xd=11-7
+srliw 64 0000000<25|101<12|0011011<0 shamt=24-20 xs1=19-15 xd=11-7
+srlw 64 0000000<25|101<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+sub common 0100000<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+subw 64 0100000<25|000<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+sw common 010<12|0100011<0 imm~=31-25|11-7 xs2=24-20 xs1=19-15
+wfi common 00010000010100000000000001110011<0
+xor common 0000000<25|100<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+xori common 100<12|0010011<0 imm~=31-20 xs1=19-15 xd=11-7
+div common 0000001<25|100<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+divu common 0000001<25|101<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+divuw 64 0000001<25|101<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+divw 64 0000001<25|100<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+mul common 0000001<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mulh common 0000001<25|001<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mulhsu common 0000001<25|010<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mulhu common 0000001<25|011<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mulw 64 0000001<25|000<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+rem common 0000001<25|110<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+remu common 0000001<25|111<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+remuw 64 0000001<25|111<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+remw 64 0000001<25|110<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+fadd.q common 0000011<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fclass.q common 111001100000<20|001<12|1010011<0 fs1=19-15 xd=11-7
+fcvt.d.q common 010000100011<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.h.q common 010001000011<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.l.q 64 110001100010<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.lu.q 64 110001100011<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.q.d common 010001100001<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.q.h common 010001100010<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.q.l 64 110101100010<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.q.lu 64 110101100011<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.q.s common 010001100000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.q.w common 110101100000<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.q.wu common 110101100001<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.s.q common 010000000011<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.w.q common 110001100000<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.wu.q common 110001100001<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fdiv.q common 0001111<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+feq.q common 1010011<25|010<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fle.q common 1010011<25|000<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fleq.q common 1010011<25|100<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fli.q common 111101100001<20|000<12|1010011<0 xs1=19-15 fd=11-7
+flq common 100<12|0000111<0 imm=31-20 xs1=19-15 fd=11-7
+flt.q common 1010011<25|001<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fltq.q common 1010011<25|101<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmadd.q common 11<25|1000011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmax.q common 0010111<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmaxm.q common 0010111<25|011<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmin.q common 0010111<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fminm.q common 0010111<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmsub.q common 11<25|1000111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmul.q common 0001011<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmvh.x.q 64 111001100001<20|000<12|1010011<0 fs1=19-15 xd=11-7
+fmvp.q.x 64 1011011<25|000<12|1010011<0 xs2=24-20 xs1=19-15 fd=11-7
+fnmadd.q common 11<25|1001111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fnmsub.q common 11<25|1001011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fround.q common 010001100100<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+froundnx.q common 010001100101<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsgnj.q common 0010011<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjn.q common 0010011<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjx.q common 0010011<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsq common 100<12|0100111<0 imm=31-25|11-7 fs2=24-20 xs1=19-15
+fsqrt.q common 010111100000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsub.q common 0000111<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+sfence.vma common 0001001<25|000000001110011<0 xs2=24-20 xs1=19-15
+sret common 00010000001000000000000001110011<0
+dret common 01111011001000000000000001110011<0
+sctrclr common 00010000010000000000000001110011<0
+mnret common 01110000001000000000000001110011<0
+hinval.gvma common 0110011<25|000000001110011<0 xs2=24-20 xs1=19-15
+hinval.vvma common 0010011<25|000000001110011<0 xs2=24-20 xs1=19-15
+sfence.inval.ir common 00011000000100000000000001110011<0
+sfence.w.inval common 00011000000000000000000001110011<0
+sinval.vma common 0001011<25|000000001110011<0 xs2=24-20 xs1=19-15
+vaadd.vv common 001001<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vaadd.vx common 001001<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vaaddu.vv common 001000<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vaaddu.vx common 001000<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vadc.vim common 0100000<25|011<12|1010111<0 vs2=24-20 imm~=19-15 vd=11-7
+vadc.vvm common 0100000<25|000<12|1010111<0 vs2=24-20 vs1=19-15 vd=11-7
+vadc.vxm common 0100000<25|100<12|1010111<0 vs2=24-20 xs1=19-15 vd=11-7
+vadd.vi common 000000<26|011<12|1010111<0 vm=25-25 vs2=24-20 imm~=19-15 vd=11-7
+vadd.vv common 000000<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vadd.vx common 000000<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vand.vi common 001001<26|011<12|1010111<0 vm=25-25 vs2=24-20 imm~=19-15 vd=11-7
+vand.vv common 001001<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vand.vx common 001001<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vasub.vv common 001011<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vasub.vx common 001011<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vasubu.vv common 001010<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vasubu.vx common 001010<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vcompress.vm common 0101111<25|010<12|1010111<0 vs2=24-20 vs1=19-15 vd=11-7
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+packw 64 0000100<25|100<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+unzip 32 000010001111<20|101<12|0010011<0 xs1=19-15 xd=11-7
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+fnmadd.h common 10<25|1001111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fnmsub.h common 10<25|1001011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fround.h common 010001000100<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
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+fsgnjn.h common 0010010<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
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+fsh common 001<12|0100111<0 imm=31-25|11-7 xs1=19-15 fs2=24-20
+fsqrt.h common 010111000000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
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+prefetch.w common 00011<20|110000000010011<0 imm~<5=31-25 xs1=19-15
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+ssamoswap.w common 01001<27|010<12|0101111<0 aq=26-26 rl=25-25 xs2=24-20 xs1=19-15 xd=11-7
+sspopchk.x1 common 11001101110000001100000001110011<0
+sspopchk.x5 common 11001101110000101100000001110011<0
+sspush.x1 common 11001110000100000100000001110011<0
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+mop.r.1 common 100000011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
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+mop.r.11 common 100010011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.12 common 100011011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
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+mop.r.19 common 110000011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.2 common 100000011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.20 common 110001011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.21 common 110001011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.22 common 110001011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.23 common 110001011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.24 common 110010011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.25 common 110010011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.26 common 110010011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.27 common 110010011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.28 common 110011011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.29 common 110011011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.3 common 100000011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.30 common 110011011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.31 common 110011011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.4 common 100001011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.5 common 100001011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.6 common 100001011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.7 common 100001011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.8 common 100010011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.9 common 100010011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.rr.0 common 1000001<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.1 common 1000011<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.2 common 1000101<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.3 common 1000111<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.4 common 1100001<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.5 common 1100011<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.6 common 1100101<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.7 common 1100111<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
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+aes64ks2 64 0111111<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes32dsi 32 10101<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+aes32dsmi 32 10111<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+aes64ds 64 0011101<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes64dsm 64 0011111<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes64im 64 001100000000<20|001<12|0010011<0 xs1=19-15 xd=11-7
+aes32esi 32 10001<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+aes32esmi 32 10011<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+aes64es 64 0011001<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes64esm 64 0011011<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha256sig0 common 000100000010<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha256sig1 common 000100000011<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha256sum0 common 000100000000<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha256sum1 common 000100000001<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sig0 64 000100000110<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sig0h 32 0101110<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sig0l 32 0101010<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sig1 64 000100000111<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sig1h 32 0101111<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sig1l 32 0101011<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sum0 64 000100000100<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sum0r 32 0101000<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sum1 64 000100000101<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sum1r 32 0101001<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sm3p0 common 000100001000<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sm3p1 common 000100001001<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sm4ed common 11000<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+sm4ks common 11010<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+vandn.vv common 000001<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vandn.vx common 000001<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vbrev.v common 010010<26|01010010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vbrev8.v common 010010<26|01000010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vclz.v common 010010<26|01100010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vcpop.v common 010010<26|01110010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vctz.v common 010010<26|01101010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vrev8.v common 010010<26|01001010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vrol.vv common 010101<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vrol.vx common 010101<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vror.vi common 01010<27|011<12|1010111<0 imm=26|19-15 vm=25-25 vs2=24-20 vd=11-7
+vror.vv common 010100<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vror.vx common 010100<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vwsll.vi common 110101<26|011<12|1010111<0 vm=25-25 vs2=24-20 imm=19-15 vd=11-7
+vwsll.vv common 110101<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vwsll.vx common 110101<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vclmul.vv common 001100<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vclmul.vx common 001100<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vclmulh.vv common 001101<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vclmulh.vx common 001101<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vfncvtbf16.f.f.w common 010010<26|11101001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfwcvtbf16.f.f.v common 010010<26|01101001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfwmaccbf16.vf common 111011<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfwmaccbf16.vv common 111011<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vghsh.vv common 1011001<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vgmul.vv common 1010001<25|10001010<12|1110111<0 vs2=24-20 vd=11-7
+vaesdf.vs common 1010011<25|00001010<12|1110111<0 vs2=24-20 vd=11-7
+vaesdf.vv common 1010001<25|00001010<12|1110111<0 vs2=24-20 vd=11-7
+vaesdm.vs common 1010011<25|00000010<12|1110111<0 vs2=24-20 vd=11-7
+vaesdm.vv common 1010001<25|00000010<12|1110111<0 vs2=24-20 vd=11-7
+vaesef.vs common 1010011<25|00011010<12|1110111<0 vs2=24-20 vd=11-7
+vaesef.vv common 1010001<25|00011010<12|1110111<0 vs2=24-20 vd=11-7
+vaesem.vs common 1010011<25|00010010<12|1110111<0 vs2=24-20 vd=11-7
+vaesem.vv common 1010001<25|00010010<12|1110111<0 vs2=24-20 vd=11-7
+vaeskf1.vi common 1000101<25|010<12|1110111<0 vs2=24-20 imm=19-15 vd=11-7
+vaeskf2.vi common 1010101<25|010<12|1110111<0 vs2=24-20 imm=19-15 vd=11-7
+vaesz.vs common 1010011<25|00111010<12|1110111<0 vs2=24-20 vd=11-7
+vsha2ch.vv common 1011101<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vsha2cl.vv common 1011111<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vsha2ms.vv common 1011011<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vsm3c.vi common 1010111<25|010<12|1110111<0 vs2=24-20 imm=19-15 vd=11-7
+vsm3me.vv common 1000001<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vsm4k.vi common 1000011<25|010<12|1110111<0 vs2=24-20 imm=19-15 vd=11-7
+vsm4r.vs common 1010011<25|10000010<12|1110111<0 vs2=24-20 vd=11-7
+vsm4r.vv common 1010001<25|10000010<12|1110111<0 vs2=24-20 vd=11-7
+
diff --git a/arch/riscv/tools/insn_tbl.sh b/arch/riscv/tools/insn_tbl.sh
new file mode 100755
index 00000000000000..aede14c80146fa
--- /dev/null
+++ b/arch/riscv/tools/insn_tbl.sh
@@ -0,0 +1,256 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Generate riscv instruction helper header.
+# The generated helpers for each instruction are:
+# - riscv_insn_<insn>_MASK useful to help check if arbitrary binary is <insn>
+# - riscv_insn_<insn>_MATCH useful to help check if arbitrary binary is <insn>
+# - riscv_insn_<insn> useful to construct <insn>
+# - riscv_insn_<insn>_<var> useful to extract <var> from <insn>
+#
+# Each line of the instruction table should have the following format:
+# NAME BASE FIXED_BITS [VARIABLE_LIST]
+# NAME instruction name
+# BASE instruction base size (common[,(32|64)])
+# "common" means the instruction is valid on both architecture sizes
+# "32" or "64" means the instruction is valid on that size
+# if the instruction is valid on both architectures but has unique
+# encodings, use a 32-bit entry "common,32" and 64-bit entry
+# FIXED_BITS bitfields of the fixed bits of an instruction concatenated with '|'
+# continuous grouping of fixed bits are in the form of 'bits<offset'
+# VARIABLE_LIST a variable sized list of all variables in the instruction definition
+# in the form of name[~][<num][!num...]=(high[-low])|...
+# symbols after the name represent different modifiers:
+# ~ sign extension, can only appear once
+# < left shift by 'num' amount on extraction, can only appear once
+# ! mark 'num' as an invalid input for this variable#
+
+set -e
+
+usage() {
+ echo >&2 "usage: $0 BASE INFILE OUTFILE" >&2
+ echo >&2
+ echo >&2 " INFILE input instruction table"
+ echo >&2 " OUTFILE output header file"
+ exit 1
+}
+
+if [ $# -ne 2 ]; then
+ usage
+fi
+
+infile="$1"
+outfile="$2"
+
+file=$(readlink -f $0)
+
+echo "/* Auto-generated rv${base} header from script arch/${file#*arch/} */" > $outfile
+
+echo "#ifndef RISCV_INSN_GEN_H" >> $outfile
+echo "#define RISCV_INSN_GEN_H" >> $outfile
+echo >> $outfile
+
+printf "#include <linux/bits.h>" >> $outfile
+echo >> $outfile
+
+grep -E "^[a-z\.0-9]+[[:space:]]+" "$infile" | {
+ while read name base fixed variables; do
+ echo "/* $name */"
+
+ non_compressed_insn=${name##c.*}
+ invalid_inst_functions=""
+ variable_params=""
+ constraints=""
+ match=""
+ mask=""
+ make=""
+
+ # All compressed instructions start with "c."
+ size=${non_compressed_insn:+32};
+ size=${size:-16};
+
+ # Replace all . with _
+ formatted_inst_name=$name
+ while [ ! ${formatted_inst_name##*.*} ]; do
+ prefix=${formatted_inst_name%.*}
+ suffix=${formatted_inst_name##*.}
+ contains_dot=${formatted_inst_name##*.*}
+ formatted_inst_name=${contains_dot:-${prefix}_${suffix}}
+ done
+
+ # Collect all fixed bits of an instruction
+ OLD_IFS=$IFS
+ IFS='|'
+ for segment in $fixed; do
+ bits=${segment%<*}
+ offset=${segment#*<}
+
+ len=${#bits}
+
+ mask="${mask} | 0b"
+
+ while [ $len -gt 0 ]; do
+ len=$((len - 1))
+ mask=${mask}1
+ done
+
+ if [ ${offset} -gt 0 ]; then
+ s=" << ${offset}"
+ else
+ s=""
+ fi
+
+ mask="${mask}${s}"
+
+ match="${match} | 0b${bits}${s}"
+ done
+ IFS=$OLD_IFS
+
+ # Instruction only appears in one base
+ only_base=
+ if [ "${base}" != "${base%32}" ]; then
+ echo "#if __riscv_xlen == 32"
+ only_base=32
+ elif [ "${base}" != "${base%64}" ]; then
+ echo "#if __riscv_xlen == 64"
+ only_base=64
+ fi
+
+ # Standard name for the instruction parameter in generated functions
+ insn="_insn"
+
+ for variable in ${variables}; do
+ variable_name="${variable%%[<~=!]*}"
+ parts="${variable#*=}"
+ insert_mask=""
+ sign_extend=""
+ left_shift=""
+ extract=""
+ insert=""
+
+ # Standard name for the variable parameter in generated functions
+ var="_${variable_name}"
+ variable_params="${variable_params}u32 ${var}, "
+
+ if [ "${variable}" != "${variable#*~}" ]; then
+ sign_extend="1"
+ fi
+
+ if [ "${variable}" != "${variable#*<}" ]; then
+ left_shift="${variable#*<}"
+ left_shift="${left_shift%%[=<~!]*}"
+ else
+ left_shift="0"
+ fi
+
+ if [ "${variable}" != "${variable#*!}" ]; then
+ raw_constraints="${variable#*!}"
+ raw_constraints="${raw_constraints%%[=<~!]**}"
+
+ OLD_IFS=$IFS
+ IFS='!'
+ for constraint in $raw_constraints; do
+ constraints="${constraints}(riscv_insn_${formatted_inst_name}_extract_${variable_name}(${insn}) != ${constraint}) && "
+ done
+ IFS=$OLD_IFS
+ fi
+
+ offset=0
+ while true; do
+ part=${parts##*|}
+
+ if [ "${part#*-}" = "${part}" ]; then
+ high="${part}"
+ low="${part}"
+ len=1
+ else
+ high="${part%-*}"
+ low="${part#*-}"
+ len=$((high - low + 1))
+ fi
+
+ # Don't emit shift if 0
+ first_shift=${low}
+ if [ "${first_shift}" = "0" ]; then
+ first_shift=
+ fi
+
+ second_shift=$((offset + left_shift))
+ if [ "${second_shift}" = "0" ]; then
+ second_shift=
+ fi
+
+ extract="${extract} | ((${insn}${first_shift:+ >> }${first_shift} & GENMASK($((len - 1)), 0))${second_shift:+ << }${second_shift})"
+ insert_mask="${insert_mask} & ~GENMASK(${high}, ${low})"
+ insert="${insert} | (((${var}${second_shift:+ >> }${second_shift}) & GENMASK($((len - 1)), 0))${first_shift:+ << }${first_shift})"
+ offset=$((offset + len))
+
+ if [ "${parts}" = "${part}" ]; then
+ # Processed all parts of variable
+ break
+ fi
+
+ parts=${parts%|*}
+ done
+
+ extract="${extract# | }"
+
+ if [ ${sign_extend} ]; then
+ extract="sign_extend32(${extract}, $((offset + left_shift - 1)))"
+ type="s"
+ else
+ type="u"
+ fi
+
+ printf "static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn})\n"
+ printf "{\n"
+ printf "\treturn ${extract};\n"
+ printf "}\n"
+ printf "static __always_inline void riscv_insn_${formatted_inst_name}_insert_${variable_name}(u${size} *${insn}, ${type}32 ${var})\n"
+ printf "{\n"
+ printf "\t*_insn &= ${insert_mask# & };\n"
+ printf "\t*_insn |= ${insert# | };\n"
+ printf "}\n"
+
+ if [ "${only_base}" ]; then
+ invalid_inst_functions="${invalid_inst_functions}static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn}) {\n\tBUILD_BUG_ON_MSG(1, \"${name} is not supported on non ${only_base}-bit systems.\");\n}\n"
+ fi
+
+ make="${make} riscv_insn_${formatted_inst_name}_insert_${variable_name}(&${insn}, ${var});\n"
+ done
+
+ variable_params="${variable_params%, }"
+ variable_params="${variable_params:-void}"
+
+ printf "#define riscv_insn_${formatted_inst_name}_MASK (${mask# | })\n"
+ printf "#define riscv_insn_${formatted_inst_name}_MATCH (${match# | })\n"
+ printf "static __always_inline u${size} riscv_insn_${formatted_inst_name}(${variable_params})\n"
+ printf "{\n"
+ printf "\tu${size} ${insn} = riscv_insn_${formatted_inst_name}_MATCH;\n"
+ printf "${make} return ${insn};\n"
+ printf "}\n"
+
+ # Check against instructions that have a variable that may contain invalid values
+ if [ "$constraints" ]; then
+ printf "__RISCV_INSN_FUNCS_CONSTRAINED(${formatted_inst_name}, ${constraints% && });\n"
+ else
+ printf "__RISCV_INSN_FUNCS(${formatted_inst_name});\n"
+ fi
+
+ # If common does not appear in the base, then this instruction only appears in one base
+ if [ "$base" = "${base#common}" ]; then
+ printf "#else\n"
+ printf "__RISCV_INSN_FUNCS_UNSUPPORTED(${formatted_inst_name});\n"
+ printf "${invalid_inst_functions%\\n}\n"
+ fi
+
+ # Instruction has a base variant
+ if [ "$base" != "${base%[24]}" ]; then
+ echo "#endif"
+ fi
+
+ echo
+ done
+
+ echo "#endif /* RISCV_INST_GEN_H */"
+} >> $outfile
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 6c8afa2047bf33..abbbf74627a24d 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1235,6 +1235,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_LOONGARCH_DMSINTC KVM_DEV_TYPE_LOONGARCH_DMSINTC
KVM_DEV_TYPE_ARM_VGIC_V5,
#define KVM_DEV_TYPE_ARM_VGIC_V5 KVM_DEV_TYPE_ARM_VGIC_V5
+ KVM_DEV_TYPE_TEST,
+#define KVM_DEV_TYPE_TEST KVM_DEV_TYPE_TEST
KVM_DEV_TYPE_MAX,
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 8ff5adcfe1e0a2..0d235bdc94ec38 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -754,6 +754,12 @@ source "net/Kconfig.debug"
endmenu # "Networking Debugging"
+menu "KVM Debugging"
+
+source "virt/kvm/Kconfig.debug"
+
+endmenu # "KVM Debugging"
+
menu "Memory Debugging"
source "mm/Kconfig.debug"
diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selftests/kvm/Makefile.kvm
index 9118a5a51b89fd..88ccd15e8f9415 100644
--- a/tools/testing/selftests/kvm/Makefile.kvm
+++ b/tools/testing/selftests/kvm/Makefile.kvm
@@ -212,8 +212,10 @@ TEST_GEN_PROGS_s390 += s390/irq_routing
TEST_GEN_PROGS_s390 += mmu_stress_test
TEST_GEN_PROGS_riscv = $(TEST_GEN_PROGS_COMMON)
+TEST_GEN_PROGS_riscv += riscv/csr_test
TEST_GEN_PROGS_riscv += riscv/sbi_pmu_test
TEST_GEN_PROGS_riscv += riscv/ebreak_test
+TEST_GEN_PROGS_riscv += riscv/mmio_test
TEST_GEN_PROGS_riscv += access_tracking_perf_test
TEST_GEN_PROGS_riscv += arch_timer
TEST_GEN_PROGS_riscv += coalesced_io_test
diff --git a/tools/testing/selftests/kvm/riscv/csr_test.c b/tools/testing/selftests/kvm/riscv/csr_test.c
new file mode 100644
index 00000000000000..b3e8b99b6e9236
--- /dev/null
+++ b/tools/testing/selftests/kvm/riscv/csr_test.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * csr_test.c - Tests the csr functionality.
+ */
+#include "kvm_util.h"
+#include "ucall_common.h"
+
+#define CSR_TEST 0x240
+#define FP 0x00006000
+
+/*
+ * Use the fcsr as a U-mode accesible csr and compare against the custom 'test'
+ * hypervisor csr (currently using vsscratch)
+ */
+#define test_csr(write, initial, mode) \
+static void test_##write(void) \
+{ \
+ unsigned long hypervisor_result, reference_result, old_hypervisor; \
+ unsigned long mask = 0x15; \
+ asm volatile ( \
+ "csrs sstatus, %[enable_fp]\n" \
+ "csrw fcsr, %[init]\n" \
+ #write" zero, fcsr, %[mask]\n" \
+ "csrr %[ref_res], fcsr\n" \
+ : [ref_res] "=&r" (reference_result) \
+ : [enable_fp] "r" (FP), [mask] #mode(mask), [init] "r" (initial) \
+ : "memory" \
+ ); \
+ asm volatile ( \
+ "csrw %[test_csr], %[init]\n" \
+ #write" %[old], %[test_csr], %[mask]\n" \
+ "csrr %[hyp_res], %[test_csr]\n" \
+ : [hyp_res] "=&r" (hypervisor_result), [old] "=&r" (old_hypervisor) \
+ : [test_csr] "i"(CSR_TEST), [mask] #mode(mask), [init] "r" (initial) \
+ : "memory" \
+ ); \
+ /* Check that writing works */ \
+ GUEST_ASSERT_EQ(reference_result, hypervisor_result); \
+ /* Check that reading works */ \
+ GUEST_ASSERT_EQ(old_hypervisor, initial); \
+ GUEST_DONE(); \
+}
+
+test_csr(csrrw, 0x0, r)
+test_csr(csrrs, 0x0, r)
+test_csr(csrrc, 0x15, r)
+test_csr(csrrwi, 0x0, i)
+test_csr(csrrsi, 0x0, i)
+test_csr(csrrci, 0x15, i)
+
+static void run(void *guest_code, char *instruction)
+{
+ struct ucall uc;
+ struct kvm_vm *vm;
+ struct kvm_vcpu *vcpu;
+
+ vm = vm_create_with_one_vcpu(&vcpu, guest_code);
+
+ kvm_create_device(vm, KVM_DEV_TYPE_TEST);
+
+ vcpu_run(vcpu);
+
+ TEST_ASSERT(get_ucall(vcpu, &uc) == UCALL_DONE,
+ "CSR instruction '%s' failed: '%s'", instruction,
+ uc.buffer);
+
+ kvm_vm_free(vm);
+}
+
+static void check_test_csr_guest(void)
+{
+ unsigned long scause, stvec;
+
+ asm volatile(
+ "la %[stvec], 1f\n"
+ "csrw stvec, %[stvec]\n"
+ "csrwi %[test_csr], 0x0\n"
+ "1:\n"
+ "csrr %[scause], scause\n"
+ : [scause] "=&r" (scause), [stvec] "=&r" (stvec)
+ : [test_csr] "i" (CSR_TEST)
+ );
+
+ /* An illegal instruction will be generated if CONFIG_RISCV_KVM_TEST_CSR is not enabled. */
+ if (scause == 2)
+ GUEST_FAIL("CONFIG_RISCV_KVM_TEST_CSR not enabled.\n");
+ GUEST_DONE();
+}
+
+static int check_test_csr(void)
+{
+ struct ucall uc;
+ struct kvm_vm *vm;
+ struct kvm_vcpu *vcpu;
+ int success;
+
+ vm = vm_create_with_one_vcpu(&vcpu, check_test_csr_guest);
+
+ /* Skip if CONFIG_KVM_MMIO_TEST not enabled */
+ if (!kvm_create_device(vm, KVM_DEV_TYPE_TEST))
+ exit(KSFT_SKIP);
+
+ vcpu_run(vcpu);
+
+ success = get_ucall(vcpu, &uc) == UCALL_DONE;
+
+ kvm_vm_free(vm);
+
+ return success;
+}
+
+int main(void)
+{
+ /* Skip if CONFIG_RISCV_KVM_TEST_CSR not enabled */
+ if (!check_test_csr())
+ exit(KSFT_SKIP);
+
+ run(test_csrrw, "csrrw");
+ run(test_csrrs, "csrrs");
+ run(test_csrrc, "csrrc");
+ run(test_csrrwi, "csrrwi");
+ run(test_csrrsi, "csrrsi");
+ run(test_csrrci, "csrrci");
+
+ return 0;
+}
diff --git a/tools/testing/selftests/kvm/riscv/mmio_test.c b/tools/testing/selftests/kvm/riscv/mmio_test.c
new file mode 100644
index 00000000000000..9726860a269a3f
--- /dev/null
+++ b/tools/testing/selftests/kvm/riscv/mmio_test.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * mmio_test.c - Tests the mmio functionality.
+ */
+#include "kvm_util.h"
+#include "ucall_common.h"
+
+#define MMIO_TEST_REGION 0x20000000
+
+#define test_standard_read(len, instruction, name, options) \
+static void test_##name(void) \
+{ \
+ unsigned long mmio_result, reference_result; \
+ /* Configure the MMIO to return 0xff for each byte to check sign extension */ \
+ unsigned long reference = ((unsigned long)-1 >> ((sizeof(long) - len) * 8)); \
+ *((unsigned long *)MMIO_TEST_REGION) = reference; \
+ /* Check that reads through MMIO are equivalent to standard reads. */ \
+ asm volatile ( \
+ ".option push\n" \
+ options \
+ #instruction " %[mmio_res], 0(%[region])\n" \
+ #instruction " %[ref_res], 0(%[ref])\n" \
+ ".option pop\n" \
+ : [mmio_res] "=&cr" (mmio_result), [ref_res] "=&cr" (reference_result) \
+ : [region] "cr" (MMIO_TEST_REGION), [ref] "cr" (&reference) \
+ ); \
+ GUEST_ASSERT_EQ(mmio_result, reference_result); \
+ GUEST_DONE(); \
+}
+
+#define test_sp_read(len, instruction, name) \
+static void test_##name(void) \
+{ \
+ unsigned long mmio_result, reference_result; \
+ unsigned long tmp; \
+ /* Configure the MMIO to return 0xff for each byte to check sign extension */ \
+ unsigned long reference = ((unsigned long)-1 >> ((sizeof(long) - len) * 8)); \
+ *(((unsigned long *)MMIO_TEST_REGION)) = reference; \
+ /* Check that reads through MMIO are equivalent to standard reads. */ \
+ asm volatile ( \
+ "mv %[tmp], sp\n" \
+ "mv sp, %[region]\n" \
+ ".option push\n" \
+ ".option arch,+c\n" \
+ #instruction " %[mmio_res], 0(sp)\n" \
+ "mv sp, %[ref]\n" \
+ #instruction " %[ref_res], 0(sp)\n" \
+ ".option pop\n" \
+ "mv sp, %[tmp]\n" \
+ : [mmio_res] "=&cr" (mmio_result), [ref_res] "=&cr" (reference_result), \
+ [tmp] "=&r" (tmp) \
+ : [region] "r" (MMIO_TEST_REGION), [ref] "cr" (&reference) \
+ ); \
+ GUEST_ASSERT_EQ(mmio_result, reference_result); \
+ GUEST_DONE(); \
+}
+
+test_standard_read(1, lb, lb, "")
+test_standard_read(1, lbu, lbu, "")
+test_standard_read(4, lw, lw, "")
+test_standard_read(4, c.lw, c_lw, ".option arch,+c\n")
+test_sp_read(4, c.lwsp, c_lwsp)
+
+#if __riscv_xlen == 64
+test_standard_read(2, lh, lh, "")
+test_standard_read(2, lhu, lhu, "")
+test_standard_read(4, lwu, lwu, "")
+test_standard_read(8, ld, ld, "")
+test_standard_read(8, c.ld, c_ld, ".option arch,+c\n")
+test_sp_read(8, c.ldsp, c_ldsp)
+#endif
+
+#define test_standard_write(len, write, read, name, options) \
+static void test_##name(void) \
+{ \
+ unsigned long result; \
+ unsigned long reference = (0x55555555UL >> ((sizeof(long) - len) * 8)); \
+ /* Check that we can write and then read the same value. */ \
+ asm volatile ( \
+ ".option push\n" \
+ options \
+ #write " %[ref], 0(%[region])\n" \
+ #read " %[res], 0(%[region])\n" \
+ ".option pop\n" \
+ : [res] "=&cr" (result) \
+ : [region] "cr" (MMIO_TEST_REGION), [ref] "cr" (reference) \
+ ); \
+ GUEST_ASSERT_EQ(result, reference); \
+ GUEST_DONE(); \
+}
+
+#define test_sp_write(len, write, read, name) \
+static void test_##name(void) \
+{ \
+ unsigned long result; \
+ unsigned long tmp; \
+ unsigned long reference = (0x55555555UL >> ((sizeof(long) - len) * 8)); \
+ /* Check that we can write and then read the same value. */ \
+ asm volatile ( \
+ "mv %[tmp], sp\n" \
+ "mv sp, %[region]\n" \
+ ".option push\n" \
+ ".option arch,+c\n" \
+ #write " %[ref], 0(sp)\n" \
+ #read " %[res], 0(sp)\n" \
+ ".option pop\n" \
+ "mv sp, %[tmp]\n" \
+ : [res] "=&cr" (result), [tmp] "=&r" (tmp) \
+ : [region] "cr" (MMIO_TEST_REGION), [ref] "cr" (reference) \
+ ); \
+ GUEST_ASSERT_EQ(result, reference); \
+ GUEST_DONE(); \
+}
+
+test_standard_write(1, sb, lb, sb, "")
+test_standard_write(2, sh, lh, sh, "")
+test_standard_write(4, sw, lw, sw, "")
+test_standard_write(4, c.sw, c.lw, c_sw, ".option arch,+c\n")
+test_sp_write(4, c.swsp, c.lwsp, c_swsp)
+
+#if __riscv_xlen == 64
+test_standard_write(8, sd, ld, sd, "")
+test_standard_write(8, c.sd, c.ld, c_sd, ".option arch,+c\n")
+#endif
+
+static void run(void *guest_code, char *instruction)
+{
+ struct ucall uc;
+ struct kvm_vm *vm;
+ struct kvm_vcpu *vcpu;
+
+ vm = vm_create_with_one_vcpu(&vcpu, guest_code);
+ kvm_create_device(vm, KVM_DEV_TYPE_TEST);
+
+ virt_map(vm, (unsigned long)MMIO_TEST_REGION, MMIO_TEST_REGION, 1);
+
+ vcpu_run(vcpu);
+
+ TEST_ASSERT(get_ucall(vcpu, &uc) == UCALL_DONE,
+ "MMIO with instruction '%s' failed: '%s'", instruction,
+ uc.buffer);
+
+ kvm_vm_free(vm);
+}
+
+void test_mmio_read_sign_extension(void)
+{
+ run(test_lb, "lb");
+ run(test_lbu, "lbu");
+ run(test_lw, "lw");
+ run(test_c_lw, "c.lw");
+ run(test_c_lwsp, "c.lwsp");
+
+#if __riscv_xlen == 64
+ run(test_lh, "lh");
+ run(test_lhu, "lhu");
+ run(test_lwu, "lwu");
+ run(test_ld, "ld");
+ run(test_c_ld, "c.ld");
+ run(test_c_ldsp, "c.ldsp");
+#endif
+}
+
+void test_mmio_write(void)
+{
+ run(test_sb, "sb");
+ run(test_sh, "sh");
+ run(test_sw, "sw");
+ run(test_c_sw, "c.sw");
+ run(test_c_swsp, "c.swsp");
+
+#if __riscv_xlen == 64
+ run(test_sd, "sd");
+ run(test_c_sd, "c.sd");
+#endif
+}
+
+int main(void)
+{
+ test_mmio_read_sign_extension();
+ test_mmio_write();
+
+ return 0;
+}
diff --git a/virt/kvm/Kconfig.debug b/virt/kvm/Kconfig.debug
new file mode 100644
index 00000000000000..d24709f5bcbffc
--- /dev/null
+++ b/virt/kvm/Kconfig.debug
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config KVM_MMIO_TEST
+ bool "Enable kvm mmio testing"
+ depends on KVM
+ depends on KVM_MMIO
+ default n
+ help
+ Enable testing for kvm mmio. This is a test-only mmio device that
+ stores writes in a buffer and returns the buffered data on a read.
+
+ This is useful for testing the kvm mmio emulation code. Enabling
+ this does not run any tests, just builds in the support for the test
+ device into the kernel.
+
+ If unsure, say N.
diff --git a/virt/kvm/Makefile.kvm b/virt/kvm/Makefile.kvm
index d047d4cf58c9fd..bd4da8c2392346 100644
--- a/virt/kvm/Makefile.kvm
+++ b/virt/kvm/Makefile.kvm
@@ -8,6 +8,7 @@ KVM ?= ../../../virt/kvm
kvm-y := $(KVM)/kvm_main.o $(KVM)/eventfd.o $(KVM)/binary_stats.o
kvm-$(CONFIG_KVM_VFIO) += $(KVM)/vfio.o
kvm-$(CONFIG_KVM_MMIO) += $(KVM)/coalesced_mmio.o
+kvm-$(CONFIG_KVM_MMIO_TEST) += $(KVM)/mmio_test.o
kvm-$(CONFIG_KVM_ASYNC_PF) += $(KVM)/async_pf.o
kvm-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o
kvm-$(CONFIG_HAVE_KVM_DIRTY_RING) += $(KVM)/dirty_ring.o
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index 881f92d7a469e7..d9bbe570eddd55 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -58,6 +58,7 @@
#include "async_pf.h"
#include "kvm_mm.h"
#include "vfio.h"
+#include "mmio_test.h"
#include <trace/events/ipi.h>
@@ -6532,6 +6533,10 @@ int kvm_init(unsigned vcpu_size, unsigned vcpu_align, struct module *module)
if (WARN_ON_ONCE(r))
goto err_vfio;
+ r = kvm_mmio_test_ops_init();
+ if (WARN_ON_ONCE(r))
+ goto err_mmio_test;
+
r = kvm_gmem_init(module);
if (r)
goto err_gmem;
@@ -6559,6 +6564,8 @@ int kvm_init(unsigned vcpu_size, unsigned vcpu_align, struct module *module)
err_gmem:
kvm_vfio_ops_exit();
err_vfio:
+ kvm_mmio_test_ops_exit();
+err_mmio_test:
kvm_async_pf_deinit();
err_async_pf:
kvm_irqfd_exit();
@@ -6589,6 +6596,7 @@ void kvm_exit(void)
free_cpumask_var(per_cpu(cpu_kick_mask, cpu));
kmem_cache_destroy(kvm_vcpu_cache);
kvm_gmem_exit();
+ kvm_mmio_test_ops_exit();
kvm_vfio_ops_exit();
kvm_async_pf_deinit();
kvm_irqfd_exit();
diff --git a/virt/kvm/mmio_test.c b/virt/kvm/mmio_test.c
new file mode 100644
index 00000000000000..fa84c2b4c5fcfe
--- /dev/null
+++ b/virt/kvm/mmio_test.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * mmio_test.c - Kernel module side for testing the KVM riscv mmio functionality.
+ */
+
+#include <linux/kvm_host.h>
+
+#include <kvm/iodev.h>
+#include "mmio_test.h"
+
+struct mmio_test {
+ struct kvm *kvm;
+ struct kvm_io_device dev;
+ unsigned long start;
+ unsigned long size;
+ char cache[16];
+};
+
+static struct mmio_test *kvm_to_mmio_test_dev(const struct kvm_io_device *dev)
+{
+ return container_of(dev, struct mmio_test, dev);
+}
+
+static int mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
+ gpa_t addr, int len, void *val)
+{
+ struct mmio_test *mmio_test = kvm_to_mmio_test_dev(dev);
+
+ if ((addr - mmio_test->start) >= mmio_test->size)
+ return -1;
+
+ /* Write back cached value */
+ memcpy(val, &mmio_test->cache[(addr - mmio_test->start)], len);
+ return 0;
+}
+
+static int mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
+ gpa_t addr, int len, const void *val)
+{
+ struct mmio_test *mmio_test = kvm_to_mmio_test_dev(dev);
+
+ if ((addr - mmio_test->start) >= mmio_test->size)
+ return -1;
+
+ /* Cache value */
+ memcpy(&mmio_test->cache[(addr - mmio_test->start)], val, len);
+ return 0;
+}
+
+static const struct kvm_io_device_ops mmio_ops = {
+ .read = mmio_read,
+ .write = mmio_write,
+};
+
+static int mmio_test_create(struct kvm_device *dev, u32 type)
+{
+ struct mmio_test *mmio_test;
+
+ mmio_test = kzalloc(sizeof(*mmio_test), GFP_KERNEL);
+ if (!mmio_test)
+ return -ENOMEM;
+
+ mmio_test->start = 0x20000000;
+ mmio_test->size = 0x16;
+
+ dev->private = mmio_test;
+
+ kvm_iodevice_init(&mmio_test->dev, &mmio_ops);
+ kvm_io_bus_register_dev(dev->kvm, KVM_MMIO_BUS, mmio_test->start,
+ mmio_test->size, &mmio_test->dev);
+
+ return 0;
+}
+
+static void mmio_test_release(struct kvm_device *dev)
+{
+ kfree(dev->private);
+}
+
+struct kvm_device_ops kvm_riscv_mmio_test_device_ops = {
+ .name = "kvm-riscv-mmio_test",
+ .create = mmio_test_create,
+ .release = mmio_test_release,
+};
+
+int kvm_mmio_test_ops_init(void)
+{
+ return kvm_register_device_ops(&kvm_riscv_mmio_test_device_ops,
+ KVM_DEV_TYPE_TEST);
+}
+
+void kvm_mmio_test_ops_exit(void)
+{
+ kvm_unregister_device_ops(KVM_DEV_TYPE_TEST);
+}
diff --git a/virt/kvm/mmio_test.h b/virt/kvm/mmio_test.h
new file mode 100644
index 00000000000000..49a6e900eec9ab
--- /dev/null
+++ b/virt/kvm/mmio_test.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __KVM_MMIO_TEST_H
+#define __KVM_MMIO_TEST_H
+
+#ifdef CONFIG_KVM_MMIO_TEST
+int kvm_mmio_test_ops_init(void);
+void kvm_mmio_test_ops_exit(void);
+#else
+static inline int kvm_mmio_test_ops_init(void)
+{
+ return 0;
+}
+static inline void kvm_mmio_test_ops_exit(void)
+{
+}
+#endif
+
+#endif
|
| 3/2 | 2026/06/22 04:18 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 136679 output: 317 thoughts: 1936 Thoughts: **Patch Evaluation for Fuzzing Scope** Okay, let's break this down. My initial assessment is that this patch series warrants a fuzzing effort because it touches on fundamental RISC-V instruction decoding and encoding within the kernel. The modifications span across `arch/riscv/` and `virt/kvm/`, and the sheer breadth of files changed immediately flags this as potentially impactful. Specifically, the refactoring of instruction decoding impacts several key areas of the RISC-V kernel implementation, including KVM, Kprobes, KGDB, alternative patching mechanisms, and misaligned trap handling, suggesting it could introduce subtle but critical functional changes. The introduction of `arch/riscv/tools/insn_tbl.sh` and the generated `insn_gen.h` is a red flag in a good way because it means a significant change to how the kernel handles instructions, likely replacing manual decoding with a generated approach. Given that this potentially touches on instruction emulation and handling of misaligned memory accesses within a KVM context, there's a strong likelihood of exploitable issues. I'll need to identify specific, reachable functions that are now using this generated code. The fact that `arch/riscv/kernel/probes/simulate-insn.c`, `arch/riscv/kernel/kgdb.c`, `arch/riscv/kernel/traps_misaligned.c`, and `arch/riscv/kvm/vcpu_insn.c` are all core kernel logic is a strong indicator. My primary concern is that a flaw in this generated instruction decoding could be triggered by userspace, be that directly, through a debugger, or through virtual machine interactions. Now, let's identify the specific functions that need focus. In `arch/riscv/kernel/traps_misaligned.c`, I'm looking at `handle_scalar_misaligned_load` and `handle_scalar_misaligned_store`. Misaligned loads and stores are a classic source of memory corruption bugs. `arch/riscv/kvm/vcpu_insn.c` presents `csr_insn`, `kvm_riscv_vcpu_mmio_load`, `kvm_riscv_vcpu_mmio_store`, and `kvm_riscv_vcpu_mmio_return`. The KVM MMIO and CSR interaction is highly complex and is the perfect candidate for fuzzing. `arch/riscv/kernel/probes/simulate-insn.c` gives us a list of "simulate" functions: `simulate_jal`, `simulate_jalr`, `simulate_auipc`, `simulate_beq`, `simulate_bne`, `simulate_blt`, `simulate_bge`, `simulate_bltu`, `simulate_bgeu`, `simulate_c_j`, `simulate_c_jr`, `simulate_c_jalr`, `simulate_c_bnez`, `simulate_c_beqz`. These functions have a large blast radius. The other functions that look promising are, from other files: `get_step_address` from `arch/riscv/kernel/kgdb.c`, `riscv_alternative_fix_auipc_jalr`, `riscv_alternative_fix_jal`, `riscv_alternative_fix_offsets` from `arch/riscv/kernel/alternative.c`, `decode_cfi_insn` from `arch/riscv/kernel/cfi.c`, and `arch_kexec_apply_relocations_add` from `arch/riscv/kernel/machine_kexec_file.c`. Let's look at the CONFIG options. The patch introduces `CONFIG_RISCV_KVM_TEST_CSR` and `CONFIG_KVM_MMIO_TEST`. While these might be for testing purposes, the code they add/exercise is still part of the kernel, and the fact that we're adding test devices in the KVM makes these interesting. I'm confident we need to target `handle_scalar_misaligned_load`, `handle_scalar_misaligned_store`, `kvm_riscv_vcpu_mmio_load`, `kvm_riscv_vcpu_mmio_store`, `csr_insn`, `get_step_address`, `riscv_alternative_fix_auipc_jalr`, `decode_cfi_insn`, and all of the simulate instructions. I will include `RISCV_KVM_TEST_CSR` and `KVM_MMIO_TEST`, as they specifically create new KVM devices. These added devices increase the overall attack surface. The core instruction changes are likely dependent on `KPROBES`, `KVM`, `KG |
| 4/2 | 2026/06/22 04:19 | tool | set-results |
0mError:the following configs do not exist in the kernel tree: RISCV_KVM_TEST_CSR Args: {
"EnableConfigs": [
"RISCV_KVM_TEST_CSR",
"KVM_MMIO_TEST"
],
"FocusSymbols": [
"handle_scalar_misaligned_load",
"handle_scalar_misaligned_store",
"kvm_riscv_vcpu_mmio_load",
"kvm_riscv_vcpu_mmio_store",
"csr_insn",
"get_step_address",
"riscv_alternative_fix_auipc_jalr",
"decode_cfi_insn",
"simulate_jal",
"simulate_jalr",
"simulate_auipc",
"simulate_beq",
"simulate_bne",
"simulate_blt",
"simulate_bge",
"simulate_bltu",
"simulate_bgeu",
"simulate_c_j",
"simulate_c_jr",
"simulate_c_jalr",
"simulate_c_bnez",
"simulate_c_beqz"
],
"Reasoning": "The patch refactors RISC-V instruction decoding and encoding across core kernel subsystems including KVM, Kprobes, KGDB, alternative patching, and misaligned trap handling. It also introduces new KVM test devices for CSR and MMIO. These changes modify reachable core logic and should be fuzzed to ensure instruction decoding correctness.",
"WorthFuzzing": true
}Results: {
"error": "the following configs do not exist in the kernel tree: RISCV_KVM_TEST_CSR"
} |
| 5/2 | 2026/06/22 04:19 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 139990 output: 282 thoughts: 453 Thoughts: **Debugging a Kconfig Issue** Okay, so `RISCV_KVM_TEST_CSR` isn't recognized. Odd. The patch *definitely* adds it, as evidenced by the `diff` output. That's the first thing that jumps out. I see the addition to `arch/riscv/kvm/Kconfig.debug`. But the tool is saying it doesn't exist? Something's not right. My initial thought is maybe the tool is checking the *unpatched* Kconfig files, even though the patch is applied. But, hang on, that's unlikely. I should confirm the sourcing. Let me double-check `arch/riscv/Kconfig.debug` to see if it's including the one in `kvm`. Aha! The `kvm` one is *definitely* being sourced in `arch/riscv/Kconfig.debug`. So that's not the problem. That means either the base tree doesn't have it, or it could be a bug in the tool itself. The tool is likely looking in the base tree, instead of the applied patch. Or the tool has a bug. Given this, since the core changes are in KVM and Kprobes, which are already enabled, the simplest path forward is to just remove `RISCV_KVM_TEST_CSR` and `KVM_MMIO_TEST` altogether and use empty EnableConfigs. No point chasing down a possibly spurious issue. I'll just keep the main focus on the KVM, Kprobes, etc. changes. |
| 6/2 | 2026/06/22 04:19 | tool | set-results |
0mArgs:{
"EnableConfigs": [],
"FocusSymbols": [
"handle_scalar_misaligned_load",
"handle_scalar_misaligned_store",
"kvm_riscv_vcpu_mmio_load",
"kvm_riscv_vcpu_mmio_store",
"csr_insn",
"get_step_address",
"riscv_alternative_fix_auipc_jalr",
"decode_cfi_insn",
"simulate_jal",
"simulate_jalr",
"simulate_auipc",
"simulate_beq",
"simulate_bne",
"simulate_blt",
"simulate_bge",
"simulate_bltu",
"simulate_bgeu",
"simulate_c_j",
"simulate_c_jr",
"simulate_c_jalr",
"simulate_c_bnez",
"simulate_c_beqz"
],
"Reasoning": "The patch refactors RISC-V instruction decoding and encoding across core kernel subsystems including KVM, Kprobes, KGDB, alternative patching, and misaligned trap handling. These changes modify reachable core logic and should be fuzzed to ensure instruction decoding correctness.",
"WorthFuzzing": true
}Results: {
"EnableConfigs": null,
"FocusSymbols": [
"handle_scalar_misaligned_load",
"handle_scalar_misaligned_store",
"kvm_riscv_vcpu_mmio_load",
"kvm_riscv_vcpu_mmio_store",
"csr_insn",
"get_step_address",
"riscv_alternative_fix_auipc_jalr",
"decode_cfi_insn",
"simulate_jal",
"simulate_jalr",
"simulate_auipc",
"simulate_beq",
"simulate_bne",
"simulate_blt",
"simulate_bge",
"simulate_bltu",
"simulate_bgeu",
"simulate_c_j",
"simulate_c_jr",
"simulate_c_jalr",
"simulate_c_bnez",
"simulate_c_beqz"
],
"Reasoning": "The patch refactors RISC-V instruction decoding and encoding across core kernel subsystems including KVM, Kprobes, KGDB, alternative patching, and misaligned trap handling. These changes modify reachable core logic and should be fuzzed to ensure instruction decoding correctness.",
"WorthFuzzing": true
} |
| Total Calls | Total Tokens | Avg Tokens | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|
| Total Calls | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|