Subject	MT8189: Add support for system and base clock controllers
Author	louisalexis.eyraud@collabora.com
Date	2026-08-01 11:20:47 +0000 UTC
Version	Version 1 Version 2 Version 3 Version 4 Version 5
Cc	angelogioacchino.delregno@collabora.com bmasney@redhat.com chun-jie.chen@mediatek.com conor.dooley@microchip.com conor@kernel.org devicetree@vger.kernel.org edward-jw.yang@mediatek.com irving-ch.lin@mediatek.com kernel@collabora.com krzk@kernel.org linux-arm-kernel@lists.infradead.org linux-clk@vger.kernel.org linux-kernel@vger.kernel.org linux-mediatek@lists.infradead.org louisalexis.eyraud@collabora.com matthias.bgg@gmail.com mturquette@baylibre.com netdev@vger.kernel.org p.zabel@pengutronix.de richardcochran@gmail.com robh@kernel.org sboyd@kernel.org wenst@chromium.org

Patches (25)

Name	Content [All]
[PATCH v5 01/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186	[Body]
[PATCH v5 02/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192	[Body]
[PATCH v5 03/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195	[Body]
[PATCH v5 04/25] dt-bindings: clock: mediatek: reorder MT8186 compatibles	[Body]
[PATCH v5 05/25] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186	[Body]
[PATCH v5 06/25] dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186	[Body]
[PATCH v5 07/25] dt-bindings: clock: mediatek: regroup MT8195 dt-bindings into MT8186	[Body]
[PATCH v5 08/25] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets	[Body]
[PATCH v5 09/25] clk: mediatek: Harmonize mtk_pll_fenc related symbol names	[Body]
[PATCH v5 10/25] clk: mediatek: pll: Add BAR reset register offsets	[Body]
[PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences	[Body]
[PATCH v5 12/25] clk: mediatek: pll: Add PLL stabilization delay definition	[Body]
[PATCH v5 13/25] clk: mediatek: pll: Add ops for PLLs using set/clr regs	[Body]
[PATCH v5 14/25] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data	[Body]
[PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs	[Body]
[PATCH v5 16/25] clk: mediatek: Add MT8189 apmixedsys clock support	[Body]
[PATCH v5 17/25] clk: mediatek: Add MT8189 topckgen clock support	[Body]
[PATCH v5 18/25] clk: mediatek: Add MT8189 vlpckgen clock support	[Body]
[PATCH v5 19/25] clk: mediatek: Add MT8189 vlpcfg clock support	[Body]
[PATCH v5 20/25] clk: mediatek: Add MT8189 bus clock support	[Body]
[PATCH v5 21/25] clk: mediatek: Add MT8189 dbgao clock support	[Body]
[PATCH v5 22/25] clk: mediatek: Add MT8189 dvfsrc clock support	[Body]
[PATCH v5 23/25] clk: mediatek: Add MT8189 i2c clock support	[Body]
[PATCH v5 24/25] clk: mediatek: Add MT8189 scp clock support	[Body]
[PATCH v5 25/25] clk: mediatek: Add MT8189 ufs clock support	[Body]

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