Currently, the mtk_clk_register_pllfh functions always registers the default PLL clock operation set (mtk_pllfh_ops). This does not allow use a custom one, for SoC such as MT8189, that needs different set with support for set/clr enable. Add a new field for the ops to register in mtk_pllfh_data structure and use this new field to either register it when not null or the default ops otherwise. Signed-off-by: Louis-Alexis Eyraud --- drivers/clk/mediatek/clk-pllfh.c | 5 +++-- drivers/clk/mediatek/clk-pllfh.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c index aa95cd9197b3..4878ac6da7da 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -153,6 +153,8 @@ static struct clk_hw * mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_data, struct mtk_pllfh_data *pllfh_data, void __iomem *base) { + const struct clk_ops *pllfh_ops = pllfh_data->data.ops ? + pllfh_data->data.ops : &mtk_pllfh_ops; struct clk_hw *hw; struct mtk_fh *fh; int ret; @@ -169,8 +171,7 @@ mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_data, fh->clk_pll.dev = dev; - hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, - &mtk_pllfh_ops); + hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, pllfh_ops); if (IS_ERR(hw)) goto out; diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pllfh.h index a4f337acad71..d32bfe194ec4 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -34,6 +34,7 @@ struct fh_pll_data { u32 updnlmt_shft; u32 msk_frddsx_dys; u32 msk_frddsx_dts; + const struct clk_ops *ops; }; struct mtk_pllfh_data { -- 2.55.0