To prepare for the new clock ops set addition, with support for set/clr enable logic only, rename mtk_pll_fenc_setclr_ops and its callback names to harmonize the naming with the same suffix. Signed-off-by: Louis-Alexis Eyraud --- drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +- drivers/clk/mediatek/clk-pll.c | 16 ++++++++-------- drivers/clk/mediatek/clk-pll.h | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c index c4ebb0170b82..41c5117b18f8 100644 --- a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c @@ -83,7 +83,7 @@ .en_set_reg = PLLEN_ALL_SET, \ .en_clr_reg = PLLEN_ALL_CLR, \ .pll_en_bit = _pll_en_bit, \ - .ops = &mtk_pll_fenc_clr_set_ops, \ + .ops = &mtk_pll_fenc_setclr_ops, \ } struct mtk_pll_desc { diff --git a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c index 7dcc164627c5..8a69f88e15a7 100644 --- a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c +++ b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c @@ -162,7 +162,7 @@ .en_set_reg = VLP_PLLEN_ALL_SET, \ .en_clr_reg = VLP_PLLEN_ALL_CLR, \ .pll_en_bit = _pll_en_bit, \ - .ops = &mtk_pll_fenc_clr_set_ops, \ + .ops = &mtk_pll_fenc_setclr_ops, \ } static DEFINE_SPINLOCK(mt8196_clk_vlp_lock); diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index e97064868908..ee478bc64085 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -38,7 +38,7 @@ int mtk_pll_is_prepared(struct clk_hw *hw) return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; } -static int mtk_pll_fenc_is_prepared(struct clk_hw *hw) +static int mtk_pll_is_prepared_fenc_setclr(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); @@ -285,7 +285,7 @@ void mtk_pll_unprepare(struct clk_hw *hw) writel(r, pll->pwr_addr); } -static int mtk_pll_prepare_setclr(struct clk_hw *hw) +static int mtk_pll_prepare_fenc_setclr(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); @@ -297,7 +297,7 @@ static int mtk_pll_prepare_setclr(struct clk_hw *hw) return 0; } -static void mtk_pll_unprepare_setclr(struct clk_hw *hw) +static void mtk_pll_unprepare_fenc_setclr(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); @@ -313,15 +313,15 @@ const struct clk_ops mtk_pll_ops = { .set_rate = mtk_pll_set_rate, }; -const struct clk_ops mtk_pll_fenc_clr_set_ops = { - .is_prepared = mtk_pll_fenc_is_prepared, - .prepare = mtk_pll_prepare_setclr, - .unprepare = mtk_pll_unprepare_setclr, +const struct clk_ops mtk_pll_fenc_setclr_ops = { + .is_prepared = mtk_pll_is_prepared_fenc_setclr, + .prepare = mtk_pll_prepare_fenc_setclr, + .unprepare = mtk_pll_unprepare_fenc_setclr, .recalc_rate = mtk_pll_recalc_rate, .determine_rate = mtk_pll_determine_rate, .set_rate = mtk_pll_set_rate, }; -EXPORT_SYMBOL_GPL(mtk_pll_fenc_clr_set_ops); +EXPORT_SYMBOL_GPL(mtk_pll_fenc_setclr_ops); struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, const struct mtk_pll_data *data, diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index f49dc2732ffe..d6d34840c09d 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -85,7 +85,7 @@ void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, struct clk_hw_onecell_data *clk_data); extern const struct clk_ops mtk_pll_ops; -extern const struct clk_ops mtk_pll_fenc_clr_set_ops; +extern const struct clk_ops mtk_pll_fenc_setclr_ops; static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) { -- 2.55.0