Subject ice: DPLL init fixes for E810 timing boards
Author poros@redhat.com
Date 2026-09-17 19:02:57 +0000 UTC
Version
Cc andrew@lunn.ch anthony.l.nguyen@intel.com arkadiusz.kubalewski@intel.com davem@davemloft.net edumazet@google.com horms@kernel.org intel-wired-lan@lists.osuosl.org kuba@kernel.org linux-kernel@vger.kernel.org netdev@vger.kernel.org pabeni@redhat.com poros@redhat.com przemyslaw.kitszel@intel.com stable@vger.kernel.org
Patches (2)
Name Content [All]
[PATCH iwl-net 1/2] ice: fix DPLL registration on boards without the SMA clock mux [Body]
[PATCH iwl-net 2/2] ice: skip the SW pin description on boards with generic DPLL pins [Body]
Series Summary
waiting
Status: waiting
Sessions
Session 2026-09-17
waiting
ID (for dev) 843e1ae6-3859-4967-a38f-606f59ed3a0f
Status waiting
Test Base Patched Verdict