ice_dpll_init_info_sw_pins() describes the SMA and U.FL wrappers by pointing them at fixed positions of the input and output arrays, inputs 4 and 5 and outputs 0 and 1 on an E810-C SFP, and reads the ref-sync partner of the input it picked. The arrays are sized by the pin counts firmware reports. On a board that does not match the Intel reference layout the driver has already fallen back to generic pins, and when such a board reports fewer pins than the reference the reads run past the end of the arrays. The wrappers are never registered on a generic board, but ice_dpll_init_pins() still calls ice_dpll_pin_ref_sync_register() on them, so a stray nonzero partner from the out of bounds read would pair NULL pins. Describe the wrappers only when the static pin table is in use and keep their ref-sync registration under the same condition. The default programming of the PCA9575 clock mux stays on the generic path, a board that has the mux still needs its SMA connectors switched to inputs. Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control") Signed-off-by: Petr Oros --- drivers/net/ethernet/intel/ice/ice_dpll.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c index e0362b6bf332e5..81bb32d2b23012 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -4124,15 +4124,15 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu) if (ret) goto deinit_sma; count += ICE_DPLL_PIN_SW_NUM; + ret = ice_dpll_pin_ref_sync_register(pf->dplls.sma, + ICE_DPLL_PIN_SW_NUM); + if (ret) + goto deinit_ufl; } ret = ice_dpll_pin_ref_sync_register(pf->dplls.inputs, pf->dplls.num_inputs); if (ret) goto deinit_ufl; - ret = ice_dpll_pin_ref_sync_register(pf->dplls.sma, - ICE_DPLL_PIN_SW_NUM); - if (ret) - goto deinit_ufl; } else { count += pf->dplls.num_outputs + 2 * ICE_DPLL_PIN_SW_NUM; } @@ -4501,6 +4501,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) int i, ret; u8 data; + if (d->generic) + goto init_sma_ctrl; if (pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) input_idx_offset = ICE_E810_RCLK_PINS_NUM; phase_adj_max = max(d->input_phase_adj_max, d->output_phase_adj_max); @@ -4566,6 +4568,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); } +init_sma_ctrl: if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) return 0; @@ -4584,7 +4587,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) if (ret) return ret; - ret = ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE, + ret = ice_dpll_pin_state_update(pf, d->sma, ICE_DPLL_PIN_TYPE_SOFTWARE, NULL); if (ret) return ret; -- 2.55.0