Patch Series

Subject	Add support for MT8196 clock controllers
Author	laura.nao@collabora.com
Date	2025-07-30 10:56:27 +0000 UTC
Version	3
Cc	angelogioacchino.delregno@collabora.com conor@kernel.org devicetree@vger.kernel.org guangjie.song@mediatek.com kernel@collabora.com krzk@kernel.org laura.nao@collabora.com linux-arm-kernel@lists.infradead.org linux-clk@vger.kernel.org linux-kernel@vger.kernel.org linux-mediatek@lists.infradead.org matthias.bgg@gmail.com mturquette@baylibre.com netdev@vger.kernel.org nfraprado@collabora.com p.zabel@pengutronix.de richardcochran@gmail.com robh@kernel.org sboyd@kernel.org wenst@chromium.org

Patches (27)

Name	Content
[PATCH v3 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control	[Body]
[PATCH v3 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC	[Body]
[PATCH v3 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC	[Body]
[PATCH v3 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()	[Body]
[PATCH v3 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC	[Body]
[PATCH v3 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct	[Body]
[PATCH v3 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter	[Body]
[PATCH v3 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro	[Body]
[PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers	[Body]
[PATCH v3 10/27] clk: mediatek: Add MT8196 apmixedsys clock support	[Body]
[PATCH v3 11/27] clk: mediatek: Add MT8196 topckgen clock support	[Body]
[PATCH v3 12/27] clk: mediatek: Add MT8196 topckgen2 clock support	[Body]
[PATCH v3 13/27] clk: mediatek: Add MT8196 vlpckgen clock support	[Body]
[PATCH v3 14/27] clk: mediatek: Add MT8196 peripheral clock support	[Body]
[PATCH v3 15/27] clk: mediatek: Add MT8196 ufssys clock support	[Body]
[PATCH v3 16/27] clk: mediatek: Add MT8196 pextpsys clock support	[Body]
[PATCH v3 17/27] clk: mediatek: Add MT8196 I2C clock support	[Body]
[PATCH v3 18/27] clk: mediatek: Add MT8196 mcu clock support	[Body]
[PATCH v3 19/27] clk: mediatek: Add MT8196 mdpsys clock support	[Body]
[PATCH v3 20/27] clk: mediatek: Add MT8196 mfg clock support	[Body]
[PATCH v3 21/27] clk: mediatek: Add MT8196 disp0 clock support	[Body]
[PATCH v3 22/27] clk: mediatek: Add MT8196 disp1 clock support	[Body]
[PATCH v3 23/27] clk: mediatek: Add MT8196 disp-ao clock support	[Body]
[PATCH v3 24/27] clk: mediatek: Add MT8196 ovl0 clock support	[Body]
[PATCH v3 25/27] clk: mediatek: Add MT8196 ovl1 clock support	[Body]
[PATCH v3 26/27] clk: mediatek: Add MT8196 vdecsys clock support	[Body]
[PATCH v3 27/27] clk: mediatek: Add MT8196 vencsys clock support	[Body]

Session 2025-07-30

ID (for dev)	ece03cf0-9c38-497e-b0d9-b76038378aa9
Status	finished
Triaged	OK [Log]
Execution Log	[Link]

Test	Base	Patched	Verdict
Build Base	e3f96b3556e4856dc4125ce875e87c5b5028b40b [Config]		passed [Log]
Build Patched		e3f96b3556e4856dc4125ce875e87c5b5028b40b [Config] [patched]	passed [Log]
Boot test: Base	e3f96b3556e4856dc4125ce875e87c5b5028b40b [Config]		passed
Boot test: Patched		e3f96b3556e4856dc4125ce875e87c5b5028b40b [Config] [patched]	passed
Fuzzing	e3f96b3556e4856dc4125ce875e87c5b5028b40b [Config]	e3f96b3556e4856dc4125ce875e87c5b5028b40b [Config] [patched]	passed [Log] [Artifacts]