Patch Series

Subject Add ethtool support to configure irq coalescing count and delay
Author suraj.gupta2@amd.com
Date 2025-07-10 10:12:26 +0000 UTC
Version 1
Cc andrew@lunn.ch davem@davemloft.net dmaengine@vger.kernel.org harini.katakam@amd.com kuba@kernel.org linux-arm-kernel@lists.infradead.org linux-kernel@vger.kernel.org michal.simek@amd.com netdev@vger.kernel.org pabeni@redhat.com radhey.shyam.pandey@amd.com suraj.gupta2@amd.com vkoul@kernel.org

Patches (4)

Name Content [All]
[PATCH V2 1/4] dmaengine: Add support to configure and read IRQ coalescing parameters [Body]
[PATCH V2 2/4] dmaengine: xilinx_dma: Fix irq handler and start transfer path for AXI DMA [Body]
[PATCH V2 3/4] dmaengine: xilinx_dma: Add support to configure/report coalesce parameters from/to client using AXI DMA [Body]
[PATCH V2 4/4] net: xilinx: axienet: Add ethtool support to configure/report irq coalescing parameters in DMAengine flow [Body]

Session 2025-07-10

ID (for dev) 38ddc3dd-34de-40a0-beda-045233a2b752
Status finished
Execution Log [Link]
Test Base Patched Verdict
Build Base 47c84997c686b4d43b225521b732492552b84758 passed [Log]
Build Patched 47c84997c686b4d43b225521b732492552b84758 [patched] passed [Log]
Boot test: Patched 47c84997c686b4d43b225521b732492552b84758 [patched] passed
Boot test: Base 47c84997c686b4d43b225521b732492552b84758 passed
Fuzzing 47c84997c686b4d43b225521b732492552b84758 47c84997c686b4d43b225521b732492552b84758 [patched] passed [Log] [Artifacts]