Syzbot CI

Subject	Add support for MT8196 clock controllers
Author	laura.nao@collabora.com
Date	2025-08-29 09:18:47 +0000 UTC
Version
Cc	angelogioacchino.delregno@collabora.com conor@kernel.org devicetree@vger.kernel.org guangjie.song@mediatek.com kernel@collabora.com krzk@kernel.org krzysztof.kozlowski@linaro.org laura.nao@collabora.com linux-arm-kernel@lists.infradead.org linux-clk@vger.kernel.org linux-kernel@vger.kernel.org linux-mediatek@lists.infradead.org matthias.bgg@gmail.com mturquette@baylibre.com netdev@vger.kernel.org nfraprado@collabora.com p.zabel@pengutronix.de richardcochran@gmail.com robh@kernel.org sboyd@kernel.org wenst@chromium.org

Subject

Add support for MT8196 clock controllers

Author

laura.nao@collabora.com

Date

2025-08-29 09:18:47 +0000 UTC

Version

angelogioacchino.delregno@collabora.com conor@kernel.org devicetree@vger.kernel.org guangjie.song@mediatek.com kernel@collabora.com krzk@kernel.org krzysztof.kozlowski@linaro.org laura.nao@collabora.com linux-arm-kernel@lists.infradead.org linux-clk@vger.kernel.org linux-kernel@vger.kernel.org linux-mediatek@lists.infradead.org matthias.bgg@gmail.com mturquette@baylibre.com netdev@vger.kernel.org nfraprado@collabora.com p.zabel@pengutronix.de richardcochran@gmail.com robh@kernel.org sboyd@kernel.org wenst@chromium.org

Name	Content [All]
[PATCH v5 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control	[Body]
[PATCH v5 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC	[Body]
[PATCH v5 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC	[Body]
[PATCH v5 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()	[Body]
[PATCH v5 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC	[Body]
[PATCH v5 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct	[Body]
[PATCH v5 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter	[Body]
[PATCH v5 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro	[Body]
[PATCH v5 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers	[Body]
[PATCH v5 10/27] clk: mediatek: Add MT8196 apmixedsys clock support	[Body]
[PATCH v5 11/27] clk: mediatek: Add MT8196 topckgen clock support	[Body]
[PATCH v5 12/27] clk: mediatek: Add MT8196 topckgen2 clock support	[Body]
[PATCH v5 13/27] clk: mediatek: Add MT8196 vlpckgen clock support	[Body]
[PATCH v5 14/27] clk: mediatek: Add MT8196 peripheral clock support	[Body]
[PATCH v5 15/27] clk: mediatek: Add MT8196 ufssys clock support	[Body]
[PATCH v5 16/27] clk: mediatek: Add MT8196 pextpsys clock support	[Body]
[PATCH v5 17/27] clk: mediatek: Add MT8196 I2C clock support	[Body]
[PATCH v5 18/27] clk: mediatek: Add MT8196 mcu clock support	[Body]
[PATCH v5 19/27] clk: mediatek: Add MT8196 mdpsys clock support	[Body]
[PATCH v5 20/27] clk: mediatek: Add MT8196 mfg clock support	[Body]
[PATCH v5 21/27] clk: mediatek: Add MT8196 disp0 clock support	[Body]
[PATCH v5 22/27] clk: mediatek: Add MT8196 disp1 clock support	[Body]
[PATCH v5 23/27] clk: mediatek: Add MT8196 disp-ao clock support	[Body]
[PATCH v5 24/27] clk: mediatek: Add MT8196 ovl0 clock support	[Body]
[PATCH v5 25/27] clk: mediatek: Add MT8196 ovl1 clock support	[Body]
[PATCH v5 26/27] clk: mediatek: Add MT8196 vdecsys clock support	[Body]
[PATCH v5 27/27] clk: mediatek: Add MT8196 vencsys clock support	[Body]

Name

Content [All]

[PATCH v5 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control

[PATCH v5 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC

[PATCH v5 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC

[PATCH v5 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()

[PATCH v5 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC

[PATCH v5 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct

[PATCH v5 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter

[PATCH v5 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro

[PATCH v5 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers

[PATCH v5 10/27] clk: mediatek: Add MT8196 apmixedsys clock support

[PATCH v5 11/27] clk: mediatek: Add MT8196 topckgen clock support

[PATCH v5 12/27] clk: mediatek: Add MT8196 topckgen2 clock support

[PATCH v5 13/27] clk: mediatek: Add MT8196 vlpckgen clock support

[PATCH v5 14/27] clk: mediatek: Add MT8196 peripheral clock support

[PATCH v5 15/27] clk: mediatek: Add MT8196 ufssys clock support

[PATCH v5 16/27] clk: mediatek: Add MT8196 pextpsys clock support

[PATCH v5 17/27] clk: mediatek: Add MT8196 I2C clock support

[PATCH v5 18/27] clk: mediatek: Add MT8196 mcu clock support

[PATCH v5 19/27] clk: mediatek: Add MT8196 mdpsys clock support

[PATCH v5 20/27] clk: mediatek: Add MT8196 mfg clock support

[PATCH v5 21/27] clk: mediatek: Add MT8196 disp0 clock support

[PATCH v5 22/27] clk: mediatek: Add MT8196 disp1 clock support

[PATCH v5 23/27] clk: mediatek: Add MT8196 disp-ao clock support

[PATCH v5 24/27] clk: mediatek: Add MT8196 ovl0 clock support

[PATCH v5 25/27] clk: mediatek: Add MT8196 ovl1 clock support

[PATCH v5 26/27] clk: mediatek: Add MT8196 vdecsys clock support

[PATCH v5 27/27] clk: mediatek: Add MT8196 vencsys clock support

Session 2025-08-29

Passed

ID (for dev)	0cf4fbc3-b6a6-4dbd-8004-5218ad58852a
Status	finished
Triaged	OK [Log]
Execution Log	[Link]

Test	Base	Patched	Verdict
Build Base	c158b5a570a188b990ef10ded172b8b93e737826 [Config]		passed [Log]
Build Patched		c158b5a570a188b990ef10ded172b8b93e737826 [Config] [patched]	passed [Log]
Boot test: Patched		c158b5a570a188b990ef10ded172b8b93e737826 [Config] [patched]	passed
Boot test: Base	c158b5a570a188b990ef10ded172b8b93e737826 [Config]		passed
Fuzzing	c158b5a570a188b990ef10ded172b8b93e737826 [Config]	c158b5a570a188b990ef10ded172b8b93e737826 [Config] [patched]	skipped [Log] [Artifacts]

Patches (27)

Series Summary

Sessions

Session 2025-08-29