Subject net: lan969x: skew the core clock by 200 ppm
Author daniel.machon@microchip.com
Date 2026-11-13 10:19:40 +0000 UTC
Version
Cc andrew@lunn.ch daniel.machon@microchip.com davem@davemloft.net edumazet@kernel.org kuba@kernel.org linux-arm-kernel@lists.infradead.org linux-kernel@vger.kernel.org netdev@vger.kernel.org p.zabel@pengutronix.de pabeni@redhat.com richardcochran@gmail.com steen.hegelund@microchip.com unglinuxdriver@microchip.com
Patches (4)
Name Content [All]
[PATCH net-next 1/4] net: lan969x: add the core PLL registers [Body]
[PATCH net-next 2/4] net: sparx5/lan969x: enable the switch core after clock setup [Body]
[PATCH net-next 3/4] net: lan969x: configure the core PLL [Body]
[PATCH net-next 4/4] net: sparx5/lan969x: scale the nominal TOD increment in adjfine [Body]
Series Summary
waiting
Status: waiting
Sessions
Session 2026-11-13
waiting
ID (for dev) bda75acd-a23d-4756-acb1-8e4b9ccdbb9d
Status waiting
Test Base Patched Verdict