| 2026-03-17 23:04 UTC |
Split Generic PHY consumer and provider API |
4 |
vladimir.oltean@nxp.com |
finished
in 4h12m0s
|
| 2026-03-09 19:08 UTC |
Split Generic PHY consumer and provider API |
3 |
vladimir.oltean@nxp.com |
finished
in 4h26m0s
|
| 2026-03-08 11:39 UTC |
Split Generic PHY consumer and provider API |
2 |
vladimir.oltean@nxp.com |
finished
in 4h0m0s
|
| 2026-03-04 17:57 UTC |
Split Generic PHY consumer and provider API |
1 |
vladimir.oltean@nxp.com |
finished
in 4h14m0s
|
| 2026-03-03 12:22 UTC |
net: dsa: add DSA support for the LAN9645x switch chip family |
1 |
jensemil.schulzostergaard@microchip.com |
finished
in 1h3m0s
|
| 2026-02-27 14:56 UTC |
net: sparx5: clean up probe/remove init and deinit paths |
2 |
daniel.machon@microchip.com |
finished
in 56m0s
|
| 2026-02-26 08:24 UTC |
net: phy: micrel: Add support for lan9645x internal phy |
3 |
jensemil.schulzostergaard@microchip.com |
finished
in 50m0s
|
| 2026-02-25 09:05 UTC |
net: sparx5: clean up probe/remove init and deinit paths |
1 |
daniel.machon@microchip.com |
finished
in 1h0m0s
|
| 2026-02-12 11:02 UTC |
net: sparx5/lan969x: fix PTP clock max_adj value |
1 |
daniel.machon@microchip.com |
finished
in 1h1m0s
|
| 2026-02-10 13:44 UTC |
net: sparx5/lan969x: fix DWRR cost max to match hardware register width |
1 |
daniel.machon@microchip.com |
finished
in 59m0s
|
| 2026-01-30 09:12 UTC |
net: phy: micrel: Add support for lan9645x internal phy |
2 |
jensemil.schulzostergaard@microchip.com |
finished
in 57m0s
|
| 2026-01-23 07:50 UTC |
net: phy: micrel: Add support for lan9645x internal phy |
1 |
jensemil.schulzostergaard@microchip.com |
finished
in 1h30m0s
|
| 2026-01-15 11:37 UTC |
Add support for Microchip LAN969x |
5 |
robert.marko@sartura.hr |
finished
in 54m0s
|
| 2025-12-29 18:37 UTC |
Add support for Microchip LAN969x |
4 |
robert.marko@sartura.hr |
finished
in 52m0s
|
| 2025-12-23 20:16 UTC |
Add support for Microchip LAN969x |
3 |
robert.marko@sartura.hr |
finished
in 52m0s
|
| 2025-12-15 16:35 UTC |
include: dt-bindings: add LAN969x clock bindings |
2 |
robert.marko@sartura.hr |
finished
in 57m0s
|
| 2025-11-10 12:42 UTC |
net: sparx5/lan969x: populate netdev of_node |
2 |
robert.marko@sartura.hr |
finished
in 39m0s
|
| 2025-11-07 14:18 UTC |
net: sparx5/lan969x: populate netdev of_node |
1 |
robert.marko@sartura.hr |
finished
in 46m0s
|
| 2025-10-26 10:17 UTC |
dt-bindings: net: sparx5: Narrow properly LAN969x register space windows |
2 |
krzysztof.kozlowski@linaro.org |
finished
in 48m0s
|
| 2025-10-26 10:16 UTC |
dt-bindings: net: sparx5: Narrow properly LAN969x register space windows |
1 |
krzysztof.kozlowski@linaro.org |
finished
in 45m0s
|
| 2025-10-23 19:13 UTC |
phy: mscc: Fix PTP for VSC8574 and VSC8572 |
5 |
horatiu.vultur@microchip.com |
finished
in 48m0s
|
| 2025-10-17 06:48 UTC |
phy: mscc: Fix PTP for VSC8574 and VSC8572 |
4 |
horatiu.vultur@microchip.com |
finished
in 44m0s
|
| 2025-10-03 12:35 UTC |
net: sparx5/lan969x: fix flooding configuration on bridge join/leave |
1 |
daniel.machon@microchip.com |
finished
in 44m0s
|
| 2025-09-29 09:13 UTC |
phy: mscc: Fix PTP for VSC8574 and VSC8572 |
3 |
horatiu.vultur@microchip.com |
finished
in 45m0s
|
| 2025-09-25 13:19 UTC |
dt-bindings: net: sparx5: correct LAN969x register space windows |
1 |
robert.marko@sartura.hr |
finished
in 56m0s
|
| 2025-09-17 11:49 UTC |
net: sparx5/lan969x: Add support for ethtool pause parameters |
1 |
daniel.machon@microchip.com |
finished
in 47m0s
|
| 2025-09-17 11:33 UTC |
phy: mscc: Fix PTP for vsc8574 and VSC8572 |
2 |
horatiu.vultur@microchip.com |
finished
in 45m0s
|
| 2025-09-17 11:00 UTC |
net: ethernet: microchip: sparx5: make it selectable for ARCH_LAN969X |
1 |
robert.marko@sartura.hr |
finished
in 35m0s
|
| 2025-09-15 08:01 UTC |
phy: mscc: Fix PTP for vsc8574 and VSC8572 |
1 |
horatiu.vultur@microchip.com |
finished
in 44m0s
|
| 2025-08-21 08:30 UTC |
dt-bindings: net: litex,liteeth: Correct example indentation |
1 |
krzysztof.kozlowski@linaro.org |
finished
in 35m0s
|