Patch Series

Subject	Add support for MT8196 clock controllers
Author	laura.nao@collabora.com
Date	2025-08-05 13:54:21 +0000 UTC
Version	4
Cc	angelogioacchino.delregno@collabora.com conor@kernel.org devicetree@vger.kernel.org guangjie.song@mediatek.com kernel@collabora.com krzk@kernel.org laura.nao@collabora.com linux-arm-kernel@lists.infradead.org linux-clk@vger.kernel.org linux-kernel@vger.kernel.org linux-mediatek@lists.infradead.org matthias.bgg@gmail.com mturquette@baylibre.com netdev@vger.kernel.org nfraprado@collabora.com p.zabel@pengutronix.de richardcochran@gmail.com robh@kernel.org sboyd@kernel.org wenst@chromium.org

Patches (27)

Name	Content
[PATCH v4 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control	[Body]
[PATCH v4 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC	[Body]
[PATCH v4 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC	[Body]
[PATCH v4 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()	[Body]
[PATCH v4 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC	[Body]
[PATCH v4 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct	[Body]
[PATCH v4 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter	[Body]
[PATCH v4 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro	[Body]
[PATCH v4 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers	[Body]
[PATCH v4 10/27] clk: mediatek: Add MT8196 apmixedsys clock support	[Body]
[PATCH v4 11/27] clk: mediatek: Add MT8196 topckgen clock support	[Body]
[PATCH v4 12/27] clk: mediatek: Add MT8196 topckgen2 clock support	[Body]
[PATCH v4 13/27] clk: mediatek: Add MT8196 vlpckgen clock support	[Body]
[PATCH v4 14/27] clk: mediatek: Add MT8196 peripheral clock support	[Body]
[PATCH v4 15/27] clk: mediatek: Add MT8196 ufssys clock support	[Body]
[PATCH v4 16/27] clk: mediatek: Add MT8196 pextpsys clock support	[Body]
[PATCH v4 17/27] clk: mediatek: Add MT8196 I2C clock support	[Body]
[PATCH v4 18/27] clk: mediatek: Add MT8196 mcu clock support	[Body]
[PATCH v4 19/27] clk: mediatek: Add MT8196 mdpsys clock support	[Body]
[PATCH v4 20/27] clk: mediatek: Add MT8196 mfg clock support	[Body]
[PATCH v4 21/27] clk: mediatek: Add MT8196 disp0 clock support	[Body]
[PATCH v4 22/27] clk: mediatek: Add MT8196 disp1 clock support	[Body]
[PATCH v4 23/27] clk: mediatek: Add MT8196 disp-ao clock support	[Body]
[PATCH v4 24/27] clk: mediatek: Add MT8196 ovl0 clock support	[Body]
[PATCH v4 25/27] clk: mediatek: Add MT8196 ovl1 clock support	[Body]
[PATCH v4 26/27] clk: mediatek: Add MT8196 vdecsys clock support	[Body]
[PATCH v4 27/27] clk: mediatek: Add MT8196 vencsys clock support	[Body]

Session 2025-08-05

ID (for dev)	5b599253-03a5-4b9a-bda9-7707fb2c23ac
Status	finished
Triaged	OK [Log]
Execution Log	[Link]

Test	Base	Patched	Verdict
Build Base	d9104cec3e8fe4b458b74709853231385779001f [Config]		passed [Log]
Build Patched		d9104cec3e8fe4b458b74709853231385779001f [Config] [patched]	passed [Log]
Boot test: Base	d9104cec3e8fe4b458b74709853231385779001f [Config]		passed
Boot test: Patched		d9104cec3e8fe4b458b74709853231385779001f [Config] [patched]	passed
Fuzzing	d9104cec3e8fe4b458b74709853231385779001f [Config]	d9104cec3e8fe4b458b74709853231385779001f [Config] [patched]	passed [Log] [Artifacts]