Patch Series

Subject dpll/ice: Add TXC DPLL type and full TX reference clock control for E825
Author grzegorz.nitka@intel.com
Date 2026-03-18 09:06:47 +0000 UTC
Version
Cc aleksandr.loktionov@intel.com andrew@lunn.ch anthony.l.nguyen@intel.com arkadiusz.kubalewski@intel.com davem@davemloft.net donald.hunter@gmail.com grzegorz.nitka@intel.com horms@kernel.org intel-wired-lan@lists.osuosl.org ivecera@redhat.com jiri@resnulli.us kuba@kernel.org linux-kernel@vger.kernel.org netdev@vger.kernel.org pabeni@redhat.com poros@redhat.com prathosh.satish@microchip.com przemyslaw.kitszel@intel.com richardcochran@gmail.com vadim.fedorenko@linux.dev

Patches (8)

Name Content [All]
[PATCH net-next 1/8] dpll: add new DPLL type for transmit clock (TXC) usage [Body]
[PATCH net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL [Body]
[PATCH net-next 3/8] dpll: extend pin notifier and netlink events with notification source ID [Body]
[PATCH net-next 4/8] dpll: zl3073x: allow SyncE_Ref pin state change [Body]
[PATCH net-next 5/8] ice: add TX clock (TXC) DPLL interface for E825 devices [Body]
[PATCH net-next 6/8] ice: implement CPI support for E825C [Body]
[PATCH net-next 7/8] ice: add Tx reference clock index handling to AN restart command [Body]
[PATCH net-next 8/8] ice: add TX reference clock (tx_clk) control for E825 devices [Body]

Session 2026-03-18

ID (for dev) 9b0af67b-7a7e-4dec-b742-9b38129f12de
Status finished
Triaged OK [Log]
Execution Log [Link]
Test Base Patched Verdict
[KASAN] Build Base 8737d7194d6d5947c3d7d8813895b44a25b84477 [Config] passed [Log]
[KASAN] Boot test: Base 8737d7194d6d5947c3d7d8813895b44a25b84477 [Config] passed [Log]
[KASAN] Build Patched 8737d7194d6d5947c3d7d8813895b44a25b84477 [Config] [patched] passed [Log]
[KASAN] Boot test: Patched 8737d7194d6d5947c3d7d8813895b44a25b84477 [Config] [patched] passed [Log]
[KASAN] Fuzz 8737d7194d6d5947c3d7d8813895b44a25b84477 [Config] 8737d7194d6d5947c3d7d8813895b44a25b84477 [Config] [patched] skipped [Log] [Artifacts]