Subject	target/i386: Fix Hygon vendor-specific CPU behavior
Author	zhang_wei@open-hieco.net
Date	2026-08-24 04:53:05 +0000 UTC
Version	Version 1 Version 2 Version 3
Cc	kvm@vger.kernel.org mst@redhat.com mtosatti@redhat.com pbonzini@redhat.com qemu-devel@nongnu.org xuyongwei@open-hieco.net zhang_wei@open-hieco.net zhao1.liu@intel.com zhouyanjing@hygon.cn

Patches (10)

Name	Content [All]
[PATCH v3 01/10] target/i386: Sync AMD CPUID aliases for Hygon	[Body]
[PATCH v3 02/10] target/i386: Hide Intel cache CPUID leaves for Hygon	[Body]
[PATCH v3 03/10] target/i386: Hide ARCH_CAPABILITIES for Hygon	[Body]
[PATCH v3 04/10] target/i386/kvm: Use AMD MCE status encoding for Hygon	[Body]
[PATCH v3 05/10] target/i386/kvm: Classify PMU vendor families	[Body]
[PATCH v3 06/10] target/i386/kvm: Use AMD PMU MSR paths for Hygon	[Body]
[PATCH v3 07/10] target/i386: Do not broadcast injected MCEs for Hygon	[Body]
[PATCH v3 08/10] hw/i386: Reserve AMD IOMMU HT GPA range for Hygon	[Body]
[PATCH v3 09/10] target/i386: Use AMD legacy cache fallback for Hygon	[Body]
[PATCH v3 10/10] target/i386: Use AMD ucode-rev default for Hygon	[Body]

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