AMD defines CPUID[0x80000001].EDX bits as aliases for a subset of CPUID[1].EDX. QEMU currently synchronizes those aliases only when the guest CPU vendor is AuthenticAMD. Hygon Dhyana uses the HygonGenuine vendor string, but implements the same AMD-compatible extended CPUID feature aliases. This can leave QEMU advertising a feature in CPUID[1].EDX while the matching extended alias in CPUID[0x80000001].EDX stays clear. This inconsistent CPUID state can confuse guest OS feature detection. Apply the alias synchronization to Hygon CPUs as well. Gate the new behavior with x-hygon-vendor-abi-fixes and disable it for pc-11.1 and older machine types, because the CPUID result is guest-visible ABI and must remain migration-compatible. Add qtest coverage for the Dhyana model, including the compat property. Signed-off-by: Tina Zhang Tested-by: Yongwei Xu --- hw/i386/pc.c | 4 +- target/i386/cpu.c | 10 ++-- target/i386/cpu.h | 12 +++++ tests/qtest/test-x86-cpuid-compat.c | 76 +++++++++++++++++++++++++++++ 4 files changed, 98 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e9e4fc262b..2b4e322b2f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -74,7 +74,9 @@ #include "hw/xen/xen-bus.h" #endif -GlobalProperty pc_compat_11_1[] = {}; +GlobalProperty pc_compat_11_1[] = { + { TYPE_X86_CPU, "x-hygon-vendor-abi-fixes", "false" }, +}; const size_t pc_compat_11_1_len = G_N_ELEMENTS(pc_compat_11_1); GlobalProperty pc_compat_11_0[] = {}; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e5ffb10d15..eca51de50d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10147,10 +10147,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) } } - /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on - * CPUID[1].EDX. + /* + * CPUs that use AMD-compatible extended CPUID aliases must keep selected + * CPUID[0x80000001].EDX bits synchronized with CPUID[1].EDX. */ - if (IS_AMD_CPU(env)) { + if (IS_AMD_CPU(env) || + (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env))) { env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] & CPUID_EXT2_AMD_ALIASES); @@ -10810,6 +10812,8 @@ static const Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only-v2", X86CPU, vendor_cpuid_only_v2, true), + DEFINE_PROP_BOOL("x-hygon-vendor-abi-fixes", X86CPU, + hygon_vendor_abi_fixes, true), DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 641f3ee5c2..61299e955c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1288,6 +1288,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_VENDOR_ZHAOXIN1 "CentaurHauls" #define CPUID_VENDOR_ZHAOXIN2 " Shanghai " +#define CPUID_VENDOR_HYGON_1 0x6f677948 /* "Hygo" */ +#define CPUID_VENDOR_HYGON_2 0x6e65476e /* "nGen" */ +#define CPUID_VENDOR_HYGON_3 0x656e6975 /* "uine" */ #define CPUID_VENDOR_HYGON "HygonGenuine" #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ @@ -1296,6 +1299,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) +#define IS_HYGON_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_HYGON_1 && \ + (env)->cpuid_vendor2 == CPUID_VENDOR_HYGON_2 && \ + (env)->cpuid_vendor3 == CPUID_VENDOR_HYGON_3) #define IS_ZHAOXIN1_CPU(env) \ ((env)->cpuid_vendor1 == CPUID_VENDOR_ZHAOXIN1_1 && \ (env)->cpuid_vendor2 == CPUID_VENDOR_ZHAOXIN1_2 && \ @@ -2473,6 +2479,12 @@ struct ArchCPU { */ bool vendor_cpuid_only_v2; + /* + * Compatibility bits for old machine types (PC machine v11.1 and older). + * If true, apply Hygon vendor-specific CPU ABI fixes. + */ + bool hygon_vendor_abi_fixes; + /* Only advertise TOPOEXT features that AMD defines */ bool amd_topoext_features_only; diff --git a/tests/qtest/test-x86-cpuid-compat.c b/tests/qtest/test-x86-cpuid-compat.c index 17c0965827..44d4631cd6 100644 --- a/tests/qtest/test-x86-cpuid-compat.c +++ b/tests/qtest/test-x86-cpuid-compat.c @@ -113,6 +113,21 @@ typedef struct FeatureTestArgs { bool expected_value; } FeatureTestArgs; +typedef struct BoolPropTestArgs { + /* Test name */ + const char *name; + /* CPU type */ + const char *cpu; + /* CPU features (may be NULL) */ + const char *cpufeat; + /* machine type (may be NULL to use default machine) */ + const char *machine; + /* CPU property to read */ + const char *property; + /* expected value of the property */ + bool expected_value; +} BoolPropTestArgs; + /* Get the value for a feature word in a X86CPUFeatureWordInfo list */ static uint32_t get_feature_word(QList *features, uint32_t eax, uint32_t ecx, const char *reg) @@ -170,6 +185,38 @@ static void test_feature_flag(const void *data) g_free(cmdline); } +static void test_bool_prop(const void *data) +{ + const BoolPropTestArgs *args = data; + char *cmdline; + char *save; + char *path; + bool value; + + cmdline = g_strdup_printf("-cpu %s", args->cpu); + + if (args->cpufeat) { + save = cmdline; + cmdline = g_strdup_printf("%s,%s", cmdline, args->cpufeat); + g_free(save); + } + if (args->machine) { + save = cmdline; + cmdline = g_strdup_printf("-machine %s %s", args->machine, cmdline); + g_free(save); + } + + qtest_start(cmdline); + path = get_cpu0_qom_path(); + value = qom_get_bool(path, args->property); + qtest_end(); + + g_assert_cmpint(value, ==, args->expected_value); + + g_free(path); + g_free(cmdline); +} + static void test_plus_minus_subprocess(void) { char *path; @@ -407,6 +454,28 @@ static const FeatureTestArgs feature_tests[] = { "max", "mmx=off", 1, 0, "EDX", 23, false, }, + { + "x86/cpuid/features/dhyana/ext-mmx", + "Dhyana", NULL, + 0x80000001, 0, "EDX", 23, true, + }, + { + "x86/cpuid/features/dhyana/ext-mmx/compat-off", + "Dhyana", "x-hygon-vendor-abi-fixes=off", + 0x80000001, 0, "EDX", 23, false, + }, +}; + +static const BoolPropTestArgs bool_prop_tests[] = { + { + "x86/cpuid/props/dhyana/hygon-vendor-abi-fixes/default", + "Dhyana", NULL, NULL, "x-hygon-vendor-abi-fixes", true, + }, + { + "x86/cpuid/props/dhyana/hygon-vendor-abi-fixes/pc-i440fx-11.1", + "Dhyana", NULL, "pc-i440fx-11.1", + "x-hygon-vendor-abi-fixes", false, + }, }; int main(int argc, char **argv) @@ -433,6 +502,13 @@ int main(int argc, char **argv) qtest_add_data_func(feature_tests[i].name, &feature_tests[i], test_feature_flag); } + for (int i = 0; i < ARRAY_SIZE(bool_prop_tests); i++) { + if (!qtest_has_cpu_model(bool_prop_tests[i].cpu)) { + continue; + } + qtest_add_data_func(bool_prop_tests[i].name, + &bool_prop_tests[i], test_bool_prop); + } return g_test_run(); } -- 2.43.7 When x-vendor-cpuid-only is enabled, QEMU suppresses CPUID leaves 2 and 4 for AuthenticAMD CPUs because those leaves describe Intel cache information. Hygon Dhyana uses the HygonGenuine vendor string, so it currently skips that filtering and can expose Intel cache leaves together with AMD/Hygon extended cache leaves. That is inconsistent guest-visible CPUID: Hygon Dhyana provides cache information through the extended cache leaves, so it should not also advertise the Intel cache descriptor and deterministic cache parameter leaves. Apply the same leaf 2 and leaf 4 filtering to Hygon CPUs when the vendor CPU ABI compat gate is enabled. The gate keeps the old CPUID output for pc-11.1 and older machine types. Signed-off-by: Tina Zhang Reviewed-by: Zhao Liu --- target/i386/cpu.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index eca51de50d..c87f4684a3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8608,6 +8608,21 @@ uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) } } +/* + * CPUID leaves 2 and 4 describe Intel cache information. AMD CPUs use + * extended cache leaves instead, and Hygon Dhyana follows that AMD/Hygon + * convention. Enable the corrected Hygon behavior only for machine types + * where the CPU ABI compat gate is on. + */ +static bool x86_cpu_filter_intel_cache_leaves(const X86CPU *cpu) +{ + const CPUX86State *env = &cpu->env; + + return cpu->vendor_cpuid_only && + (IS_AMD_CPU(env) || + (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env))); +} + void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) @@ -8693,7 +8708,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; - } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + } else if (x86_cpu_filter_intel_cache_leaves(cpu)) { *eax = *ebx = *ecx = *edx = 0; break; } @@ -8729,7 +8744,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, CPU_TOPOLOGY_LEVEL_SOCKET), 4095) << 14; } } - } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + } else if (x86_cpu_filter_intel_cache_leaves(cpu)) { *eax = *ebx = *ecx = *edx = 0; } else { *eax = 0; -- 2.43.7 IA32_ARCH_CAPABILITIES is an Intel-defined MSR. KVM can synthesize the CPUID bit and read-only MSR for non-Intel guests, and QEMU already hides that interface for AMD CPU models because Windows may not expect it on AMD-compatible CPUs. Hygon Dhyana uses the HygonGenuine vendor string, so it currently skips that AMD filter. If arch-capabilities=on is requested, QEMU can expose CPUID.7.0.EDX[ARCH_CAPABILITIES] and the associated MSR feature word to a Hygon guest. That creates a vendor-inconsistent CPU ABI: the guest sees an AMD-compatible vendor and cache/topology interface, but also sees an Intel-specific architectural capabilities MSR. Guests that choose CPU mitigation or feature paths from the vendor can mis-handle that combination; Windows is known to be sensitive to ARCH_CAPABILITIES on AMD-compatible CPUs. Apply the same ARCH_CAPABILITIES hiding rule to Hygon CPUs when the vendor CPU ABI compat gate is enabled. Keep arch_cap_always_on as the migration escape hatch, and keep the old Hygon CPUID/MSR output for pc-11.1 and older machine types via x-hygon-vendor-abi-fixes=false. Signed-off-by: Tina Zhang Reviewed-by: Zhao Liu --- target/i386/cpu.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c87f4684a3..8666f66df8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8209,6 +8209,8 @@ static uint8_t x86_cpu_get_host_avx10_version(void) return ebx & 0xff; } +static bool x86_cpu_should_hide_arch_capabilities(const X86CPU *cpu); + uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) { FeatureWordInfo *wi = &feature_word_info[w]; @@ -8294,15 +8296,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) break; case FEAT_7_0_EDX: - /* - * Windows does not like ARCH_CAPABILITIES on AMD machines at all. - * Do not show the fake ARCH_CAPABILITIES MSR that KVM sets up, - * except if needed for migration. - * - * When arch_cap_always_on is removed, this tweak can move to - * kvm_arch_get_supported_cpuid. - */ - if (cpu && IS_AMD_CPU(&cpu->env) && !cpu->arch_cap_always_on) { + if (cpu && x86_cpu_should_hide_arch_capabilities(cpu)) { unavail = CPUID_7_0_EDX_ARCH_CAPABILITIES; } break; @@ -8608,6 +8602,27 @@ uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) } } +/* + * Windows does not like ARCH_CAPABILITIES on AMD machines at all. + * Do not show the fake ARCH_CAPABILITIES MSR that KVM sets up, + * except if needed for migration. Apply the same rule to Hygon CPUs when + * the corrected vendor CPU ABI is enabled. + * + * When arch_cap_always_on is removed, this tweak can move to + * kvm_arch_get_supported_cpuid. + */ +static bool x86_cpu_should_hide_arch_capabilities(const X86CPU *cpu) +{ + const CPUX86State *env = &cpu->env; + + if (cpu->arch_cap_always_on) { + return false; + } + + return IS_AMD_CPU(env) || + (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env)); +} + /* * CPUID leaves 2 and 4 describe Intel cache information. AMD CPUs use * extended cache leaves instead, and Hygon Dhyana follows that AMD/Hygon -- 2.43.7 QEMU's KVM memory-failure injection path builds synthetic MCI_STATUS records for the guest CPU. The status encoding is vendor-specific: Intel-style records use bits such as MCI_STATUS_S and MCI_STATUS_AR for action-required events, while the AMD path uses the AMD memory-failure encoding. Today QEMU selects the AMD status encoding only for AuthenticAMD guests. Hygon guests should use the AMD status encoding as well, but currently get Intel-style injected status bits, including MCI_STATUS_S and MCI_STATUS_AR for action-required events, and a non-deferred action-optional record. That can prevent a guest OS running on the Hygon CPU model from handling the injected MCE correctly. Use the AMD injected-memory-failure MCE status encoding for Hygon guests as well. This does not depend on Hygon exposing CPUID 0x80000007.EBX recovery features such as SUCCOR, and it does not advertise any new recovery capability. The change is limited to QEMU's synthetic KVM memory-failure MCE status; it does not change CPUID, MCE bank state, or migrated CPU state. Signed-off-by: Tina Zhang Reviewed-by: Zhao Liu --- target/i386/kvm/kvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 644c45fb0a..d1c6dbe636 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -707,7 +707,7 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) uint64_t mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV; int flags = 0; - if (!IS_AMD_CPU(env)) { + if (!IS_AMD_CPU(env) && !IS_HYGON_CPU(env)) { status |= MCI_STATUS_S | MCI_STATUS_UC; if (code == BUS_MCEERR_AR) { status |= MCI_STATUS_AR | 0x134; -- 2.43.7 The Intel and Zhaoxin PMU architectures are compatible, while AMD uses a separate PMU CPUID/MSR layout. KVM's PMU initialization, host/guest compatibility, and MSR save/restore paths open-code these vendor checks in several places. Introduce X86PMUVendor and helpers that classify the existing CPU and host vendors by PMU architecture. Use the classification consistently for the compatibility check, PMU initialization, and PMU MSR paths. This is a refactoring with no functional change. Signed-off-by: Tina Zhang --- target/i386/kvm/kvm.c | 72 +++++++++++++++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 17 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index d1c6dbe636..01fc1d0674 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2166,24 +2166,53 @@ static void kvm_init_pmu_info_amd(struct kvm_cpuid2 *cpuid, X86CPU *cpu) } } -static bool is_host_compat_vendor(CPUX86State *env) +typedef enum X86PMUVendor { + X86_PMU_VENDOR_UNKNOWN, + X86_PMU_VENDOR_INTEL, + X86_PMU_VENDOR_AMD, +} X86PMUVendor; + +static X86PMUVendor x86_cpu_pmu_vendor(const CPUX86State *env) +{ + if (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) { + return X86_PMU_VENDOR_INTEL; + } + + if (IS_AMD_CPU(env)) { + return X86_PMU_VENDOR_AMD; + } + + return X86_PMU_VENDOR_UNKNOWN; +} + +static X86PMUVendor x86_host_pmu_vendor(void) { char host_vendor[CPUID_VENDOR_SZ + 1]; host_cpu_vendor_fms(host_vendor, NULL, NULL, NULL); - /* - * Intel and Zhaoxin are compatible. - */ - if ((g_str_equal(host_vendor, CPUID_VENDOR_INTEL) || - g_str_equal(host_vendor, CPUID_VENDOR_ZHAOXIN1) || - g_str_equal(host_vendor, CPUID_VENDOR_ZHAOXIN2)) && - (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { - return true; + if (g_str_equal(host_vendor, CPUID_VENDOR_INTEL) || + g_str_equal(host_vendor, CPUID_VENDOR_ZHAOXIN1) || + g_str_equal(host_vendor, CPUID_VENDOR_ZHAOXIN2)) { + return X86_PMU_VENDOR_INTEL; } - return g_str_equal(host_vendor, CPUID_VENDOR_AMD) && - IS_AMD_CPU(env); + if (g_str_equal(host_vendor, CPUID_VENDOR_AMD)) { + return X86_PMU_VENDOR_AMD; + } + + return X86_PMU_VENDOR_UNKNOWN; +} + +/* + * The guest vPMU can be virtualized only when the host and guest PMU + * architectures are compatible. + */ +static bool is_host_compat_vendor(CPUX86State *env) +{ + X86PMUVendor guest = x86_cpu_pmu_vendor(env); + + return guest != X86_PMU_VENDOR_UNKNOWN && guest == x86_host_pmu_vendor(); } static void kvm_init_pmu_info(struct kvm_cpuid2 *cpuid, X86CPU *cpu) @@ -2211,10 +2240,15 @@ static void kvm_init_pmu_info(struct kvm_cpuid2 *cpuid, X86CPU *cpu) return; } - if (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) { + switch (x86_cpu_pmu_vendor(env)) { + case X86_PMU_VENDOR_INTEL: kvm_init_pmu_info_intel(cpuid); - } else if (IS_AMD_CPU(env)) { + break; + case X86_PMU_VENDOR_AMD: kvm_init_pmu_info_amd(cpuid, cpu); + break; + case X86_PMU_VENDOR_UNKNOWN: + break; } } @@ -4268,7 +4302,8 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr); } - if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) && pmu_version > 0) { + if (x86_cpu_pmu_vendor(env) == X86_PMU_VENDOR_INTEL && + pmu_version > 0) { if (pmu_version > 1) { /* Stop the counter. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); @@ -4300,7 +4335,8 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) } } - if (IS_AMD_CPU(env) && pmu_version > 0) { + if (x86_cpu_pmu_vendor(env) == X86_PMU_VENDOR_AMD && + pmu_version > 0) { uint32_t sel_base = MSR_K7_EVNTSEL0; uint32_t ctr_base = MSR_K7_PERFCTR0; /* @@ -4846,7 +4882,8 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); } - if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) && pmu_version > 0) { + if (x86_cpu_pmu_vendor(env) == X86_PMU_VENDOR_INTEL && + pmu_version > 0) { if (pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); @@ -4862,7 +4899,8 @@ static int kvm_get_msrs(X86CPU *cpu) } } - if (IS_AMD_CPU(env) && pmu_version > 0) { + if (x86_cpu_pmu_vendor(env) == X86_PMU_VENDOR_AMD && + pmu_version > 0) { uint32_t sel_base = MSR_K7_EVNTSEL0; uint32_t ctr_base = MSR_K7_PERFCTR0; /* -- 2.43.7 On SVM, KVM uses the AMD PMU implementation and AMD PMU CPUID/MSR layout. Hygon guests that enable PMU and request AMD PMU CPUID features such as perfctr-core need QEMU's KVM PMU setup and MSR state paths to use that layout too. The relevant QEMU KVM PMU paths are currently restricted to AuthenticAMD guests: host/guest PMU compatibility checks, AMD PMU information initialization, and AMD PMU MSR save/restore. For a Hygon Dhyana guest with pmu=on, the compatibility check reports vPMU as unsupported solely because the guest vendor is HygonGenuine rather than AuthenticAMD. If the VM continues, QEMU still skips AMD PMU setup and never saves or restores the AMD PMU MSRs for the Hygon guest. Treat Hygon as using the AMD PMU CPUID/MSR layout for these KVM PMU paths. Because the PMU MSR layout is shared, accept both AMD and Hygon hosts for guests using that layout. This intentionally allows the PMU compatibility check to pass for AMD-host/Hygon-guest and Hygon-host/AMD-guest combinations. This does not enable PMU, perfctr-core, or perfmon-v2 by default for the Dhyana CPU model. On backward migration to older QEMU, Hygon PMU MSR state may still be dropped because older QEMU did not write that state back through the AMD PMU MSR KVM paths for Hygon guests. Signed-off-by: Tina Zhang --- target/i386/kvm/kvm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 01fc1d0674..f33bb6bd06 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2178,7 +2178,7 @@ static X86PMUVendor x86_cpu_pmu_vendor(const CPUX86State *env) return X86_PMU_VENDOR_INTEL; } - if (IS_AMD_CPU(env)) { + if (IS_AMD_CPU(env) || IS_HYGON_CPU(env)) { return X86_PMU_VENDOR_AMD; } @@ -2197,7 +2197,8 @@ static X86PMUVendor x86_host_pmu_vendor(void) return X86_PMU_VENDOR_INTEL; } - if (g_str_equal(host_vendor, CPUID_VENDOR_AMD)) { + if (g_str_equal(host_vendor, CPUID_VENDOR_AMD) || + g_str_equal(host_vendor, CPUID_VENDOR_HYGON)) { return X86_PMU_VENDOR_AMD; } -- 2.43.7 cpu_x86_support_mca_broadcast() excludes AMD CPUs because QEMU handles AMD injected MCEs as local machine checks, not as Intel-style broadcast MCEs. Hygon Dhyana missed that exclusion: it is not an AMD vendor CPU and its family is greater than 6, so QEMU reported MCA broadcast support. This affects QEMU's synthetic MCE injection paths. KVM memory-failure injection uses this helper to decide whether to set MCE_INJECT_BROADCAST. HMP 'mce -b' uses it to decide whether a broadcast request is valid. With a multi-vCPU Dhyana guest, QEMU could fan out an injected MCE to secondary vCPUs and populate extra bank records. Linux routes Hygon through the AMD MCE feature initialization path and does not use Intel/Zhaoxin LMCE broadcast handling for Hygon. Do not advertise Intel-style MCA broadcast support for Hygon in QEMU's injected MCE paths. This is limited to the MCE broadcast-support decision. It does not claim that all Hygon MCE/MCA behavior is identical to AMD. Signed-off-by: Tina Zhang Reviewed-by: Zhao Liu --- target/i386/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index 6836214162..c5bbe9715b 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -95,7 +95,7 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) int family = 0; int model = 0; - if (IS_AMD_CPU(env)) { + if (IS_AMD_CPU(env) || IS_HYGON_CPU(env)) { return 0; } -- 2.43.7 pc_memory_init() avoids the AMD IOMMU HyperTransport range below 1 TiB only for AMD vCPUs. Dhyana therefore allows RAM, hotplug address space, or 64-bit PCI MMIO to overlap 0xfd00000000-0xffffffffff. Linux supports Dhyana platforms in the AMD IOMMU driver. The driver reports this range as reserved unless the IOMMU advertises FEATURE_HT_RANGE_IGNORE. A VFIO device cannot DMA to guest addresses that QEMU places in the reserved range: VFIO_DMA_MAP may fail with -EINVAL, or the IOMMU may report an INVALID_DEVICE_REQUEST fault. Apply the AMD IOMMU HT GPA layout to Hygon vCPUs. When the possible address space reaches the reserved range, move RAM above 4 GiB to 1 TiB; also expose the range as reserved in E820 when the vCPU can address it. Changing the GPA layout affects migration, so enable the Hygon behavior through x-hygon-vendor-abi-fixes. pc-11.1 and older machine types retain their previous Hygon layout. The existing enforce_amd_1tb_hole setting continues to preserve the AMD layout of pc/q35 machine types through 7.0. Add functional tests for Dhyana with pc-q35-11.2 and with pc-q35-11.1 compatibility. Signed-off-by: Yanjing Zhou Signed-off-by: Tina Zhang --- hw/i386/pc.c | 26 ++++++++++---- .../functional/x86_64/test_mem_addr_space.py | 36 +++++++++++++++++++ 2 files changed, 55 insertions(+), 7 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2b4e322b2f..1220dbd79c 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -738,6 +738,24 @@ static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) +/* + * The HyperTransport range close to the 1 TiB boundary is unique to AMD + * and Hygon hosts with IOMMUs enabled. Restrict RAM-above-4G relocation + * to above 1 TiB to AMD and Hygon vCPUs only. @enforce_amd_1tb_hole is + * false in machine types through 7.0 and @x-hygon-vendor-abi-fixes is + * false in machine types through 11.1, for compatibility purposes. + */ +static bool x86_cpu_has_iommu_ht_gpa_hole(const PCMachineClass *pcmc, + const X86CPU *cpu) +{ + if (!pcmc->enforce_amd_1tb_hole) { + return false; + } + + return IS_AMD_CPU(&cpu->env) || + (IS_HYGON_CPU(&cpu->env) && cpu->hygon_vendor_abi_fixes); +} + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -761,13 +779,7 @@ void pc_memory_init(PCMachineState *pcms, linux_boot = (machine->kernel_filename != NULL); - /* - * The HyperTransport range close to the 1T boundary is unique to AMD - * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation - * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in - * older machine types (<= 7.0) for compatibility purposes. - */ - if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { + if (x86_cpu_has_iommu_ht_gpa_hole(pcmc, cpu)) { /* Bail out if max possible address does not cross HT range */ if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; diff --git a/tests/functional/x86_64/test_mem_addr_space.py b/tests/functional/x86_64/test_mem_addr_space.py index 61b4a190b4..fa6c603b96 100755 --- a/tests/functional/x86_64/test_mem_addr_space.py +++ b/tests/functional/x86_64/test_mem_addr_space.py @@ -208,6 +208,24 @@ def test_phybits_low_tcg_q35_71_amd(self): self.assertEqual(self.vm.exitcode(), 1, "QEMU exit code should be 1") self.assertRegex(self.vm.get_log(), r'phys-bits too low') + def test_phybits_low_tcg_q35_112_hygon(self): + """ + Same as q35-7.1 AMD case except that here we check that Dhyana + follows the same AMD IOMMU HT reserved GPA range with q35-11.2. + """ + self.ensure_64bit_binary() + self.set_machine('pc-q35-11.2') + self.vm.add_args('-S', '-cpu', 'Dhyana,phys-bits=40', + '-m', '512,slots=1,maxmem=976G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + self.vm.wait() + self.assertEqual(self.vm.exitcode(), 1, "QEMU exit code should be 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + def test_phybits_ok_tcg_q35_70_amd(self): """ Same as q35-7.0 AMD case except that here we check that QEMU can @@ -225,6 +243,24 @@ def test_phybits_ok_tcg_q35_70_amd(self): self.vm.shutdown() self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + def test_phybits_ok_tcg_q35_111_hygon(self): + """ + Same as q35-7.1 Dhyana case except that here we check that the + q35-11.1 compatibility setting keeps the old memory layout. + """ + self.ensure_64bit_binary() + self.set_machine('pc-q35-11.1') + self.vm.add_args('-S', '-cpu', 'Dhyana,phys-bits=40', + '-m', '512,slots=1,maxmem=976G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + def test_phybits_ok_tcg_q35_71_amd(self): """ Same as q35-7.1 AMD case except that here we check that QEMU can -- 2.43.7 When legacy-cache=on, x86_cpu_realizefn() builds a hardcoded cache model. It selected the AMD legacy cache table only for CPUs with the AuthenticAMD vendor ID. Dhyana uses the HygonGenuine vendor ID, so this explicit compatibility path fell back to QEMU's old Intel legacy cache table. The wrong table is visible through AMD extended cache leaves. With the Intel legacy table, Dhyana reports 32 KiB, 8-way L1 caches in CPUID 0x80000005 and a 4 MiB, 16-way L2 cache in CPUID 0x80000006. Linux uses the AMD/Hygon cache enumeration path for Hygon and reads these AMD extended cache leaves. Use the AMD legacy cache table for Hygon in this fallback path when the new vendor CPU ABI is enabled. Keep the old fallback for pc-11.1 and older machine types through x-hygon-vendor-abi-fixes=false. The default Dhyana model is unchanged because it provides EPYC cache_info and therefore defaults legacy-cache to off. The guest-visible change is limited to users who explicitly configure legacy-cache=on on new machine types. Signed-off-by: Tina Zhang Reviewed-by: Zhao Liu --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8666f66df8..f65a5b32bc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10329,7 +10329,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) env->enable_legacy_vendor_cache = true; } - if (IS_AMD_CPU(env)) { + if (IS_AMD_CPU(env) || + (IS_HYGON_CPU(env) && cpu->hygon_vendor_abi_fixes)) { env->cache_info = legacy_amd_cache_info; } else { env->cache_info = legacy_intel_cache_info; -- 2.43.7 QEMU currently gives named Hygon Dhyana CPUs the non-AMD default ucode-rev value, 0x100000000. That is the Intel/KVM-VMX-shaped encoding, where the visible revision is in the high 32 bits. Linux reads MSR 0x8b for Hygon CPUs through the AMD patch-level path, using MSR_AMD64_PATCH_LEVEL and storing the low 32 bits as cpuinfo_x86.microcode. With the old QEMU default, a Dhyana guest sees microcode revision 0. Use the AMD/KVM-SVM-shaped default, 0x01000065, for Hygon on this specific MSR 0x8b default path. This does not route Hygon through AMD microcode loading and does not claim that Hygon CPUs are otherwise identical to AMD CPUs. Preserve migration ABI through the vendor CPU ABI compatibility gate used by this Hygon bug-fix group. pc-11.1 and older machine types leave that gate off, so they retain the previous ucode-rev default. Explicit user-provided ucode-rev values still override the default. Add qtest coverage for the new default, the compatibility cases, and an explicit user override. Signed-off-by: Tina Zhang Reviewed-by: Zhao Liu --- target/i386/cpu.c | 3 ++- tests/qtest/test-x86-cpuid-compat.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f65a5b32bc..0630cfd8b2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10222,7 +10222,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) * needs to happen after the evenual setting of ucode_rev in * accel-specific code in cpu_common_realize. */ - if (IS_AMD_CPU(env)) { + if (IS_AMD_CPU(env) || + (IS_HYGON_CPU(env) && cpu->hygon_vendor_abi_fixes)) { cpu->ucode_rev = 0x01000065; } else { cpu->ucode_rev = 0x100000000ULL; diff --git a/tests/qtest/test-x86-cpuid-compat.c b/tests/qtest/test-x86-cpuid-compat.c index 44d4631cd6..13c9ddb4db 100644 --- a/tests/qtest/test-x86-cpuid-compat.c +++ b/tests/qtest/test-x86-cpuid-compat.c @@ -404,6 +404,25 @@ static const CpuidTestArgs cpuid_tests[] = { "486", "xlevel2=0xC0000002,xstore=on", NULL, "xlevel2", 0xC0000002, }, + { + "x86/cpuid/props/dhyana/ucode-rev/default", + "Dhyana", NULL, NULL, "ucode-rev", 0x01000065, + }, + { + "x86/cpuid/props/dhyana/ucode-rev/compat-off", + "Dhyana", "x-hygon-vendor-abi-fixes=off", NULL, + "ucode-rev", 0x100000000LL, + }, + { + "x86/cpuid/props/dhyana/ucode-rev/pc-i440fx-11.1", + "Dhyana", NULL, "pc-i440fx-11.1", + "ucode-rev", 0x100000000LL, + }, + { + "x86/cpuid/props/dhyana/ucode-rev/user", + "Dhyana", "ucode-rev=0x12345678", NULL, + "ucode-rev", 0x12345678, + }, }; /* -- 2.43.7