Subject	dpll/ice: Add generic DPLL type and full TX reference clock control for E825
Author	grzegorz.nitka@intel.com
Date	2026-05-14 22:59:39 +0000 UTC
Version	Version 7 Version 8 Version 9 Version 11 Version 12 Version 13 Version 14
Cc	aleksandr.loktionov@intel.com andrew@lunn.ch anthony.l.nguyen@intel.com arkadiusz.kubalewski@intel.com davem@davemloft.net donald.hunter@gmail.com edumazet@google.com grzegorz.nitka@intel.com horms@kernel.org intel-wired-lan@lists.osuosl.org ivecera@redhat.com jiri@nvidia.com jiri@resnulli.us kuba@kernel.org linux-kernel@vger.kernel.org netdev@vger.kernel.org pabeni@redhat.com poros@redhat.com prathosh.satish@microchip.com przemyslaw.kitszel@intel.com richardcochran@gmail.com vadim.fedorenko@linux.dev

Patches (8)

Name	Content [All]
[PATCH v9 net-next 1/8] dpll: add generic DPLL type	[Body]
[PATCH v9 net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL	[Body]
[PATCH v9 net-next 3/8] dpll: extend pin notifier with notification source ID	[Body]
[PATCH v9 net-next 4/8] dpll: allow fwnode pins to attempt state change without capability bit	[Body]
[PATCH v9 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825	[Body]
[PATCH v9 net-next 6/8] ice: implement CPI support for E825C	[Body]
[PATCH v9 net-next 7/8] ice: add Tx reference clock index handling to AN restart command	[Body]
[PATCH v9 net-next 8/8] ice: implement E825 TX ref clock control and TXC hardware sync status	[Body]

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