Subject dpll/ice: Add TXC DPLL type and full TX reference clock control for E825
Author grzegorz.nitka@intel.com
Date 2026-04-02 23:06:19 +0000 UTC
Version
Cc aleksandr.loktionov@intel.com andrew@lunn.ch anthony.l.nguyen@intel.com arkadiusz.kubalewski@intel.com davem@davemloft.net donald.hunter@gmail.com edumazet@google.com grzegorz.nitka@intel.com horms@kernel.org intel-wired-lan@lists.osuosl.org ivecera@redhat.com jiri@nvidia.com jiri@resnulli.us kuba@kernel.org linux-kernel@vger.kernel.org netdev@vger.kernel.org pabeni@redhat.com poros@redhat.com prathosh.satish@microchip.com przemyslaw.kitszel@intel.com richardcochran@gmail.com vadim.fedorenko@linux.dev
Patches (8)
Expand
Series Summary
Passed
✓ All tests passed. No findings.
Sessions
Session 2026-04-02
Passed
ID (for dev) 959ca327-61cd-4ead-8eb3-4f6e19a0934f
Status finished
Triaged OK [Log]
Execution Log [Link]
Test Base Patched Verdict
[KASAN] Build Base f35340f2d653f1003602878403c901396ab03c17 [Config] passed [Log]
[KASAN] Boot test: Base f35340f2d653f1003602878403c901396ab03c17 [Config] passed [Log]
[KASAN] Build Patched f35340f2d653f1003602878403c901396ab03c17 [Config] [patched] passed [Log]
[KASAN] Boot test: Patched f35340f2d653f1003602878403c901396ab03c17 [Config] [patched] passed [Log]
[KASAN] Fuzz f35340f2d653f1003602878403c901396ab03c17 [Config] f35340f2d653f1003602878403c901396ab03c17 [Config] [patched] skipped [Log] [Artifacts]