| 2026-08-25 02:26 UTC |
Make SBR work for CXL Downstream Ports |
2 |
fabio.m.de.francesco@linux.intel.com |
finished
in 4h9m0s
|
| 2026-08-13 09:36 UTC |
vfio/pci: Add CXL Type-2 device passthrough support |
4 |
mhonap@nvidia.com |
finished
in 7m0s
|
| 2026-03-22 19:53 UTC |
dax/hmem, cxl: Coordinate Soft Reserved handling with CXL and HMEM |
8 |
smita.koralahallichannabasappa@amd.com |
finished
in 1h52m0s
|
| 2026-03-19 01:14 UTC |
dax/hmem, cxl: Coordinate Soft Reserved handling with CXL and HMEM |
7 |
smita.koralahallichannabasappa@amd.com |
finished
in 2h11m0s
|
| 2026-02-10 06:44 UTC |
dax/hmem, cxl: Coordinate Soft Reserved handling with CXL and HMEM |
6 |
smita.koralahallichannabasappa@amd.com |
skipped
|
| 2026-01-22 04:55 UTC |
dax/hmem, cxl: Coordinate Soft Reserved handling with CXL and HMEM |
5 |
smita.koralahallichannabasappa@amd.com |
skipped
|
| 2025-11-12 19:29 UTC |
Specific Purpose Memory NUMA Nodes |
2 |
gourry@gourry.net |
finished
in 3h47m0s
|
| 2025-11-07 22:49 UTC |
Protected Memory NUMA Nodes |
1 |
gourry@gourry.net |
skipped
|
| 2025-07-22 07:34 UTC |
treewide: Fix typo "notifer" |
3 |
wangyuli@uniontech.com |
finished
in 1h36m0s
|
| 2025-07-15 13:44 UTC |
treewide: Fix typo "notifer" |
2 |
wangyuli@uniontech.com |
finished
in 3h39m0s
|
| 2025-07-15 07:12 UTC |
treewide: Fix typo "notifer" |
1 |
wangyuli@uniontech.com |
finished
in 3h40m0s
|