| Published | Title | Version | Author | Status |
|---|---|---|---|---|
| 2025-10-13 21:55 UTC | riscv control-flow integrity for usermode | 20 | debug@rivosinc.com | finished in 3h58m0s |
| 2025-09-23 04:18 UTC | Legacy hardware/cache events as json | 5 | irogers@google.com | finished in 38m0s |
| 2025-09-14 18:11 UTC | Legacy hardware/cache events as json | 4 | irogers@google.com | finished in 38m0s |
| 2025-09-09 07:03 UTC | Add SBI v3.0 PMU enhancements | 6 | atishp@rivosinc.com | finished in 48m0s |
| 2025-08-29 14:41 UTC | Add SBI v3.0 PMU enhancements | 5 | atishp@rivosinc.com | finished in 48m0s |
| 2025-08-28 20:59 UTC | Legacy hardware/cache events as json | 3 | irogers@google.com | finished in 38m0s |
| 2025-08-28 16:32 UTC | Legacy hardware/cache events as json | 2 | irogers@google.com | finished in 47m0s |
| 2025-08-28 06:42 UTC | Legacy hardware/cache events as json | 1 | irogers@google.com | finished in 40m0s |
| 2025-08-22 17:47 UTC | riscv: add initial support for hardware breakpoints | 1 | jesse@rivosinc.com | skipped |
| 2025-08-05 19:39 UTC | riscv: add initial support for hardware breakpoints | 1 | jesse@rivosinc.com | skipped |