| 2025-12-13 15:08 UTC |
riscv: sbi: Add support to test PMU extension |
1 |
jamestiotio@gmail.com |
skipped
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| 2025-12-11 17:20 UTC |
riscv control-flow integrity for usermode |
26 |
devnull@kernel.org |
skipped
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| 2025-12-05 18:41 UTC |
riscv control-flow integrity for usermode |
25 |
devnull@kernel.org |
finished
in 4h7m0s
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| 2025-12-04 20:03 UTC |
riscv control-flow integrity for usermode |
24 |
debug@rivosinc.com |
finished
in 3h51m0s
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| 2025-11-13 00:42 UTC |
riscv control-flow integrity for usermode |
23 |
devnull@kernel.org |
finished
in 54m0s
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| 2025-10-23 16:51 UTC |
riscv control-flow integrity for usermode |
22 |
devnull@kernel.org |
finished
in 3h43m0s
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| 2025-10-15 18:13 UTC |
riscv control-flow integrity for usermode |
21 |
debug@rivosinc.com |
finished
in 3h40m0s
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| 2025-10-13 21:55 UTC |
riscv control-flow integrity for usermode |
20 |
debug@rivosinc.com |
finished
in 3h58m0s
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| 2025-09-23 04:18 UTC |
Legacy hardware/cache events as json |
5 |
irogers@google.com |
finished
in 38m0s
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| 2025-09-14 18:11 UTC |
Legacy hardware/cache events as json |
4 |
irogers@google.com |
finished
in 38m0s
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| 2025-09-09 07:03 UTC |
Add SBI v3.0 PMU enhancements |
6 |
atishp@rivosinc.com |
finished
in 48m0s
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| 2025-08-29 14:41 UTC |
Add SBI v3.0 PMU enhancements |
5 |
atishp@rivosinc.com |
finished
in 48m0s
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| 2025-08-28 20:59 UTC |
Legacy hardware/cache events as json |
3 |
irogers@google.com |
finished
in 38m0s
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| 2025-08-28 16:32 UTC |
Legacy hardware/cache events as json |
2 |
irogers@google.com |
finished
in 47m0s
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| 2025-08-28 06:42 UTC |
Legacy hardware/cache events as json |
1 |
irogers@google.com |
finished
in 40m0s
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| 2025-08-22 17:47 UTC |
riscv: add initial support for hardware breakpoints |
1 |
jesse@rivosinc.com |
skipped
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| 2025-08-05 19:39 UTC |
riscv: add initial support for hardware breakpoints |
1 |
jesse@rivosinc.com |
skipped
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