| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/08/03 19:03 | flow | patch-triage |
0mArgs:null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch refactors MediaTek SoC-specific clock drivers to use a common probe/remove infrastructure and changes several Kconfig options to tristate. These platform drivers bind to specific MediaTek compatible strings (e.g., \"mediatek,mt2701-topckgen\") which are not present in the device trees of generic virtualized environments like QEMU or GCE. Therefore, the modified code paths are impossible to reach and test during standard fuzzing.",
"WorthFuzzing": false
} |
| 1/1 | 2026/08/03 19:03 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit bcae9805b06d74233d95c1426614080fd3776de3\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Mon Aug 3 19:03:37 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig\nindex 2c09fd729bab0..ac992cfc6c3e8 100644\n--- a/drivers/clk/mediatek/Kconfig\n+++ b/drivers/clk/mediatek/Kconfig\n@@ -19,7 +19,7 @@ config COMMON_CLK_MEDIATEK_FHCTL\n \t spread spectrum clocking features.\n \n config COMMON_CLK_MT2701\n-\tbool \"Clock driver for MediaTek MT2701\"\n+\ttristate \"Clock driver for MediaTek MT2701\"\n \tdepends on (ARCH_MEDIATEK \u0026\u0026 ARM) || COMPILE_TEST\n \tselect COMMON_CLK_MEDIATEK\n \tdefault ARCH_MEDIATEK \u0026\u0026 ARM\n@@ -27,49 +27,49 @@ config COMMON_CLK_MT2701\n \t This driver supports MediaTek MT2701 basic clocks.\n \n config COMMON_CLK_MT2701_MMSYS\n-\tbool \"Clock driver for MediaTek MT2701 mmsys\"\n+\ttristate \"Clock driver for MediaTek MT2701 mmsys\"\n \tdepends on COMMON_CLK_MT2701\n \thelp\n \t This driver supports MediaTek MT2701 mmsys clocks.\n \n config COMMON_CLK_MT2701_IMGSYS\n-\tbool \"Clock driver for MediaTek MT2701 imgsys\"\n+\ttristate \"Clock driver for MediaTek MT2701 imgsys\"\n \tdepends on COMMON_CLK_MT2701\n \thelp\n \t This driver supports MediaTek MT2701 imgsys clocks.\n \n config COMMON_CLK_MT2701_VDECSYS\n-\tbool \"Clock driver for MediaTek MT2701 vdecsys\"\n+\ttristate \"Clock driver for MediaTek MT2701 vdecsys\"\n \tdepends on COMMON_CLK_MT2701\n \thelp\n \t This driver supports MediaTek MT2701 vdecsys clocks.\n \n config COMMON_CLK_MT2701_HIFSYS\n-\tbool \"Clock driver for MediaTek MT2701 hifsys\"\n+\ttristate \"Clock driver for MediaTek MT2701 hifsys\"\n \tdepends on COMMON_CLK_MT2701\n \thelp\n \t This driver supports MediaTek MT2701 hifsys clocks.\n \n config COMMON_CLK_MT2701_ETHSYS\n-\tbool \"Clock driver for MediaTek MT2701 ethsys\"\n+\ttristate \"Clock driver for MediaTek MT2701 ethsys\"\n \tdepends on COMMON_CLK_MT2701\n \thelp\n \t This driver supports MediaTek MT2701 ethsys clocks.\n \n config COMMON_CLK_MT2701_BDPSYS\n-\tbool \"Clock driver for MediaTek MT2701 bdpsys\"\n+\ttristate \"Clock driver for MediaTek MT2701 bdpsys\"\n \tdepends on COMMON_CLK_MT2701\n \thelp\n \t This driver supports MediaTek MT2701 bdpsys clocks.\n \n config COMMON_CLK_MT2701_AUDSYS\n-\tbool \"Clock driver for Mediatek MT2701 audsys\"\n+\ttristate \"Clock driver for Mediatek MT2701 audsys\"\n \tdepends on COMMON_CLK_MT2701\n \thelp\n \t This driver supports Mediatek MT2701 audsys clocks.\n \n config COMMON_CLK_MT2701_G3DSYS\n-\tbool \"Clock driver for MediaTek MT2701 g3dsys\"\n+\ttristate \"Clock driver for MediaTek MT2701 g3dsys\"\n \tdepends on COMMON_CLK_MT2701\n \thelp\n \t This driver supports MediaTek MT2701 g3dsys clocks.\n@@ -342,7 +342,7 @@ config COMMON_CLK_MT6795_VENCSYS\n \t This driver supports MediaTek MT6795 vencsys clocks.\n \n config COMMON_CLK_MT6797\n-\tbool \"Clock driver for MediaTek MT6797\"\n+\ttristate \"Clock driver for MediaTek MT6797\"\n \tdepends on (ARCH_MEDIATEK \u0026\u0026 ARM64) || COMPILE_TEST\n \tselect COMMON_CLK_MEDIATEK\n \tdefault ARCH_MEDIATEK \u0026\u0026 ARM64\n@@ -427,7 +427,7 @@ config COMMON_CLK_MT7629_HIFSYS\n \t to PCI-E and USB.\n \n config COMMON_CLK_MT7981\n-\tbool \"Clock driver for MediaTek MT7981\"\n+\ttristate \"Clock driver for MediaTek MT7981\"\n \tdepends on ARCH_MEDIATEK || COMPILE_TEST\n \tselect COMMON_CLK_MEDIATEK\n \tdefault ARCH_MEDIATEK\n@@ -909,13 +909,13 @@ config COMMON_CLK_MT8192_VENCSYS\n \t This driver supports MediaTek MT8192 vencsys clocks.\n \n config COMMON_CLK_MT8195\n- bool \"Clock driver for MediaTek MT8195\"\n- depends on ARM64 || COMPILE_TEST\n- select COMMON_CLK_MEDIATEK\n+\ttristate \"Clock driver for MediaTek MT8195\"\n+\tdepends on ARM64 || COMPILE_TEST\n+\tselect COMMON_CLK_MEDIATEK\n \tselect COMMON_CLK_MEDIATEK_FHCTL\n- default ARCH_MEDIATEK\n- help\n- This driver supports MediaTek MT8195 clocks.\n+\tdefault ARCH_MEDIATEK\n+\thelp\n+\t This driver supports MediaTek MT8195 clocks.\n \n config COMMON_CLK_MT8195_APUSYS\n \ttristate \"Clock driver for MediaTek MT8195 apusys\"\ndiff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c\nindex e103121cf58e7..533d35614661a 100644\n--- a/drivers/clk/mediatek/clk-mt2701-aud.c\n+++ b/drivers/clk/mediatek/clk-mt2701-aud.c\n@@ -128,6 +128,7 @@ static const struct mtk_gate audio_clks[] = {\n static const struct mtk_clk_desc audio_desc = {\n \t.clks = audio_clks,\n \t.num_clks = ARRAY_SIZE(audio_clks),\n+\t.populate_children = true,\n };\n \n static const struct of_device_id of_match_clk_mt2701_aud[] = {\n@@ -136,39 +137,9 @@ static const struct of_device_id of_match_clk_mt2701_aud[] = {\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_aud);\n \n-static int clk_mt2701_aud_probe(struct platform_device *pdev)\n-{\n-\tint r;\n-\n-\tr = mtk_clk_simple_probe(pdev);\n-\tif (r) {\n-\t\tdev_err(\u0026pdev-\u003edev,\n-\t\t\t\"could not register clock provider: %s: %d\\n\",\n-\t\t\tpdev-\u003ename, r);\n-\n-\t\treturn r;\n-\t}\n-\n-\tr = devm_of_platform_populate(\u0026pdev-\u003edev);\n-\tif (r)\n-\t\tgoto err_plat_populate;\n-\n-\treturn 0;\n-\n-err_plat_populate:\n-\tmtk_clk_simple_remove(pdev);\n-\treturn r;\n-}\n-\n-static void clk_mt2701_aud_remove(struct platform_device *pdev)\n-{\n-\tof_platform_depopulate(\u0026pdev-\u003edev);\n-\tmtk_clk_simple_remove(pdev);\n-}\n-\n static struct platform_driver clk_mt2701_aud_drv = {\n-\t.probe = clk_mt2701_aud_probe,\n-\t.remove = clk_mt2701_aud_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt2701-aud\",\n \t\t.of_match_table = of_match_clk_mt2701_aud,\ndiff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c\nindex 710c4f2f9f304..5ea0c4acaf1be 100644\n--- a/drivers/clk/mediatek/clk-mt2701.c\n+++ b/drivers/clk/mediatek/clk-mt2701.c\n@@ -6,6 +6,7 @@\n \n #include \u003clinux/clk-provider.h\u003e\n #include \u003clinux/platform_device.h\u003e\n+#include \u003clinux/module.h\u003e\n \n #include \"clk-cpumux.h\"\n #include \"clk-gate.h\"\n@@ -655,38 +656,19 @@ static const struct mtk_gate top_clks[] = {\n \t\t28),\n };\n \n-static int mtk_topckgen_init(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tvoid __iomem *base;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_TOP_NR);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),\n-\t\t\t\t\t\t\t\tclk_data);\n-\n-\tmtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),\n-\t\t\t\t\t\t\t\tclk_data);\n-\n-\tmtk_clk_register_composites(\u0026pdev-\u003edev, top_muxes,\n-\t\t\t\t ARRAY_SIZE(top_muxes), base,\n-\t\t\t\t \u0026mt2701_clk_lock, clk_data);\n-\n-\tmtk_clk_register_dividers(\u0026pdev-\u003edev, top_adj_divs, ARRAY_SIZE(top_adj_divs),\n-\t\t\t\tbase, \u0026mt2701_clk_lock, clk_data);\n-\n-\tmtk_clk_register_gates(\u0026pdev-\u003edev, node, top_clks,\n-\t\t\t ARRAY_SIZE(top_clks), clk_data);\n-\n-\treturn of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-}\n+static const struct mtk_clk_desc topck_desc = {\n+\t.clks = top_clks,\n+\t.num_clks = ARRAY_SIZE(top_clks),\n+\t.fixed_clks = top_fixed_clks,\n+\t.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),\n+\t.factor_clks = top_fixed_divs,\n+\t.num_factor_clks = ARRAY_SIZE(top_fixed_divs),\n+\t.composite_clks = top_muxes,\n+\t.num_composite_clks = ARRAY_SIZE(top_muxes),\n+\t.divider_clks = top_adj_divs,\n+\t.num_divider_clks = ARRAY_SIZE(top_adj_divs),\n+\t.clk_lock = \u0026mt2701_clk_lock,\n+};\n \n static const struct mtk_gate_regs infra_cg_regs = {\n \t.set_ofs = 0x0040,\n@@ -725,81 +707,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {\n static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };\n static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };\n \n-static const struct mtk_clk_rst_desc clk_rst_desc[] = {\n-\t/* infrasys */\n-\t{\n-\t\t.version = MTK_RST_SIMPLE,\n-\t\t.rst_bank_ofs = infrasys_rst_ofs,\n-\t\t.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),\n-\t},\n-\t/* pericfg */\n-\t{\n-\t\t.version = MTK_RST_SIMPLE,\n-\t\t.rst_bank_ofs = pericfg_rst_ofs,\n-\t\t.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),\n-\t},\n+static const struct mtk_clk_rst_desc infra_rst_desc = {\n+\t.version = MTK_RST_SIMPLE,\n+\t.rst_bank_ofs = infrasys_rst_ofs,\n+\t.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),\n };\n \n-static struct clk_hw_onecell_data *infra_clk_data;\n-\n-static void __init mtk_infrasys_init_early(struct device_node *node)\n-{\n-\tint r, i;\n-\n-\tif (!infra_clk_data) {\n-\t\tinfra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);\n-\t\tif (!infra_clk_data)\n-\t\t\treturn;\n-\n-\t\tfor (i = 0; i \u003c CLK_INFRA_NR; i++)\n-\t\t\tinfra_clk_data-\u003ehws[i] = ERR_PTR(-EPROBE_DEFER);\n-\t}\n-\n-\tmtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),\n-\t\t\t\t\t\tinfra_clk_data);\n-\n-\tmtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),\n-\t\t\t\t infra_clk_data);\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,\n-\t\t\t\t infra_clk_data);\n-\tif (r)\n-\t\tpr_err(\"%s(): could not register clock provider: %d\\n\",\n-\t\t\t__func__, r);\n-}\n-CLK_OF_DECLARE_DRIVER(mtk_infra, \"mediatek,mt2701-infracfg\",\n-\t\t\tmtk_infrasys_init_early);\n-\n-static int mtk_infrasys_init(struct platform_device *pdev)\n-{\n-\tint r, i;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tif (!infra_clk_data) {\n-\t\tinfra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);\n-\t\tif (!infra_clk_data)\n-\t\t\treturn -ENOMEM;\n-\t} else {\n-\t\tfor (i = 0; i \u003c CLK_INFRA_NR; i++) {\n-\t\t\tif (infra_clk_data-\u003ehws[i] == ERR_PTR(-EPROBE_DEFER))\n-\t\t\t\tinfra_clk_data-\u003ehws[i] = ERR_PTR(-ENOENT);\n-\t\t}\n-\t}\n-\n-\tmtk_clk_register_gates(\u0026pdev-\u003edev, node, infra_clks,\n-\t\t\t ARRAY_SIZE(infra_clks), infra_clk_data);\n-\tmtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),\n-\t\t\t\t\t\tinfra_clk_data);\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,\n-\t\t\t\t infra_clk_data);\n-\tif (r)\n-\t\treturn r;\n-\n-\tmtk_register_reset_controller_with_dev(\u0026pdev-\u003edev, \u0026clk_rst_desc[0]);\n-\n-\treturn 0;\n-}\n+static const struct mtk_clk_desc infracfg_desc = {\n+\t.clks = infra_clks,\n+\t.num_clks = ARRAY_SIZE(infra_clks),\n+\t.factor_clks = infra_fixed_divs,\n+\t.num_factor_clks = ARRAY_SIZE(infra_fixed_divs),\n+\t.cpumuxes = cpu_muxes,\n+\t.num_cpumuxes = ARRAY_SIZE(cpu_muxes),\n+\t.rst_desc = \u0026infra_rst_desc,\n+};\n \n static const struct mtk_gate_regs peri0_cg_regs = {\n \t.set_ofs = 0x0008,\n@@ -883,36 +805,20 @@ static const struct mtk_composite peri_muxs[] = {\n \t\t0x40c, 3, 1),\n };\n \n-static int mtk_pericfg_init(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tvoid __iomem *base;\n-\tint r;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_PERI_NR);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_gates(\u0026pdev-\u003edev, node, peri_clks,\n-\t\t\t ARRAY_SIZE(peri_clks), clk_data);\n-\n-\tmtk_clk_register_composites(\u0026pdev-\u003edev, peri_muxs,\n-\t\t\t\t ARRAY_SIZE(peri_muxs), base,\n-\t\t\t\t \u0026mt2701_clk_lock, clk_data);\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\treturn r;\n-\n-\tmtk_register_reset_controller_with_dev(\u0026pdev-\u003edev, \u0026clk_rst_desc[1]);\n+static const struct mtk_clk_rst_desc peri_rst_desc = {\n+\t.version = MTK_RST_SIMPLE,\n+\t.rst_bank_ofs = pericfg_rst_ofs,\n+\t.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),\n+};\n \n-\treturn 0;\n-}\n+static const struct mtk_clk_desc pericfg_desc = {\n+\t.clks = peri_clks,\n+\t.num_clks = ARRAY_SIZE(peri_clks),\n+\t.composite_clks = peri_muxs,\n+\t.num_composite_clks = ARRAY_SIZE(peri_muxs),\n+\t.rst_desc = \u0026peri_rst_desc,\n+\t.clk_lock = \u0026mt2701_clk_lock,\n+};\n \n #define MT8590_PLL_FMAX\t\t(2000 * MHZ)\n #define CON0_MT8590_RST_BAR\tBIT(27)\n@@ -968,74 +874,41 @@ static const struct mtk_fixed_factor apmixed_fixed_divs[] = {\n \tFACTOR(CLK_APMIXED_HDMI_REF, \"hdmi_ref\", \"tvdpll\", 1, 1),\n };\n \n-static int mtk_apmixedsys_init(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_plls(\u0026pdev-\u003edev, apmixed_plls, ARRAY_SIZE(apmixed_plls),\n-\t\t\t\t\t\t\t\tclk_data);\n-\tmtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),\n-\t\t\t\t\t\t\t\tclk_data);\n-\n-\treturn of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-}\n+static const struct mtk_clk_desc apmixedsys_desc = {\n+\t.plls = apmixed_plls,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n+\t.factor_clks = apmixed_fixed_divs,\n+\t.num_factor_clks = ARRAY_SIZE(apmixed_fixed_divs),\n+};\n \n static const struct of_device_id of_match_clk_mt2701[] = {\n \t{\n \t\t.compatible = \"mediatek,mt2701-topckgen\",\n-\t\t.data = mtk_topckgen_init,\n+\t\t.data = \u0026topck_desc,\n \t}, {\n \t\t.compatible = \"mediatek,mt2701-infracfg\",\n-\t\t.data = mtk_infrasys_init,\n+\t\t.data = \u0026infracfg_desc,\n \t}, {\n \t\t.compatible = \"mediatek,mt2701-pericfg\",\n-\t\t.data = mtk_pericfg_init,\n+\t\t.data = \u0026pericfg_desc,\n \t}, {\n \t\t.compatible = \"mediatek,mt2701-apmixedsys\",\n-\t\t.data = mtk_apmixedsys_init,\n+\t\t.data = \u0026apmixedsys_desc,\n \t}, {\n \t\t/* sentinel */\n \t}\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt2701);\n \n-static int clk_mt2701_probe(struct platform_device *pdev)\n-{\n-\tint (*clk_init)(struct platform_device *);\n-\tint r;\n-\n-\tclk_init = of_device_get_match_data(\u0026pdev-\u003edev);\n-\tif (!clk_init)\n-\t\treturn -EINVAL;\n-\n-\tr = clk_init(pdev);\n-\tif (r)\n-\t\tdev_err(\u0026pdev-\u003edev,\n-\t\t\t\"could not register clock provider: %s: %d\\n\",\n-\t\t\tpdev-\u003ename, r);\n-\n-\treturn r;\n-}\n-\n static struct platform_driver clk_mt2701_drv = {\n-\t.probe = clk_mt2701_probe,\n \t.driver = {\n \t\t.name = \"clk-mt2701\",\n \t\t.of_match_table = of_match_clk_mt2701,\n \t},\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n };\n-\n-static int __init clk_mt2701_init(void)\n-{\n-\treturn platform_driver_register(\u0026clk_mt2701_drv);\n-}\n-\n-arch_initcall(clk_mt2701_init);\n+module_platform_driver(clk_mt2701_drv);\n \n MODULE_DESCRIPTION(\"MediaTek MT2701 main clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c\nindex 54b18e9f83f8f..1e06f87e71d08 100644\n--- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c\n@@ -109,54 +109,20 @@ static const struct mtk_pll_data plls[] = {\n \t 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),\n };\n \n-static int clk_mt2712_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tint r;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tr = mtk_clk_register_plls(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls), clk_data);\n-\tif (r)\n-\t\tgoto free_clk_data;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r) {\n-\t\tdev_err(\u0026pdev-\u003edev, \"Cannot register clock provider: %d\\n\", r);\n-\t\tgoto unregister_plls;\n-\t}\n-\n-\treturn 0;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-free_clk_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n-static void clk_mt2712_apmixed_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+};\n \n static const struct of_device_id of_match_clk_mt2712_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt2712-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt2712-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_apmixed);\n \n static struct platform_driver clk_mt2712_apmixed_drv = {\n-\t.probe = clk_mt2712_apmixed_probe,\n-\t.remove = clk_mt2712_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt2712-apmixed\",\n \t\t.of_match_table = of_match_clk_mt2712_apmixed,\ndiff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c\nindex 9e30c089a2092..94cb0bee8bb40 100644\n--- a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c\n@@ -77,54 +77,20 @@ static const struct mtk_pll_data apmixedsys_plls[] = {\n \tPLL(CLK_APMIXED_APLL2, \"apll2\", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0, APLL2_CON0, 4, APLL2_CON2, AP_PLL_CON_5, 1, APLL2_CON1, 31, 0)\n };\n \n-static int clk_mt6735_apmixed_probe(struct platform_device *pdev)\n-{\n-\tvoid __iomem *base;\n-\tstruct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tint ret;\n-\n-\tbase = devm_ioremap_resource(\u0026pdev-\u003edev, res);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_devm_alloc_clk_data(\u0026pdev-\u003edev, ARRAY_SIZE(apmixedsys_plls));\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\tplatform_set_drvdata(pdev, clk_data);\n-\n-\tret = mtk_clk_register_plls(\u0026pdev-\u003edev, apmixedsys_plls,\n-\t\t\t\t ARRAY_SIZE(apmixedsys_plls), clk_data);\n-\tif (ret) {\n-\t\tdev_err(\u0026pdev-\u003edev, \"Failed to register PLLs: %d\\n\", ret);\n-\t\treturn ret;\n-\t}\n-\n-\tret = devm_of_clk_add_hw_provider(\u0026pdev-\u003edev, of_clk_hw_onecell_get,\n-\t\t\t\t\t clk_data);\n-\tif (ret)\n-\t\tdev_err(\u0026pdev-\u003edev,\n-\t\t\t\"Failed to register clock provider: %d\\n\", ret);\n-\n-\treturn ret;\n-}\n-\n-static void clk_mt6735_apmixed_remove(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tmtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data);\n-}\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = apmixedsys_plls,\n+\t.num_plls = ARRAY_SIZE(apmixedsys_plls),\n+};\n \n static const struct of_device_id of_match_mt6735_apmixedsys[] = {\n-\t{ .compatible = \"mediatek,mt6735-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt6735-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_mt6735_apmixedsys);\n \n static struct platform_driver clk_mt6735_apmixedsys = {\n-\t.probe = clk_mt6735_apmixed_probe,\n-\t.remove = clk_mt6735_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt6735-apmixedsys\",\n \t\t.of_match_table = of_match_mt6735_apmixedsys,\ndiff --git a/drivers/clk/mediatek/clk-mt6735-imgsys.c b/drivers/clk/mediatek/clk-mt6735-imgsys.c\nindex c564f8f724324..813241d526cf4 100644\n--- a/drivers/clk/mediatek/clk-mt6735-imgsys.c\n+++ b/drivers/clk/mediatek/clk-mt6735-imgsys.c\n@@ -41,6 +41,7 @@ static const struct of_device_id of_match_mt6735_imgsys[] = {\n \t{ .compatible = \"mediatek,mt6735-imgsys\", .data = \u0026imgsys_clks },\n \t{ /* sentinel */ }\n };\n+MODULE_DEVICE_TABLE(of, of_match_mt6735_imgsys);\n \n static struct platform_driver clk_mt6735_imgsys = {\n \t.probe = mtk_clk_simple_probe,\ndiff --git a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c\nindex 1f5aedddf209d..8a18ee244a4de 100644\n--- a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c\n+++ b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c\n@@ -45,6 +45,7 @@ static const struct of_device_id of_match_mt6735_mfgcfg[] = {\n \t{ .compatible = \"mediatek,mt6735-mfgcfg\", .data = \u0026mfgcfg_clks },\n \t{ /* sentinel */ }\n };\n+MODULE_DEVICE_TABLE(of, of_match_mt6735_mfgcfg);\n \n static struct platform_driver clk_mt6735_mfgcfg = {\n \t.probe = mtk_clk_simple_probe,\ndiff --git a/drivers/clk/mediatek/clk-mt6735-vdecsys.c b/drivers/clk/mediatek/clk-mt6735-vdecsys.c\nindex 8817085fc1db4..d53ebf92e878d 100644\n--- a/drivers/clk/mediatek/clk-mt6735-vdecsys.c\n+++ b/drivers/clk/mediatek/clk-mt6735-vdecsys.c\n@@ -63,6 +63,7 @@ static const struct of_device_id of_match_mt6735_vdecsys[] = {\n \t{ .compatible = \"mediatek,mt6735-vdecsys\", .data = \u0026vdecsys_clks },\n \t{ /* sentinel */ }\n };\n+MODULE_DEVICE_TABLE(of, of_match_mt6735_vdecsys);\n \n static struct platform_driver clk_mt6735_vdecsys = {\n \t.probe = mtk_clk_simple_probe,\ndiff --git a/drivers/clk/mediatek/clk-mt6735-vencsys.c b/drivers/clk/mediatek/clk-mt6735-vencsys.c\nindex 8dec7f98492ac..64ba9da9fd427 100644\n--- a/drivers/clk/mediatek/clk-mt6735-vencsys.c\n+++ b/drivers/clk/mediatek/clk-mt6735-vencsys.c\n@@ -37,6 +37,7 @@ static const struct of_device_id of_match_mt6735_vencsys[] = {\n \t{ .compatible = \"mediatek,mt6735-vencsys\", .data = \u0026vencsys_clks },\n \t{ /* sentinel */ }\n };\n+MODULE_DEVICE_TABLE(of, of_match_mt6735_vencsys);\n \n static struct platform_driver clk_mt6735_vencsys = {\n \t.probe = mtk_clk_simple_probe,\ndiff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c\nindex 4b9dcb910b03f..a806789ae27c1 100644\n--- a/drivers/clk/mediatek/clk-mt6779.c\n+++ b/drivers/clk/mediatek/clk-mt6779.c\n@@ -808,7 +808,7 @@ static const char * const i2s5_m_ck_parents[] = {\n \t\"aud_2_sel\"\n };\n \n-static const struct mtk_composite top_aud_muxes[] = {\n+static const struct mtk_composite top_aud_muxes_divs[] = {\n \tMUX(CLK_TOP_I2S0_M_SEL, \"i2s0_m_ck_sel\", i2s0_m_ck_parents,\n \t 0x320, 8, 1),\n \tMUX(CLK_TOP_I2S1_M_SEL, \"i2s1_m_ck_sel\", i2s1_m_ck_parents,\n@@ -821,9 +821,7 @@ static const struct mtk_composite top_aud_muxes[] = {\n \t 0x320, 12, 1),\n \tMUX(CLK_TOP_I2S5_M_SEL, \"i2s5_m_ck_sel\", i2s5_m_ck_parents,\n \t 0x328, 20, 1),\n-};\n \n-static struct mtk_composite top_aud_divs[] = {\n \tDIV_GATE(CLK_TOP_APLL12_DIV0, \"apll12_div0\", \"i2s0_m_ck_sel\",\n \t\t 0x320, 2, 0x324, 8, 0),\n \tDIV_GATE(CLK_TOP_APLL12_DIV1, \"apll12_div1\", \"i2s1_m_ck_sel\",\n@@ -1211,125 +1209,47 @@ static const struct mtk_pll_data plls[] = {\n \t 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),\n };\n \n-static int clk_mt6779_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_plls(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls), clk_data);\n-\n-\tmtk_clk_register_gates(\u0026pdev-\u003edev, node, apmixed_clks,\n-\t\t\t ARRAY_SIZE(apmixed_clks), clk_data);\n-\n-\treturn of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-}\n-\n-static int clk_mt6779_top_probe(struct platform_device *pdev)\n-{\n-\tvoid __iomem *base;\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),\n-\t\t\t\t clk_data);\n-\n-\tmtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);\n-\n-\tmtk_clk_register_muxes(\u0026pdev-\u003edev, top_muxes,\n-\t\t\t ARRAY_SIZE(top_muxes), node,\n-\t\t\t \u0026mt6779_clk_lock, clk_data);\n-\n-\tmtk_clk_register_composites(\u0026pdev-\u003edev, top_aud_muxes,\n-\t\t\t\t ARRAY_SIZE(top_aud_muxes), base,\n-\t\t\t\t \u0026mt6779_clk_lock, clk_data);\n-\n-\tmtk_clk_register_composites(\u0026pdev-\u003edev, top_aud_divs,\n-\t\t\t\t ARRAY_SIZE(top_aud_divs), base,\n-\t\t\t\t \u0026mt6779_clk_lock, clk_data);\n-\n-\treturn of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-}\n-\n-static const struct of_device_id of_match_clk_mt6779[] = {\n-\t{\n-\t\t.compatible = \"mediatek,mt6779-apmixed\",\n-\t\t.data = clk_mt6779_apmixed_probe,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt6779-topckgen\",\n-\t\t.data = clk_mt6779_top_probe,\n-\t}, {\n-\t\t/* sentinel */\n-\t}\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.clks = apmixed_clks,\n+\t.num_clks = ARRAY_SIZE(apmixed_clks),\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n };\n \n-static int clk_mt6779_probe(struct platform_device *pdev)\n-{\n-\tint (*clk_probe)(struct platform_device *pdev);\n-\tint r;\n-\n-\tclk_probe = of_device_get_match_data(\u0026pdev-\u003edev);\n-\tif (!clk_probe)\n-\t\treturn -EINVAL;\n-\n-\tr = clk_probe(pdev);\n-\tif (r)\n-\t\tdev_err(\u0026pdev-\u003edev,\n-\t\t\t\"could not register clock provider: %s: %d\\n\",\n-\t\t\tpdev-\u003ename, r);\n-\n-\treturn r;\n-}\n+static const struct mtk_clk_desc topck_desc = {\n+\t.fixed_clks = top_fixed_clks,\n+\t.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),\n+\t.factor_clks = top_divs,\n+\t.num_factor_clks = ARRAY_SIZE(top_divs),\n+\t.mux_clks = top_muxes,\n+\t.num_mux_clks = ARRAY_SIZE(top_muxes),\n+\t.composite_clks = top_aud_muxes_divs,\n+\t.num_composite_clks = ARRAY_SIZE(top_aud_muxes_divs),\n+\t.clk_lock = \u0026mt6779_clk_lock,\n+};\n \n static const struct mtk_clk_desc infra_desc = {\n \t.clks = infra_clks,\n \t.num_clks = ARRAY_SIZE(infra_clks),\n };\n \n-static const struct of_device_id of_match_clk_mt6779_infra[] = {\n+static const struct of_device_id of_match_clk_mt6779[] = {\n+\t{ .compatible = \"mediatek,mt6779-apmixed\", .data = \u0026apmixed_desc },\n+\t{ .compatible = \"mediatek,mt6779-topckgen\", .data = \u0026topck_desc },\n \t{ .compatible = \"mediatek,mt6779-infracfg_ao\", .data = \u0026infra_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt6779);\n \n-static struct platform_driver clk_mt6779_infra_drv = {\n+static struct platform_driver clk_mt6779_drv = {\n \t.probe = mtk_clk_simple_probe,\n \t.remove = mtk_clk_simple_remove,\n-\t.driver = {\n-\t\t.name = \"clk-mt6779-infra\",\n-\t\t.of_match_table = of_match_clk_mt6779_infra,\n-\t},\n-};\n-\n-static struct platform_driver clk_mt6779_drv = {\n-\t.probe = clk_mt6779_probe,\n \t.driver = {\n \t\t.name = \"clk-mt6779\",\n \t\t.of_match_table = of_match_clk_mt6779,\n \t},\n };\n-\n-static int __init clk_mt6779_init(void)\n-{\n-\tint ret = platform_driver_register(\u0026clk_mt6779_drv);\n-\n-\tif (ret)\n-\t\treturn ret;\n-\treturn platform_driver_register(\u0026clk_mt6779_infra_drv);\n-}\n-\n-arch_initcall(clk_mt6779_init);\n+module_platform_driver(clk_mt6779_drv);\n \n MODULE_DESCRIPTION(\"MediaTek MT6779 main clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c\nindex 123d5d7fea855..239a3f5e17604 100644\n--- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c\n@@ -175,6 +175,8 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)\n \tdev_dbg(dev, \"Performing initial setup for MD1\\n\");\n \tclk_mt6795_apmixed_setup_md1(base);\n \n+\tplatform_set_drvdata(pdev, clk_data);\n+\n \treturn 0;\n \n unregister_ref2usb:\ndiff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/mediatek/clk-mt6795-infracfg.c\nindex e4559569f5b02..6aefc577ece5c 100644\n--- a/drivers/clk/mediatek/clk-mt6795-infracfg.c\n+++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c\n@@ -8,7 +8,6 @@\n #include \u003cdt-bindings/reset/mediatek,mt6795-resets.h\u003e\n #include \u003clinux/module.h\u003e\n #include \u003clinux/platform_device.h\u003e\n-#include \"clk-cpumux.h\"\n #include \"clk-gate.h\"\n #include \"clk-mtk.h\"\n #include \"reset.h\"\n@@ -77,74 +76,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {\n \t.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),\n };\n \n+static const struct mtk_clk_desc infra_desc = {\n+\t.clks = infra_gates,\n+\t.num_clks = ARRAY_SIZE(infra_gates),\n+\t.cpumuxes = cpu_muxes,\n+\t.num_cpumuxes = ARRAY_SIZE(cpu_muxes),\n+\t.rst_desc = \u0026clk_rst_desc,\n+};\n+\n static const struct of_device_id of_match_clk_mt6795_infracfg[] = {\n-\t{ .compatible = \"mediatek,mt6795-infracfg\" },\n+\t{ .compatible = \"mediatek,mt6795-infracfg\", .data = \u0026infra_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_infracfg);\n \n-static int clk_mt6795_infracfg_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tvoid __iomem *base;\n-\tint ret;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tret = mtk_register_reset_controller_with_dev(\u0026pdev-\u003edev, \u0026clk_rst_desc);\n-\tif (ret)\n-\t\tgoto free_clk_data;\n-\n-\tret = mtk_clk_register_gates(\u0026pdev-\u003edev, node, infra_gates,\n-\t\t\t\t ARRAY_SIZE(infra_gates), clk_data);\n-\tif (ret)\n-\t\tgoto free_clk_data;\n-\n-\tret = mtk_clk_register_cpumuxes(\u0026pdev-\u003edev, node, cpu_muxes,\n-\t\t\t\t\tARRAY_SIZE(cpu_muxes), clk_data);\n-\tif (ret)\n-\t\tgoto unregister_gates;\n-\n-\tret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_cpumuxes;\n-\n-\treturn 0;\n-\n-unregister_cpumuxes:\n-\tmtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);\n-unregister_gates:\n-\tmtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);\n-free_clk_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn ret;\n-}\n-\n-static void clk_mt6795_infracfg_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);\n-\tmtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt6795_infracfg_drv = {\n \t.driver = {\n \t\t.name = \"clk-mt6795-infracfg\",\n \t\t.of_match_table = of_match_clk_mt6795_infracfg,\n \t},\n-\t.probe = clk_mt6795_infracfg_probe,\n-\t.remove = clk_mt6795_infracfg_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n };\n module_platform_driver(clk_mt6795_infracfg_drv);\n \ndiff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediatek/clk-mt6795-pericfg.c\nindex d48240eb2a67c..53c79e830b6a1 100644\n--- a/drivers/clk/mediatek/clk-mt6795-pericfg.c\n+++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c\n@@ -85,75 +85,28 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {\n \t.rst_idx_map_nr = ARRAY_SIZE(peri_idx_map),\n };\n \n+static const struct mtk_clk_desc pericfg_desc = {\n+\t.clks = peri_gates,\n+\t.num_clks = ARRAY_SIZE(peri_gates),\n+\t.composite_clks = peri_clks,\n+\t.num_composite_clks = ARRAY_SIZE(peri_clks),\n+\t.rst_desc = \u0026clk_rst_desc,\n+\t.clk_lock = \u0026mt6795_peri_clk_lock,\n+};\n+\n static const struct of_device_id of_match_clk_mt6795_pericfg[] = {\n-\t{ .compatible = \"mediatek,mt6795-pericfg\" },\n+\t{ .compatible = \"mediatek,mt6795-pericfg\", .data = \u0026pericfg_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_pericfg);\n \n-static int clk_mt6795_pericfg_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tvoid __iomem *base;\n-\tint ret;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tret = mtk_register_reset_controller_with_dev(\u0026pdev-\u003edev, \u0026clk_rst_desc);\n-\tif (ret)\n-\t\tgoto free_clk_data;\n-\n-\tret = mtk_clk_register_gates(\u0026pdev-\u003edev, node, peri_gates,\n-\t\t\t\t ARRAY_SIZE(peri_gates), clk_data);\n-\tif (ret)\n-\t\tgoto free_clk_data;\n-\n-\tret = mtk_clk_register_composites(\u0026pdev-\u003edev, peri_clks,\n-\t\t\t\t\t ARRAY_SIZE(peri_clks), base,\n-\t\t\t\t\t \u0026mt6795_peri_clk_lock, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_gates;\n-\n-\tret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_composites;\n-\n-\treturn 0;\n-\n-unregister_composites:\n-\tmtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);\n-unregister_gates:\n-\tmtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);\n-free_clk_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn ret;\n-}\n-\n-static void clk_mt6795_pericfg_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);\n-\tmtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt6795_pericfg_drv = {\n \t.driver = {\n \t\t.name = \"clk-mt6795-pericfg\",\n \t\t.of_match_table = of_match_clk_mt6795_pericfg,\n \t},\n-\t.probe = clk_mt6795_pericfg_probe,\n-\t.remove = clk_mt6795_pericfg_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n };\n module_platform_driver(clk_mt6795_pericfg_drv);\n \ndiff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c\nindex ebf850ac57f54..1934420375e88 100644\n--- a/drivers/clk/mediatek/clk-mt6797.c\n+++ b/drivers/clk/mediatek/clk-mt6797.c\n@@ -379,29 +379,13 @@ static const struct mtk_composite top_muxes[] = {\n \t 0x0104, 1, 2),\n };\n \n-static int mtk_topckgen_init(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tvoid __iomem *base;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_TOP_NR);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),\n-\t\t\t\t clk_data);\n-\n-\tmtk_clk_register_composites(\u0026pdev-\u003edev, top_muxes,\n-\t\t\t\t ARRAY_SIZE(top_muxes), base,\n-\t\t\t\t \u0026mt6797_clk_lock, clk_data);\n-\n-\treturn of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-}\n+static const struct mtk_clk_desc topckgen_desc = {\n+\t.factor_clks = top_fixed_divs,\n+\t.num_factor_clks = ARRAY_SIZE(top_fixed_divs),\n+\t.composite_clks = top_muxes,\n+\t.num_composite_clks = ARRAY_SIZE(top_muxes),\n+\t.clk_lock = \u0026mt6797_clk_lock,\n+};\n \n static const struct mtk_gate_regs infra0_cg_regs = {\n \t.set_ofs = 0x0080,\n@@ -539,58 +523,12 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {\n \tFACTOR(CLK_INFRA_13M, \"clk13m\", \"clk26m\", 1, 2),\n };\n \n-static struct clk_hw_onecell_data *infra_clk_data;\n-\n-static void mtk_infrasys_init_early(struct device_node *node)\n-{\n-\tint r, i;\n-\n-\tif (!infra_clk_data) {\n-\t\tinfra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);\n-\t\tif (!infra_clk_data)\n-\t\t\treturn;\n-\n-\t\tfor (i = 0; i \u003c CLK_INFRA_NR; i++)\n-\t\t\tinfra_clk_data-\u003ehws[i] = ERR_PTR(-EPROBE_DEFER);\n-\t}\n-\n-\tmtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),\n-\t\t\t\t infra_clk_data);\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,\n-\t\t\t\t infra_clk_data);\n-\tif (r)\n-\t\tpr_err(\"%s(): could not register clock provider: %d\\n\",\n-\t\t __func__, r);\n-}\n-\n-CLK_OF_DECLARE_DRIVER(mtk_infra, \"mediatek,mt6797-infracfg\",\n-\t\t mtk_infrasys_init_early);\n-\n-static int mtk_infrasys_init(struct platform_device *pdev)\n-{\n-\tint i;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tif (!infra_clk_data) {\n-\t\tinfra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);\n-\t\tif (!infra_clk_data)\n-\t\t\treturn -ENOMEM;\n-\t} else {\n-\t\tfor (i = 0; i \u003c CLK_INFRA_NR; i++) {\n-\t\t\tif (infra_clk_data-\u003ehws[i] == ERR_PTR(-EPROBE_DEFER))\n-\t\t\t\tinfra_clk_data-\u003ehws[i] = ERR_PTR(-ENOENT);\n-\t\t}\n-\t}\n-\n-\tmtk_clk_register_gates(\u0026pdev-\u003edev, node, infra_clks,\n-\t\t\t ARRAY_SIZE(infra_clks), infra_clk_data);\n-\tmtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),\n-\t\t\t\t infra_clk_data);\n-\n-\treturn of_clk_add_hw_provider(node, of_clk_hw_onecell_get,\n-\t\t\t\t infra_clk_data);\n-}\n+static const struct mtk_clk_desc infracfg_desc = {\n+\t.clks = infra_clks,\n+\t.num_clks = ARRAY_SIZE(infra_clks),\n+\t.factor_clks = infra_fixed_divs,\n+\t.num_factor_clks = ARRAY_SIZE(infra_fixed_divs),\n+};\n \n #define MT6797_PLL_FMAX\t\t(3000UL * MHZ)\n \n@@ -646,68 +584,36 @@ static const struct mtk_pll_data plls[] = {\n \t 0x2B4, 4, 0x2BC, 0x2B8, 0),\n };\n \n-static int mtk_apmixedsys_init(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_plls(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls), clk_data);\n-\n-\treturn of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-}\n+static const struct mtk_clk_desc apmixedsys_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+};\n \n static const struct of_device_id of_match_clk_mt6797[] = {\n \t{\n \t\t.compatible = \"mediatek,mt6797-topckgen\",\n-\t\t.data = mtk_topckgen_init,\n+\t\t.data = \u0026topckgen_desc,\n \t}, {\n \t\t.compatible = \"mediatek,mt6797-infracfg\",\n-\t\t.data = mtk_infrasys_init,\n+\t\t.data = \u0026infracfg_desc,\n \t}, {\n \t\t.compatible = \"mediatek,mt6797-apmixedsys\",\n-\t\t.data = mtk_apmixedsys_init,\n+\t\t.data = \u0026apmixedsys_desc,\n \t}, {\n \t\t/* sentinel */\n \t}\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt6797);\n \n-static int clk_mt6797_probe(struct platform_device *pdev)\n-{\n-\tint (*clk_init)(struct platform_device *);\n-\tint r;\n-\n-\tclk_init = of_device_get_match_data(\u0026pdev-\u003edev);\n-\tif (!clk_init)\n-\t\treturn -EINVAL;\n-\n-\tr = clk_init(pdev);\n-\tif (r)\n-\t\tdev_err(\u0026pdev-\u003edev,\n-\t\t\t\"could not register clock provider: %s: %d\\n\",\n-\t\t\tpdev-\u003ename, r);\n-\n-\treturn r;\n-}\n-\n static struct platform_driver clk_mt6797_drv = {\n-\t.probe = clk_mt6797_probe,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt6797\",\n \t\t.of_match_table = of_match_clk_mt6797,\n \t},\n };\n-\n-static int __init clk_mt6797_init(void)\n-{\n-\treturn platform_driver_register(\u0026clk_mt6797_drv);\n-}\n-\n-arch_initcall(clk_mt6797_init);\n+module_platform_driver(clk_mt6797_drv);\n \n MODULE_DESCRIPTION(\"MediaTek MT6797 main clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c\nindex 8a29eaab0cfcb..e9f731eadace1 100644\n--- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c\n@@ -80,64 +80,22 @@ static const struct mtk_gate apmixed_clks[] = {\n \tGATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, \"main_core_en\", \"mainpll\", 5),\n };\n \n-static int clk_mt7622_apmixed_probe(struct platform_device *pdev)\n-{\n-\tvoid __iomem *base;\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct device *dev = \u0026pdev-\u003edev;\n-\tint ret;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = mtk_clk_register_gates(\u0026pdev-\u003edev, node, apmixed_clks,\n-\t\t\t\t ARRAY_SIZE(apmixed_clks), clk_data);\n-\tif (ret)\n-\t\tgoto unregister_plls;\n-\n-\tret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_gates;\n-\n-\treturn 0;\n-\n-unregister_gates:\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-\n-\treturn ret;\n-}\n-\n-static void clk_mt7622_apmixed_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-}\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+\t.clks = apmixed_clks,\n+\t.num_clks = ARRAY_SIZE(apmixed_clks),\n+};\n \n static const struct of_device_id of_match_clk_mt7622_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt7622-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt7622-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_apmixed);\n \n static struct platform_driver clk_mt7622_apmixed_drv = {\n-\t.probe = clk_mt7622_apmixed_probe,\n-\t.remove = clk_mt7622_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt7622-apmixed\",\n \t\t.of_match_table = of_match_clk_mt7622_apmixed,\ndiff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c\nindex a4ea5e20efa29..6004c58be1b5b 100644\n--- a/drivers/clk/mediatek/clk-mt7622-aud.c\n+++ b/drivers/clk/mediatek/clk-mt7622-aud.c\n@@ -110,38 +110,9 @@ static const struct mtk_gate audio_clks[] = {\n static const struct mtk_clk_desc audio_desc = {\n \t.clks = audio_clks,\n \t.num_clks = ARRAY_SIZE(audio_clks),\n+\t.populate_children = true,\n };\n \n-static int clk_mt7622_aud_probe(struct platform_device *pdev)\n-{\n-\tint r;\n-\n-\tr = mtk_clk_simple_probe(pdev);\n-\tif (r) {\n-\t\tdev_err(\u0026pdev-\u003edev,\n-\t\t\t\"could not register clock provider: %s: %d\\n\",\n-\t\t\tpdev-\u003ename, r);\n-\n-\t\treturn r;\n-\t}\n-\n-\tr = devm_of_platform_populate(\u0026pdev-\u003edev);\n-\tif (r)\n-\t\tgoto err_plat_populate;\n-\n-\treturn 0;\n-\n-err_plat_populate:\n-\tmtk_clk_simple_remove(pdev);\n-\treturn r;\n-}\n-\n-static void clk_mt7622_aud_remove(struct platform_device *pdev)\n-{\n-\tof_platform_depopulate(\u0026pdev-\u003edev);\n-\tmtk_clk_simple_remove(pdev);\n-}\n-\n static const struct of_device_id of_match_clk_mt7622_aud[] = {\n \t{ .compatible = \"mediatek,mt7622-audsys\", .data = \u0026audio_desc },\n \t{ /* sentinel */ }\n@@ -149,8 +120,8 @@ static const struct of_device_id of_match_clk_mt7622_aud[] = {\n MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_aud);\n \n static struct platform_driver clk_mt7622_aud_drv = {\n-\t.probe = clk_mt7622_aud_probe,\n-\t.remove = clk_mt7622_aud_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt7622-aud\",\n \t\t.of_match_table = of_match_clk_mt7622_aud,\ndiff --git a/drivers/clk/mediatek/clk-mt7622-infracfg.c b/drivers/clk/mediatek/clk-mt7622-infracfg.c\nindex cfdf3b07c3e06..2e463d1481d02 100644\n--- a/drivers/clk/mediatek/clk-mt7622-infracfg.c\n+++ b/drivers/clk/mediatek/clk-mt7622-infracfg.c\n@@ -9,7 +9,6 @@\n #include \u003clinux/module.h\u003e\n #include \u003clinux/platform_device.h\u003e\n \n-#include \"clk-cpumux.h\"\n #include \"clk-gate.h\"\n #include \"clk-mtk.h\"\n #include \"reset.h\"\n@@ -51,74 +50,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {\n \t.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),\n };\n \n+static const struct mtk_clk_desc infra_desc = {\n+\t.clks = infra_clks,\n+\t.num_clks = ARRAY_SIZE(infra_clks),\n+\t.cpumuxes = cpu_muxes,\n+\t.num_cpumuxes = ARRAY_SIZE(cpu_muxes),\n+\t.rst_desc = \u0026clk_rst_desc,\n+};\n+\n static const struct of_device_id of_match_clk_mt7622_infracfg[] = {\n-\t{ .compatible = \"mediatek,mt7622-infracfg\" },\n+\t{ .compatible = \"mediatek,mt7622-infracfg\", .data = \u0026infra_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg);\n \n-static int clk_mt7622_infracfg_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tvoid __iomem *base;\n-\tint ret;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tret = mtk_register_reset_controller_with_dev(\u0026pdev-\u003edev, \u0026clk_rst_desc);\n-\tif (ret)\n-\t\tgoto free_clk_data;\n-\n-\tret = mtk_clk_register_gates(\u0026pdev-\u003edev, node, infra_clks,\n-\t\t\t\t ARRAY_SIZE(infra_clks), clk_data);\n-\tif (ret)\n-\t\tgoto free_clk_data;\n-\n-\tret = mtk_clk_register_cpumuxes(\u0026pdev-\u003edev, node, cpu_muxes,\n-\t\t\t\t\tARRAY_SIZE(cpu_muxes), clk_data);\n-\tif (ret)\n-\t\tgoto unregister_gates;\n-\n-\tret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_cpumuxes;\n-\n-\treturn 0;\n-\n-unregister_cpumuxes:\n-\tmtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);\n-unregister_gates:\n-\tmtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);\n-free_clk_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn ret;\n-}\n-\n-static void clk_mt7622_infracfg_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);\n-\tmtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt7622_infracfg_drv = {\n \t.driver = {\n \t\t.name = \"clk-mt7622-infracfg\",\n \t\t.of_match_table = of_match_clk_mt7622_infracfg,\n \t},\n-\t.probe = clk_mt7622_infracfg_probe,\n-\t.remove = clk_mt7622_infracfg_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n };\n module_platform_driver(clk_mt7622_infracfg_drv);\n \ndiff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediatek/clk-mt7981-apmixed.c\nindex 851d0bc7840ac..810395aff2538 100644\n--- a/drivers/clk/mediatek/clk-mt7981-apmixed.c\n+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c\n@@ -59,45 +59,26 @@ static const struct mtk_pll_data plls[] = {\n \t 0x0278, 4, 0, 0x027C, 0),\n };\n \n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+};\n+\n static const struct of_device_id of_match_clk_mt7981_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt7981-apmixedsys\", },\n+\t{ .compatible = \"mediatek,mt7981-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_apmixed);\n \n-static int clk_mt7981_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tint r;\n-\n-\tclk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_plls(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls), clk_data);\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r) {\n-\t\tpr_err(\"%s(): could not register clock provider: %d\\n\",\n-\t\t __func__, r);\n-\t\tgoto free_apmixed_data;\n-\t}\n-\treturn r;\n-\n-free_apmixed_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n static struct platform_driver clk_mt7981_apmixed_drv = {\n-\t.probe = clk_mt7981_apmixed_probe,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt7981-apmixed\",\n \t\t.of_match_table = of_match_clk_mt7981_apmixed,\n \t},\n };\n-builtin_platform_driver(clk_mt7981_apmixed_drv);\n+module_platform_driver(clk_mt7981_apmixed_drv);\n \n MODULE_DESCRIPTION(\"MediaTek MT7981 apmixedsys clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c\nindex af3e002bbfb76..6df3e9555e4e2 100644\n--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c\n+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c\n@@ -57,45 +57,26 @@ static const struct mtk_pll_data plls[] = {\n \t 0x0278, 4, 0, 0x027c, 0),\n };\n \n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+};\n+\n static const struct of_device_id of_match_clk_mt7986_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt7986-apmixedsys\", },\n+\t{ .compatible = \"mediatek,mt7986-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_apmixed);\n \n-static int clk_mt7986_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tint r;\n-\n-\tclk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tmtk_clk_register_plls(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls), clk_data);\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r) {\n-\t\tpr_err(\"%s(): could not register clock provider: %d\\n\",\n-\t\t __func__, r);\n-\t\tgoto free_apmixed_data;\n-\t}\n-\treturn r;\n-\n-free_apmixed_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n static struct platform_driver clk_mt7986_apmixed_drv = {\n-\t.probe = clk_mt7986_apmixed_probe,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt7986-apmixed\",\n \t\t.of_match_table = of_match_clk_mt7986_apmixed,\n \t},\n };\n-builtin_platform_driver(clk_mt7986_apmixed_drv);\n+module_platform_driver(clk_mt7986_apmixed_drv);\n \n MODULE_DESCRIPTION(\"MediaTek MT7986 apmixedsys clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediatek/clk-mt7988-apmixed.c\nindex 416a4b88d100b..f7bb00e7d17a1 100644\n--- a/drivers/clk/mediatek/clk-mt7988-apmixed.c\n+++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c\n@@ -71,46 +71,26 @@ static const struct mtk_pll_data plls[] = {\n \t 0, 0x0318, 0, 0x0314),\n };\n \n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+};\n+\n static const struct of_device_id of_match_clk_mt7988_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt7988-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt7988-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n-\n-static int clk_mt7988_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tint r;\n-\n-\tclk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tr = mtk_clk_register_plls(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls), clk_data);\n-\tif (r)\n-\t\tgoto free_apmixed_data;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\treturn r;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-free_apmixed_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_apmixed);\n \n static struct platform_driver clk_mt7988_apmixed_drv = {\n-\t.probe = clk_mt7988_apmixed_probe,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt7988-apmixed\",\n \t\t.of_match_table = of_match_clk_mt7988_apmixed,\n \t},\n };\n-builtin_platform_driver(clk_mt7988_apmixed_drv);\n+module_platform_driver(clk_mt7988_apmixed_drv);\n \n MODULE_DESCRIPTION(\"MediaTek MT7988 apmixedsys clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c\nindex 19e4ee489ec39..fe868417de482 100644\n--- a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c\n@@ -47,54 +47,20 @@ static const struct mtk_pll_data plls[] = {\n \tPLL(CLK_APMIXED_VDECPLL, \"vdecpll\", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),\n };\n \n-static int clk_mt8135_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tint ret;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tret = mtk_clk_register_plls(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls),\n-\t\t\t\t clk_data);\n-\tif (ret)\n-\t\tgoto free_clk_data;\n-\n-\tret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_plls;\n-\n-\treturn 0;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-free_clk_data:\n-\tmtk_free_clk_data(clk_data);\n-\n-\treturn ret;\n-}\n-\n-static void clk_mt8135_apmixed_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+};\n \n static const struct of_device_id of_match_clk_mt8135_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt8135-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt8135-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8135_apmixed);\n \n static struct platform_driver clk_mt8135_apmixed_drv = {\n-\t.probe = clk_mt8135_apmixed_probe,\n-\t.remove = clk_mt8135_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8135-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8135_apmixed,\ndiff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c\nindex fb6c21bbeef81..2b1d1de74cdbd 100644\n--- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c\n@@ -89,44 +89,13 @@ static const struct mtk_clk_divider adj_divs[] = {\n \t\t 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO),\n };\n \n-static int clk_mt8167_apmixed_probe(struct platform_device *pdev)\n-{\n-\tvoid __iomem *base;\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct device *dev = \u0026pdev-\u003edev;\n-\tint ret;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_devm_alloc_clk_data(dev, MT8167_CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = mtk_clk_register_dividers(dev, adj_divs, ARRAY_SIZE(adj_divs), base,\n-\t\t\t\t\t\u0026mt8167_apmixed_clk_lock, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_plls;\n-\n-\tret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_dividers;\n-\n-\treturn 0;\n-\n-unregister_dividers:\n-\tmtk_clk_unregister_dividers(adj_divs, ARRAY_SIZE(adj_divs), clk_data);\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-\n-\treturn ret;\n-}\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+\t.divider_clks = adj_divs,\n+\t.num_divider_clks = ARRAY_SIZE(adj_divs),\n+\t.clk_lock = \u0026mt8167_apmixed_clk_lock,\n+};\n \n static const struct of_device_id of_match_clk_mt8167_apmixed[] = {\n \t{ .compatible = \"mediatek,mt8167-apmixedsys\" },\n@@ -135,13 +104,14 @@ static const struct of_device_id of_match_clk_mt8167_apmixed[] = {\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_apmixed);\n \n static struct platform_driver clk_mt8167_apmixed_drv = {\n-\t.probe = clk_mt8167_apmixed_probe,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8167-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8167_apmixed,\n \t},\n };\n-builtin_platform_driver(clk_mt8167_apmixed_drv)\n+module_platform_driver(clk_mt8167_apmixed_drv)\n \n MODULE_DESCRIPTION(\"MediaTek MT8167 apmixedsys clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c\nindex d7d416172ab35..65dc4489a09c8 100644\n--- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c\n@@ -179,6 +179,8 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)\n \tif (r)\n \t\tgoto unregister_ref2usb;\n \n+\tplatform_set_drvdata(pdev, clk_data);\n+\n \treturn 0;\n \n unregister_ref2usb:\ndiff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/mediatek/clk-mt8173-infracfg.c\nindex fa2d1d557e04f..fdd994736e833 100644\n--- a/drivers/clk/mediatek/clk-mt8173-infracfg.c\n+++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c\n@@ -17,22 +17,20 @@\n \t\tGATE_MTK(_id, _name, _parent, \u0026infra_cg_regs,\t\\\n \t\t\t _shift, \u0026mtk_clk_gate_ops_setclr)\n \n-static struct clk_hw_onecell_data *infra_clk_data;\n-\n static const struct mtk_gate_regs infra_cg_regs = {\n \t.set_ofs = 0x0040,\n \t.clr_ofs = 0x0044,\n \t.sta_ofs = 0x0048,\n };\n \n-static const char * const ca53_parents[] __initconst = {\n+static const char * const ca53_parents[] = {\n \t\"clk26m\",\n \t\"armca7pll\",\n \t\"mainpll\",\n \t\"univpll\"\n };\n \n-static const char * const ca72_parents[] __initconst = {\n+static const char * const ca72_parents[] = {\n \t\"clk26m\",\n \t\"armca15pll\",\n \t\"mainpll\",\n@@ -44,7 +42,7 @@ static const struct mtk_composite cpu_muxes[] = {\n \tMUX(CLK_INFRA_CA72SEL, \"infra_ca72_sel\", ca72_parents, 0x0000, 2, 2),\n };\n \n-static const struct mtk_fixed_factor infra_early_divs[] = {\n+static const struct mtk_fixed_factor infra_divs[] = {\n \tFACTOR(CLK_INFRA_CLK_13M, \"clk13m\", \"clk26m\", 1, 2),\n };\n \n@@ -70,93 +68,29 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {\n \t.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),\n };\n \n+static const struct mtk_clk_desc infracfg_desc = {\n+\t.clks = infra_gates,\n+\t.num_clks = ARRAY_SIZE(infra_gates),\n+\t.factor_clks = infra_divs,\n+\t.num_factor_clks = ARRAY_SIZE(infra_divs),\n+\t.cpumuxes = cpu_muxes,\n+\t.num_cpumuxes = ARRAY_SIZE(cpu_muxes),\n+\t.rst_desc = \u0026clk_rst_desc,\n+};\n+\n static const struct of_device_id of_match_clk_mt8173_infracfg[] = {\n-\t{ .compatible = \"mediatek,mt8173-infracfg\" },\n+\t{ .compatible = \"mediatek,mt8173-infracfg\", .data = \u0026infracfg_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_infracfg);\n \n-static void clk_mt8173_infra_init_early(struct device_node *node)\n-{\n-\tint i;\n-\n-\tinfra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);\n-\tif (!infra_clk_data)\n-\t\treturn;\n-\n-\tfor (i = 0; i \u003c CLK_INFRA_NR_CLK; i++)\n-\t\tinfra_clk_data-\u003ehws[i] = ERR_PTR(-EPROBE_DEFER);\n-\n-\tmtk_clk_register_factors(infra_early_divs,\n-\t\t\t\t ARRAY_SIZE(infra_early_divs), infra_clk_data);\n-\n-\tof_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data);\n-}\n-CLK_OF_DECLARE_DRIVER(mtk_infrasys, \"mediatek,mt8173-infracfg\",\n-\t\t clk_mt8173_infra_init_early);\n-\n-static int clk_mt8173_infracfg_probe(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tint r, i;\n-\n-\tif (!infra_clk_data) {\n-\t\tinfra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);\n-\t\tif (!infra_clk_data)\n-\t\t\treturn -ENOMEM;\n-\t} else {\n-\t\tfor (i = 0; i \u003c CLK_INFRA_NR_CLK; i++)\n-\t\t\tif (infra_clk_data-\u003ehws[i] == ERR_PTR(-EPROBE_DEFER))\n-\t\t\t\tinfra_clk_data-\u003ehws[i] = ERR_PTR(-ENOENT);\n-\t}\n-\n-\tr = mtk_clk_register_gates(\u0026pdev-\u003edev, node, infra_gates,\n-\t\t\t\t ARRAY_SIZE(infra_gates), infra_clk_data);\n-\tif (r)\n-\t\treturn r;\n-\n-\tr = mtk_clk_register_cpumuxes(\u0026pdev-\u003edev, node, cpu_muxes,\n-\t\t\t\t ARRAY_SIZE(cpu_muxes), infra_clk_data);\n-\tif (r)\n-\t\tgoto unregister_gates;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data);\n-\tif (r)\n-\t\tgoto unregister_cpumuxes;\n-\n-\tr = mtk_register_reset_controller_with_dev(\u0026pdev-\u003edev, \u0026clk_rst_desc);\n-\tif (r)\n-\t\tgoto unregister_clk_hw;\n-\n-\treturn 0;\n-\n-unregister_clk_hw:\n-\tof_clk_del_provider(node);\n-unregister_cpumuxes:\n-\tmtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_data);\n-unregister_gates:\n-\tmtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), infra_clk_data);\n-\treturn r;\n-}\n-\n-static void clk_mt8173_infracfg_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);\n-\tmtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt8173_infracfg_drv = {\n \t.driver = {\n \t\t.name = \"clk-mt8173-infracfg\",\n \t\t.of_match_table = of_match_clk_mt8173_infracfg,\n \t},\n-\t.probe = clk_mt8173_infracfg_probe,\n-\t.remove = clk_mt8173_infracfg_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n };\n module_platform_driver(clk_mt8173_infracfg_drv);\n \ndiff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c\nindex 6242d4f5376e7..deb96537a3aba 100644\n--- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c\n@@ -139,59 +139,28 @@ static const struct mtk_pll_data plls[] = {\n \t 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),\n };\n \n-static int clk_mt8183_apmixed_probe(struct platform_device *pdev)\n-{\n-\tvoid __iomem *base;\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct device *dev = \u0026pdev-\u003edev;\n-\tint ret;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = mtk_clk_register_gates(\u0026pdev-\u003edev, node, apmixed_clks,\n-\t\t\t\t ARRAY_SIZE(apmixed_clks), clk_data);\n-\tif (ret)\n-\t\tgoto unregister_plls;\n-\n-\tret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_gates;\n-\n-\treturn 0;\n-\n-unregister_gates:\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-\n-\treturn ret;\n-}\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+\t.clks = apmixed_clks,\n+\t.num_clks = ARRAY_SIZE(apmixed_clks),\n+};\n \n static const struct of_device_id of_match_clk_mt8183_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt8183-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt8183-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_apmixed);\n \n static struct platform_driver clk_mt8183_apmixed_drv = {\n-\t.probe = clk_mt8183_apmixed_probe,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8183-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8183_apmixed,\n \t},\n };\n-builtin_platform_driver(clk_mt8183_apmixed_drv)\n+module_platform_driver(clk_mt8183_apmixed_drv)\n \n MODULE_DESCRIPTION(\"MediaTek MT8183 apmixedsys clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c\nindex 011d329ad30e9..0a53b0408dccf 100644\n--- a/drivers/clk/mediatek/clk-mt8183-audio.c\n+++ b/drivers/clk/mediatek/clk-mt8183-audio.c\n@@ -70,29 +70,9 @@ static const struct mtk_gate audio_clks[] = {\n static const struct mtk_clk_desc audio_desc = {\n \t.clks = audio_clks,\n \t.num_clks = ARRAY_SIZE(audio_clks),\n+\t.populate_children = true,\n };\n \n-static int clk_mt8183_audio_probe(struct platform_device *pdev)\n-{\n-\tint r;\n-\n-\tr = mtk_clk_simple_probe(pdev);\n-\tif (r)\n-\t\treturn r;\n-\n-\tr = devm_of_platform_populate(\u0026pdev-\u003edev);\n-\tif (r)\n-\t\tmtk_clk_simple_remove(pdev);\n-\n-\treturn r;\n-}\n-\n-static void clk_mt8183_audio_remove(struct platform_device *pdev)\n-{\n-\tof_platform_depopulate(\u0026pdev-\u003edev);\n-\tmtk_clk_simple_remove(pdev);\n-}\n-\n static const struct of_device_id of_match_clk_mt8183_audio[] = {\n \t{ .compatible = \"mediatek,mt8183-audiosys\", .data = \u0026audio_desc },\n \t{ /* sentinel */ }\n@@ -100,8 +80,8 @@ static const struct of_device_id of_match_clk_mt8183_audio[] = {\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_audio);\n \n static struct platform_driver clk_mt8183_audio_drv = {\n-\t.probe = clk_mt8183_audio_probe,\n-\t.remove = clk_mt8183_audio_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8183-audio\",\n \t\t.of_match_table = of_match_clk_mt8183_audio,\ndiff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c\nindex d35dd2632e43a..b674b1e581a52 100644\n--- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c\n@@ -132,60 +132,23 @@ static struct mtk_pllfh_data pllfhs[] = {\n \tFH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),\n };\n \n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+\t.fhctl_node = \"mediatek,mt8186-fhctl\",\n+\t.pllfhs = pllfhs,\n+\t.num_pllfhs = ARRAY_SIZE(pllfhs),\n+};\n+\n static const struct of_device_id of_match_clk_mt8186_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt8186-apmixedsys\", },\n+\t{ .compatible = \"mediatek,mt8186-apmixedsys\", .data = \u0026apmixed_desc },\n \t{}\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_apmixed);\n \n-static int clk_mt8186_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tconst u8 *fhctl_node = \"mediatek,mt8186-fhctl\";\n-\tint r;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tfhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));\n-\n-\tr = mtk_clk_register_pllfhs(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls),\n-\t\t\t\t pllfhs, ARRAY_SIZE(pllfhs), clk_data);\n-\tif (r)\n-\t\tgoto free_apmixed_data;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\tplatform_set_drvdata(pdev, clk_data);\n-\n-\treturn r;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,\n-\t\t\t\t ARRAY_SIZE(pllfhs), clk_data);\n-free_apmixed_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n-static void clk_mt8186_apmixed_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,\n-\t\t\t\t ARRAY_SIZE(pllfhs), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt8186_apmixed_drv = {\n-\t.probe = clk_mt8186_apmixed_probe,\n-\t.remove = clk_mt8186_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8186-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8186_apmixed,\ndiff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c\nindex 48a2f61d4b77e..3937d93cac346 100644\n--- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c\n@@ -89,62 +89,22 @@ static const struct mtk_pll_data plls[] = {\n \t 0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),\n };\n \n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+\t.clks = apmixed_clks,\n+\t.num_clks = ARRAY_SIZE(apmixed_clks),\n+};\n+\n static const struct of_device_id of_match_clk_mt8188_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt8188-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt8188-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_apmixed);\n \n-static int clk_mt8188_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tint r;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tr = mtk_clk_register_plls(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls), clk_data);\n-\tif (r)\n-\t\tgoto free_apmixed_data;\n-\n-\tr = mtk_clk_register_gates(\u0026pdev-\u003edev, node, apmixed_clks,\n-\t\t\t\t ARRAY_SIZE(apmixed_clks), clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_gates;\n-\n-\tplatform_set_drvdata(pdev, clk_data);\n-\n-\treturn 0;\n-\n-unregister_gates:\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-free_apmixed_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n-static void clk_mt8188_apmixed_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt8188_apmixed_drv = {\n-\t.probe = clk_mt8188_apmixed_probe,\n-\t.remove = clk_mt8188_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8188-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8188_apmixed,\ndiff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c\nindex b0563a285bd66..92593370f23b1 100644\n--- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c\n@@ -143,70 +143,29 @@ static struct mtk_pllfh_data pllfhs[] = {\n \tFH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154),\n };\n \n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.clks = apmixed_clks,\n+\t.num_clks = ARRAY_SIZE(apmixed_clks),\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+\t.fhctl_node = \"mediatek,mt8192-fhctl\",\n+\t.pllfhs = pllfhs,\n+\t.num_pllfhs = ARRAY_SIZE(pllfhs),\n+};\n+\n static const struct of_device_id of_match_clk_mt8192_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt8192-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt8192-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_apmixed);\n \n-static int clk_mt8192_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tconst u8 *fhctl_node = \"mediatek,mt8192-fhctl\";\n-\tint r;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tfhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));\n-\n-\tr = mtk_clk_register_pllfhs(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls),\n-\t\t\t\t pllfhs, ARRAY_SIZE(pllfhs), clk_data);\n-\tif (r)\n-\t\tgoto free_clk_data;\n-\n-\tr = mtk_clk_register_gates(\u0026pdev-\u003edev, node, apmixed_clks,\n-\t\t\t\t ARRAY_SIZE(apmixed_clks), clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_gates;\n-\n-\treturn r;\n-\n-unregister_gates:\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-unregister_plls:\n-\tmtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,\n-\t\t\t\t ARRAY_SIZE(pllfhs), clk_data);\n-free_clk_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n-static void clk_mt8192_apmixed_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-\tmtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,\n-\t\t\t\t ARRAY_SIZE(pllfhs), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt8192_apmixed_drv = {\n \t.driver = {\n \t\t.name = \"clk-mt8192-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8192_apmixed,\n \t},\n-\t.probe = clk_mt8192_apmixed_probe,\n-\t.remove = clk_mt8192_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n };\n module_platform_driver(clk_mt8192_apmixed_drv);\n MODULE_DESCRIPTION(\"MediaTek MT8192 apmixed clocks driver\");\ndiff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c\nindex f3ebf8713fbb7..8625f656a2e44 100644\n--- a/drivers/clk/mediatek/clk-mt8192-aud.c\n+++ b/drivers/clk/mediatek/clk-mt8192-aud.c\n@@ -80,29 +80,9 @@ static const struct mtk_gate aud_clks[] = {\n static const struct mtk_clk_desc aud_desc = {\n \t.clks = aud_clks,\n \t.num_clks = ARRAY_SIZE(aud_clks),\n+\t.populate_children = true,\n };\n \n-static int clk_mt8192_aud_probe(struct platform_device *pdev)\n-{\n-\tint r;\n-\n-\tr = mtk_clk_simple_probe(pdev);\n-\tif (r)\n-\t\treturn r;\n-\n-\tr = devm_of_platform_populate(\u0026pdev-\u003edev);\n-\tif (r)\n-\t\tmtk_clk_simple_remove(pdev);\n-\n-\treturn r;\n-}\n-\n-static void clk_mt8192_aud_remove(struct platform_device *pdev)\n-{\n-\tof_platform_depopulate(\u0026pdev-\u003edev);\n-\tmtk_clk_simple_remove(pdev);\n-}\n-\n static const struct of_device_id of_match_clk_mt8192_aud[] = {\n \t{ .compatible = \"mediatek,mt8192-audsys\", .data = \u0026aud_desc },\n \t{ /* sentinel */ }\n@@ -110,8 +90,8 @@ static const struct of_device_id of_match_clk_mt8192_aud[] = {\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_aud);\n \n static struct platform_driver clk_mt8192_aud_drv = {\n-\t.probe = clk_mt8192_aud_probe,\n-\t.remove = clk_mt8192_aud_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8192-aud\",\n \t\t.of_match_table = of_match_clk_mt8192_aud,\ndiff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c\nindex a120c33055474..fc60cd4d93824 100644\n--- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c\n@@ -161,68 +161,25 @@ static struct mtk_pllfh_data pllfhs[] = {\n \tFH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),\n };\n \n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.clks = apmixed_clks,\n+\t.num_clks = ARRAY_SIZE(apmixed_clks),\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+\t.fhctl_node = \"mediatek,mt8195-fhctl\",\n+\t.pllfhs = pllfhs,\n+\t.num_pllfhs = ARRAY_SIZE(pllfhs),\n+};\n+\n static const struct of_device_id of_match_clk_mt8195_apmixed[] = {\n \t{ .compatible = \"mediatek,mt8195-apmixedsys\", },\n \t{}\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apmixed);\n \n-static int clk_mt8195_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tconst u8 *fhctl_node = \"mediatek,mt8195-fhctl\";\n-\tint r;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tfhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));\n-\n-\tr = mtk_clk_register_pllfhs(\u0026pdev-\u003edev, plls, ARRAY_SIZE(plls),\n-\t\t\t\t pllfhs, ARRAY_SIZE(pllfhs), clk_data);\n-\tif (r)\n-\t\tgoto free_apmixed_data;\n-\n-\tr = mtk_clk_register_gates(\u0026pdev-\u003edev, node, apmixed_clks,\n-\t\t\t\t ARRAY_SIZE(apmixed_clks), clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_gates;\n-\n-\tplatform_set_drvdata(pdev, clk_data);\n-\n-\treturn r;\n-\n-unregister_gates:\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-unregister_plls:\n-\tmtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,\n-\t\t\t\t ARRAY_SIZE(pllfhs), clk_data);\n-free_apmixed_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n-static void clk_mt8195_apmixed_remove(struct platform_device *pdev)\n-{\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);\n-\tmtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,\n-\t\t\t\t ARRAY_SIZE(pllfhs), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt8195_apmixed_drv = {\n-\t.probe = clk_mt8195_apmixed_probe,\n-\t.remove = clk_mt8195_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8195-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8195_apmixed,\ndiff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c\nindex a2d98ed58e348..36d358141ecb1 100644\n--- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c\n+++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c\n@@ -56,55 +56,20 @@ static const struct mtk_pll_data apusys_plls[] = {\n \tPLL(CLK_APUSYS_PLL_APUPLL2, \"apusys_pll_apupll2\", 0x038, 0x044, 0x03c, 0x03c),\n };\n \n-static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tint r;\n-\n-\tclk_data = mtk_alloc_clk_data(CLK_APUSYS_PLL_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tr = mtk_clk_register_plls(\u0026pdev-\u003edev, apusys_plls,\n-\t\t\t\t ARRAY_SIZE(apusys_plls), clk_data);\n-\tif (r)\n-\t\tgoto free_apusys_pll_data;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\tplatform_set_drvdata(pdev, clk_data);\n-\n-\treturn r;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);\n-free_apusys_pll_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n-static void clk_mt8195_apusys_pll_remove(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n+static const struct mtk_clk_desc apu_pll_desc = {\n+\t.plls = apusys_plls,\n+\t.num_plls = ARRAY_SIZE(apusys_plls),\n+};\n \n static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = {\n-\t{ .compatible = \"mediatek,mt8195-apusys_pll\", },\n+\t{ .compatible = \"mediatek,mt8195-apusys_pll\", .data = \u0026apu_pll_desc },\n \t{}\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apusys_pll);\n \n static struct platform_driver clk_mt8195_apusys_pll_drv = {\n-\t.probe = clk_mt8195_apusys_pll_probe,\n-\t.remove = clk_mt8195_apusys_pll_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8195-apusys_pll\",\n \t\t.of_match_table = of_match_clk_mt8195_apusys_pll,\ndiff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c\nindex c4ebb0170b82b..a20fa02070a88 100644\n--- a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c\n@@ -86,11 +86,6 @@\n \t\t.ops = \u0026mtk_pll_fenc_clr_set_ops,\t\t\\\n }\n \n-struct mtk_pll_desc {\n-\tconst struct mtk_pll_data *clks;\n-\tsize_t num_clks;\n-};\n-\n static const struct mtk_pll_data apmixed_plls[] = {\n \tPLL_FENC(CLK_APMIXED_MAINPLL, \"mainpll\", MAINPLL_CON0, FENC_STATUS_CON0,\n \t\t 7, PLL_AO, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22, 0),\n@@ -110,9 +105,9 @@ static const struct mtk_pll_data apmixed_plls[] = {\n \t\t 0, 0, SGMIIPLL_CON1, 24, SGMIIPLL_CON1, 0, 22, 7),\n };\n \n-static const struct mtk_pll_desc apmixed_desc = {\n-\t.clks = apmixed_plls,\n-\t.num_clks = ARRAY_SIZE(apmixed_plls),\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = apmixed_plls,\n+\t.num_plls = ARRAY_SIZE(apmixed_plls),\n };\n \n static const struct mtk_pll_data apmixed2_plls[] = {\n@@ -132,57 +127,11 @@ static const struct mtk_pll_data apmixed2_plls[] = {\n \t\t 0, 0, TVDPLL3_CON1, 24, TVDPLL3_CON1, 0, 22, 6),\n };\n \n-static const struct mtk_pll_desc apmixed2_desc = {\n-\t.clks = apmixed2_plls,\n-\t.num_clks = ARRAY_SIZE(apmixed2_plls),\n+static const struct mtk_clk_desc apmixed2_desc = {\n+\t.plls = apmixed2_plls,\n+\t.num_plls = ARRAY_SIZE(apmixed2_plls),\n };\n \n-static int clk_mt8196_apmixed_probe(struct platform_device *pdev)\n-{\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tconst struct mtk_pll_desc *mcd;\n-\tint r;\n-\n-\tmcd = device_get_match_data(\u0026pdev-\u003edev);\n-\tif (!mcd)\n-\t\treturn -EINVAL;\n-\n-\tclk_data = mtk_alloc_clk_data(mcd-\u003enum_clks);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tr = mtk_clk_register_plls(\u0026pdev-\u003edev, mcd-\u003eclks, mcd-\u003enum_clks,\n-\t\t\t\t clk_data);\n-\tif (r)\n-\t\tgoto free_apmixed_data;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\tplatform_set_drvdata(pdev, clk_data);\n-\n-\treturn r;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_plls(mcd-\u003eclks, mcd-\u003enum_clks, clk_data);\n-free_apmixed_data:\n-\tmtk_free_clk_data(clk_data);\n-\treturn r;\n-}\n-\n-static void clk_mt8196_apmixed_remove(struct platform_device *pdev)\n-{\n-\tconst struct mtk_pll_desc *mcd = device_get_match_data(\u0026pdev-\u003edev);\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_plls(mcd-\u003eclks, mcd-\u003enum_clks, clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static const struct of_device_id of_match_clk_mt8196_apmixed[] = {\n \t{ .compatible = \"mediatek,mt8196-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ .compatible = \"mediatek,mt8196-apmixedsys-gp2\",\n@@ -192,8 +141,8 @@ static const struct of_device_id of_match_clk_mt8196_apmixed[] = {\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_apmixed);\n \n static struct platform_driver clk_mt8196_apmixed_drv = {\n-\t.probe = clk_mt8196_apmixed_probe,\n-\t.remove = clk_mt8196_apmixed_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8196-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8196_apmixed,\ndiff --git a/drivers/clk/mediatek/clk-mt8196-mcu.c b/drivers/clk/mediatek/clk-mt8196-mcu.c\nindex 13642fc673c26..e392408c93b28 100644\n--- a/drivers/clk/mediatek/clk-mt8196-mcu.c\n+++ b/drivers/clk/mediatek/clk-mt8196-mcu.c\n@@ -68,29 +68,44 @@\n \t\t.pcwibits = MT8196_INTEGER_BITS,\t\t\\\n \t}\n \n-static const struct mtk_pll_data cpu_bl_plls[] = {\n-\tPLL(CLK_CPBL_ARMPLL_BL, \"armpll-bl\", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0,\n-\t 0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22),\n+static const struct mtk_clk_desc cpu_bl_plls = {\n+\t.plls = (const struct mtk_pll_data[]){\n+\t\tPLL(CLK_CPBL_ARMPLL_BL, \"armpll-bl\", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0,\n+\t\t 0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22),\n+\t},\n+\t.num_plls = 1,\n };\n \n-static const struct mtk_pll_data cpu_b_plls[] = {\n-\tPLL(CLK_CPB_ARMPLL_B, \"armpll-b\", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0,\n-\t PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22),\n+static const struct mtk_clk_desc cpu_b_plls = {\n+\t.plls = (const struct mtk_pll_data[]){\n+\t\tPLL(CLK_CPB_ARMPLL_B, \"armpll-b\", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0,\n+\t\t PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22),\n+\t},\n+\t.num_plls = 1,\n };\n \n-static const struct mtk_pll_data cpu_ll_plls[] = {\n-\tPLL(CLK_CPLL_ARMPLL_LL, \"armpll-ll\", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0,\n-\t 0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22),\n+static const struct mtk_clk_desc cpu_ll_plls = {\n+\t.plls = (const struct mtk_pll_data[]){\n+\t\tPLL(CLK_CPLL_ARMPLL_LL, \"armpll-ll\", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0,\n+\t\t 0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22),\n+\t},\n+\t.num_plls = 1,\n };\n \n-static const struct mtk_pll_data cci_plls[] = {\n-\tPLL(CLK_CCIPLL, \"ccipll\", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,\n-\t BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22),\n+static const struct mtk_clk_desc cci_plls = {\n+\t.plls = (const struct mtk_pll_data[]){\n+\t\tPLL(CLK_CCIPLL, \"ccipll\", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,\n+\t\t BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22),\n+\t},\n+\t.num_plls = 1,\n };\n \n-static const struct mtk_pll_data ptp_plls[] = {\n-\tPLL(CLK_PTPPLL, \"ptppll\", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO,\n-\t BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22),\n+static const struct mtk_clk_desc ptp_plls = {\n+\t.plls = (const struct mtk_pll_data[]){\n+\t\tPLL(CLK_PTPPLL, \"ptppll\", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO,\n+\t\t BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22),\n+\t},\n+\t.num_plls = 1,\n };\n \n static const struct of_device_id of_match_clk_mt8196_mcu[] = {\n@@ -106,56 +121,9 @@ static const struct of_device_id of_match_clk_mt8196_mcu[] = {\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mcu);\n \n-static int clk_mt8196_mcu_probe(struct platform_device *pdev)\n-{\n-\tconst struct mtk_pll_data *plls;\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tconst int num_plls = 1;\n-\tint r;\n-\n-\tplls = of_device_get_match_data(\u0026pdev-\u003edev);\n-\tif (!plls)\n-\t\treturn -EINVAL;\n-\n-\tclk_data = mtk_alloc_clk_data(num_plls);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tr = mtk_clk_register_plls(\u0026pdev-\u003edev, plls, num_plls, clk_data);\n-\tif (r)\n-\t\tgoto free_clk_data;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\tplatform_set_drvdata(pdev, clk_data);\n-\n-\treturn r;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, num_plls, clk_data);\n-free_clk_data:\n-\tmtk_free_clk_data(clk_data);\n-\n-\treturn r;\n-}\n-\n-static void clk_mt8196_mcu_remove(struct platform_device *pdev)\n-{\n-\tconst struct mtk_pll_data *plls = of_device_get_match_data(\u0026pdev-\u003edev);\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_plls(plls, 1, clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt8196_mcu_drv = {\n-\t.probe = clk_mt8196_mcu_probe,\n-\t.remove = clk_mt8196_mcu_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8196-mcu\",\n \t\t.of_match_table = of_match_clk_mt8196_mcu,\ndiff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/clk-mt8196-mfg.c\nindex a317183f1681b..a209162f62075 100644\n--- a/drivers/clk/mediatek/clk-mt8196-mfg.c\n+++ b/drivers/clk/mediatek/clk-mt8196-mfg.c\n@@ -61,22 +61,31 @@\n \t\t.parent_name = \"mfg_eb\",\t\t\t\\\n \t}\n \n-static const struct mtk_pll_data mfg_ao_plls[] = {\n-\tPLL(CLK_MFG_AO_MFGPLL, \"mfgpll\", MFGPLL_CON0, MFGPLL_CON0, 0, 0,\n-\t PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0,\n-\t MFGPLL_CON1, 0, 22),\n+static const struct mtk_clk_desc mfg_ao_plls = {\n+\t.plls = (const struct mtk_pll_data[]){\n+\t\tPLL(CLK_MFG_AO_MFGPLL, \"mfgpll\", MFGPLL_CON0,\n+\t\t MFGPLL_CON0, 0, 0, PLL_PARENT_EN, BIT(0),\n+\t\t MFGPLL_CON1, 24, 0, 0, 0, MFGPLL_CON1, 0, 22),\n+\t},\n+\t.num_plls = 1,\n };\n \n-static const struct mtk_pll_data mfgsc0_ao_plls[] = {\n-\tPLL(CLK_MFGSC0_AO_MFGPLL_SC0, \"mfgpll-sc0\", MFGPLL_SC0_CON0,\n-\t MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24,\n-\t 0, 0, 0, MFGPLL_SC0_CON1, 0, 22),\n+static const struct mtk_clk_desc mfgsc0_ao_plls = {\n+\t.plls = (const struct mtk_pll_data[]){\n+\t\tPLL(CLK_MFGSC0_AO_MFGPLL_SC0, \"mfgpll-sc0\", MFGPLL_SC0_CON0,\n+\t\t MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0),\n+\t\t MFGPLL_SC0_CON1, 24, 0, 0, 0, MFGPLL_SC0_CON1, 0, 22),\n+\t},\n+\t.num_plls = 1,\n };\n \n-static const struct mtk_pll_data mfgsc1_ao_plls[] = {\n-\tPLL(CLK_MFGSC1_AO_MFGPLL_SC1, \"mfgpll-sc1\", MFGPLL_SC1_CON0,\n-\t MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24,\n-\t 0, 0, 0, MFGPLL_SC1_CON1, 0, 22),\n+static const struct mtk_clk_desc mfgsc1_ao_plls = {\n+\t.plls = (const struct mtk_pll_data[]){\n+\t\tPLL(CLK_MFGSC1_AO_MFGPLL_SC1, \"mfgpll-sc1\", MFGPLL_SC1_CON0,\n+\t\t MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0),\n+\t\t MFGPLL_SC1_CON1, 24, 0, 0, 0, MFGPLL_SC1_CON1, 0, 22),\n+\t},\n+\t.num_plls = 1,\n };\n \n static const struct of_device_id of_match_clk_mt8196_mfg[] = {\n@@ -90,56 +99,9 @@ static const struct of_device_id of_match_clk_mt8196_mfg[] = {\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mfg);\n \n-static int clk_mt8196_mfg_probe(struct platform_device *pdev)\n-{\n-\tconst struct mtk_pll_data *plls;\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tconst int num_plls = 1;\n-\tint r;\n-\n-\tplls = of_device_get_match_data(\u0026pdev-\u003edev);\n-\tif (!plls)\n-\t\treturn -EINVAL;\n-\n-\tclk_data = mtk_alloc_clk_data(num_plls);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tr = mtk_clk_register_plls(\u0026pdev-\u003edev, plls, num_plls, clk_data);\n-\tif (r)\n-\t\tgoto free_clk_data;\n-\n-\tr = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (r)\n-\t\tgoto unregister_plls;\n-\n-\tplatform_set_drvdata(pdev, clk_data);\n-\n-\treturn r;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, num_plls, clk_data);\n-free_clk_data:\n-\tmtk_free_clk_data(clk_data);\n-\n-\treturn r;\n-}\n-\n-static void clk_mt8196_mfg_remove(struct platform_device *pdev)\n-{\n-\tconst struct mtk_pll_data *plls = of_device_get_match_data(\u0026pdev-\u003edev);\n-\tstruct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\n-\tof_clk_del_provider(node);\n-\tmtk_clk_unregister_plls(plls, 1, clk_data);\n-\tmtk_free_clk_data(clk_data);\n-}\n-\n static struct platform_driver clk_mt8196_mfg_drv = {\n-\t.probe = clk_mt8196_mfg_probe,\n-\t.remove = clk_mt8196_mfg_remove,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8196-mfg\",\n \t\t.of_match_table = of_match_clk_mt8196_mfg,\ndiff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c\nindex 2a6206cae2f08..2fb09e7acde75 100644\n--- a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c\n+++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c\n@@ -71,52 +71,26 @@ static const struct mtk_pll_data plls[] = {\n \t 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),\n };\n \n-static int clk_mt8516_apmixed_probe(struct platform_device *pdev)\n-{\n-\tvoid __iomem *base;\n-\tstruct clk_hw_onecell_data *clk_data;\n-\tstruct device_node *node = pdev-\u003edev.of_node;\n-\tstruct device *dev = \u0026pdev-\u003edev;\n-\tint ret;\n-\n-\tbase = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(base))\n-\t\treturn PTR_ERR(base);\n-\n-\tclk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);\n-\tif (!clk_data)\n-\t\treturn -ENOMEM;\n-\n-\tret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);\n-\tif (ret)\n-\t\tgoto unregister_plls;\n-\n-\treturn 0;\n-\n-unregister_plls:\n-\tmtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);\n-\n-\treturn ret;\n-}\n+static const struct mtk_clk_desc apmixed_desc = {\n+\t.plls = plls,\n+\t.num_plls = ARRAY_SIZE(plls),\n+};\n \n static const struct of_device_id of_match_clk_mt8516_apmixed[] = {\n-\t{ .compatible = \"mediatek,mt8516-apmixedsys\" },\n+\t{ .compatible = \"mediatek,mt8516-apmixedsys\", .data = \u0026apmixed_desc },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_apmixed);\n \n static struct platform_driver clk_mt8516_apmixed_drv = {\n-\t.probe = clk_mt8516_apmixed_probe,\n+\t.probe = mtk_clk_simple_probe,\n+\t.remove = mtk_clk_simple_remove,\n \t.driver = {\n \t\t.name = \"clk-mt8516-apmixed\",\n \t\t.of_match_table = of_match_clk_mt8516_apmixed,\n \t},\n };\n-builtin_platform_driver(clk_mt8516_apmixed_drv)\n+module_platform_driver(clk_mt8516_apmixed_drv)\n \n MODULE_DESCRIPTION(\"MediaTek MT8516 apmixedsys clocks driver\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex 3dfdd3a422f80..e80ae497fadd4 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -12,6 +12,7 @@\n #include \u003clinux/module.h\u003e\n #include \u003clinux/of.h\u003e\n #include \u003clinux/of_address.h\u003e\n+#include \u003clinux/of_platform.h\u003e\n #include \u003clinux/platform_device.h\u003e\n #include \u003clinux/pm_runtime.h\u003e\n #include \u003clinux/slab.h\u003e\n@@ -19,6 +20,12 @@\n #include \"clk-mtk.h\"\n #include \"clk-gate.h\"\n #include \"clk-mux.h\"\n+#include \"clk-cpumux.h\"\n+#include \"clk-pll.h\"\n+\n+#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL)\n+#include \"clk-fhctl.h\"\n+#endif\n \n const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };\n EXPORT_SYMBOL_GPL(cg_regs_dummy);\n@@ -485,7 +492,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,\n \t}\n \n \t/* Composite and divider clocks needs us to pass iomem pointer */\n-\tif (mcd-\u003ecomposite_clks || mcd-\u003edivider_clks) {\n+\tif (mcd-\u003ecomposite_clks || mcd-\u003edivider_clks || mcd-\u003eplls) {\n \t\tif (!mcd-\u003eshared_io)\n \t\t\tbase = devm_platform_ioremap_resource(pdev, 0);\n \t\telse\n@@ -513,6 +520,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,\n \tnum_clks = mcd-\u003enum_clks + mcd-\u003enum_composite_clks;\n \tnum_clks += mcd-\u003enum_fixed_clks + mcd-\u003enum_factor_clks;\n \tnum_clks += mcd-\u003enum_mux_clks + mcd-\u003enum_divider_clks;\n+\tnum_clks += mcd-\u003enum_cpumuxes + mcd-\u003enum_plls;\n \n \tclk_data = mtk_alloc_clk_data(num_clks);\n \tif (!clk_data) {\n@@ -520,11 +528,29 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,\n \t\tgoto free_base;\n \t}\n \n+\tif (mcd-\u003eplls) {\n+\t\tif (mcd-\u003efhctl_node) {\n+#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL)\n+\t\t\tfhctl_parse_dt(mcd-\u003efhctl_node, mcd-\u003epllfhs,\n+\t\t\t\t mcd-\u003enum_pllfhs);\n+\t\t\tr = mtk_clk_register_pllfhs(\u0026pdev-\u003edev, mcd-\u003eplls,\n+\t\t\t\t\t\t mcd-\u003enum_plls, mcd-\u003epllfhs,\n+\t\t\t\t\t\t mcd-\u003enum_pllfhs, clk_data);\n+#endif\n+\t\t} else {\n+\t\t\tr = mtk_clk_register_plls(\u0026pdev-\u003edev, mcd-\u003eplls,\n+\t\t\t\t\t mcd-\u003enum_plls, clk_data);\n+\t\t}\n+\n+\t\tif (r)\n+\t\t\tgoto free_data;\n+\t}\n+\n \tif (mcd-\u003efixed_clks) {\n \t\tr = mtk_clk_register_fixed_clks(mcd-\u003efixed_clks,\n \t\t\t\t\t\tmcd-\u003enum_fixed_clks, clk_data);\n \t\tif (r)\n-\t\t\tgoto free_data;\n+\t\t\tgoto unregister_plls;\n \t}\n \n \tif (mcd-\u003efactor_clks) {\n@@ -542,6 +568,13 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,\n \t\t\tgoto unregister_factors;\n \t}\n \n+\tif (mcd-\u003ecpumuxes) {\n+\t\tr = mtk_clk_register_cpumuxes(\u0026pdev-\u003edev, node, mcd-\u003ecpumuxes,\n+\t\t\t\t\t mcd-\u003enum_cpumuxes, clk_data);\n+\t\tif (r)\n+\t\t\tgoto unregister_muxes;\n+\t}\n+\n \tif (mcd-\u003ecomposite_clks) {\n \t\t/* We don't check composite_lock because it's optional */\n \t\tr = mtk_clk_register_composites(\u0026pdev-\u003edev,\n@@ -549,7 +582,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,\n \t\t\t\t\t\tmcd-\u003enum_composite_clks,\n \t\t\t\t\t\tbase, mcd-\u003eclk_lock, clk_data);\n \t\tif (r)\n-\t\t\tgoto unregister_muxes;\n+\t\t\tgoto unregister_cpumuxes;\n \t}\n \n \tif (mcd-\u003edivider_clks) {\n@@ -592,6 +625,12 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,\n \tif (mcd-\u003eneed_runtime_pm)\n \t\tpm_runtime_put(\u0026pdev-\u003edev);\n \n+\tif (mcd-\u003epopulate_children) {\n+\t\tr = devm_of_platform_populate(\u0026pdev-\u003edev);\n+\t\tif (r)\n+\t\t\tgoto unregister_clks;\n+\t}\n+\n \treturn r;\n \n unregister_clks:\n@@ -605,6 +644,10 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,\n \tif (mcd-\u003ecomposite_clks)\n \t\tmtk_clk_unregister_composites(mcd-\u003ecomposite_clks,\n \t\t\t\t\t mcd-\u003enum_composite_clks, clk_data);\n+unregister_cpumuxes:\n+\tif (mcd-\u003ecpumuxes)\n+\t\tmtk_clk_unregister_cpumuxes(mcd-\u003ecpumuxes,\n+\t\t\t\t\t mcd-\u003enum_cpumuxes, clk_data);\n unregister_muxes:\n \tif (mcd-\u003emux_clks)\n \t\tmtk_clk_unregister_muxes(mcd-\u003emux_clks,\n@@ -617,6 +660,18 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,\n \tif (mcd-\u003efixed_clks)\n \t\tmtk_clk_unregister_fixed_clks(mcd-\u003efixed_clks,\n \t\t\t\t\t mcd-\u003enum_fixed_clks, clk_data);\n+unregister_plls:\n+\tif (mcd-\u003eplls) {\n+\t\tif (mcd-\u003efhctl_node)\n+#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL)\n+\t\t\tmtk_clk_unregister_pllfhs(mcd-\u003eplls, mcd-\u003enum_plls,\n+\t\t\t\t\t\t mcd-\u003epllfhs, mcd-\u003enum_pllfhs,\n+\t\t\t\t\t\t clk_data);\n+#endif\n+\t\telse\n+\t\t\tmtk_clk_unregister_plls(mcd-\u003eplls, mcd-\u003enum_plls,\n+\t\t\t\t\t\tclk_data);\n+\t}\n free_data:\n \tmtk_free_clk_data(clk_data);\n free_base:\n@@ -643,6 +698,9 @@ static void __mtk_clk_simple_remove(struct platform_device *pdev,\n \tif (mcd-\u003ecomposite_clks)\n \t\tmtk_clk_unregister_composites(mcd-\u003ecomposite_clks,\n \t\t\t\t\t mcd-\u003enum_composite_clks, clk_data);\n+\tif (mcd-\u003ecpumuxes)\n+\t\tmtk_clk_unregister_cpumuxes(mcd-\u003ecpumuxes,\n+\t\t\t\t\t mcd-\u003enum_cpumuxes, clk_data);\n \tif (mcd-\u003emux_clks)\n \t\tmtk_clk_unregister_muxes(mcd-\u003emux_clks,\n \t\t\t\t\t mcd-\u003enum_mux_clks, clk_data);\n@@ -652,6 +710,18 @@ static void __mtk_clk_simple_remove(struct platform_device *pdev,\n \tif (mcd-\u003efixed_clks)\n \t\tmtk_clk_unregister_fixed_clks(mcd-\u003efixed_clks,\n \t\t\t\t\t mcd-\u003enum_fixed_clks, clk_data);\n+\tif (mcd-\u003eplls) {\n+\t\tif (mcd-\u003efhctl_node)\n+#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL)\n+\t\t\tmtk_clk_unregister_pllfhs(mcd-\u003eplls, mcd-\u003enum_plls,\n+\t\t\t\t\t\t mcd-\u003epllfhs, mcd-\u003enum_pllfhs,\n+\t\t\t\t\t\t clk_data);\n+#endif\n+\t\telse\n+\t\t\tmtk_clk_unregister_plls(mcd-\u003eplls, mcd-\u003enum_plls,\n+\t\t\t\t\t\tclk_data);\n+\t}\n+\n \tmtk_free_clk_data(clk_data);\n }\n \ndiff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h\nindex 5417b9264e6df..4e959ec68da07 100644\n--- a/drivers/clk/mediatek/clk-mtk.h\n+++ b/drivers/clk/mediatek/clk-mtk.h\n@@ -15,6 +15,8 @@\n \n #include \"reset.h\"\n \n+#include \"clk-fhctl.h\"\n+\n #define MAX_MUX_GATE_BIT\t31\n #define INVALID_MUX_GATE_BIT\t(MAX_MUX_GATE_BIT + 1)\n \n@@ -23,6 +25,7 @@\n #define MTK_WAIT_HWV_DONE_US\t30\n \n struct platform_device;\n+struct mtk_pll_data;\n \n /*\n * We need the clock IDs to start from zero but to maintain devicetree\n@@ -252,6 +255,10 @@ struct mtk_clk_desc {\n \tsize_t num_factor_clks;\n \tconst struct mtk_mux *mux_clks;\n \tsize_t num_mux_clks;\n+\tconst struct mtk_composite *cpumuxes;\n+\tsize_t num_cpumuxes;\n+\tconst struct mtk_pll_data *plls;\n+\tsize_t num_plls;\n \tconst struct mtk_clk_rst_desc *rst_desc;\n \tspinlock_t *clk_lock;\n \tbool shared_io;\n@@ -260,6 +267,11 @@ struct mtk_clk_desc {\n \tunsigned int mfg_clk_idx;\n \n \tbool need_runtime_pm;\n+\tbool populate_children;\n+\n+\tconst u8 *fhctl_node;\n+\tstruct mtk_pllfh_data *pllfhs;\n+\tsize_t num_pllfhs;\n };\n \n int mtk_clk_pdev_probe(struct platform_device *pdev);\n"
} |
| 2/1 | 2026/08/03 19:03 | agent | patch-evaluator |
0mModel:best-expensive Args: null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch refactors MediaTek SoC-specific clock drivers to use a common probe/remove infrastructure and changes several Kconfig options to tristate. These platform drivers bind to specific MediaTek compatible strings (e.g., \"mediatek,mt2701-topckgen\") which are not present in the device trees of generic virtualized environments like QEMU or GCE. Therefore, the modified code paths are impossible to reach and test during standard fuzzing.",
"WorthFuzzing": false
}Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). - Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU. - Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove) that are executed only during PCI hot-unplug or sysfs driver unbind operations. If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. Prefer non-static, non-inlined API entrypoint functions over internal static helper functions (which are inlined by the compiler and do not have distinct symbol addresses). 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes:
commit bcae9805b06d74233d95c1426614080fd3776de3
Author: syz-cluster <triage@syzkaller.com>
Date: Mon Aug 3 19:03:37 2026 +0000
syz-cluster: applied patch under review
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 2c09fd729bab0..ac992cfc6c3e8 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -19,7 +19,7 @@ config COMMON_CLK_MEDIATEK_FHCTL
spread spectrum clocking features.
config COMMON_CLK_MT2701
- bool "Clock driver for MediaTek MT2701"
+ tristate "Clock driver for MediaTek MT2701"
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK && ARM
@@ -27,49 +27,49 @@ config COMMON_CLK_MT2701
This driver supports MediaTek MT2701 basic clocks.
config COMMON_CLK_MT2701_MMSYS
- bool "Clock driver for MediaTek MT2701 mmsys"
+ tristate "Clock driver for MediaTek MT2701 mmsys"
depends on COMMON_CLK_MT2701
help
This driver supports MediaTek MT2701 mmsys clocks.
config COMMON_CLK_MT2701_IMGSYS
- bool "Clock driver for MediaTek MT2701 imgsys"
+ tristate "Clock driver for MediaTek MT2701 imgsys"
depends on COMMON_CLK_MT2701
help
This driver supports MediaTek MT2701 imgsys clocks.
config COMMON_CLK_MT2701_VDECSYS
- bool "Clock driver for MediaTek MT2701 vdecsys"
+ tristate "Clock driver for MediaTek MT2701 vdecsys"
depends on COMMON_CLK_MT2701
help
This driver supports MediaTek MT2701 vdecsys clocks.
config COMMON_CLK_MT2701_HIFSYS
- bool "Clock driver for MediaTek MT2701 hifsys"
+ tristate "Clock driver for MediaTek MT2701 hifsys"
depends on COMMON_CLK_MT2701
help
This driver supports MediaTek MT2701 hifsys clocks.
config COMMON_CLK_MT2701_ETHSYS
- bool "Clock driver for MediaTek MT2701 ethsys"
+ tristate "Clock driver for MediaTek MT2701 ethsys"
depends on COMMON_CLK_MT2701
help
This driver supports MediaTek MT2701 ethsys clocks.
config COMMON_CLK_MT2701_BDPSYS
- bool "Clock driver for MediaTek MT2701 bdpsys"
+ tristate "Clock driver for MediaTek MT2701 bdpsys"
depends on COMMON_CLK_MT2701
help
This driver supports MediaTek MT2701 bdpsys clocks.
config COMMON_CLK_MT2701_AUDSYS
- bool "Clock driver for Mediatek MT2701 audsys"
+ tristate "Clock driver for Mediatek MT2701 audsys"
depends on COMMON_CLK_MT2701
help
This driver supports Mediatek MT2701 audsys clocks.
config COMMON_CLK_MT2701_G3DSYS
- bool "Clock driver for MediaTek MT2701 g3dsys"
+ tristate "Clock driver for MediaTek MT2701 g3dsys"
depends on COMMON_CLK_MT2701
help
This driver supports MediaTek MT2701 g3dsys clocks.
@@ -342,7 +342,7 @@ config COMMON_CLK_MT6795_VENCSYS
This driver supports MediaTek MT6795 vencsys clocks.
config COMMON_CLK_MT6797
- bool "Clock driver for MediaTek MT6797"
+ tristate "Clock driver for MediaTek MT6797"
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK && ARM64
@@ -427,7 +427,7 @@ config COMMON_CLK_MT7629_HIFSYS
to PCI-E and USB.
config COMMON_CLK_MT7981
- bool "Clock driver for MediaTek MT7981"
+ tristate "Clock driver for MediaTek MT7981"
depends on ARCH_MEDIATEK || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK
@@ -909,13 +909,13 @@ config COMMON_CLK_MT8192_VENCSYS
This driver supports MediaTek MT8192 vencsys clocks.
config COMMON_CLK_MT8195
- bool "Clock driver for MediaTek MT8195"
- depends on ARM64 || COMPILE_TEST
- select COMMON_CLK_MEDIATEK
+ tristate "Clock driver for MediaTek MT8195"
+ depends on ARM64 || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
select COMMON_CLK_MEDIATEK_FHCTL
- default ARCH_MEDIATEK
- help
- This driver supports MediaTek MT8195 clocks.
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8195 clocks.
config COMMON_CLK_MT8195_APUSYS
tristate "Clock driver for MediaTek MT8195 apusys"
diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c
index e103121cf58e7..533d35614661a 100644
--- a/drivers/clk/mediatek/clk-mt2701-aud.c
+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
@@ -128,6 +128,7 @@ static const struct mtk_gate audio_clks[] = {
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
+ .populate_children = true,
};
static const struct of_device_id of_match_clk_mt2701_aud[] = {
@@ -136,39 +137,9 @@ static const struct of_device_id of_match_clk_mt2701_aud[] = {
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_aud);
-static int clk_mt2701_aud_probe(struct platform_device *pdev)
-{
- int r;
-
- r = mtk_clk_simple_probe(pdev);
- if (r) {
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
- }
-
- r = devm_of_platform_populate(&pdev->dev);
- if (r)
- goto err_plat_populate;
-
- return 0;
-
-err_plat_populate:
- mtk_clk_simple_remove(pdev);
- return r;
-}
-
-static void clk_mt2701_aud_remove(struct platform_device *pdev)
-{
- of_platform_depopulate(&pdev->dev);
- mtk_clk_simple_remove(pdev);
-}
-
static struct platform_driver clk_mt2701_aud_drv = {
- .probe = clk_mt2701_aud_probe,
- .remove = clk_mt2701_aud_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-aud",
.of_match_table = of_match_clk_mt2701_aud,
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 710c4f2f9f304..5ea0c4acaf1be 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -6,6 +6,7 @@
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
+#include <linux/module.h>
#include "clk-cpumux.h"
#include "clk-gate.h"
@@ -655,38 +656,19 @@ static const struct mtk_gate top_clks[] = {
28),
};
-static int mtk_topckgen_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- void __iomem *base;
- struct device_node *node = pdev->dev.of_node;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
- clk_data);
-
- mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
- clk_data);
-
- mtk_clk_register_composites(&pdev->dev, top_muxes,
- ARRAY_SIZE(top_muxes), base,
- &mt2701_clk_lock, clk_data);
-
- mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_divs),
- base, &mt2701_clk_lock, clk_data);
-
- mtk_clk_register_gates(&pdev->dev, node, top_clks,
- ARRAY_SIZE(top_clks), clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-}
+static const struct mtk_clk_desc topck_desc = {
+ .clks = top_clks,
+ .num_clks = ARRAY_SIZE(top_clks),
+ .fixed_clks = top_fixed_clks,
+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
+ .factor_clks = top_fixed_divs,
+ .num_factor_clks = ARRAY_SIZE(top_fixed_divs),
+ .composite_clks = top_muxes,
+ .num_composite_clks = ARRAY_SIZE(top_muxes),
+ .divider_clks = top_adj_divs,
+ .num_divider_clks = ARRAY_SIZE(top_adj_divs),
+ .clk_lock = &mt2701_clk_lock,
+};
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x0040,
@@ -725,81 +707,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
-static const struct mtk_clk_rst_desc clk_rst_desc[] = {
- /* infrasys */
- {
- .version = MTK_RST_SIMPLE,
- .rst_bank_ofs = infrasys_rst_ofs,
- .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
- },
- /* pericfg */
- {
- .version = MTK_RST_SIMPLE,
- .rst_bank_ofs = pericfg_rst_ofs,
- .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
- },
+static const struct mtk_clk_rst_desc infra_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_ofs = infrasys_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
};
-static struct clk_hw_onecell_data *infra_clk_data;
-
-static void __init mtk_infrasys_init_early(struct device_node *node)
-{
- int r, i;
-
- if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
- if (!infra_clk_data)
- return;
-
- for (i = 0; i < CLK_INFRA_NR; i++)
- infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
- }
-
- mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
- infra_clk_data);
-
- mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
- infra_clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- infra_clk_data);
- if (r)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-}
-CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
- mtk_infrasys_init_early);
-
-static int mtk_infrasys_init(struct platform_device *pdev)
-{
- int r, i;
- struct device_node *node = pdev->dev.of_node;
-
- if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
- if (!infra_clk_data)
- return -ENOMEM;
- } else {
- for (i = 0; i < CLK_INFRA_NR; i++) {
- if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
- infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
- }
- }
-
- mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- ARRAY_SIZE(infra_clks), infra_clk_data);
- mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
- infra_clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- infra_clk_data);
- if (r)
- return r;
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
-
- return 0;
-}
+static const struct mtk_clk_desc infracfg_desc = {
+ .clks = infra_clks,
+ .num_clks = ARRAY_SIZE(infra_clks),
+ .factor_clks = infra_fixed_divs,
+ .num_factor_clks = ARRAY_SIZE(infra_fixed_divs),
+ .cpumuxes = cpu_muxes,
+ .num_cpumuxes = ARRAY_SIZE(cpu_muxes),
+ .rst_desc = &infra_rst_desc,
+};
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x0008,
@@ -883,36 +805,20 @@ static const struct mtk_composite peri_muxs[] = {
0x40c, 3, 1),
};
-static int mtk_pericfg_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- void __iomem *base;
- int r;
- struct device_node *node = pdev->dev.of_node;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_gates(&pdev->dev, node, peri_clks,
- ARRAY_SIZE(peri_clks), clk_data);
-
- mtk_clk_register_composites(&pdev->dev, peri_muxs,
- ARRAY_SIZE(peri_muxs), base,
- &mt2701_clk_lock, clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- return r;
-
- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
+static const struct mtk_clk_rst_desc peri_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_ofs = pericfg_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
+};
- return 0;
-}
+static const struct mtk_clk_desc pericfg_desc = {
+ .clks = peri_clks,
+ .num_clks = ARRAY_SIZE(peri_clks),
+ .composite_clks = peri_muxs,
+ .num_composite_clks = ARRAY_SIZE(peri_muxs),
+ .rst_desc = &peri_rst_desc,
+ .clk_lock = &mt2701_clk_lock,
+};
#define MT8590_PLL_FMAX (2000 * MHZ)
#define CON0_MT8590_RST_BAR BIT(27)
@@ -968,74 +874,41 @@ static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
};
-static int mtk_apmixedsys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls),
- clk_data);
- mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
- clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-}
+static const struct mtk_clk_desc apmixedsys_desc = {
+ .plls = apmixed_plls,
+ .num_plls = ARRAY_SIZE(apmixed_plls),
+ .factor_clks = apmixed_fixed_divs,
+ .num_factor_clks = ARRAY_SIZE(apmixed_fixed_divs),
+};
static const struct of_device_id of_match_clk_mt2701[] = {
{
.compatible = "mediatek,mt2701-topckgen",
- .data = mtk_topckgen_init,
+ .data = &topck_desc,
}, {
.compatible = "mediatek,mt2701-infracfg",
- .data = mtk_infrasys_init,
+ .data = &infracfg_desc,
}, {
.compatible = "mediatek,mt2701-pericfg",
- .data = mtk_pericfg_init,
+ .data = &pericfg_desc,
}, {
.compatible = "mediatek,mt2701-apmixedsys",
- .data = mtk_apmixedsys_init,
+ .data = &apmixedsys_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701);
-static int clk_mt2701_probe(struct platform_device *pdev)
-{
- int (*clk_init)(struct platform_device *);
- int r;
-
- clk_init = of_device_get_match_data(&pdev->dev);
- if (!clk_init)
- return -EINVAL;
-
- r = clk_init(pdev);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
-}
-
static struct platform_driver clk_mt2701_drv = {
- .probe = clk_mt2701_probe,
.driver = {
.name = "clk-mt2701",
.of_match_table = of_match_clk_mt2701,
},
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
};
-
-static int __init clk_mt2701_init(void)
-{
- return platform_driver_register(&clk_mt2701_drv);
-}
-
-arch_initcall(clk_mt2701_init);
+module_platform_driver(clk_mt2701_drv);
MODULE_DESCRIPTION("MediaTek MT2701 main clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c
index 54b18e9f83f8f..1e06f87e71d08 100644
--- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c
@@ -109,54 +109,20 @@ static const struct mtk_pll_data plls[] = {
0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
};
-static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- int r;
- struct device_node *node = pdev->dev.of_node;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
- if (r)
- goto free_clk_data;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
- dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r);
- goto unregister_plls;
- }
-
- return 0;
-
-unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-free_clk_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static void clk_mt2712_apmixed_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
- mtk_free_clk_data(clk_data);
-}
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+};
static const struct of_device_id of_match_clk_mt2712_apmixed[] = {
- { .compatible = "mediatek,mt2712-apmixedsys" },
+ { .compatible = "mediatek,mt2712-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_apmixed);
static struct platform_driver clk_mt2712_apmixed_drv = {
- .probe = clk_mt2712_apmixed_probe,
- .remove = clk_mt2712_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2712-apmixed",
.of_match_table = of_match_clk_mt2712_apmixed,
diff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
index 9e30c089a2092..94cb0bee8bb40 100644
--- a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
@@ -77,54 +77,20 @@ static const struct mtk_pll_data apmixedsys_plls[] = {
PLL(CLK_APMIXED_APLL2, "apll2", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0, APLL2_CON0, 4, APLL2_CON2, AP_PLL_CON_5, 1, APLL2_CON1, 31, 0)
};
-static int clk_mt6735_apmixed_probe(struct platform_device *pdev)
-{
- void __iomem *base;
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- struct clk_hw_onecell_data *clk_data;
- int ret;
-
- base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_devm_alloc_clk_data(&pdev->dev, ARRAY_SIZE(apmixedsys_plls));
- if (!clk_data)
- return -ENOMEM;
- platform_set_drvdata(pdev, clk_data);
-
- ret = mtk_clk_register_plls(&pdev->dev, apmixedsys_plls,
- ARRAY_SIZE(apmixedsys_plls), clk_data);
- if (ret) {
- dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
- return ret;
- }
-
- ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
- clk_data);
- if (ret)
- dev_err(&pdev->dev,
- "Failed to register clock provider: %d\n", ret);
-
- return ret;
-}
-
-static void clk_mt6735_apmixed_remove(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data);
-}
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = apmixedsys_plls,
+ .num_plls = ARRAY_SIZE(apmixedsys_plls),
+};
static const struct of_device_id of_match_mt6735_apmixedsys[] = {
- { .compatible = "mediatek,mt6735-apmixedsys" },
+ { .compatible = "mediatek,mt6735-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_mt6735_apmixedsys);
static struct platform_driver clk_mt6735_apmixedsys = {
- .probe = clk_mt6735_apmixed_probe,
- .remove = clk_mt6735_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6735-apmixedsys",
.of_match_table = of_match_mt6735_apmixedsys,
diff --git a/drivers/clk/mediatek/clk-mt6735-imgsys.c b/drivers/clk/mediatek/clk-mt6735-imgsys.c
index c564f8f724324..813241d526cf4 100644
--- a/drivers/clk/mediatek/clk-mt6735-imgsys.c
+++ b/drivers/clk/mediatek/clk-mt6735-imgsys.c
@@ -41,6 +41,7 @@ static const struct of_device_id of_match_mt6735_imgsys[] = {
{ .compatible = "mediatek,mt6735-imgsys", .data = &imgsys_clks },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, of_match_mt6735_imgsys);
static struct platform_driver clk_mt6735_imgsys = {
.probe = mtk_clk_simple_probe,
diff --git a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c
index 1f5aedddf209d..8a18ee244a4de 100644
--- a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c
+++ b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c
@@ -45,6 +45,7 @@ static const struct of_device_id of_match_mt6735_mfgcfg[] = {
{ .compatible = "mediatek,mt6735-mfgcfg", .data = &mfgcfg_clks },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, of_match_mt6735_mfgcfg);
static struct platform_driver clk_mt6735_mfgcfg = {
.probe = mtk_clk_simple_probe,
diff --git a/drivers/clk/mediatek/clk-mt6735-vdecsys.c b/drivers/clk/mediatek/clk-mt6735-vdecsys.c
index 8817085fc1db4..d53ebf92e878d 100644
--- a/drivers/clk/mediatek/clk-mt6735-vdecsys.c
+++ b/drivers/clk/mediatek/clk-mt6735-vdecsys.c
@@ -63,6 +63,7 @@ static const struct of_device_id of_match_mt6735_vdecsys[] = {
{ .compatible = "mediatek,mt6735-vdecsys", .data = &vdecsys_clks },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, of_match_mt6735_vdecsys);
static struct platform_driver clk_mt6735_vdecsys = {
.probe = mtk_clk_simple_probe,
diff --git a/drivers/clk/mediatek/clk-mt6735-vencsys.c b/drivers/clk/mediatek/clk-mt6735-vencsys.c
index 8dec7f98492ac..64ba9da9fd427 100644
--- a/drivers/clk/mediatek/clk-mt6735-vencsys.c
+++ b/drivers/clk/mediatek/clk-mt6735-vencsys.c
@@ -37,6 +37,7 @@ static const struct of_device_id of_match_mt6735_vencsys[] = {
{ .compatible = "mediatek,mt6735-vencsys", .data = &vencsys_clks },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, of_match_mt6735_vencsys);
static struct platform_driver clk_mt6735_vencsys = {
.probe = mtk_clk_simple_probe,
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
index 4b9dcb910b03f..a806789ae27c1 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -808,7 +808,7 @@ static const char * const i2s5_m_ck_parents[] = {
"aud_2_sel"
};
-static const struct mtk_composite top_aud_muxes[] = {
+static const struct mtk_composite top_aud_muxes_divs[] = {
MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
0x320, 8, 1),
MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
@@ -821,9 +821,7 @@ static const struct mtk_composite top_aud_muxes[] = {
0x320, 12, 1),
MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
0x328, 20, 1),
-};
-static struct mtk_composite top_aud_divs[] = {
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
0x320, 2, 0x324, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
@@ -1211,125 +1209,47 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
};
-static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
-
- mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- ARRAY_SIZE(apmixed_clks), clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-}
-
-static int clk_mt6779_top_probe(struct platform_device *pdev)
-{
- void __iomem *base;
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
- clk_data);
-
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-
- mtk_clk_register_muxes(&pdev->dev, top_muxes,
- ARRAY_SIZE(top_muxes), node,
- &mt6779_clk_lock, clk_data);
-
- mtk_clk_register_composites(&pdev->dev, top_aud_muxes,
- ARRAY_SIZE(top_aud_muxes), base,
- &mt6779_clk_lock, clk_data);
-
- mtk_clk_register_composites(&pdev->dev, top_aud_divs,
- ARRAY_SIZE(top_aud_divs), base,
- &mt6779_clk_lock, clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-}
-
-static const struct of_device_id of_match_clk_mt6779[] = {
- {
- .compatible = "mediatek,mt6779-apmixed",
- .data = clk_mt6779_apmixed_probe,
- }, {
- .compatible = "mediatek,mt6779-topckgen",
- .data = clk_mt6779_top_probe,
- }, {
- /* sentinel */
- }
+static const struct mtk_clk_desc apmixed_desc = {
+ .clks = apmixed_clks,
+ .num_clks = ARRAY_SIZE(apmixed_clks),
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
};
-static int clk_mt6779_probe(struct platform_device *pdev)
-{
- int (*clk_probe)(struct platform_device *pdev);
- int r;
-
- clk_probe = of_device_get_match_data(&pdev->dev);
- if (!clk_probe)
- return -EINVAL;
-
- r = clk_probe(pdev);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
-}
+static const struct mtk_clk_desc topck_desc = {
+ .fixed_clks = top_fixed_clks,
+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
+ .factor_clks = top_divs,
+ .num_factor_clks = ARRAY_SIZE(top_divs),
+ .mux_clks = top_muxes,
+ .num_mux_clks = ARRAY_SIZE(top_muxes),
+ .composite_clks = top_aud_muxes_divs,
+ .num_composite_clks = ARRAY_SIZE(top_aud_muxes_divs),
+ .clk_lock = &mt6779_clk_lock,
+};
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
};
-static const struct of_device_id of_match_clk_mt6779_infra[] = {
+static const struct of_device_id of_match_clk_mt6779[] = {
+ { .compatible = "mediatek,mt6779-apmixed", .data = &apmixed_desc },
+ { .compatible = "mediatek,mt6779-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779);
-static struct platform_driver clk_mt6779_infra_drv = {
+static struct platform_driver clk_mt6779_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
- .driver = {
- .name = "clk-mt6779-infra",
- .of_match_table = of_match_clk_mt6779_infra,
- },
-};
-
-static struct platform_driver clk_mt6779_drv = {
- .probe = clk_mt6779_probe,
.driver = {
.name = "clk-mt6779",
.of_match_table = of_match_clk_mt6779,
},
};
-
-static int __init clk_mt6779_init(void)
-{
- int ret = platform_driver_register(&clk_mt6779_drv);
-
- if (ret)
- return ret;
- return platform_driver_register(&clk_mt6779_infra_drv);
-}
-
-arch_initcall(clk_mt6779_init);
+module_platform_driver(clk_mt6779_drv);
MODULE_DESCRIPTION("MediaTek MT6779 main clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
index 123d5d7fea855..239a3f5e17604 100644
--- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
@@ -175,6 +175,8 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
dev_dbg(dev, "Performing initial setup for MD1\n");
clk_mt6795_apmixed_setup_md1(base);
+ platform_set_drvdata(pdev, clk_data);
+
return 0;
unregister_ref2usb:
diff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/mediatek/clk-mt6795-infracfg.c
index e4559569f5b02..6aefc577ece5c 100644
--- a/drivers/clk/mediatek/clk-mt6795-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c
@@ -8,7 +8,6 @@
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "reset.h"
@@ -77,74 +76,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
};
+static const struct mtk_clk_desc infra_desc = {
+ .clks = infra_gates,
+ .num_clks = ARRAY_SIZE(infra_gates),
+ .cpumuxes = cpu_muxes,
+ .num_cpumuxes = ARRAY_SIZE(cpu_muxes),
+ .rst_desc = &clk_rst_desc,
+};
+
static const struct of_device_id of_match_clk_mt6795_infracfg[] = {
- { .compatible = "mediatek,mt6795-infracfg" },
+ { .compatible = "mediatek,mt6795-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_infracfg);
-static int clk_mt6795_infracfg_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- void __iomem *base;
- int ret;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
- if (ret)
- goto free_clk_data;
-
- ret = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
- ARRAY_SIZE(infra_gates), clk_data);
- if (ret)
- goto free_clk_data;
-
- ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
- ARRAY_SIZE(cpu_muxes), clk_data);
- if (ret)
- goto unregister_gates;
-
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (ret)
- goto unregister_cpumuxes;
-
- return 0;
-
-unregister_cpumuxes:
- mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
-unregister_gates:
- mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
-free_clk_data:
- mtk_free_clk_data(clk_data);
- return ret;
-}
-
-static void clk_mt6795_infracfg_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
- mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt6795_infracfg_drv = {
.driver = {
.name = "clk-mt6795-infracfg",
.of_match_table = of_match_clk_mt6795_infracfg,
},
- .probe = clk_mt6795_infracfg_probe,
- .remove = clk_mt6795_infracfg_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt6795_infracfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediatek/clk-mt6795-pericfg.c
index d48240eb2a67c..53c79e830b6a1 100644
--- a/drivers/clk/mediatek/clk-mt6795-pericfg.c
+++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c
@@ -85,75 +85,28 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_idx_map_nr = ARRAY_SIZE(peri_idx_map),
};
+static const struct mtk_clk_desc pericfg_desc = {
+ .clks = peri_gates,
+ .num_clks = ARRAY_SIZE(peri_gates),
+ .composite_clks = peri_clks,
+ .num_composite_clks = ARRAY_SIZE(peri_clks),
+ .rst_desc = &clk_rst_desc,
+ .clk_lock = &mt6795_peri_clk_lock,
+};
+
static const struct of_device_id of_match_clk_mt6795_pericfg[] = {
- { .compatible = "mediatek,mt6795-pericfg" },
+ { .compatible = "mediatek,mt6795-pericfg", .data = &pericfg_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_pericfg);
-static int clk_mt6795_pericfg_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- void __iomem *base;
- int ret;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
- if (ret)
- goto free_clk_data;
-
- ret = mtk_clk_register_gates(&pdev->dev, node, peri_gates,
- ARRAY_SIZE(peri_gates), clk_data);
- if (ret)
- goto free_clk_data;
-
- ret = mtk_clk_register_composites(&pdev->dev, peri_clks,
- ARRAY_SIZE(peri_clks), base,
- &mt6795_peri_clk_lock, clk_data);
- if (ret)
- goto unregister_gates;
-
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (ret)
- goto unregister_composites;
-
- return 0;
-
-unregister_composites:
- mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
-unregister_gates:
- mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
-free_clk_data:
- mtk_free_clk_data(clk_data);
- return ret;
-}
-
-static void clk_mt6795_pericfg_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
- mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt6795_pericfg_drv = {
.driver = {
.name = "clk-mt6795-pericfg",
.of_match_table = of_match_clk_mt6795_pericfg,
},
- .probe = clk_mt6795_pericfg_probe,
- .remove = clk_mt6795_pericfg_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt6795_pericfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index ebf850ac57f54..1934420375e88 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -379,29 +379,13 @@ static const struct mtk_composite top_muxes[] = {
0x0104, 1, 2),
};
-static int mtk_topckgen_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- void __iomem *base;
- struct device_node *node = pdev->dev.of_node;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
- clk_data);
-
- mtk_clk_register_composites(&pdev->dev, top_muxes,
- ARRAY_SIZE(top_muxes), base,
- &mt6797_clk_lock, clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-}
+static const struct mtk_clk_desc topckgen_desc = {
+ .factor_clks = top_fixed_divs,
+ .num_factor_clks = ARRAY_SIZE(top_fixed_divs),
+ .composite_clks = top_muxes,
+ .num_composite_clks = ARRAY_SIZE(top_muxes),
+ .clk_lock = &mt6797_clk_lock,
+};
static const struct mtk_gate_regs infra0_cg_regs = {
.set_ofs = 0x0080,
@@ -539,58 +523,12 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
};
-static struct clk_hw_onecell_data *infra_clk_data;
-
-static void mtk_infrasys_init_early(struct device_node *node)
-{
- int r, i;
-
- if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
- if (!infra_clk_data)
- return;
-
- for (i = 0; i < CLK_INFRA_NR; i++)
- infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
- }
-
- mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
- infra_clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- infra_clk_data);
- if (r)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-}
-
-CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
- mtk_infrasys_init_early);
-
-static int mtk_infrasys_init(struct platform_device *pdev)
-{
- int i;
- struct device_node *node = pdev->dev.of_node;
-
- if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
- if (!infra_clk_data)
- return -ENOMEM;
- } else {
- for (i = 0; i < CLK_INFRA_NR; i++) {
- if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
- infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
- }
- }
-
- mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- ARRAY_SIZE(infra_clks), infra_clk_data);
- mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
- infra_clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- infra_clk_data);
-}
+static const struct mtk_clk_desc infracfg_desc = {
+ .clks = infra_clks,
+ .num_clks = ARRAY_SIZE(infra_clks),
+ .factor_clks = infra_fixed_divs,
+ .num_factor_clks = ARRAY_SIZE(infra_fixed_divs),
+};
#define MT6797_PLL_FMAX (3000UL * MHZ)
@@ -646,68 +584,36 @@ static const struct mtk_pll_data plls[] = {
0x2B4, 4, 0x2BC, 0x2B8, 0),
};
-static int mtk_apmixedsys_init(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-}
+static const struct mtk_clk_desc apmixedsys_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+};
static const struct of_device_id of_match_clk_mt6797[] = {
{
.compatible = "mediatek,mt6797-topckgen",
- .data = mtk_topckgen_init,
+ .data = &topckgen_desc,
}, {
.compatible = "mediatek,mt6797-infracfg",
- .data = mtk_infrasys_init,
+ .data = &infracfg_desc,
}, {
.compatible = "mediatek,mt6797-apmixedsys",
- .data = mtk_apmixedsys_init,
+ .data = &apmixedsys_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6797);
-static int clk_mt6797_probe(struct platform_device *pdev)
-{
- int (*clk_init)(struct platform_device *);
- int r;
-
- clk_init = of_device_get_match_data(&pdev->dev);
- if (!clk_init)
- return -EINVAL;
-
- r = clk_init(pdev);
- if (r)
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
-}
-
static struct platform_driver clk_mt6797_drv = {
- .probe = clk_mt6797_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6797",
.of_match_table = of_match_clk_mt6797,
},
};
-
-static int __init clk_mt6797_init(void)
-{
- return platform_driver_register(&clk_mt6797_drv);
-}
-
-arch_initcall(clk_mt6797_init);
+module_platform_driver(clk_mt6797_drv);
MODULE_DESCRIPTION("MediaTek MT6797 main clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c
index 8a29eaab0cfcb..e9f731eadace1 100644
--- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c
@@ -80,64 +80,22 @@ static const struct mtk_gate apmixed_clks[] = {
GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
};
-static int clk_mt7622_apmixed_probe(struct platform_device *pdev)
-{
- void __iomem *base;
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- struct device *dev = &pdev->dev;
- int ret;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
- if (ret)
- return ret;
-
- ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- ARRAY_SIZE(apmixed_clks), clk_data);
- if (ret)
- goto unregister_plls;
-
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (ret)
- goto unregister_gates;
-
- return 0;
-
-unregister_gates:
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
-unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-
- return ret;
-}
-
-static void clk_mt7622_apmixed_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-}
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+ .clks = apmixed_clks,
+ .num_clks = ARRAY_SIZE(apmixed_clks),
+};
static const struct of_device_id of_match_clk_mt7622_apmixed[] = {
- { .compatible = "mediatek,mt7622-apmixedsys" },
+ { .compatible = "mediatek,mt7622-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_apmixed);
static struct platform_driver clk_mt7622_apmixed_drv = {
- .probe = clk_mt7622_apmixed_probe,
- .remove = clk_mt7622_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7622-apmixed",
.of_match_table = of_match_clk_mt7622_apmixed,
diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c
index a4ea5e20efa29..6004c58be1b5b 100644
--- a/drivers/clk/mediatek/clk-mt7622-aud.c
+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -110,38 +110,9 @@ static const struct mtk_gate audio_clks[] = {
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
+ .populate_children = true,
};
-static int clk_mt7622_aud_probe(struct platform_device *pdev)
-{
- int r;
-
- r = mtk_clk_simple_probe(pdev);
- if (r) {
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
- return r;
- }
-
- r = devm_of_platform_populate(&pdev->dev);
- if (r)
- goto err_plat_populate;
-
- return 0;
-
-err_plat_populate:
- mtk_clk_simple_remove(pdev);
- return r;
-}
-
-static void clk_mt7622_aud_remove(struct platform_device *pdev)
-{
- of_platform_depopulate(&pdev->dev);
- mtk_clk_simple_remove(pdev);
-}
-
static const struct of_device_id of_match_clk_mt7622_aud[] = {
{ .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
{ /* sentinel */ }
@@ -149,8 +120,8 @@ static const struct of_device_id of_match_clk_mt7622_aud[] = {
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_aud);
static struct platform_driver clk_mt7622_aud_drv = {
- .probe = clk_mt7622_aud_probe,
- .remove = clk_mt7622_aud_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7622-aud",
.of_match_table = of_match_clk_mt7622_aud,
diff --git a/drivers/clk/mediatek/clk-mt7622-infracfg.c b/drivers/clk/mediatek/clk-mt7622-infracfg.c
index cfdf3b07c3e06..2e463d1481d02 100644
--- a/drivers/clk/mediatek/clk-mt7622-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7622-infracfg.c
@@ -9,7 +9,6 @@
#include <linux/module.h>
#include <linux/platform_device.h>
-#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "reset.h"
@@ -51,74 +50,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
};
+static const struct mtk_clk_desc infra_desc = {
+ .clks = infra_clks,
+ .num_clks = ARRAY_SIZE(infra_clks),
+ .cpumuxes = cpu_muxes,
+ .num_cpumuxes = ARRAY_SIZE(cpu_muxes),
+ .rst_desc = &clk_rst_desc,
+};
+
static const struct of_device_id of_match_clk_mt7622_infracfg[] = {
- { .compatible = "mediatek,mt7622-infracfg" },
+ { .compatible = "mediatek,mt7622-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg);
-static int clk_mt7622_infracfg_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- void __iomem *base;
- int ret;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
- if (ret)
- goto free_clk_data;
-
- ret = mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- ARRAY_SIZE(infra_clks), clk_data);
- if (ret)
- goto free_clk_data;
-
- ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
- ARRAY_SIZE(cpu_muxes), clk_data);
- if (ret)
- goto unregister_gates;
-
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (ret)
- goto unregister_cpumuxes;
-
- return 0;
-
-unregister_cpumuxes:
- mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
-unregister_gates:
- mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
-free_clk_data:
- mtk_free_clk_data(clk_data);
- return ret;
-}
-
-static void clk_mt7622_infracfg_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
- mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt7622_infracfg_drv = {
.driver = {
.name = "clk-mt7622-infracfg",
.of_match_table = of_match_clk_mt7622_infracfg,
},
- .probe = clk_mt7622_infracfg_probe,
- .remove = clk_mt7622_infracfg_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7622_infracfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediatek/clk-mt7981-apmixed.c
index 851d0bc7840ac..810395aff2538 100644
--- a/drivers/clk/mediatek/clk-mt7981-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
@@ -59,45 +59,26 @@ static const struct mtk_pll_data plls[] = {
0x0278, 4, 0, 0x027C, 0),
};
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+};
+
static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
- { .compatible = "mediatek,mt7981-apmixedsys", },
+ { .compatible = "mediatek,mt7981-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_apmixed);
-static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_apmixed_data;
- }
- return r;
-
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
static struct platform_driver clk_mt7981_apmixed_drv = {
- .probe = clk_mt7981_apmixed_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7981-apmixed",
.of_match_table = of_match_clk_mt7981_apmixed,
},
};
-builtin_platform_driver(clk_mt7981_apmixed_drv);
+module_platform_driver(clk_mt7981_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT7981 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c
index af3e002bbfb76..6df3e9555e4e2 100644
--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
@@ -57,45 +57,26 @@ static const struct mtk_pll_data plls[] = {
0x0278, 4, 0, 0x027c, 0),
};
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+};
+
static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
- { .compatible = "mediatek,mt7986-apmixedsys", },
+ { .compatible = "mediatek,mt7986-apmixedsys", .data = &apmixed_desc },
{ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_apmixed);
-static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_apmixed_data;
- }
- return r;
-
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
static struct platform_driver clk_mt7986_apmixed_drv = {
- .probe = clk_mt7986_apmixed_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7986-apmixed",
.of_match_table = of_match_clk_mt7986_apmixed,
},
};
-builtin_platform_driver(clk_mt7986_apmixed_drv);
+module_platform_driver(clk_mt7986_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT7986 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediatek/clk-mt7988-apmixed.c
index 416a4b88d100b..f7bb00e7d17a1 100644
--- a/drivers/clk/mediatek/clk-mt7988-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
@@ -71,46 +71,26 @@ static const struct mtk_pll_data plls[] = {
0, 0x0318, 0, 0x0314),
};
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+};
+
static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
- { .compatible = "mediatek,mt7988-apmixedsys" },
+ { .compatible = "mediatek,mt7988-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
-
-static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
- if (!clk_data)
- return -ENOMEM;
-
- r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
- if (r)
- goto free_apmixed_data;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_plls;
-
- return r;
-
-unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_apmixed);
static struct platform_driver clk_mt7988_apmixed_drv = {
- .probe = clk_mt7988_apmixed_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7988-apmixed",
.of_match_table = of_match_clk_mt7988_apmixed,
},
};
-builtin_platform_driver(clk_mt7988_apmixed_drv);
+module_platform_driver(clk_mt7988_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT7988 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c
index 19e4ee489ec39..fe868417de482 100644
--- a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c
@@ -47,54 +47,20 @@ static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
};
-static int clk_mt8135_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int ret;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- ret = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls),
- clk_data);
- if (ret)
- goto free_clk_data;
-
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (ret)
- goto unregister_plls;
-
- return 0;
-
-unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-free_clk_data:
- mtk_free_clk_data(clk_data);
-
- return ret;
-}
-
-static void clk_mt8135_apmixed_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
- mtk_free_clk_data(clk_data);
-}
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+};
static const struct of_device_id of_match_clk_mt8135_apmixed[] = {
- { .compatible = "mediatek,mt8135-apmixedsys" },
+ { .compatible = "mediatek,mt8135-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8135_apmixed);
static struct platform_driver clk_mt8135_apmixed_drv = {
- .probe = clk_mt8135_apmixed_probe,
- .remove = clk_mt8135_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8135-apmixed",
.of_match_table = of_match_clk_mt8135_apmixed,
diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c
index fb6c21bbeef81..2b1d1de74cdbd 100644
--- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c
@@ -89,44 +89,13 @@ static const struct mtk_clk_divider adj_divs[] = {
0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO),
};
-static int clk_mt8167_apmixed_probe(struct platform_device *pdev)
-{
- void __iomem *base;
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- struct device *dev = &pdev->dev;
- int ret;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_devm_alloc_clk_data(dev, MT8167_CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
- if (ret)
- return ret;
-
- ret = mtk_clk_register_dividers(dev, adj_divs, ARRAY_SIZE(adj_divs), base,
- &mt8167_apmixed_clk_lock, clk_data);
- if (ret)
- goto unregister_plls;
-
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (ret)
- goto unregister_dividers;
-
- return 0;
-
-unregister_dividers:
- mtk_clk_unregister_dividers(adj_divs, ARRAY_SIZE(adj_divs), clk_data);
-unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-
- return ret;
-}
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+ .divider_clks = adj_divs,
+ .num_divider_clks = ARRAY_SIZE(adj_divs),
+ .clk_lock = &mt8167_apmixed_clk_lock,
+};
static const struct of_device_id of_match_clk_mt8167_apmixed[] = {
{ .compatible = "mediatek,mt8167-apmixedsys" },
@@ -135,13 +104,14 @@ static const struct of_device_id of_match_clk_mt8167_apmixed[] = {
MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_apmixed);
static struct platform_driver clk_mt8167_apmixed_drv = {
- .probe = clk_mt8167_apmixed_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8167-apmixed",
.of_match_table = of_match_clk_mt8167_apmixed,
},
};
-builtin_platform_driver(clk_mt8167_apmixed_drv)
+module_platform_driver(clk_mt8167_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT8167 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
index d7d416172ab35..65dc4489a09c8 100644
--- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
@@ -179,6 +179,8 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
if (r)
goto unregister_ref2usb;
+ platform_set_drvdata(pdev, clk_data);
+
return 0;
unregister_ref2usb:
diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/mediatek/clk-mt8173-infracfg.c
index fa2d1d557e04f..fdd994736e833 100644
--- a/drivers/clk/mediatek/clk-mt8173-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c
@@ -17,22 +17,20 @@
GATE_MTK(_id, _name, _parent, &infra_cg_regs, \
_shift, &mtk_clk_gate_ops_setclr)
-static struct clk_hw_onecell_data *infra_clk_data;
-
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
};
-static const char * const ca53_parents[] __initconst = {
+static const char * const ca53_parents[] = {
"clk26m",
"armca7pll",
"mainpll",
"univpll"
};
-static const char * const ca72_parents[] __initconst = {
+static const char * const ca72_parents[] = {
"clk26m",
"armca15pll",
"mainpll",
@@ -44,7 +42,7 @@ static const struct mtk_composite cpu_muxes[] = {
MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
};
-static const struct mtk_fixed_factor infra_early_divs[] = {
+static const struct mtk_fixed_factor infra_divs[] = {
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
@@ -70,93 +68,29 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
};
+static const struct mtk_clk_desc infracfg_desc = {
+ .clks = infra_gates,
+ .num_clks = ARRAY_SIZE(infra_gates),
+ .factor_clks = infra_divs,
+ .num_factor_clks = ARRAY_SIZE(infra_divs),
+ .cpumuxes = cpu_muxes,
+ .num_cpumuxes = ARRAY_SIZE(cpu_muxes),
+ .rst_desc = &clk_rst_desc,
+};
+
static const struct of_device_id of_match_clk_mt8173_infracfg[] = {
- { .compatible = "mediatek,mt8173-infracfg" },
+ { .compatible = "mediatek,mt8173-infracfg", .data = &infracfg_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_infracfg);
-static void clk_mt8173_infra_init_early(struct device_node *node)
-{
- int i;
-
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- if (!infra_clk_data)
- return;
-
- for (i = 0; i < CLK_INFRA_NR_CLK; i++)
- infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
-
- mtk_clk_register_factors(infra_early_divs,
- ARRAY_SIZE(infra_early_divs), infra_clk_data);
-
- of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data);
-}
-CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
- clk_mt8173_infra_init_early);
-
-static int clk_mt8173_infracfg_probe(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- int r, i;
-
- if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- if (!infra_clk_data)
- return -ENOMEM;
- } else {
- for (i = 0; i < CLK_INFRA_NR_CLK; i++)
- if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
- infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
- }
-
- r = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
- ARRAY_SIZE(infra_gates), infra_clk_data);
- if (r)
- return r;
-
- r = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
- ARRAY_SIZE(cpu_muxes), infra_clk_data);
- if (r)
- goto unregister_gates;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data);
- if (r)
- goto unregister_cpumuxes;
-
- r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
- if (r)
- goto unregister_clk_hw;
-
- return 0;
-
-unregister_clk_hw:
- of_clk_del_provider(node);
-unregister_cpumuxes:
- mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_data);
-unregister_gates:
- mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), infra_clk_data);
- return r;
-}
-
-static void clk_mt8173_infracfg_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
- mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt8173_infracfg_drv = {
.driver = {
.name = "clk-mt8173-infracfg",
.of_match_table = of_match_clk_mt8173_infracfg,
},
- .probe = clk_mt8173_infracfg_probe,
- .remove = clk_mt8173_infracfg_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8173_infracfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
index 6242d4f5376e7..deb96537a3aba 100644
--- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
@@ -139,59 +139,28 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
};
-static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
-{
- void __iomem *base;
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- struct device *dev = &pdev->dev;
- int ret;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
- if (ret)
- return ret;
-
- ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- ARRAY_SIZE(apmixed_clks), clk_data);
- if (ret)
- goto unregister_plls;
-
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (ret)
- goto unregister_gates;
-
- return 0;
-
-unregister_gates:
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
-unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-
- return ret;
-}
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+ .clks = apmixed_clks,
+ .num_clks = ARRAY_SIZE(apmixed_clks),
+};
static const struct of_device_id of_match_clk_mt8183_apmixed[] = {
- { .compatible = "mediatek,mt8183-apmixedsys" },
+ { .compatible = "mediatek,mt8183-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_apmixed);
static struct platform_driver clk_mt8183_apmixed_drv = {
- .probe = clk_mt8183_apmixed_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-apmixed",
.of_match_table = of_match_clk_mt8183_apmixed,
},
};
-builtin_platform_driver(clk_mt8183_apmixed_drv)
+module_platform_driver(clk_mt8183_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT8183 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c
index 011d329ad30e9..0a53b0408dccf 100644
--- a/drivers/clk/mediatek/clk-mt8183-audio.c
+++ b/drivers/clk/mediatek/clk-mt8183-audio.c
@@ -70,29 +70,9 @@ static const struct mtk_gate audio_clks[] = {
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
+ .populate_children = true,
};
-static int clk_mt8183_audio_probe(struct platform_device *pdev)
-{
- int r;
-
- r = mtk_clk_simple_probe(pdev);
- if (r)
- return r;
-
- r = devm_of_platform_populate(&pdev->dev);
- if (r)
- mtk_clk_simple_remove(pdev);
-
- return r;
-}
-
-static void clk_mt8183_audio_remove(struct platform_device *pdev)
-{
- of_platform_depopulate(&pdev->dev);
- mtk_clk_simple_remove(pdev);
-}
-
static const struct of_device_id of_match_clk_mt8183_audio[] = {
{ .compatible = "mediatek,mt8183-audiosys", .data = &audio_desc },
{ /* sentinel */ }
@@ -100,8 +80,8 @@ static const struct of_device_id of_match_clk_mt8183_audio[] = {
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_audio);
static struct platform_driver clk_mt8183_audio_drv = {
- .probe = clk_mt8183_audio_probe,
- .remove = clk_mt8183_audio_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-audio",
.of_match_table = of_match_clk_mt8183_audio,
diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
index d35dd2632e43a..b674b1e581a52 100644
--- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
@@ -132,60 +132,23 @@ static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),
};
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+ .fhctl_node = "mediatek,mt8186-fhctl",
+ .pllfhs = pllfhs,
+ .num_pllfhs = ARRAY_SIZE(pllfhs),
+};
+
static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
- { .compatible = "mediatek,mt8186-apmixedsys", },
+ { .compatible = "mediatek,mt8186-apmixedsys", .data = &apmixed_desc },
{}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_apmixed);
-static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- const u8 *fhctl_node = "mediatek,mt8186-fhctl";
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
-
- r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
- pllfhs, ARRAY_SIZE(pllfhs), clk_data);
- if (r)
- goto free_apmixed_data;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_plls;
-
- platform_set_drvdata(pdev, clk_data);
-
- return r;
-
-unregister_plls:
- mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
- ARRAY_SIZE(pllfhs), clk_data);
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static void clk_mt8186_apmixed_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
- ARRAY_SIZE(pllfhs), clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt8186_apmixed_drv = {
- .probe = clk_mt8186_apmixed_probe,
- .remove = clk_mt8186_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-apmixed",
.of_match_table = of_match_clk_mt8186_apmixed,
diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
index 48a2f61d4b77e..3937d93cac346 100644
--- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
@@ -89,62 +89,22 @@ static const struct mtk_pll_data plls[] = {
0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
};
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+ .clks = apmixed_clks,
+ .num_clks = ARRAY_SIZE(apmixed_clks),
+};
+
static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
- { .compatible = "mediatek,mt8188-apmixedsys" },
+ { .compatible = "mediatek,mt8188-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_apmixed);
-static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
- if (r)
- goto free_apmixed_data;
-
- r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- ARRAY_SIZE(apmixed_clks), clk_data);
- if (r)
- goto unregister_plls;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_gates;
-
- platform_set_drvdata(pdev, clk_data);
-
- return 0;
-
-unregister_gates:
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
-unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static void clk_mt8188_apmixed_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt8188_apmixed_drv = {
- .probe = clk_mt8188_apmixed_probe,
- .remove = clk_mt8188_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-apmixed",
.of_match_table = of_match_clk_mt8188_apmixed,
diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
index b0563a285bd66..92593370f23b1 100644
--- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
@@ -143,70 +143,29 @@ static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154),
};
+static const struct mtk_clk_desc apmixed_desc = {
+ .clks = apmixed_clks,
+ .num_clks = ARRAY_SIZE(apmixed_clks),
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+ .fhctl_node = "mediatek,mt8192-fhctl",
+ .pllfhs = pllfhs,
+ .num_pllfhs = ARRAY_SIZE(pllfhs),
+};
+
static const struct of_device_id of_match_clk_mt8192_apmixed[] = {
- { .compatible = "mediatek,mt8192-apmixedsys" },
+ { .compatible = "mediatek,mt8192-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_apmixed);
-static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- const u8 *fhctl_node = "mediatek,mt8192-fhctl";
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
-
- r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
- pllfhs, ARRAY_SIZE(pllfhs), clk_data);
- if (r)
- goto free_clk_data;
-
- r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- ARRAY_SIZE(apmixed_clks), clk_data);
- if (r)
- goto unregister_plls;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_gates;
-
- return r;
-
-unregister_gates:
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
-unregister_plls:
- mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
- ARRAY_SIZE(pllfhs), clk_data);
-free_clk_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static void clk_mt8192_apmixed_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
- mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
- ARRAY_SIZE(pllfhs), clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt8192_apmixed_drv = {
.driver = {
.name = "clk-mt8192-apmixed",
.of_match_table = of_match_clk_mt8192_apmixed,
},
- .probe = clk_mt8192_apmixed_probe,
- .remove = clk_mt8192_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8192_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT8192 apmixed clocks driver");
diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c
index f3ebf8713fbb7..8625f656a2e44 100644
--- a/drivers/clk/mediatek/clk-mt8192-aud.c
+++ b/drivers/clk/mediatek/clk-mt8192-aud.c
@@ -80,29 +80,9 @@ static const struct mtk_gate aud_clks[] = {
static const struct mtk_clk_desc aud_desc = {
.clks = aud_clks,
.num_clks = ARRAY_SIZE(aud_clks),
+ .populate_children = true,
};
-static int clk_mt8192_aud_probe(struct platform_device *pdev)
-{
- int r;
-
- r = mtk_clk_simple_probe(pdev);
- if (r)
- return r;
-
- r = devm_of_platform_populate(&pdev->dev);
- if (r)
- mtk_clk_simple_remove(pdev);
-
- return r;
-}
-
-static void clk_mt8192_aud_remove(struct platform_device *pdev)
-{
- of_platform_depopulate(&pdev->dev);
- mtk_clk_simple_remove(pdev);
-}
-
static const struct of_device_id of_match_clk_mt8192_aud[] = {
{ .compatible = "mediatek,mt8192-audsys", .data = &aud_desc },
{ /* sentinel */ }
@@ -110,8 +90,8 @@ static const struct of_device_id of_match_clk_mt8192_aud[] = {
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_aud);
static struct platform_driver clk_mt8192_aud_drv = {
- .probe = clk_mt8192_aud_probe,
- .remove = clk_mt8192_aud_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-aud",
.of_match_table = of_match_clk_mt8192_aud,
diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
index a120c33055474..fc60cd4d93824 100644
--- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
@@ -161,68 +161,25 @@ static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
};
+static const struct mtk_clk_desc apmixed_desc = {
+ .clks = apmixed_clks,
+ .num_clks = ARRAY_SIZE(apmixed_clks),
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+ .fhctl_node = "mediatek,mt8195-fhctl",
+ .pllfhs = pllfhs,
+ .num_pllfhs = ARRAY_SIZE(pllfhs),
+};
+
static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
{ .compatible = "mediatek,mt8195-apmixedsys", },
{}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apmixed);
-static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- const u8 *fhctl_node = "mediatek,mt8195-fhctl";
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
-
- r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
- pllfhs, ARRAY_SIZE(pllfhs), clk_data);
- if (r)
- goto free_apmixed_data;
-
- r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- ARRAY_SIZE(apmixed_clks), clk_data);
- if (r)
- goto unregister_plls;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_gates;
-
- platform_set_drvdata(pdev, clk_data);
-
- return r;
-
-unregister_gates:
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
-unregister_plls:
- mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
- ARRAY_SIZE(pllfhs), clk_data);
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static void clk_mt8195_apmixed_remove(struct platform_device *pdev)
-{
- struct device_node *node = pdev->dev.of_node;
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
-
- of_clk_del_provider(node);
- mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
- mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
- ARRAY_SIZE(pllfhs), clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt8195_apmixed_drv = {
- .probe = clk_mt8195_apmixed_probe,
- .remove = clk_mt8195_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-apmixed",
.of_match_table = of_match_clk_mt8195_apmixed,
diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
index a2d98ed58e348..36d358141ecb1 100644
--- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
+++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
@@ -56,55 +56,20 @@ static const struct mtk_pll_data apusys_plls[] = {
PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x03c),
};
-static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(CLK_APUSYS_PLL_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- r = mtk_clk_register_plls(&pdev->dev, apusys_plls,
- ARRAY_SIZE(apusys_plls), clk_data);
- if (r)
- goto free_apusys_pll_data;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_plls;
-
- platform_set_drvdata(pdev, clk_data);
-
- return r;
-
-unregister_plls:
- mtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
-free_apusys_pll_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static void clk_mt8195_apusys_pll_remove(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
- struct device_node *node = pdev->dev.of_node;
-
- of_clk_del_provider(node);
- mtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
- mtk_free_clk_data(clk_data);
-}
+static const struct mtk_clk_desc apu_pll_desc = {
+ .plls = apusys_plls,
+ .num_plls = ARRAY_SIZE(apusys_plls),
+};
static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = {
- { .compatible = "mediatek,mt8195-apusys_pll", },
+ { .compatible = "mediatek,mt8195-apusys_pll", .data = &apu_pll_desc },
{}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apusys_pll);
static struct platform_driver clk_mt8195_apusys_pll_drv = {
- .probe = clk_mt8195_apusys_pll_probe,
- .remove = clk_mt8195_apusys_pll_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-apusys_pll",
.of_match_table = of_match_clk_mt8195_apusys_pll,
diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c
index c4ebb0170b82b..a20fa02070a88 100644
--- a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c
@@ -86,11 +86,6 @@
.ops = &mtk_pll_fenc_clr_set_ops, \
}
-struct mtk_pll_desc {
- const struct mtk_pll_data *clks;
- size_t num_clks;
-};
-
static const struct mtk_pll_data apmixed_plls[] = {
PLL_FENC(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, FENC_STATUS_CON0,
7, PLL_AO, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22, 0),
@@ -110,9 +105,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
0, 0, SGMIIPLL_CON1, 24, SGMIIPLL_CON1, 0, 22, 7),
};
-static const struct mtk_pll_desc apmixed_desc = {
- .clks = apmixed_plls,
- .num_clks = ARRAY_SIZE(apmixed_plls),
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = apmixed_plls,
+ .num_plls = ARRAY_SIZE(apmixed_plls),
};
static const struct mtk_pll_data apmixed2_plls[] = {
@@ -132,57 +127,11 @@ static const struct mtk_pll_data apmixed2_plls[] = {
0, 0, TVDPLL3_CON1, 24, TVDPLL3_CON1, 0, 22, 6),
};
-static const struct mtk_pll_desc apmixed2_desc = {
- .clks = apmixed2_plls,
- .num_clks = ARRAY_SIZE(apmixed2_plls),
+static const struct mtk_clk_desc apmixed2_desc = {
+ .plls = apmixed2_plls,
+ .num_plls = ARRAY_SIZE(apmixed2_plls),
};
-static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- const struct mtk_pll_desc *mcd;
- int r;
-
- mcd = device_get_match_data(&pdev->dev);
- if (!mcd)
- return -EINVAL;
-
- clk_data = mtk_alloc_clk_data(mcd->num_clks);
- if (!clk_data)
- return -ENOMEM;
-
- r = mtk_clk_register_plls(&pdev->dev, mcd->clks, mcd->num_clks,
- clk_data);
- if (r)
- goto free_apmixed_data;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_plls;
-
- platform_set_drvdata(pdev, clk_data);
-
- return r;
-
-unregister_plls:
- mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static void clk_mt8196_apmixed_remove(struct platform_device *pdev)
-{
- const struct mtk_pll_desc *mcd = device_get_match_data(&pdev->dev);
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
- struct device_node *node = pdev->dev.of_node;
-
- of_clk_del_provider(node);
- mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static const struct of_device_id of_match_clk_mt8196_apmixed[] = {
{ .compatible = "mediatek,mt8196-apmixedsys", .data = &apmixed_desc },
{ .compatible = "mediatek,mt8196-apmixedsys-gp2",
@@ -192,8 +141,8 @@ static const struct of_device_id of_match_clk_mt8196_apmixed[] = {
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_apmixed);
static struct platform_driver clk_mt8196_apmixed_drv = {
- .probe = clk_mt8196_apmixed_probe,
- .remove = clk_mt8196_apmixed_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-apmixed",
.of_match_table = of_match_clk_mt8196_apmixed,
diff --git a/drivers/clk/mediatek/clk-mt8196-mcu.c b/drivers/clk/mediatek/clk-mt8196-mcu.c
index 13642fc673c26..e392408c93b28 100644
--- a/drivers/clk/mediatek/clk-mt8196-mcu.c
+++ b/drivers/clk/mediatek/clk-mt8196-mcu.c
@@ -68,29 +68,44 @@
.pcwibits = MT8196_INTEGER_BITS, \
}
-static const struct mtk_pll_data cpu_bl_plls[] = {
- PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0,
- 0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22),
+static const struct mtk_clk_desc cpu_bl_plls = {
+ .plls = (const struct mtk_pll_data[]){
+ PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0,
+ 0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22),
+ },
+ .num_plls = 1,
};
-static const struct mtk_pll_data cpu_b_plls[] = {
- PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0,
- PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22),
+static const struct mtk_clk_desc cpu_b_plls = {
+ .plls = (const struct mtk_pll_data[]){
+ PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0,
+ PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22),
+ },
+ .num_plls = 1,
};
-static const struct mtk_pll_data cpu_ll_plls[] = {
- PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0,
- 0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22),
+static const struct mtk_clk_desc cpu_ll_plls = {
+ .plls = (const struct mtk_pll_data[]){
+ PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0,
+ 0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22),
+ },
+ .num_plls = 1,
};
-static const struct mtk_pll_data cci_plls[] = {
- PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,
- BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22),
+static const struct mtk_clk_desc cci_plls = {
+ .plls = (const struct mtk_pll_data[]){
+ PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,
+ BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22),
+ },
+ .num_plls = 1,
};
-static const struct mtk_pll_data ptp_plls[] = {
- PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO,
- BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22),
+static const struct mtk_clk_desc ptp_plls = {
+ .plls = (const struct mtk_pll_data[]){
+ PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO,
+ BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22),
+ },
+ .num_plls = 1,
};
static const struct of_device_id of_match_clk_mt8196_mcu[] = {
@@ -106,56 +121,9 @@ static const struct of_device_id of_match_clk_mt8196_mcu[] = {
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mcu);
-static int clk_mt8196_mcu_probe(struct platform_device *pdev)
-{
- const struct mtk_pll_data *plls;
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- const int num_plls = 1;
- int r;
-
- plls = of_device_get_match_data(&pdev->dev);
- if (!plls)
- return -EINVAL;
-
- clk_data = mtk_alloc_clk_data(num_plls);
- if (!clk_data)
- return -ENOMEM;
-
- r = mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data);
- if (r)
- goto free_clk_data;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_plls;
-
- platform_set_drvdata(pdev, clk_data);
-
- return r;
-
-unregister_plls:
- mtk_clk_unregister_plls(plls, num_plls, clk_data);
-free_clk_data:
- mtk_free_clk_data(clk_data);
-
- return r;
-}
-
-static void clk_mt8196_mcu_remove(struct platform_device *pdev)
-{
- const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
- struct device_node *node = pdev->dev.of_node;
-
- of_clk_del_provider(node);
- mtk_clk_unregister_plls(plls, 1, clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt8196_mcu_drv = {
- .probe = clk_mt8196_mcu_probe,
- .remove = clk_mt8196_mcu_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-mcu",
.of_match_table = of_match_clk_mt8196_mcu,
diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/clk-mt8196-mfg.c
index a317183f1681b..a209162f62075 100644
--- a/drivers/clk/mediatek/clk-mt8196-mfg.c
+++ b/drivers/clk/mediatek/clk-mt8196-mfg.c
@@ -61,22 +61,31 @@
.parent_name = "mfg_eb", \
}
-static const struct mtk_pll_data mfg_ao_plls[] = {
- PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0,
- PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
- MFGPLL_CON1, 0, 22),
+static const struct mtk_clk_desc mfg_ao_plls = {
+ .plls = (const struct mtk_pll_data[]){
+ PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0,
+ MFGPLL_CON0, 0, 0, PLL_PARENT_EN, BIT(0),
+ MFGPLL_CON1, 24, 0, 0, 0, MFGPLL_CON1, 0, 22),
+ },
+ .num_plls = 1,
};
-static const struct mtk_pll_data mfgsc0_ao_plls[] = {
- PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
- MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24,
- 0, 0, 0, MFGPLL_SC0_CON1, 0, 22),
+static const struct mtk_clk_desc mfgsc0_ao_plls = {
+ .plls = (const struct mtk_pll_data[]){
+ PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
+ MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0),
+ MFGPLL_SC0_CON1, 24, 0, 0, 0, MFGPLL_SC0_CON1, 0, 22),
+ },
+ .num_plls = 1,
};
-static const struct mtk_pll_data mfgsc1_ao_plls[] = {
- PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
- MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24,
- 0, 0, 0, MFGPLL_SC1_CON1, 0, 22),
+static const struct mtk_clk_desc mfgsc1_ao_plls = {
+ .plls = (const struct mtk_pll_data[]){
+ PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
+ MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0),
+ MFGPLL_SC1_CON1, 24, 0, 0, 0, MFGPLL_SC1_CON1, 0, 22),
+ },
+ .num_plls = 1,
};
static const struct of_device_id of_match_clk_mt8196_mfg[] = {
@@ -90,56 +99,9 @@ static const struct of_device_id of_match_clk_mt8196_mfg[] = {
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mfg);
-static int clk_mt8196_mfg_probe(struct platform_device *pdev)
-{
- const struct mtk_pll_data *plls;
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- const int num_plls = 1;
- int r;
-
- plls = of_device_get_match_data(&pdev->dev);
- if (!plls)
- return -EINVAL;
-
- clk_data = mtk_alloc_clk_data(num_plls);
- if (!clk_data)
- return -ENOMEM;
-
- r = mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data);
- if (r)
- goto free_clk_data;
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
- goto unregister_plls;
-
- platform_set_drvdata(pdev, clk_data);
-
- return r;
-
-unregister_plls:
- mtk_clk_unregister_plls(plls, num_plls, clk_data);
-free_clk_data:
- mtk_free_clk_data(clk_data);
-
- return r;
-}
-
-static void clk_mt8196_mfg_remove(struct platform_device *pdev)
-{
- const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
- struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
- struct device_node *node = pdev->dev.of_node;
-
- of_clk_del_provider(node);
- mtk_clk_unregister_plls(plls, 1, clk_data);
- mtk_free_clk_data(clk_data);
-}
-
static struct platform_driver clk_mt8196_mfg_drv = {
- .probe = clk_mt8196_mfg_probe,
- .remove = clk_mt8196_mfg_remove,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-mfg",
.of_match_table = of_match_clk_mt8196_mfg,
diff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c
index 2a6206cae2f08..2fb09e7acde75 100644
--- a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c
@@ -71,52 +71,26 @@ static const struct mtk_pll_data plls[] = {
31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
};
-static int clk_mt8516_apmixed_probe(struct platform_device *pdev)
-{
- void __iomem *base;
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- struct device *dev = &pdev->dev;
- int ret;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
- if (!clk_data)
- return -ENOMEM;
-
- ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
- if (ret)
- return ret;
-
- ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (ret)
- goto unregister_plls;
-
- return 0;
-
-unregister_plls:
- mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-
- return ret;
-}
+static const struct mtk_clk_desc apmixed_desc = {
+ .plls = plls,
+ .num_plls = ARRAY_SIZE(plls),
+};
static const struct of_device_id of_match_clk_mt8516_apmixed[] = {
- { .compatible = "mediatek,mt8516-apmixedsys" },
+ { .compatible = "mediatek,mt8516-apmixedsys", .data = &apmixed_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_apmixed);
static struct platform_driver clk_mt8516_apmixed_drv = {
- .probe = clk_mt8516_apmixed_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8516-apmixed",
.of_match_table = of_match_clk_mt8516_apmixed,
},
};
-builtin_platform_driver(clk_mt8516_apmixed_drv)
+module_platform_driver(clk_mt8516_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT8516 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 3dfdd3a422f80..e80ae497fadd4 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -12,6 +12,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
@@ -19,6 +20,12 @@
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
+#include "clk-cpumux.h"
+#include "clk-pll.h"
+
+#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL)
+#include "clk-fhctl.h"
+#endif
const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
EXPORT_SYMBOL_GPL(cg_regs_dummy);
@@ -485,7 +492,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
}
/* Composite and divider clocks needs us to pass iomem pointer */
- if (mcd->composite_clks || mcd->divider_clks) {
+ if (mcd->composite_clks || mcd->divider_clks || mcd->plls) {
if (!mcd->shared_io)
base = devm_platform_ioremap_resource(pdev, 0);
else
@@ -513,6 +520,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
num_clks = mcd->num_clks + mcd->num_composite_clks;
num_clks += mcd->num_fixed_clks + mcd->num_factor_clks;
num_clks += mcd->num_mux_clks + mcd->num_divider_clks;
+ num_clks += mcd->num_cpumuxes + mcd->num_plls;
clk_data = mtk_alloc_clk_data(num_clks);
if (!clk_data) {
@@ -520,11 +528,29 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
goto free_base;
}
+ if (mcd->plls) {
+ if (mcd->fhctl_node) {
+#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL)
+ fhctl_parse_dt(mcd->fhctl_node, mcd->pllfhs,
+ mcd->num_pllfhs);
+ r = mtk_clk_register_pllfhs(&pdev->dev, mcd->plls,
+ mcd->num_plls, mcd->pllfhs,
+ mcd->num_pllfhs, clk_data);
+#endif
+ } else {
+ r = mtk_clk_register_plls(&pdev->dev, mcd->plls,
+ mcd->num_plls, clk_data);
+ }
+
+ if (r)
+ goto free_data;
+ }
+
if (mcd->fixed_clks) {
r = mtk_clk_register_fixed_clks(mcd->fixed_clks,
mcd->num_fixed_clks, clk_data);
if (r)
- goto free_data;
+ goto unregister_plls;
}
if (mcd->factor_clks) {
@@ -542,6 +568,13 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
goto unregister_factors;
}
+ if (mcd->cpumuxes) {
+ r = mtk_clk_register_cpumuxes(&pdev->dev, node, mcd->cpumuxes,
+ mcd->num_cpumuxes, clk_data);
+ if (r)
+ goto unregister_muxes;
+ }
+
if (mcd->composite_clks) {
/* We don't check composite_lock because it's optional */
r = mtk_clk_register_composites(&pdev->dev,
@@ -549,7 +582,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
mcd->num_composite_clks,
base, mcd->clk_lock, clk_data);
if (r)
- goto unregister_muxes;
+ goto unregister_cpumuxes;
}
if (mcd->divider_clks) {
@@ -592,6 +625,12 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
if (mcd->need_runtime_pm)
pm_runtime_put(&pdev->dev);
+ if (mcd->populate_children) {
+ r = devm_of_platform_populate(&pdev->dev);
+ if (r)
+ goto unregister_clks;
+ }
+
return r;
unregister_clks:
@@ -605,6 +644,10 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
if (mcd->composite_clks)
mtk_clk_unregister_composites(mcd->composite_clks,
mcd->num_composite_clks, clk_data);
+unregister_cpumuxes:
+ if (mcd->cpumuxes)
+ mtk_clk_unregister_cpumuxes(mcd->cpumuxes,
+ mcd->num_cpumuxes, clk_data);
unregister_muxes:
if (mcd->mux_clks)
mtk_clk_unregister_muxes(mcd->mux_clks,
@@ -617,6 +660,18 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
if (mcd->fixed_clks)
mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
mcd->num_fixed_clks, clk_data);
+unregister_plls:
+ if (mcd->plls) {
+ if (mcd->fhctl_node)
+#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL)
+ mtk_clk_unregister_pllfhs(mcd->plls, mcd->num_plls,
+ mcd->pllfhs, mcd->num_pllfhs,
+ clk_data);
+#endif
+ else
+ mtk_clk_unregister_plls(mcd->plls, mcd->num_plls,
+ clk_data);
+ }
free_data:
mtk_free_clk_data(clk_data);
free_base:
@@ -643,6 +698,9 @@ static void __mtk_clk_simple_remove(struct platform_device *pdev,
if (mcd->composite_clks)
mtk_clk_unregister_composites(mcd->composite_clks,
mcd->num_composite_clks, clk_data);
+ if (mcd->cpumuxes)
+ mtk_clk_unregister_cpumuxes(mcd->cpumuxes,
+ mcd->num_cpumuxes, clk_data);
if (mcd->mux_clks)
mtk_clk_unregister_muxes(mcd->mux_clks,
mcd->num_mux_clks, clk_data);
@@ -652,6 +710,18 @@ static void __mtk_clk_simple_remove(struct platform_device *pdev,
if (mcd->fixed_clks)
mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
mcd->num_fixed_clks, clk_data);
+ if (mcd->plls) {
+ if (mcd->fhctl_node)
+#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL)
+ mtk_clk_unregister_pllfhs(mcd->plls, mcd->num_plls,
+ mcd->pllfhs, mcd->num_pllfhs,
+ clk_data);
+#endif
+ else
+ mtk_clk_unregister_plls(mcd->plls, mcd->num_plls,
+ clk_data);
+ }
+
mtk_free_clk_data(clk_data);
}
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 5417b9264e6df..4e959ec68da07 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -15,6 +15,8 @@
#include "reset.h"
+#include "clk-fhctl.h"
+
#define MAX_MUX_GATE_BIT 31
#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
@@ -23,6 +25,7 @@
#define MTK_WAIT_HWV_DONE_US 30
struct platform_device;
+struct mtk_pll_data;
/*
* We need the clock IDs to start from zero but to maintain devicetree
@@ -252,6 +255,10 @@ struct mtk_clk_desc {
size_t num_factor_clks;
const struct mtk_mux *mux_clks;
size_t num_mux_clks;
+ const struct mtk_composite *cpumuxes;
+ size_t num_cpumuxes;
+ const struct mtk_pll_data *plls;
+ size_t num_plls;
const struct mtk_clk_rst_desc *rst_desc;
spinlock_t *clk_lock;
bool shared_io;
@@ -260,6 +267,11 @@ struct mtk_clk_desc {
unsigned int mfg_clk_idx;
bool need_runtime_pm;
+ bool populate_children;
+
+ const u8 *fhctl_node;
+ struct mtk_pllfh_data *pllfhs;
+ size_t num_pllfhs;
};
int mtk_clk_pdev_probe(struct platform_device *pdev);
|
| 3/2 | 2026/08/03 19:03 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 46521 output: 127 thoughts: 1175 Thoughts: **WorthFuzzing Assessment: The MediaTek Clock Driver Refactor** Okay, so this patch is touching the MediaTek clock driver subsystem. It seems like the core of the change revolves around refactoring the probe and remove functions for various clock drivers within the `drivers/clk/mediatek/` directory. They're making a common `mtk_clk_simple_probe` and `mtk_clk_simple_remove` function and using a `struct mtk_clk_desc` for each driver. Also, I see some Kconfig options are switching from `bool` to `tristate`, which means they can be built as modules. My immediate thought is, "Is this fuzzable?" The changes themselves look like straightforward refactoring, mostly moving data around. However, it *does* alter the initialization sequence of these clock drivers. Clock drivers are usually probed pretty early on during system boot or during device probe. Fuzzing them directly through system calls is unlikely, unless there's a user-space interface. Debugfs isn't mentioned here, so that's not the avenue. But, syzkaller *can* fuzz device probing, especially if it can inject devices. It does this with virtual devices or DT overlay, but it doesn't normally use DT overlays in the standard configuration. Now, these are MediaTek SoC clock drivers. They're platform drivers, matching on specific "compatible" strings in the device tree (like `"mediatek,mt2701-topckgen"`). In a virtualized environment like QEMU, the machine (e.g., `q35` or `virt` for ARM64) almost certainly won't have these specific MediaTek compatible strings in its device tree. My understanding is these drivers will *never* probe in a standard QEMU setup. Let me double-check. The drivers are registered as `module_platform_driver` or `builtin_platform_driver`. They *bind* to specific compatible strings. No matching DT node? No probe function called. Syzkaller doesn't seem to have a way (currently) to dynamically create platform devices with arbitrary compatible strings, unless it's a specific pseudo-device or part of the base DT. And being MediaTek-specific, they won't be in the generic `virt` machine DT. The prompt specifically says to return `WorthFuzzing=false` if the code paths are unreachable in virtualized environments like GCE or QEMU, even with emulated hardware. Since these are MediaTek SoC-specific clock drivers that require specific device tree nodes, and these nodes are *not* present in a generic QEMU/GCE environment, the modified code is unreachable. `WorthFuzzing` should be false. Just to be absolutely sure, let's see if any generic code is modified that could be reached. `drivers/clk/mediatek/clk-mtk.c` is updated, but it's only called by the MediaTek clock drivers' probe functions. If no MediaTek clock driver probes, `__mtk_clk_simple_probe` isn't executed. Nope, this is MediaTek specific, no cross-over. So, I'm going to return `WorthFuzzing=false`. The reasoning is that these are MediaTek SoC-specific clock drivers that rely on device tree nodes that are *absent* in generic virtualized environments like QEMU and GCE, rendering the changed code unreachable during standard fuzzing. My reasoning will be: "The patch refactors MediaTek SoC-specific clock drivers to use a common probe/remove infrastructure and changes some Kconfig options to tristate. These platform drivers bind to specific MediaTek compatible strings (e.g., "mediatek,mt2701-topckgen") which are not present in the device trees of generic virtualized environments like QEMU or GCE. Therefore, the modified code paths are impossible to reach during standard fuzzing." Okay, let's get the results set: `WorthFuzzing: false`. |
| 4/2 | 2026/08/03 19:03 | tool | set-results |
0mArgs:{
"EnableConfigs": [],
"FocusSymbols": [],
"Reasoning": "The patch refactors MediaTek SoC-specific clock drivers to use a common probe/remove infrastructure and changes several Kconfig options to tristate. These platform drivers bind to specific MediaTek compatible strings (e.g., \"mediatek,mt2701-topckgen\") which are not present in the device trees of generic virtualized environments like QEMU or GCE. Therefore, the modified code paths are impossible to reach and test during standard fuzzing.",
"WorthFuzzing": false
}Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch refactors MediaTek SoC-specific clock drivers to use a common probe/remove infrastructure and changes several Kconfig options to tristate. These platform drivers bind to specific MediaTek compatible strings (e.g., \"mediatek,mt2701-topckgen\") which are not present in the device trees of generic virtualized environments like QEMU or GCE. Therefore, the modified code paths are impossible to reach and test during standard fuzzing.",
"WorthFuzzing": false
} |
| Total Calls | Total Tokens | Avg Tokens | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|
| Total Calls | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|