AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/09/24 18:14	flow	patch-triage	1m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The patch modifies drivers/ptp/ptp_idt82p33.c, which is a device driver for Renesas/IDT 82P33xxx Synchronization Management Units (SMU) / PTP hardware clocks connected via I2C or SPI. This driver requires specific physical ASIC hardware that is not emulated in standard virtualized fuzzing environments (QEMU/GCE). The modified driver callbacks and teardown routines cannot be reached or executed during fuzzing.", "WorthFuzzing": false }
1/1	2026/09/24 18:14	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit 4cde60ecb0b7aeea0e4b6680040c174e5844776c\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Thu Sep 24 18:14:03 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c\nindex f01c50dfa44e8..ffc2ec1fc4bed 100644\n--- a/drivers/ptp/ptp_idt82p33.c\n+++ b/drivers/ptp/ptp_idt82p33.c\n@@ -918,6 +918,13 @@ static void idt82p33_ptp_clock_unregister_all(struct idt82p33 idt82p33)\n \tstruct idt82p33_channel channel;\n \tu8 i;\n \n+\tmutex_lock(idt82p33-\u003elock);\n+\tidt82p33-\u003estopping = true;\n+\tidt82p33-\u003eextts_mask = 0;\n+\tmutex_unlock(idt82p33-\u003elock);\n+\n+\tcancel_delayed_work_sync(\u0026idt82p33-\u003eextts_work);\n+\n \tfor (i = 0; i \u003c MAX_PHC_PLL; i++) {\n \t\tchannel = \u0026idt82p33-\u003echannel[i];\n \t\tcancel_delayed_work_sync(\u0026channel-\u003eadjtime_work);\n@@ -937,6 +944,10 @@ static int idt82p33_enable(struct ptp_clock_info ptp,\n \tint err = -EOPNOTSUPP;\n \n \tmutex_lock(idt82p33-\u003elock);\n+\tif (idt82p33-\u003estopping) {\n+\t\terr = -ENODEV;\n+\t\tgoto out;\n+\t}\n \n \tswitch (rq-\u003etype) {\n \tcase PTP_CLK_REQ_PEROUT:\n@@ -958,6 +969,7 @@ static int idt82p33_enable(struct ptp_clock_info ptp,\n \t\tbreak;\n \t}\n \n+out:\n \tmutex_unlock(idt82p33-\u003elock);\n \n \tif (err)\n@@ -1044,11 +1056,14 @@ static int idt82p33_adjtime(struct ptp_clock_info ptp, s64 delta_ns)\n \t\treturn -EBUSY;\n \n \tmutex_lock(idt82p33-\u003elock);\n+\tif (idt82p33-\u003estopping) {\n+\t\terr = -ENODEV;\n+\t\tgoto out;\n+\t}\n \n \tif (abs(delta_ns) \u003c phase_snap_threshold) {\n \t\terr = idt82p33_start_ddco(channel, delta_ns);\n-\t\tmutex_unlock(idt82p33-\u003elock);\n-\t\treturn err;\n+\t\tgoto out;\n \t}\n \n \t/ Use more accurate internal 1pps triggered write first /\n@@ -1056,6 +1071,7 @@ static int idt82p33_adjtime(struct ptp_clock_info ptp, s64 delta_ns)\n \tif (err \u0026\u0026 delta_ns \u003e IMMEDIATE_SNAP_THRESHOLD_NS)\n \t\terr = _idt82p33_adjtime_immediate(channel, delta_ns);\n \n+out:\n \tmutex_unlock(idt82p33-\u003elock);\n \n \tif (err)\n@@ -1342,6 +1358,8 @@ static void idt82p33_extts_check(struct work_struct work)\n \t\treturn;\n \n \tmutex_lock(idt82p33-\u003elock);\n+\tif (idt82p33-\u003estopping)\n+\t\tgoto out;\n \n \tfor (i = 0; i \u003c MAX_PHC_PLL; i++) {\n \t\tmask = 1 \u003c\u003c i;\n@@ -1367,6 +1385,7 @@ static void idt82p33_extts_check(struct work_struct work)\n \t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\n \t\t\t\t msecs_to_jiffies(EXTTS_PERIOD_MS));\n \n+out:\n \tmutex_unlock(idt82p33-\u003elock);\n }\n \n@@ -1442,8 +1461,6 @@ static void idt82p33_remove(struct platform_device pdev)\n {\n \tstruct idt82p33 idt82p33 = platform_get_drvdata(pdev);\n \n-\tcancel_delayed_work_sync(\u0026idt82p33-\u003eextts_work);\n-\n \tidt82p33_ptp_clock_unregister_all(idt82p33);\n }\n \ndiff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h\nindex 6a63c14b6966b..b88c921adaa91 100644\n--- a/drivers/ptp/ptp_idt82p33.h\n+++ b/drivers/ptp/ptp_idt82p33.h\n@@ -91,6 +91,7 @@ struct idt82p33 {\n \tu8\t\t\textts_mask;\n \tbool\t\t\textts_single_shot;\n \tstruct delayed_work\textts_work;\n+\tbool\t\t\tstopping;\n \t/* Remember the ptp channel to report extts /\n \tstruct idt82p33_channel\tevent_channel[MAX_PHC_PLL];\n \t/* Mutex to protect operations from being interrupted */\n" }
2/1	2026/09/24 18:14	agent	patch-evaluator	1m Model: core Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch modifies drivers/ptp/ptp_idt82p33.c, which is a device driver for Renesas/IDT 82P33xxx Synchronization Management Units (SMU) / PTP hardware clocks connected via I2C or SPI. This driver requires specific physical ASIC hardware that is not emulated in standard virtualized fuzzing environments (QEMU/GCE). The modified driver callbacks and teardown routines cannot be reached or executed during fuzzing.", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer and security engineer. Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on internal assumptions. You must actively use your code access tools to inspect the actual source code, callers, and surrounding context. ================================================================================ 1. CORE TRIAGE PHILOSOPHY ================================================================================ The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs, and newly triggered assertions introduced by the patch series. - REACHABILITY IS THE PRIMARY GATE: Fuzzing can only discover bugs in code that can actually execute in standard virtualized environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap). If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed, regardless of whether it adds assertions or complex logic. - DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS: Patch authors routinely label changes as "cleanups", "refactorings", or state "No functional change intended". Do NOT take these claims at face value. Code refactorings that rearrange logic, introduce helper functions, or alter state management in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs. If reachable executable code is modified or refactored, it MUST be fuzzed. - NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED: When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON, VM_WARN_ON, BUG_ON, lockdep_assert) in reachable code paths, it enforces new or stricter invariants. Even if the author believes the invariant always holds, fuzzing is essential to verify whether an unusual sequence of operations can violate it. ================================================================================ 2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA) ================================================================================ Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories: - Non-kernel and non-executable changes: * Modifications to Documentation/, comments, or spelling fixes. * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/) that do not affect the compiled kernel image (vmlinux) or kernel modules. * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints that do not alter control flow or data structures. * Build system or Kconfig changes that do not alter compiled C logic. - Structurally unreachable hardware: * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU. - Unreachable execution paths: * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during physical PCI hot-unplug or manual sysfs driver unbinding. * Code paths exclusive to architectures other than the target architecture. ================================================================================ 3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA) ================================================================================ Return WorthFuzzing=true whenever the patch touches reachable executable code, including: - Core Subsystems: * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/), BPF, scheduler, core networking, VFS, or syscall handling. - Refactorings and Code Cleanups: * Any restructuring of reachable data structures, helper abstractions, or algorithm flows. - Runtime Assertions and Defensive Checks: * Any introduction or alteration of assertions (WARN_ON, VM_WARN_ON, BUG_ON, etc.) in reachable paths. - Reachable Drivers and Protocols: Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.). ================================================================================ 4. EXTRACTING FocusSymbols (PREVENTING DILUTION) ================================================================================ When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer: - AVOID UBIQUITOUS LIFECYCLE HOT-PATHS: Do NOT list generic, ubiquitous functions called by almost every program in the corpus (including, but not limited to: general memory allocators and deallocators, page fault and trap handlers, or core synchronization primitives; this is not an exhaustive list). Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused", which severely dilutes fuzzing effort away from the actual changes. - TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS: List functions that specifically implement the logic being added or altered, or direct API entrypoints for the subsystem feature under review. - HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h): Compiler-inlined static functions (such as static inlines in mm/.h or include/linux/.h) lack distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters. If the changes are primarily in static inline helpers, identify non-static, feature-specific caller functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers). ================================================================================ 5. IDENTIFYING EnableConfigs ================================================================================ Identify any specific CONFIG_ options required to properly compile and reach the modified code: - Inspect Kconfig files and #ifdef guards; do not make assumptions. - Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed. - Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: Target architecture: amd64 For your convenience, here is the diff of the changes: commit 4cde60ecb0b7aeea0e4b6680040c174e5844776c Author: syz-cluster <triage@syzkaller.com> Date: Thu Sep 24 18:14:03 2026 +0000 syz-cluster: applied patch under review diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c index f01c50dfa44e8..ffc2ec1fc4bed 100644 --- a/drivers/ptp/ptp_idt82p33.c +++ b/drivers/ptp/ptp_idt82p33.c @@ -918,6 +918,13 @@ static void idt82p33_ptp_clock_unregister_all(struct idt82p33 idt82p33) struct idt82p33_channel channel; u8 i; + mutex_lock(idt82p33->lock); + idt82p33->stopping = true; + idt82p33->extts_mask = 0; + mutex_unlock(idt82p33->lock); + + cancel_delayed_work_sync(&idt82p33->extts_work); + for (i = 0; i < MAX_PHC_PLL; i++) { channel = &idt82p33->channel[i]; cancel_delayed_work_sync(&channel->adjtime_work); @@ -937,6 +944,10 @@ static int idt82p33_enable(struct ptp_clock_info ptp, int err = -EOPNOTSUPP; mutex_lock(idt82p33->lock); + if (idt82p33->stopping) { + err = -ENODEV; + goto out; + } switch (rq->type) { case PTP_CLK_REQ_PEROUT: @@ -958,6 +969,7 @@ static int idt82p33_enable(struct ptp_clock_info ptp, break; } +out: mutex_unlock(idt82p33->lock); if (err) @@ -1044,11 +1056,14 @@ static int idt82p33_adjtime(struct ptp_clock_info ptp, s64 delta_ns) return -EBUSY; mutex_lock(idt82p33->lock); + if (idt82p33->stopping) { + err = -ENODEV; + goto out; + } if (abs(delta_ns) < phase_snap_threshold) { err = idt82p33_start_ddco(channel, delta_ns); - mutex_unlock(idt82p33->lock); - return err; + goto out; } / Use more accurate internal 1pps triggered write first / @@ -1056,6 +1071,7 @@ static int idt82p33_adjtime(struct ptp_clock_info ptp, s64 delta_ns) if (err && delta_ns > IMMEDIATE_SNAP_THRESHOLD_NS) err = _idt82p33_adjtime_immediate(channel, delta_ns); +out: mutex_unlock(idt82p33->lock); if (err) @@ -1342,6 +1358,8 @@ static void idt82p33_extts_check(struct work_struct work) return; mutex_lock(idt82p33->lock); + if (idt82p33->stopping) + goto out; for (i = 0; i < MAX_PHC_PLL; i++) { mask = 1 << i; @@ -1367,6 +1385,7 @@ static void idt82p33_extts_check(struct work_struct work) schedule_delayed_work(&idt82p33->extts_work, msecs_to_jiffies(EXTTS_PERIOD_MS)); +out: mutex_unlock(idt82p33->lock); } @@ -1442,8 +1461,6 @@ static void idt82p33_remove(struct platform_device pdev) { struct idt82p33 idt82p33 = platform_get_drvdata(pdev); - cancel_delayed_work_sync(&idt82p33->extts_work); - idt82p33_ptp_clock_unregister_all(idt82p33); } diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h index 6a63c14b6966b..b88c921adaa91 100644 --- a/drivers/ptp/ptp_idt82p33.h +++ b/drivers/ptp/ptp_idt82p33.h @@ -91,6 +91,7 @@ struct idt82p33 { u8 extts_mask; bool extts_single_shot; struct delayed_work extts_work; + bool stopping; /* Remember the ptp channel to report extts / struct idt82p33_channel event_channel[MAX_PHC_PLL]; /* Mutex to protect operations from being interrupted */
3/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 4113 output: 30 thoughts: 146 Thoughts: Analyzing the Patch: Diving into the `ptp_idt82p33` Driver Okay, let's break this down. The patch focuses on modifications to `drivers/ptp/ptp_idt82p33.c` and its header file, which immediately signals we're dealing with a Precision Time Protocol (PTP) driver, specifically for the IDT82P33 chip. I need to understand the implications of these changes. First, I want to confirm my initial assumption. Is this a platform driver? Understanding how it's instantiated is crucial. I need to determine if this driver is relevant to my current development environment, or if it has some conditionality that prevents it being reached during testing. I need to quickly ascertain how it's probed and whether it's even possible to trigger it within a QEMU setup or other virtual environment. To get the essential information, I'll leverage my usual tools. I'll reach for either `grepper` to search the codebase for relevant function calls, probe functions, or device tree bindings related to the IDT82P33, or if necessary, I'll directly read the contents of the `ptp_idt82p33.c` file itself. This should quickly reveal the probing mechanism. I'll also check `drivers/ptp/Kconfig` to see if there are any conditional compilation flags or dependencies that might affect the driver's availability.
4/2	2026/09/24 18:14	tool	grepper	0m Args: { "Expression": "idt82p33", "PathPrefix": "drivers/ptp" } Results: { "Output": "\nFull output is too long, showing 500 out of 945 lines.\nUse more precise expression if possible.\n\ndrivers/ptp/Kconfig=152=config PTP_1588_CLOCK_IDT82P33\n--\ndrivers/ptp/Kconfig-161-\t To compile this driver as a module, choose M here: the module\ndrivers/ptp/Kconfig:162:\t will be called ptp_idt82p33.\ndrivers/ptp/Kconfig-163-\n--\ndrivers/ptp/Makefile=17=obj-$(CONFIG_PTP_1588_CLOCK_FC3W)\t+= ptp_fc3.o\ndrivers/ptp/Makefile:18:obj-$(CONFIG_PTP_1588_CLOCK_IDT82P33)\t+= ptp_idt82p33.o\ndrivers/ptp/Makefile-19-obj-$(CONFIG_PTP_1588_CLOCK_MOCK)\t+= ptp_mock.o\n--\ndrivers/ptp/ptp_idt82p33.c-18-#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/ptp/ptp_idt82p33.c:19:#include \u003clinux/mfd/idt82p33_reg.h\u003e\ndrivers/ptp/ptp_idt82p33.c-20-\ndrivers/ptp/ptp_idt82p33.c-21-#include \"ptp_private.h\"\ndrivers/ptp/ptp_idt82p33.c:22:#include \"ptp_idt82p33.h\"\ndrivers/ptp/ptp_idt82p33.c-23-\n--\ndrivers/ptp/ptp_idt82p33.c=41=static struct ptp_pin_desc pin_config[MAX_PHC_PLL][MAX_TRIG_CLK];\ndrivers/ptp/ptp_idt82p33.c-42-\ndrivers/ptp/ptp_idt82p33.c:43:static inline int idt82p33_read(struct idt82p33 idt82p33, u16 regaddr,\ndrivers/ptp/ptp_idt82p33.c-44-\t\t\t\tu8 buf, u16 count)\ndrivers/ptp/ptp_idt82p33.c-45-{\ndrivers/ptp/ptp_idt82p33.c:46:\treturn regmap_bulk_read(idt82p33-\u003eregmap, regaddr, buf, count);\ndrivers/ptp/ptp_idt82p33.c-47-}\ndrivers/ptp/ptp_idt82p33.c-48-\ndrivers/ptp/ptp_idt82p33.c:49:static inline int idt82p33_write(struct idt82p33 idt82p33, u16 regaddr,\ndrivers/ptp/ptp_idt82p33.c-50-\t\t\t\t u8 buf, u16 count)\ndrivers/ptp/ptp_idt82p33.c-51-{\ndrivers/ptp/ptp_idt82p33.c:52:\treturn regmap_bulk_write(idt82p33-\u003eregmap, regaddr, buf, count);\ndrivers/ptp/ptp_idt82p33.c-53-}\ndrivers/ptp/ptp_idt82p33.c-54-\ndrivers/ptp/ptp_idt82p33.c:55:static void idt82p33_byte_array_to_timespec(struct timespec64 ts,\ndrivers/ptp/ptp_idt82p33.c-56-\t\t\t\t\t u8 buf[TOD_BYTE_COUNT])\n--\ndrivers/ptp/ptp_idt82p33.c-77-\ndrivers/ptp/ptp_idt82p33.c:78:static void idt82p33_timespec_to_byte_array(struct timespec64 const ts,\ndrivers/ptp/ptp_idt82p33.c-79-\t\t\t\t\t u8 buf[TOD_BYTE_COUNT])\n--\ndrivers/ptp/ptp_idt82p33.c-98-\ndrivers/ptp/ptp_idt82p33.c:99:static int idt82p33_dpll_set_mode(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-100-\t\t\t\t enum pll_mode mode)\ndrivers/ptp/ptp_idt82p33.c-101-{\ndrivers/ptp/ptp_idt82p33.c:102:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-103-\tu8 dpll_mode;\n--\ndrivers/ptp/ptp_idt82p33.c-108-\ndrivers/ptp/ptp_idt82p33.c:109:\terr = idt82p33_read(idt82p33, channel-\u003edpll_mode_cnfg,\ndrivers/ptp/ptp_idt82p33.c-110-\t\t\t \u0026dpll_mode, sizeof(dpll_mode));\n--\ndrivers/ptp/ptp_idt82p33.c-117-\ndrivers/ptp/ptp_idt82p33.c:118:\terr = idt82p33_write(idt82p33, channel-\u003edpll_mode_cnfg,\ndrivers/ptp/ptp_idt82p33.c-119-\t\t\t \u0026dpll_mode, sizeof(dpll_mode));\n--\ndrivers/ptp/ptp_idt82p33.c-127-\ndrivers/ptp/ptp_idt82p33.c:128:static int idt82p33_set_tod_trigger(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-129-\t\t\t\t u8 trigger, bool write)\ndrivers/ptp/ptp_idt82p33.c-130-{\ndrivers/ptp/ptp_idt82p33.c:131:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-132-\tint err;\n--\ndrivers/ptp/ptp_idt82p33.c-137-\ndrivers/ptp/ptp_idt82p33.c:138:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c-139-\t\t\t \u0026cfg, sizeof(cfg));\n--\ndrivers/ptp/ptp_idt82p33.c-150-\ndrivers/ptp/ptp_idt82p33.c:151:\treturn idt82p33_write(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c-152-\t\t\t \u0026trigger, sizeof(trigger));\n--\ndrivers/ptp/ptp_idt82p33.c-154-\ndrivers/ptp/ptp_idt82p33.c:155:static int idt82p33_get_extts(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-156-\t\t\t struct timespec64 ts)\ndrivers/ptp/ptp_idt82p33.c-157-{\ndrivers/ptp/ptp_idt82p33.c:158:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-159-\tu8 buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-161-\ndrivers/ptp/ptp_idt82p33.c:162:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c-163-\n--\ndrivers/ptp/ptp_idt82p33.c-172-\ndrivers/ptp/ptp_idt82p33.c:173:\tidt82p33_byte_array_to_timespec(ts, buf);\ndrivers/ptp/ptp_idt82p33.c-174-\n--\ndrivers/ptp/ptp_idt82p33.c=204=static bool is_one_shot(u8 mask)\n--\ndrivers/ptp/ptp_idt82p33.c-212-\ndrivers/ptp/ptp_idt82p33.c:213:static int arm_tod_read_with_trigger(struct idt82p33_channel channel, u8 trigger)\ndrivers/ptp/ptp_idt82p33.c-214-{\ndrivers/ptp/ptp_idt82p33.c:215:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-216-\tu8 buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-219-\t/ Remember the current tod_sts before setting the trigger /\ndrivers/ptp/ptp_idt82p33.c:220:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c-221-\n--\ndrivers/ptp/ptp_idt82p33.c-226-\ndrivers/ptp/ptp_idt82p33.c:227:\terr = idt82p33_set_tod_trigger(channel, trigger, false);\ndrivers/ptp/ptp_idt82p33.c-228-\ndrivers/ptp/ptp_idt82p33.c-229-\tif (err)\ndrivers/ptp/ptp_idt82p33.c:230:\t\tdev_err(idt82p33-\u003edev, \"%s: err = %d\", __func__, err);\ndrivers/ptp/ptp_idt82p33.c-231-\n--\ndrivers/ptp/ptp_idt82p33.c-234-\ndrivers/ptp/ptp_idt82p33.c:235:static int idt82p33_extts_enable(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-236-\t\t\t\t struct ptp_clock_request rq, int on)\n--\ndrivers/ptp/ptp_idt82p33.c-238-\tu8 index = rq-\u003eextts.index;\ndrivers/ptp/ptp_idt82p33.c:239:\tstruct idt82p33 idt82p33;\ndrivers/ptp/ptp_idt82p33.c-240-\tu8 mask = 1 \u003c\u003c index;\n--\ndrivers/ptp/ptp_idt82p33.c-245-\ndrivers/ptp/ptp_idt82p33.c:246:\tidt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:247:\told_mask = idt82p33-\u003eextts_mask;\ndrivers/ptp/ptp_idt82p33.c-248-\n--\ndrivers/ptp/ptp_idt82p33.c-253-\t\t/* Return if it was already enabled /\ndrivers/ptp/ptp_idt82p33.c:254:\t\tif (idt82p33-\u003eextts_mask \u0026 mask)\ndrivers/ptp/ptp_idt82p33.c-255-\t\t\treturn 0;\n--\ndrivers/ptp/ptp_idt82p33.c-260-\t\tif (ref \u003c 0) {\ndrivers/ptp/ptp_idt82p33.c:261:\t\t\tdev_err(idt82p33-\u003edev, \"%s: No valid pin found for Pll%d!\\n\",\ndrivers/ptp/ptp_idt82p33.c-262-\t\t\t\t__func__, channel-\u003eplln);\n--\ndrivers/ptp/ptp_idt82p33.c-268-\t\tif (err) {\ndrivers/ptp/ptp_idt82p33.c:269:\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-270-\t\t\t\t\"%s: Unsupported ref %d!\\n\", __func__, ref);\n--\ndrivers/ptp/ptp_idt82p33.c-273-\ndrivers/ptp/ptp_idt82p33.c:274:\t\terr = arm_tod_read_with_trigger(\u0026idt82p33-\u003echannel[index], trigger);\ndrivers/ptp/ptp_idt82p33.c-275-\ndrivers/ptp/ptp_idt82p33.c-276-\t\tif (err == 0) {\ndrivers/ptp/ptp_idt82p33.c:277:\t\t\tidt82p33-\u003eextts_mask \|= mask;\ndrivers/ptp/ptp_idt82p33.c:278:\t\t\tidt82p33-\u003echannel[index].tod_trigger = trigger;\ndrivers/ptp/ptp_idt82p33.c:279:\t\t\tidt82p33-\u003eevent_channel[index] = channel;\ndrivers/ptp/ptp_idt82p33.c:280:\t\t\tidt82p33-\u003eextts_single_shot = is_one_shot(idt82p33-\u003eextts_mask);\ndrivers/ptp/ptp_idt82p33.c-281-\n--\ndrivers/ptp/ptp_idt82p33.c-284-\ndrivers/ptp/ptp_idt82p33.c:285:\t\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\ndrivers/ptp/ptp_idt82p33.c-286-\t\t\t\t\t msecs_to_jiffies(EXTTS_PERIOD_MS));\n--\ndrivers/ptp/ptp_idt82p33.c-288-\t} else {\ndrivers/ptp/ptp_idt82p33.c:289:\t\tidt82p33-\u003eextts_mask \u0026= ~mask;\ndrivers/ptp/ptp_idt82p33.c:290:\t\tidt82p33-\u003eextts_single_shot = is_one_shot(idt82p33-\u003eextts_mask);\ndrivers/ptp/ptp_idt82p33.c-291-\ndrivers/ptp/ptp_idt82p33.c:292:\t\tif (idt82p33-\u003eextts_mask == 0)\ndrivers/ptp/ptp_idt82p33.c:293:\t\t\tcancel_delayed_work(\u0026idt82p33-\u003eextts_work);\ndrivers/ptp/ptp_idt82p33.c-294-\t}\n--\ndrivers/ptp/ptp_idt82p33.c-298-\ndrivers/ptp/ptp_idt82p33.c:299:static int idt82p33_extts_check_channel(struct idt82p33 idt82p33, u8 todn)\ndrivers/ptp/ptp_idt82p33.c-300-{\ndrivers/ptp/ptp_idt82p33.c:301:\tstruct idt82p33_channel event_channel;\ndrivers/ptp/ptp_idt82p33.c-302-\tstruct ptp_clock_event event;\n--\ndrivers/ptp/ptp_idt82p33.c-305-\ndrivers/ptp/ptp_idt82p33.c:306:\terr = idt82p33_get_extts(\u0026idt82p33-\u003echannel[todn], \u0026ts);\ndrivers/ptp/ptp_idt82p33.c-307-\tif (err == 0) {\ndrivers/ptp/ptp_idt82p33.c:308:\t\tevent_channel = idt82p33-\u003eevent_channel[todn];\ndrivers/ptp/ptp_idt82p33.c-309-\t\tevent.type = PTP_CLOCK_EXTTS;\n--\ndrivers/ptp/ptp_idt82p33.c-317-\ndrivers/ptp/ptp_idt82p33.c:318:static u8 idt82p33_extts_enable_mask(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-319-\t\t\t\t u8 extts_mask, bool enable)\ndrivers/ptp/ptp_idt82p33.c-320-{\ndrivers/ptp/ptp_idt82p33.c:321:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-322-\tu8 trigger = channel-\u003etod_trigger;\n--\ndrivers/ptp/ptp_idt82p33.c-330-\tif (enable == false)\ndrivers/ptp/ptp_idt82p33.c:331:\t\tcancel_delayed_work_sync(\u0026idt82p33-\u003eextts_work);\ndrivers/ptp/ptp_idt82p33.c-332-\n--\ndrivers/ptp/ptp_idt82p33.c-339-\t\tif (enable) {\ndrivers/ptp/ptp_idt82p33.c:340:\t\t\terr = arm_tod_read_with_trigger(\u0026idt82p33-\u003echannel[i], trigger);\ndrivers/ptp/ptp_idt82p33.c-341-\t\t\tif (err)\ndrivers/ptp/ptp_idt82p33.c:342:\t\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-343-\t\t\t\t\t\"%s: Arm ToD read trigger failed, err = %d\",\n--\ndrivers/ptp/ptp_idt82p33.c-345-\t\t} else {\ndrivers/ptp/ptp_idt82p33.c:346:\t\t\terr = idt82p33_extts_check_channel(idt82p33, i);\ndrivers/ptp/ptp_idt82p33.c:347:\t\t\tif (err == 0 \u0026\u0026 idt82p33-\u003eextts_single_shot)\ndrivers/ptp/ptp_idt82p33.c-348-\t\t\t\t/ trigger happened so we won't re-enable it /\n--\ndrivers/ptp/ptp_idt82p33.c-353-\tif (enable)\ndrivers/ptp/ptp_idt82p33.c:354:\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\ndrivers/ptp/ptp_idt82p33.c-355-\t\t\t\t msecs_to_jiffies(EXTTS_PERIOD_MS));\n--\ndrivers/ptp/ptp_idt82p33.c-359-\ndrivers/ptp/ptp_idt82p33.c:360:static int _idt82p33_gettime(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-361-\t\t\t struct timespec64 ts)\ndrivers/ptp/ptp_idt82p33.c-362-{\ndrivers/ptp/ptp_idt82p33.c:363:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:364:\tu8 old_mask = idt82p33-\u003eextts_mask;\ndrivers/ptp/ptp_idt82p33.c-365-\tu8 buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-370-\tif (old_mask)\ndrivers/ptp/ptp_idt82p33.c:371:\t\tnew_mask = idt82p33_extts_enable_mask(channel, old_mask, false);\ndrivers/ptp/ptp_idt82p33.c-372-\ndrivers/ptp/ptp_idt82p33.c:373:\terr = idt82p33_set_tod_trigger(channel, HW_TOD_RD_TRIG_SEL_LSB_TOD_STS,\ndrivers/ptp/ptp_idt82p33.c-374-\t\t\t\t false);\n--\ndrivers/ptp/ptp_idt82p33.c-379-\ndrivers/ptp/ptp_idt82p33.c:380:\tif (idt82p33-\u003ecalculate_overhead_flag)\ndrivers/ptp/ptp_idt82p33.c:381:\t\tidt82p33-\u003estart_time = ktime_get_raw();\ndrivers/ptp/ptp_idt82p33.c-382-\ndrivers/ptp/ptp_idt82p33.c:383:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c-384-\n--\ndrivers/ptp/ptp_idt82p33.c-389-\tif (new_mask)\ndrivers/ptp/ptp_idt82p33.c:390:\t\tidt82p33_extts_enable_mask(channel, new_mask, true);\ndrivers/ptp/ptp_idt82p33.c-391-\ndrivers/ptp/ptp_idt82p33.c:392:\tidt82p33_byte_array_to_timespec(ts, buf);\ndrivers/ptp/ptp_idt82p33.c-393-\n--\ndrivers/ptp/ptp_idt82p33.c-402-\ndrivers/ptp/ptp_idt82p33.c:403:static int _idt82p33_settime(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-404-\t\t\t struct timespec64 const ts)\ndrivers/ptp/ptp_idt82p33.c-405-{\ndrivers/ptp/ptp_idt82p33.c:406:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-407-\tstruct timespec64 local_ts = ts;\n--\ndrivers/ptp/ptp_idt82p33.c-412-\ndrivers/ptp/ptp_idt82p33.c:413:\terr = idt82p33_set_tod_trigger(channel, HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,\ndrivers/ptp/ptp_idt82p33.c-414-\t\t\t\t true);\n--\ndrivers/ptp/ptp_idt82p33.c-419-\ndrivers/ptp/ptp_idt82p33.c:420:\tif (idt82p33-\u003ecalculate_overhead_flag) {\ndrivers/ptp/ptp_idt82p33.c-421-\t\tdynamic_overhead_ns = ktime_to_ns(ktime_get_raw())\ndrivers/ptp/ptp_idt82p33.c:422:\t\t\t\t\t- ktime_to_ns(idt82p33-\u003estart_time);\ndrivers/ptp/ptp_idt82p33.c-423-\n--\ndrivers/ptp/ptp_idt82p33.c-425-\ndrivers/ptp/ptp_idt82p33.c:426:\t\tidt82p33-\u003ecalculate_overhead_flag = 0;\ndrivers/ptp/ptp_idt82p33.c-427-\t}\ndrivers/ptp/ptp_idt82p33.c-428-\ndrivers/ptp/ptp_idt82p33.c:429:\tidt82p33_timespec_to_byte_array(\u0026local_ts, buf);\ndrivers/ptp/ptp_idt82p33.c-430-\n--\ndrivers/ptp/ptp_idt82p33.c-434-\tfor (i = 0; i \u003c TOD_BYTE_COUNT; i++) {\ndrivers/ptp/ptp_idt82p33.c:435:\t\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_cnfg + i,\ndrivers/ptp/ptp_idt82p33.c-436-\t\t\t\t \u0026buf[i], sizeof(buf[i]));\n--\ndrivers/ptp/ptp_idt82p33.c-443-\ndrivers/ptp/ptp_idt82p33.c:444:static int _idt82p33_adjtime_immediate(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-445-\t\t\t\t s64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c-446-{\ndrivers/ptp/ptp_idt82p33.c:447:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-448-\tstruct timespec64 ts;\n--\ndrivers/ptp/ptp_idt82p33.c-451-\ndrivers/ptp/ptp_idt82p33.c:452:\tidt82p33-\u003ecalculate_overhead_flag = 1;\ndrivers/ptp/ptp_idt82p33.c-453-\ndrivers/ptp/ptp_idt82p33.c:454:\terr = _idt82p33_gettime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c-455-\n--\ndrivers/ptp/ptp_idt82p33.c-459-\tnow_ns = timespec64_to_ns(\u0026ts);\ndrivers/ptp/ptp_idt82p33.c:460:\tnow_ns += delta_ns + idt82p33-\u003etod_write_overhead_ns;\ndrivers/ptp/ptp_idt82p33.c-461-\n--\ndrivers/ptp/ptp_idt82p33.c-463-\ndrivers/ptp/ptp_idt82p33.c:464:\terr = _idt82p33_settime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c-465-\n--\ndrivers/ptp/ptp_idt82p33.c-468-\ndrivers/ptp/ptp_idt82p33.c:469:static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-470-\t\t\t\t\t\ts64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c-471-{\ndrivers/ptp/ptp_idt82p33.c:472:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-473-\tchar buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-479-\ndrivers/ptp/ptp_idt82p33.c:480:\terr = _idt82p33_gettime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c-481-\n--\ndrivers/ptp/ptp_idt82p33.c-492-\tts = ns_to_timespec64(ns);\ndrivers/ptp/ptp_idt82p33.c:493:\tidt82p33_timespec_to_byte_array(\u0026ts, buf);\ndrivers/ptp/ptp_idt82p33.c-494-\n--\ndrivers/ptp/ptp_idt82p33.c-497-\t /\ndrivers/ptp/ptp_idt82p33.c:498:\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_cnfg, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c-499-\tif (err)\n--\ndrivers/ptp/ptp_idt82p33.c-506-\ndrivers/ptp/ptp_idt82p33.c:507:\treturn idt82p33_set_tod_trigger(channel, HW_TOD_TRIG_SEL_TOD_PPS, true);\ndrivers/ptp/ptp_idt82p33.c-508-}\ndrivers/ptp/ptp_idt82p33.c-509-\ndrivers/ptp/ptp_idt82p33.c:510:static void idt82p33_adjtime_workaround(struct work_struct work)\ndrivers/ptp/ptp_idt82p33.c-511-{\ndrivers/ptp/ptp_idt82p33.c:512:\tstruct idt82p33_channel channel = container_of(work,\ndrivers/ptp/ptp_idt82p33.c:513:\t\t\t\t\t\t\tstruct idt82p33_channel,\ndrivers/ptp/ptp_idt82p33.c-514-\t\t\t\t\t\t\tadjtime_work.work);\ndrivers/ptp/ptp_idt82p33.c:515:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-516-\ndrivers/ptp/ptp_idt82p33.c:517:\tmutex_lock(idt82p33-\u003elock);\ndrivers/ptp/ptp_idt82p33.c-518-\t/* Workaround for TOD-to-output alignment issue /\ndrivers/ptp/ptp_idt82p33.c:519:\t_idt82p33_adjtime_internal_triggered(channel, 0);\ndrivers/ptp/ptp_idt82p33.c:520:\tmutex_unlock(idt82p33-\u003elock);\ndrivers/ptp/ptp_idt82p33.c-521-}\ndrivers/ptp/ptp_idt82p33.c-522-\ndrivers/ptp/ptp_idt82p33.c:523:static int _idt82p33_adjfine(struct idt82p33_channel channel, long scaled_ppm)\ndrivers/ptp/ptp_idt82p33.c-524-{\ndrivers/ptp/ptp_idt82p33.c:525:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-526-\tunsigned char buf[5] = {0};\n--\ndrivers/ptp/ptp_idt82p33.c-551-\ndrivers/ptp/ptp_idt82p33.c:552:\terr = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);\ndrivers/ptp/ptp_idt82p33.c-553-\n--\ndrivers/ptp/ptp_idt82p33.c-556-\ndrivers/ptp/ptp_idt82p33.c:557:\terr = idt82p33_write(idt82p33, channel-\u003edpll_freq_cnfg,\ndrivers/ptp/ptp_idt82p33.c-558-\t\t\t buf, sizeof(buf));\n--\ndrivers/ptp/ptp_idt82p33.c-563-/ ppb = scaled_ppm * 125 / 2^13 /\ndrivers/ptp/ptp_idt82p33.c:564:static s32 idt82p33_ddco_scaled_ppm(long current_ppm, s32 ddco_ppb)\ndrivers/ptp/ptp_idt82p33.c-565-{\n--\ndrivers/ptp/ptp_idt82p33.c-578-\ndrivers/ptp/ptp_idt82p33.c:579:static int idt82p33_stop_ddco(struct idt82p33_channel channel)\ndrivers/ptp/ptp_idt82p33.c-580-{\n--\ndrivers/ptp/ptp_idt82p33.c-582-\ndrivers/ptp/ptp_idt82p33.c:583:\terr = _idt82p33_adjfine(channel, channel-\u003ecurrent_freq);\ndrivers/ptp/ptp_idt82p33.c-584-\tif (err)\n--\ndrivers/ptp/ptp_idt82p33.c-591-\ndrivers/ptp/ptp_idt82p33.c:592:static int idt82p33_start_ddco(struct idt82p33_channel channel, s32 delta_ns)\ndrivers/ptp/ptp_idt82p33.c-593-{\n--\ndrivers/ptp/ptp_idt82p33.c-612-\ndrivers/ptp/ptp_idt82p33.c:613:\terr = _idt82p33_adjfine(channel,\ndrivers/ptp/ptp_idt82p33.c:614:\t\t\t\tidt82p33_ddco_scaled_ppm(current_ppm, ppb));\ndrivers/ptp/ptp_idt82p33.c-615-\tif (err)\n--\ndrivers/ptp/ptp_idt82p33.c-625-\ndrivers/ptp/ptp_idt82p33.c:626:static int idt82p33_measure_one_byte_write_overhead(\ndrivers/ptp/ptp_idt82p33.c:627:\t\tstruct idt82p33_channel channel, s64 overhead_ns)\ndrivers/ptp/ptp_idt82p33.c-628-{\ndrivers/ptp/ptp_idt82p33.c:629:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-630-\tktime_t start, stop;\n--\ndrivers/ptp/ptp_idt82p33.c-642-\ndrivers/ptp/ptp_idt82p33.c:643:\t\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c-644-\t\t\t\t \u0026trigger, sizeof(trigger));\n--\ndrivers/ptp/ptp_idt82p33.c-658-\ndrivers/ptp/ptp_idt82p33.c:659:static int idt82p33_measure_one_byte_read_overhead(\ndrivers/ptp/ptp_idt82p33.c:660:\t\tstruct idt82p33_channel channel, s64 overhead_ns)\ndrivers/ptp/ptp_idt82p33.c-661-{\ndrivers/ptp/ptp_idt82p33.c:662:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-663-\tktime_t start, stop;\n--\ndrivers/ptp/ptp_idt82p33.c-675-\ndrivers/ptp/ptp_idt82p33.c:676:\t\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c-677-\t\t\t\t \u0026trigger, sizeof(trigger));\n--\ndrivers/ptp/ptp_idt82p33.c-691-\ndrivers/ptp/ptp_idt82p33.c:692:static int idt82p33_measure_tod_write_9_byte_overhead(\ndrivers/ptp/ptp_idt82p33.c:693:\t\tstruct idt82p33_channel channel)\ndrivers/ptp/ptp_idt82p33.c-694-{\ndrivers/ptp/ptp_idt82p33.c:695:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-696-\tu8 buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-702-\ttotal_ns = 0;\ndrivers/ptp/ptp_idt82p33.c:703:\tidt82p33-\u003etod_write_overhead_ns = 0;\ndrivers/ptp/ptp_idt82p33.c-704-\n--\ndrivers/ptp/ptp_idt82p33.c-710-\t\tfor (j = 0; j \u003c (TOD_BYTE_COUNT - 1); j++) {\ndrivers/ptp/ptp_idt82p33.c:711:\t\t\terr = idt82p33_write(idt82p33,\ndrivers/ptp/ptp_idt82p33.c-712-\t\t\t\t\t channel-\u003edpll_tod_cnfg + i,\n--\ndrivers/ptp/ptp_idt82p33.c-722-\ndrivers/ptp/ptp_idt82p33.c:723:\tidt82p33-\u003etod_write_overhead_ns = div_s64(total_ns,\ndrivers/ptp/ptp_idt82p33.c-724-\t\t\t\t\t\t MAX_MEASURMENT_COUNT);\n--\ndrivers/ptp/ptp_idt82p33.c-728-\ndrivers/ptp/ptp_idt82p33.c:729:static int idt82p33_measure_settime_gettime_gap_overhead(\ndrivers/ptp/ptp_idt82p33.c:730:\t\tstruct idt82p33_channel channel, s64 overhead_ns)\ndrivers/ptp/ptp_idt82p33.c-731-{\n--\ndrivers/ptp/ptp_idt82p33.c-737-\ndrivers/ptp/ptp_idt82p33.c:738:\terr = _idt82p33_settime(channel, \u0026ts1);\ndrivers/ptp/ptp_idt82p33.c-739-\n--\ndrivers/ptp/ptp_idt82p33.c-742-\ndrivers/ptp/ptp_idt82p33.c:743:\terr = _idt82p33_gettime(channel, \u0026ts2);\ndrivers/ptp/ptp_idt82p33.c-744-\n--\ndrivers/ptp/ptp_idt82p33.c-750-\ndrivers/ptp/ptp_idt82p33.c:751:static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel channel)\ndrivers/ptp/ptp_idt82p33.c-752-{\ndrivers/ptp/ptp_idt82p33.c-753-\ts64 trailing_overhead_ns, one_byte_write_ns, gap_ns, one_byte_read_ns;\ndrivers/ptp/ptp_idt82p33.c:754:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-755-\tint err;\ndrivers/ptp/ptp_idt82p33.c-756-\ndrivers/ptp/ptp_idt82p33.c:757:\tidt82p33-\u003etod_write_overhead_ns = 0;\ndrivers/ptp/ptp_idt82p33.c-758-\ndrivers/ptp/ptp_idt82p33.c:759:\terr = idt82p33_measure_settime_gettime_gap_overhead(channel, \u0026gap_ns);\ndrivers/ptp/ptp_idt82p33.c-760-\ndrivers/ptp/ptp_idt82p33.c-761-\tif (err) {\ndrivers/ptp/ptp_idt82p33.c:762:\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-763-\t\t\t\"Failed in %s with err %d!\\n\", __func__, err);\n--\ndrivers/ptp/ptp_idt82p33.c-766-\ndrivers/ptp/ptp_idt82p33.c:767:\terr = idt82p33_measure_one_byte_write_overhead(channel,\ndrivers/ptp/ptp_idt82p33.c-768-\t\t\t\t\t\t \u0026one_byte_write_ns);\n--\ndrivers/ptp/ptp_idt82p33.c-772-\ndrivers/ptp/ptp_idt82p33.c:773:\terr = idt82p33_measure_one_byte_read_overhead(channel,\ndrivers/ptp/ptp_idt82p33.c-774-\t\t\t\t\t\t \u0026one_byte_read_ns);\n--\ndrivers/ptp/ptp_idt82p33.c-778-\ndrivers/ptp/ptp_idt82p33.c:779:\terr = idt82p33_measure_tod_write_9_byte_overhead(channel);\ndrivers/ptp/ptp_idt82p33.c-780-\n--\ndrivers/ptp/ptp_idt82p33.c-786-\ndrivers/ptp/ptp_idt82p33.c:787:\tidt82p33-\u003etod_write_overhead_ns -= trailing_overhead_ns;\ndrivers/ptp/ptp_idt82p33.c-788-\n--\ndrivers/ptp/ptp_idt82p33.c-791-\ndrivers/ptp/ptp_idt82p33.c:792:static int idt82p33_check_and_set_masks(struct idt82p33 idt82p33,\ndrivers/ptp/ptp_idt82p33.c-793-\t\t\t\t\tu8 page,\n--\ndrivers/ptp/ptp_idt82p33.c-800-\t\tif ((val \u0026 0xfc) \|\| !(val \u0026 0x3)) {\ndrivers/ptp/ptp_idt82p33.c:801:\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-802-\t\t\t\t\"Invalid PLL mask 0x%x\\n\", val);\n--\ndrivers/ptp/ptp_idt82p33.c-804-\t\t} else {\ndrivers/ptp/ptp_idt82p33.c:805:\t\t\tidt82p33-\u003epll_mask = val;\ndrivers/ptp/ptp_idt82p33.c-806-\t\t}\n--\ndrivers/ptp/ptp_idt82p33.c-808-\t\toffset == PLL0_OUTMASK_ADDR_LO) {\ndrivers/ptp/ptp_idt82p33.c:809:\t\tidt82p33-\u003echannel[0].output_mask = val;\ndrivers/ptp/ptp_idt82p33.c-810-\t} else if (page == PLL1_OUTMASK_ADDR_HI \u0026\u0026\ndrivers/ptp/ptp_idt82p33.c-811-\t\toffset == PLL1_OUTMASK_ADDR_LO) {\ndrivers/ptp/ptp_idt82p33.c:812:\t\tidt82p33-\u003echannel[1].output_mask = val;\ndrivers/ptp/ptp_idt82p33.c-813-\t}\n--\ndrivers/ptp/ptp_idt82p33.c-817-\ndrivers/ptp/ptp_idt82p33.c:818:static void idt82p33_display_masks(struct idt82p33 idt82p33)\ndrivers/ptp/ptp_idt82p33.c-819-{\n--\ndrivers/ptp/ptp_idt82p33.c-821-\ndrivers/ptp/ptp_idt82p33.c:822:\tdev_info(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c:823:\t\t \"pllmask = 0x%02x\\n\", idt82p33-\u003epll_mask);\ndrivers/ptp/ptp_idt82p33.c-824-\n--\ndrivers/ptp/ptp_idt82p33.c-827-\ndrivers/ptp/ptp_idt82p33.c:828:\t\tif (mask \u0026 idt82p33-\u003epll_mask)\ndrivers/ptp/ptp_idt82p33.c:829:\t\t\tdev_info(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-830-\t\t\t\t \"PLL%d output_mask = 0x%04x\\n\",\ndrivers/ptp/ptp_idt82p33.c:831:\t\t\t\t i, idt82p33-\u003echannel[i].output_mask);\ndrivers/ptp/ptp_idt82p33.c-832-\t}\n--\ndrivers/ptp/ptp_idt82p33.c-834-\ndrivers/ptp/ptp_idt82p33.c:835:static int idt82p33_sync_tod(struct idt82p33_channel channel, bool enable)\ndrivers/ptp/ptp_idt82p33.c-836-{\ndrivers/ptp/ptp_idt82p33.c:837:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-838-\tu8 sync_cnfg;\n--\ndrivers/ptp/ptp_idt82p33.c-840-\ndrivers/ptp/ptp_idt82p33.c:841:\terr = idt82p33_read(idt82p33, channel-\u003edpll_sync_cnfg,\ndrivers/ptp/ptp_idt82p33.c-842-\t\t\t \u0026sync_cnfg, sizeof(sync_cnfg));\n--\ndrivers/ptp/ptp_idt82p33.c-849-\ndrivers/ptp/ptp_idt82p33.c:850:\treturn idt82p33_write(idt82p33, channel-\u003edpll_sync_cnfg,\ndrivers/ptp/ptp_idt82p33.c-851-\t\t\t \u0026sync_cnfg, sizeof(sync_cnfg));\n--\ndrivers/ptp/ptp_idt82p33.c-853-\ndrivers/ptp/ptp_idt82p33.c:854:static long idt82p33_work_handler(struct ptp_clock_info ptp)\ndrivers/ptp/ptp_idt82p33.c-855-{\ndrivers/ptp/ptp_idt82p33.c:856:\tstruct idt82p33_channel channel =\ndrivers/ptp/ptp_idt82p33.c:857:\t\t\tcontainer_of(ptp, struct idt82p33_channel, caps);\ndrivers/ptp/ptp_idt82p33.c:858:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-859-\ndrivers/ptp/ptp_idt82p33.c:860:\tmutex_lock(idt82p33-\u003elock);\ndrivers/ptp/ptp_idt82p33.c:861:\t(void)idt82p33_stop_ddco(channel);\ndrivers/ptp/ptp_idt82p33.c:862:\tmutex_unlock(idt82p33-\u003elock);\ndrivers/ptp/ptp_idt82p33.c-863-\n--\ndrivers/ptp/ptp_idt82p33.c-867-\ndrivers/ptp/ptp_idt82p33.c:868:static int idt82p33_output_enable(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-869-\t\t\t\t bool enable, unsigned int outn)\ndrivers/ptp/ptp_idt82p33.c-870-{\ndrivers/ptp/ptp_idt82p33.c:871:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-872-\tint err;\n--\ndrivers/ptp/ptp_idt82p33.c-874-\ndrivers/ptp/ptp_idt82p33.c:875:\terr = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), \u0026val, sizeof(val));\ndrivers/ptp/ptp_idt82p33.c-876-\tif (err)\n--\ndrivers/ptp/ptp_idt82p33.c-882-\ndrivers/ptp/ptp_idt82p33.c:883:\treturn idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), \u0026val, sizeof(val));\ndrivers/ptp/ptp_idt82p33.c-884-}\ndrivers/ptp/ptp_idt82p33.c-885-\ndrivers/ptp/ptp_idt82p33.c:886:static int idt82p33_perout_enable(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-887-\t\t\t\t bool enable,\n--\ndrivers/ptp/ptp_idt82p33.c-890-\t/ Enable/disable individual output instead */\ndrivers/ptp/ptp_idt82p33.c:891:\treturn idt82p33_output_enable(channel, enable, perout-\u003eindex);\ndrivers/ptp/ptp_idt82p33.c-892-}\n\n" }
5/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 18765 output: 45 thoughts: 48 Thoughts: Okay, let's dive into this. Here's how I'd approach understanding the registration and probing of `ptp_idt82p33`. Investigating the Registration and Probe of `ptp_idt82p33` Alright, I need to get a clear picture of how this `ptp_idt82p33` device is being handled within the kernel. My first step is to trace its registration and probing sequence. I'll need to understand the entry points. Let's start by looking at the relevant code in `ptp_idt82p33.c`. I'll focus my initial scan around line 1400. That should give me a good jumping-off point to see how the driver interacts with the device during its initialization phase. From there, I'll be looking for the crucial functions that handle device detection and resource allocation.
6/2	2026/09/24 18:14	tool	read-file	0m Args: { "File": "drivers/ptp/ptp_idt82p33.c", "FirstLine": 1380, "LineCount": 90 } Results: { "Contents": "1380:\t\t\t\t}\n1381:\t\t\t}\n1382:\t\t}\n1383:\t\n1384:\t\tif (idt82p33-\u003eextts_mask)\n1385:\t\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\n1386:\t\t\t\t\t msecs_to_jiffies(EXTTS_PERIOD_MS));\n1387:\t\n1388:\tout:\n1389:\t\tmutex_unlock(idt82p33-\u003elock);\n1390:\t}\n1391:\t\n1392:\tstatic int idt82p33_probe(struct platform_device pdev)\n1393:\t{\n1394:\t\tstruct rsmu_ddata ddata = dev_get_drvdata(pdev-\u003edev.parent);\n1395:\t\tstruct idt82p33 idt82p33;\n1396:\t\tint err;\n1397:\t\tu8 i;\n1398:\t\n1399:\t\tidt82p33 = devm_kzalloc(\u0026pdev-\u003edev,\n1400:\t\t\t\t\tsizeof(struct idt82p33), GFP_KERNEL);\n1401:\t\tif (!idt82p33)\n1402:\t\t\treturn -ENOMEM;\n1403:\t\n1404:\t\tidt82p33-\u003edev = \u0026pdev-\u003edev;\n1405:\t\tidt82p33-\u003emfd = pdev-\u003edev.parent;\n1406:\t\tidt82p33-\u003elock = \u0026ddata-\u003elock;\n1407:\t\tidt82p33-\u003eregmap = ddata-\u003eregmap;\n1408:\t\tidt82p33-\u003etod_write_overhead_ns = 0;\n1409:\t\tidt82p33-\u003ecalculate_overhead_flag = 0;\n1410:\t\tidt82p33-\u003epll_mask = DEFAULT_PLL_MASK;\n1411:\t\tidt82p33-\u003echannel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;\n1412:\t\tidt82p33-\u003echannel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;\n1413:\t\tidt82p33-\u003eextts_mask = 0;\n1414:\t\tINIT_DELAYED_WORK(\u0026idt82p33-\u003eextts_work, idt82p33_extts_check);\n1415:\t\n1416:\t\tmutex_lock(idt82p33-\u003elock);\n1417:\t\n1418:\t\t/ cold reset before loading firmware /\n1419:\t\tidt82p33_reset(idt82p33, true);\n1420:\t\n1421:\t\terr = idt82p33_load_firmware(idt82p33);\n1422:\t\tif (err)\n1423:\t\t\tdev_warn(idt82p33-\u003edev,\n1424:\t\t\t\t \"loading firmware failed with %d\\n\", err);\n1425:\t\n1426:\t\t/ soft reset after loading firmware /\n1427:\t\tidt82p33_reset(idt82p33, false);\n1428:\t\n1429:\t\tif (idt82p33-\u003epll_mask) {\n1430:\t\t\tfor (i = 0; i \u003c MAX_PHC_PLL; i++) {\n1431:\t\t\t\tif (idt82p33-\u003epll_mask \u0026 (1 \u003c\u003c i))\n1432:\t\t\t\t\terr = idt82p33_enable_channel(idt82p33, i);\n1433:\t\t\t\telse\n1434:\t\t\t\t\terr = idt82p33_channel_init(idt82p33, i);\n1435:\t\t\t\tif (err) {\n1436:\t\t\t\t\tdev_err(idt82p33-\u003edev,\n1437:\t\t\t\t\t\t\"Failed in %s with err %d!\\n\",\n1438:\t\t\t\t\t\t__func__, err);\n1439:\t\t\t\t\tbreak;\n1440:\t\t\t\t}\n1441:\t\t\t}\n1442:\t\t} else {\n1443:\t\t\tdev_err(idt82p33-\u003edev,\n1444:\t\t\t\t\"no PLLs flagged as PHCs, nothing to do\\n\");\n1445:\t\t\terr = -ENODEV;\n1446:\t\t}\n1447:\t\n1448:\t\tmutex_unlock(idt82p33-\u003elock);\n1449:\t\n1450:\t\tif (err) {\n1451:\t\t\tidt82p33_ptp_clock_unregister_all(idt82p33);\n1452:\t\t\treturn err;\n1453:\t\t}\n1454:\t\n1455:\t\tplatform_set_drvdata(pdev, idt82p33);\n1456:\t\n1457:\t\treturn 0;\n1458:\t}\n1459:\t\n1460:\tstatic void idt82p33_remove(struct platform_device pdev)\n1461:\t{\n1462:\t\tstruct idt82p33 *idt82p33 = platform_get_drvdata(pdev);\n1463:\t\n1464:\t\tidt82p33_ptp_clock_unregister_all(idt82p33);\n1465:\t}\n1466:\t\n1467:\tstatic struct platform_driver idt82p33_driver = {\n1468:\t\t.driver = {\n1469:\t\t\t.name = \"82p33x1x-phc\",\n" }
7/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 20555 output: 25 thoughts: 46 Thoughts: Okay, let's dive into this. Here's my thought process on this "82p33x1x-phc" platform device: Dissecting the "82p33x1x-phc" Device Right, so the first thing I want to do is figure out what the kernel's definition of this platform device is. It's named "82p33x1x-phc", and based on the name, it could be vendor specific. But before I start making assumptions, let's get the facts. Time to fire up `grep`. I'll run a search for that string across the entire kernel source tree. This should reveal where it's defined, used, and, most importantly, which driver or subsystem is associated with it. This is the starting point for understanding its purpose and function within the system.
8/2	2026/09/24 18:14	tool	grepper	0m Args: { "Expression": "82p33x1x-phc" } Results: { "Output": "drivers/mfd/rsmu_core.c=34=static struct mfd_cell rsmu_sabre_devs[] = {\ndrivers/mfd/rsmu_core.c-35-\t[RSMU_PHC] = {\ndrivers/mfd/rsmu_core.c:36:\t\t.name = \"82p33x1x-phc\",\ndrivers/mfd/rsmu_core.c-37-\t},\n--\ndrivers/ptp/ptp_idt82p33.c=1467=static struct platform_driver idt82p33_driver = {\ndrivers/ptp/ptp_idt82p33.c-1468-\t.driver = {\ndrivers/ptp/ptp_idt82p33.c:1469:\t\t.name = \"82p33x1x-phc\",\ndrivers/ptp/ptp_idt82p33.c-1470-\t},\n" }
9/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 21071 output: 26 thoughts: 37 Thoughts: Okay, let's dive into this. Here's my thought process on the matter: Delving into the `rsmu` Landscape Right, so we need to understand what's creating or interfacing with this `rsmu_sabre_devs` thing, or, perhaps, what is probing a `rsmu` interface. The logical starting point for me, given the context, is definitely the driver space, specifically the multi-function device drivers. Therefore, I’m immediately zeroing in on the `drivers/mfd/rsmu*` directory. That's where I'd expect to find the code responsible for handling this subsystem. Let's see what we can find there.
10/2	2026/09/24 18:14	tool	grepper	0m Args: { "Expression": "rsmu", "PathPrefix": "drivers/mfd" } Results: { "Output": "\nFull output is too long, showing 500 out of 507 lines.\nUse more precise expression if possible.\n\ndrivers/mfd/Makefile=299=obj-$(CONFIG_MFD_QNAP_MCU)\t+= qnap-mcu.o\ndrivers/mfd/Makefile-300-\ndrivers/mfd/Makefile:301:obj-$(CONFIG_MFD_RSMU_I2C)\t+= rsmu_i2c.o rsmu_core.o\ndrivers/mfd/Makefile:302:obj-$(CONFIG_MFD_RSMU_SPI)\t+= rsmu_spi.o rsmu_core.o\ndrivers/mfd/Makefile-303-\n--\ndrivers/mfd/rsmu.h-10-\ndrivers/mfd/rsmu.h:11:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/mfd/rsmu.h-12-\n--\ndrivers/mfd/rsmu.h-14-\ndrivers/mfd/rsmu.h:15:int rsmu_core_init(struct rsmu_ddata rsmu);\ndrivers/mfd/rsmu.h:16:void rsmu_core_exit(struct rsmu_ddata rsmu);\ndrivers/mfd/rsmu.h-17-\n--\ndrivers/mfd/rsmu_core.c-10-#include \u003clinux/mfd/core.h\u003e\ndrivers/mfd/rsmu_core.c:11:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/mfd/rsmu_core.c-12-#include \u003clinux/module.h\u003e\n--\ndrivers/mfd/rsmu_core.c-16-\ndrivers/mfd/rsmu_core.c:17:#include \"rsmu.h\"\ndrivers/mfd/rsmu_core.c-18-\ndrivers/mfd/rsmu_core.c=19=enum {\n--\ndrivers/mfd/rsmu_core.c-24-\ndrivers/mfd/rsmu_core.c:25:static struct mfd_cell rsmu_cm_devs[] = {\ndrivers/mfd/rsmu_core.c-26-\t[RSMU_PHC] = {\n--\ndrivers/mfd/rsmu_core.c-33-\ndrivers/mfd/rsmu_core.c:34:static struct mfd_cell rsmu_sabre_devs[] = {\ndrivers/mfd/rsmu_core.c-35-\t[RSMU_PHC] = {\n--\ndrivers/mfd/rsmu_core.c-42-\ndrivers/mfd/rsmu_core.c:43:static struct mfd_cell rsmu_sl_devs[] = {\ndrivers/mfd/rsmu_core.c-44-\t[RSMU_PHC] = {\n--\ndrivers/mfd/rsmu_core.c-51-\ndrivers/mfd/rsmu_core.c:52:int rsmu_core_init(struct rsmu_ddata rsmu)\ndrivers/mfd/rsmu_core.c-53-{\n--\ndrivers/mfd/rsmu_core.c-56-\ndrivers/mfd/rsmu_core.c:57:\tswitch (rsmu-\u003etype) {\ndrivers/mfd/rsmu_core.c-58-\tcase RSMU_CM:\ndrivers/mfd/rsmu_core.c:59:\t\tcells = rsmu_cm_devs;\ndrivers/mfd/rsmu_core.c-60-\t\tbreak;\ndrivers/mfd/rsmu_core.c-61-\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_core.c:62:\t\tcells = rsmu_sabre_devs;\ndrivers/mfd/rsmu_core.c-63-\t\tbreak;\ndrivers/mfd/rsmu_core.c-64-\tcase RSMU_SL:\ndrivers/mfd/rsmu_core.c:65:\t\tcells = rsmu_sl_devs;\ndrivers/mfd/rsmu_core.c-66-\t\tbreak;\ndrivers/mfd/rsmu_core.c-67-\tdefault:\ndrivers/mfd/rsmu_core.c:68:\t\tdev_err(rsmu-\u003edev, \"Unsupported RSMU device type: %d\\n\", rsmu-\u003etype);\ndrivers/mfd/rsmu_core.c-69-\t\treturn -ENODEV;\n--\ndrivers/mfd/rsmu_core.c-71-\ndrivers/mfd/rsmu_core.c:72:\tmutex_init(\u0026rsmu-\u003elock);\ndrivers/mfd/rsmu_core.c-73-\ndrivers/mfd/rsmu_core.c:74:\tret = devm_mfd_add_devices(rsmu-\u003edev, PLATFORM_DEVID_AUTO, cells,\ndrivers/mfd/rsmu_core.c-75-\t\t\t\t RSMU_N_DEVS, NULL, 0, NULL);\ndrivers/mfd/rsmu_core.c-76-\tif (ret \u003c 0)\ndrivers/mfd/rsmu_core.c:77:\t\tdev_err(rsmu-\u003edev, \"Failed to register sub-devices: %d\\n\", ret);\ndrivers/mfd/rsmu_core.c-78-\n--\ndrivers/mfd/rsmu_core.c-80-}\ndrivers/mfd/rsmu_core.c:81:EXPORT_SYMBOL_GPL(rsmu_core_init);\ndrivers/mfd/rsmu_core.c-82-\ndrivers/mfd/rsmu_core.c:83:void rsmu_core_exit(struct rsmu_ddata rsmu)\ndrivers/mfd/rsmu_core.c-84-{\ndrivers/mfd/rsmu_core.c:85:\tmutex_destroy(\u0026rsmu-\u003elock);\ndrivers/mfd/rsmu_core.c-86-}\ndrivers/mfd/rsmu_core.c:87:EXPORT_SYMBOL_GPL(rsmu_core_exit);\ndrivers/mfd/rsmu_core.c-88-\n--\ndrivers/mfd/rsmu_i2c.c-11-#include \u003clinux/mfd/core.h\u003e\ndrivers/mfd/rsmu_i2c.c:12:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/mfd/rsmu_i2c.c-13-#include \u003clinux/module.h\u003e\n--\ndrivers/mfd/rsmu_i2c.c-17-\ndrivers/mfd/rsmu_i2c.c:18:#include \"rsmu.h\"\ndrivers/mfd/rsmu_i2c.c-19-\n--\ndrivers/mfd/rsmu_i2c.c-34-\ndrivers/mfd/rsmu_i2c.c:35:typedef int (rsmu_rw_device)(struct rsmu_ddata rsmu, u8 reg, u8 buf, u8 bytes);\ndrivers/mfd/rsmu_i2c.c-36-\ndrivers/mfd/rsmu_i2c.c:37:static const struct regmap_range_cfg rsmu_sabre_range_cfg[] = {\ndrivers/mfd/rsmu_i2c.c-38-\t{\n--\ndrivers/mfd/rsmu_i2c.c-48-\ndrivers/mfd/rsmu_i2c.c:49:static bool rsmu_sabre_volatile_reg(struct device dev, unsigned int reg)\ndrivers/mfd/rsmu_i2c.c-50-{\n--\ndrivers/mfd/rsmu_i2c.c-58-\ndrivers/mfd/rsmu_i2c.c:59:static int rsmu_smbus_i2c_write_device(struct rsmu_ddata rsmu, u8 reg, u8 buf, u8 bytes)\ndrivers/mfd/rsmu_i2c.c-60-{\ndrivers/mfd/rsmu_i2c.c:61:\tstruct i2c_client client = to_i2c_client(rsmu-\u003edev);\ndrivers/mfd/rsmu_i2c.c-62-\n--\ndrivers/mfd/rsmu_i2c.c-65-\ndrivers/mfd/rsmu_i2c.c:66:static int rsmu_smbus_i2c_read_device(struct rsmu_ddata rsmu, u8 reg, u8 buf, u8 bytes)\ndrivers/mfd/rsmu_i2c.c-67-{\ndrivers/mfd/rsmu_i2c.c:68:\tstruct i2c_client client = to_i2c_client(rsmu-\u003edev);\ndrivers/mfd/rsmu_i2c.c-69-\tint ret;\n--\ndrivers/mfd/rsmu_i2c.c-79-\ndrivers/mfd/rsmu_i2c.c:80:static int rsmu_i2c_read_device(struct rsmu_ddata rsmu, u8 reg, u8 buf, u8 bytes)\ndrivers/mfd/rsmu_i2c.c-81-{\ndrivers/mfd/rsmu_i2c.c:82:\tstruct i2c_client client = to_i2c_client(rsmu-\u003edev);\ndrivers/mfd/rsmu_i2c.c-83-\tstruct i2c_msg msg[2];\n--\ndrivers/mfd/rsmu_i2c.c-98-\tif (cnt \u003c 0) {\ndrivers/mfd/rsmu_i2c.c:99:\t\tdev_err(rsmu-\u003edev, \"i2c_transfer failed at addr: %04x!\", reg);\ndrivers/mfd/rsmu_i2c.c-100-\t\treturn cnt;\ndrivers/mfd/rsmu_i2c.c-101-\t} else if (cnt != 2) {\ndrivers/mfd/rsmu_i2c.c:102:\t\tdev_err(rsmu-\u003edev,\ndrivers/mfd/rsmu_i2c.c-103-\t\t\t\"i2c_transfer sent only %d of 2 messages\", cnt);\n--\ndrivers/mfd/rsmu_i2c.c-109-\ndrivers/mfd/rsmu_i2c.c:110:static int rsmu_i2c_write_device(struct rsmu_ddata rsmu, u8 reg, u8 buf, u8 bytes)\ndrivers/mfd/rsmu_i2c.c-111-{\ndrivers/mfd/rsmu_i2c.c:112:\tstruct i2c_client client = to_i2c_client(rsmu-\u003edev);\ndrivers/mfd/rsmu_i2c.c-113-\t/* we add 1 byte for device register /\n--\ndrivers/mfd/rsmu_i2c.c-133-\ndrivers/mfd/rsmu_i2c.c:134:static int rsmu_write_page_register(struct rsmu_ddata rsmu, u32 reg,\ndrivers/mfd/rsmu_i2c.c:135:\t\t\t\t rsmu_rw_device rsmu_write_device)\ndrivers/mfd/rsmu_i2c.c-136-{\n--\ndrivers/mfd/rsmu_i2c.c-141-\t/* Simply return if we are on the same page /\ndrivers/mfd/rsmu_i2c.c:142:\tif (rsmu-\u003epage == page)\ndrivers/mfd/rsmu_i2c.c-143-\t\treturn 0;\n--\ndrivers/mfd/rsmu_i2c.c-149-\ndrivers/mfd/rsmu_i2c.c:150:\terr = rsmu_write_device(rsmu, RSMU_CM_PAGE_ADDR, buf, sizeof(buf));\ndrivers/mfd/rsmu_i2c.c-151-\tif (err)\ndrivers/mfd/rsmu_i2c.c:152:\t\tdev_err(rsmu-\u003edev, \"Failed to set page offset 0x%x\\n\", page);\ndrivers/mfd/rsmu_i2c.c-153-\telse\ndrivers/mfd/rsmu_i2c.c-154-\t\t/ Remember the last page /\ndrivers/mfd/rsmu_i2c.c:155:\t\trsmu-\u003epage = page;\ndrivers/mfd/rsmu_i2c.c-156-\n--\ndrivers/mfd/rsmu_i2c.c-159-\ndrivers/mfd/rsmu_i2c.c:160:static int rsmu_i2c_reg_read(void context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_i2c.c-161-{\ndrivers/mfd/rsmu_i2c.c:162:\tstruct rsmu_ddata rsmu = i2c_get_clientdata((struct i2c_client )context);\ndrivers/mfd/rsmu_i2c.c-163-\tu8 addr = (u8)(reg \u0026 RSMU_CM_ADDRESS_MASK);\n--\ndrivers/mfd/rsmu_i2c.c-165-\ndrivers/mfd/rsmu_i2c.c:166:\terr = rsmu_write_page_register(rsmu, reg, rsmu_i2c_write_device);\ndrivers/mfd/rsmu_i2c.c-167-\tif (err)\n--\ndrivers/mfd/rsmu_i2c.c-169-\ndrivers/mfd/rsmu_i2c.c:170:\terr = rsmu_i2c_read_device(rsmu, addr, (u8 )val, 1);\ndrivers/mfd/rsmu_i2c.c-171-\tif (err)\ndrivers/mfd/rsmu_i2c.c:172:\t\tdev_err(rsmu-\u003edev, \"Failed to read offset address 0x%x\\n\", addr);\ndrivers/mfd/rsmu_i2c.c-173-\n--\ndrivers/mfd/rsmu_i2c.c-176-\ndrivers/mfd/rsmu_i2c.c:177:static int rsmu_i2c_reg_write(void context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_i2c.c-178-{\ndrivers/mfd/rsmu_i2c.c:179:\tstruct rsmu_ddata rsmu = i2c_get_clientdata((struct i2c_client )context);\ndrivers/mfd/rsmu_i2c.c-180-\tu8 addr = (u8)(reg \u0026 RSMU_CM_ADDRESS_MASK);\n--\ndrivers/mfd/rsmu_i2c.c-183-\ndrivers/mfd/rsmu_i2c.c:184:\terr = rsmu_write_page_register(rsmu, reg, rsmu_i2c_write_device);\ndrivers/mfd/rsmu_i2c.c-185-\tif (err)\n--\ndrivers/mfd/rsmu_i2c.c-187-\ndrivers/mfd/rsmu_i2c.c:188:\terr = rsmu_i2c_write_device(rsmu, addr, \u0026data, 1);\ndrivers/mfd/rsmu_i2c.c-189-\tif (err)\ndrivers/mfd/rsmu_i2c.c:190:\t\tdev_err(rsmu-\u003edev,\ndrivers/mfd/rsmu_i2c.c-191-\t\t\t\"Failed to write offset address 0x%x\\n\", addr);\n--\ndrivers/mfd/rsmu_i2c.c-195-\ndrivers/mfd/rsmu_i2c.c:196:static int rsmu_smbus_i2c_reg_read(void context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_i2c.c-197-{\ndrivers/mfd/rsmu_i2c.c:198:\tstruct rsmu_ddata rsmu = i2c_get_clientdata((struct i2c_client )context);\ndrivers/mfd/rsmu_i2c.c-199-\tu8 addr = (u8)(reg \u0026 RSMU_CM_ADDRESS_MASK);\n--\ndrivers/mfd/rsmu_i2c.c-201-\ndrivers/mfd/rsmu_i2c.c:202:\terr = rsmu_write_page_register(rsmu, reg, rsmu_smbus_i2c_write_device);\ndrivers/mfd/rsmu_i2c.c-203-\tif (err)\n--\ndrivers/mfd/rsmu_i2c.c-205-\ndrivers/mfd/rsmu_i2c.c:206:\terr = rsmu_smbus_i2c_read_device(rsmu, addr, (u8 )val, 1);\ndrivers/mfd/rsmu_i2c.c-207-\tif (err)\ndrivers/mfd/rsmu_i2c.c:208:\t\tdev_err(rsmu-\u003edev, \"Failed to read offset address 0x%x\\n\", addr);\ndrivers/mfd/rsmu_i2c.c-209-\n--\ndrivers/mfd/rsmu_i2c.c-212-\ndrivers/mfd/rsmu_i2c.c:213:static int rsmu_smbus_i2c_reg_write(void context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_i2c.c-214-{\ndrivers/mfd/rsmu_i2c.c:215:\tstruct rsmu_ddata rsmu = i2c_get_clientdata((struct i2c_client )context);\ndrivers/mfd/rsmu_i2c.c-216-\tu8 addr = (u8)(reg \u0026 RSMU_CM_ADDRESS_MASK);\n--\ndrivers/mfd/rsmu_i2c.c-219-\ndrivers/mfd/rsmu_i2c.c:220:\terr = rsmu_write_page_register(rsmu, reg, rsmu_smbus_i2c_write_device);\ndrivers/mfd/rsmu_i2c.c-221-\tif (err)\n--\ndrivers/mfd/rsmu_i2c.c-223-\ndrivers/mfd/rsmu_i2c.c:224:\terr = rsmu_smbus_i2c_write_device(rsmu, addr, \u0026data, 1);\ndrivers/mfd/rsmu_i2c.c-225-\tif (err)\ndrivers/mfd/rsmu_i2c.c:226:\t\tdev_err(rsmu-\u003edev,\ndrivers/mfd/rsmu_i2c.c-227-\t\t\t\"Failed to write offset address 0x%x\\n\", addr);\n--\ndrivers/mfd/rsmu_i2c.c-231-\ndrivers/mfd/rsmu_i2c.c:232:static const struct regmap_config rsmu_i2c_cm_regmap_config = {\ndrivers/mfd/rsmu_i2c.c-233-\t.reg_bits = 32,\n--\ndrivers/mfd/rsmu_i2c.c-235-\t.max_register = 0x20120000,\ndrivers/mfd/rsmu_i2c.c:236:\t.reg_read = rsmu_i2c_reg_read,\ndrivers/mfd/rsmu_i2c.c:237:\t.reg_write = rsmu_i2c_reg_write,\ndrivers/mfd/rsmu_i2c.c-238-\t.cache_type = REGCACHE_NONE,\n--\ndrivers/mfd/rsmu_i2c.c-240-\ndrivers/mfd/rsmu_i2c.c:241:static const struct regmap_config rsmu_smbus_i2c_cm_regmap_config = {\ndrivers/mfd/rsmu_i2c.c-242-\t.reg_bits = 32,\n--\ndrivers/mfd/rsmu_i2c.c-244-\t.max_register = 0x20120000,\ndrivers/mfd/rsmu_i2c.c:245:\t.reg_read = rsmu_smbus_i2c_reg_read,\ndrivers/mfd/rsmu_i2c.c:246:\t.reg_write = rsmu_smbus_i2c_reg_write,\ndrivers/mfd/rsmu_i2c.c-247-\t.cache_type = REGCACHE_NONE,\n--\ndrivers/mfd/rsmu_i2c.c-249-\ndrivers/mfd/rsmu_i2c.c:250:static const struct regmap_config rsmu_sabre_regmap_config = {\ndrivers/mfd/rsmu_i2c.c-251-\t.reg_bits = 8,\n--\ndrivers/mfd/rsmu_i2c.c-253-\t.max_register = 0x400,\ndrivers/mfd/rsmu_i2c.c:254:\t.ranges = rsmu_sabre_range_cfg,\ndrivers/mfd/rsmu_i2c.c:255:\t.num_ranges = ARRAY_SIZE(rsmu_sabre_range_cfg),\ndrivers/mfd/rsmu_i2c.c:256:\t.volatile_reg = rsmu_sabre_volatile_reg,\ndrivers/mfd/rsmu_i2c.c-257-\t.cache_type = REGCACHE_MAPLE,\n--\ndrivers/mfd/rsmu_i2c.c-260-\ndrivers/mfd/rsmu_i2c.c:261:static const struct regmap_config rsmu_sl_regmap_config = {\ndrivers/mfd/rsmu_i2c.c-262-\t.reg_bits = 16,\n--\ndrivers/mfd/rsmu_i2c.c-269-\ndrivers/mfd/rsmu_i2c.c:270:static int rsmu_i2c_probe(struct i2c_client client)\ndrivers/mfd/rsmu_i2c.c-271-{\n--\ndrivers/mfd/rsmu_i2c.c-273-\tconst struct regmap_config cfg;\ndrivers/mfd/rsmu_i2c.c:274:\tstruct rsmu_ddata rsmu;\ndrivers/mfd/rsmu_i2c.c-275-\tint ret;\ndrivers/mfd/rsmu_i2c.c-276-\ndrivers/mfd/rsmu_i2c.c:277:\trsmu = devm_kzalloc(\u0026client-\u003edev, sizeof(rsmu), GFP_KERNEL);\ndrivers/mfd/rsmu_i2c.c:278:\tif (!rsmu)\ndrivers/mfd/rsmu_i2c.c-279-\t\treturn -ENOMEM;\ndrivers/mfd/rsmu_i2c.c-280-\ndrivers/mfd/rsmu_i2c.c:281:\ti2c_set_clientdata(client, rsmu);\ndrivers/mfd/rsmu_i2c.c-282-\ndrivers/mfd/rsmu_i2c.c:283:\trsmu-\u003edev = \u0026client-\u003edev;\ndrivers/mfd/rsmu_i2c.c:284:\trsmu-\u003etype = (enum rsmu_type)id-\u003edriver_data;\ndrivers/mfd/rsmu_i2c.c-285-\ndrivers/mfd/rsmu_i2c.c:286:\tswitch (rsmu-\u003etype) {\ndrivers/mfd/rsmu_i2c.c-287-\tcase RSMU_CM:\ndrivers/mfd/rsmu_i2c.c-288-\t\tif (i2c_check_functionality(client-\u003eadapter, I2C_FUNC_I2C)) {\ndrivers/mfd/rsmu_i2c.c:289:\t\t\tcfg = \u0026rsmu_i2c_cm_regmap_config;\ndrivers/mfd/rsmu_i2c.c-290-\t\t} else if (i2c_check_functionality(client-\u003eadapter,\ndrivers/mfd/rsmu_i2c.c-291-\t\t\t\t\t\t I2C_FUNC_SMBUS_I2C_BLOCK)) {\ndrivers/mfd/rsmu_i2c.c:292:\t\t\tcfg = \u0026rsmu_smbus_i2c_cm_regmap_config;\ndrivers/mfd/rsmu_i2c.c-293-\t\t} else {\ndrivers/mfd/rsmu_i2c.c:294:\t\t\tdev_err(rsmu-\u003edev, \"Unsupported i2c adapter\\n\");\ndrivers/mfd/rsmu_i2c.c-295-\t\t\treturn -ENOTSUPP;\n--\ndrivers/mfd/rsmu_i2c.c-298-\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_i2c.c:299:\t\tcfg = \u0026rsmu_sabre_regmap_config;\ndrivers/mfd/rsmu_i2c.c-300-\t\tbreak;\ndrivers/mfd/rsmu_i2c.c-301-\tcase RSMU_SL:\ndrivers/mfd/rsmu_i2c.c:302:\t\tcfg = \u0026rsmu_sl_regmap_config;\ndrivers/mfd/rsmu_i2c.c-303-\t\tbreak;\ndrivers/mfd/rsmu_i2c.c-304-\tdefault:\ndrivers/mfd/rsmu_i2c.c:305:\t\tdev_err(rsmu-\u003edev, \"Unsupported RSMU device type: %d\\n\", rsmu-\u003etype);\ndrivers/mfd/rsmu_i2c.c-306-\t\treturn -ENODEV;\n--\ndrivers/mfd/rsmu_i2c.c-308-\ndrivers/mfd/rsmu_i2c.c:309:\tif (rsmu-\u003etype == RSMU_CM)\ndrivers/mfd/rsmu_i2c.c:310:\t\trsmu-\u003eregmap = devm_regmap_init(\u0026client-\u003edev, NULL, client, cfg);\ndrivers/mfd/rsmu_i2c.c-311-\telse\ndrivers/mfd/rsmu_i2c.c:312:\t\trsmu-\u003eregmap = devm_regmap_init_i2c(client, cfg);\ndrivers/mfd/rsmu_i2c.c-313-\ndrivers/mfd/rsmu_i2c.c:314:\tif (IS_ERR(rsmu-\u003eregmap)) {\ndrivers/mfd/rsmu_i2c.c:315:\t\tret = PTR_ERR(rsmu-\u003eregmap);\ndrivers/mfd/rsmu_i2c.c:316:\t\tdev_err(rsmu-\u003edev, \"Failed to allocate register map: %d\\n\", ret);\ndrivers/mfd/rsmu_i2c.c-317-\t\treturn ret;\n--\ndrivers/mfd/rsmu_i2c.c-319-\ndrivers/mfd/rsmu_i2c.c:320:\treturn rsmu_core_init(rsmu);\ndrivers/mfd/rsmu_i2c.c-321-}\ndrivers/mfd/rsmu_i2c.c-322-\ndrivers/mfd/rsmu_i2c.c:323:static void rsmu_i2c_remove(struct i2c_client client)\ndrivers/mfd/rsmu_i2c.c-324-{\ndrivers/mfd/rsmu_i2c.c:325:\tstruct rsmu_ddata rsmu = i2c_get_clientdata(client);\ndrivers/mfd/rsmu_i2c.c-326-\ndrivers/mfd/rsmu_i2c.c:327:\trsmu_core_exit(rsmu);\ndrivers/mfd/rsmu_i2c.c-328-}\ndrivers/mfd/rsmu_i2c.c-329-\ndrivers/mfd/rsmu_i2c.c:330:static const struct i2c_device_id rsmu_i2c_id[] = {\ndrivers/mfd/rsmu_i2c.c-331-\t{ \"8a34000\", RSMU_CM },\n--\ndrivers/mfd/rsmu_i2c.c-339-};\ndrivers/mfd/rsmu_i2c.c:340:MODULE_DEVICE_TABLE(i2c, rsmu_i2c_id);\ndrivers/mfd/rsmu_i2c.c-341-\ndrivers/mfd/rsmu_i2c.c:342:static const struct of_device_id rsmu_i2c_of_match[] = {\ndrivers/mfd/rsmu_i2c.c-343-\t{ .compatible = \"idt,8a34000\", .data = (void )RSMU_CM },\n--\ndrivers/mfd/rsmu_i2c.c-351-};\ndrivers/mfd/rsmu_i2c.c:352:MODULE_DEVICE_TABLE(of, rsmu_i2c_of_match);\ndrivers/mfd/rsmu_i2c.c-353-\ndrivers/mfd/rsmu_i2c.c:354:static struct i2c_driver rsmu_i2c_driver = {\ndrivers/mfd/rsmu_i2c.c-355-\t.driver = {\ndrivers/mfd/rsmu_i2c.c:356:\t\t.name = \"rsmu-i2c\",\ndrivers/mfd/rsmu_i2c.c:357:\t\t.of_match_table = rsmu_i2c_of_match,\ndrivers/mfd/rsmu_i2c.c-358-\t},\ndrivers/mfd/rsmu_i2c.c:359:\t.probe = rsmu_i2c_probe,\ndrivers/mfd/rsmu_i2c.c:360:\t.remove\t= rsmu_i2c_remove,\ndrivers/mfd/rsmu_i2c.c:361:\t.id_table = rsmu_i2c_id,\ndrivers/mfd/rsmu_i2c.c-362-};\ndrivers/mfd/rsmu_i2c.c-363-\ndrivers/mfd/rsmu_i2c.c:364:static int __init rsmu_i2c_init(void)\ndrivers/mfd/rsmu_i2c.c-365-{\ndrivers/mfd/rsmu_i2c.c:366:\treturn i2c_add_driver(\u0026rsmu_i2c_driver);\ndrivers/mfd/rsmu_i2c.c-367-}\ndrivers/mfd/rsmu_i2c.c:368:subsys_initcall(rsmu_i2c_init);\ndrivers/mfd/rsmu_i2c.c-369-\ndrivers/mfd/rsmu_i2c.c:370:static void __exit rsmu_i2c_exit(void)\ndrivers/mfd/rsmu_i2c.c-371-{\ndrivers/mfd/rsmu_i2c.c:372:\ti2c_del_driver(\u0026rsmu_i2c_driver);\ndrivers/mfd/rsmu_i2c.c-373-}\ndrivers/mfd/rsmu_i2c.c:374:module_exit(rsmu_i2c_exit);\ndrivers/mfd/rsmu_i2c.c-375-\n--\ndrivers/mfd/rsmu_spi.c-10-#include \u003clinux/mfd/core.h\u003e\ndrivers/mfd/rsmu_spi.c:11:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/mfd/rsmu_spi.c-12-#include \u003clinux/module.h\u003e\n--\ndrivers/mfd/rsmu_spi.c-17-\ndrivers/mfd/rsmu_spi.c:18:#include \"rsmu.h\"\ndrivers/mfd/rsmu_spi.c-19-\n--\ndrivers/mfd/rsmu_spi.c-24-\ndrivers/mfd/rsmu_spi.c:25:static int rsmu_read_device(struct rsmu_ddata rsmu, u8 reg, u8 buf, u16 bytes)\ndrivers/mfd/rsmu_spi.c-26-{\ndrivers/mfd/rsmu_spi.c:27:\tstruct spi_device client = to_spi_device(rsmu-\u003edev);\ndrivers/mfd/rsmu_spi.c-28-\tstruct spi_transfer xfer = {0};\n--\ndrivers/mfd/rsmu_spi.c-65-\ndrivers/mfd/rsmu_spi.c:66:static int rsmu_write_device(struct rsmu_ddata rsmu, u8 reg, u8 buf, u16 bytes)\ndrivers/mfd/rsmu_spi.c-67-{\ndrivers/mfd/rsmu_spi.c:68:\tstruct spi_device client = to_spi_device(rsmu-\u003edev);\ndrivers/mfd/rsmu_spi.c-69-\tstruct spi_transfer xfer = {0};\n--\ndrivers/mfd/rsmu_spi.c-93- /\ndrivers/mfd/rsmu_spi.c:94:static int rsmu_write_page_register(struct rsmu_ddata rsmu, u32 reg)\ndrivers/mfd/rsmu_spi.c-95-{\n--\ndrivers/mfd/rsmu_spi.c-101-\ndrivers/mfd/rsmu_spi.c:102:\tswitch (rsmu-\u003etype) {\ndrivers/mfd/rsmu_spi.c-103-\tcase RSMU_CM:\n--\ndrivers/mfd/rsmu_spi.c-122-\tdefault:\ndrivers/mfd/rsmu_spi.c:123:\t\tdev_err(rsmu-\u003edev, \"Unsupported RSMU device type: %d\\n\", rsmu-\u003etype);\ndrivers/mfd/rsmu_spi.c-124-\t\treturn -ENODEV;\n--\ndrivers/mfd/rsmu_spi.c-127-\t/* Simply return if we are on the same page /\ndrivers/mfd/rsmu_spi.c:128:\tif (rsmu-\u003epage == page)\ndrivers/mfd/rsmu_spi.c-129-\t\treturn 0;\ndrivers/mfd/rsmu_spi.c-130-\ndrivers/mfd/rsmu_spi.c:131:\terr = rsmu_write_device(rsmu, page_reg, buf, bytes);\ndrivers/mfd/rsmu_spi.c-132-\tif (err)\ndrivers/mfd/rsmu_spi.c:133:\t\tdev_err(rsmu-\u003edev, \"Failed to set page offset 0x%x\\n\", page);\ndrivers/mfd/rsmu_spi.c-134-\telse\ndrivers/mfd/rsmu_spi.c-135-\t\t/ Remember the last page /\ndrivers/mfd/rsmu_spi.c:136:\t\trsmu-\u003epage = page;\ndrivers/mfd/rsmu_spi.c-137-\n--\ndrivers/mfd/rsmu_spi.c-140-\ndrivers/mfd/rsmu_spi.c:141:static int rsmu_reg_read(void context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_spi.c-142-{\ndrivers/mfd/rsmu_spi.c:143:\tstruct rsmu_ddata rsmu = spi_get_drvdata((struct spi_device )context);\ndrivers/mfd/rsmu_spi.c-144-\tu8 addr = (u8)(reg \u0026 RSMU_ADDR_MASK);\n--\ndrivers/mfd/rsmu_spi.c-146-\ndrivers/mfd/rsmu_spi.c:147:\terr = rsmu_write_page_register(rsmu, reg);\ndrivers/mfd/rsmu_spi.c-148-\tif (err)\n--\ndrivers/mfd/rsmu_spi.c-150-\ndrivers/mfd/rsmu_spi.c:151:\terr = rsmu_read_device(rsmu, addr, (u8 )val, 1);\ndrivers/mfd/rsmu_spi.c-152-\tif (err)\ndrivers/mfd/rsmu_spi.c:153:\t\tdev_err(rsmu-\u003edev, \"Failed to read offset address 0x%x\\n\", addr);\ndrivers/mfd/rsmu_spi.c-154-\n--\ndrivers/mfd/rsmu_spi.c-157-\ndrivers/mfd/rsmu_spi.c:158:static int rsmu_reg_write(void context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_spi.c-159-{\ndrivers/mfd/rsmu_spi.c:160:\tstruct rsmu_ddata rsmu = spi_get_drvdata((struct spi_device )context);\ndrivers/mfd/rsmu_spi.c-161-\tu8 addr = (u8)(reg \u0026 RSMU_ADDR_MASK);\n--\ndrivers/mfd/rsmu_spi.c-164-\ndrivers/mfd/rsmu_spi.c:165:\terr = rsmu_write_page_register(rsmu, reg);\ndrivers/mfd/rsmu_spi.c-166-\tif (err)\n--\ndrivers/mfd/rsmu_spi.c-168-\ndrivers/mfd/rsmu_spi.c:169:\terr = rsmu_write_device(rsmu, addr, \u0026data, 1);\ndrivers/mfd/rsmu_spi.c-170-\tif (err)\ndrivers/mfd/rsmu_spi.c:171:\t\tdev_err(rsmu-\u003edev,\ndrivers/mfd/rsmu_spi.c-172-\t\t\t\"Failed to write offset address 0x%x\\n\", addr);\n--\ndrivers/mfd/rsmu_spi.c-176-\ndrivers/mfd/rsmu_spi.c:177:static const struct regmap_config rsmu_cm_regmap_config = {\ndrivers/mfd/rsmu_spi.c-178-\t.reg_bits = 32,\n--\ndrivers/mfd/rsmu_spi.c-180-\t.max_register = 0x20120000,\ndrivers/mfd/rsmu_spi.c:181:\t.reg_read = rsmu_reg_read,\ndrivers/mfd/rsmu_spi.c:182:\t.reg_write = rsmu_reg_write,\ndrivers/mfd/rsmu_spi.c-183-\t.cache_type = REGCACHE_NONE,\n--\ndrivers/mfd/rsmu_spi.c-185-\ndrivers/mfd/rsmu_spi.c:186:static const struct regmap_config rsmu_sabre_regmap_config = {\ndrivers/mfd/rsmu_spi.c-187-\t.reg_bits = 16,\n--\ndrivers/mfd/rsmu_spi.c-189-\t.max_register = 0x400,\ndrivers/mfd/rsmu_spi.c:190:\t.reg_read = rsmu_reg_read,\ndrivers/mfd/rsmu_spi.c:191:\t.reg_write = rsmu_reg_write,\ndrivers/mfd/rsmu_spi.c-192-\t.cache_type = REGCACHE_NONE,\n--\ndrivers/mfd/rsmu_spi.c-194-\ndrivers/mfd/rsmu_spi.c:195:static int rsmu_spi_probe(struct spi_device client)\ndrivers/mfd/rsmu_spi.c-196-{\n--\ndrivers/mfd/rsmu_spi.c-198-\tconst struct regmap_config cfg;\ndrivers/mfd/rsmu_spi.c:199:\tstruct rsmu_ddata rsmu;\ndrivers/mfd/rsmu_spi.c-200-\tint ret;\ndrivers/mfd/rsmu_spi.c-201-\ndrivers/mfd/rsmu_spi.c:202:\trsmu = devm_kzalloc(\u0026client-\u003edev, sizeof(rsmu), GFP_KERNEL);\ndrivers/mfd/rsmu_spi.c:203:\tif (!rsmu)\ndrivers/mfd/rsmu_spi.c-204-\t\treturn -ENOMEM;\ndrivers/mfd/rsmu_spi.c-205-\ndrivers/mfd/rsmu_spi.c:206:\tspi_set_drvdata(client, rsmu);\ndrivers/mfd/rsmu_spi.c-207-\ndrivers/mfd/rsmu_spi.c:208:\trsmu-\u003edev = \u0026client-\u003edev;\ndrivers/mfd/rsmu_spi.c:209:\trsmu-\u003etype = (enum rsmu_type)id-\u003edriver_data;\ndrivers/mfd/rsmu_spi.c-210-\ndrivers/mfd/rsmu_spi.c-211-\t/ Initialize regmap /\ndrivers/mfd/rsmu_spi.c:212:\tswitch (rsmu-\u003etype) {\ndrivers/mfd/rsmu_spi.c-213-\tcase RSMU_CM:\ndrivers/mfd/rsmu_spi.c:214:\t\tcfg = \u0026rsmu_cm_regmap_config;\ndrivers/mfd/rsmu_spi.c-215-\t\tbreak;\ndrivers/mfd/rsmu_spi.c-216-\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_spi.c:217:\t\tcfg = \u0026rsmu_sabre_regmap_config;\ndrivers/mfd/rsmu_spi.c-218-\t\tbreak;\ndrivers/mfd/rsmu_spi.c-219-\tdefault:\ndrivers/mfd/rsmu_spi.c:220:\t\tdev_err(rsmu-\u003edev, \"Unsupported RSMU device type: %d\\n\", rsmu-\u003etype);\ndrivers/mfd/rsmu_spi.c-221-\t\treturn -ENODEV;\n--\ndrivers/mfd/rsmu_spi.c-223-\ndrivers/mfd/rsmu_spi.c:224:\trsmu-\u003eregmap = devm_regmap_init(\u0026client-\u003edev, NULL, client, cfg);\ndrivers/mfd/rsmu_spi.c:225:\tif (IS_ERR(rsmu-\u003eregmap)) {\ndrivers/mfd/rsmu_spi.c:226:\t\tret = PTR_ERR(rsmu-\u003eregmap);\ndrivers/mfd/rsmu_spi.c:227:\t\tdev_err(rsmu-\u003edev, \"Failed to allocate register map: %d\\n\", ret);\ndrivers/mfd/rsmu_spi.c-228-\t\treturn ret;\n--\ndrivers/mfd/rsmu_spi.c-230-\ndrivers/mfd/rsmu_spi.c:231:\treturn rsmu_core_init(rsmu);\ndrivers/mfd/rsmu_spi.c-232-}\ndrivers/mfd/rsmu_spi.c-233-\ndrivers/mfd/rsmu_spi.c:234:static void rsmu_spi_remove(struct spi_device client)\ndrivers/mfd/rsmu_spi.c-235-{\ndrivers/mfd/rsmu_spi.c:236:\tstruct rsmu_ddata rsmu = spi_get_drvdata(client);\ndrivers/mfd/rsmu_spi.c-237-\ndrivers/mfd/rsmu_spi.c:238:\trsmu_core_exit(rsmu);\ndrivers/mfd/rsmu_spi.c-239-}\ndrivers/mfd/rsmu_spi.c-240-\ndrivers/mfd/rsmu_spi.c:241:static const struct spi_device_id rsmu_spi_id[] = {\ndrivers/mfd/rsmu_spi.c-242-\t{ .name = \"8a34000\", .driver_data = RSMU_CM },\n--\ndrivers/mfd/rsmu_spi.c-248-};\ndrivers/mfd/rsmu_spi.c:249:MODULE_DEVICE_TABLE(spi, rsmu_spi_id);\ndrivers/mfd/rsmu_spi.c-250-\ndrivers/mfd/rsmu_spi.c:251:static const struct of_device_id rsmu_spi_of_match[] = {\ndrivers/mfd/rsmu_spi.c-252-\t{ .compatible = \"idt,8a34000\", .data = (void )RSMU_CM },\n--\ndrivers/mfd/rsmu_spi.c-258-};\ndrivers/mfd/rsmu_spi.c:259:MODULE_DEVICE_TABLE(of, rsmu_spi_of_match);\ndrivers/mfd/rsmu_spi.c-260-\ndrivers/mfd/rsmu_spi.c:261:static struct spi_driver rsmu_spi_driver = {\ndrivers/mfd/rsmu_spi.c-262-\t.driver = {\ndrivers/mfd/rsmu_spi.c:263:\t\t.name = \"rsmu-spi\",\ndrivers/mfd/rsmu_spi.c:264:\t\t.of_match_table = rsmu_spi_of_match,\ndrivers/mfd/rsmu_spi.c-265-\t},\ndrivers/mfd/rsmu_spi.c:266:\t.probe = rsmu_spi_probe,\ndrivers/mfd/rsmu_spi.c:267:\t.remove\t= rsmu_spi_remove,\ndrivers/mfd/rsmu_spi.c:268:\t.id_table = rsmu_spi_id,\ndrivers/mfd/rsmu_spi.c-269-};\ndrivers/mfd/rsmu_spi.c-270-\ndrivers/mfd/rsmu_spi.c:271:static int __init rsmu_spi_init(void)\ndrivers/mfd/rsmu_spi.c-272-{\ndrivers/mfd/rsmu_spi.c:273:\treturn spi_register_driver(\u0026rsmu_spi_driver);\ndrivers/mfd/rsmu_spi.c-274-}\ndrivers/mfd/rsmu_spi.c:275:subsys_initcall(rsmu_spi_init);\n\n" }
11/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 33419 output: 30 thoughts: 55 Thoughts: Okay, let's dive into this. Here's how I'd approach this analysis: Analyzing RSMU Device Identification Right, so I need to understand how the system identifies devices that use the `RSMU_SABRE` protocol. My initial thought is to examine the device driver code, specifically the `rsmu_i2c` and `rsmu_spi` drivers. That seems like the logical place to start. I'm thinking, "Which specific devices are recognized as `RSMU_SABRE`?" To answer that question, I'll need to look closely at the device ID tables. That means scrutinizing the `rsmu_i2c_id` and `rsmu_spi_id` data structures. These tables should contain the relevant information mapping device identifiers to the `RSMU_SABRE` protocol. I'm expecting to find a list of vendor and device IDs, or perhaps some other unique identifiers, that trigger the system to associate a device with this particular protocol. I anticipate finding this information within the ID tables.
12/2	2026/09/24 18:14	tool	grepper	0m Args: { "Expression": "RSMU_SABRE", "PathPrefix": "drivers/mfd" } Results: { "Output": "drivers/mfd/rsmu_core.c=52=int rsmu_core_init(struct rsmu_ddata rsmu)\n--\ndrivers/mfd/rsmu_core.c-60-\t\tbreak;\ndrivers/mfd/rsmu_core.c:61:\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_core.c-62-\t\tcells = rsmu_sabre_devs;\n--\ndrivers/mfd/rsmu_i2c.c-31- /\ndrivers/mfd/rsmu_i2c.c:32:#define\tRSMU_SABRE_PAGE_ADDR\t\t0x7F\ndrivers/mfd/rsmu_i2c.c:33:#define\tRSMU_SABRE_PAGE_WINDOW\t\t128\ndrivers/mfd/rsmu_i2c.c-34-\n--\ndrivers/mfd/rsmu_i2c.c=37=static const struct regmap_range_cfg rsmu_sabre_range_cfg[] = {\n--\ndrivers/mfd/rsmu_i2c.c-40-\t\t.range_max = 0x400,\ndrivers/mfd/rsmu_i2c.c:41:\t\t.selector_reg = RSMU_SABRE_PAGE_ADDR,\ndrivers/mfd/rsmu_i2c.c-42-\t\t.selector_mask = 0xFF,\n--\ndrivers/mfd/rsmu_i2c.c-44-\t\t.window_start = 0,\ndrivers/mfd/rsmu_i2c.c:45:\t\t.window_len = RSMU_SABRE_PAGE_WINDOW,\ndrivers/mfd/rsmu_i2c.c-46-\t}\n--\ndrivers/mfd/rsmu_i2c.c=49=static bool rsmu_sabre_volatile_reg(struct device dev, unsigned int reg)\n--\ndrivers/mfd/rsmu_i2c.c-51-\tswitch (reg) {\ndrivers/mfd/rsmu_i2c.c:52:\tcase RSMU_SABRE_PAGE_ADDR:\ndrivers/mfd/rsmu_i2c.c-53-\t\treturn false;\n--\ndrivers/mfd/rsmu_i2c.c=270=static int rsmu_i2c_probe(struct i2c_client client)\n--\ndrivers/mfd/rsmu_i2c.c-297-\t\tbreak;\ndrivers/mfd/rsmu_i2c.c:298:\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_i2c.c-299-\t\tcfg = \u0026rsmu_sabre_regmap_config;\n--\ndrivers/mfd/rsmu_i2c.c=330=static const struct i2c_device_id rsmu_i2c_id[] = {\n--\ndrivers/mfd/rsmu_i2c.c-333-\t{ \"8a34002\", RSMU_CM },\ndrivers/mfd/rsmu_i2c.c:334:\t{ \"82p33810\", RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c:335:\t{ \"82p33811\", RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c-336-\t{ \"8v19n850\", RSMU_SL },\n--\ndrivers/mfd/rsmu_i2c.c=342=static const struct of_device_id rsmu_i2c_of_match[] = {\n--\ndrivers/mfd/rsmu_i2c.c-345-\t{ .compatible = \"idt,8a34002\", .data = (void )RSMU_CM },\ndrivers/mfd/rsmu_i2c.c:346:\t{ .compatible = \"idt,82p33810\", .data = (void )RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c:347:\t{ .compatible = \"idt,82p33811\", .data = (void )RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c-348-\t{ .compatible = \"idt,8v19n850\", .data = (void )RSMU_SL },\n--\ndrivers/mfd/rsmu_spi.c-20-#define\tRSMU_CM_PAGE_ADDR\t\t0x7C\ndrivers/mfd/rsmu_spi.c:21:#define\tRSMU_SABRE_PAGE_ADDR\t\t0x7F\ndrivers/mfd/rsmu_spi.c-22-#define\tRSMU_PAGE_MASK\t\t\t0xFFFFFF80\n--\ndrivers/mfd/rsmu_spi.c=94=static int rsmu_write_page_register(struct rsmu_ddata rsmu, u32 reg)\n--\ndrivers/mfd/rsmu_spi.c-111-\t\tbreak;\ndrivers/mfd/rsmu_spi.c:112:\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_spi.c-113-\t\t/ Do not modify page register if reg is page register itself /\n--\ndrivers/mfd/rsmu_spi.c-115-\t\t\treturn 0;\ndrivers/mfd/rsmu_spi.c:116:\t\tpage_reg = RSMU_SABRE_PAGE_ADDR;\ndrivers/mfd/rsmu_spi.c-117-\t\tpage = reg \u0026 RSMU_PAGE_MASK;\n--\ndrivers/mfd/rsmu_spi.c=195=static int rsmu_spi_probe(struct spi_device client)\n--\ndrivers/mfd/rsmu_spi.c-215-\t\tbreak;\ndrivers/mfd/rsmu_spi.c:216:\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_spi.c-217-\t\tcfg = \u0026rsmu_sabre_regmap_config;\n--\ndrivers/mfd/rsmu_spi.c=241=static const struct spi_device_id rsmu_spi_id[] = {\n--\ndrivers/mfd/rsmu_spi.c-244-\t{ .name = \"8a34002\", .driver_data = RSMU_CM },\ndrivers/mfd/rsmu_spi.c:245:\t{ .name = \"82p33810\", .driver_data = RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c:246:\t{ .name = \"82p33811\", .driver_data = RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c-247-\t{ }\n--\ndrivers/mfd/rsmu_spi.c=251=static const struct of_device_id rsmu_spi_of_match[] = {\n--\ndrivers/mfd/rsmu_spi.c-254-\t{ .compatible = \"idt,8a34002\", .data = (void )RSMU_CM },\ndrivers/mfd/rsmu_spi.c:255:\t{ .compatible = \"idt,82p33810\", .data = (void )RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c:256:\t{ .compatible = \"idt,82p33811\", .data = (void *)RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c-257-\t{}\n" }
13/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 35660 output: 37 thoughts: 1879 Thoughts: WorthFuzzing Analysis: IDT82P33 Driver Patch Okay, so `82p33810` and `82p33811` are pointing me towards I2C or SPI devices, potentially. The initial question is whether these can be instantiated in standard fuzzing environments like QEMU or syzkaller. Does syzkaller even support these types of devices? Specifically, does it have an emulated I2C bus or some way to interact with devices via `/sys/bus/i2c/devices/.../new_device`? I should check syzkaller's sysfs and I2C support docs, or, better yet, just reread the directions on how to determine if something is worth fuzzing. Right, the guide. The primary thing to consider is reachability. Does the modified code execute in standard virtualized environments? Section 2 outlines when to return `WorthFuzzing=false`. It's only when the code falls into categories like non-executable changes or structurally unreachable hardware. Specifically, things like vendor-specific PCIe cards not emulated in QEMU. Also, drivers which are only accessed during PCI hot unplug or manual sysfs unbinding. Section 3 outlines the opposite, when to return `WorthFuzzing=true`. Now, is `ptp_idt82p33` reachable? Let's look at the patch itself to find out. Looking at the diff, it seems the patch is primarily adding checks for a `stopping` flag within `idt82p33`. It's using `mutex_lock` around critical sections. It's adding `stopping = true` in `idt82p33_ptp_clock_unregister_all` before canceling delayed works. It is also returning `-ENODEV` (Device Not Found) inside `idt82p33_enable` and `idt82p33_adjtime` if `stopping` is true, and it adds a `goto out` right after the check. Finally, it adds another stopping check in `idt82p33_extts_check`. The patch also looks like it removes `cancel_delayed_work_sync(&idt82p33->extts_work)` from `idt82p33_remove` function. Now that I've looked at the patch, the commit log should help me to determine why it was changed.
14/2	2026/09/24 18:14	tool	grepper	0m Args: { "Expression": ".", "PathPrefix": "drivers/ptp/ptp_idt82p33.c" } Results:* { "Output": "\nFull output is too long, showing 500 out of 1475 lines.\nUse more precise expression if possible.\n\ndrivers/ptp/ptp_idt82p33.c:1:// SPDX-License-Identifier: GPL-2.0\ndrivers/ptp/ptp_idt82p33.c:2://\ndrivers/ptp/ptp_idt82p33.c:3:// Copyright (C) 2018 Integrated Device Technology, Inc\ndrivers/ptp/ptp_idt82p33.c:4://\ndrivers/ptp/ptp_idt82p33.c:5:\ndrivers/ptp/ptp_idt82p33.c:6:#define pr_fmt(fmt) \"IDT_82p33xxx: \" fmt\ndrivers/ptp/ptp_idt82p33.c:7:\ndrivers/ptp/ptp_idt82p33.c:8:#include \u003clinux/firmware.h\u003e\ndrivers/ptp/ptp_idt82p33.c:9:#include \u003clinux/platform_device.h\u003e\ndrivers/ptp/ptp_idt82p33.c:10:#include \u003clinux/module.h\u003e\ndrivers/ptp/ptp_idt82p33.c:11:#include \u003clinux/ptp_clock_kernel.h\u003e\ndrivers/ptp/ptp_idt82p33.c:12:#include \u003clinux/delay.h\u003e\ndrivers/ptp/ptp_idt82p33.c:13:#include \u003clinux/jiffies.h\u003e\ndrivers/ptp/ptp_idt82p33.c:14:#include \u003clinux/kernel.h\u003e\ndrivers/ptp/ptp_idt82p33.c:15:#include \u003clinux/timekeeping.h\u003e\ndrivers/ptp/ptp_idt82p33.c:16:#include \u003clinux/bitops.h\u003e\ndrivers/ptp/ptp_idt82p33.c:17:#include \u003clinux/of.h\u003e\ndrivers/ptp/ptp_idt82p33.c:18:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/ptp/ptp_idt82p33.c:19:#include \u003clinux/mfd/idt82p33_reg.h\u003e\ndrivers/ptp/ptp_idt82p33.c:20:\ndrivers/ptp/ptp_idt82p33.c:21:#include \"ptp_private.h\"\ndrivers/ptp/ptp_idt82p33.c:22:#include \"ptp_idt82p33.h\"\ndrivers/ptp/ptp_idt82p33.c:23:\ndrivers/ptp/ptp_idt82p33.c:24:MODULE_DESCRIPTION(\"Driver for IDT 82p33xxx clock devices\");\ndrivers/ptp/ptp_idt82p33.c:25:MODULE_AUTHOR(\"IDT support-1588 \u003cIDT-support-1588@lm.renesas.com\u003e\");\ndrivers/ptp/ptp_idt82p33.c:26:MODULE_VERSION(\"1.0\");\ndrivers/ptp/ptp_idt82p33.c:27:MODULE_LICENSE(\"GPL\");\ndrivers/ptp/ptp_idt82p33.c:28:MODULE_FIRMWARE(FW_FILENAME);\ndrivers/ptp/ptp_idt82p33.c:29:\ndrivers/ptp/ptp_idt82p33.c:30:#define EXTTS_PERIOD_MS (95)\ndrivers/ptp/ptp_idt82p33.c:31:\ndrivers/ptp/ptp_idt82p33.c:32:/* Module Parameters /\ndrivers/ptp/ptp_idt82p33.c:33:static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;\ndrivers/ptp/ptp_idt82p33.c:34:module_param(phase_snap_threshold, uint, 0);\ndrivers/ptp/ptp_idt82p33.c:35:MODULE_PARM_DESC(phase_snap_threshold,\ndrivers/ptp/ptp_idt82p33.c:36:\"threshold (10000ns by default) below which adjtime would use double dco\");\ndrivers/ptp/ptp_idt82p33.c:37:\ndrivers/ptp/ptp_idt82p33.c:38:static char firmware;\ndrivers/ptp/ptp_idt82p33.c:39:module_param(firmware, charp, 0);\ndrivers/ptp/ptp_idt82p33.c:40:\ndrivers/ptp/ptp_idt82p33.c:41:static struct ptp_pin_desc pin_config[MAX_PHC_PLL][MAX_TRIG_CLK];\ndrivers/ptp/ptp_idt82p33.c:42:\ndrivers/ptp/ptp_idt82p33.c:43:static inline int idt82p33_read(struct idt82p33 idt82p33, u16 regaddr,\ndrivers/ptp/ptp_idt82p33.c:44:\t\t\t\tu8 buf, u16 count)\ndrivers/ptp/ptp_idt82p33.c:45:{\ndrivers/ptp/ptp_idt82p33.c:46:\treturn regmap_bulk_read(idt82p33-\u003eregmap, regaddr, buf, count);\ndrivers/ptp/ptp_idt82p33.c:47:}\ndrivers/ptp/ptp_idt82p33.c:48:\ndrivers/ptp/ptp_idt82p33.c:49:static inline int idt82p33_write(struct idt82p33 idt82p33, u16 regaddr,\ndrivers/ptp/ptp_idt82p33.c:50:\t\t\t\t u8 buf, u16 count)\ndrivers/ptp/ptp_idt82p33.c:51:{\ndrivers/ptp/ptp_idt82p33.c:52:\treturn regmap_bulk_write(idt82p33-\u003eregmap, regaddr, buf, count);\ndrivers/ptp/ptp_idt82p33.c:53:}\ndrivers/ptp/ptp_idt82p33.c:54:\ndrivers/ptp/ptp_idt82p33.c:55:static void idt82p33_byte_array_to_timespec(struct timespec64 ts,\ndrivers/ptp/ptp_idt82p33.c:56:\t\t\t\t\t u8 buf[TOD_BYTE_COUNT])\ndrivers/ptp/ptp_idt82p33.c:57:{\ndrivers/ptp/ptp_idt82p33.c:58:\ttime64_t sec;\ndrivers/ptp/ptp_idt82p33.c:59:\ts32 nsec;\ndrivers/ptp/ptp_idt82p33.c:60:\tu8 i;\ndrivers/ptp/ptp_idt82p33.c:61:\ndrivers/ptp/ptp_idt82p33.c:62:\tnsec = buf[3];\ndrivers/ptp/ptp_idt82p33.c:63:\tfor (i = 0; i \u003c 3; i++) {\ndrivers/ptp/ptp_idt82p33.c:64:\t\tnsec \u003c\u003c= 8;\ndrivers/ptp/ptp_idt82p33.c:65:\t\tnsec \|= buf[2 - i];\ndrivers/ptp/ptp_idt82p33.c:66:\t}\ndrivers/ptp/ptp_idt82p33.c:67:\ndrivers/ptp/ptp_idt82p33.c:68:\tsec = buf[9];\ndrivers/ptp/ptp_idt82p33.c:69:\tfor (i = 0; i \u003c 5; i++) {\ndrivers/ptp/ptp_idt82p33.c:70:\t\tsec \u003c\u003c= 8;\ndrivers/ptp/ptp_idt82p33.c:71:\t\tsec \|= buf[8 - i];\ndrivers/ptp/ptp_idt82p33.c:72:\t}\ndrivers/ptp/ptp_idt82p33.c:73:\ndrivers/ptp/ptp_idt82p33.c:74:\tts-\u003etv_sec = sec;\ndrivers/ptp/ptp_idt82p33.c:75:\tts-\u003etv_nsec = nsec;\ndrivers/ptp/ptp_idt82p33.c:76:}\ndrivers/ptp/ptp_idt82p33.c:77:\ndrivers/ptp/ptp_idt82p33.c:78:static void idt82p33_timespec_to_byte_array(struct timespec64 const ts,\ndrivers/ptp/ptp_idt82p33.c:79:\t\t\t\t\t u8 buf[TOD_BYTE_COUNT])\ndrivers/ptp/ptp_idt82p33.c:80:{\ndrivers/ptp/ptp_idt82p33.c:81:\ttime64_t sec;\ndrivers/ptp/ptp_idt82p33.c:82:\ts32 nsec;\ndrivers/ptp/ptp_idt82p33.c:83:\tu8 i;\ndrivers/ptp/ptp_idt82p33.c:84:\ndrivers/ptp/ptp_idt82p33.c:85:\tnsec = ts-\u003etv_nsec;\ndrivers/ptp/ptp_idt82p33.c:86:\tsec = ts-\u003etv_sec;\ndrivers/ptp/ptp_idt82p33.c:87:\ndrivers/ptp/ptp_idt82p33.c:88:\tfor (i = 0; i \u003c 4; i++) {\ndrivers/ptp/ptp_idt82p33.c:89:\t\tbuf[i] = nsec \u0026 0xff;\ndrivers/ptp/ptp_idt82p33.c:90:\t\tnsec \u003e\u003e= 8;\ndrivers/ptp/ptp_idt82p33.c:91:\t}\ndrivers/ptp/ptp_idt82p33.c:92:\ndrivers/ptp/ptp_idt82p33.c:93:\tfor (i = 4; i \u003c TOD_BYTE_COUNT; i++) {\ndrivers/ptp/ptp_idt82p33.c:94:\t\tbuf[i] = sec \u0026 0xff;\ndrivers/ptp/ptp_idt82p33.c:95:\t\tsec \u003e\u003e= 8;\ndrivers/ptp/ptp_idt82p33.c:96:\t}\ndrivers/ptp/ptp_idt82p33.c:97:}\ndrivers/ptp/ptp_idt82p33.c:98:\ndrivers/ptp/ptp_idt82p33.c:99:static int idt82p33_dpll_set_mode(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:100:\t\t\t\t enum pll_mode mode)\ndrivers/ptp/ptp_idt82p33.c:101:{\ndrivers/ptp/ptp_idt82p33.c:102:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:103:\tu8 dpll_mode;\ndrivers/ptp/ptp_idt82p33.c:104:\tint err;\ndrivers/ptp/ptp_idt82p33.c:105:\ndrivers/ptp/ptp_idt82p33.c:106:\tif (channel-\u003epll_mode == mode)\ndrivers/ptp/ptp_idt82p33.c:107:\t\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:108:\ndrivers/ptp/ptp_idt82p33.c:109:\terr = idt82p33_read(idt82p33, channel-\u003edpll_mode_cnfg,\ndrivers/ptp/ptp_idt82p33.c:110:\t\t\t \u0026dpll_mode, sizeof(dpll_mode));\ndrivers/ptp/ptp_idt82p33.c:111:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:112:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:113:\ndrivers/ptp/ptp_idt82p33.c:114:\tdpll_mode \u0026= ~(PLL_MODE_MASK \u003c\u003c PLL_MODE_SHIFT);\ndrivers/ptp/ptp_idt82p33.c:115:\ndrivers/ptp/ptp_idt82p33.c:116:\tdpll_mode \|= (mode \u003c\u003c PLL_MODE_SHIFT);\ndrivers/ptp/ptp_idt82p33.c:117:\ndrivers/ptp/ptp_idt82p33.c:118:\terr = idt82p33_write(idt82p33, channel-\u003edpll_mode_cnfg,\ndrivers/ptp/ptp_idt82p33.c:119:\t\t\t \u0026dpll_mode, sizeof(dpll_mode));\ndrivers/ptp/ptp_idt82p33.c:120:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:121:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:122:\ndrivers/ptp/ptp_idt82p33.c:123:\tchannel-\u003epll_mode = mode;\ndrivers/ptp/ptp_idt82p33.c:124:\ndrivers/ptp/ptp_idt82p33.c:125:\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:126:}\ndrivers/ptp/ptp_idt82p33.c:127:\ndrivers/ptp/ptp_idt82p33.c:128:static int idt82p33_set_tod_trigger(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:129:\t\t\t\t u8 trigger, bool write)\ndrivers/ptp/ptp_idt82p33.c:130:{\ndrivers/ptp/ptp_idt82p33.c:131:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:132:\tint err;\ndrivers/ptp/ptp_idt82p33.c:133:\tu8 cfg;\ndrivers/ptp/ptp_idt82p33.c:134:\ndrivers/ptp/ptp_idt82p33.c:135:\tif (trigger \u003e WR_TRIG_SEL_MAX)\ndrivers/ptp/ptp_idt82p33.c:136:\t\treturn -EINVAL;\ndrivers/ptp/ptp_idt82p33.c:137:\ndrivers/ptp/ptp_idt82p33.c:138:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c:139:\t\t\t \u0026cfg, sizeof(cfg));\ndrivers/ptp/ptp_idt82p33.c:140:\ndrivers/ptp/ptp_idt82p33.c:141:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:142:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:143:\ndrivers/ptp/ptp_idt82p33.c:144:\tif (write == true)\ndrivers/ptp/ptp_idt82p33.c:145:\t\ttrigger = (trigger \u003c\u003c WRITE_TRIGGER_SHIFT) \|\ndrivers/ptp/ptp_idt82p33.c:146:\t\t\t (cfg \u0026 READ_TRIGGER_MASK);\ndrivers/ptp/ptp_idt82p33.c:147:\telse\ndrivers/ptp/ptp_idt82p33.c:148:\t\ttrigger = (trigger \u003c\u003c READ_TRIGGER_SHIFT) \|\ndrivers/ptp/ptp_idt82p33.c:149:\t\t\t (cfg \u0026 WRITE_TRIGGER_MASK);\ndrivers/ptp/ptp_idt82p33.c:150:\ndrivers/ptp/ptp_idt82p33.c:151:\treturn idt82p33_write(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c:152:\t\t\t \u0026trigger, sizeof(trigger));\ndrivers/ptp/ptp_idt82p33.c:153:}\ndrivers/ptp/ptp_idt82p33.c:154:\ndrivers/ptp/ptp_idt82p33.c:155:static int idt82p33_get_extts(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:156:\t\t\t struct timespec64 ts)\ndrivers/ptp/ptp_idt82p33.c:157:{\ndrivers/ptp/ptp_idt82p33.c:158:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:159:\tu8 buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:160:\tint err;\ndrivers/ptp/ptp_idt82p33.c:161:\ndrivers/ptp/ptp_idt82p33.c:162:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c:163:\ndrivers/ptp/ptp_idt82p33.c:164:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:165:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:166:\ndrivers/ptp/ptp_idt82p33.c:167:\t/ Since trigger is not self clearing itself, we have to poll tod_sts /\ndrivers/ptp/ptp_idt82p33.c:168:\tif (memcmp(buf, channel-\u003eextts_tod_sts, TOD_BYTE_COUNT) == 0)\ndrivers/ptp/ptp_idt82p33.c:169:\t\treturn -EAGAIN;\ndrivers/ptp/ptp_idt82p33.c:170:\ndrivers/ptp/ptp_idt82p33.c:171:\tmemcpy(channel-\u003eextts_tod_sts, buf, TOD_BYTE_COUNT);\ndrivers/ptp/ptp_idt82p33.c:172:\ndrivers/ptp/ptp_idt82p33.c:173:\tidt82p33_byte_array_to_timespec(ts, buf);\ndrivers/ptp/ptp_idt82p33.c:174:\ndrivers/ptp/ptp_idt82p33.c:175:\tif (channel-\u003ediscard_next_extts) {\ndrivers/ptp/ptp_idt82p33.c:176:\t\tchannel-\u003ediscard_next_extts = false;\ndrivers/ptp/ptp_idt82p33.c:177:\t\treturn -EAGAIN;\ndrivers/ptp/ptp_idt82p33.c:178:\t}\ndrivers/ptp/ptp_idt82p33.c:179:\ndrivers/ptp/ptp_idt82p33.c:180:\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:181:}\ndrivers/ptp/ptp_idt82p33.c:182:\ndrivers/ptp/ptp_idt82p33.c:183:static int map_ref_to_tod_trig_sel(int ref, u8 trigger)\ndrivers/ptp/ptp_idt82p33.c:184:{\ndrivers/ptp/ptp_idt82p33.c:185:\tint err = 0;\ndrivers/ptp/ptp_idt82p33.c:186:\ndrivers/ptp/ptp_idt82p33.c:187:\tswitch (ref) {\ndrivers/ptp/ptp_idt82p33.c:188:\tcase 0:\ndrivers/ptp/ptp_idt82p33.c:189:\t\ttrigger = HW_TOD_TRIG_SEL_IN12;\ndrivers/ptp/ptp_idt82p33.c:190:\t\tbreak;\ndrivers/ptp/ptp_idt82p33.c:191:\tcase 1:\ndrivers/ptp/ptp_idt82p33.c:192:\t\ttrigger = HW_TOD_TRIG_SEL_IN13;\ndrivers/ptp/ptp_idt82p33.c:193:\t\tbreak;\ndrivers/ptp/ptp_idt82p33.c:194:\tcase 2:\ndrivers/ptp/ptp_idt82p33.c:195:\t\ttrigger = HW_TOD_TRIG_SEL_IN14;\ndrivers/ptp/ptp_idt82p33.c:196:\t\tbreak;\ndrivers/ptp/ptp_idt82p33.c:197:\tdefault:\ndrivers/ptp/ptp_idt82p33.c:198:\t\terr = -EINVAL;\ndrivers/ptp/ptp_idt82p33.c:199:\t}\ndrivers/ptp/ptp_idt82p33.c:200:\ndrivers/ptp/ptp_idt82p33.c:201:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:202:}\ndrivers/ptp/ptp_idt82p33.c:203:\ndrivers/ptp/ptp_idt82p33.c:204:static bool is_one_shot(u8 mask)\ndrivers/ptp/ptp_idt82p33.c:205:{\ndrivers/ptp/ptp_idt82p33.c:206:\t/ Treat single bit PLL masks as continuous trigger /\ndrivers/ptp/ptp_idt82p33.c:207:\tif ((mask == 1) \|\| (mask == 2))\ndrivers/ptp/ptp_idt82p33.c:208:\t\treturn false;\ndrivers/ptp/ptp_idt82p33.c:209:\telse\ndrivers/ptp/ptp_idt82p33.c:210:\t\treturn true;\ndrivers/ptp/ptp_idt82p33.c:211:}\ndrivers/ptp/ptp_idt82p33.c:212:\ndrivers/ptp/ptp_idt82p33.c:213:static int arm_tod_read_with_trigger(struct idt82p33_channel channel, u8 trigger)\ndrivers/ptp/ptp_idt82p33.c:214:{\ndrivers/ptp/ptp_idt82p33.c:215:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:216:\tu8 buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:217:\tint err;\ndrivers/ptp/ptp_idt82p33.c:218:\ndrivers/ptp/ptp_idt82p33.c:219:\t/ Remember the current tod_sts before setting the trigger /\ndrivers/ptp/ptp_idt82p33.c:220:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c:221:\ndrivers/ptp/ptp_idt82p33.c:222:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:223:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:224:\ndrivers/ptp/ptp_idt82p33.c:225:\tmemcpy(channel-\u003eextts_tod_sts, buf, TOD_BYTE_COUNT);\ndrivers/ptp/ptp_idt82p33.c:226:\ndrivers/ptp/ptp_idt82p33.c:227:\terr = idt82p33_set_tod_trigger(channel, trigger, false);\ndrivers/ptp/ptp_idt82p33.c:228:\ndrivers/ptp/ptp_idt82p33.c:229:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:230:\t\tdev_err(idt82p33-\u003edev, \"%s: err = %d\", __func__, err);\ndrivers/ptp/ptp_idt82p33.c:231:\ndrivers/ptp/ptp_idt82p33.c:232:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:233:}\ndrivers/ptp/ptp_idt82p33.c:234:\ndrivers/ptp/ptp_idt82p33.c:235:static int idt82p33_extts_enable(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:236:\t\t\t\t struct ptp_clock_request rq, int on)\ndrivers/ptp/ptp_idt82p33.c:237:{\ndrivers/ptp/ptp_idt82p33.c:238:\tu8 index = rq-\u003eextts.index;\ndrivers/ptp/ptp_idt82p33.c:239:\tstruct idt82p33 idt82p33;\ndrivers/ptp/ptp_idt82p33.c:240:\tu8 mask = 1 \u003c\u003c index;\ndrivers/ptp/ptp_idt82p33.c:241:\tint err = 0;\ndrivers/ptp/ptp_idt82p33.c:242:\tu8 old_mask;\ndrivers/ptp/ptp_idt82p33.c:243:\tu8 trigger;\ndrivers/ptp/ptp_idt82p33.c:244:\tint ref;\ndrivers/ptp/ptp_idt82p33.c:245:\ndrivers/ptp/ptp_idt82p33.c:246:\tidt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:247:\told_mask = idt82p33-\u003eextts_mask;\ndrivers/ptp/ptp_idt82p33.c:248:\ndrivers/ptp/ptp_idt82p33.c:249:\tif (index \u003e= MAX_PHC_PLL)\ndrivers/ptp/ptp_idt82p33.c:250:\t\treturn -EINVAL;\ndrivers/ptp/ptp_idt82p33.c:251:\ndrivers/ptp/ptp_idt82p33.c:252:\tif (on) {\ndrivers/ptp/ptp_idt82p33.c:253:\t\t/* Return if it was already enabled /\ndrivers/ptp/ptp_idt82p33.c:254:\t\tif (idt82p33-\u003eextts_mask \u0026 mask)\ndrivers/ptp/ptp_idt82p33.c:255:\t\t\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:256:\ndrivers/ptp/ptp_idt82p33.c:257:\t\t/ Use the pin configured for the channel /\ndrivers/ptp/ptp_idt82p33.c:258:\t\tref = ptp_find_pin(channel-\u003eptp_clock, PTP_PF_EXTTS, channel-\u003eplln);\ndrivers/ptp/ptp_idt82p33.c:259:\ndrivers/ptp/ptp_idt82p33.c:260:\t\tif (ref \u003c 0) {\ndrivers/ptp/ptp_idt82p33.c:261:\t\t\tdev_err(idt82p33-\u003edev, \"%s: No valid pin found for Pll%d!\\n\",\ndrivers/ptp/ptp_idt82p33.c:262:\t\t\t\t__func__, channel-\u003eplln);\ndrivers/ptp/ptp_idt82p33.c:263:\t\t\treturn -EBUSY;\ndrivers/ptp/ptp_idt82p33.c:264:\t\t}\ndrivers/ptp/ptp_idt82p33.c:265:\ndrivers/ptp/ptp_idt82p33.c:266:\t\terr = map_ref_to_tod_trig_sel(ref, \u0026trigger);\ndrivers/ptp/ptp_idt82p33.c:267:\ndrivers/ptp/ptp_idt82p33.c:268:\t\tif (err) {\ndrivers/ptp/ptp_idt82p33.c:269:\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c:270:\t\t\t\t\"%s: Unsupported ref %d!\\n\", __func__, ref);\ndrivers/ptp/ptp_idt82p33.c:271:\t\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:272:\t\t}\ndrivers/ptp/ptp_idt82p33.c:273:\ndrivers/ptp/ptp_idt82p33.c:274:\t\terr = arm_tod_read_with_trigger(\u0026idt82p33-\u003echannel[index], trigger);\ndrivers/ptp/ptp_idt82p33.c:275:\ndrivers/ptp/ptp_idt82p33.c:276:\t\tif (err == 0) {\ndrivers/ptp/ptp_idt82p33.c:277:\t\t\tidt82p33-\u003eextts_mask \|= mask;\ndrivers/ptp/ptp_idt82p33.c:278:\t\t\tidt82p33-\u003echannel[index].tod_trigger = trigger;\ndrivers/ptp/ptp_idt82p33.c:279:\t\t\tidt82p33-\u003eevent_channel[index] = channel;\ndrivers/ptp/ptp_idt82p33.c:280:\t\t\tidt82p33-\u003eextts_single_shot = is_one_shot(idt82p33-\u003eextts_mask);\ndrivers/ptp/ptp_idt82p33.c:281:\ndrivers/ptp/ptp_idt82p33.c:282:\t\t\tif (old_mask)\ndrivers/ptp/ptp_idt82p33.c:283:\t\t\t\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:284:\ndrivers/ptp/ptp_idt82p33.c:285:\t\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\ndrivers/ptp/ptp_idt82p33.c:286:\t\t\t\t\t msecs_to_jiffies(EXTTS_PERIOD_MS));\ndrivers/ptp/ptp_idt82p33.c:287:\t\t}\ndrivers/ptp/ptp_idt82p33.c:288:\t} else {\ndrivers/ptp/ptp_idt82p33.c:289:\t\tidt82p33-\u003eextts_mask \u0026= ~mask;\ndrivers/ptp/ptp_idt82p33.c:290:\t\tidt82p33-\u003eextts_single_shot = is_one_shot(idt82p33-\u003eextts_mask);\ndrivers/ptp/ptp_idt82p33.c:291:\ndrivers/ptp/ptp_idt82p33.c:292:\t\tif (idt82p33-\u003eextts_mask == 0)\ndrivers/ptp/ptp_idt82p33.c:293:\t\t\tcancel_delayed_work(\u0026idt82p33-\u003eextts_work);\ndrivers/ptp/ptp_idt82p33.c:294:\t}\ndrivers/ptp/ptp_idt82p33.c:295:\ndrivers/ptp/ptp_idt82p33.c:296:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:297:}\ndrivers/ptp/ptp_idt82p33.c:298:\ndrivers/ptp/ptp_idt82p33.c:299:static int idt82p33_extts_check_channel(struct idt82p33 idt82p33, u8 todn)\ndrivers/ptp/ptp_idt82p33.c:300:{\ndrivers/ptp/ptp_idt82p33.c:301:\tstruct idt82p33_channel event_channel;\ndrivers/ptp/ptp_idt82p33.c:302:\tstruct ptp_clock_event event;\ndrivers/ptp/ptp_idt82p33.c:303:\tstruct timespec64 ts;\ndrivers/ptp/ptp_idt82p33.c:304:\tint err;\ndrivers/ptp/ptp_idt82p33.c:305:\ndrivers/ptp/ptp_idt82p33.c:306:\terr = idt82p33_get_extts(\u0026idt82p33-\u003echannel[todn], \u0026ts);\ndrivers/ptp/ptp_idt82p33.c:307:\tif (err == 0) {\ndrivers/ptp/ptp_idt82p33.c:308:\t\tevent_channel = idt82p33-\u003eevent_channel[todn];\ndrivers/ptp/ptp_idt82p33.c:309:\t\tevent.type = PTP_CLOCK_EXTTS;\ndrivers/ptp/ptp_idt82p33.c:310:\t\tevent.index = todn;\ndrivers/ptp/ptp_idt82p33.c:311:\t\tevent.timestamp = timespec64_to_ns(\u0026ts);\ndrivers/ptp/ptp_idt82p33.c:312:\t\tptp_clock_event(event_channel-\u003eptp_clock,\ndrivers/ptp/ptp_idt82p33.c:313:\t\t\t\t\u0026event);\ndrivers/ptp/ptp_idt82p33.c:314:\t}\ndrivers/ptp/ptp_idt82p33.c:315:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:316:}\ndrivers/ptp/ptp_idt82p33.c:317:\ndrivers/ptp/ptp_idt82p33.c:318:static u8 idt82p33_extts_enable_mask(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:319:\t\t\t\t u8 extts_mask, bool enable)\ndrivers/ptp/ptp_idt82p33.c:320:{\ndrivers/ptp/ptp_idt82p33.c:321:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:322:\tu8 trigger = channel-\u003etod_trigger;\ndrivers/ptp/ptp_idt82p33.c:323:\tu8 mask;\ndrivers/ptp/ptp_idt82p33.c:324:\tint err;\ndrivers/ptp/ptp_idt82p33.c:325:\tint i;\ndrivers/ptp/ptp_idt82p33.c:326:\ndrivers/ptp/ptp_idt82p33.c:327:\tif (extts_mask == 0)\ndrivers/ptp/ptp_idt82p33.c:328:\t\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:329:\ndrivers/ptp/ptp_idt82p33.c:330:\tif (enable == false)\ndrivers/ptp/ptp_idt82p33.c:331:\t\tcancel_delayed_work_sync(\u0026idt82p33-\u003eextts_work);\ndrivers/ptp/ptp_idt82p33.c:332:\ndrivers/ptp/ptp_idt82p33.c:333:\tfor (i = 0; i \u003c MAX_PHC_PLL; i++) {\ndrivers/ptp/ptp_idt82p33.c:334:\t\tmask = 1 \u003c\u003c i;\ndrivers/ptp/ptp_idt82p33.c:335:\ndrivers/ptp/ptp_idt82p33.c:336:\t\tif ((extts_mask \u0026 mask) == 0)\ndrivers/ptp/ptp_idt82p33.c:337:\t\t\tcontinue;\ndrivers/ptp/ptp_idt82p33.c:338:\ndrivers/ptp/ptp_idt82p33.c:339:\t\tif (enable) {\ndrivers/ptp/ptp_idt82p33.c:340:\t\t\terr = arm_tod_read_with_trigger(\u0026idt82p33-\u003echannel[i], trigger);\ndrivers/ptp/ptp_idt82p33.c:341:\t\t\tif (err)\ndrivers/ptp/ptp_idt82p33.c:342:\t\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c:343:\t\t\t\t\t\"%s: Arm ToD read trigger failed, err = %d\",\ndrivers/ptp/ptp_idt82p33.c:344:\t\t\t\t\t__func__, err);\ndrivers/ptp/ptp_idt82p33.c:345:\t\t} else {\ndrivers/ptp/ptp_idt82p33.c:346:\t\t\terr = idt82p33_extts_check_channel(idt82p33, i);\ndrivers/ptp/ptp_idt82p33.c:347:\t\t\tif (err == 0 \u0026\u0026 idt82p33-\u003eextts_single_shot)\ndrivers/ptp/ptp_idt82p33.c:348:\t\t\t\t/ trigger happened so we won't re-enable it /\ndrivers/ptp/ptp_idt82p33.c:349:\t\t\t\textts_mask \u0026= ~mask;\ndrivers/ptp/ptp_idt82p33.c:350:\t\t}\ndrivers/ptp/ptp_idt82p33.c:351:\t}\ndrivers/ptp/ptp_idt82p33.c:352:\ndrivers/ptp/ptp_idt82p33.c:353:\tif (enable)\ndrivers/ptp/ptp_idt82p33.c:354:\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\ndrivers/ptp/ptp_idt82p33.c:355:\t\t\t\t msecs_to_jiffies(EXTTS_PERIOD_MS));\ndrivers/ptp/ptp_idt82p33.c:356:\ndrivers/ptp/ptp_idt82p33.c:357:\treturn extts_mask;\ndrivers/ptp/ptp_idt82p33.c:358:}\ndrivers/ptp/ptp_idt82p33.c:359:\ndrivers/ptp/ptp_idt82p33.c:360:static int _idt82p33_gettime(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:361:\t\t\t struct timespec64 ts)\ndrivers/ptp/ptp_idt82p33.c:362:{\ndrivers/ptp/ptp_idt82p33.c:363:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:364:\tu8 old_mask = idt82p33-\u003eextts_mask;\ndrivers/ptp/ptp_idt82p33.c:365:\tu8 buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:366:\tu8 new_mask = 0;\ndrivers/ptp/ptp_idt82p33.c:367:\tint err;\ndrivers/ptp/ptp_idt82p33.c:368:\ndrivers/ptp/ptp_idt82p33.c:369:\t/* Disable extts /\ndrivers/ptp/ptp_idt82p33.c:370:\tif (old_mask)\ndrivers/ptp/ptp_idt82p33.c:371:\t\tnew_mask = idt82p33_extts_enable_mask(channel, old_mask, false);\ndrivers/ptp/ptp_idt82p33.c:372:\ndrivers/ptp/ptp_idt82p33.c:373:\terr = idt82p33_set_tod_trigger(channel, HW_TOD_RD_TRIG_SEL_LSB_TOD_STS,\ndrivers/ptp/ptp_idt82p33.c:374:\t\t\t\t false);\ndrivers/ptp/ptp_idt82p33.c:375:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:376:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:377:\ndrivers/ptp/ptp_idt82p33.c:378:\tchannel-\u003ediscard_next_extts = true;\ndrivers/ptp/ptp_idt82p33.c:379:\ndrivers/ptp/ptp_idt82p33.c:380:\tif (idt82p33-\u003ecalculate_overhead_flag)\ndrivers/ptp/ptp_idt82p33.c:381:\t\tidt82p33-\u003estart_time = ktime_get_raw();\ndrivers/ptp/ptp_idt82p33.c:382:\ndrivers/ptp/ptp_idt82p33.c:383:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c:384:\ndrivers/ptp/ptp_idt82p33.c:385:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:386:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:387:\ndrivers/ptp/ptp_idt82p33.c:388:\t/ Re-enable extts /\ndrivers/ptp/ptp_idt82p33.c:389:\tif (new_mask)\ndrivers/ptp/ptp_idt82p33.c:390:\t\tidt82p33_extts_enable_mask(channel, new_mask, true);\ndrivers/ptp/ptp_idt82p33.c:391:\ndrivers/ptp/ptp_idt82p33.c:392:\tidt82p33_byte_array_to_timespec(ts, buf);\ndrivers/ptp/ptp_idt82p33.c:393:\ndrivers/ptp/ptp_idt82p33.c:394:\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:395:}\ndrivers/ptp/ptp_idt82p33.c:396:\ndrivers/ptp/ptp_idt82p33.c:397:/\ndrivers/ptp/ptp_idt82p33.c:398: * TOD Trigger:\ndrivers/ptp/ptp_idt82p33.c:399: * Bits[7:4] Write 0x9, MSB write\ndrivers/ptp/ptp_idt82p33.c:400: * Bits[3:0] Read 0x9, LSB read\ndrivers/ptp/ptp_idt82p33.c:401: /\ndrivers/ptp/ptp_idt82p33.c:402:\ndrivers/ptp/ptp_idt82p33.c:403:static int _idt82p33_settime(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:404:\t\t\t struct timespec64 const ts)\ndrivers/ptp/ptp_idt82p33.c:405:{\ndrivers/ptp/ptp_idt82p33.c:406:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:407:\tstruct timespec64 local_ts = ts;\ndrivers/ptp/ptp_idt82p33.c:408:\tchar buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:409:\ts64 dynamic_overhead_ns;\ndrivers/ptp/ptp_idt82p33.c:410:\tint err;\ndrivers/ptp/ptp_idt82p33.c:411:\tu8 i;\ndrivers/ptp/ptp_idt82p33.c:412:\ndrivers/ptp/ptp_idt82p33.c:413:\terr = idt82p33_set_tod_trigger(channel, HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,\ndrivers/ptp/ptp_idt82p33.c:414:\t\t\t\t true);\ndrivers/ptp/ptp_idt82p33.c:415:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:416:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:417:\ndrivers/ptp/ptp_idt82p33.c:418:\tchannel-\u003ediscard_next_extts = true;\ndrivers/ptp/ptp_idt82p33.c:419:\ndrivers/ptp/ptp_idt82p33.c:420:\tif (idt82p33-\u003ecalculate_overhead_flag) {\ndrivers/ptp/ptp_idt82p33.c:421:\t\tdynamic_overhead_ns = ktime_to_ns(ktime_get_raw())\ndrivers/ptp/ptp_idt82p33.c:422:\t\t\t\t\t- ktime_to_ns(idt82p33-\u003estart_time);\ndrivers/ptp/ptp_idt82p33.c:423:\ndrivers/ptp/ptp_idt82p33.c:424:\t\ttimespec64_add_ns(\u0026local_ts, dynamic_overhead_ns);\ndrivers/ptp/ptp_idt82p33.c:425:\ndrivers/ptp/ptp_idt82p33.c:426:\t\tidt82p33-\u003ecalculate_overhead_flag = 0;\ndrivers/ptp/ptp_idt82p33.c:427:\t}\ndrivers/ptp/ptp_idt82p33.c:428:\ndrivers/ptp/ptp_idt82p33.c:429:\tidt82p33_timespec_to_byte_array(\u0026local_ts, buf);\ndrivers/ptp/ptp_idt82p33.c:430:\ndrivers/ptp/ptp_idt82p33.c:431:\t/\ndrivers/ptp/ptp_idt82p33.c:432:\t * Store the new time value.\ndrivers/ptp/ptp_idt82p33.c:433:\t /\ndrivers/ptp/ptp_idt82p33.c:434:\tfor (i = 0; i \u003c TOD_BYTE_COUNT; i++) {\ndrivers/ptp/ptp_idt82p33.c:435:\t\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_cnfg + i,\ndrivers/ptp/ptp_idt82p33.c:436:\t\t\t\t \u0026buf[i], sizeof(buf[i]));\ndrivers/ptp/ptp_idt82p33.c:437:\t\tif (err)\ndrivers/ptp/ptp_idt82p33.c:438:\t\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:439:\t}\ndrivers/ptp/ptp_idt82p33.c:440:\ndrivers/ptp/ptp_idt82p33.c:441:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:442:}\ndrivers/ptp/ptp_idt82p33.c:443:\ndrivers/ptp/ptp_idt82p33.c:444:static int _idt82p33_adjtime_immediate(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:445:\t\t\t\t s64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c:446:{\ndrivers/ptp/ptp_idt82p33.c:447:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:448:\tstruct timespec64 ts;\ndrivers/ptp/ptp_idt82p33.c:449:\ts64 now_ns;\ndrivers/ptp/ptp_idt82p33.c:450:\tint err;\ndrivers/ptp/ptp_idt82p33.c:451:\ndrivers/ptp/ptp_idt82p33.c:452:\tidt82p33-\u003ecalculate_overhead_flag = 1;\ndrivers/ptp/ptp_idt82p33.c:453:\ndrivers/ptp/ptp_idt82p33.c:454:\terr = _idt82p33_gettime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c:455:\ndrivers/ptp/ptp_idt82p33.c:456:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:457:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:458:\ndrivers/ptp/ptp_idt82p33.c:459:\tnow_ns = timespec64_to_ns(\u0026ts);\ndrivers/ptp/ptp_idt82p33.c:460:\tnow_ns += delta_ns + idt82p33-\u003etod_write_overhead_ns;\ndrivers/ptp/ptp_idt82p33.c:461:\ndrivers/ptp/ptp_idt82p33.c:462:\tts = ns_to_timespec64(now_ns);\ndrivers/ptp/ptp_idt82p33.c:463:\ndrivers/ptp/ptp_idt82p33.c:464:\terr = _idt82p33_settime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c:465:\ndrivers/ptp/ptp_idt82p33.c:466:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:467:}\ndrivers/ptp/ptp_idt82p33.c:468:\ndrivers/ptp/ptp_idt82p33.c:469:static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c:470:\t\t\t\t\t\ts64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c:471:{\ndrivers/ptp/ptp_idt82p33.c:472:\tstruct idt82p33 idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:473:\tchar buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:474:\tstruct timespec64 ts;\ndrivers/ptp/ptp_idt82p33.c:475:\tconst u8 delay_ns = 32;\ndrivers/ptp/ptp_idt82p33.c:476:\ts32 remainder;\ndrivers/ptp/ptp_idt82p33.c:477:\ts64 ns;\ndrivers/ptp/ptp_idt82p33.c:478:\tint err;\ndrivers/ptp/ptp_idt82p33.c:479:\ndrivers/ptp/ptp_idt82p33.c:480:\terr = _idt82p33_gettime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c:481:\ndrivers/ptp/ptp_idt82p33.c:482:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:483:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:484:\ndrivers/ptp/ptp_idt82p33.c:485:\tif (ts.tv_nsec \u003e (NSEC_PER_SEC - 5 NSEC_PER_MSEC)) {\ndrivers/ptp/ptp_idt82p33.c:486:\t\t/* Too close to miss next trigger, so skip it /\ndrivers/ptp/ptp_idt82p33.c:487:\t\tmdelay(6);\ndrivers/ptp/ptp_idt82p33.c:488:\t\tns = (ts.tv_sec + 2) NSEC_PER_SEC + delta_ns + delay_ns;\ndrivers/ptp/ptp_idt82p33.c:489:\t} else\ndrivers/ptp/ptp_idt82p33.c:490:\t\tns = (ts.tv_sec + 1) * NSEC_PER_SEC + delta_ns + delay_ns;\ndrivers/ptp/ptp_idt82p33.c:491:\ndrivers/ptp/ptp_idt82p33.c:492:\tts = ns_to_timespec64(ns);\ndrivers/ptp/ptp_idt82p33.c:493:\tidt82p33_timespec_to_byte_array(\u0026ts, buf);\ndrivers/ptp/ptp_idt82p33.c:494:\ndrivers/ptp/ptp_idt82p33.c:495:\t/\ndrivers/ptp/ptp_idt82p33.c:496:\t Store the new time value.\ndrivers/ptp/ptp_idt82p33.c:497:\t */\ndrivers/ptp/ptp_idt82p33.c:498:\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_cnfg, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c:499:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:500:\t\treturn err;\n\n" }
15/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 53541 output: 32 thoughts: 302 Thoughts: Analyzing the IDT 82p33 PTP Driver Okay, let's dive into this `drivers/ptp/ptp_idt82p33.c` file. It looks like we're dealing with the PTP hardware clock driver for the IDT 82p33xxx family. My initial scan points to functions like `idt82p33_ptp_clock_unregister_all`, `idt82p33_enable`, `idt82p33_adjtime`, `idt82p33_extts_check`, and `idt82p33_remove`, which are all standard for a driver of this type. But, I need to understand the probing sequence for this device... that's where the real magic happens, right? Alright, let me examine the initialization process. Ah, found it! Lines 1419-1427 are key. We have a "cold reset" before loading the firmware, followed by a firmware load via `idt82p33_load_firmware`. It looks like it handles some error checking here. Interesting. Then there's a "soft reset" after the firmware is loaded. This sequence is pretty standard for these devices, but I need to understand what those resets actually do. Okay, let's look at `idt82p33_reset` and `idt82p33_enable_channel` to understand those operations. That's the key to understanding how this driver interacts with the hardware.
16/2	2026/09/24 18:14	tool	grepper	0m Args: { "Expression": "idt82p33_reset", "PathPrefix": "drivers/ptp" } Results: { "Output": "drivers/ptp/ptp_idt82p33.c=1207=static int idt82p33_enable_channel(struct idt82p33 idt82p33, u32 index)\n--\ndrivers/ptp/ptp_idt82p33.c-1260-\ndrivers/ptp/ptp_idt82p33.c:1261:static int idt82p33_reset(struct idt82p33 idt82p33, bool cold)\ndrivers/ptp/ptp_idt82p33.c-1262-{\n--\ndrivers/ptp/ptp_idt82p33.c=1392=static int idt82p33_probe(struct platform_device pdev)\n--\ndrivers/ptp/ptp_idt82p33.c-1418-\t/ cold reset before loading firmware /\ndrivers/ptp/ptp_idt82p33.c:1419:\tidt82p33_reset(idt82p33, true);\ndrivers/ptp/ptp_idt82p33.c-1420-\n--\ndrivers/ptp/ptp_idt82p33.c-1426-\t/ soft reset after loading firmware */\ndrivers/ptp/ptp_idt82p33.c:1427:\tidt82p33_reset(idt82p33, false);\ndrivers/ptp/ptp_idt82p33.c-1428-\n" }
17/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 54622 output: 45 thoughts: 40 Thoughts: Here's my summary, as if I were thinking these thoughts: Analyzing IDT82P33 Reset and Channel Enable Routines Okay, let's dive into this code. I need to get a clear picture of how this IDT82P33 chip is being managed. Specifically, I'm going to focus on the `idt82p33_reset` and `idt82p33_enable_channel` functions, and I'm guessing the relevant interactions are somewhere between lines 1207 and 1300. That range is a good place to start, given the usual organization of these kinds of drivers. I'm looking for the sequence of operations. This reset call is critical. It sets the baseline state, initializes the registers, gets the device in a known, safe starting state. Then, I need to understand how the channel is subsequently enabled; what's involved in that process? What resources are allocated or configured during the enable, and what's the general sequence? That's likely where the core interactions happen. Time to get to work.
18/2	2026/09/24 18:14	tool	read-file	0m Args: { "File": "drivers/ptp/ptp_idt82p33.c", "FirstLine": 1205, "LineCount": 80 } Results: { "Contents": "1205:\t}\n1206:\t\n1207:\tstatic int idt82p33_enable_channel(struct idt82p33 idt82p33, u32 index)\n1208:\t{\n1209:\t\tstruct idt82p33_channel channel;\n1210:\t\tint err;\n1211:\t\n1212:\t\tif (!(index \u003c MAX_PHC_PLL))\n1213:\t\t\treturn -EINVAL;\n1214:\t\n1215:\t\tchannel = \u0026idt82p33-\u003echannel[index];\n1216:\t\n1217:\t\terr = idt82p33_channel_init(idt82p33, index);\n1218:\t\tif (err) {\n1219:\t\t\tdev_err(idt82p33-\u003edev,\n1220:\t\t\t\t\"Channel_init failed in %s with err %d!\\n\",\n1221:\t\t\t\t__func__, err);\n1222:\t\t\treturn err;\n1223:\t\t}\n1224:\t\n1225:\t\tidt82p33_caps_init(index, \u0026channel-\u003ecaps,\n1226:\t\t\t\t pin_config[index], MAX_TRIG_CLK);\n1227:\t\n1228:\t\tchannel-\u003eptp_clock = ptp_clock_register(\u0026channel-\u003ecaps, NULL);\n1229:\t\n1230:\t\tif (IS_ERR(channel-\u003eptp_clock)) {\n1231:\t\t\terr = PTR_ERR(channel-\u003eptp_clock);\n1232:\t\t\tchannel-\u003eptp_clock = NULL;\n1233:\t\t\treturn err;\n1234:\t\t}\n1235:\t\n1236:\t\tif (!channel-\u003eptp_clock)\n1237:\t\t\treturn -ENOTSUPP;\n1238:\t\n1239:\t\terr = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);\n1240:\t\tif (err) {\n1241:\t\t\tdev_err(idt82p33-\u003edev,\n1242:\t\t\t\t\"Dpll_set_mode failed in %s with err %d!\\n\",\n1243:\t\t\t\t__func__, err);\n1244:\t\t\treturn err;\n1245:\t\t}\n1246:\t\n1247:\t\terr = idt82p33_enable_tod(channel);\n1248:\t\tif (err) {\n1249:\t\t\tdev_err(idt82p33-\u003edev,\n1250:\t\t\t\t\"Enable_tod failed in %s with err %d!\\n\",\n1251:\t\t\t\t__func__, err);\n1252:\t\t\treturn err;\n1253:\t\t}\n1254:\t\n1255:\t\tdev_info(idt82p33-\u003edev, \"PLL%d registered as ptp%d\\n\",\n1256:\t\t\t index, channel-\u003eptp_clock-\u003eindex);\n1257:\t\n1258:\t\treturn 0;\n1259:\t}\n1260:\t\n1261:\tstatic int idt82p33_reset(struct idt82p33 *idt82p33, bool cold)\n1262:\t{\n1263:\t\tint err;\n1264:\t\tu8 cfg = SOFT_RESET_EN;\n1265:\t\n1266:\t\tif (cold == true)\n1267:\t\t\tgoto cold_reset;\n1268:\t\n1269:\t\terr = idt82p33_read(idt82p33, REG_SOFT_RESET, \u0026cfg, sizeof(cfg));\n1270:\t\tif (err) {\n1271:\t\t\tdev_err(idt82p33-\u003edev,\n1272:\t\t\t\t\"Soft reset failed with err %d!\\n\", err);\n1273:\t\t\treturn err;\n1274:\t\t}\n1275:\t\n1276:\t\tcfg \|= SOFT_RESET_EN;\n1277:\t\n1278:\tcold_reset:\n1279:\t\terr = idt82p33_write(idt82p33, REG_SOFT_RESET, \u0026cfg, sizeof(cfg));\n1280:\t\tif (err)\n1281:\t\t\tdev_err(idt82p33-\u003edev,\n1282:\t\t\t\t\"Cold reset failed with err %d!\\n\", err);\n1283:\t\treturn err;\n1284:\t}\n" }
19/2	2026/09/24 18:14	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 56144 output: 42 thoughts: 2747 Thoughts: Analysis of IDT 82P33 Driver Reachability in Fuzzing Environments Okay, so I'm looking at this `ptp_idt82p33` driver and wondering if it's even remotely fuzzable in a standard QEMU environment. The device instantiation is key: it's named `"82p33x1x-phc"` and is solely registered through `rsmu_sabre_devs` within `rsmu_core_init`, which in turn, is called by `rsmu_i2c_probe` (specifically when probing an I2C device "82p33810" or "82p33811") or `rsmu_spi_probe`. The `idt82p33_driver` then matches this platform device and calls `idt82p33_probe`. During the `idt82p33_probe` routine it initializes regmap and goes through reset, firmware loading, and enabling channels which leads to the registration of `/dev/ptpX` via `ptp_clock_register`. This makes me think it's possible to interact with it through user space, but then I have to ask - is this hardware reachable? Can `rsmu_i2c` or `rsmu_spi` or these specific I2C devices be probed without physical hardware? QEMU doesn't emulate the IDT 82p33810 chip, so that's a no. Could I create an I2C client via sysfs? Maybe. The relevant code in `rsmu_i2c_probe` is `devm_regmap_init_i2c` which in itself doesn't cause any I/O and then `rsmu_core_init` creates the child. This then leads to calling `idt82p33_probe`. However, the `idt82p33_reset` function, which is called during `idt82p33_probe`, uses `regmap_bulk_write` which would try to write to the I2C device. But does QEMU even have an emulated I2C bus? If it writes to a non-existent device (NAK), then the `idt82p33_reset` function will return an error. So, how about syzkaller? Does it instantiate I2C devices? My instinct is no, because that generally depends on specific hardware. I think it's more general and would require hardware drivers to be reachable. Let's carefully consider the patch fuzzing guidelines. Reachability is the primary gate. The code needs to be executable in standard virtualized environments. The instructions explicitly say not to fuzz structurally unreachable hardware, like vendor-specific devices that require physical cards (ASICs). And looking at Section 2 under "Structurally unreachable hardware", it specifically mentions that these drivers can be unreachable. Furthermore, reading "Reachable Drivers and Protocols" makes it seem drivers accessible via virtual buses are the focus. This `ptp_idt82p33` driver is for a physical timing hardware chip from Renesas (IDT 82P33xxx). It requires the actual chip connected over I2C or SPI (via the Renesas RSMU MFD driver). QEMU doesn't emulate this. My conclusion is that it's structurally unreachable. The modified code includes `idt82p33_ptp_clock_unregister_all`, `idt82p33_enable`, `idt82p33_adjtime`, and `idt82p33_extts_check`. But the first one is used in `idt82p33_remove`, which is a driver teardown callback, only executed during hot-unplug or manual sysfs unbinding (which is also unreachable). The other functions that were modified, `idt82p33_enable` and `idt82p33_adjtime` etc., are hooked up in `struct ptp_clock_info caps`. However, given that the driver itself is dependent on the existence of the physical chip, it is not possible to reach it in a standard fuzzing environment. Therefore, the patch does not need to be fuzzed.
20/2	2026/09/24 18:15	tool	grepper	0m Args: { "Expression": "idt82p33_enable\|idt82p33_adjtime", "PathPrefix": "drivers/ptp" } Results: { "Output": "drivers/ptp/ptp_idt82p33.c=403=static int _idt82p33_settime(struct idt82p33_channel channel,\n--\ndrivers/ptp/ptp_idt82p33.c-443-\ndrivers/ptp/ptp_idt82p33.c:444:static int _idt82p33_adjtime_immediate(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-445-\t\t\t\t s64 delta_ns)\n--\ndrivers/ptp/ptp_idt82p33.c-468-\ndrivers/ptp/ptp_idt82p33.c:469:static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel channel,\ndrivers/ptp/ptp_idt82p33.c-470-\t\t\t\t\t\ts64 delta_ns)\n--\ndrivers/ptp/ptp_idt82p33.c-509-\ndrivers/ptp/ptp_idt82p33.c:510:static void idt82p33_adjtime_workaround(struct work_struct work)\ndrivers/ptp/ptp_idt82p33.c-511-{\n--\ndrivers/ptp/ptp_idt82p33.c-518-\t/* Workaround for TOD-to-output alignment issue /\ndrivers/ptp/ptp_idt82p33.c:519:\t_idt82p33_adjtime_internal_triggered(channel, 0);\ndrivers/ptp/ptp_idt82p33.c-520-\tmutex_unlock(idt82p33-\u003elock);\n--\ndrivers/ptp/ptp_idt82p33.c=886=static int idt82p33_perout_enable(struct idt82p33_channel channel,\n--\ndrivers/ptp/ptp_idt82p33.c-893-\ndrivers/ptp/ptp_idt82p33.c:894:static int idt82p33_enable_tod(struct idt82p33_channel channel)\ndrivers/ptp/ptp_idt82p33.c-895-{\n--\ndrivers/ptp/ptp_idt82p33.c=916=static void idt82p33_ptp_clock_unregister_all(struct idt82p33 idt82p33)\n--\ndrivers/ptp/ptp_idt82p33.c-937-\ndrivers/ptp/ptp_idt82p33.c:938:static int idt82p33_enable(struct ptp_clock_info ptp,\ndrivers/ptp/ptp_idt82p33.c-939-\t\t\t struct ptp_clock_request rq, int on)\n--\ndrivers/ptp/ptp_idt82p33.c=1022=static int idt82p33_adjfine(struct ptp_clock_info ptp, long scaled_ppm)\n--\ndrivers/ptp/ptp_idt82p33.c-1047-\ndrivers/ptp/ptp_idt82p33.c:1048:static int idt82p33_adjtime(struct ptp_clock_info ptp, s64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c-1049-{\n--\ndrivers/ptp/ptp_idt82p33.c-1069-\t/* Use more accurate internal 1pps triggered write first /\ndrivers/ptp/ptp_idt82p33.c:1070:\terr = _idt82p33_adjtime_internal_triggered(channel, delta_ns);\ndrivers/ptp/ptp_idt82p33.c-1071-\tif (err \u0026\u0026 delta_ns \u003e IMMEDIATE_SNAP_THRESHOLD_NS)\ndrivers/ptp/ptp_idt82p33.c:1072:\t\terr = _idt82p33_adjtime_immediate(channel, delta_ns);\ndrivers/ptp/ptp_idt82p33.c-1073-\n--\ndrivers/ptp/ptp_idt82p33.c=1118=static int idt82p33_channel_init(struct idt82p33 idt82p33, u32 index)\n--\ndrivers/ptp/ptp_idt82p33.c-1149-\tchannel-\u003eidt82p33 = idt82p33;\ndrivers/ptp/ptp_idt82p33.c:1150:\tINIT_DELAYED_WORK(\u0026channel-\u003eadjtime_work, idt82p33_adjtime_workaround);\ndrivers/ptp/ptp_idt82p33.c-1151-\n--\ndrivers/ptp/ptp_idt82p33.c=1169=static void idt82p33_caps_init(u32 index, struct ptp_clock_info caps,\n--\ndrivers/ptp/ptp_idt82p33.c-1182-\tcaps-\u003eadjfine = idt82p33_adjfine;\ndrivers/ptp/ptp_idt82p33.c:1183:\tcaps-\u003eadjtime = idt82p33_adjtime;\ndrivers/ptp/ptp_idt82p33.c-1184-\tcaps-\u003egettime64 = idt82p33_gettime;\ndrivers/ptp/ptp_idt82p33.c-1185-\tcaps-\u003esettime64 = idt82p33_settime;\ndrivers/ptp/ptp_idt82p33.c:1186:\tcaps-\u003eenable = idt82p33_enable;\ndrivers/ptp/ptp_idt82p33.c-1187-\tcaps-\u003everify = idt82p33_verify_pin;\n--\ndrivers/ptp/ptp_idt82p33.c-1206-\ndrivers/ptp/ptp_idt82p33.c:1207:static int idt82p33_enable_channel(struct idt82p33 idt82p33, u32 index)\ndrivers/ptp/ptp_idt82p33.c-1208-{\n--\ndrivers/ptp/ptp_idt82p33.c-1246-\ndrivers/ptp/ptp_idt82p33.c:1247:\terr = idt82p33_enable_tod(channel);\ndrivers/ptp/ptp_idt82p33.c-1248-\tif (err) {\n--\ndrivers/ptp/ptp_idt82p33.c=1392=static int idt82p33_probe(struct platform_device *pdev)\n--\ndrivers/ptp/ptp_idt82p33.c-1431-\t\t\tif (idt82p33-\u003epll_mask \u0026 (1 \u003c\u003c i))\ndrivers/ptp/ptp_idt82p33.c:1432:\t\t\t\terr = idt82p33_enable_channel(idt82p33, i);\ndrivers/ptp/ptp_idt82p33.c-1433-\t\t\telse\n" }
21/2	2026/09/24 18:15	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 61838 output: 22 thoughts: 1370 Thoughts: Analyzing the `idt82p33` Driver's Reachability for Fuzzing Okay, let's break this down. My initial thought is to examine the `idt82p33` driver, specifically focusing on a patch that introduces a `stopping` flag within `idt82p33_ptp_clock_unregister_all`. This flag seems to be added to prevent races during device unregistration, particularly between `ptp_clock_unregister` and related work queues. The patch's primary function is to synchronize the unregistration of the PTP clock. The key observation here is the movement of `cancel_delayed_work_sync(&idt82p33->extts_work);` into `idt82p33_ptp_clock_unregister_all` in `idt82p33_remove`. It indicates that the system needs to prevent further execution of `idt82p33_enable`, `idt82p33_adjtime`, or `idt82p33_extts_check` after unregistration, which means there may be a race condition that could have existed previously. This confirms the patch's purpose: preventing issues during driver removal. Now, the critical question: Is this driver code reachable in a standard fuzzing environment, according to the "REACHABILITY" guidelines? The question becomes, can we emulate the hardware this driver interfaces with within a standard QEMU setup, or will it require some complex hardware setup? The analysis guidelines give the criteria for being worth fuzzing. I need to make a judgment based on this: * "Structurally unreachable hardware": Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU. * "Unreachable execution paths": Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during physical PCI hot-unplug or manual sysfs driver unbinding. I need to confirm if the driver's target hardware can be created in QEMU. To do that, I'll go through the driver and check where the "82p33x1x-phc" is instantiated, as that is the type this driver is responsible for. I did a `grepper` previously, and that resulted in one entry for "82p33x1x-phc": `drivers/mfd/rsmu_core.c:36`: `static struct mfd_cell rsmu_sabre_devs[] = { [RSMU_PHC] = { .name = "82p33x1x-phc", }, };` Now I need to discover how `rsmu_sabre_devs` is used: Only in `drivers/mfd/rsmu_core.c:62`: ```c int rsmu_core_init(struct rsmu_ddata rsmu) { struct mfd_cell cells; int ret; switch (rsmu->type) { case RSMU_CM: cells = rsmu_cm_devs; break; case RSMU_SABRE: cells = rsmu_sabre_devs; break; case RSMU_SL: cells = rsmu_sl_devs; break; default: dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type); return -ENODEV; } mutex_init(&rsmu->lock); ret = devm_mfd_add_devices(rsmu->dev, PLATFORM_DEVID_AUTO, cells, RSMU_N_DEVS, NULL, 0, NULL); ... ``` I see that `rsmu_core_init` can instantiate the PTP, based on the RSMU type. Now I need to find where `rsmu_core_init` is called. I see it is only called in `drivers/mfd/rsmu_i2c.c` (`rsmu_i2c_probe`) and `drivers/mfd/rsmu_spi.c` (`rsmu_spi_probe`). Now, where are `rsmu_i2c` and `rsmu_spi` instantiated? Let's grep for `rsmu-i2c` and `rsmu-spi` or `82p33810`. I
22/2	2026/09/24 18:15	tool	grepper	0m Args: { "Expression": "82p33810" } Results: { "Output": "Documentation/devicetree/bindings/ptp/ptp-idt82p33.yaml=15=properties:\n--\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml-17- enum:\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml:18: - idt,82p33810\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml-19- - idt,82p33813\n--\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml=36=examples:\n--\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml-41- phc@51 {\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml:42: compatible = \"idt,82p33810\";\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml-43- reg = \u003c0x51\u003e;\n--\ndrivers/mfd/rsmu_i2c.c=330=static const struct i2c_device_id rsmu_i2c_id[] = {\n--\ndrivers/mfd/rsmu_i2c.c-333-\t{ \"8a34002\", RSMU_CM },\ndrivers/mfd/rsmu_i2c.c:334:\t{ \"82p33810\", RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c-335-\t{ \"82p33811\", RSMU_SABRE },\n--\ndrivers/mfd/rsmu_i2c.c=342=static const struct of_device_id rsmu_i2c_of_match[] = {\n--\ndrivers/mfd/rsmu_i2c.c-345-\t{ .compatible = \"idt,8a34002\", .data = (void )RSMU_CM },\ndrivers/mfd/rsmu_i2c.c:346:\t{ .compatible = \"idt,82p33810\", .data = (void )RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c-347-\t{ .compatible = \"idt,82p33811\", .data = (void )RSMU_SABRE },\n--\ndrivers/mfd/rsmu_spi.c=241=static const struct spi_device_id rsmu_spi_id[] = {\n--\ndrivers/mfd/rsmu_spi.c-244-\t{ .name = \"8a34002\", .driver_data = RSMU_CM },\ndrivers/mfd/rsmu_spi.c:245:\t{ .name = \"82p33810\", .driver_data = RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c-246-\t{ .name = \"82p33811\", .driver_data = RSMU_SABRE },\n--\ndrivers/mfd/rsmu_spi.c=251=static const struct of_device_id rsmu_spi_of_match[] = {\n--\ndrivers/mfd/rsmu_spi.c-254-\t{ .compatible = \"idt,8a34002\", .data = (void )RSMU_CM },\ndrivers/mfd/rsmu_spi.c:255:\t{ .compatible = \"idt,82p33810\", .data = (void )RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c-256-\t{ .compatible = \"idt,82p33811\", .data = (void )RSMU_SABRE },\n" }
23/2	2026/09/24 18:15	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 65252 output: 133 thoughts: 1002 Thoughts: Analysis of `ptp_idt82p33` Driver for Fuzzing Okay, let's break this down. The `rsmu-i2c` and `rsmu-spi` drivers are the building blocks, matching OF/Device Tree or I2C/SPI board info. But on amd64, which is the target architecture, there are no DTS files describing the IDT 82P33810! And critically, neither QEMU nor GCE emulate the IDT 82P33810 or 82P33811 hardware. Even if we could somehow trick the system into creating an I2C client device via `sysfs new_device`, `idt82p33_probe` immediately attempts I2C transactions (`idt82p33_reset`) that will fail because the hardware simply isn't there at that I2C address. Probing fails instantly. The patch's modifications within `ptp_idt82p33.c` are all within that driver: teardown, enabling, adjusting time, an ext trigger check, and removal logic, plus a `stopping` flag. These are all specific to the Renesas/IDT 82P33xxx hardware clock chip. No emulation exists. Now, let's compare that against the Negative Criteria. We've got "Structurally unreachable hardware" here, specifically a vendor-specific driver requiring a physical ASIC/I2C/SPI connection. It's not emulated in the standard fuzzing environment, QEMU. It also falls under unreachable execution paths as the teardown callbacks are only executed on physical removal. Wait a second, let me check for virtual PTP clocks... Ah, `ptp_mock.c` is in the `drivers/ptp/Makefile`. But this driver is completely separate from `ptp_idt82p33`! `ptp_idt82p33.c` is for the specific physical IDT hardware. Can Syzkaller even touch `ptp_idt82p33`? No. Syzkaller on amd64, running in QEMU/GCE, cannot probe or instantiate this driver. It requires the IDT 82p33xxx hardware or an MFD device (from I2C/SPI, connected to an IDT 82P33810/82P33811). This is not emulated. Even during probe, there are I2C/SPI transactions. No physical hardware, no `/dev/ptp` device will ever be registered. Therefore, this patch modifies code that is inherently unreachable in standard virtualized environments. WorthFuzzing is false.* Let's verify the instructions. - WorthFuzzing: False. - FocusSymbols: Empty. - EnableConfigs: Empty. - Reasoning: Concise. The code is unreachable because it's a vendor-specific hardware driver for IDT/Renesas 82p33xxx synchronization management units that requires a physical ASIC over I2C/SPI, not emulated in QEMU/GCE. Teardown and other callbacks will not be executed. Okay, let's invoke `set-results`.
24/2	2026/09/24 18:15	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The patch modifies drivers/ptp/ptp_idt82p33.c, which is a device driver for Renesas/IDT 82P33xxx Synchronization Management Units (SMU) / PTP hardware clocks connected via I2C or SPI. This driver requires specific physical ASIC hardware that is not emulated in standard virtualized fuzzing environments (QEMU/GCE). The modified driver callbacks and teardown routines cannot be reached or executed during fuzzing.", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch modifies drivers/ptp/ptp_idt82p33.c, which is a device driver for Renesas/IDT 82P33xxx Synchronization Management Units (SMU) / PTP hardware clocks connected via I2C or SPI. This driver requires specific physical ASIC hardware that is not emulated in standard virtualized fuzzing environments (QEMU/GCE). The modified driver callbacks and teardown routines cannot be reached or executed during fuzzing.", "WorthFuzzing": false }
25/1	2026/09/24 18:15	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies drivers/ptp/ptp_idt82p33.c, which is a device driver for Renesas/IDT 82P33xxx Synchronization Management Units (SMU) / PTP hardware clocks connected via I2C or SPI. This driver requires specific physical ASIC hardware that is not emulated in standard virtualized fuzzing environments (QEMU/GCE). The modified driver callbacks and teardown routines cannot be reached or executed during fuzzing.",
  "WorthFuzzing": false
}

{
  "PatchDiff": "commit 4cde60ecb0b7aeea0e4b6680040c174e5844776c\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Thu Sep 24 18:14:03 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c\nindex f01c50dfa44e8..ffc2ec1fc4bed 100644\n--- a/drivers/ptp/ptp_idt82p33.c\n+++ b/drivers/ptp/ptp_idt82p33.c\n@@ -918,6 +918,13 @@ static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)\n \tstruct idt82p33_channel *channel;\n \tu8 i;\n \n+\tmutex_lock(idt82p33-\u003elock);\n+\tidt82p33-\u003estopping = true;\n+\tidt82p33-\u003eextts_mask = 0;\n+\tmutex_unlock(idt82p33-\u003elock);\n+\n+\tcancel_delayed_work_sync(\u0026idt82p33-\u003eextts_work);\n+\n \tfor (i = 0; i \u003c MAX_PHC_PLL; i++) {\n \t\tchannel = \u0026idt82p33-\u003echannel[i];\n \t\tcancel_delayed_work_sync(\u0026channel-\u003eadjtime_work);\n@@ -937,6 +944,10 @@ static int idt82p33_enable(struct ptp_clock_info *ptp,\n \tint err = -EOPNOTSUPP;\n \n \tmutex_lock(idt82p33-\u003elock);\n+\tif (idt82p33-\u003estopping) {\n+\t\terr = -ENODEV;\n+\t\tgoto out;\n+\t}\n \n \tswitch (rq-\u003etype) {\n \tcase PTP_CLK_REQ_PEROUT:\n@@ -958,6 +969,7 @@ static int idt82p33_enable(struct ptp_clock_info *ptp,\n \t\tbreak;\n \t}\n \n+out:\n \tmutex_unlock(idt82p33-\u003elock);\n \n \tif (err)\n@@ -1044,11 +1056,14 @@ static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)\n \t\treturn -EBUSY;\n \n \tmutex_lock(idt82p33-\u003elock);\n+\tif (idt82p33-\u003estopping) {\n+\t\terr = -ENODEV;\n+\t\tgoto out;\n+\t}\n \n \tif (abs(delta_ns) \u003c phase_snap_threshold) {\n \t\terr = idt82p33_start_ddco(channel, delta_ns);\n-\t\tmutex_unlock(idt82p33-\u003elock);\n-\t\treturn err;\n+\t\tgoto out;\n \t}\n \n \t/* Use more accurate internal 1pps triggered write first */\n@@ -1056,6 +1071,7 @@ static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)\n \tif (err \u0026\u0026 delta_ns \u003e IMMEDIATE_SNAP_THRESHOLD_NS)\n \t\terr = _idt82p33_adjtime_immediate(channel, delta_ns);\n \n+out:\n \tmutex_unlock(idt82p33-\u003elock);\n \n \tif (err)\n@@ -1342,6 +1358,8 @@ static void idt82p33_extts_check(struct work_struct *work)\n \t\treturn;\n \n \tmutex_lock(idt82p33-\u003elock);\n+\tif (idt82p33-\u003estopping)\n+\t\tgoto out;\n \n \tfor (i = 0; i \u003c MAX_PHC_PLL; i++) {\n \t\tmask = 1 \u003c\u003c i;\n@@ -1367,6 +1385,7 @@ static void idt82p33_extts_check(struct work_struct *work)\n \t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\n \t\t\t\t      msecs_to_jiffies(EXTTS_PERIOD_MS));\n \n+out:\n \tmutex_unlock(idt82p33-\u003elock);\n }\n \n@@ -1442,8 +1461,6 @@ static void idt82p33_remove(struct platform_device *pdev)\n {\n \tstruct idt82p33 *idt82p33 = platform_get_drvdata(pdev);\n \n-\tcancel_delayed_work_sync(\u0026idt82p33-\u003eextts_work);\n-\n \tidt82p33_ptp_clock_unregister_all(idt82p33);\n }\n \ndiff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h\nindex 6a63c14b6966b..b88c921adaa91 100644\n--- a/drivers/ptp/ptp_idt82p33.h\n+++ b/drivers/ptp/ptp_idt82p33.h\n@@ -91,6 +91,7 @@ struct idt82p33 {\n \tu8\t\t\textts_mask;\n \tbool\t\t\textts_single_shot;\n \tstruct delayed_work\textts_work;\n+\tbool\t\t\tstopping;\n \t/* Remember the ptp channel to report extts */\n \tstruct idt82p33_channel\t*event_channel[MAX_PHC_PLL];\n \t/* Mutex to protect operations from being interrupted */\n"
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies drivers/ptp/ptp_idt82p33.c, which is a device driver for Renesas/IDT 82P33xxx Synchronization Management Units (SMU) / PTP hardware clocks connected via I2C or SPI. This driver requires specific physical ASIC hardware that is not emulated in standard virtualized fuzzing environments (QEMU/GCE). The modified driver callbacks and teardown routines cannot be reached or executed during fuzzing.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit 4cde60ecb0b7aeea0e4b6680040c174e5844776c
Author: syz-cluster <triage@syzkaller.com>
Date:   Thu Sep 24 18:14:03 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c
index f01c50dfa44e8..ffc2ec1fc4bed 100644
--- a/drivers/ptp/ptp_idt82p33.c
+++ b/drivers/ptp/ptp_idt82p33.c
@@ -918,6 +918,13 @@ static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
 	struct idt82p33_channel *channel;
 	u8 i;
 
+	mutex_lock(idt82p33->lock);
+	idt82p33->stopping = true;
+	idt82p33->extts_mask = 0;
+	mutex_unlock(idt82p33->lock);
+
+	cancel_delayed_work_sync(&idt82p33->extts_work);
+
 	for (i = 0; i < MAX_PHC_PLL; i++) {
 		channel = &idt82p33->channel[i];
 		cancel_delayed_work_sync(&channel->adjtime_work);
@@ -937,6 +944,10 @@ static int idt82p33_enable(struct ptp_clock_info *ptp,
 	int err = -EOPNOTSUPP;
 
 	mutex_lock(idt82p33->lock);
+	if (idt82p33->stopping) {
+		err = -ENODEV;
+		goto out;
+	}
 
 	switch (rq->type) {
 	case PTP_CLK_REQ_PEROUT:
@@ -958,6 +969,7 @@ static int idt82p33_enable(struct ptp_clock_info *ptp,
 		break;
 	}
 
+out:
 	mutex_unlock(idt82p33->lock);
 
 	if (err)
@@ -1044,11 +1056,14 @@ static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
 		return -EBUSY;
 
 	mutex_lock(idt82p33->lock);
+	if (idt82p33->stopping) {
+		err = -ENODEV;
+		goto out;
+	}
 
 	if (abs(delta_ns) < phase_snap_threshold) {
 		err = idt82p33_start_ddco(channel, delta_ns);
-		mutex_unlock(idt82p33->lock);
-		return err;
+		goto out;
 	}
 
 	/* Use more accurate internal 1pps triggered write first */
@@ -1056,6 +1071,7 @@ static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
 	if (err && delta_ns > IMMEDIATE_SNAP_THRESHOLD_NS)
 		err = _idt82p33_adjtime_immediate(channel, delta_ns);
 
+out:
 	mutex_unlock(idt82p33->lock);
 
 	if (err)
@@ -1342,6 +1358,8 @@ static void idt82p33_extts_check(struct work_struct *work)
 		return;
 
 	mutex_lock(idt82p33->lock);
+	if (idt82p33->stopping)
+		goto out;
 
 	for (i = 0; i < MAX_PHC_PLL; i++) {
 		mask = 1 << i;
@@ -1367,6 +1385,7 @@ static void idt82p33_extts_check(struct work_struct *work)
 		schedule_delayed_work(&idt82p33->extts_work,
 				      msecs_to_jiffies(EXTTS_PERIOD_MS));
 
+out:
 	mutex_unlock(idt82p33->lock);
 }
 
@@ -1442,8 +1461,6 @@ static void idt82p33_remove(struct platform_device *pdev)
 {
 	struct idt82p33 *idt82p33 = platform_get_drvdata(pdev);
 
-	cancel_delayed_work_sync(&idt82p33->extts_work);
-
 	idt82p33_ptp_clock_unregister_all(idt82p33);
 }
 
diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h
index 6a63c14b6966b..b88c921adaa91 100644
--- a/drivers/ptp/ptp_idt82p33.h
+++ b/drivers/ptp/ptp_idt82p33.h
@@ -91,6 +91,7 @@ struct idt82p33 {
 	u8			extts_mask;
 	bool			extts_single_shot;
 	struct delayed_work	extts_work;
+	bool			stopping;
 	/* Remember the ptp channel to report extts */
 	struct idt82p33_channel	*event_channel[MAX_PHC_PLL];
 	/* Mutex to protect operations from being interrupted */

							input: 4113
							output: 30
							thoughts: 146

**Analyzing the Patch: Diving into the `ptp_idt82p33` Driver**

Okay, let's break this down. The patch focuses on modifications to `drivers/ptp/ptp_idt82p33.c` and its header file, which immediately signals we're dealing with a Precision Time Protocol (PTP) driver, specifically for the IDT82P33 chip. I need to understand the implications of these changes.

First, I want to confirm my initial assumption. Is this a platform driver? Understanding how it's instantiated is crucial. I need to determine if this driver is relevant to my current development environment, or if it has some conditionality that prevents it being reached during testing. I need to quickly ascertain how it's probed and whether it's even *possible* to trigger it within a QEMU setup or other virtual environment.

To get the essential information, I'll leverage my usual tools. I'll reach for either `grepper` to search the codebase for relevant function calls, probe functions, or device tree bindings related to the IDT82P33, or if necessary, I'll directly read the contents of the `ptp_idt82p33.c` file itself. This should quickly reveal the probing mechanism. I'll also check `drivers/ptp/Kconfig` to see if there are any conditional compilation flags or dependencies that might affect the driver's availability.

{
  "Expression": "idt82p33",
  "PathPrefix": "drivers/ptp"
}

{
  "Output": "\nFull output is too long, showing 500 out of 945 lines.\nUse more precise expression if possible.\n\ndrivers/ptp/Kconfig=152=config PTP_1588_CLOCK_IDT82P33\n--\ndrivers/ptp/Kconfig-161-\t  To compile this driver as a module, choose M here: the module\ndrivers/ptp/Kconfig:162:\t  will be called ptp_idt82p33.\ndrivers/ptp/Kconfig-163-\n--\ndrivers/ptp/Makefile=17=obj-$(CONFIG_PTP_1588_CLOCK_FC3W)\t+= ptp_fc3.o\ndrivers/ptp/Makefile:18:obj-$(CONFIG_PTP_1588_CLOCK_IDT82P33)\t+= ptp_idt82p33.o\ndrivers/ptp/Makefile-19-obj-$(CONFIG_PTP_1588_CLOCK_MOCK)\t+= ptp_mock.o\n--\ndrivers/ptp/ptp_idt82p33.c-18-#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/ptp/ptp_idt82p33.c:19:#include \u003clinux/mfd/idt82p33_reg.h\u003e\ndrivers/ptp/ptp_idt82p33.c-20-\ndrivers/ptp/ptp_idt82p33.c-21-#include \"ptp_private.h\"\ndrivers/ptp/ptp_idt82p33.c:22:#include \"ptp_idt82p33.h\"\ndrivers/ptp/ptp_idt82p33.c-23-\n--\ndrivers/ptp/ptp_idt82p33.c=41=static struct ptp_pin_desc pin_config[MAX_PHC_PLL][MAX_TRIG_CLK];\ndrivers/ptp/ptp_idt82p33.c-42-\ndrivers/ptp/ptp_idt82p33.c:43:static inline int idt82p33_read(struct idt82p33 *idt82p33, u16 regaddr,\ndrivers/ptp/ptp_idt82p33.c-44-\t\t\t\tu8 *buf, u16 count)\ndrivers/ptp/ptp_idt82p33.c-45-{\ndrivers/ptp/ptp_idt82p33.c:46:\treturn regmap_bulk_read(idt82p33-\u003eregmap, regaddr, buf, count);\ndrivers/ptp/ptp_idt82p33.c-47-}\ndrivers/ptp/ptp_idt82p33.c-48-\ndrivers/ptp/ptp_idt82p33.c:49:static inline int idt82p33_write(struct idt82p33 *idt82p33, u16 regaddr,\ndrivers/ptp/ptp_idt82p33.c-50-\t\t\t\t u8 *buf, u16 count)\ndrivers/ptp/ptp_idt82p33.c-51-{\ndrivers/ptp/ptp_idt82p33.c:52:\treturn regmap_bulk_write(idt82p33-\u003eregmap, regaddr, buf, count);\ndrivers/ptp/ptp_idt82p33.c-53-}\ndrivers/ptp/ptp_idt82p33.c-54-\ndrivers/ptp/ptp_idt82p33.c:55:static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,\ndrivers/ptp/ptp_idt82p33.c-56-\t\t\t\t\t    u8 buf[TOD_BYTE_COUNT])\n--\ndrivers/ptp/ptp_idt82p33.c-77-\ndrivers/ptp/ptp_idt82p33.c:78:static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,\ndrivers/ptp/ptp_idt82p33.c-79-\t\t\t\t\t    u8 buf[TOD_BYTE_COUNT])\n--\ndrivers/ptp/ptp_idt82p33.c-98-\ndrivers/ptp/ptp_idt82p33.c:99:static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-100-\t\t\t\t  enum pll_mode mode)\ndrivers/ptp/ptp_idt82p33.c-101-{\ndrivers/ptp/ptp_idt82p33.c:102:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-103-\tu8 dpll_mode;\n--\ndrivers/ptp/ptp_idt82p33.c-108-\ndrivers/ptp/ptp_idt82p33.c:109:\terr = idt82p33_read(idt82p33, channel-\u003edpll_mode_cnfg,\ndrivers/ptp/ptp_idt82p33.c-110-\t\t\t    \u0026dpll_mode, sizeof(dpll_mode));\n--\ndrivers/ptp/ptp_idt82p33.c-117-\ndrivers/ptp/ptp_idt82p33.c:118:\terr = idt82p33_write(idt82p33, channel-\u003edpll_mode_cnfg,\ndrivers/ptp/ptp_idt82p33.c-119-\t\t\t     \u0026dpll_mode, sizeof(dpll_mode));\n--\ndrivers/ptp/ptp_idt82p33.c-127-\ndrivers/ptp/ptp_idt82p33.c:128:static int idt82p33_set_tod_trigger(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-129-\t\t\t\t    u8 trigger, bool write)\ndrivers/ptp/ptp_idt82p33.c-130-{\ndrivers/ptp/ptp_idt82p33.c:131:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-132-\tint err;\n--\ndrivers/ptp/ptp_idt82p33.c-137-\ndrivers/ptp/ptp_idt82p33.c:138:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c-139-\t\t\t    \u0026cfg, sizeof(cfg));\n--\ndrivers/ptp/ptp_idt82p33.c-150-\ndrivers/ptp/ptp_idt82p33.c:151:\treturn idt82p33_write(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c-152-\t\t\t      \u0026trigger, sizeof(trigger));\n--\ndrivers/ptp/ptp_idt82p33.c-154-\ndrivers/ptp/ptp_idt82p33.c:155:static int idt82p33_get_extts(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-156-\t\t\t      struct timespec64 *ts)\ndrivers/ptp/ptp_idt82p33.c-157-{\ndrivers/ptp/ptp_idt82p33.c:158:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-159-\tu8 buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-161-\ndrivers/ptp/ptp_idt82p33.c:162:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c-163-\n--\ndrivers/ptp/ptp_idt82p33.c-172-\ndrivers/ptp/ptp_idt82p33.c:173:\tidt82p33_byte_array_to_timespec(ts, buf);\ndrivers/ptp/ptp_idt82p33.c-174-\n--\ndrivers/ptp/ptp_idt82p33.c=204=static bool is_one_shot(u8 mask)\n--\ndrivers/ptp/ptp_idt82p33.c-212-\ndrivers/ptp/ptp_idt82p33.c:213:static int arm_tod_read_with_trigger(struct idt82p33_channel *channel, u8 trigger)\ndrivers/ptp/ptp_idt82p33.c-214-{\ndrivers/ptp/ptp_idt82p33.c:215:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-216-\tu8 buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-219-\t/* Remember the current tod_sts before setting the trigger */\ndrivers/ptp/ptp_idt82p33.c:220:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c-221-\n--\ndrivers/ptp/ptp_idt82p33.c-226-\ndrivers/ptp/ptp_idt82p33.c:227:\terr = idt82p33_set_tod_trigger(channel, trigger, false);\ndrivers/ptp/ptp_idt82p33.c-228-\ndrivers/ptp/ptp_idt82p33.c-229-\tif (err)\ndrivers/ptp/ptp_idt82p33.c:230:\t\tdev_err(idt82p33-\u003edev, \"%s: err = %d\", __func__, err);\ndrivers/ptp/ptp_idt82p33.c-231-\n--\ndrivers/ptp/ptp_idt82p33.c-234-\ndrivers/ptp/ptp_idt82p33.c:235:static int idt82p33_extts_enable(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-236-\t\t\t\t struct ptp_clock_request *rq, int on)\n--\ndrivers/ptp/ptp_idt82p33.c-238-\tu8 index = rq-\u003eextts.index;\ndrivers/ptp/ptp_idt82p33.c:239:\tstruct idt82p33 *idt82p33;\ndrivers/ptp/ptp_idt82p33.c-240-\tu8 mask = 1 \u003c\u003c index;\n--\ndrivers/ptp/ptp_idt82p33.c-245-\ndrivers/ptp/ptp_idt82p33.c:246:\tidt82p33  = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:247:\told_mask = idt82p33-\u003eextts_mask;\ndrivers/ptp/ptp_idt82p33.c-248-\n--\ndrivers/ptp/ptp_idt82p33.c-253-\t\t/* Return if it was already enabled */\ndrivers/ptp/ptp_idt82p33.c:254:\t\tif (idt82p33-\u003eextts_mask \u0026 mask)\ndrivers/ptp/ptp_idt82p33.c-255-\t\t\treturn 0;\n--\ndrivers/ptp/ptp_idt82p33.c-260-\t\tif (ref \u003c 0) {\ndrivers/ptp/ptp_idt82p33.c:261:\t\t\tdev_err(idt82p33-\u003edev, \"%s: No valid pin found for Pll%d!\\n\",\ndrivers/ptp/ptp_idt82p33.c-262-\t\t\t\t__func__, channel-\u003eplln);\n--\ndrivers/ptp/ptp_idt82p33.c-268-\t\tif (err) {\ndrivers/ptp/ptp_idt82p33.c:269:\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-270-\t\t\t\t\"%s: Unsupported ref %d!\\n\", __func__, ref);\n--\ndrivers/ptp/ptp_idt82p33.c-273-\ndrivers/ptp/ptp_idt82p33.c:274:\t\terr = arm_tod_read_with_trigger(\u0026idt82p33-\u003echannel[index], trigger);\ndrivers/ptp/ptp_idt82p33.c-275-\ndrivers/ptp/ptp_idt82p33.c-276-\t\tif (err == 0) {\ndrivers/ptp/ptp_idt82p33.c:277:\t\t\tidt82p33-\u003eextts_mask |= mask;\ndrivers/ptp/ptp_idt82p33.c:278:\t\t\tidt82p33-\u003echannel[index].tod_trigger = trigger;\ndrivers/ptp/ptp_idt82p33.c:279:\t\t\tidt82p33-\u003eevent_channel[index] = channel;\ndrivers/ptp/ptp_idt82p33.c:280:\t\t\tidt82p33-\u003eextts_single_shot = is_one_shot(idt82p33-\u003eextts_mask);\ndrivers/ptp/ptp_idt82p33.c-281-\n--\ndrivers/ptp/ptp_idt82p33.c-284-\ndrivers/ptp/ptp_idt82p33.c:285:\t\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\ndrivers/ptp/ptp_idt82p33.c-286-\t\t\t\t\t      msecs_to_jiffies(EXTTS_PERIOD_MS));\n--\ndrivers/ptp/ptp_idt82p33.c-288-\t} else {\ndrivers/ptp/ptp_idt82p33.c:289:\t\tidt82p33-\u003eextts_mask \u0026= ~mask;\ndrivers/ptp/ptp_idt82p33.c:290:\t\tidt82p33-\u003eextts_single_shot = is_one_shot(idt82p33-\u003eextts_mask);\ndrivers/ptp/ptp_idt82p33.c-291-\ndrivers/ptp/ptp_idt82p33.c:292:\t\tif (idt82p33-\u003eextts_mask == 0)\ndrivers/ptp/ptp_idt82p33.c:293:\t\t\tcancel_delayed_work(\u0026idt82p33-\u003eextts_work);\ndrivers/ptp/ptp_idt82p33.c-294-\t}\n--\ndrivers/ptp/ptp_idt82p33.c-298-\ndrivers/ptp/ptp_idt82p33.c:299:static int idt82p33_extts_check_channel(struct idt82p33 *idt82p33, u8 todn)\ndrivers/ptp/ptp_idt82p33.c-300-{\ndrivers/ptp/ptp_idt82p33.c:301:\tstruct idt82p33_channel *event_channel;\ndrivers/ptp/ptp_idt82p33.c-302-\tstruct ptp_clock_event event;\n--\ndrivers/ptp/ptp_idt82p33.c-305-\ndrivers/ptp/ptp_idt82p33.c:306:\terr = idt82p33_get_extts(\u0026idt82p33-\u003echannel[todn], \u0026ts);\ndrivers/ptp/ptp_idt82p33.c-307-\tif (err == 0) {\ndrivers/ptp/ptp_idt82p33.c:308:\t\tevent_channel = idt82p33-\u003eevent_channel[todn];\ndrivers/ptp/ptp_idt82p33.c-309-\t\tevent.type = PTP_CLOCK_EXTTS;\n--\ndrivers/ptp/ptp_idt82p33.c-317-\ndrivers/ptp/ptp_idt82p33.c:318:static u8 idt82p33_extts_enable_mask(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-319-\t\t\t\t     u8 extts_mask, bool enable)\ndrivers/ptp/ptp_idt82p33.c-320-{\ndrivers/ptp/ptp_idt82p33.c:321:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-322-\tu8 trigger = channel-\u003etod_trigger;\n--\ndrivers/ptp/ptp_idt82p33.c-330-\tif (enable == false)\ndrivers/ptp/ptp_idt82p33.c:331:\t\tcancel_delayed_work_sync(\u0026idt82p33-\u003eextts_work);\ndrivers/ptp/ptp_idt82p33.c-332-\n--\ndrivers/ptp/ptp_idt82p33.c-339-\t\tif (enable) {\ndrivers/ptp/ptp_idt82p33.c:340:\t\t\terr = arm_tod_read_with_trigger(\u0026idt82p33-\u003echannel[i], trigger);\ndrivers/ptp/ptp_idt82p33.c-341-\t\t\tif (err)\ndrivers/ptp/ptp_idt82p33.c:342:\t\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-343-\t\t\t\t\t\"%s: Arm ToD read trigger failed, err = %d\",\n--\ndrivers/ptp/ptp_idt82p33.c-345-\t\t} else {\ndrivers/ptp/ptp_idt82p33.c:346:\t\t\terr = idt82p33_extts_check_channel(idt82p33, i);\ndrivers/ptp/ptp_idt82p33.c:347:\t\t\tif (err == 0 \u0026\u0026 idt82p33-\u003eextts_single_shot)\ndrivers/ptp/ptp_idt82p33.c-348-\t\t\t\t/* trigger happened so we won't re-enable it */\n--\ndrivers/ptp/ptp_idt82p33.c-353-\tif (enable)\ndrivers/ptp/ptp_idt82p33.c:354:\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\ndrivers/ptp/ptp_idt82p33.c-355-\t\t\t\t      msecs_to_jiffies(EXTTS_PERIOD_MS));\n--\ndrivers/ptp/ptp_idt82p33.c-359-\ndrivers/ptp/ptp_idt82p33.c:360:static int _idt82p33_gettime(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-361-\t\t\t     struct timespec64 *ts)\ndrivers/ptp/ptp_idt82p33.c-362-{\ndrivers/ptp/ptp_idt82p33.c:363:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:364:\tu8 old_mask = idt82p33-\u003eextts_mask;\ndrivers/ptp/ptp_idt82p33.c-365-\tu8 buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-370-\tif (old_mask)\ndrivers/ptp/ptp_idt82p33.c:371:\t\tnew_mask = idt82p33_extts_enable_mask(channel, old_mask, false);\ndrivers/ptp/ptp_idt82p33.c-372-\ndrivers/ptp/ptp_idt82p33.c:373:\terr = idt82p33_set_tod_trigger(channel, HW_TOD_RD_TRIG_SEL_LSB_TOD_STS,\ndrivers/ptp/ptp_idt82p33.c-374-\t\t\t\t       false);\n--\ndrivers/ptp/ptp_idt82p33.c-379-\ndrivers/ptp/ptp_idt82p33.c:380:\tif (idt82p33-\u003ecalculate_overhead_flag)\ndrivers/ptp/ptp_idt82p33.c:381:\t\tidt82p33-\u003estart_time = ktime_get_raw();\ndrivers/ptp/ptp_idt82p33.c-382-\ndrivers/ptp/ptp_idt82p33.c:383:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c-384-\n--\ndrivers/ptp/ptp_idt82p33.c-389-\tif (new_mask)\ndrivers/ptp/ptp_idt82p33.c:390:\t\tidt82p33_extts_enable_mask(channel, new_mask, true);\ndrivers/ptp/ptp_idt82p33.c-391-\ndrivers/ptp/ptp_idt82p33.c:392:\tidt82p33_byte_array_to_timespec(ts, buf);\ndrivers/ptp/ptp_idt82p33.c-393-\n--\ndrivers/ptp/ptp_idt82p33.c-402-\ndrivers/ptp/ptp_idt82p33.c:403:static int _idt82p33_settime(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-404-\t\t\t     struct timespec64 const *ts)\ndrivers/ptp/ptp_idt82p33.c-405-{\ndrivers/ptp/ptp_idt82p33.c:406:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-407-\tstruct timespec64 local_ts = *ts;\n--\ndrivers/ptp/ptp_idt82p33.c-412-\ndrivers/ptp/ptp_idt82p33.c:413:\terr = idt82p33_set_tod_trigger(channel, HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,\ndrivers/ptp/ptp_idt82p33.c-414-\t\t\t\t       true);\n--\ndrivers/ptp/ptp_idt82p33.c-419-\ndrivers/ptp/ptp_idt82p33.c:420:\tif (idt82p33-\u003ecalculate_overhead_flag) {\ndrivers/ptp/ptp_idt82p33.c-421-\t\tdynamic_overhead_ns = ktime_to_ns(ktime_get_raw())\ndrivers/ptp/ptp_idt82p33.c:422:\t\t\t\t\t- ktime_to_ns(idt82p33-\u003estart_time);\ndrivers/ptp/ptp_idt82p33.c-423-\n--\ndrivers/ptp/ptp_idt82p33.c-425-\ndrivers/ptp/ptp_idt82p33.c:426:\t\tidt82p33-\u003ecalculate_overhead_flag = 0;\ndrivers/ptp/ptp_idt82p33.c-427-\t}\ndrivers/ptp/ptp_idt82p33.c-428-\ndrivers/ptp/ptp_idt82p33.c:429:\tidt82p33_timespec_to_byte_array(\u0026local_ts, buf);\ndrivers/ptp/ptp_idt82p33.c-430-\n--\ndrivers/ptp/ptp_idt82p33.c-434-\tfor (i = 0; i \u003c TOD_BYTE_COUNT; i++) {\ndrivers/ptp/ptp_idt82p33.c:435:\t\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_cnfg + i,\ndrivers/ptp/ptp_idt82p33.c-436-\t\t\t\t     \u0026buf[i], sizeof(buf[i]));\n--\ndrivers/ptp/ptp_idt82p33.c-443-\ndrivers/ptp/ptp_idt82p33.c:444:static int _idt82p33_adjtime_immediate(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-445-\t\t\t\t       s64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c-446-{\ndrivers/ptp/ptp_idt82p33.c:447:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-448-\tstruct timespec64 ts;\n--\ndrivers/ptp/ptp_idt82p33.c-451-\ndrivers/ptp/ptp_idt82p33.c:452:\tidt82p33-\u003ecalculate_overhead_flag = 1;\ndrivers/ptp/ptp_idt82p33.c-453-\ndrivers/ptp/ptp_idt82p33.c:454:\terr = _idt82p33_gettime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c-455-\n--\ndrivers/ptp/ptp_idt82p33.c-459-\tnow_ns = timespec64_to_ns(\u0026ts);\ndrivers/ptp/ptp_idt82p33.c:460:\tnow_ns += delta_ns + idt82p33-\u003etod_write_overhead_ns;\ndrivers/ptp/ptp_idt82p33.c-461-\n--\ndrivers/ptp/ptp_idt82p33.c-463-\ndrivers/ptp/ptp_idt82p33.c:464:\terr = _idt82p33_settime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c-465-\n--\ndrivers/ptp/ptp_idt82p33.c-468-\ndrivers/ptp/ptp_idt82p33.c:469:static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-470-\t\t\t\t\t\ts64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c-471-{\ndrivers/ptp/ptp_idt82p33.c:472:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-473-\tchar buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-479-\ndrivers/ptp/ptp_idt82p33.c:480:\terr = _idt82p33_gettime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c-481-\n--\ndrivers/ptp/ptp_idt82p33.c-492-\tts = ns_to_timespec64(ns);\ndrivers/ptp/ptp_idt82p33.c:493:\tidt82p33_timespec_to_byte_array(\u0026ts, buf);\ndrivers/ptp/ptp_idt82p33.c-494-\n--\ndrivers/ptp/ptp_idt82p33.c-497-\t */\ndrivers/ptp/ptp_idt82p33.c:498:\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_cnfg, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c-499-\tif (err)\n--\ndrivers/ptp/ptp_idt82p33.c-506-\ndrivers/ptp/ptp_idt82p33.c:507:\treturn idt82p33_set_tod_trigger(channel, HW_TOD_TRIG_SEL_TOD_PPS, true);\ndrivers/ptp/ptp_idt82p33.c-508-}\ndrivers/ptp/ptp_idt82p33.c-509-\ndrivers/ptp/ptp_idt82p33.c:510:static void idt82p33_adjtime_workaround(struct work_struct *work)\ndrivers/ptp/ptp_idt82p33.c-511-{\ndrivers/ptp/ptp_idt82p33.c:512:\tstruct idt82p33_channel *channel = container_of(work,\ndrivers/ptp/ptp_idt82p33.c:513:\t\t\t\t\t\t\tstruct idt82p33_channel,\ndrivers/ptp/ptp_idt82p33.c-514-\t\t\t\t\t\t\tadjtime_work.work);\ndrivers/ptp/ptp_idt82p33.c:515:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-516-\ndrivers/ptp/ptp_idt82p33.c:517:\tmutex_lock(idt82p33-\u003elock);\ndrivers/ptp/ptp_idt82p33.c-518-\t/* Workaround for TOD-to-output alignment issue */\ndrivers/ptp/ptp_idt82p33.c:519:\t_idt82p33_adjtime_internal_triggered(channel, 0);\ndrivers/ptp/ptp_idt82p33.c:520:\tmutex_unlock(idt82p33-\u003elock);\ndrivers/ptp/ptp_idt82p33.c-521-}\ndrivers/ptp/ptp_idt82p33.c-522-\ndrivers/ptp/ptp_idt82p33.c:523:static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)\ndrivers/ptp/ptp_idt82p33.c-524-{\ndrivers/ptp/ptp_idt82p33.c:525:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-526-\tunsigned char buf[5] = {0};\n--\ndrivers/ptp/ptp_idt82p33.c-551-\ndrivers/ptp/ptp_idt82p33.c:552:\terr = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);\ndrivers/ptp/ptp_idt82p33.c-553-\n--\ndrivers/ptp/ptp_idt82p33.c-556-\ndrivers/ptp/ptp_idt82p33.c:557:\terr = idt82p33_write(idt82p33, channel-\u003edpll_freq_cnfg,\ndrivers/ptp/ptp_idt82p33.c-558-\t\t\t     buf, sizeof(buf));\n--\ndrivers/ptp/ptp_idt82p33.c-563-/* ppb = scaled_ppm * 125 / 2^13 */\ndrivers/ptp/ptp_idt82p33.c:564:static s32 idt82p33_ddco_scaled_ppm(long current_ppm, s32 ddco_ppb)\ndrivers/ptp/ptp_idt82p33.c-565-{\n--\ndrivers/ptp/ptp_idt82p33.c-578-\ndrivers/ptp/ptp_idt82p33.c:579:static int idt82p33_stop_ddco(struct idt82p33_channel *channel)\ndrivers/ptp/ptp_idt82p33.c-580-{\n--\ndrivers/ptp/ptp_idt82p33.c-582-\ndrivers/ptp/ptp_idt82p33.c:583:\terr = _idt82p33_adjfine(channel, channel-\u003ecurrent_freq);\ndrivers/ptp/ptp_idt82p33.c-584-\tif (err)\n--\ndrivers/ptp/ptp_idt82p33.c-591-\ndrivers/ptp/ptp_idt82p33.c:592:static int idt82p33_start_ddco(struct idt82p33_channel *channel, s32 delta_ns)\ndrivers/ptp/ptp_idt82p33.c-593-{\n--\ndrivers/ptp/ptp_idt82p33.c-612-\ndrivers/ptp/ptp_idt82p33.c:613:\terr = _idt82p33_adjfine(channel,\ndrivers/ptp/ptp_idt82p33.c:614:\t\t\t\tidt82p33_ddco_scaled_ppm(current_ppm, ppb));\ndrivers/ptp/ptp_idt82p33.c-615-\tif (err)\n--\ndrivers/ptp/ptp_idt82p33.c-625-\ndrivers/ptp/ptp_idt82p33.c:626:static int idt82p33_measure_one_byte_write_overhead(\ndrivers/ptp/ptp_idt82p33.c:627:\t\tstruct idt82p33_channel *channel, s64 *overhead_ns)\ndrivers/ptp/ptp_idt82p33.c-628-{\ndrivers/ptp/ptp_idt82p33.c:629:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-630-\tktime_t start, stop;\n--\ndrivers/ptp/ptp_idt82p33.c-642-\ndrivers/ptp/ptp_idt82p33.c:643:\t\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c-644-\t\t\t\t     \u0026trigger, sizeof(trigger));\n--\ndrivers/ptp/ptp_idt82p33.c-658-\ndrivers/ptp/ptp_idt82p33.c:659:static int idt82p33_measure_one_byte_read_overhead(\ndrivers/ptp/ptp_idt82p33.c:660:\t\tstruct idt82p33_channel *channel, s64 *overhead_ns)\ndrivers/ptp/ptp_idt82p33.c-661-{\ndrivers/ptp/ptp_idt82p33.c:662:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-663-\tktime_t start, stop;\n--\ndrivers/ptp/ptp_idt82p33.c-675-\ndrivers/ptp/ptp_idt82p33.c:676:\t\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c-677-\t\t\t\t    \u0026trigger, sizeof(trigger));\n--\ndrivers/ptp/ptp_idt82p33.c-691-\ndrivers/ptp/ptp_idt82p33.c:692:static int idt82p33_measure_tod_write_9_byte_overhead(\ndrivers/ptp/ptp_idt82p33.c:693:\t\tstruct idt82p33_channel *channel)\ndrivers/ptp/ptp_idt82p33.c-694-{\ndrivers/ptp/ptp_idt82p33.c:695:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-696-\tu8 buf[TOD_BYTE_COUNT];\n--\ndrivers/ptp/ptp_idt82p33.c-702-\ttotal_ns = 0;\ndrivers/ptp/ptp_idt82p33.c:703:\tidt82p33-\u003etod_write_overhead_ns = 0;\ndrivers/ptp/ptp_idt82p33.c-704-\n--\ndrivers/ptp/ptp_idt82p33.c-710-\t\tfor (j = 0; j \u003c (TOD_BYTE_COUNT - 1); j++) {\ndrivers/ptp/ptp_idt82p33.c:711:\t\t\terr = idt82p33_write(idt82p33,\ndrivers/ptp/ptp_idt82p33.c-712-\t\t\t\t\t     channel-\u003edpll_tod_cnfg + i,\n--\ndrivers/ptp/ptp_idt82p33.c-722-\ndrivers/ptp/ptp_idt82p33.c:723:\tidt82p33-\u003etod_write_overhead_ns = div_s64(total_ns,\ndrivers/ptp/ptp_idt82p33.c-724-\t\t\t\t\t\t  MAX_MEASURMENT_COUNT);\n--\ndrivers/ptp/ptp_idt82p33.c-728-\ndrivers/ptp/ptp_idt82p33.c:729:static int idt82p33_measure_settime_gettime_gap_overhead(\ndrivers/ptp/ptp_idt82p33.c:730:\t\tstruct idt82p33_channel *channel, s64 *overhead_ns)\ndrivers/ptp/ptp_idt82p33.c-731-{\n--\ndrivers/ptp/ptp_idt82p33.c-737-\ndrivers/ptp/ptp_idt82p33.c:738:\terr = _idt82p33_settime(channel, \u0026ts1);\ndrivers/ptp/ptp_idt82p33.c-739-\n--\ndrivers/ptp/ptp_idt82p33.c-742-\ndrivers/ptp/ptp_idt82p33.c:743:\terr = _idt82p33_gettime(channel, \u0026ts2);\ndrivers/ptp/ptp_idt82p33.c-744-\n--\ndrivers/ptp/ptp_idt82p33.c-750-\ndrivers/ptp/ptp_idt82p33.c:751:static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)\ndrivers/ptp/ptp_idt82p33.c-752-{\ndrivers/ptp/ptp_idt82p33.c-753-\ts64 trailing_overhead_ns, one_byte_write_ns, gap_ns, one_byte_read_ns;\ndrivers/ptp/ptp_idt82p33.c:754:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-755-\tint err;\ndrivers/ptp/ptp_idt82p33.c-756-\ndrivers/ptp/ptp_idt82p33.c:757:\tidt82p33-\u003etod_write_overhead_ns = 0;\ndrivers/ptp/ptp_idt82p33.c-758-\ndrivers/ptp/ptp_idt82p33.c:759:\terr = idt82p33_measure_settime_gettime_gap_overhead(channel, \u0026gap_ns);\ndrivers/ptp/ptp_idt82p33.c-760-\ndrivers/ptp/ptp_idt82p33.c-761-\tif (err) {\ndrivers/ptp/ptp_idt82p33.c:762:\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-763-\t\t\t\"Failed in %s with err %d!\\n\", __func__, err);\n--\ndrivers/ptp/ptp_idt82p33.c-766-\ndrivers/ptp/ptp_idt82p33.c:767:\terr = idt82p33_measure_one_byte_write_overhead(channel,\ndrivers/ptp/ptp_idt82p33.c-768-\t\t\t\t\t\t       \u0026one_byte_write_ns);\n--\ndrivers/ptp/ptp_idt82p33.c-772-\ndrivers/ptp/ptp_idt82p33.c:773:\terr = idt82p33_measure_one_byte_read_overhead(channel,\ndrivers/ptp/ptp_idt82p33.c-774-\t\t\t\t\t\t      \u0026one_byte_read_ns);\n--\ndrivers/ptp/ptp_idt82p33.c-778-\ndrivers/ptp/ptp_idt82p33.c:779:\terr = idt82p33_measure_tod_write_9_byte_overhead(channel);\ndrivers/ptp/ptp_idt82p33.c-780-\n--\ndrivers/ptp/ptp_idt82p33.c-786-\ndrivers/ptp/ptp_idt82p33.c:787:\tidt82p33-\u003etod_write_overhead_ns -= trailing_overhead_ns;\ndrivers/ptp/ptp_idt82p33.c-788-\n--\ndrivers/ptp/ptp_idt82p33.c-791-\ndrivers/ptp/ptp_idt82p33.c:792:static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,\ndrivers/ptp/ptp_idt82p33.c-793-\t\t\t\t\tu8 page,\n--\ndrivers/ptp/ptp_idt82p33.c-800-\t\tif ((val \u0026 0xfc) || !(val \u0026 0x3)) {\ndrivers/ptp/ptp_idt82p33.c:801:\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-802-\t\t\t\t\"Invalid PLL mask 0x%x\\n\", val);\n--\ndrivers/ptp/ptp_idt82p33.c-804-\t\t} else {\ndrivers/ptp/ptp_idt82p33.c:805:\t\t\tidt82p33-\u003epll_mask = val;\ndrivers/ptp/ptp_idt82p33.c-806-\t\t}\n--\ndrivers/ptp/ptp_idt82p33.c-808-\t\toffset == PLL0_OUTMASK_ADDR_LO) {\ndrivers/ptp/ptp_idt82p33.c:809:\t\tidt82p33-\u003echannel[0].output_mask = val;\ndrivers/ptp/ptp_idt82p33.c-810-\t} else if (page == PLL1_OUTMASK_ADDR_HI \u0026\u0026\ndrivers/ptp/ptp_idt82p33.c-811-\t\toffset == PLL1_OUTMASK_ADDR_LO) {\ndrivers/ptp/ptp_idt82p33.c:812:\t\tidt82p33-\u003echannel[1].output_mask = val;\ndrivers/ptp/ptp_idt82p33.c-813-\t}\n--\ndrivers/ptp/ptp_idt82p33.c-817-\ndrivers/ptp/ptp_idt82p33.c:818:static void idt82p33_display_masks(struct idt82p33 *idt82p33)\ndrivers/ptp/ptp_idt82p33.c-819-{\n--\ndrivers/ptp/ptp_idt82p33.c-821-\ndrivers/ptp/ptp_idt82p33.c:822:\tdev_info(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c:823:\t\t \"pllmask = 0x%02x\\n\", idt82p33-\u003epll_mask);\ndrivers/ptp/ptp_idt82p33.c-824-\n--\ndrivers/ptp/ptp_idt82p33.c-827-\ndrivers/ptp/ptp_idt82p33.c:828:\t\tif (mask \u0026 idt82p33-\u003epll_mask)\ndrivers/ptp/ptp_idt82p33.c:829:\t\t\tdev_info(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c-830-\t\t\t\t \"PLL%d output_mask = 0x%04x\\n\",\ndrivers/ptp/ptp_idt82p33.c:831:\t\t\t\t i, idt82p33-\u003echannel[i].output_mask);\ndrivers/ptp/ptp_idt82p33.c-832-\t}\n--\ndrivers/ptp/ptp_idt82p33.c-834-\ndrivers/ptp/ptp_idt82p33.c:835:static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)\ndrivers/ptp/ptp_idt82p33.c-836-{\ndrivers/ptp/ptp_idt82p33.c:837:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-838-\tu8 sync_cnfg;\n--\ndrivers/ptp/ptp_idt82p33.c-840-\ndrivers/ptp/ptp_idt82p33.c:841:\terr = idt82p33_read(idt82p33, channel-\u003edpll_sync_cnfg,\ndrivers/ptp/ptp_idt82p33.c-842-\t\t\t    \u0026sync_cnfg, sizeof(sync_cnfg));\n--\ndrivers/ptp/ptp_idt82p33.c-849-\ndrivers/ptp/ptp_idt82p33.c:850:\treturn idt82p33_write(idt82p33, channel-\u003edpll_sync_cnfg,\ndrivers/ptp/ptp_idt82p33.c-851-\t\t\t      \u0026sync_cnfg, sizeof(sync_cnfg));\n--\ndrivers/ptp/ptp_idt82p33.c-853-\ndrivers/ptp/ptp_idt82p33.c:854:static long idt82p33_work_handler(struct ptp_clock_info *ptp)\ndrivers/ptp/ptp_idt82p33.c-855-{\ndrivers/ptp/ptp_idt82p33.c:856:\tstruct idt82p33_channel *channel =\ndrivers/ptp/ptp_idt82p33.c:857:\t\t\tcontainer_of(ptp, struct idt82p33_channel, caps);\ndrivers/ptp/ptp_idt82p33.c:858:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-859-\ndrivers/ptp/ptp_idt82p33.c:860:\tmutex_lock(idt82p33-\u003elock);\ndrivers/ptp/ptp_idt82p33.c:861:\t(void)idt82p33_stop_ddco(channel);\ndrivers/ptp/ptp_idt82p33.c:862:\tmutex_unlock(idt82p33-\u003elock);\ndrivers/ptp/ptp_idt82p33.c-863-\n--\ndrivers/ptp/ptp_idt82p33.c-867-\ndrivers/ptp/ptp_idt82p33.c:868:static int idt82p33_output_enable(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-869-\t\t\t\t  bool enable, unsigned int outn)\ndrivers/ptp/ptp_idt82p33.c-870-{\ndrivers/ptp/ptp_idt82p33.c:871:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c-872-\tint err;\n--\ndrivers/ptp/ptp_idt82p33.c-874-\ndrivers/ptp/ptp_idt82p33.c:875:\terr = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), \u0026val, sizeof(val));\ndrivers/ptp/ptp_idt82p33.c-876-\tif (err)\n--\ndrivers/ptp/ptp_idt82p33.c-882-\ndrivers/ptp/ptp_idt82p33.c:883:\treturn idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), \u0026val, sizeof(val));\ndrivers/ptp/ptp_idt82p33.c-884-}\ndrivers/ptp/ptp_idt82p33.c-885-\ndrivers/ptp/ptp_idt82p33.c:886:static int idt82p33_perout_enable(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-887-\t\t\t\t  bool enable,\n--\ndrivers/ptp/ptp_idt82p33.c-890-\t/* Enable/disable individual output instead */\ndrivers/ptp/ptp_idt82p33.c:891:\treturn idt82p33_output_enable(channel, enable, perout-\u003eindex);\ndrivers/ptp/ptp_idt82p33.c-892-}\n\n"
}

							input: 18765
							output: 45
							thoughts: 48

Okay, let's dive into this. Here's how I'd approach understanding the registration and probing of `ptp_idt82p33`.

**Investigating the Registration and Probe of `ptp_idt82p33`**

Alright, I need to get a clear picture of how this `ptp_idt82p33` device is being handled within the kernel. My first step is to trace its registration and probing sequence. I'll need to understand the entry points. Let's start by looking at the relevant code in `ptp_idt82p33.c`. I'll focus my initial scan around line 1400. That should give me a good jumping-off point to see how the driver interacts with the device during its initialization phase. From there, I'll be looking for the crucial functions that handle device detection and resource allocation.

{
  "File": "drivers/ptp/ptp_idt82p33.c",
  "FirstLine": 1380,
  "LineCount": 90
}

{
  "Contents": "1380:\t\t\t\t}\n1381:\t\t\t}\n1382:\t\t}\n1383:\t\n1384:\t\tif (idt82p33-\u003eextts_mask)\n1385:\t\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\n1386:\t\t\t\t\t      msecs_to_jiffies(EXTTS_PERIOD_MS));\n1387:\t\n1388:\tout:\n1389:\t\tmutex_unlock(idt82p33-\u003elock);\n1390:\t}\n1391:\t\n1392:\tstatic int idt82p33_probe(struct platform_device *pdev)\n1393:\t{\n1394:\t\tstruct rsmu_ddata *ddata = dev_get_drvdata(pdev-\u003edev.parent);\n1395:\t\tstruct idt82p33 *idt82p33;\n1396:\t\tint err;\n1397:\t\tu8 i;\n1398:\t\n1399:\t\tidt82p33 = devm_kzalloc(\u0026pdev-\u003edev,\n1400:\t\t\t\t\tsizeof(struct idt82p33), GFP_KERNEL);\n1401:\t\tif (!idt82p33)\n1402:\t\t\treturn -ENOMEM;\n1403:\t\n1404:\t\tidt82p33-\u003edev = \u0026pdev-\u003edev;\n1405:\t\tidt82p33-\u003emfd = pdev-\u003edev.parent;\n1406:\t\tidt82p33-\u003elock = \u0026ddata-\u003elock;\n1407:\t\tidt82p33-\u003eregmap = ddata-\u003eregmap;\n1408:\t\tidt82p33-\u003etod_write_overhead_ns = 0;\n1409:\t\tidt82p33-\u003ecalculate_overhead_flag = 0;\n1410:\t\tidt82p33-\u003epll_mask = DEFAULT_PLL_MASK;\n1411:\t\tidt82p33-\u003echannel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;\n1412:\t\tidt82p33-\u003echannel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;\n1413:\t\tidt82p33-\u003eextts_mask = 0;\n1414:\t\tINIT_DELAYED_WORK(\u0026idt82p33-\u003eextts_work, idt82p33_extts_check);\n1415:\t\n1416:\t\tmutex_lock(idt82p33-\u003elock);\n1417:\t\n1418:\t\t/* cold reset before loading firmware */\n1419:\t\tidt82p33_reset(idt82p33, true);\n1420:\t\n1421:\t\terr = idt82p33_load_firmware(idt82p33);\n1422:\t\tif (err)\n1423:\t\t\tdev_warn(idt82p33-\u003edev,\n1424:\t\t\t\t \"loading firmware failed with %d\\n\", err);\n1425:\t\n1426:\t\t/* soft reset after loading firmware */\n1427:\t\tidt82p33_reset(idt82p33, false);\n1428:\t\n1429:\t\tif (idt82p33-\u003epll_mask) {\n1430:\t\t\tfor (i = 0; i \u003c MAX_PHC_PLL; i++) {\n1431:\t\t\t\tif (idt82p33-\u003epll_mask \u0026 (1 \u003c\u003c i))\n1432:\t\t\t\t\terr = idt82p33_enable_channel(idt82p33, i);\n1433:\t\t\t\telse\n1434:\t\t\t\t\terr = idt82p33_channel_init(idt82p33, i);\n1435:\t\t\t\tif (err) {\n1436:\t\t\t\t\tdev_err(idt82p33-\u003edev,\n1437:\t\t\t\t\t\t\"Failed in %s with err %d!\\n\",\n1438:\t\t\t\t\t\t__func__, err);\n1439:\t\t\t\t\tbreak;\n1440:\t\t\t\t}\n1441:\t\t\t}\n1442:\t\t} else {\n1443:\t\t\tdev_err(idt82p33-\u003edev,\n1444:\t\t\t\t\"no PLLs flagged as PHCs, nothing to do\\n\");\n1445:\t\t\terr = -ENODEV;\n1446:\t\t}\n1447:\t\n1448:\t\tmutex_unlock(idt82p33-\u003elock);\n1449:\t\n1450:\t\tif (err) {\n1451:\t\t\tidt82p33_ptp_clock_unregister_all(idt82p33);\n1452:\t\t\treturn err;\n1453:\t\t}\n1454:\t\n1455:\t\tplatform_set_drvdata(pdev, idt82p33);\n1456:\t\n1457:\t\treturn 0;\n1458:\t}\n1459:\t\n1460:\tstatic void idt82p33_remove(struct platform_device *pdev)\n1461:\t{\n1462:\t\tstruct idt82p33 *idt82p33 = platform_get_drvdata(pdev);\n1463:\t\n1464:\t\tidt82p33_ptp_clock_unregister_all(idt82p33);\n1465:\t}\n1466:\t\n1467:\tstatic struct platform_driver idt82p33_driver = {\n1468:\t\t.driver = {\n1469:\t\t\t.name = \"82p33x1x-phc\",\n"
}

							input: 20555
							output: 25
							thoughts: 46

Okay, let's dive into this. Here's my thought process on this "82p33x1x-phc" platform device:

**Dissecting the "82p33x1x-phc" Device**

Right, so the first thing I want to do is figure out what the kernel's definition of this platform device is. It's named "82p33x1x-phc", and based on the name, it *could* be vendor specific. But before I start making assumptions, let's get the facts. Time to fire up `grep`. I'll run a search for that string across the entire kernel source tree. This should reveal where it's defined, used, and, most importantly, which driver or subsystem is associated with it. This is the starting point for understanding its purpose and function within the system.

{
  "Expression": "82p33x1x-phc"
}

{
  "Output": "drivers/mfd/rsmu_core.c=34=static struct mfd_cell rsmu_sabre_devs[] = {\ndrivers/mfd/rsmu_core.c-35-\t[RSMU_PHC] = {\ndrivers/mfd/rsmu_core.c:36:\t\t.name = \"82p33x1x-phc\",\ndrivers/mfd/rsmu_core.c-37-\t},\n--\ndrivers/ptp/ptp_idt82p33.c=1467=static struct platform_driver idt82p33_driver = {\ndrivers/ptp/ptp_idt82p33.c-1468-\t.driver = {\ndrivers/ptp/ptp_idt82p33.c:1469:\t\t.name = \"82p33x1x-phc\",\ndrivers/ptp/ptp_idt82p33.c-1470-\t},\n"
}

							input: 21071
							output: 26
							thoughts: 37

Okay, let's dive into this. Here's my thought process on the matter:

**Delving into the `rsmu` Landscape**

Right, so we need to understand what's creating or interfacing with this `rsmu_sabre_devs` thing, or, perhaps, what is probing a `rsmu` interface. The logical starting point for me, given the context, is definitely the driver space, specifically the multi-function device drivers. Therefore, I’m immediately zeroing in on the `drivers/mfd/rsmu*` directory. That's where I'd expect to find the code responsible for handling this subsystem. Let's see what we can find there.

{
  "Expression": "rsmu",
  "PathPrefix": "drivers/mfd"
}

{
  "Output": "\nFull output is too long, showing 500 out of 507 lines.\nUse more precise expression if possible.\n\ndrivers/mfd/Makefile=299=obj-$(CONFIG_MFD_QNAP_MCU)\t+= qnap-mcu.o\ndrivers/mfd/Makefile-300-\ndrivers/mfd/Makefile:301:obj-$(CONFIG_MFD_RSMU_I2C)\t+= rsmu_i2c.o rsmu_core.o\ndrivers/mfd/Makefile:302:obj-$(CONFIG_MFD_RSMU_SPI)\t+= rsmu_spi.o rsmu_core.o\ndrivers/mfd/Makefile-303-\n--\ndrivers/mfd/rsmu.h-10-\ndrivers/mfd/rsmu.h:11:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/mfd/rsmu.h-12-\n--\ndrivers/mfd/rsmu.h-14-\ndrivers/mfd/rsmu.h:15:int rsmu_core_init(struct rsmu_ddata *rsmu);\ndrivers/mfd/rsmu.h:16:void rsmu_core_exit(struct rsmu_ddata *rsmu);\ndrivers/mfd/rsmu.h-17-\n--\ndrivers/mfd/rsmu_core.c-10-#include \u003clinux/mfd/core.h\u003e\ndrivers/mfd/rsmu_core.c:11:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/mfd/rsmu_core.c-12-#include \u003clinux/module.h\u003e\n--\ndrivers/mfd/rsmu_core.c-16-\ndrivers/mfd/rsmu_core.c:17:#include \"rsmu.h\"\ndrivers/mfd/rsmu_core.c-18-\ndrivers/mfd/rsmu_core.c=19=enum {\n--\ndrivers/mfd/rsmu_core.c-24-\ndrivers/mfd/rsmu_core.c:25:static struct mfd_cell rsmu_cm_devs[] = {\ndrivers/mfd/rsmu_core.c-26-\t[RSMU_PHC] = {\n--\ndrivers/mfd/rsmu_core.c-33-\ndrivers/mfd/rsmu_core.c:34:static struct mfd_cell rsmu_sabre_devs[] = {\ndrivers/mfd/rsmu_core.c-35-\t[RSMU_PHC] = {\n--\ndrivers/mfd/rsmu_core.c-42-\ndrivers/mfd/rsmu_core.c:43:static struct mfd_cell rsmu_sl_devs[] = {\ndrivers/mfd/rsmu_core.c-44-\t[RSMU_PHC] = {\n--\ndrivers/mfd/rsmu_core.c-51-\ndrivers/mfd/rsmu_core.c:52:int rsmu_core_init(struct rsmu_ddata *rsmu)\ndrivers/mfd/rsmu_core.c-53-{\n--\ndrivers/mfd/rsmu_core.c-56-\ndrivers/mfd/rsmu_core.c:57:\tswitch (rsmu-\u003etype) {\ndrivers/mfd/rsmu_core.c-58-\tcase RSMU_CM:\ndrivers/mfd/rsmu_core.c:59:\t\tcells = rsmu_cm_devs;\ndrivers/mfd/rsmu_core.c-60-\t\tbreak;\ndrivers/mfd/rsmu_core.c-61-\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_core.c:62:\t\tcells = rsmu_sabre_devs;\ndrivers/mfd/rsmu_core.c-63-\t\tbreak;\ndrivers/mfd/rsmu_core.c-64-\tcase RSMU_SL:\ndrivers/mfd/rsmu_core.c:65:\t\tcells = rsmu_sl_devs;\ndrivers/mfd/rsmu_core.c-66-\t\tbreak;\ndrivers/mfd/rsmu_core.c-67-\tdefault:\ndrivers/mfd/rsmu_core.c:68:\t\tdev_err(rsmu-\u003edev, \"Unsupported RSMU device type: %d\\n\", rsmu-\u003etype);\ndrivers/mfd/rsmu_core.c-69-\t\treturn -ENODEV;\n--\ndrivers/mfd/rsmu_core.c-71-\ndrivers/mfd/rsmu_core.c:72:\tmutex_init(\u0026rsmu-\u003elock);\ndrivers/mfd/rsmu_core.c-73-\ndrivers/mfd/rsmu_core.c:74:\tret = devm_mfd_add_devices(rsmu-\u003edev, PLATFORM_DEVID_AUTO, cells,\ndrivers/mfd/rsmu_core.c-75-\t\t\t\t   RSMU_N_DEVS, NULL, 0, NULL);\ndrivers/mfd/rsmu_core.c-76-\tif (ret \u003c 0)\ndrivers/mfd/rsmu_core.c:77:\t\tdev_err(rsmu-\u003edev, \"Failed to register sub-devices: %d\\n\", ret);\ndrivers/mfd/rsmu_core.c-78-\n--\ndrivers/mfd/rsmu_core.c-80-}\ndrivers/mfd/rsmu_core.c:81:EXPORT_SYMBOL_GPL(rsmu_core_init);\ndrivers/mfd/rsmu_core.c-82-\ndrivers/mfd/rsmu_core.c:83:void rsmu_core_exit(struct rsmu_ddata *rsmu)\ndrivers/mfd/rsmu_core.c-84-{\ndrivers/mfd/rsmu_core.c:85:\tmutex_destroy(\u0026rsmu-\u003elock);\ndrivers/mfd/rsmu_core.c-86-}\ndrivers/mfd/rsmu_core.c:87:EXPORT_SYMBOL_GPL(rsmu_core_exit);\ndrivers/mfd/rsmu_core.c-88-\n--\ndrivers/mfd/rsmu_i2c.c-11-#include \u003clinux/mfd/core.h\u003e\ndrivers/mfd/rsmu_i2c.c:12:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/mfd/rsmu_i2c.c-13-#include \u003clinux/module.h\u003e\n--\ndrivers/mfd/rsmu_i2c.c-17-\ndrivers/mfd/rsmu_i2c.c:18:#include \"rsmu.h\"\ndrivers/mfd/rsmu_i2c.c-19-\n--\ndrivers/mfd/rsmu_i2c.c-34-\ndrivers/mfd/rsmu_i2c.c:35:typedef int (*rsmu_rw_device)(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u8 bytes);\ndrivers/mfd/rsmu_i2c.c-36-\ndrivers/mfd/rsmu_i2c.c:37:static const struct regmap_range_cfg rsmu_sabre_range_cfg[] = {\ndrivers/mfd/rsmu_i2c.c-38-\t{\n--\ndrivers/mfd/rsmu_i2c.c-48-\ndrivers/mfd/rsmu_i2c.c:49:static bool rsmu_sabre_volatile_reg(struct device *dev, unsigned int reg)\ndrivers/mfd/rsmu_i2c.c-50-{\n--\ndrivers/mfd/rsmu_i2c.c-58-\ndrivers/mfd/rsmu_i2c.c:59:static int rsmu_smbus_i2c_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u8 bytes)\ndrivers/mfd/rsmu_i2c.c-60-{\ndrivers/mfd/rsmu_i2c.c:61:\tstruct i2c_client *client = to_i2c_client(rsmu-\u003edev);\ndrivers/mfd/rsmu_i2c.c-62-\n--\ndrivers/mfd/rsmu_i2c.c-65-\ndrivers/mfd/rsmu_i2c.c:66:static int rsmu_smbus_i2c_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u8 bytes)\ndrivers/mfd/rsmu_i2c.c-67-{\ndrivers/mfd/rsmu_i2c.c:68:\tstruct i2c_client *client = to_i2c_client(rsmu-\u003edev);\ndrivers/mfd/rsmu_i2c.c-69-\tint ret;\n--\ndrivers/mfd/rsmu_i2c.c-79-\ndrivers/mfd/rsmu_i2c.c:80:static int rsmu_i2c_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u8 bytes)\ndrivers/mfd/rsmu_i2c.c-81-{\ndrivers/mfd/rsmu_i2c.c:82:\tstruct i2c_client *client = to_i2c_client(rsmu-\u003edev);\ndrivers/mfd/rsmu_i2c.c-83-\tstruct i2c_msg msg[2];\n--\ndrivers/mfd/rsmu_i2c.c-98-\tif (cnt \u003c 0) {\ndrivers/mfd/rsmu_i2c.c:99:\t\tdev_err(rsmu-\u003edev, \"i2c_transfer failed at addr: %04x!\", reg);\ndrivers/mfd/rsmu_i2c.c-100-\t\treturn cnt;\ndrivers/mfd/rsmu_i2c.c-101-\t} else if (cnt != 2) {\ndrivers/mfd/rsmu_i2c.c:102:\t\tdev_err(rsmu-\u003edev,\ndrivers/mfd/rsmu_i2c.c-103-\t\t\t\"i2c_transfer sent only %d of 2 messages\", cnt);\n--\ndrivers/mfd/rsmu_i2c.c-109-\ndrivers/mfd/rsmu_i2c.c:110:static int rsmu_i2c_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u8 bytes)\ndrivers/mfd/rsmu_i2c.c-111-{\ndrivers/mfd/rsmu_i2c.c:112:\tstruct i2c_client *client = to_i2c_client(rsmu-\u003edev);\ndrivers/mfd/rsmu_i2c.c-113-\t/* we add 1 byte for device register */\n--\ndrivers/mfd/rsmu_i2c.c-133-\ndrivers/mfd/rsmu_i2c.c:134:static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg,\ndrivers/mfd/rsmu_i2c.c:135:\t\t\t\t    rsmu_rw_device rsmu_write_device)\ndrivers/mfd/rsmu_i2c.c-136-{\n--\ndrivers/mfd/rsmu_i2c.c-141-\t/* Simply return if we are on the same page */\ndrivers/mfd/rsmu_i2c.c:142:\tif (rsmu-\u003epage == page)\ndrivers/mfd/rsmu_i2c.c-143-\t\treturn 0;\n--\ndrivers/mfd/rsmu_i2c.c-149-\ndrivers/mfd/rsmu_i2c.c:150:\terr = rsmu_write_device(rsmu, RSMU_CM_PAGE_ADDR, buf, sizeof(buf));\ndrivers/mfd/rsmu_i2c.c-151-\tif (err)\ndrivers/mfd/rsmu_i2c.c:152:\t\tdev_err(rsmu-\u003edev, \"Failed to set page offset 0x%x\\n\", page);\ndrivers/mfd/rsmu_i2c.c-153-\telse\ndrivers/mfd/rsmu_i2c.c-154-\t\t/* Remember the last page */\ndrivers/mfd/rsmu_i2c.c:155:\t\trsmu-\u003epage = page;\ndrivers/mfd/rsmu_i2c.c-156-\n--\ndrivers/mfd/rsmu_i2c.c-159-\ndrivers/mfd/rsmu_i2c.c:160:static int rsmu_i2c_reg_read(void *context, unsigned int reg, unsigned int *val)\ndrivers/mfd/rsmu_i2c.c-161-{\ndrivers/mfd/rsmu_i2c.c:162:\tstruct rsmu_ddata *rsmu = i2c_get_clientdata((struct i2c_client *)context);\ndrivers/mfd/rsmu_i2c.c-163-\tu8 addr = (u8)(reg \u0026 RSMU_CM_ADDRESS_MASK);\n--\ndrivers/mfd/rsmu_i2c.c-165-\ndrivers/mfd/rsmu_i2c.c:166:\terr = rsmu_write_page_register(rsmu, reg, rsmu_i2c_write_device);\ndrivers/mfd/rsmu_i2c.c-167-\tif (err)\n--\ndrivers/mfd/rsmu_i2c.c-169-\ndrivers/mfd/rsmu_i2c.c:170:\terr = rsmu_i2c_read_device(rsmu, addr, (u8 *)val, 1);\ndrivers/mfd/rsmu_i2c.c-171-\tif (err)\ndrivers/mfd/rsmu_i2c.c:172:\t\tdev_err(rsmu-\u003edev, \"Failed to read offset address 0x%x\\n\", addr);\ndrivers/mfd/rsmu_i2c.c-173-\n--\ndrivers/mfd/rsmu_i2c.c-176-\ndrivers/mfd/rsmu_i2c.c:177:static int rsmu_i2c_reg_write(void *context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_i2c.c-178-{\ndrivers/mfd/rsmu_i2c.c:179:\tstruct rsmu_ddata *rsmu = i2c_get_clientdata((struct i2c_client *)context);\ndrivers/mfd/rsmu_i2c.c-180-\tu8 addr = (u8)(reg \u0026 RSMU_CM_ADDRESS_MASK);\n--\ndrivers/mfd/rsmu_i2c.c-183-\ndrivers/mfd/rsmu_i2c.c:184:\terr = rsmu_write_page_register(rsmu, reg, rsmu_i2c_write_device);\ndrivers/mfd/rsmu_i2c.c-185-\tif (err)\n--\ndrivers/mfd/rsmu_i2c.c-187-\ndrivers/mfd/rsmu_i2c.c:188:\terr = rsmu_i2c_write_device(rsmu, addr, \u0026data, 1);\ndrivers/mfd/rsmu_i2c.c-189-\tif (err)\ndrivers/mfd/rsmu_i2c.c:190:\t\tdev_err(rsmu-\u003edev,\ndrivers/mfd/rsmu_i2c.c-191-\t\t\t\"Failed to write offset address 0x%x\\n\", addr);\n--\ndrivers/mfd/rsmu_i2c.c-195-\ndrivers/mfd/rsmu_i2c.c:196:static int rsmu_smbus_i2c_reg_read(void *context, unsigned int reg, unsigned int *val)\ndrivers/mfd/rsmu_i2c.c-197-{\ndrivers/mfd/rsmu_i2c.c:198:\tstruct rsmu_ddata *rsmu = i2c_get_clientdata((struct i2c_client *)context);\ndrivers/mfd/rsmu_i2c.c-199-\tu8 addr = (u8)(reg \u0026 RSMU_CM_ADDRESS_MASK);\n--\ndrivers/mfd/rsmu_i2c.c-201-\ndrivers/mfd/rsmu_i2c.c:202:\terr = rsmu_write_page_register(rsmu, reg, rsmu_smbus_i2c_write_device);\ndrivers/mfd/rsmu_i2c.c-203-\tif (err)\n--\ndrivers/mfd/rsmu_i2c.c-205-\ndrivers/mfd/rsmu_i2c.c:206:\terr = rsmu_smbus_i2c_read_device(rsmu, addr, (u8 *)val, 1);\ndrivers/mfd/rsmu_i2c.c-207-\tif (err)\ndrivers/mfd/rsmu_i2c.c:208:\t\tdev_err(rsmu-\u003edev, \"Failed to read offset address 0x%x\\n\", addr);\ndrivers/mfd/rsmu_i2c.c-209-\n--\ndrivers/mfd/rsmu_i2c.c-212-\ndrivers/mfd/rsmu_i2c.c:213:static int rsmu_smbus_i2c_reg_write(void *context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_i2c.c-214-{\ndrivers/mfd/rsmu_i2c.c:215:\tstruct rsmu_ddata *rsmu = i2c_get_clientdata((struct i2c_client *)context);\ndrivers/mfd/rsmu_i2c.c-216-\tu8 addr = (u8)(reg \u0026 RSMU_CM_ADDRESS_MASK);\n--\ndrivers/mfd/rsmu_i2c.c-219-\ndrivers/mfd/rsmu_i2c.c:220:\terr = rsmu_write_page_register(rsmu, reg, rsmu_smbus_i2c_write_device);\ndrivers/mfd/rsmu_i2c.c-221-\tif (err)\n--\ndrivers/mfd/rsmu_i2c.c-223-\ndrivers/mfd/rsmu_i2c.c:224:\terr = rsmu_smbus_i2c_write_device(rsmu, addr, \u0026data, 1);\ndrivers/mfd/rsmu_i2c.c-225-\tif (err)\ndrivers/mfd/rsmu_i2c.c:226:\t\tdev_err(rsmu-\u003edev,\ndrivers/mfd/rsmu_i2c.c-227-\t\t\t\"Failed to write offset address 0x%x\\n\", addr);\n--\ndrivers/mfd/rsmu_i2c.c-231-\ndrivers/mfd/rsmu_i2c.c:232:static const struct regmap_config rsmu_i2c_cm_regmap_config = {\ndrivers/mfd/rsmu_i2c.c-233-\t.reg_bits = 32,\n--\ndrivers/mfd/rsmu_i2c.c-235-\t.max_register = 0x20120000,\ndrivers/mfd/rsmu_i2c.c:236:\t.reg_read = rsmu_i2c_reg_read,\ndrivers/mfd/rsmu_i2c.c:237:\t.reg_write = rsmu_i2c_reg_write,\ndrivers/mfd/rsmu_i2c.c-238-\t.cache_type = REGCACHE_NONE,\n--\ndrivers/mfd/rsmu_i2c.c-240-\ndrivers/mfd/rsmu_i2c.c:241:static const struct regmap_config rsmu_smbus_i2c_cm_regmap_config = {\ndrivers/mfd/rsmu_i2c.c-242-\t.reg_bits = 32,\n--\ndrivers/mfd/rsmu_i2c.c-244-\t.max_register = 0x20120000,\ndrivers/mfd/rsmu_i2c.c:245:\t.reg_read = rsmu_smbus_i2c_reg_read,\ndrivers/mfd/rsmu_i2c.c:246:\t.reg_write = rsmu_smbus_i2c_reg_write,\ndrivers/mfd/rsmu_i2c.c-247-\t.cache_type = REGCACHE_NONE,\n--\ndrivers/mfd/rsmu_i2c.c-249-\ndrivers/mfd/rsmu_i2c.c:250:static const struct regmap_config rsmu_sabre_regmap_config = {\ndrivers/mfd/rsmu_i2c.c-251-\t.reg_bits = 8,\n--\ndrivers/mfd/rsmu_i2c.c-253-\t.max_register = 0x400,\ndrivers/mfd/rsmu_i2c.c:254:\t.ranges = rsmu_sabre_range_cfg,\ndrivers/mfd/rsmu_i2c.c:255:\t.num_ranges = ARRAY_SIZE(rsmu_sabre_range_cfg),\ndrivers/mfd/rsmu_i2c.c:256:\t.volatile_reg = rsmu_sabre_volatile_reg,\ndrivers/mfd/rsmu_i2c.c-257-\t.cache_type = REGCACHE_MAPLE,\n--\ndrivers/mfd/rsmu_i2c.c-260-\ndrivers/mfd/rsmu_i2c.c:261:static const struct regmap_config rsmu_sl_regmap_config = {\ndrivers/mfd/rsmu_i2c.c-262-\t.reg_bits = 16,\n--\ndrivers/mfd/rsmu_i2c.c-269-\ndrivers/mfd/rsmu_i2c.c:270:static int rsmu_i2c_probe(struct i2c_client *client)\ndrivers/mfd/rsmu_i2c.c-271-{\n--\ndrivers/mfd/rsmu_i2c.c-273-\tconst struct regmap_config *cfg;\ndrivers/mfd/rsmu_i2c.c:274:\tstruct rsmu_ddata *rsmu;\ndrivers/mfd/rsmu_i2c.c-275-\tint ret;\ndrivers/mfd/rsmu_i2c.c-276-\ndrivers/mfd/rsmu_i2c.c:277:\trsmu = devm_kzalloc(\u0026client-\u003edev, sizeof(*rsmu), GFP_KERNEL);\ndrivers/mfd/rsmu_i2c.c:278:\tif (!rsmu)\ndrivers/mfd/rsmu_i2c.c-279-\t\treturn -ENOMEM;\ndrivers/mfd/rsmu_i2c.c-280-\ndrivers/mfd/rsmu_i2c.c:281:\ti2c_set_clientdata(client, rsmu);\ndrivers/mfd/rsmu_i2c.c-282-\ndrivers/mfd/rsmu_i2c.c:283:\trsmu-\u003edev = \u0026client-\u003edev;\ndrivers/mfd/rsmu_i2c.c:284:\trsmu-\u003etype = (enum rsmu_type)id-\u003edriver_data;\ndrivers/mfd/rsmu_i2c.c-285-\ndrivers/mfd/rsmu_i2c.c:286:\tswitch (rsmu-\u003etype) {\ndrivers/mfd/rsmu_i2c.c-287-\tcase RSMU_CM:\ndrivers/mfd/rsmu_i2c.c-288-\t\tif (i2c_check_functionality(client-\u003eadapter, I2C_FUNC_I2C)) {\ndrivers/mfd/rsmu_i2c.c:289:\t\t\tcfg = \u0026rsmu_i2c_cm_regmap_config;\ndrivers/mfd/rsmu_i2c.c-290-\t\t} else if (i2c_check_functionality(client-\u003eadapter,\ndrivers/mfd/rsmu_i2c.c-291-\t\t\t\t\t\t   I2C_FUNC_SMBUS_I2C_BLOCK)) {\ndrivers/mfd/rsmu_i2c.c:292:\t\t\tcfg = \u0026rsmu_smbus_i2c_cm_regmap_config;\ndrivers/mfd/rsmu_i2c.c-293-\t\t} else {\ndrivers/mfd/rsmu_i2c.c:294:\t\t\tdev_err(rsmu-\u003edev, \"Unsupported i2c adapter\\n\");\ndrivers/mfd/rsmu_i2c.c-295-\t\t\treturn -ENOTSUPP;\n--\ndrivers/mfd/rsmu_i2c.c-298-\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_i2c.c:299:\t\tcfg = \u0026rsmu_sabre_regmap_config;\ndrivers/mfd/rsmu_i2c.c-300-\t\tbreak;\ndrivers/mfd/rsmu_i2c.c-301-\tcase RSMU_SL:\ndrivers/mfd/rsmu_i2c.c:302:\t\tcfg = \u0026rsmu_sl_regmap_config;\ndrivers/mfd/rsmu_i2c.c-303-\t\tbreak;\ndrivers/mfd/rsmu_i2c.c-304-\tdefault:\ndrivers/mfd/rsmu_i2c.c:305:\t\tdev_err(rsmu-\u003edev, \"Unsupported RSMU device type: %d\\n\", rsmu-\u003etype);\ndrivers/mfd/rsmu_i2c.c-306-\t\treturn -ENODEV;\n--\ndrivers/mfd/rsmu_i2c.c-308-\ndrivers/mfd/rsmu_i2c.c:309:\tif (rsmu-\u003etype == RSMU_CM)\ndrivers/mfd/rsmu_i2c.c:310:\t\trsmu-\u003eregmap = devm_regmap_init(\u0026client-\u003edev, NULL, client, cfg);\ndrivers/mfd/rsmu_i2c.c-311-\telse\ndrivers/mfd/rsmu_i2c.c:312:\t\trsmu-\u003eregmap = devm_regmap_init_i2c(client, cfg);\ndrivers/mfd/rsmu_i2c.c-313-\ndrivers/mfd/rsmu_i2c.c:314:\tif (IS_ERR(rsmu-\u003eregmap)) {\ndrivers/mfd/rsmu_i2c.c:315:\t\tret = PTR_ERR(rsmu-\u003eregmap);\ndrivers/mfd/rsmu_i2c.c:316:\t\tdev_err(rsmu-\u003edev, \"Failed to allocate register map: %d\\n\", ret);\ndrivers/mfd/rsmu_i2c.c-317-\t\treturn ret;\n--\ndrivers/mfd/rsmu_i2c.c-319-\ndrivers/mfd/rsmu_i2c.c:320:\treturn rsmu_core_init(rsmu);\ndrivers/mfd/rsmu_i2c.c-321-}\ndrivers/mfd/rsmu_i2c.c-322-\ndrivers/mfd/rsmu_i2c.c:323:static void rsmu_i2c_remove(struct i2c_client *client)\ndrivers/mfd/rsmu_i2c.c-324-{\ndrivers/mfd/rsmu_i2c.c:325:\tstruct rsmu_ddata *rsmu = i2c_get_clientdata(client);\ndrivers/mfd/rsmu_i2c.c-326-\ndrivers/mfd/rsmu_i2c.c:327:\trsmu_core_exit(rsmu);\ndrivers/mfd/rsmu_i2c.c-328-}\ndrivers/mfd/rsmu_i2c.c-329-\ndrivers/mfd/rsmu_i2c.c:330:static const struct i2c_device_id rsmu_i2c_id[] = {\ndrivers/mfd/rsmu_i2c.c-331-\t{ \"8a34000\",  RSMU_CM },\n--\ndrivers/mfd/rsmu_i2c.c-339-};\ndrivers/mfd/rsmu_i2c.c:340:MODULE_DEVICE_TABLE(i2c, rsmu_i2c_id);\ndrivers/mfd/rsmu_i2c.c-341-\ndrivers/mfd/rsmu_i2c.c:342:static const struct of_device_id rsmu_i2c_of_match[] = {\ndrivers/mfd/rsmu_i2c.c-343-\t{ .compatible = \"idt,8a34000\",  .data = (void *)RSMU_CM },\n--\ndrivers/mfd/rsmu_i2c.c-351-};\ndrivers/mfd/rsmu_i2c.c:352:MODULE_DEVICE_TABLE(of, rsmu_i2c_of_match);\ndrivers/mfd/rsmu_i2c.c-353-\ndrivers/mfd/rsmu_i2c.c:354:static struct i2c_driver rsmu_i2c_driver = {\ndrivers/mfd/rsmu_i2c.c-355-\t.driver = {\ndrivers/mfd/rsmu_i2c.c:356:\t\t.name = \"rsmu-i2c\",\ndrivers/mfd/rsmu_i2c.c:357:\t\t.of_match_table = rsmu_i2c_of_match,\ndrivers/mfd/rsmu_i2c.c-358-\t},\ndrivers/mfd/rsmu_i2c.c:359:\t.probe = rsmu_i2c_probe,\ndrivers/mfd/rsmu_i2c.c:360:\t.remove\t= rsmu_i2c_remove,\ndrivers/mfd/rsmu_i2c.c:361:\t.id_table = rsmu_i2c_id,\ndrivers/mfd/rsmu_i2c.c-362-};\ndrivers/mfd/rsmu_i2c.c-363-\ndrivers/mfd/rsmu_i2c.c:364:static int __init rsmu_i2c_init(void)\ndrivers/mfd/rsmu_i2c.c-365-{\ndrivers/mfd/rsmu_i2c.c:366:\treturn i2c_add_driver(\u0026rsmu_i2c_driver);\ndrivers/mfd/rsmu_i2c.c-367-}\ndrivers/mfd/rsmu_i2c.c:368:subsys_initcall(rsmu_i2c_init);\ndrivers/mfd/rsmu_i2c.c-369-\ndrivers/mfd/rsmu_i2c.c:370:static void __exit rsmu_i2c_exit(void)\ndrivers/mfd/rsmu_i2c.c-371-{\ndrivers/mfd/rsmu_i2c.c:372:\ti2c_del_driver(\u0026rsmu_i2c_driver);\ndrivers/mfd/rsmu_i2c.c-373-}\ndrivers/mfd/rsmu_i2c.c:374:module_exit(rsmu_i2c_exit);\ndrivers/mfd/rsmu_i2c.c-375-\n--\ndrivers/mfd/rsmu_spi.c-10-#include \u003clinux/mfd/core.h\u003e\ndrivers/mfd/rsmu_spi.c:11:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/mfd/rsmu_spi.c-12-#include \u003clinux/module.h\u003e\n--\ndrivers/mfd/rsmu_spi.c-17-\ndrivers/mfd/rsmu_spi.c:18:#include \"rsmu.h\"\ndrivers/mfd/rsmu_spi.c-19-\n--\ndrivers/mfd/rsmu_spi.c-24-\ndrivers/mfd/rsmu_spi.c:25:static int rsmu_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)\ndrivers/mfd/rsmu_spi.c-26-{\ndrivers/mfd/rsmu_spi.c:27:\tstruct spi_device *client = to_spi_device(rsmu-\u003edev);\ndrivers/mfd/rsmu_spi.c-28-\tstruct spi_transfer xfer = {0};\n--\ndrivers/mfd/rsmu_spi.c-65-\ndrivers/mfd/rsmu_spi.c:66:static int rsmu_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)\ndrivers/mfd/rsmu_spi.c-67-{\ndrivers/mfd/rsmu_spi.c:68:\tstruct spi_device *client = to_spi_device(rsmu-\u003edev);\ndrivers/mfd/rsmu_spi.c-69-\tstruct spi_transfer xfer = {0};\n--\ndrivers/mfd/rsmu_spi.c-93- */\ndrivers/mfd/rsmu_spi.c:94:static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg)\ndrivers/mfd/rsmu_spi.c-95-{\n--\ndrivers/mfd/rsmu_spi.c-101-\ndrivers/mfd/rsmu_spi.c:102:\tswitch (rsmu-\u003etype) {\ndrivers/mfd/rsmu_spi.c-103-\tcase RSMU_CM:\n--\ndrivers/mfd/rsmu_spi.c-122-\tdefault:\ndrivers/mfd/rsmu_spi.c:123:\t\tdev_err(rsmu-\u003edev, \"Unsupported RSMU device type: %d\\n\", rsmu-\u003etype);\ndrivers/mfd/rsmu_spi.c-124-\t\treturn -ENODEV;\n--\ndrivers/mfd/rsmu_spi.c-127-\t/* Simply return if we are on the same page */\ndrivers/mfd/rsmu_spi.c:128:\tif (rsmu-\u003epage == page)\ndrivers/mfd/rsmu_spi.c-129-\t\treturn 0;\ndrivers/mfd/rsmu_spi.c-130-\ndrivers/mfd/rsmu_spi.c:131:\terr = rsmu_write_device(rsmu, page_reg, buf, bytes);\ndrivers/mfd/rsmu_spi.c-132-\tif (err)\ndrivers/mfd/rsmu_spi.c:133:\t\tdev_err(rsmu-\u003edev, \"Failed to set page offset 0x%x\\n\", page);\ndrivers/mfd/rsmu_spi.c-134-\telse\ndrivers/mfd/rsmu_spi.c-135-\t\t/* Remember the last page */\ndrivers/mfd/rsmu_spi.c:136:\t\trsmu-\u003epage = page;\ndrivers/mfd/rsmu_spi.c-137-\n--\ndrivers/mfd/rsmu_spi.c-140-\ndrivers/mfd/rsmu_spi.c:141:static int rsmu_reg_read(void *context, unsigned int reg, unsigned int *val)\ndrivers/mfd/rsmu_spi.c-142-{\ndrivers/mfd/rsmu_spi.c:143:\tstruct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);\ndrivers/mfd/rsmu_spi.c-144-\tu8 addr = (u8)(reg \u0026 RSMU_ADDR_MASK);\n--\ndrivers/mfd/rsmu_spi.c-146-\ndrivers/mfd/rsmu_spi.c:147:\terr = rsmu_write_page_register(rsmu, reg);\ndrivers/mfd/rsmu_spi.c-148-\tif (err)\n--\ndrivers/mfd/rsmu_spi.c-150-\ndrivers/mfd/rsmu_spi.c:151:\terr = rsmu_read_device(rsmu, addr, (u8 *)val, 1);\ndrivers/mfd/rsmu_spi.c-152-\tif (err)\ndrivers/mfd/rsmu_spi.c:153:\t\tdev_err(rsmu-\u003edev, \"Failed to read offset address 0x%x\\n\", addr);\ndrivers/mfd/rsmu_spi.c-154-\n--\ndrivers/mfd/rsmu_spi.c-157-\ndrivers/mfd/rsmu_spi.c:158:static int rsmu_reg_write(void *context, unsigned int reg, unsigned int val)\ndrivers/mfd/rsmu_spi.c-159-{\ndrivers/mfd/rsmu_spi.c:160:\tstruct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);\ndrivers/mfd/rsmu_spi.c-161-\tu8 addr = (u8)(reg \u0026 RSMU_ADDR_MASK);\n--\ndrivers/mfd/rsmu_spi.c-164-\ndrivers/mfd/rsmu_spi.c:165:\terr = rsmu_write_page_register(rsmu, reg);\ndrivers/mfd/rsmu_spi.c-166-\tif (err)\n--\ndrivers/mfd/rsmu_spi.c-168-\ndrivers/mfd/rsmu_spi.c:169:\terr = rsmu_write_device(rsmu, addr, \u0026data, 1);\ndrivers/mfd/rsmu_spi.c-170-\tif (err)\ndrivers/mfd/rsmu_spi.c:171:\t\tdev_err(rsmu-\u003edev,\ndrivers/mfd/rsmu_spi.c-172-\t\t\t\"Failed to write offset address 0x%x\\n\", addr);\n--\ndrivers/mfd/rsmu_spi.c-176-\ndrivers/mfd/rsmu_spi.c:177:static const struct regmap_config rsmu_cm_regmap_config = {\ndrivers/mfd/rsmu_spi.c-178-\t.reg_bits = 32,\n--\ndrivers/mfd/rsmu_spi.c-180-\t.max_register = 0x20120000,\ndrivers/mfd/rsmu_spi.c:181:\t.reg_read = rsmu_reg_read,\ndrivers/mfd/rsmu_spi.c:182:\t.reg_write = rsmu_reg_write,\ndrivers/mfd/rsmu_spi.c-183-\t.cache_type = REGCACHE_NONE,\n--\ndrivers/mfd/rsmu_spi.c-185-\ndrivers/mfd/rsmu_spi.c:186:static const struct regmap_config rsmu_sabre_regmap_config = {\ndrivers/mfd/rsmu_spi.c-187-\t.reg_bits = 16,\n--\ndrivers/mfd/rsmu_spi.c-189-\t.max_register = 0x400,\ndrivers/mfd/rsmu_spi.c:190:\t.reg_read = rsmu_reg_read,\ndrivers/mfd/rsmu_spi.c:191:\t.reg_write = rsmu_reg_write,\ndrivers/mfd/rsmu_spi.c-192-\t.cache_type = REGCACHE_NONE,\n--\ndrivers/mfd/rsmu_spi.c-194-\ndrivers/mfd/rsmu_spi.c:195:static int rsmu_spi_probe(struct spi_device *client)\ndrivers/mfd/rsmu_spi.c-196-{\n--\ndrivers/mfd/rsmu_spi.c-198-\tconst struct regmap_config *cfg;\ndrivers/mfd/rsmu_spi.c:199:\tstruct rsmu_ddata *rsmu;\ndrivers/mfd/rsmu_spi.c-200-\tint ret;\ndrivers/mfd/rsmu_spi.c-201-\ndrivers/mfd/rsmu_spi.c:202:\trsmu = devm_kzalloc(\u0026client-\u003edev, sizeof(*rsmu), GFP_KERNEL);\ndrivers/mfd/rsmu_spi.c:203:\tif (!rsmu)\ndrivers/mfd/rsmu_spi.c-204-\t\treturn -ENOMEM;\ndrivers/mfd/rsmu_spi.c-205-\ndrivers/mfd/rsmu_spi.c:206:\tspi_set_drvdata(client, rsmu);\ndrivers/mfd/rsmu_spi.c-207-\ndrivers/mfd/rsmu_spi.c:208:\trsmu-\u003edev = \u0026client-\u003edev;\ndrivers/mfd/rsmu_spi.c:209:\trsmu-\u003etype = (enum rsmu_type)id-\u003edriver_data;\ndrivers/mfd/rsmu_spi.c-210-\ndrivers/mfd/rsmu_spi.c-211-\t/* Initialize regmap */\ndrivers/mfd/rsmu_spi.c:212:\tswitch (rsmu-\u003etype) {\ndrivers/mfd/rsmu_spi.c-213-\tcase RSMU_CM:\ndrivers/mfd/rsmu_spi.c:214:\t\tcfg = \u0026rsmu_cm_regmap_config;\ndrivers/mfd/rsmu_spi.c-215-\t\tbreak;\ndrivers/mfd/rsmu_spi.c-216-\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_spi.c:217:\t\tcfg = \u0026rsmu_sabre_regmap_config;\ndrivers/mfd/rsmu_spi.c-218-\t\tbreak;\ndrivers/mfd/rsmu_spi.c-219-\tdefault:\ndrivers/mfd/rsmu_spi.c:220:\t\tdev_err(rsmu-\u003edev, \"Unsupported RSMU device type: %d\\n\", rsmu-\u003etype);\ndrivers/mfd/rsmu_spi.c-221-\t\treturn -ENODEV;\n--\ndrivers/mfd/rsmu_spi.c-223-\ndrivers/mfd/rsmu_spi.c:224:\trsmu-\u003eregmap = devm_regmap_init(\u0026client-\u003edev, NULL, client, cfg);\ndrivers/mfd/rsmu_spi.c:225:\tif (IS_ERR(rsmu-\u003eregmap)) {\ndrivers/mfd/rsmu_spi.c:226:\t\tret = PTR_ERR(rsmu-\u003eregmap);\ndrivers/mfd/rsmu_spi.c:227:\t\tdev_err(rsmu-\u003edev, \"Failed to allocate register map: %d\\n\", ret);\ndrivers/mfd/rsmu_spi.c-228-\t\treturn ret;\n--\ndrivers/mfd/rsmu_spi.c-230-\ndrivers/mfd/rsmu_spi.c:231:\treturn rsmu_core_init(rsmu);\ndrivers/mfd/rsmu_spi.c-232-}\ndrivers/mfd/rsmu_spi.c-233-\ndrivers/mfd/rsmu_spi.c:234:static void rsmu_spi_remove(struct spi_device *client)\ndrivers/mfd/rsmu_spi.c-235-{\ndrivers/mfd/rsmu_spi.c:236:\tstruct rsmu_ddata *rsmu = spi_get_drvdata(client);\ndrivers/mfd/rsmu_spi.c-237-\ndrivers/mfd/rsmu_spi.c:238:\trsmu_core_exit(rsmu);\ndrivers/mfd/rsmu_spi.c-239-}\ndrivers/mfd/rsmu_spi.c-240-\ndrivers/mfd/rsmu_spi.c:241:static const struct spi_device_id rsmu_spi_id[] = {\ndrivers/mfd/rsmu_spi.c-242-\t{ .name = \"8a34000\", .driver_data = RSMU_CM },\n--\ndrivers/mfd/rsmu_spi.c-248-};\ndrivers/mfd/rsmu_spi.c:249:MODULE_DEVICE_TABLE(spi, rsmu_spi_id);\ndrivers/mfd/rsmu_spi.c-250-\ndrivers/mfd/rsmu_spi.c:251:static const struct of_device_id rsmu_spi_of_match[] = {\ndrivers/mfd/rsmu_spi.c-252-\t{ .compatible = \"idt,8a34000\",  .data = (void *)RSMU_CM },\n--\ndrivers/mfd/rsmu_spi.c-258-};\ndrivers/mfd/rsmu_spi.c:259:MODULE_DEVICE_TABLE(of, rsmu_spi_of_match);\ndrivers/mfd/rsmu_spi.c-260-\ndrivers/mfd/rsmu_spi.c:261:static struct spi_driver rsmu_spi_driver = {\ndrivers/mfd/rsmu_spi.c-262-\t.driver = {\ndrivers/mfd/rsmu_spi.c:263:\t\t.name = \"rsmu-spi\",\ndrivers/mfd/rsmu_spi.c:264:\t\t.of_match_table = rsmu_spi_of_match,\ndrivers/mfd/rsmu_spi.c-265-\t},\ndrivers/mfd/rsmu_spi.c:266:\t.probe = rsmu_spi_probe,\ndrivers/mfd/rsmu_spi.c:267:\t.remove\t= rsmu_spi_remove,\ndrivers/mfd/rsmu_spi.c:268:\t.id_table = rsmu_spi_id,\ndrivers/mfd/rsmu_spi.c-269-};\ndrivers/mfd/rsmu_spi.c-270-\ndrivers/mfd/rsmu_spi.c:271:static int __init rsmu_spi_init(void)\ndrivers/mfd/rsmu_spi.c-272-{\ndrivers/mfd/rsmu_spi.c:273:\treturn spi_register_driver(\u0026rsmu_spi_driver);\ndrivers/mfd/rsmu_spi.c-274-}\ndrivers/mfd/rsmu_spi.c:275:subsys_initcall(rsmu_spi_init);\n\n"
}

							input: 33419
							output: 30
							thoughts: 55

Okay, let's dive into this. Here's how I'd approach this analysis:

**Analyzing RSMU Device Identification**

Right, so I need to understand how the system identifies devices that use the `RSMU_SABRE` protocol. My initial thought is to examine the device driver code, specifically the `rsmu_i2c` and `rsmu_spi` drivers. That seems like the logical place to start.

I'm thinking, "Which specific devices are recognized as `RSMU_SABRE`?" To answer that question, I'll need to look closely at the device ID tables. That means scrutinizing the `rsmu_i2c_id` and `rsmu_spi_id` data structures. These tables should contain the relevant information mapping device identifiers to the `RSMU_SABRE` protocol. I'm expecting to find a list of vendor and device IDs, or perhaps some other unique identifiers, that trigger the system to associate a device with this particular protocol. I anticipate finding this information within the ID tables.

{
  "Expression": "RSMU_SABRE",
  "PathPrefix": "drivers/mfd"
}

{
  "Output": "drivers/mfd/rsmu_core.c=52=int rsmu_core_init(struct rsmu_ddata *rsmu)\n--\ndrivers/mfd/rsmu_core.c-60-\t\tbreak;\ndrivers/mfd/rsmu_core.c:61:\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_core.c-62-\t\tcells = rsmu_sabre_devs;\n--\ndrivers/mfd/rsmu_i2c.c-31- */\ndrivers/mfd/rsmu_i2c.c:32:#define\tRSMU_SABRE_PAGE_ADDR\t\t0x7F\ndrivers/mfd/rsmu_i2c.c:33:#define\tRSMU_SABRE_PAGE_WINDOW\t\t128\ndrivers/mfd/rsmu_i2c.c-34-\n--\ndrivers/mfd/rsmu_i2c.c=37=static const struct regmap_range_cfg rsmu_sabre_range_cfg[] = {\n--\ndrivers/mfd/rsmu_i2c.c-40-\t\t.range_max = 0x400,\ndrivers/mfd/rsmu_i2c.c:41:\t\t.selector_reg = RSMU_SABRE_PAGE_ADDR,\ndrivers/mfd/rsmu_i2c.c-42-\t\t.selector_mask = 0xFF,\n--\ndrivers/mfd/rsmu_i2c.c-44-\t\t.window_start = 0,\ndrivers/mfd/rsmu_i2c.c:45:\t\t.window_len = RSMU_SABRE_PAGE_WINDOW,\ndrivers/mfd/rsmu_i2c.c-46-\t}\n--\ndrivers/mfd/rsmu_i2c.c=49=static bool rsmu_sabre_volatile_reg(struct device *dev, unsigned int reg)\n--\ndrivers/mfd/rsmu_i2c.c-51-\tswitch (reg) {\ndrivers/mfd/rsmu_i2c.c:52:\tcase RSMU_SABRE_PAGE_ADDR:\ndrivers/mfd/rsmu_i2c.c-53-\t\treturn false;\n--\ndrivers/mfd/rsmu_i2c.c=270=static int rsmu_i2c_probe(struct i2c_client *client)\n--\ndrivers/mfd/rsmu_i2c.c-297-\t\tbreak;\ndrivers/mfd/rsmu_i2c.c:298:\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_i2c.c-299-\t\tcfg = \u0026rsmu_sabre_regmap_config;\n--\ndrivers/mfd/rsmu_i2c.c=330=static const struct i2c_device_id rsmu_i2c_id[] = {\n--\ndrivers/mfd/rsmu_i2c.c-333-\t{ \"8a34002\",  RSMU_CM },\ndrivers/mfd/rsmu_i2c.c:334:\t{ \"82p33810\", RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c:335:\t{ \"82p33811\", RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c-336-\t{ \"8v19n850\", RSMU_SL },\n--\ndrivers/mfd/rsmu_i2c.c=342=static const struct of_device_id rsmu_i2c_of_match[] = {\n--\ndrivers/mfd/rsmu_i2c.c-345-\t{ .compatible = \"idt,8a34002\",  .data = (void *)RSMU_CM },\ndrivers/mfd/rsmu_i2c.c:346:\t{ .compatible = \"idt,82p33810\", .data = (void *)RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c:347:\t{ .compatible = \"idt,82p33811\", .data = (void *)RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c-348-\t{ .compatible = \"idt,8v19n850\", .data = (void *)RSMU_SL },\n--\ndrivers/mfd/rsmu_spi.c-20-#define\tRSMU_CM_PAGE_ADDR\t\t0x7C\ndrivers/mfd/rsmu_spi.c:21:#define\tRSMU_SABRE_PAGE_ADDR\t\t0x7F\ndrivers/mfd/rsmu_spi.c-22-#define\tRSMU_PAGE_MASK\t\t\t0xFFFFFF80\n--\ndrivers/mfd/rsmu_spi.c=94=static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg)\n--\ndrivers/mfd/rsmu_spi.c-111-\t\tbreak;\ndrivers/mfd/rsmu_spi.c:112:\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_spi.c-113-\t\t/* Do not modify page register if reg is page register itself */\n--\ndrivers/mfd/rsmu_spi.c-115-\t\t\treturn 0;\ndrivers/mfd/rsmu_spi.c:116:\t\tpage_reg = RSMU_SABRE_PAGE_ADDR;\ndrivers/mfd/rsmu_spi.c-117-\t\tpage = reg \u0026 RSMU_PAGE_MASK;\n--\ndrivers/mfd/rsmu_spi.c=195=static int rsmu_spi_probe(struct spi_device *client)\n--\ndrivers/mfd/rsmu_spi.c-215-\t\tbreak;\ndrivers/mfd/rsmu_spi.c:216:\tcase RSMU_SABRE:\ndrivers/mfd/rsmu_spi.c-217-\t\tcfg = \u0026rsmu_sabre_regmap_config;\n--\ndrivers/mfd/rsmu_spi.c=241=static const struct spi_device_id rsmu_spi_id[] = {\n--\ndrivers/mfd/rsmu_spi.c-244-\t{ .name = \"8a34002\", .driver_data = RSMU_CM },\ndrivers/mfd/rsmu_spi.c:245:\t{ .name = \"82p33810\", .driver_data = RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c:246:\t{ .name = \"82p33811\", .driver_data = RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c-247-\t{ }\n--\ndrivers/mfd/rsmu_spi.c=251=static const struct of_device_id rsmu_spi_of_match[] = {\n--\ndrivers/mfd/rsmu_spi.c-254-\t{ .compatible = \"idt,8a34002\",  .data = (void *)RSMU_CM },\ndrivers/mfd/rsmu_spi.c:255:\t{ .compatible = \"idt,82p33810\", .data = (void *)RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c:256:\t{ .compatible = \"idt,82p33811\", .data = (void *)RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c-257-\t{}\n"
}

							input: 35660
							output: 37
							thoughts: 1879

**WorthFuzzing Analysis: IDT82P33 Driver Patch**

Okay, so `82p33810` and `82p33811` are pointing me towards I2C or SPI devices, potentially. The initial question is whether these can be instantiated in standard fuzzing environments like QEMU or syzkaller. Does syzkaller even *support* these types of devices? Specifically, does it have an emulated I2C bus or some way to interact with devices via `/sys/bus/i2c/devices/.../new_device`? I should check syzkaller's sysfs and I2C support docs, or, better yet, just reread the directions on how to determine if something is worth fuzzing.

Right, the guide. The primary thing to consider is reachability. Does the modified code execute in standard virtualized environments? Section 2 outlines when to return `WorthFuzzing=false`. It's *only* when the code falls into categories like non-executable changes or structurally unreachable hardware. Specifically, things like vendor-specific PCIe cards not emulated in QEMU. Also, drivers which are only accessed during PCI hot unplug or manual sysfs unbinding. Section 3 outlines the opposite, when to return `WorthFuzzing=true`.

Now, is `ptp_idt82p33` reachable? Let's look at the patch itself to find out.

Looking at the diff, it seems the patch is primarily adding checks for a `stopping` flag within `idt82p33`. It's using `mutex_lock` around critical sections. It's adding `stopping = true` in `idt82p33_ptp_clock_unregister_all` before canceling delayed works. It is also returning `-ENODEV` (Device Not Found) inside `idt82p33_enable` and `idt82p33_adjtime` if `stopping` is true, and it adds a `goto out` right after the check. Finally, it adds another stopping check in `idt82p33_extts_check`. The patch also looks like it removes `cancel_delayed_work_sync(&idt82p33->extts_work)` from `idt82p33_remove` function.

Now that I've looked at the patch, the commit log should help me to determine why it was changed.

{
  "Expression": ".*",
  "PathPrefix": "drivers/ptp/ptp_idt82p33.c"
}

{
  "Output": "\nFull output is too long, showing 500 out of 1475 lines.\nUse more precise expression if possible.\n\ndrivers/ptp/ptp_idt82p33.c:1:// SPDX-License-Identifier: GPL-2.0\ndrivers/ptp/ptp_idt82p33.c:2://\ndrivers/ptp/ptp_idt82p33.c:3:// Copyright (C) 2018 Integrated Device Technology, Inc\ndrivers/ptp/ptp_idt82p33.c:4://\ndrivers/ptp/ptp_idt82p33.c:5:\ndrivers/ptp/ptp_idt82p33.c:6:#define pr_fmt(fmt) \"IDT_82p33xxx: \" fmt\ndrivers/ptp/ptp_idt82p33.c:7:\ndrivers/ptp/ptp_idt82p33.c:8:#include \u003clinux/firmware.h\u003e\ndrivers/ptp/ptp_idt82p33.c:9:#include \u003clinux/platform_device.h\u003e\ndrivers/ptp/ptp_idt82p33.c:10:#include \u003clinux/module.h\u003e\ndrivers/ptp/ptp_idt82p33.c:11:#include \u003clinux/ptp_clock_kernel.h\u003e\ndrivers/ptp/ptp_idt82p33.c:12:#include \u003clinux/delay.h\u003e\ndrivers/ptp/ptp_idt82p33.c:13:#include \u003clinux/jiffies.h\u003e\ndrivers/ptp/ptp_idt82p33.c:14:#include \u003clinux/kernel.h\u003e\ndrivers/ptp/ptp_idt82p33.c:15:#include \u003clinux/timekeeping.h\u003e\ndrivers/ptp/ptp_idt82p33.c:16:#include \u003clinux/bitops.h\u003e\ndrivers/ptp/ptp_idt82p33.c:17:#include \u003clinux/of.h\u003e\ndrivers/ptp/ptp_idt82p33.c:18:#include \u003clinux/mfd/rsmu.h\u003e\ndrivers/ptp/ptp_idt82p33.c:19:#include \u003clinux/mfd/idt82p33_reg.h\u003e\ndrivers/ptp/ptp_idt82p33.c:20:\ndrivers/ptp/ptp_idt82p33.c:21:#include \"ptp_private.h\"\ndrivers/ptp/ptp_idt82p33.c:22:#include \"ptp_idt82p33.h\"\ndrivers/ptp/ptp_idt82p33.c:23:\ndrivers/ptp/ptp_idt82p33.c:24:MODULE_DESCRIPTION(\"Driver for IDT 82p33xxx clock devices\");\ndrivers/ptp/ptp_idt82p33.c:25:MODULE_AUTHOR(\"IDT support-1588 \u003cIDT-support-1588@lm.renesas.com\u003e\");\ndrivers/ptp/ptp_idt82p33.c:26:MODULE_VERSION(\"1.0\");\ndrivers/ptp/ptp_idt82p33.c:27:MODULE_LICENSE(\"GPL\");\ndrivers/ptp/ptp_idt82p33.c:28:MODULE_FIRMWARE(FW_FILENAME);\ndrivers/ptp/ptp_idt82p33.c:29:\ndrivers/ptp/ptp_idt82p33.c:30:#define EXTTS_PERIOD_MS (95)\ndrivers/ptp/ptp_idt82p33.c:31:\ndrivers/ptp/ptp_idt82p33.c:32:/* Module Parameters */\ndrivers/ptp/ptp_idt82p33.c:33:static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;\ndrivers/ptp/ptp_idt82p33.c:34:module_param(phase_snap_threshold, uint, 0);\ndrivers/ptp/ptp_idt82p33.c:35:MODULE_PARM_DESC(phase_snap_threshold,\ndrivers/ptp/ptp_idt82p33.c:36:\"threshold (10000ns by default) below which adjtime would use double dco\");\ndrivers/ptp/ptp_idt82p33.c:37:\ndrivers/ptp/ptp_idt82p33.c:38:static char *firmware;\ndrivers/ptp/ptp_idt82p33.c:39:module_param(firmware, charp, 0);\ndrivers/ptp/ptp_idt82p33.c:40:\ndrivers/ptp/ptp_idt82p33.c:41:static struct ptp_pin_desc pin_config[MAX_PHC_PLL][MAX_TRIG_CLK];\ndrivers/ptp/ptp_idt82p33.c:42:\ndrivers/ptp/ptp_idt82p33.c:43:static inline int idt82p33_read(struct idt82p33 *idt82p33, u16 regaddr,\ndrivers/ptp/ptp_idt82p33.c:44:\t\t\t\tu8 *buf, u16 count)\ndrivers/ptp/ptp_idt82p33.c:45:{\ndrivers/ptp/ptp_idt82p33.c:46:\treturn regmap_bulk_read(idt82p33-\u003eregmap, regaddr, buf, count);\ndrivers/ptp/ptp_idt82p33.c:47:}\ndrivers/ptp/ptp_idt82p33.c:48:\ndrivers/ptp/ptp_idt82p33.c:49:static inline int idt82p33_write(struct idt82p33 *idt82p33, u16 regaddr,\ndrivers/ptp/ptp_idt82p33.c:50:\t\t\t\t u8 *buf, u16 count)\ndrivers/ptp/ptp_idt82p33.c:51:{\ndrivers/ptp/ptp_idt82p33.c:52:\treturn regmap_bulk_write(idt82p33-\u003eregmap, regaddr, buf, count);\ndrivers/ptp/ptp_idt82p33.c:53:}\ndrivers/ptp/ptp_idt82p33.c:54:\ndrivers/ptp/ptp_idt82p33.c:55:static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,\ndrivers/ptp/ptp_idt82p33.c:56:\t\t\t\t\t    u8 buf[TOD_BYTE_COUNT])\ndrivers/ptp/ptp_idt82p33.c:57:{\ndrivers/ptp/ptp_idt82p33.c:58:\ttime64_t sec;\ndrivers/ptp/ptp_idt82p33.c:59:\ts32 nsec;\ndrivers/ptp/ptp_idt82p33.c:60:\tu8 i;\ndrivers/ptp/ptp_idt82p33.c:61:\ndrivers/ptp/ptp_idt82p33.c:62:\tnsec = buf[3];\ndrivers/ptp/ptp_idt82p33.c:63:\tfor (i = 0; i \u003c 3; i++) {\ndrivers/ptp/ptp_idt82p33.c:64:\t\tnsec \u003c\u003c= 8;\ndrivers/ptp/ptp_idt82p33.c:65:\t\tnsec |= buf[2 - i];\ndrivers/ptp/ptp_idt82p33.c:66:\t}\ndrivers/ptp/ptp_idt82p33.c:67:\ndrivers/ptp/ptp_idt82p33.c:68:\tsec = buf[9];\ndrivers/ptp/ptp_idt82p33.c:69:\tfor (i = 0; i \u003c 5; i++) {\ndrivers/ptp/ptp_idt82p33.c:70:\t\tsec \u003c\u003c= 8;\ndrivers/ptp/ptp_idt82p33.c:71:\t\tsec |= buf[8 - i];\ndrivers/ptp/ptp_idt82p33.c:72:\t}\ndrivers/ptp/ptp_idt82p33.c:73:\ndrivers/ptp/ptp_idt82p33.c:74:\tts-\u003etv_sec = sec;\ndrivers/ptp/ptp_idt82p33.c:75:\tts-\u003etv_nsec = nsec;\ndrivers/ptp/ptp_idt82p33.c:76:}\ndrivers/ptp/ptp_idt82p33.c:77:\ndrivers/ptp/ptp_idt82p33.c:78:static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,\ndrivers/ptp/ptp_idt82p33.c:79:\t\t\t\t\t    u8 buf[TOD_BYTE_COUNT])\ndrivers/ptp/ptp_idt82p33.c:80:{\ndrivers/ptp/ptp_idt82p33.c:81:\ttime64_t sec;\ndrivers/ptp/ptp_idt82p33.c:82:\ts32 nsec;\ndrivers/ptp/ptp_idt82p33.c:83:\tu8 i;\ndrivers/ptp/ptp_idt82p33.c:84:\ndrivers/ptp/ptp_idt82p33.c:85:\tnsec = ts-\u003etv_nsec;\ndrivers/ptp/ptp_idt82p33.c:86:\tsec = ts-\u003etv_sec;\ndrivers/ptp/ptp_idt82p33.c:87:\ndrivers/ptp/ptp_idt82p33.c:88:\tfor (i = 0; i \u003c 4; i++) {\ndrivers/ptp/ptp_idt82p33.c:89:\t\tbuf[i] = nsec \u0026 0xff;\ndrivers/ptp/ptp_idt82p33.c:90:\t\tnsec \u003e\u003e= 8;\ndrivers/ptp/ptp_idt82p33.c:91:\t}\ndrivers/ptp/ptp_idt82p33.c:92:\ndrivers/ptp/ptp_idt82p33.c:93:\tfor (i = 4; i \u003c TOD_BYTE_COUNT; i++) {\ndrivers/ptp/ptp_idt82p33.c:94:\t\tbuf[i] = sec \u0026 0xff;\ndrivers/ptp/ptp_idt82p33.c:95:\t\tsec \u003e\u003e= 8;\ndrivers/ptp/ptp_idt82p33.c:96:\t}\ndrivers/ptp/ptp_idt82p33.c:97:}\ndrivers/ptp/ptp_idt82p33.c:98:\ndrivers/ptp/ptp_idt82p33.c:99:static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:100:\t\t\t\t  enum pll_mode mode)\ndrivers/ptp/ptp_idt82p33.c:101:{\ndrivers/ptp/ptp_idt82p33.c:102:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:103:\tu8 dpll_mode;\ndrivers/ptp/ptp_idt82p33.c:104:\tint err;\ndrivers/ptp/ptp_idt82p33.c:105:\ndrivers/ptp/ptp_idt82p33.c:106:\tif (channel-\u003epll_mode == mode)\ndrivers/ptp/ptp_idt82p33.c:107:\t\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:108:\ndrivers/ptp/ptp_idt82p33.c:109:\terr = idt82p33_read(idt82p33, channel-\u003edpll_mode_cnfg,\ndrivers/ptp/ptp_idt82p33.c:110:\t\t\t    \u0026dpll_mode, sizeof(dpll_mode));\ndrivers/ptp/ptp_idt82p33.c:111:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:112:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:113:\ndrivers/ptp/ptp_idt82p33.c:114:\tdpll_mode \u0026= ~(PLL_MODE_MASK \u003c\u003c PLL_MODE_SHIFT);\ndrivers/ptp/ptp_idt82p33.c:115:\ndrivers/ptp/ptp_idt82p33.c:116:\tdpll_mode |= (mode \u003c\u003c PLL_MODE_SHIFT);\ndrivers/ptp/ptp_idt82p33.c:117:\ndrivers/ptp/ptp_idt82p33.c:118:\terr = idt82p33_write(idt82p33, channel-\u003edpll_mode_cnfg,\ndrivers/ptp/ptp_idt82p33.c:119:\t\t\t     \u0026dpll_mode, sizeof(dpll_mode));\ndrivers/ptp/ptp_idt82p33.c:120:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:121:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:122:\ndrivers/ptp/ptp_idt82p33.c:123:\tchannel-\u003epll_mode = mode;\ndrivers/ptp/ptp_idt82p33.c:124:\ndrivers/ptp/ptp_idt82p33.c:125:\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:126:}\ndrivers/ptp/ptp_idt82p33.c:127:\ndrivers/ptp/ptp_idt82p33.c:128:static int idt82p33_set_tod_trigger(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:129:\t\t\t\t    u8 trigger, bool write)\ndrivers/ptp/ptp_idt82p33.c:130:{\ndrivers/ptp/ptp_idt82p33.c:131:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:132:\tint err;\ndrivers/ptp/ptp_idt82p33.c:133:\tu8 cfg;\ndrivers/ptp/ptp_idt82p33.c:134:\ndrivers/ptp/ptp_idt82p33.c:135:\tif (trigger \u003e WR_TRIG_SEL_MAX)\ndrivers/ptp/ptp_idt82p33.c:136:\t\treturn -EINVAL;\ndrivers/ptp/ptp_idt82p33.c:137:\ndrivers/ptp/ptp_idt82p33.c:138:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c:139:\t\t\t    \u0026cfg, sizeof(cfg));\ndrivers/ptp/ptp_idt82p33.c:140:\ndrivers/ptp/ptp_idt82p33.c:141:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:142:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:143:\ndrivers/ptp/ptp_idt82p33.c:144:\tif (write == true)\ndrivers/ptp/ptp_idt82p33.c:145:\t\ttrigger = (trigger \u003c\u003c WRITE_TRIGGER_SHIFT) |\ndrivers/ptp/ptp_idt82p33.c:146:\t\t\t  (cfg \u0026 READ_TRIGGER_MASK);\ndrivers/ptp/ptp_idt82p33.c:147:\telse\ndrivers/ptp/ptp_idt82p33.c:148:\t\ttrigger = (trigger \u003c\u003c READ_TRIGGER_SHIFT) |\ndrivers/ptp/ptp_idt82p33.c:149:\t\t\t  (cfg \u0026 WRITE_TRIGGER_MASK);\ndrivers/ptp/ptp_idt82p33.c:150:\ndrivers/ptp/ptp_idt82p33.c:151:\treturn idt82p33_write(idt82p33, channel-\u003edpll_tod_trigger,\ndrivers/ptp/ptp_idt82p33.c:152:\t\t\t      \u0026trigger, sizeof(trigger));\ndrivers/ptp/ptp_idt82p33.c:153:}\ndrivers/ptp/ptp_idt82p33.c:154:\ndrivers/ptp/ptp_idt82p33.c:155:static int idt82p33_get_extts(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:156:\t\t\t      struct timespec64 *ts)\ndrivers/ptp/ptp_idt82p33.c:157:{\ndrivers/ptp/ptp_idt82p33.c:158:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:159:\tu8 buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:160:\tint err;\ndrivers/ptp/ptp_idt82p33.c:161:\ndrivers/ptp/ptp_idt82p33.c:162:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c:163:\ndrivers/ptp/ptp_idt82p33.c:164:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:165:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:166:\ndrivers/ptp/ptp_idt82p33.c:167:\t/* Since trigger is not self clearing itself, we have to poll tod_sts */\ndrivers/ptp/ptp_idt82p33.c:168:\tif (memcmp(buf, channel-\u003eextts_tod_sts, TOD_BYTE_COUNT) == 0)\ndrivers/ptp/ptp_idt82p33.c:169:\t\treturn -EAGAIN;\ndrivers/ptp/ptp_idt82p33.c:170:\ndrivers/ptp/ptp_idt82p33.c:171:\tmemcpy(channel-\u003eextts_tod_sts, buf, TOD_BYTE_COUNT);\ndrivers/ptp/ptp_idt82p33.c:172:\ndrivers/ptp/ptp_idt82p33.c:173:\tidt82p33_byte_array_to_timespec(ts, buf);\ndrivers/ptp/ptp_idt82p33.c:174:\ndrivers/ptp/ptp_idt82p33.c:175:\tif (channel-\u003ediscard_next_extts) {\ndrivers/ptp/ptp_idt82p33.c:176:\t\tchannel-\u003ediscard_next_extts = false;\ndrivers/ptp/ptp_idt82p33.c:177:\t\treturn -EAGAIN;\ndrivers/ptp/ptp_idt82p33.c:178:\t}\ndrivers/ptp/ptp_idt82p33.c:179:\ndrivers/ptp/ptp_idt82p33.c:180:\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:181:}\ndrivers/ptp/ptp_idt82p33.c:182:\ndrivers/ptp/ptp_idt82p33.c:183:static int map_ref_to_tod_trig_sel(int ref, u8 *trigger)\ndrivers/ptp/ptp_idt82p33.c:184:{\ndrivers/ptp/ptp_idt82p33.c:185:\tint err = 0;\ndrivers/ptp/ptp_idt82p33.c:186:\ndrivers/ptp/ptp_idt82p33.c:187:\tswitch (ref) {\ndrivers/ptp/ptp_idt82p33.c:188:\tcase 0:\ndrivers/ptp/ptp_idt82p33.c:189:\t\t*trigger = HW_TOD_TRIG_SEL_IN12;\ndrivers/ptp/ptp_idt82p33.c:190:\t\tbreak;\ndrivers/ptp/ptp_idt82p33.c:191:\tcase 1:\ndrivers/ptp/ptp_idt82p33.c:192:\t\t*trigger = HW_TOD_TRIG_SEL_IN13;\ndrivers/ptp/ptp_idt82p33.c:193:\t\tbreak;\ndrivers/ptp/ptp_idt82p33.c:194:\tcase 2:\ndrivers/ptp/ptp_idt82p33.c:195:\t\t*trigger = HW_TOD_TRIG_SEL_IN14;\ndrivers/ptp/ptp_idt82p33.c:196:\t\tbreak;\ndrivers/ptp/ptp_idt82p33.c:197:\tdefault:\ndrivers/ptp/ptp_idt82p33.c:198:\t\terr = -EINVAL;\ndrivers/ptp/ptp_idt82p33.c:199:\t}\ndrivers/ptp/ptp_idt82p33.c:200:\ndrivers/ptp/ptp_idt82p33.c:201:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:202:}\ndrivers/ptp/ptp_idt82p33.c:203:\ndrivers/ptp/ptp_idt82p33.c:204:static bool is_one_shot(u8 mask)\ndrivers/ptp/ptp_idt82p33.c:205:{\ndrivers/ptp/ptp_idt82p33.c:206:\t/* Treat single bit PLL masks as continuous trigger */\ndrivers/ptp/ptp_idt82p33.c:207:\tif ((mask == 1) || (mask == 2))\ndrivers/ptp/ptp_idt82p33.c:208:\t\treturn false;\ndrivers/ptp/ptp_idt82p33.c:209:\telse\ndrivers/ptp/ptp_idt82p33.c:210:\t\treturn true;\ndrivers/ptp/ptp_idt82p33.c:211:}\ndrivers/ptp/ptp_idt82p33.c:212:\ndrivers/ptp/ptp_idt82p33.c:213:static int arm_tod_read_with_trigger(struct idt82p33_channel *channel, u8 trigger)\ndrivers/ptp/ptp_idt82p33.c:214:{\ndrivers/ptp/ptp_idt82p33.c:215:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:216:\tu8 buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:217:\tint err;\ndrivers/ptp/ptp_idt82p33.c:218:\ndrivers/ptp/ptp_idt82p33.c:219:\t/* Remember the current tod_sts before setting the trigger */\ndrivers/ptp/ptp_idt82p33.c:220:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c:221:\ndrivers/ptp/ptp_idt82p33.c:222:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:223:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:224:\ndrivers/ptp/ptp_idt82p33.c:225:\tmemcpy(channel-\u003eextts_tod_sts, buf, TOD_BYTE_COUNT);\ndrivers/ptp/ptp_idt82p33.c:226:\ndrivers/ptp/ptp_idt82p33.c:227:\terr = idt82p33_set_tod_trigger(channel, trigger, false);\ndrivers/ptp/ptp_idt82p33.c:228:\ndrivers/ptp/ptp_idt82p33.c:229:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:230:\t\tdev_err(idt82p33-\u003edev, \"%s: err = %d\", __func__, err);\ndrivers/ptp/ptp_idt82p33.c:231:\ndrivers/ptp/ptp_idt82p33.c:232:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:233:}\ndrivers/ptp/ptp_idt82p33.c:234:\ndrivers/ptp/ptp_idt82p33.c:235:static int idt82p33_extts_enable(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:236:\t\t\t\t struct ptp_clock_request *rq, int on)\ndrivers/ptp/ptp_idt82p33.c:237:{\ndrivers/ptp/ptp_idt82p33.c:238:\tu8 index = rq-\u003eextts.index;\ndrivers/ptp/ptp_idt82p33.c:239:\tstruct idt82p33 *idt82p33;\ndrivers/ptp/ptp_idt82p33.c:240:\tu8 mask = 1 \u003c\u003c index;\ndrivers/ptp/ptp_idt82p33.c:241:\tint err = 0;\ndrivers/ptp/ptp_idt82p33.c:242:\tu8 old_mask;\ndrivers/ptp/ptp_idt82p33.c:243:\tu8 trigger;\ndrivers/ptp/ptp_idt82p33.c:244:\tint ref;\ndrivers/ptp/ptp_idt82p33.c:245:\ndrivers/ptp/ptp_idt82p33.c:246:\tidt82p33  = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:247:\told_mask = idt82p33-\u003eextts_mask;\ndrivers/ptp/ptp_idt82p33.c:248:\ndrivers/ptp/ptp_idt82p33.c:249:\tif (index \u003e= MAX_PHC_PLL)\ndrivers/ptp/ptp_idt82p33.c:250:\t\treturn -EINVAL;\ndrivers/ptp/ptp_idt82p33.c:251:\ndrivers/ptp/ptp_idt82p33.c:252:\tif (on) {\ndrivers/ptp/ptp_idt82p33.c:253:\t\t/* Return if it was already enabled */\ndrivers/ptp/ptp_idt82p33.c:254:\t\tif (idt82p33-\u003eextts_mask \u0026 mask)\ndrivers/ptp/ptp_idt82p33.c:255:\t\t\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:256:\ndrivers/ptp/ptp_idt82p33.c:257:\t\t/* Use the pin configured for the channel */\ndrivers/ptp/ptp_idt82p33.c:258:\t\tref = ptp_find_pin(channel-\u003eptp_clock, PTP_PF_EXTTS, channel-\u003eplln);\ndrivers/ptp/ptp_idt82p33.c:259:\ndrivers/ptp/ptp_idt82p33.c:260:\t\tif (ref \u003c 0) {\ndrivers/ptp/ptp_idt82p33.c:261:\t\t\tdev_err(idt82p33-\u003edev, \"%s: No valid pin found for Pll%d!\\n\",\ndrivers/ptp/ptp_idt82p33.c:262:\t\t\t\t__func__, channel-\u003eplln);\ndrivers/ptp/ptp_idt82p33.c:263:\t\t\treturn -EBUSY;\ndrivers/ptp/ptp_idt82p33.c:264:\t\t}\ndrivers/ptp/ptp_idt82p33.c:265:\ndrivers/ptp/ptp_idt82p33.c:266:\t\terr = map_ref_to_tod_trig_sel(ref, \u0026trigger);\ndrivers/ptp/ptp_idt82p33.c:267:\ndrivers/ptp/ptp_idt82p33.c:268:\t\tif (err) {\ndrivers/ptp/ptp_idt82p33.c:269:\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c:270:\t\t\t\t\"%s: Unsupported ref %d!\\n\", __func__, ref);\ndrivers/ptp/ptp_idt82p33.c:271:\t\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:272:\t\t}\ndrivers/ptp/ptp_idt82p33.c:273:\ndrivers/ptp/ptp_idt82p33.c:274:\t\terr = arm_tod_read_with_trigger(\u0026idt82p33-\u003echannel[index], trigger);\ndrivers/ptp/ptp_idt82p33.c:275:\ndrivers/ptp/ptp_idt82p33.c:276:\t\tif (err == 0) {\ndrivers/ptp/ptp_idt82p33.c:277:\t\t\tidt82p33-\u003eextts_mask |= mask;\ndrivers/ptp/ptp_idt82p33.c:278:\t\t\tidt82p33-\u003echannel[index].tod_trigger = trigger;\ndrivers/ptp/ptp_idt82p33.c:279:\t\t\tidt82p33-\u003eevent_channel[index] = channel;\ndrivers/ptp/ptp_idt82p33.c:280:\t\t\tidt82p33-\u003eextts_single_shot = is_one_shot(idt82p33-\u003eextts_mask);\ndrivers/ptp/ptp_idt82p33.c:281:\ndrivers/ptp/ptp_idt82p33.c:282:\t\t\tif (old_mask)\ndrivers/ptp/ptp_idt82p33.c:283:\t\t\t\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:284:\ndrivers/ptp/ptp_idt82p33.c:285:\t\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\ndrivers/ptp/ptp_idt82p33.c:286:\t\t\t\t\t      msecs_to_jiffies(EXTTS_PERIOD_MS));\ndrivers/ptp/ptp_idt82p33.c:287:\t\t}\ndrivers/ptp/ptp_idt82p33.c:288:\t} else {\ndrivers/ptp/ptp_idt82p33.c:289:\t\tidt82p33-\u003eextts_mask \u0026= ~mask;\ndrivers/ptp/ptp_idt82p33.c:290:\t\tidt82p33-\u003eextts_single_shot = is_one_shot(idt82p33-\u003eextts_mask);\ndrivers/ptp/ptp_idt82p33.c:291:\ndrivers/ptp/ptp_idt82p33.c:292:\t\tif (idt82p33-\u003eextts_mask == 0)\ndrivers/ptp/ptp_idt82p33.c:293:\t\t\tcancel_delayed_work(\u0026idt82p33-\u003eextts_work);\ndrivers/ptp/ptp_idt82p33.c:294:\t}\ndrivers/ptp/ptp_idt82p33.c:295:\ndrivers/ptp/ptp_idt82p33.c:296:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:297:}\ndrivers/ptp/ptp_idt82p33.c:298:\ndrivers/ptp/ptp_idt82p33.c:299:static int idt82p33_extts_check_channel(struct idt82p33 *idt82p33, u8 todn)\ndrivers/ptp/ptp_idt82p33.c:300:{\ndrivers/ptp/ptp_idt82p33.c:301:\tstruct idt82p33_channel *event_channel;\ndrivers/ptp/ptp_idt82p33.c:302:\tstruct ptp_clock_event event;\ndrivers/ptp/ptp_idt82p33.c:303:\tstruct timespec64 ts;\ndrivers/ptp/ptp_idt82p33.c:304:\tint err;\ndrivers/ptp/ptp_idt82p33.c:305:\ndrivers/ptp/ptp_idt82p33.c:306:\terr = idt82p33_get_extts(\u0026idt82p33-\u003echannel[todn], \u0026ts);\ndrivers/ptp/ptp_idt82p33.c:307:\tif (err == 0) {\ndrivers/ptp/ptp_idt82p33.c:308:\t\tevent_channel = idt82p33-\u003eevent_channel[todn];\ndrivers/ptp/ptp_idt82p33.c:309:\t\tevent.type = PTP_CLOCK_EXTTS;\ndrivers/ptp/ptp_idt82p33.c:310:\t\tevent.index = todn;\ndrivers/ptp/ptp_idt82p33.c:311:\t\tevent.timestamp = timespec64_to_ns(\u0026ts);\ndrivers/ptp/ptp_idt82p33.c:312:\t\tptp_clock_event(event_channel-\u003eptp_clock,\ndrivers/ptp/ptp_idt82p33.c:313:\t\t\t\t\u0026event);\ndrivers/ptp/ptp_idt82p33.c:314:\t}\ndrivers/ptp/ptp_idt82p33.c:315:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:316:}\ndrivers/ptp/ptp_idt82p33.c:317:\ndrivers/ptp/ptp_idt82p33.c:318:static u8 idt82p33_extts_enable_mask(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:319:\t\t\t\t     u8 extts_mask, bool enable)\ndrivers/ptp/ptp_idt82p33.c:320:{\ndrivers/ptp/ptp_idt82p33.c:321:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:322:\tu8 trigger = channel-\u003etod_trigger;\ndrivers/ptp/ptp_idt82p33.c:323:\tu8 mask;\ndrivers/ptp/ptp_idt82p33.c:324:\tint err;\ndrivers/ptp/ptp_idt82p33.c:325:\tint i;\ndrivers/ptp/ptp_idt82p33.c:326:\ndrivers/ptp/ptp_idt82p33.c:327:\tif (extts_mask == 0)\ndrivers/ptp/ptp_idt82p33.c:328:\t\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:329:\ndrivers/ptp/ptp_idt82p33.c:330:\tif (enable == false)\ndrivers/ptp/ptp_idt82p33.c:331:\t\tcancel_delayed_work_sync(\u0026idt82p33-\u003eextts_work);\ndrivers/ptp/ptp_idt82p33.c:332:\ndrivers/ptp/ptp_idt82p33.c:333:\tfor (i = 0; i \u003c MAX_PHC_PLL; i++) {\ndrivers/ptp/ptp_idt82p33.c:334:\t\tmask = 1 \u003c\u003c i;\ndrivers/ptp/ptp_idt82p33.c:335:\ndrivers/ptp/ptp_idt82p33.c:336:\t\tif ((extts_mask \u0026 mask) == 0)\ndrivers/ptp/ptp_idt82p33.c:337:\t\t\tcontinue;\ndrivers/ptp/ptp_idt82p33.c:338:\ndrivers/ptp/ptp_idt82p33.c:339:\t\tif (enable) {\ndrivers/ptp/ptp_idt82p33.c:340:\t\t\terr = arm_tod_read_with_trigger(\u0026idt82p33-\u003echannel[i], trigger);\ndrivers/ptp/ptp_idt82p33.c:341:\t\t\tif (err)\ndrivers/ptp/ptp_idt82p33.c:342:\t\t\t\tdev_err(idt82p33-\u003edev,\ndrivers/ptp/ptp_idt82p33.c:343:\t\t\t\t\t\"%s: Arm ToD read trigger failed, err = %d\",\ndrivers/ptp/ptp_idt82p33.c:344:\t\t\t\t\t__func__, err);\ndrivers/ptp/ptp_idt82p33.c:345:\t\t} else {\ndrivers/ptp/ptp_idt82p33.c:346:\t\t\terr = idt82p33_extts_check_channel(idt82p33, i);\ndrivers/ptp/ptp_idt82p33.c:347:\t\t\tif (err == 0 \u0026\u0026 idt82p33-\u003eextts_single_shot)\ndrivers/ptp/ptp_idt82p33.c:348:\t\t\t\t/* trigger happened so we won't re-enable it */\ndrivers/ptp/ptp_idt82p33.c:349:\t\t\t\textts_mask \u0026= ~mask;\ndrivers/ptp/ptp_idt82p33.c:350:\t\t}\ndrivers/ptp/ptp_idt82p33.c:351:\t}\ndrivers/ptp/ptp_idt82p33.c:352:\ndrivers/ptp/ptp_idt82p33.c:353:\tif (enable)\ndrivers/ptp/ptp_idt82p33.c:354:\t\tschedule_delayed_work(\u0026idt82p33-\u003eextts_work,\ndrivers/ptp/ptp_idt82p33.c:355:\t\t\t\t      msecs_to_jiffies(EXTTS_PERIOD_MS));\ndrivers/ptp/ptp_idt82p33.c:356:\ndrivers/ptp/ptp_idt82p33.c:357:\treturn extts_mask;\ndrivers/ptp/ptp_idt82p33.c:358:}\ndrivers/ptp/ptp_idt82p33.c:359:\ndrivers/ptp/ptp_idt82p33.c:360:static int _idt82p33_gettime(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:361:\t\t\t     struct timespec64 *ts)\ndrivers/ptp/ptp_idt82p33.c:362:{\ndrivers/ptp/ptp_idt82p33.c:363:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:364:\tu8 old_mask = idt82p33-\u003eextts_mask;\ndrivers/ptp/ptp_idt82p33.c:365:\tu8 buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:366:\tu8 new_mask = 0;\ndrivers/ptp/ptp_idt82p33.c:367:\tint err;\ndrivers/ptp/ptp_idt82p33.c:368:\ndrivers/ptp/ptp_idt82p33.c:369:\t/* Disable extts */\ndrivers/ptp/ptp_idt82p33.c:370:\tif (old_mask)\ndrivers/ptp/ptp_idt82p33.c:371:\t\tnew_mask = idt82p33_extts_enable_mask(channel, old_mask, false);\ndrivers/ptp/ptp_idt82p33.c:372:\ndrivers/ptp/ptp_idt82p33.c:373:\terr = idt82p33_set_tod_trigger(channel, HW_TOD_RD_TRIG_SEL_LSB_TOD_STS,\ndrivers/ptp/ptp_idt82p33.c:374:\t\t\t\t       false);\ndrivers/ptp/ptp_idt82p33.c:375:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:376:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:377:\ndrivers/ptp/ptp_idt82p33.c:378:\tchannel-\u003ediscard_next_extts = true;\ndrivers/ptp/ptp_idt82p33.c:379:\ndrivers/ptp/ptp_idt82p33.c:380:\tif (idt82p33-\u003ecalculate_overhead_flag)\ndrivers/ptp/ptp_idt82p33.c:381:\t\tidt82p33-\u003estart_time = ktime_get_raw();\ndrivers/ptp/ptp_idt82p33.c:382:\ndrivers/ptp/ptp_idt82p33.c:383:\terr = idt82p33_read(idt82p33, channel-\u003edpll_tod_sts, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c:384:\ndrivers/ptp/ptp_idt82p33.c:385:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:386:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:387:\ndrivers/ptp/ptp_idt82p33.c:388:\t/* Re-enable extts */\ndrivers/ptp/ptp_idt82p33.c:389:\tif (new_mask)\ndrivers/ptp/ptp_idt82p33.c:390:\t\tidt82p33_extts_enable_mask(channel, new_mask, true);\ndrivers/ptp/ptp_idt82p33.c:391:\ndrivers/ptp/ptp_idt82p33.c:392:\tidt82p33_byte_array_to_timespec(ts, buf);\ndrivers/ptp/ptp_idt82p33.c:393:\ndrivers/ptp/ptp_idt82p33.c:394:\treturn 0;\ndrivers/ptp/ptp_idt82p33.c:395:}\ndrivers/ptp/ptp_idt82p33.c:396:\ndrivers/ptp/ptp_idt82p33.c:397:/*\ndrivers/ptp/ptp_idt82p33.c:398: *   TOD Trigger:\ndrivers/ptp/ptp_idt82p33.c:399: *   Bits[7:4] Write 0x9, MSB write\ndrivers/ptp/ptp_idt82p33.c:400: *   Bits[3:0] Read 0x9, LSB read\ndrivers/ptp/ptp_idt82p33.c:401: */\ndrivers/ptp/ptp_idt82p33.c:402:\ndrivers/ptp/ptp_idt82p33.c:403:static int _idt82p33_settime(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:404:\t\t\t     struct timespec64 const *ts)\ndrivers/ptp/ptp_idt82p33.c:405:{\ndrivers/ptp/ptp_idt82p33.c:406:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:407:\tstruct timespec64 local_ts = *ts;\ndrivers/ptp/ptp_idt82p33.c:408:\tchar buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:409:\ts64 dynamic_overhead_ns;\ndrivers/ptp/ptp_idt82p33.c:410:\tint err;\ndrivers/ptp/ptp_idt82p33.c:411:\tu8 i;\ndrivers/ptp/ptp_idt82p33.c:412:\ndrivers/ptp/ptp_idt82p33.c:413:\terr = idt82p33_set_tod_trigger(channel, HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,\ndrivers/ptp/ptp_idt82p33.c:414:\t\t\t\t       true);\ndrivers/ptp/ptp_idt82p33.c:415:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:416:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:417:\ndrivers/ptp/ptp_idt82p33.c:418:\tchannel-\u003ediscard_next_extts = true;\ndrivers/ptp/ptp_idt82p33.c:419:\ndrivers/ptp/ptp_idt82p33.c:420:\tif (idt82p33-\u003ecalculate_overhead_flag) {\ndrivers/ptp/ptp_idt82p33.c:421:\t\tdynamic_overhead_ns = ktime_to_ns(ktime_get_raw())\ndrivers/ptp/ptp_idt82p33.c:422:\t\t\t\t\t- ktime_to_ns(idt82p33-\u003estart_time);\ndrivers/ptp/ptp_idt82p33.c:423:\ndrivers/ptp/ptp_idt82p33.c:424:\t\ttimespec64_add_ns(\u0026local_ts, dynamic_overhead_ns);\ndrivers/ptp/ptp_idt82p33.c:425:\ndrivers/ptp/ptp_idt82p33.c:426:\t\tidt82p33-\u003ecalculate_overhead_flag = 0;\ndrivers/ptp/ptp_idt82p33.c:427:\t}\ndrivers/ptp/ptp_idt82p33.c:428:\ndrivers/ptp/ptp_idt82p33.c:429:\tidt82p33_timespec_to_byte_array(\u0026local_ts, buf);\ndrivers/ptp/ptp_idt82p33.c:430:\ndrivers/ptp/ptp_idt82p33.c:431:\t/*\ndrivers/ptp/ptp_idt82p33.c:432:\t * Store the new time value.\ndrivers/ptp/ptp_idt82p33.c:433:\t */\ndrivers/ptp/ptp_idt82p33.c:434:\tfor (i = 0; i \u003c TOD_BYTE_COUNT; i++) {\ndrivers/ptp/ptp_idt82p33.c:435:\t\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_cnfg + i,\ndrivers/ptp/ptp_idt82p33.c:436:\t\t\t\t     \u0026buf[i], sizeof(buf[i]));\ndrivers/ptp/ptp_idt82p33.c:437:\t\tif (err)\ndrivers/ptp/ptp_idt82p33.c:438:\t\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:439:\t}\ndrivers/ptp/ptp_idt82p33.c:440:\ndrivers/ptp/ptp_idt82p33.c:441:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:442:}\ndrivers/ptp/ptp_idt82p33.c:443:\ndrivers/ptp/ptp_idt82p33.c:444:static int _idt82p33_adjtime_immediate(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:445:\t\t\t\t       s64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c:446:{\ndrivers/ptp/ptp_idt82p33.c:447:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:448:\tstruct timespec64 ts;\ndrivers/ptp/ptp_idt82p33.c:449:\ts64 now_ns;\ndrivers/ptp/ptp_idt82p33.c:450:\tint err;\ndrivers/ptp/ptp_idt82p33.c:451:\ndrivers/ptp/ptp_idt82p33.c:452:\tidt82p33-\u003ecalculate_overhead_flag = 1;\ndrivers/ptp/ptp_idt82p33.c:453:\ndrivers/ptp/ptp_idt82p33.c:454:\terr = _idt82p33_gettime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c:455:\ndrivers/ptp/ptp_idt82p33.c:456:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:457:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:458:\ndrivers/ptp/ptp_idt82p33.c:459:\tnow_ns = timespec64_to_ns(\u0026ts);\ndrivers/ptp/ptp_idt82p33.c:460:\tnow_ns += delta_ns + idt82p33-\u003etod_write_overhead_ns;\ndrivers/ptp/ptp_idt82p33.c:461:\ndrivers/ptp/ptp_idt82p33.c:462:\tts = ns_to_timespec64(now_ns);\ndrivers/ptp/ptp_idt82p33.c:463:\ndrivers/ptp/ptp_idt82p33.c:464:\terr = _idt82p33_settime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c:465:\ndrivers/ptp/ptp_idt82p33.c:466:\treturn err;\ndrivers/ptp/ptp_idt82p33.c:467:}\ndrivers/ptp/ptp_idt82p33.c:468:\ndrivers/ptp/ptp_idt82p33.c:469:static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c:470:\t\t\t\t\t\ts64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c:471:{\ndrivers/ptp/ptp_idt82p33.c:472:\tstruct idt82p33 *idt82p33 = channel-\u003eidt82p33;\ndrivers/ptp/ptp_idt82p33.c:473:\tchar buf[TOD_BYTE_COUNT];\ndrivers/ptp/ptp_idt82p33.c:474:\tstruct timespec64 ts;\ndrivers/ptp/ptp_idt82p33.c:475:\tconst u8 delay_ns = 32;\ndrivers/ptp/ptp_idt82p33.c:476:\ts32 remainder;\ndrivers/ptp/ptp_idt82p33.c:477:\ts64 ns;\ndrivers/ptp/ptp_idt82p33.c:478:\tint err;\ndrivers/ptp/ptp_idt82p33.c:479:\ndrivers/ptp/ptp_idt82p33.c:480:\terr = _idt82p33_gettime(channel, \u0026ts);\ndrivers/ptp/ptp_idt82p33.c:481:\ndrivers/ptp/ptp_idt82p33.c:482:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:483:\t\treturn err;\ndrivers/ptp/ptp_idt82p33.c:484:\ndrivers/ptp/ptp_idt82p33.c:485:\tif (ts.tv_nsec \u003e (NSEC_PER_SEC - 5 * NSEC_PER_MSEC)) {\ndrivers/ptp/ptp_idt82p33.c:486:\t\t/*  Too close to miss next trigger, so skip it */\ndrivers/ptp/ptp_idt82p33.c:487:\t\tmdelay(6);\ndrivers/ptp/ptp_idt82p33.c:488:\t\tns = (ts.tv_sec + 2) * NSEC_PER_SEC + delta_ns + delay_ns;\ndrivers/ptp/ptp_idt82p33.c:489:\t} else\ndrivers/ptp/ptp_idt82p33.c:490:\t\tns = (ts.tv_sec + 1) * NSEC_PER_SEC + delta_ns + delay_ns;\ndrivers/ptp/ptp_idt82p33.c:491:\ndrivers/ptp/ptp_idt82p33.c:492:\tts = ns_to_timespec64(ns);\ndrivers/ptp/ptp_idt82p33.c:493:\tidt82p33_timespec_to_byte_array(\u0026ts, buf);\ndrivers/ptp/ptp_idt82p33.c:494:\ndrivers/ptp/ptp_idt82p33.c:495:\t/*\ndrivers/ptp/ptp_idt82p33.c:496:\t * Store the new time value.\ndrivers/ptp/ptp_idt82p33.c:497:\t */\ndrivers/ptp/ptp_idt82p33.c:498:\terr = idt82p33_write(idt82p33, channel-\u003edpll_tod_cnfg, buf, sizeof(buf));\ndrivers/ptp/ptp_idt82p33.c:499:\tif (err)\ndrivers/ptp/ptp_idt82p33.c:500:\t\treturn err;\n\n"
}

							input: 53541
							output: 32
							thoughts: 302

**Analyzing the IDT 82p33 PTP Driver**

Okay, let's dive into this `drivers/ptp/ptp_idt82p33.c` file. It looks like we're dealing with the PTP hardware clock driver for the IDT 82p33xxx family. My initial scan points to functions like `idt82p33_ptp_clock_unregister_all`, `idt82p33_enable`, `idt82p33_adjtime`, `idt82p33_extts_check`, and `idt82p33_remove`, which are all standard for a driver of this type. But, I need to understand the probing sequence for this device... that's where the real magic happens, right?

Alright, let me examine the initialization process. Ah, found it! Lines 1419-1427 are key. We have a "cold reset" before loading the firmware, followed by a firmware load via `idt82p33_load_firmware`. It looks like it handles some error checking here. Interesting. Then there's a "soft reset" after the firmware is loaded. This sequence is pretty standard for these devices, but I need to understand what those resets actually do.

Okay, let's look at `idt82p33_reset` and `idt82p33_enable_channel` to understand those operations. That's the key to understanding how this driver interacts with the hardware.

{
  "Expression": "idt82p33_reset",
  "PathPrefix": "drivers/ptp"
}

{
  "Output": "drivers/ptp/ptp_idt82p33.c=1207=static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)\n--\ndrivers/ptp/ptp_idt82p33.c-1260-\ndrivers/ptp/ptp_idt82p33.c:1261:static int idt82p33_reset(struct idt82p33 *idt82p33, bool cold)\ndrivers/ptp/ptp_idt82p33.c-1262-{\n--\ndrivers/ptp/ptp_idt82p33.c=1392=static int idt82p33_probe(struct platform_device *pdev)\n--\ndrivers/ptp/ptp_idt82p33.c-1418-\t/* cold reset before loading firmware */\ndrivers/ptp/ptp_idt82p33.c:1419:\tidt82p33_reset(idt82p33, true);\ndrivers/ptp/ptp_idt82p33.c-1420-\n--\ndrivers/ptp/ptp_idt82p33.c-1426-\t/* soft reset after loading firmware */\ndrivers/ptp/ptp_idt82p33.c:1427:\tidt82p33_reset(idt82p33, false);\ndrivers/ptp/ptp_idt82p33.c-1428-\n"
}

							input: 54622
							output: 45
							thoughts: 40

Here's my summary, as if I were thinking these thoughts:

**Analyzing IDT82P33 Reset and Channel Enable Routines**

Okay, let's dive into this code. I need to get a clear picture of how this IDT82P33 chip is being managed. Specifically, I'm going to focus on the `idt82p33_reset` and `idt82p33_enable_channel` functions, and I'm guessing the relevant interactions are somewhere between lines 1207 and 1300. That range is a good place to start, given the usual organization of these kinds of drivers. I'm looking for the sequence of operations. This reset call is critical. It sets the baseline state, initializes the registers, gets the device in a known, safe starting state. Then, I need to understand how the channel is subsequently enabled; what's involved in that process? What resources are allocated or configured during the enable, and what's the general sequence? That's likely where the core interactions happen. Time to get to work.

{
  "File": "drivers/ptp/ptp_idt82p33.c",
  "FirstLine": 1205,
  "LineCount": 80
}

{
  "Contents": "1205:\t}\n1206:\t\n1207:\tstatic int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)\n1208:\t{\n1209:\t\tstruct idt82p33_channel *channel;\n1210:\t\tint err;\n1211:\t\n1212:\t\tif (!(index \u003c MAX_PHC_PLL))\n1213:\t\t\treturn -EINVAL;\n1214:\t\n1215:\t\tchannel = \u0026idt82p33-\u003echannel[index];\n1216:\t\n1217:\t\terr = idt82p33_channel_init(idt82p33, index);\n1218:\t\tif (err) {\n1219:\t\t\tdev_err(idt82p33-\u003edev,\n1220:\t\t\t\t\"Channel_init failed in %s with err %d!\\n\",\n1221:\t\t\t\t__func__, err);\n1222:\t\t\treturn err;\n1223:\t\t}\n1224:\t\n1225:\t\tidt82p33_caps_init(index, \u0026channel-\u003ecaps,\n1226:\t\t\t\t   pin_config[index], MAX_TRIG_CLK);\n1227:\t\n1228:\t\tchannel-\u003eptp_clock = ptp_clock_register(\u0026channel-\u003ecaps, NULL);\n1229:\t\n1230:\t\tif (IS_ERR(channel-\u003eptp_clock)) {\n1231:\t\t\terr = PTR_ERR(channel-\u003eptp_clock);\n1232:\t\t\tchannel-\u003eptp_clock = NULL;\n1233:\t\t\treturn err;\n1234:\t\t}\n1235:\t\n1236:\t\tif (!channel-\u003eptp_clock)\n1237:\t\t\treturn -ENOTSUPP;\n1238:\t\n1239:\t\terr = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);\n1240:\t\tif (err) {\n1241:\t\t\tdev_err(idt82p33-\u003edev,\n1242:\t\t\t\t\"Dpll_set_mode failed in %s with err %d!\\n\",\n1243:\t\t\t\t__func__, err);\n1244:\t\t\treturn err;\n1245:\t\t}\n1246:\t\n1247:\t\terr = idt82p33_enable_tod(channel);\n1248:\t\tif (err) {\n1249:\t\t\tdev_err(idt82p33-\u003edev,\n1250:\t\t\t\t\"Enable_tod failed in %s with err %d!\\n\",\n1251:\t\t\t\t__func__, err);\n1252:\t\t\treturn err;\n1253:\t\t}\n1254:\t\n1255:\t\tdev_info(idt82p33-\u003edev, \"PLL%d registered as ptp%d\\n\",\n1256:\t\t\t index, channel-\u003eptp_clock-\u003eindex);\n1257:\t\n1258:\t\treturn 0;\n1259:\t}\n1260:\t\n1261:\tstatic int idt82p33_reset(struct idt82p33 *idt82p33, bool cold)\n1262:\t{\n1263:\t\tint err;\n1264:\t\tu8 cfg = SOFT_RESET_EN;\n1265:\t\n1266:\t\tif (cold == true)\n1267:\t\t\tgoto cold_reset;\n1268:\t\n1269:\t\terr = idt82p33_read(idt82p33, REG_SOFT_RESET, \u0026cfg, sizeof(cfg));\n1270:\t\tif (err) {\n1271:\t\t\tdev_err(idt82p33-\u003edev,\n1272:\t\t\t\t\"Soft reset failed with err %d!\\n\", err);\n1273:\t\t\treturn err;\n1274:\t\t}\n1275:\t\n1276:\t\tcfg |= SOFT_RESET_EN;\n1277:\t\n1278:\tcold_reset:\n1279:\t\terr = idt82p33_write(idt82p33, REG_SOFT_RESET, \u0026cfg, sizeof(cfg));\n1280:\t\tif (err)\n1281:\t\t\tdev_err(idt82p33-\u003edev,\n1282:\t\t\t\t\"Cold reset failed with err %d!\\n\", err);\n1283:\t\treturn err;\n1284:\t}\n"
}

							input: 56144
							output: 42
							thoughts: 2747

**Analysis of IDT 82P33 Driver Reachability in Fuzzing Environments**

Okay, so I'm looking at this `ptp_idt82p33` driver and wondering if it's even remotely fuzzable in a standard QEMU environment. The device instantiation is key: it's named `"82p33x1x-phc"` and is solely registered through `rsmu_sabre_devs` within `rsmu_core_init`, which in turn, is called by `rsmu_i2c_probe` (specifically when probing an I2C device "82p33810" or "82p33811") or `rsmu_spi_probe`. The `idt82p33_driver` then matches this platform device and calls `idt82p33_probe`.

During the `idt82p33_probe` routine it initializes regmap and goes through reset, firmware loading, and enabling channels which leads to the registration of `/dev/ptpX` via `ptp_clock_register`. This makes me think it's possible to interact with it through user space, but then I have to ask - is this hardware reachable?

Can `rsmu_i2c` or `rsmu_spi` or these specific I2C devices be probed without physical hardware? QEMU doesn't emulate the IDT 82p33810 chip, so that's a no. Could I create an I2C client via sysfs? Maybe. The relevant code in `rsmu_i2c_probe` is `devm_regmap_init_i2c` which in itself doesn't cause any I/O and then `rsmu_core_init` creates the child. This then leads to calling `idt82p33_probe`.

However, the `idt82p33_reset` function, which is called during `idt82p33_probe`, uses `regmap_bulk_write` which would try to write to the I2C device. But does QEMU even have an emulated I2C bus? If it writes to a non-existent device (NAK), then the `idt82p33_reset` function will return an error. So, how about syzkaller? Does it instantiate I2C devices? My instinct is no, because that generally depends on specific hardware. I think it's more general and would require hardware drivers to be reachable.

Let's carefully consider the patch fuzzing guidelines. Reachability is the *primary* gate. The code needs to be executable in standard virtualized environments. The instructions explicitly say *not* to fuzz structurally unreachable hardware, like vendor-specific devices that require physical cards (ASICs). And looking at Section 2 under "Structurally unreachable hardware", it specifically mentions that these drivers can be unreachable.

Furthermore, reading "Reachable Drivers and Protocols" makes it seem drivers accessible via virtual buses are the focus.

This `ptp_idt82p33` driver is for a physical timing hardware chip from Renesas (IDT 82P33xxx). It requires the actual chip connected over I2C or SPI (via the Renesas RSMU MFD driver). QEMU doesn't emulate this. My conclusion is that it's structurally unreachable. The modified code includes `idt82p33_ptp_clock_unregister_all`, `idt82p33_enable`, `idt82p33_adjtime`, and `idt82p33_extts_check`. But the first one is used in `idt82p33_remove`, which is a driver teardown callback, only executed during hot-unplug or manual sysfs unbinding (which is also unreachable).

The other functions that were modified, `idt82p33_enable` and `idt82p33_adjtime` etc., are hooked up in `struct ptp_clock_info caps`. However, given that the driver itself is dependent on the existence of the physical chip, it is not possible to reach it in a standard fuzzing environment. Therefore, the patch does not need to be fuzzed.

{
  "Expression": "idt82p33_enable|idt82p33_adjtime",
  "PathPrefix": "drivers/ptp"
}

{
  "Output": "drivers/ptp/ptp_idt82p33.c=403=static int _idt82p33_settime(struct idt82p33_channel *channel,\n--\ndrivers/ptp/ptp_idt82p33.c-443-\ndrivers/ptp/ptp_idt82p33.c:444:static int _idt82p33_adjtime_immediate(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-445-\t\t\t\t       s64 delta_ns)\n--\ndrivers/ptp/ptp_idt82p33.c-468-\ndrivers/ptp/ptp_idt82p33.c:469:static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel *channel,\ndrivers/ptp/ptp_idt82p33.c-470-\t\t\t\t\t\ts64 delta_ns)\n--\ndrivers/ptp/ptp_idt82p33.c-509-\ndrivers/ptp/ptp_idt82p33.c:510:static void idt82p33_adjtime_workaround(struct work_struct *work)\ndrivers/ptp/ptp_idt82p33.c-511-{\n--\ndrivers/ptp/ptp_idt82p33.c-518-\t/* Workaround for TOD-to-output alignment issue */\ndrivers/ptp/ptp_idt82p33.c:519:\t_idt82p33_adjtime_internal_triggered(channel, 0);\ndrivers/ptp/ptp_idt82p33.c-520-\tmutex_unlock(idt82p33-\u003elock);\n--\ndrivers/ptp/ptp_idt82p33.c=886=static int idt82p33_perout_enable(struct idt82p33_channel *channel,\n--\ndrivers/ptp/ptp_idt82p33.c-893-\ndrivers/ptp/ptp_idt82p33.c:894:static int idt82p33_enable_tod(struct idt82p33_channel *channel)\ndrivers/ptp/ptp_idt82p33.c-895-{\n--\ndrivers/ptp/ptp_idt82p33.c=916=static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)\n--\ndrivers/ptp/ptp_idt82p33.c-937-\ndrivers/ptp/ptp_idt82p33.c:938:static int idt82p33_enable(struct ptp_clock_info *ptp,\ndrivers/ptp/ptp_idt82p33.c-939-\t\t\t   struct ptp_clock_request *rq, int on)\n--\ndrivers/ptp/ptp_idt82p33.c=1022=static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)\n--\ndrivers/ptp/ptp_idt82p33.c-1047-\ndrivers/ptp/ptp_idt82p33.c:1048:static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)\ndrivers/ptp/ptp_idt82p33.c-1049-{\n--\ndrivers/ptp/ptp_idt82p33.c-1069-\t/* Use more accurate internal 1pps triggered write first */\ndrivers/ptp/ptp_idt82p33.c:1070:\terr = _idt82p33_adjtime_internal_triggered(channel, delta_ns);\ndrivers/ptp/ptp_idt82p33.c-1071-\tif (err \u0026\u0026 delta_ns \u003e IMMEDIATE_SNAP_THRESHOLD_NS)\ndrivers/ptp/ptp_idt82p33.c:1072:\t\terr = _idt82p33_adjtime_immediate(channel, delta_ns);\ndrivers/ptp/ptp_idt82p33.c-1073-\n--\ndrivers/ptp/ptp_idt82p33.c=1118=static int idt82p33_channel_init(struct idt82p33 *idt82p33, u32 index)\n--\ndrivers/ptp/ptp_idt82p33.c-1149-\tchannel-\u003eidt82p33 = idt82p33;\ndrivers/ptp/ptp_idt82p33.c:1150:\tINIT_DELAYED_WORK(\u0026channel-\u003eadjtime_work, idt82p33_adjtime_workaround);\ndrivers/ptp/ptp_idt82p33.c-1151-\n--\ndrivers/ptp/ptp_idt82p33.c=1169=static void idt82p33_caps_init(u32 index, struct ptp_clock_info *caps,\n--\ndrivers/ptp/ptp_idt82p33.c-1182-\tcaps-\u003eadjfine = idt82p33_adjfine;\ndrivers/ptp/ptp_idt82p33.c:1183:\tcaps-\u003eadjtime = idt82p33_adjtime;\ndrivers/ptp/ptp_idt82p33.c-1184-\tcaps-\u003egettime64 = idt82p33_gettime;\ndrivers/ptp/ptp_idt82p33.c-1185-\tcaps-\u003esettime64 = idt82p33_settime;\ndrivers/ptp/ptp_idt82p33.c:1186:\tcaps-\u003eenable = idt82p33_enable;\ndrivers/ptp/ptp_idt82p33.c-1187-\tcaps-\u003everify = idt82p33_verify_pin;\n--\ndrivers/ptp/ptp_idt82p33.c-1206-\ndrivers/ptp/ptp_idt82p33.c:1207:static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)\ndrivers/ptp/ptp_idt82p33.c-1208-{\n--\ndrivers/ptp/ptp_idt82p33.c-1246-\ndrivers/ptp/ptp_idt82p33.c:1247:\terr = idt82p33_enable_tod(channel);\ndrivers/ptp/ptp_idt82p33.c-1248-\tif (err) {\n--\ndrivers/ptp/ptp_idt82p33.c=1392=static int idt82p33_probe(struct platform_device *pdev)\n--\ndrivers/ptp/ptp_idt82p33.c-1431-\t\t\tif (idt82p33-\u003epll_mask \u0026 (1 \u003c\u003c i))\ndrivers/ptp/ptp_idt82p33.c:1432:\t\t\t\terr = idt82p33_enable_channel(idt82p33, i);\ndrivers/ptp/ptp_idt82p33.c-1433-\t\t\telse\n"
}

							input: 61838
							output: 22
							thoughts: 1370

**Analyzing the `idt82p33` Driver's Reachability for Fuzzing**

Okay, let's break this down. My initial thought is to examine the `idt82p33` driver, specifically focusing on a patch that introduces a `stopping` flag within `idt82p33_ptp_clock_unregister_all`. This flag seems to be added to prevent races during device unregistration, particularly between `ptp_clock_unregister` and related work queues. The patch's primary function is to synchronize the unregistration of the PTP clock.

The key observation here is the movement of `cancel_delayed_work_sync(&idt82p33->extts_work);` into `idt82p33_ptp_clock_unregister_all` in `idt82p33_remove`. It indicates that the system needs to prevent further execution of `idt82p33_enable`, `idt82p33_adjtime`, or `idt82p33_extts_check` after unregistration, which means there may be a race condition that could have existed previously. This confirms the patch's purpose: preventing issues during driver removal.

Now, the critical question: Is this driver code reachable in a standard fuzzing environment, according to the "REACHABILITY" guidelines? The question becomes, can we emulate the hardware this driver interfaces with within a standard QEMU setup, or will it require some complex hardware setup?

The analysis guidelines give the criteria for being worth fuzzing. I need to make a judgment based on this:
*   "Structurally unreachable hardware": Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
*   "Unreachable execution paths": Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during physical PCI hot-unplug or manual sysfs driver unbinding.

I need to confirm if the driver's target hardware can be created in QEMU. To do that, I'll go through the driver and check where the "82p33x1x-phc" is instantiated, as that is the type this driver is responsible for. I did a `grepper` previously, and that resulted in one entry for "82p33x1x-phc":
`drivers/mfd/rsmu_core.c:36`: `static struct mfd_cell rsmu_sabre_devs[] = { [RSMU_PHC] = { .name = "82p33x1x-phc", }, };`

Now I need to discover how `rsmu_sabre_devs` is used:
Only in `drivers/mfd/rsmu_core.c:62`:
```c
int rsmu_core_init(struct rsmu_ddata *rsmu)
{
	struct mfd_cell *cells;
	int ret;

	switch (rsmu->type) {
	case RSMU_CM:
		cells = rsmu_cm_devs;
		break;
	case RSMU_SABRE:
		cells = rsmu_sabre_devs;
		break;
	case RSMU_SL:
		cells = rsmu_sl_devs;
		break;
	default:
		dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
		return -ENODEV;
	}

	mutex_init(&rsmu->lock);

	ret = devm_mfd_add_devices(rsmu->dev, PLATFORM_DEVID_AUTO, cells,
				   RSMU_N_DEVS, NULL, 0, NULL);
...
```

I see that `rsmu_core_init` can instantiate the PTP, based on the RSMU type.

Now I need to find where `rsmu_core_init` is called.
I see it is only called in `drivers/mfd/rsmu_i2c.c` (`rsmu_i2c_probe`) and `drivers/mfd/rsmu_spi.c` (`rsmu_spi_probe`).

Now, where are `rsmu_i2c` and `rsmu_spi` instantiated?
Let's grep for `rsmu-i2c` and `rsmu-spi` or `82p33810`.

I

{
  "Expression": "82p33810"
}

{
  "Output": "Documentation/devicetree/bindings/ptp/ptp-idt82p33.yaml=15=properties:\n--\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml-17-    enum:\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml:18:      - idt,82p33810\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml-19-      - idt,82p33813\n--\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml=36=examples:\n--\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml-41-        phc@51 {\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml:42:            compatible = \"idt,82p33810\";\nDocumentation/devicetree/bindings/ptp/ptp-idt82p33.yaml-43-            reg = \u003c0x51\u003e;\n--\ndrivers/mfd/rsmu_i2c.c=330=static const struct i2c_device_id rsmu_i2c_id[] = {\n--\ndrivers/mfd/rsmu_i2c.c-333-\t{ \"8a34002\",  RSMU_CM },\ndrivers/mfd/rsmu_i2c.c:334:\t{ \"82p33810\", RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c-335-\t{ \"82p33811\", RSMU_SABRE },\n--\ndrivers/mfd/rsmu_i2c.c=342=static const struct of_device_id rsmu_i2c_of_match[] = {\n--\ndrivers/mfd/rsmu_i2c.c-345-\t{ .compatible = \"idt,8a34002\",  .data = (void *)RSMU_CM },\ndrivers/mfd/rsmu_i2c.c:346:\t{ .compatible = \"idt,82p33810\", .data = (void *)RSMU_SABRE },\ndrivers/mfd/rsmu_i2c.c-347-\t{ .compatible = \"idt,82p33811\", .data = (void *)RSMU_SABRE },\n--\ndrivers/mfd/rsmu_spi.c=241=static const struct spi_device_id rsmu_spi_id[] = {\n--\ndrivers/mfd/rsmu_spi.c-244-\t{ .name = \"8a34002\", .driver_data = RSMU_CM },\ndrivers/mfd/rsmu_spi.c:245:\t{ .name = \"82p33810\", .driver_data = RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c-246-\t{ .name = \"82p33811\", .driver_data = RSMU_SABRE },\n--\ndrivers/mfd/rsmu_spi.c=251=static const struct of_device_id rsmu_spi_of_match[] = {\n--\ndrivers/mfd/rsmu_spi.c-254-\t{ .compatible = \"idt,8a34002\",  .data = (void *)RSMU_CM },\ndrivers/mfd/rsmu_spi.c:255:\t{ .compatible = \"idt,82p33810\", .data = (void *)RSMU_SABRE },\ndrivers/mfd/rsmu_spi.c-256-\t{ .compatible = \"idt,82p33811\", .data = (void *)RSMU_SABRE },\n"
}

							input: 65252
							output: 133
							thoughts: 1002

**Analysis of `ptp_idt82p33` Driver for Fuzzing**

Okay, let's break this down. The `rsmu-i2c` and `rsmu-spi` drivers are the building blocks, matching OF/Device Tree or I2C/SPI board info. But on amd64, which is the target architecture, there are no DTS files describing the IDT 82P33810! And critically, neither QEMU nor GCE emulate the IDT 82P33810 or 82P33811 hardware. Even *if* we could somehow trick the system into creating an I2C client device via `sysfs new_device`, `idt82p33_probe` immediately attempts I2C transactions (`idt82p33_reset`) that will fail because the hardware simply isn't there at that I2C address. Probing fails instantly.

The patch's modifications within `ptp_idt82p33.c` are all within that driver: teardown, enabling, adjusting time, an ext trigger check, and removal logic, plus a `stopping` flag. These are *all* specific to the Renesas/IDT 82P33xxx hardware clock chip. No emulation exists.

Now, let's compare that against the Negative Criteria. We've got "Structurally unreachable hardware" here, *specifically* a vendor-specific driver requiring a physical ASIC/I2C/SPI connection. It's not emulated in the standard fuzzing environment, QEMU. It also falls under unreachable execution paths as the teardown callbacks are only executed on physical removal.

Wait a second, let me check for virtual PTP clocks... Ah, `ptp_mock.c` is in the `drivers/ptp/Makefile`. But this driver is completely separate from `ptp_idt82p33`! `ptp_idt82p33.c` is for the *specific* physical IDT hardware.

Can Syzkaller even touch `ptp_idt82p33`? No. Syzkaller on amd64, running in QEMU/GCE, *cannot* probe or instantiate this driver. It *requires* the IDT 82p33xxx hardware or an MFD device (from I2C/SPI, connected to an IDT 82P33810/82P33811). This is not emulated. Even during probe, there are I2C/SPI transactions. No physical hardware, no `/dev/ptp*` device will ever be registered.

Therefore, this patch modifies code that is inherently unreachable in standard virtualized environments. **WorthFuzzing is false.**

Let's verify the instructions.
- WorthFuzzing: False.
- FocusSymbols: Empty.
- EnableConfigs: Empty.
- Reasoning: Concise. The code is unreachable because it's a vendor-specific hardware driver for IDT/Renesas 82p33xxx synchronization management units that requires a physical ASIC over I2C/SPI, not emulated in QEMU/GCE. Teardown and other callbacks will not be executed.

Okay, let's invoke `set-results`.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies drivers/ptp/ptp_idt82p33.c, which is a device driver for Renesas/IDT 82P33xxx Synchronization Management Units (SMU) / PTP hardware clocks connected via I2C or SPI. This driver requires specific physical ASIC hardware that is not emulated in standard virtualized fuzzing environments (QEMU/GCE). The modified driver callbacks and teardown routines cannot be reached or executed during fuzzing.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies drivers/ptp/ptp_idt82p33.c, which is a device driver for Renesas/IDT 82P33xxx Synchronization Management Units (SMU) / PTP hardware clocks connected via I2C or SPI. This driver requires specific physical ASIC hardware that is not emulated in standard virtualized fuzzing environments (QEMU/GCE). The modified driver callbacks and teardown routines cannot be reached or executed during fuzzing.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

LLM Calls Summary:
Total Calls	Total Tokens	Avg Tokens	Total Duration (Seconds)	Avg Duration (Seconds)

Tool Calls Summary:
Total Calls	Total Duration (Seconds)	Avg Duration (Seconds)