| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/07/19 18:30 | flow | patch-triage |
0mArgs:null Results: {
"EnableConfigs": [
"NET_DSA_MT7530",
"NET_DSA_MT7530_MDIO"
],
"FocusSymbols": [
"mt753x_port_change_conduit",
"mt7530_port_fast_age"
],
"Reasoning": "The patch replaces custom register access functions with the regmap API, which changes locking and error handling behavior. It also adds new DSA switch operations `port_change_conduit` and `port_fast_age`.",
"WorthFuzzing": true
} |
| 1/1 | 2026/07/19 18:30 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit 7d2dc209a34612ab3ddf502404476b81e1f49f47\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Sun Jul 19 18:30:55 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c\nindex 11ea924a9f3577..b1178924eb06f7 100644\n--- a/drivers/net/dsa/mt7530-mdio.c\n+++ b/drivers/net/dsa/mt7530-mdio.c\n@@ -48,6 +48,9 @@ mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)\n \tu16 page, r, lo, hi;\n \tint ret;\n \n+\t/* Callers do not check for errors, keep the value deterministic */\n+\t*val = 0;\n+\n \tpage = (reg \u003e\u003e 6) \u0026 0x3ff;\n \tr = (reg \u003e\u003e 2) \u0026 0xf;\n \n@@ -141,12 +144,14 @@ static const struct regmap_config regmap_config = {\n \t.val_bits = 32,\n \t.reg_stride = 4,\n \t.max_register = MT7530_CREV,\n-\t.disable_locking = true,\n+\t.lock = mt7530_mdio_regmap_lock,\n+\t.unlock = mt7530_mdio_regmap_unlock,\n };\n \n static int\n mt7530_probe(struct mdio_device *mdiodev)\n {\n+\tstruct regmap_config rc = regmap_config;\n \tstruct mt7530_priv *priv;\n \tstruct device_node *dn;\n \tint ret;\n@@ -200,8 +205,9 @@ mt7530_probe(struct mdio_device *mdiodev)\n \t\t\treturn PTR_ERR(priv-\u003eio_pwr);\n \t}\n \n-\tpriv-\u003eregmap = devm_regmap_init(priv-\u003edev, \u0026mt7530_regmap_bus, priv,\n-\t\t\t\t\t\u0026regmap_config);\n+\trc.lock_arg = \u0026priv-\u003ebus-\u003emdio_lock;\n+\tpriv-\u003eregmap = devm_regmap_init(priv-\u003edev, \u0026mt7530_regmap_bus,\n+\t\t\t\t\tpriv, \u0026rc);\n \tif (IS_ERR(priv-\u003eregmap))\n \t\treturn PTR_ERR(priv-\u003eregmap);\n \ndiff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c\nindex 3c2a3029b10cfb..6fe6783dfe3f5f 100644\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -150,99 +150,17 @@ core_clear(struct mt7530_priv *priv, u32 reg, u32 val)\n \tcore_rmw(priv, reg, val, 0);\n }\n \n-static int\n-mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)\n-{\n-\tint ret;\n-\n-\tret = regmap_write(priv-\u003eregmap, reg, val);\n-\n-\tif (ret \u003c 0)\n-\t\tdev_err(priv-\u003edev,\n-\t\t\t\"failed to write mt7530 register\\n\");\n-\n-\treturn ret;\n-}\n \n static u32\n-mt7530_mii_read(struct mt7530_priv *priv, u32 reg)\n+mt7530_mii_poll(struct mt7530_dummy_poll *p)\n {\n-\tint ret;\n \tu32 val;\n \n-\tret = regmap_read(priv-\u003eregmap, reg, \u0026val);\n-\tif (ret) {\n-\t\tWARN_ON_ONCE(1);\n-\t\tdev_err(priv-\u003edev,\n-\t\t\t\"failed to read mt7530 register\\n\");\n-\t\treturn 0;\n-\t}\n+\tregmap_read(p-\u003epriv-\u003eregmap, p-\u003ereg, \u0026val);\n \n \treturn val;\n }\n \n-static void\n-mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)\n-{\n-\tmt7530_mutex_lock(priv);\n-\n-\tmt7530_mii_write(priv, reg, val);\n-\n-\tmt7530_mutex_unlock(priv);\n-}\n-\n-static u32\n-_mt7530_unlocked_read(struct mt7530_dummy_poll *p)\n-{\n-\treturn mt7530_mii_read(p-\u003epriv, p-\u003ereg);\n-}\n-\n-static u32\n-_mt7530_read(struct mt7530_dummy_poll *p)\n-{\n-\tu32 val;\n-\n-\tmt7530_mutex_lock(p-\u003epriv);\n-\n-\tval = mt7530_mii_read(p-\u003epriv, p-\u003ereg);\n-\n-\tmt7530_mutex_unlock(p-\u003epriv);\n-\n-\treturn val;\n-}\n-\n-static u32\n-mt7530_read(struct mt7530_priv *priv, u32 reg)\n-{\n-\tstruct mt7530_dummy_poll p;\n-\n-\tINIT_MT7530_DUMMY_POLL(\u0026p, priv, reg);\n-\treturn _mt7530_read(\u0026p);\n-}\n-\n-static void\n-mt7530_rmw(struct mt7530_priv *priv, u32 reg,\n-\t u32 mask, u32 set)\n-{\n-\tmt7530_mutex_lock(priv);\n-\n-\tregmap_update_bits(priv-\u003eregmap, reg, mask, set);\n-\n-\tmt7530_mutex_unlock(priv);\n-}\n-\n-static void\n-mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)\n-{\n-\tmt7530_rmw(priv, reg, val, val);\n-}\n-\n-static void\n-mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)\n-{\n-\tmt7530_rmw(priv, reg, val, 0);\n-}\n-\n static int\n mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)\n {\n@@ -252,10 +170,10 @@ mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)\n \n \t/* Set the command operating upon the MAC address entries */\n \tval = ATC_BUSY | ATC_MAT(0) | cmd;\n-\tmt7530_write(priv, MT7530_ATC, val);\n+\tregmap_write(priv-\u003eregmap, MT7530_ATC, val);\n \n \tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7530_ATC);\n-\tret = readx_poll_timeout(_mt7530_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 ATC_BUSY), 20, 20000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"reset timeout\\n\");\n@@ -265,7 +183,7 @@ mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)\n \t/* Additional sanity for read command if the specified\n \t * entry is invalid\n \t */\n-\tval = mt7530_read(priv, MT7530_ATC);\n+\tregmap_read(priv-\u003eregmap, MT7530_ATC, \u0026val);\n \tif ((cmd == MT7530_FDB_READ) \u0026\u0026 (val \u0026 ATC_INVALID))\n \t\treturn -EINVAL;\n \n@@ -275,6 +193,28 @@ mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)\n \treturn 0;\n }\n \n+static void mt7530_port_fast_age(struct dsa_switch *ds, int port)\n+{\n+\tstruct mt7530_priv *priv = ds-\u003epriv;\n+\tstruct mt7530_dummy_poll p;\n+\tu32 val;\n+\tint ret;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\n+\t/* Flush all non-static MAC address entries */\n+\tval = ATC_BUSY | ATC_MAT_NON_STATIC_MAC | MT7530_FDB_FLUSH;\n+\tregmap_write(priv-\u003eregmap, MT7530_ATC, val);\n+\n+\tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7530_ATC);\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n+\t\t\t\t !(val \u0026 ATC_BUSY), 20, 20000);\n+\tif (ret \u003c 0)\n+\t\tdev_err(priv-\u003edev, \"fast age timeout\\n\");\n+\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+}\n+\n static void\n mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)\n {\n@@ -283,22 +223,23 @@ mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)\n \n \t/* Read from ARL table into an array */\n \tfor (i = 0; i \u003c 3; i++) {\n-\t\treg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));\n+\t\tregmap_read(priv-\u003eregmap, MT7530_TSRA1 + (i * 4),\n+\t\t\t \u0026reg[i]);\n \n \t\tdev_dbg(priv-\u003edev, \"%s(%d) reg[%d]=0x%x\\n\",\n \t\t\t__func__, __LINE__, i, reg[i]);\n \t}\n \n-\tfdb-\u003evid = (reg[1] \u003e\u003e CVID) \u0026 CVID_MASK;\n-\tfdb-\u003eaging = (reg[2] \u003e\u003e AGE_TIMER) \u0026 AGE_TIMER_MASK;\n-\tfdb-\u003eport_mask = (reg[2] \u003e\u003e PORT_MAP) \u0026 PORT_MAP_MASK;\n-\tfdb-\u003emac[0] = (reg[0] \u003e\u003e MAC_BYTE_0) \u0026 MAC_BYTE_MASK;\n-\tfdb-\u003emac[1] = (reg[0] \u003e\u003e MAC_BYTE_1) \u0026 MAC_BYTE_MASK;\n-\tfdb-\u003emac[2] = (reg[0] \u003e\u003e MAC_BYTE_2) \u0026 MAC_BYTE_MASK;\n-\tfdb-\u003emac[3] = (reg[0] \u003e\u003e MAC_BYTE_3) \u0026 MAC_BYTE_MASK;\n-\tfdb-\u003emac[4] = (reg[1] \u003e\u003e MAC_BYTE_4) \u0026 MAC_BYTE_MASK;\n-\tfdb-\u003emac[5] = (reg[1] \u003e\u003e MAC_BYTE_5) \u0026 MAC_BYTE_MASK;\n-\tfdb-\u003enoarp = ((reg[2] \u003e\u003e ENT_STATUS) \u0026 ENT_STATUS_MASK) == STATIC_ENT;\n+\tfdb-\u003evid = FIELD_GET(CVID_MASK, reg[1]);\n+\tfdb-\u003eaging = FIELD_GET(AGE_TIMER_MASK, reg[2]);\n+\tfdb-\u003eport_mask = FIELD_GET(PORT_MAP_MASK, reg[2]);\n+\tfdb-\u003emac[0] = FIELD_GET(MAC_BYTE_0_MASK, reg[0]);\n+\tfdb-\u003emac[1] = FIELD_GET(MAC_BYTE_1_MASK, reg[0]);\n+\tfdb-\u003emac[2] = FIELD_GET(MAC_BYTE_2_MASK, reg[0]);\n+\tfdb-\u003emac[3] = FIELD_GET(MAC_BYTE_3_MASK, reg[0]);\n+\tfdb-\u003emac[4] = FIELD_GET(MAC_BYTE_4_MASK, reg[1]);\n+\tfdb-\u003emac[5] = FIELD_GET(MAC_BYTE_5_MASK, reg[1]);\n+\tfdb-\u003enoarp = FIELD_GET(ENT_STATUS_MASK, reg[2]) == STATIC_ENT;\n }\n \n static void\n@@ -309,26 +250,26 @@ mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,\n \tu32 reg[3] = { 0 };\n \tint i;\n \n-\treg[1] |= vid \u0026 CVID_MASK;\n+\treg[1] |= FIELD_PREP(CVID_MASK, vid);\n \treg[1] |= ATA2_IVL;\n \treg[1] |= ATA2_FID(FID_BRIDGED);\n-\treg[2] |= (aging \u0026 AGE_TIMER_MASK) \u003c\u003c AGE_TIMER;\n-\treg[2] |= (port_mask \u0026 PORT_MAP_MASK) \u003c\u003c PORT_MAP;\n+\treg[2] |= FIELD_PREP(AGE_TIMER_MASK, aging);\n+\treg[2] |= FIELD_PREP(PORT_MAP_MASK, port_mask);\n \t/* STATIC_ENT indicate that entry is static wouldn't\n \t * be aged out and STATIC_EMP specified as erasing an\n \t * entry\n \t */\n-\treg[2] |= (type \u0026 ENT_STATUS_MASK) \u003c\u003c ENT_STATUS;\n-\treg[1] |= mac[5] \u003c\u003c MAC_BYTE_5;\n-\treg[1] |= mac[4] \u003c\u003c MAC_BYTE_4;\n-\treg[0] |= mac[3] \u003c\u003c MAC_BYTE_3;\n-\treg[0] |= mac[2] \u003c\u003c MAC_BYTE_2;\n-\treg[0] |= mac[1] \u003c\u003c MAC_BYTE_1;\n-\treg[0] |= mac[0] \u003c\u003c MAC_BYTE_0;\n+\treg[2] |= FIELD_PREP(ENT_STATUS_MASK, type);\n+\treg[1] |= FIELD_PREP(MAC_BYTE_5_MASK, mac[5]);\n+\treg[1] |= FIELD_PREP(MAC_BYTE_4_MASK, mac[4]);\n+\treg[0] |= FIELD_PREP(MAC_BYTE_3_MASK, mac[3]);\n+\treg[0] |= FIELD_PREP(MAC_BYTE_2_MASK, mac[2]);\n+\treg[0] |= FIELD_PREP(MAC_BYTE_1_MASK, mac[1]);\n+\treg[0] |= FIELD_PREP(MAC_BYTE_0_MASK, mac[0]);\n \n \t/* Write array into the ARL table */\n \tfor (i = 0; i \u003c 3; i++)\n-\t\tmt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);\n+\t\tregmap_write(priv-\u003eregmap, MT7530_ATA1 + (i * 4), reg[i]);\n }\n \n /* Set up switch core clock for MT7530 */\n@@ -382,14 +323,16 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)\n \tcore_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);\n \n \tif (interface == PHY_INTERFACE_MODE_RGMII) {\n-\t\tmt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,\n-\t\t\t P6_INTF_MODE(0));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_P6ECR,\n+\t\t\t\t P6_INTF_MODE_MASK, P6_INTF_MODE(0));\n \t\treturn;\n \t}\n \n-\tmt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_P6ECR, P6_INTF_MODE_MASK,\n+\t\t\t P6_INTF_MODE(1));\n \n-\txtal = mt7530_read(priv, MT753X_MTRAP) \u0026 MT7530_XTAL_MASK;\n+\tregmap_read(priv-\u003eregmap, MT753X_MTRAP, \u0026xtal);\n+\txtal \u0026= MT7530_XTAL_MASK;\n \n \tif (xtal == MT7530_XTAL_25MHZ)\n \t\tssc_delta = 0x57;\n@@ -433,9 +376,9 @@ mt7531_pll_setup(struct mt7530_priv *priv)\n \tu32 hwstrap;\n \tu32 val;\n \n-\tval = mt7530_read(priv, MT7531_CREV);\n-\ttop_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);\n-\thwstrap = mt7530_read(priv, MT753X_TRAP);\n+\tregmap_read(priv-\u003eregmap, MT7531_CREV, \u0026val);\n+\tregmap_read(priv-\u003eregmap, MT7531_TOP_SIG_SR, \u0026top_sig);\n+\tregmap_read(priv-\u003eregmap, MT753X_TRAP, \u0026hwstrap);\n \tif ((val \u0026 CHIP_REV_M) \u003e 0)\n \t\txtal = (top_sig \u0026 PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :\n \t\t\t\t\t\t MT7531_XTAL_FSEL_25MHZ;\n@@ -444,72 +387,72 @@ mt7531_pll_setup(struct mt7530_priv *priv)\n \t\t\t\t\t\t MT7531_XTAL_FSEL_40MHZ;\n \n \t/* Step 1 : Disable MT7531 COREPLL */\n-\tval = mt7530_read(priv, MT7531_PLLGP_EN);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_EN, \u0026val);\n \tval \u0026= ~EN_COREPLL;\n-\tmt7530_write(priv, MT7531_PLLGP_EN, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_EN, val);\n \n \t/* Step 2: switch to XTAL output */\n-\tval = mt7530_read(priv, MT7531_PLLGP_EN);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_EN, \u0026val);\n \tval |= SW_CLKSW;\n-\tmt7530_write(priv, MT7531_PLLGP_EN, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_EN, val);\n \n-\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_CR0, \u0026val);\n \tval \u0026= ~RG_COREPLL_EN;\n-\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_CR0, val);\n \n \t/* Step 3: disable PLLGP and enable program PLLGP */\n-\tval = mt7530_read(priv, MT7531_PLLGP_EN);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_EN, \u0026val);\n \tval |= SW_PLLGP;\n-\tmt7530_write(priv, MT7531_PLLGP_EN, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_EN, val);\n \n \t/* Step 4: program COREPLL output frequency to 500MHz */\n-\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\n-\tval \u0026= ~RG_COREPLL_POSDIV_M;\n-\tval |= 2 \u003c\u003c RG_COREPLL_POSDIV_S;\n-\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_CR0, \u0026val);\n+\tval \u0026= ~RG_COREPLL_POSDIV_MASK;\n+\tval |= RG_COREPLL_POSDIV(2);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_CR0, val);\n \tusleep_range(25, 35);\n \n \tswitch (xtal) {\n \tcase MT7531_XTAL_FSEL_25MHZ:\n-\t\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\n-\t\tval \u0026= ~RG_COREPLL_SDM_PCW_M;\n-\t\tval |= 0x140000 \u003c\u003c RG_COREPLL_SDM_PCW_S;\n-\t\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\n+\t\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_CR0, \u0026val);\n+\t\tval \u0026= ~RG_COREPLL_SDM_PCW_MASK;\n+\t\tval |= RG_COREPLL_SDM_PCW(0x140000);\n+\t\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_CR0, val);\n \t\tbreak;\n \tcase MT7531_XTAL_FSEL_40MHZ:\n-\t\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\n-\t\tval \u0026= ~RG_COREPLL_SDM_PCW_M;\n-\t\tval |= 0x190000 \u003c\u003c RG_COREPLL_SDM_PCW_S;\n-\t\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\n+\t\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_CR0, \u0026val);\n+\t\tval \u0026= ~RG_COREPLL_SDM_PCW_MASK;\n+\t\tval |= RG_COREPLL_SDM_PCW(0x190000);\n+\t\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_CR0, val);\n \t\tbreak;\n \t}\n \n \t/* Set feedback divide ratio update signal to high */\n-\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_CR0, \u0026val);\n \tval |= RG_COREPLL_SDM_PCW_CHG;\n-\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_CR0, val);\n \t/* Wait for at least 16 XTAL clocks */\n \tusleep_range(10, 20);\n \n \t/* Step 5: set feedback divide ratio update signal to low */\n-\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_CR0, \u0026val);\n \tval \u0026= ~RG_COREPLL_SDM_PCW_CHG;\n-\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_CR0, val);\n \n \t/* Enable 325M clock for SGMII */\n-\tmt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);\n+\tregmap_write(priv-\u003eregmap, MT7531_ANA_PLLGP_CR5, 0xad0000);\n \n \t/* Enable 250SSC clock for RGMII */\n-\tmt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);\n+\tregmap_write(priv-\u003eregmap, MT7531_ANA_PLLGP_CR2, 0x4f40000);\n \n \t/* Step 6: Enable MT7531 PLL */\n-\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_CR0, \u0026val);\n \tval |= RG_COREPLL_EN;\n-\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_CR0, val);\n \n-\tval = mt7530_read(priv, MT7531_PLLGP_EN);\n+\tregmap_read(priv-\u003eregmap, MT7531_PLLGP_EN, \u0026val);\n \tval |= EN_COREPLL;\n-\tmt7530_write(priv, MT7531_PLLGP_EN, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_PLLGP_EN, val);\n \tusleep_range(25, 35);\n }\n \n@@ -518,8 +461,8 @@ mt7530_mib_reset(struct dsa_switch *ds)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\tmt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);\n-\tmt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);\n+\tregmap_write(priv-\u003eregmap, MT7530_MIB_CCR, CCR_MIB_FLUSH);\n+\tregmap_write(priv-\u003eregmap, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);\n }\n \n static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)\n@@ -555,9 +498,9 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,\n \n \tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7531_PHY_IAC);\n \n-\tmt7530_mutex_lock(priv);\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -566,9 +509,9 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,\n \n \treg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |\n \t MT7531_MDIO_DEV_ADDR(devad) | regnum;\n-\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n+\tregmap_write(priv-\u003eregmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -577,9 +520,9 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,\n \n \treg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |\n \t MT7531_MDIO_DEV_ADDR(devad);\n-\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n+\tregmap_write(priv-\u003eregmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -588,7 +531,7 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,\n \n \tret = val \u0026 MT7531_MDIO_RW_DATA_MASK;\n out:\n-\tmt7530_mutex_unlock(priv);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n \treturn ret;\n }\n@@ -603,9 +546,9 @@ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,\n \n \tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7531_PHY_IAC);\n \n-\tmt7530_mutex_lock(priv);\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -614,9 +557,9 @@ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,\n \n \treg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |\n \t MT7531_MDIO_DEV_ADDR(devad) | regnum;\n-\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n+\tregmap_write(priv-\u003eregmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -625,9 +568,9 @@ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,\n \n \treg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |\n \t MT7531_MDIO_DEV_ADDR(devad) | data;\n-\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n+\tregmap_write(priv-\u003eregmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -635,7 +578,7 @@ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,\n \t}\n \n out:\n-\tmt7530_mutex_unlock(priv);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n \treturn ret;\n }\n@@ -649,9 +592,9 @@ mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)\n \n \tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7531_PHY_IAC);\n \n-\tmt7530_mutex_lock(priv);\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -661,9 +604,9 @@ mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)\n \tval = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |\n \t MT7531_MDIO_REG_ADDR(regnum);\n \n-\tmt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);\n+\tregmap_write(priv-\u003eregmap, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -672,7 +615,7 @@ mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)\n \n \tret = val \u0026 MT7531_MDIO_RW_DATA_MASK;\n out:\n-\tmt7530_mutex_unlock(priv);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n \treturn ret;\n }\n@@ -687,9 +630,9 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,\n \n \tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7531_PHY_IAC);\n \n-\tmt7530_mutex_lock(priv);\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, reg,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, reg,\n \t\t\t\t !(reg \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -699,9 +642,9 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,\n \treg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |\n \t MT7531_MDIO_REG_ADDR(regnum) | data;\n \n-\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n+\tregmap_write(priv-\u003eregmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\n \n-\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, reg,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, reg,\n \t\t\t\t !(reg \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n@@ -709,7 +652,7 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,\n \t}\n \n out:\n-\tmt7530_mutex_unlock(priv);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n \treturn ret;\n }\n@@ -766,11 +709,11 @@ mt7530_read_port_stats(struct mt7530_priv *priv, int port,\n {\n \tu32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset;\n \n-\tval = mt7530_read(priv, reg);\n+\tregmap_read(priv-\u003eregmap, reg, \u0026val);\n \t*data = val;\n \n \tif (size == 2) {\n-\t\tval = mt7530_read(priv, reg + 4);\n+\t\tregmap_read(priv-\u003eregmap, reg + 4, \u0026val);\n \t\t*data |= (u64)val \u003c\u003c 32;\n \t}\n }\n@@ -1052,7 +995,8 @@ mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)\n \t\t}\n \t}\n \n-\tmt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));\n+\tregmap_write(priv-\u003eregmap, MT7530_AAC,\n+\t\t AGE_CNT(age_count) | AGE_UNIT(age_unit));\n \n \treturn 0;\n }\n@@ -1073,11 +1017,11 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \tu8 tx_delay = 0;\n-\tint val;\n+\tu32 val;\n \n \tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n-\tval = mt7530_read(priv, MT753X_MTRAP);\n+\tregmap_read(priv-\u003eregmap, MT753X_MTRAP, \u0026val);\n \n \tval \u0026= ~MT7530_P5_PHY0_SEL \u0026 ~MT7530_P5_MAC_SEL \u0026 ~MT7530_P5_RGMII_MODE;\n \n@@ -1090,7 +1034,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)\n \t/* MUX_PHY_P4: P4 -\u003e P5 -\u003e SoC MAC */\n \tcase MUX_PHY_P4:\n \t\t/* Setup the MAC by default for the cpu port */\n-\t\tmt7530_write(priv, MT753X_PMCR_P(5), 0x56300);\n+\t\tregmap_write(priv-\u003eregmap, MT753X_PMCR_P(5), 0x56300);\n \t\tbreak;\n \n \t/* GMAC5: P5 -\u003e SoC MAC or external PHY */\n@@ -1104,7 +1048,8 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)\n \t\tval |= MT7530_P5_RGMII_MODE;\n \n \t\t/* P5 RGMII RX Clock Control: delay setting for 1000M */\n-\t\tmt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);\n+\t\tregmap_write(priv-\u003eregmap, MT7530_P5RGMIIRXCR,\n+\t\t\t CSR_RGMII_EDGE_ALIGN);\n \n \t\t/* Don't set delay in DSA mode */\n \t\tif (!dsa_is_dsa_port(priv-\u003eds, 5) \u0026\u0026\n@@ -1113,15 +1058,15 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)\n \t\t\ttx_delay = 4; /* n * 0.5 ns */\n \n \t\t/* P5 RGMII TX Clock Control: delay x */\n-\t\tmt7530_write(priv, MT7530_P5RGMIITXCR,\n+\t\tregmap_write(priv-\u003eregmap, MT7530_P5RGMIITXCR,\n \t\t\t CSR_RGMII_TXC_CFG(0x10 + tx_delay));\n \n \t\t/* reduce P5 RGMII Tx driving, 8mA */\n-\t\tmt7530_write(priv, MT7530_IO_DRV_CR,\n+\t\tregmap_write(priv-\u003eregmap, MT7530_IO_DRV_CR,\n \t\t\t P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));\n \t}\n \n-\tmt7530_write(priv, MT753X_MTRAP, val);\n+\tregmap_write(priv-\u003eregmap, MT753X_MTRAP, val);\n \n \tdev_dbg(ds-\u003edev, \"Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\\n\", val,\n \t\tmt7530_p5_mode_str(priv-\u003ep5_mode), phy_modes(interface));\n@@ -1306,35 +1251,35 @@ mt753x_trap_frames(struct mt7530_priv *priv)\n \t * switch egress VLAN tag processing. This preserves VLAN tags\n \t * for reception on VLAN sub-interfaces.\n \t */\n-\tmt7530_rmw(priv, MT753X_BPC,\n-\t\t PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |\n-\t\t\t BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,\n-\t\t PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |\n-\t\t\t BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t TO_CPU_FW_CPU_ONLY);\n+\tregmap_update_bits(priv-\u003eregmap, MT753X_BPC,\n+\t\t\t PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |\n+\t\t\t\t BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,\n+\t\t\t PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n+\t\t\t\t PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |\n+\t\t\t\t BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n+\t\t\t\t TO_CPU_FW_CPU_ONLY);\n \n \t/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and\n \t * egress them with EG_TAG disabled.\n \t */\n-\tmt7530_rmw(priv, MT753X_RGAC1,\n-\t\t R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |\n-\t\t\t R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,\n-\t\t R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |\n-\t\t\t R01_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t TO_CPU_FW_CPU_ONLY);\n+\tregmap_update_bits(priv-\u003eregmap, MT753X_RGAC1,\n+\t\t\t R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |\n+\t\t\t\t R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,\n+\t\t\t R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n+\t\t\t\t R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |\n+\t\t\t\t R01_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n+\t\t\t\t TO_CPU_FW_CPU_ONLY);\n \n \t/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and\n \t * egress them with EG_TAG disabled.\n \t */\n-\tmt7530_rmw(priv, MT753X_RGAC2,\n-\t\t R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |\n-\t\t\t R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,\n-\t\t R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |\n-\t\t\t R03_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t TO_CPU_FW_CPU_ONLY);\n+\tregmap_update_bits(priv-\u003eregmap, MT753X_RGAC2,\n+\t\t\t R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |\n+\t\t\t\t R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,\n+\t\t\t R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n+\t\t\t\t R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |\n+\t\t\t\t R03_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n+\t\t\t\t TO_CPU_FW_CPU_ONLY);\n }\n \n static void\n@@ -1343,12 +1288,11 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n \t/* Enable Mediatek header mode on the cpu port */\n-\tmt7530_write(priv, MT7530_PVC_P(port),\n-\t\t PORT_SPEC_TAG);\n+\tregmap_write(priv-\u003eregmap, MT7530_PVC_P(port), PORT_SPEC_TAG);\n \n \t/* Enable flooding on the CPU port */\n-\tmt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |\n-\t\t UNU_FFP(BIT(port)));\n+\tregmap_set_bits(priv-\u003eregmap, MT753X_MFC,\n+\t\t\tBC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));\n \n \t/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on\n \t * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that\n@@ -1356,17 +1300,18 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)\n \t */\n \tif (priv-\u003eid == ID_MT7531 || priv-\u003eid == ID_MT7988 ||\n \t priv-\u003eid == ID_EN7581 || priv-\u003eid == ID_AN7583)\n-\t\tmt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));\n+\t\tregmap_set_bits(priv-\u003eregmap, MT7531_CFC,\n+\t\t\t\tMT7531_CPU_PMAP(BIT(port)));\n \n \t/* CPU port gets connected to all user ports of\n \t * the switch.\n \t */\n-\tmt7530_write(priv, MT7530_PCR_P(port),\n+\tregmap_write(priv-\u003eregmap, MT7530_PCR_P(port),\n \t\t PCR_MATRIX(dsa_user_ports(priv-\u003eds)));\n \n \t/* Set to fallback mode for independent VLAN learning */\n-\tmt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,\n-\t\t MT7530_PORT_FALLBACK_MODE);\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n+\t\t\t PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE);\n }\n \n static int\n@@ -1388,8 +1333,8 @@ mt7530_port_enable(struct dsa_switch *ds, int port,\n \t\tpriv-\u003eports[port].pm |= PCR_MATRIX(BIT(cpu_dp-\u003eindex));\n \t}\n \tpriv-\u003eports[port].enable = true;\n-\tmt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,\n-\t\t priv-\u003eports[port].pm);\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port), PCR_MATRIX_MASK,\n+\t\t\t priv-\u003eports[port].pm);\n \n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n@@ -1397,9 +1342,9 @@ mt7530_port_enable(struct dsa_switch *ds, int port,\n \t\treturn 0;\n \n \tif (port == 5)\n-\t\tmt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);\n+\t\tregmap_clear_bits(priv-\u003eregmap, MT753X_MTRAP, MT7530_P5_DIS);\n \telse if (port == 6)\n-\t\tmt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);\n+\t\tregmap_clear_bits(priv-\u003eregmap, MT753X_MTRAP, MT7530_P6_DIS);\n \n \treturn 0;\n }\n@@ -1415,8 +1360,8 @@ mt7530_port_disable(struct dsa_switch *ds, int port)\n \t * enablement for the port.\n \t */\n \tpriv-\u003eports[port].enable = false;\n-\tmt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,\n-\t\t PCR_MATRIX_CLR);\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port), PCR_MATRIX_MASK,\n+\t\t\t PCR_MATRIX_CLR);\n \n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n@@ -1425,9 +1370,9 @@ mt7530_port_disable(struct dsa_switch *ds, int port)\n \n \t/* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */\n \tif (port == 5 \u0026\u0026 priv-\u003ep5_mode == GMAC5)\n-\t\tmt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT753X_MTRAP, MT7530_P5_DIS);\n \telse if (port == 6)\n-\t\tmt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT753X_MTRAP, MT7530_P6_DIS);\n }\n \n static int\n@@ -1444,9 +1389,7 @@ mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n \tif (!dsa_is_cpu_port(ds, port))\n \t\treturn 0;\n \n-\tmt7530_mutex_lock(priv);\n-\n-\tval = mt7530_mii_read(priv, MT7530_GMACCR);\n+\tregmap_read(priv-\u003eregmap, MT7530_GMACCR, \u0026val);\n \tval \u0026= ~MAX_RX_PKT_LEN_MASK;\n \n \t/* RX length also includes Ethernet header, MTK tag, and FCS length */\n@@ -1463,9 +1406,7 @@ mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n \t\tval |= MAX_RX_PKT_LEN_JUMBO;\n \t}\n \n-\tmt7530_mii_write(priv, MT7530_GMACCR, val);\n-\n-\tmt7530_mutex_unlock(priv);\n+\tregmap_write(priv-\u003eregmap, MT7530_GMACCR, val);\n \n \treturn 0;\n }\n@@ -1501,8 +1442,9 @@ mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)\n \t\tbreak;\n \t}\n \n-\tmt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),\n-\t\t FID_PST(FID_BRIDGED, stp_state));\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_SSP_P(port),\n+\t\t\t FID_PST_MASK(FID_BRIDGED),\n+\t\t\t FID_PST(FID_BRIDGED, stp_state));\n }\n \n static void mt7530_update_port_member(struct mt7530_priv *priv, int port,\n@@ -1541,8 +1483,9 @@ static void mt7530_update_port_member(struct mt7530_priv *priv, int port,\n \t\t}\n \n \t\tif (other_p-\u003eenable)\n-\t\t\tmt7530_rmw(priv, MT7530_PCR_P(other_port),\n-\t\t\t\t PCR_MATRIX_MASK, other_p-\u003epm);\n+\t\t\tregmap_update_bits(priv-\u003eregmap,\n+\t\t\t\t\t MT7530_PCR_P(other_port),\n+\t\t\t\t\t PCR_MATRIX_MASK, other_p-\u003epm);\n \t}\n \n \t/* Add/remove the all other ports to this port matrix. For !join\n@@ -1551,7 +1494,8 @@ static void mt7530_update_port_member(struct mt7530_priv *priv, int port,\n \t */\n \tp-\u003epm = PCR_MATRIX(port_bitmap);\n \tif (priv-\u003eports[port].enable)\n-\t\tmt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p-\u003epm);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n+\t\t\t\t PCR_MATRIX_MASK, p-\u003epm);\n }\n \n static int\n@@ -1574,20 +1518,23 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int port,\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n \tif (flags.mask \u0026 BR_LEARNING)\n-\t\tmt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,\n-\t\t\t flags.val \u0026 BR_LEARNING ? 0 : SA_DIS);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PSC_P(port), SA_DIS,\n+\t\t\t\t flags.val \u0026 BR_LEARNING ? 0 : SA_DIS);\n \n \tif (flags.mask \u0026 BR_FLOOD)\n-\t\tmt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),\n-\t\t\t flags.val \u0026 BR_FLOOD ? UNU_FFP(BIT(port)) : 0);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT753X_MFC,\n+\t\t\t\t UNU_FFP(BIT(port)),\n+\t\t\t\t flags.val \u0026 BR_FLOOD ? UNU_FFP(BIT(port)) : 0);\n \n \tif (flags.mask \u0026 BR_MCAST_FLOOD)\n-\t\tmt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),\n-\t\t\t flags.val \u0026 BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT753X_MFC,\n+\t\t\t\t UNM_FFP(BIT(port)),\n+\t\t\t\t flags.val \u0026 BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);\n \n \tif (flags.mask \u0026 BR_BCAST_FLOOD)\n-\t\tmt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),\n-\t\t\t flags.val \u0026 BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT753X_MFC,\n+\t\t\t\t BC_FFP(BIT(port)),\n+\t\t\t\t flags.val \u0026 BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);\n \n \tif (flags.mask \u0026 BR_ISOLATED) {\n \t\tstruct dsa_port *dp = dsa_to_port(ds, port);\n@@ -1615,8 +1562,8 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int port,\n \tmt7530_update_port_member(priv, port, bridge.dev, true);\n \n \t/* Set to fallback mode for independent VLAN learning */\n-\tmt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,\n-\t\t MT7530_PORT_FALLBACK_MODE);\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n+\t\t\t PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE);\n \n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n@@ -1630,18 +1577,18 @@ mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)\n \tu32 val;\n \tint ret;\n \n-\tval = VTCR_BUSY | VTCR_FUNC(cmd) | vid;\n-\tmt7530_write(priv, MT7530_VTCR, val);\n+\tval = VTCR_BUSY | VTCR_FUNC(cmd) | VTCR_VID(vid);\n+\tregmap_write(priv-\u003eregmap, MT7530_VTCR, val);\n \n \tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7530_VTCR);\n-\tret = readx_poll_timeout(_mt7530_read, \u0026p, val,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\n \t\t\t\t !(val \u0026 VTCR_BUSY), 20, 20000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n \t\treturn ret;\n \t}\n \n-\tval = mt7530_read(priv, MT7530_VTCR);\n+\tregmap_read(priv-\u003eregmap, MT7530_VTCR, \u0026val);\n \tif (val \u0026 VTCR_INVALID) {\n \t\tdev_err(priv-\u003edev, \"read VTCR invalid\\n\");\n \t\treturn -EINVAL;\n@@ -1660,8 +1607,8 @@ mt7530_setup_vlan0(struct mt7530_priv *priv)\n \t */\n \tval = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |\n \t VLAN_VALID;\n-\tmt7530_write(priv, MT7530_VAWD1, val);\n-\tmt7530_write(priv, MT7530_VAWD2, 0);\n+\tregmap_write(priv-\u003eregmap, MT7530_VAWD1, val);\n+\tregmap_write(priv-\u003eregmap, MT7530_VAWD2, 0);\n \n \treturn mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);\n }\n@@ -1677,18 +1624,19 @@ mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)\n \t * bridge. Don't set standalone ports to fallback mode.\n \t */\n \tif (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))\n-\t\tmt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,\n-\t\t\t MT7530_PORT_FALLBACK_MODE);\n-\n-\tmt7530_rmw(priv, MT7530_PVC_P(port),\n-\t\t VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,\n-\t\t VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |\n-\t\t PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |\n-\t\t MT7530_VLAN_ACC_ALL);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n+\t\t\t\t PCR_PORT_VLAN_MASK,\n+\t\t\t\t MT7530_PORT_FALLBACK_MODE);\n+\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n+\t\t\t VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,\n+\t\t\t VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |\n+\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |\n+\t\t\t MT7530_VLAN_ACC_ALL);\n \n \t/* Set PVID to 0 */\n-\tmt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,\n-\t\t G0_PORT_VID_DEF);\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n+\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n \n \tfor (i = 0; i \u003c priv-\u003eds-\u003enum_ports; i++) {\n \t\tif (i == port)\n@@ -1719,24 +1667,27 @@ mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)\n \t * table lookup.\n \t */\n \tif (dsa_is_user_port(ds, port)) {\n-\t\tmt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,\n-\t\t\t MT7530_PORT_SECURITY_MODE);\n-\t\tmt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,\n-\t\t\t G0_PORT_VID(priv-\u003eports[port].pvid));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n+\t\t\t\t PCR_PORT_VLAN_MASK,\n+\t\t\t\t MT7530_PORT_SECURITY_MODE);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n+\t\t\t\t G0_PORT_VID_MASK,\n+\t\t\t\t G0_PORT_VID(priv-\u003eports[port].pvid));\n \n \t\t/* Only accept tagged frames if PVID is not set */\n \t\tif (!priv-\u003eports[port].pvid)\n-\t\t\tmt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,\n-\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n+\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n+\t\t\t\t\t ACC_FRM_MASK,\n+\t\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n \n \t\t/* Set the port as a user port which is to be able to recognize\n \t\t * VID from incoming packets before fetching entry within the\n \t\t * VLAN table.\n \t\t */\n-\t\tmt7530_rmw(priv, MT7530_PVC_P(port),\n-\t\t\t VLAN_ATTR_MASK | PVC_EG_TAG_MASK,\n-\t\t\t VLAN_ATTR(MT7530_VLAN_USER) |\n-\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n+\t\t\t\t VLAN_ATTR_MASK | PVC_EG_TAG_MASK,\n+\t\t\t\t VLAN_ATTR(MT7530_VLAN_USER) |\n+\t\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));\n \t} else {\n \t\t/* Also set CPU ports to the \"user\" VLAN port attribute, to\n \t\t * allow VLAN classification, but keep the EG_TAG attribute as\n@@ -1745,8 +1696,9 @@ mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)\n \t\t * are forwarded to user ports as tagged, and untagged as\n \t\t * untagged.\n \t\t */\n-\t\tmt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,\n-\t\t\t VLAN_ATTR(MT7530_VLAN_USER));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n+\t\t\t\t VLAN_ATTR_MASK,\n+\t\t\t\t VLAN_ATTR(MT7530_VLAN_USER));\n \t}\n }\n \n@@ -1764,8 +1716,8 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int port,\n \t * back to the default as is at initial boot which is a VLAN-unaware\n \t * port.\n \t */\n-\tmt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,\n-\t\t MT7530_PORT_MATRIX_MODE);\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n+\t\t\t PCR_PORT_VLAN_MASK, MT7530_PORT_MATRIX_MODE);\n \n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n }\n@@ -1848,14 +1800,16 @@ mt7530_port_mdb_add(struct dsa_switch *ds, int port,\n \tconst u8 *addr = mdb-\u003eaddr;\n \tu16 vid = mdb-\u003evid;\n \tu8 port_mask = 0;\n+\tu32 val;\n \tint ret;\n \n \tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n \tmt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);\n-\tif (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))\n-\t\tport_mask = (mt7530_read(priv, MT7530_ATRD) \u003e\u003e PORT_MAP)\n-\t\t\t \u0026 PORT_MAP_MASK;\n+\tif (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {\n+\t\tregmap_read(priv-\u003eregmap, MT7530_ATRD, \u0026val);\n+\t\tport_mask = FIELD_GET(PORT_MAP_MASK, val);\n+\t}\n \n \tport_mask |= BIT(port);\n \tmt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);\n@@ -1875,14 +1829,16 @@ mt7530_port_mdb_del(struct dsa_switch *ds, int port,\n \tconst u8 *addr = mdb-\u003eaddr;\n \tu16 vid = mdb-\u003evid;\n \tu8 port_mask = 0;\n+\tu32 val;\n \tint ret;\n \n \tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n \tmt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);\n-\tif (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))\n-\t\tport_mask = (mt7530_read(priv, MT7530_ATRD) \u003e\u003e PORT_MAP)\n-\t\t\t \u0026 PORT_MAP_MASK;\n+\tif (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {\n+\t\tregmap_read(priv-\u003eregmap, MT7530_ATRD, \u0026val);\n+\t\tport_mask = FIELD_GET(PORT_MAP_MASK, val);\n+\t}\n \n \tport_mask \u0026= ~BIT(port);\n \tmt7530_fdb_write(priv, vid, port_mask, addr, -1,\n@@ -1931,7 +1887,7 @@ mt7530_hw_vlan_add(struct mt7530_priv *priv,\n \t */\n \tval = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |\n \t VLAN_VALID;\n-\tmt7530_write(priv, MT7530_VAWD1, val);\n+\tregmap_write(priv-\u003eregmap, MT7530_VAWD1, val);\n \n \t/* Decide whether adding tag or not for those outgoing packets from the\n \t * port inside the VLAN.\n@@ -1946,9 +1902,9 @@ mt7530_hw_vlan_add(struct mt7530_priv *priv,\n \t\tval = MT7530_VLAN_EGRESS_UNTAG;\n \telse\n \t\tval = MT7530_VLAN_EGRESS_TAG;\n-\tmt7530_rmw(priv, MT7530_VAWD2,\n-\t\t ETAG_CTRL_P_MASK(entry-\u003eport),\n-\t\t ETAG_CTRL_P(entry-\u003eport, val));\n+\tregmap_update_bits(priv-\u003eregmap, MT7530_VAWD2,\n+\t\t\t ETAG_CTRL_P_MASK(entry-\u003eport),\n+\t\t\t ETAG_CTRL_P(entry-\u003eport, val));\n }\n \n static void\n@@ -1960,7 +1916,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *priv,\n \n \tnew_members = entry-\u003eold_members \u0026 ~BIT(entry-\u003eport);\n \n-\tval = mt7530_read(priv, MT7530_VAWD1);\n+\tregmap_read(priv-\u003eregmap, MT7530_VAWD1, \u0026val);\n \tif (!(val \u0026 VLAN_VALID)) {\n \t\tdev_err(priv-\u003edev,\n \t\t\t\"Cannot be deleted due to invalid entry\\n\");\n@@ -1970,10 +1926,10 @@ mt7530_hw_vlan_del(struct mt7530_priv *priv,\n \tif (new_members) {\n \t\tval = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |\n \t\t VLAN_VALID;\n-\t\tmt7530_write(priv, MT7530_VAWD1, val);\n+\t\tregmap_write(priv-\u003eregmap, MT7530_VAWD1, val);\n \t} else {\n-\t\tmt7530_write(priv, MT7530_VAWD1, 0);\n-\t\tmt7530_write(priv, MT7530_VAWD2, 0);\n+\t\tregmap_write(priv-\u003eregmap, MT7530_VAWD1, 0);\n+\t\tregmap_write(priv-\u003eregmap, MT7530_VAWD2, 0);\n \t}\n }\n \n@@ -1987,9 +1943,9 @@ mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,\n \t/* Fetch entry */\n \tmt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);\n \n-\tval = mt7530_read(priv, MT7530_VAWD1);\n+\tregmap_read(priv-\u003eregmap, MT7530_VAWD1, \u0026val);\n \n-\tentry-\u003eold_members = (val \u003e\u003e PORT_MEM_SHFT) \u0026 PORT_MEM_MASK;\n+\tentry-\u003eold_members = FIELD_GET(PORT_MEM_MASK, val);\n \n \t/* Manipulate entry */\n \tvlan_op(priv, entry);\n@@ -2026,25 +1982,26 @@ mt7530_port_vlan_add(struct dsa_switch *ds, int port,\n \t\tpriv-\u003eports[port].pvid = vlan-\u003evid;\n \n \t\t/* Accept all frames if PVID is set */\n-\t\tmt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,\n-\t\t\t MT7530_VLAN_ACC_ALL);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n+\t\t\t\t ACC_FRM_MASK, MT7530_VLAN_ACC_ALL);\n \n \t\t/* Only configure PVID if VLAN filtering is enabled */\n \t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n-\t\t\tmt7530_rmw(priv, MT7530_PPBV1_P(port),\n-\t\t\t\t G0_PORT_VID_MASK,\n-\t\t\t\t G0_PORT_VID(vlan-\u003evid));\n+\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n+\t\t\t\t\t G0_PORT_VID_MASK,\n+\t\t\t\t\t G0_PORT_VID(vlan-\u003evid));\n \t} else if (vlan-\u003evid \u0026\u0026 priv-\u003eports[port].pvid == vlan-\u003evid) {\n \t\t/* This VLAN is overwritten without PVID, so unset it */\n \t\tpriv-\u003eports[port].pvid = G0_PORT_VID_DEF;\n \n \t\t/* Only accept tagged frames if the port is VLAN-aware */\n \t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n-\t\t\tmt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,\n-\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n+\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n+\t\t\t\t\t ACC_FRM_MASK,\n+\t\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n \n-\t\tmt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,\n-\t\t\t G0_PORT_VID_DEF);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n+\t\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n \t}\n \n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n@@ -2078,11 +2035,12 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int port,\n \n \t\t/* Only accept tagged frames if the port is VLAN-aware */\n \t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n-\t\t\tmt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,\n-\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n+\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n+\t\t\t\t\t ACC_FRM_MASK,\n+\t\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n \n-\t\tmt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,\n-\t\t\t G0_PORT_VID_DEF);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n+\t\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n \t}\n \n \n@@ -2103,7 +2061,7 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,\n \tif ((ingress ? priv-\u003emirror_rx : priv-\u003emirror_tx) \u0026 BIT(port))\n \t\treturn -EEXIST;\n \n-\tval = mt7530_read(priv, MT753X_MIRROR_REG(priv-\u003eid));\n+\tregmap_read(priv-\u003eregmap, MT753X_MIRROR_REG(priv-\u003eid), \u0026val);\n \n \t/* MT7530 only supports one monitor port */\n \tmonitor_port = MT753X_MIRROR_PORT_GET(priv-\u003eid, val);\n@@ -2114,9 +2072,9 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,\n \tval |= MT753X_MIRROR_EN(priv-\u003eid);\n \tval \u0026= ~MT753X_MIRROR_PORT_MASK(priv-\u003eid);\n \tval |= MT753X_MIRROR_PORT_SET(priv-\u003eid, mirror-\u003eto_local_port);\n-\tmt7530_write(priv, MT753X_MIRROR_REG(priv-\u003eid), val);\n+\tregmap_write(priv-\u003eregmap, MT753X_MIRROR_REG(priv-\u003eid), val);\n \n-\tval = mt7530_read(priv, MT7530_PCR_P(port));\n+\tregmap_read(priv-\u003eregmap, MT7530_PCR_P(port), \u0026val);\n \tif (ingress) {\n \t\tval |= PORT_RX_MIR;\n \t\tpriv-\u003emirror_rx |= BIT(port);\n@@ -2124,7 +2082,7 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,\n \t\tval |= PORT_TX_MIR;\n \t\tpriv-\u003emirror_tx |= BIT(port);\n \t}\n-\tmt7530_write(priv, MT7530_PCR_P(port), val);\n+\tregmap_write(priv-\u003eregmap, MT7530_PCR_P(port), val);\n \n \treturn 0;\n }\n@@ -2135,7 +2093,7 @@ static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \tu32 val;\n \n-\tval = mt7530_read(priv, MT7530_PCR_P(port));\n+\tregmap_read(priv-\u003eregmap, MT7530_PCR_P(port), \u0026val);\n \tif (mirror-\u003eingress) {\n \t\tval \u0026= ~PORT_RX_MIR;\n \t\tpriv-\u003emirror_rx \u0026= ~BIT(port);\n@@ -2143,12 +2101,12 @@ static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,\n \t\tval \u0026= ~PORT_TX_MIR;\n \t\tpriv-\u003emirror_tx \u0026= ~BIT(port);\n \t}\n-\tmt7530_write(priv, MT7530_PCR_P(port), val);\n+\tregmap_write(priv-\u003eregmap, MT7530_PCR_P(port), val);\n \n \tif (!priv-\u003emirror_rx \u0026\u0026 !priv-\u003emirror_tx) {\n-\t\tval = mt7530_read(priv, MT753X_MIRROR_REG(priv-\u003eid));\n+\t\tregmap_read(priv-\u003eregmap, MT753X_MIRROR_REG(priv-\u003eid), \u0026val);\n \t\tval \u0026= ~MT753X_MIRROR_EN(priv-\u003eid);\n-\t\tmt7530_write(priv, MT753X_MIRROR_REG(priv-\u003eid), val);\n+\t\tregmap_write(priv-\u003eregmap, MT753X_MIRROR_REG(priv-\u003eid), val);\n \t}\n }\n \n@@ -2178,8 +2136,11 @@ mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)\n {\n \tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n \tu32 bit = mt7530_gpio_to_bit(offset);\n+\tu32 val;\n+\n+\tregmap_read(priv-\u003eregmap, MT7530_LED_GPIO_DATA, \u0026val);\n \n-\treturn !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) \u0026 bit);\n+\treturn !!(val \u0026 bit);\n }\n \n static int\n@@ -2189,9 +2150,9 @@ mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)\n \tu32 bit = mt7530_gpio_to_bit(offset);\n \n \tif (value)\n-\t\tmt7530_set(priv, MT7530_LED_GPIO_DATA, bit);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT7530_LED_GPIO_DATA, bit);\n \telse\n-\t\tmt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);\n+\t\tregmap_clear_bits(priv-\u003eregmap, MT7530_LED_GPIO_DATA, bit);\n \n \treturn 0;\n }\n@@ -2201,8 +2162,11 @@ mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)\n {\n \tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n \tu32 bit = mt7530_gpio_to_bit(offset);\n+\tu32 val;\n+\n+\tregmap_read(priv-\u003eregmap, MT7530_LED_GPIO_DIR, \u0026val);\n \n-\treturn (mt7530_read(priv, MT7530_LED_GPIO_DIR) \u0026 bit) ?\n+\treturn (val \u0026 bit) ?\n \t\tGPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;\n }\n \n@@ -2212,8 +2176,8 @@ mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)\n \tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n \tu32 bit = mt7530_gpio_to_bit(offset);\n \n-\tmt7530_clear(priv, MT7530_LED_GPIO_OE, bit);\n-\tmt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);\n+\tregmap_clear_bits(priv-\u003eregmap, MT7530_LED_GPIO_OE, bit);\n+\tregmap_clear_bits(priv-\u003eregmap, MT7530_LED_GPIO_DIR, bit);\n \n \treturn 0;\n }\n@@ -2224,14 +2188,14 @@ mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int valu\n \tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n \tu32 bit = mt7530_gpio_to_bit(offset);\n \n-\tmt7530_set(priv, MT7530_LED_GPIO_DIR, bit);\n+\tregmap_set_bits(priv-\u003eregmap, MT7530_LED_GPIO_DIR, bit);\n \n \tif (value)\n-\t\tmt7530_set(priv, MT7530_LED_GPIO_DATA, bit);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT7530_LED_GPIO_DATA, bit);\n \telse\n-\t\tmt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);\n+\t\tregmap_clear_bits(priv-\u003eregmap, MT7530_LED_GPIO_DATA, bit);\n \n-\tmt7530_set(priv, MT7530_LED_GPIO_OE, bit);\n+\tregmap_set_bits(priv-\u003eregmap, MT7530_LED_GPIO_OE, bit);\n \n \treturn 0;\n }\n@@ -2246,9 +2210,9 @@ mt7530_setup_gpio(struct mt7530_priv *priv)\n \tif (!gc)\n \t\treturn -ENOMEM;\n \n-\tmt7530_write(priv, MT7530_LED_GPIO_OE, 0);\n-\tmt7530_write(priv, MT7530_LED_GPIO_DIR, 0);\n-\tmt7530_write(priv, MT7530_LED_IO_MODE, 0);\n+\tregmap_write(priv-\u003eregmap, MT7530_LED_GPIO_OE, 0);\n+\tregmap_write(priv-\u003eregmap, MT7530_LED_GPIO_DIR, 0);\n+\tregmap_write(priv-\u003eregmap, MT7530_LED_IO_MODE, 0);\n \n \tgc-\u003elabel = \"mt7530\";\n \tgc-\u003eparent = dev;\n@@ -2337,7 +2301,8 @@ mt7530_setup_irq(struct mt7530_priv *priv)\n \n \t/* This register must be set for MT7530 to properly fire interrupts */\n \tif (priv-\u003eid == ID_MT7530 || priv-\u003eid == ID_MT7621)\n-\t\tmt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT7530_TOP_SIG_CTRL,\n+\t\t\t\tTOP_SIG_CTRL_NORMAL);\n \n \tret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev),\n \t\t\t\t\t priv-\u003eregmap, irq,\n@@ -2485,15 +2450,15 @@ mt7530_setup(struct dsa_switch *ds)\n \n \t/* Waiting for MT7530 got to stable */\n \tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT753X_TRAP);\n-\tret = readx_poll_timeout(_mt7530_read, \u0026p, val, val != 0,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val, val != 0,\n \t\t\t\t 20, 1000000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"reset timeout\\n\");\n \t\treturn ret;\n \t}\n \n-\tid = mt7530_read(priv, MT7530_CREV);\n-\tid \u003e\u003e= CHIP_NAME_SHIFT;\n+\tregmap_read(priv-\u003eregmap, MT7530_CREV, \u0026id);\n+\tid = FIELD_GET(CHIP_NAME_MASK, id);\n \tif (id != MT7530_ID) {\n \t\tdev_err(priv-\u003edev, \"chip %x can't be supported\\n\", id);\n \t\treturn -ENODEV;\n@@ -2506,24 +2471,24 @@ mt7530_setup(struct dsa_switch *ds)\n \t}\n \n \t/* Reset the switch through internal reset */\n-\tmt7530_write(priv, MT7530_SYS_CTRL,\n-\t\t SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |\n-\t\t SYS_CTRL_REG_RST);\n+\tregmap_write(priv-\u003eregmap, MT7530_SYS_CTRL,\n+\t\t SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);\n \n \t/* Lower Tx driving for TRGMII path */\n \tfor (i = 0; i \u003c NUM_TRGMII_CTRL; i++)\n-\t\tmt7530_write(priv, MT7530_TRGMII_TD_ODT(i),\n+\t\tregmap_write(priv-\u003eregmap, MT7530_TRGMII_TD_ODT(i),\n \t\t\t TD_DM_DRVP(8) | TD_DM_DRVN(8));\n \n \tfor (i = 0; i \u003c NUM_TRGMII_CTRL; i++)\n-\t\tmt7530_rmw(priv, MT7530_TRGMII_RD(i),\n-\t\t\t RD_TAP_MASK, RD_TAP(16));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_TRGMII_RD(i),\n+\t\t\t\t RD_TAP_MASK, RD_TAP(16));\n \n \t/* Allow modifying the trap and directly access PHY registers via the\n \t * MDIO bus the switch is on.\n \t */\n-\tmt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |\n-\t\t MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);\n+\tregmap_update_bits(priv-\u003eregmap, MT753X_MTRAP,\n+\t\t\t MT7530_CHG_TRAP | MT7530_PHY_INDIRECT_ACCESS,\n+\t\t\t MT7530_CHG_TRAP);\n \n \tif ((val \u0026 MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)\n \t\tmt7530_pll_setup(priv);\n@@ -2537,17 +2502,16 @@ mt7530_setup(struct dsa_switch *ds)\n \t\t/* Clear link settings and enable force mode to force link down\n \t\t * on all ports until they're enabled later.\n \t\t */\n-\t\tmt7530_rmw(priv, MT753X_PMCR_P(i),\n-\t\t\t PMCR_LINK_SETTINGS_MASK |\n-\t\t\t MT753X_FORCE_MODE(priv-\u003eid),\n-\t\t\t MT753X_FORCE_MODE(priv-\u003eid));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT753X_PMCR_P(i),\n+\t\t\t\t PMCR_LINK_SETTINGS_MASK | MT753X_FORCE_MODE(priv-\u003eid),\n+\t\t\t\t MT753X_FORCE_MODE(priv-\u003eid));\n \n \t\t/* Disable forwarding by default on all ports */\n-\t\tmt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,\n-\t\t\t PCR_MATRIX_CLR);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(i),\n+\t\t\t\t PCR_MATRIX_MASK, PCR_MATRIX_CLR);\n \n \t\t/* Disable learning by default on all ports */\n-\t\tmt7530_set(priv, MT7530_PSC_P(i), SA_DIS);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT7530_PSC_P(i), SA_DIS);\n \n \t\tif (dsa_is_cpu_port(ds, i)) {\n \t\t\tmt753x_cpu_port_enable(ds, i);\n@@ -2555,16 +2519,17 @@ mt7530_setup(struct dsa_switch *ds)\n \t\t\tmt7530_port_disable(ds, i);\n \n \t\t\t/* Set default PVID to 0 on all user ports */\n-\t\t\tmt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,\n-\t\t\t\t G0_PORT_VID_DEF);\n+\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(i),\n+\t\t\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n \t\t}\n \t\t/* Enable consistent egress tag */\n-\t\tmt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,\n-\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(i),\n+\t\t\t\t PVC_EG_TAG_MASK,\n+\t\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));\n \t}\n \n \t/* Allow mirroring frames received on the local port (monitor port). */\n-\tmt7530_set(priv, MT753X_AGC, LOCAL_EN);\n+\tregmap_set_bits(priv-\u003eregmap, MT753X_AGC, LOCAL_EN);\n \n \t/* Setup VLAN ID 0 for VLAN-unaware bridges */\n \tret = mt7530_setup_vlan0(priv);\n@@ -2611,7 +2576,8 @@ mt7530_setup(struct dsa_switch *ds)\n \n \t\tif (priv-\u003ep5_mode == MUX_PHY_P0 ||\n \t\t priv-\u003ep5_mode == MUX_PHY_P4) {\n-\t\t\tmt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);\n+\t\t\tregmap_clear_bits(priv-\u003eregmap, MT753X_MTRAP,\n+\t\t\t\t\t MT7530_P5_DIS);\n \t\t\tmt7530_setup_port5(ds, interface);\n \t\t}\n \t}\n@@ -2650,26 +2616,26 @@ mt7531_setup_common(struct dsa_switch *ds)\n \tmt7530_mib_reset(ds);\n \n \t/* Disable flooding on all ports */\n-\tmt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |\n-\t\t UNU_FFP_MASK);\n+\tregmap_clear_bits(priv-\u003eregmap, MT753X_MFC,\n+\t\t\t BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK);\n \n \tfor (i = 0; i \u003c priv-\u003eds-\u003enum_ports; i++) {\n \t\t/* Clear link settings and enable force mode to force link down\n \t\t * on all ports until they're enabled later.\n \t\t */\n-\t\tmt7530_rmw(priv, MT753X_PMCR_P(i),\n-\t\t\t PMCR_LINK_SETTINGS_MASK |\n-\t\t\t MT753X_FORCE_MODE(priv-\u003eid),\n-\t\t\t MT753X_FORCE_MODE(priv-\u003eid));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT753X_PMCR_P(i),\n+\t\t\t\t PMCR_LINK_SETTINGS_MASK | MT753X_FORCE_MODE(priv-\u003eid),\n+\t\t\t\t MT753X_FORCE_MODE(priv-\u003eid));\n \n \t\t/* Disable forwarding by default on all ports */\n-\t\tmt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,\n-\t\t\t PCR_MATRIX_CLR);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(i),\n+\t\t\t\t PCR_MATRIX_MASK, PCR_MATRIX_CLR);\n \n \t\t/* Disable learning by default on all ports */\n-\t\tmt7530_set(priv, MT7530_PSC_P(i), SA_DIS);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT7530_PSC_P(i), SA_DIS);\n \n-\t\tmt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT7531_DBG_CNT(i),\n+\t\t\t\tMT7531_DIS_CLR);\n \n \t\tif (dsa_is_cpu_port(ds, i)) {\n \t\t\tmt753x_cpu_port_enable(ds, i);\n@@ -2677,21 +2643,22 @@ mt7531_setup_common(struct dsa_switch *ds)\n \t\t\tmt7530_port_disable(ds, i);\n \n \t\t\t/* Set default PVID to 0 on all user ports */\n-\t\t\tmt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,\n-\t\t\t\t G0_PORT_VID_DEF);\n+\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(i),\n+\t\t\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n \t\t}\n \n \t\t/* Enable consistent egress tag */\n-\t\tmt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,\n-\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(i),\n+\t\t\t\t PVC_EG_TAG_MASK,\n+\t\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));\n \t}\n \n \t/* Allow mirroring frames received on the local port (monitor port). */\n-\tmt7530_set(priv, MT753X_AGC, LOCAL_EN);\n+\tregmap_set_bits(priv-\u003eregmap, MT753X_AGC, LOCAL_EN);\n \n \t/* Enable Special Tag for rx frames */\n \tif (priv-\u003eid == ID_EN7581 || priv-\u003eid == ID_AN7583)\n-\t\tmt7530_write(priv, MT753X_CPORT_SPTAG_CFG,\n+\t\tregmap_write(priv-\u003eregmap, MT753X_CPORT_SPTAG_CFG,\n \t\t\t CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN);\n \n \t/* Flush the FDB table */\n@@ -2726,15 +2693,15 @@ mt7531_setup(struct dsa_switch *ds)\n \n \t/* Waiting for MT7530 got to stable */\n \tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT753X_TRAP);\n-\tret = readx_poll_timeout(_mt7530_read, \u0026p, val, val != 0,\n+\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val, val != 0,\n \t\t\t\t 20, 1000000);\n \tif (ret \u003c 0) {\n \t\tdev_err(priv-\u003edev, \"reset timeout\\n\");\n \t\treturn ret;\n \t}\n \n-\tid = mt7530_read(priv, MT7531_CREV);\n-\tid \u003e\u003e= CHIP_NAME_SHIFT;\n+\tregmap_read(priv-\u003eregmap, MT7531_CREV, \u0026id);\n+\tid = FIELD_GET(CHIP_NAME_MASK, id);\n \n \tif (id != MT7531_ID) {\n \t\tdev_err(priv-\u003edev, \"chip %x can't be supported\\n\", id);\n@@ -2744,15 +2711,17 @@ mt7531_setup(struct dsa_switch *ds)\n \t/* MT7531AE has got two SGMII units. One for port 5, one for port 6.\n \t * MT7531BE has got only one SGMII unit which is for port 6.\n \t */\n-\tval = mt7530_read(priv, MT7531_TOP_SIG_SR);\n+\tregmap_read(priv-\u003eregmap, MT7531_TOP_SIG_SR, \u0026val);\n \tpriv-\u003ep5_sgmii = !!(val \u0026 PAD_DUAL_SGMII_EN);\n \n \t/* Force link down on all ports before internal reset */\n \tfor (i = 0; i \u003c priv-\u003eds-\u003enum_ports; i++)\n-\t\tmt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);\n+\t\tregmap_write(priv-\u003eregmap, MT753X_PMCR_P(i),\n+\t\t\t MT7531_FORCE_MODE_LNK);\n \n \t/* Reset the switch through internal reset */\n-\tmt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);\n+\tregmap_write(priv-\u003eregmap, MT7530_SYS_CTRL,\n+\t\t SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);\n \n \tif (!priv-\u003ep5_sgmii) {\n \t\tmt7531_pll_setup(priv);\n@@ -2761,14 +2730,16 @@ mt7531_setup(struct dsa_switch *ds)\n \t\t * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO\n \t\t * to expose the MDIO bus of the switch.\n \t\t */\n-\t\tmt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,\n-\t\t\t MT7531_EXT_P_MDC_11);\n-\t\tmt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,\n-\t\t\t MT7531_EXT_P_MDIO_12);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7531_GPIO_MODE1,\n+\t\t\t\t MT7531_GPIO11_RG_RXD2_MASK,\n+\t\t\t\t MT7531_EXT_P_MDC_11);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7531_GPIO_MODE1,\n+\t\t\t\t MT7531_GPIO12_RG_RXD3_MASK,\n+\t\t\t\t MT7531_EXT_P_MDIO_12);\n \t}\n \n-\tmt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,\n-\t\t MT7531_GPIO0_INTERRUPT);\n+\tregmap_update_bits(priv-\u003eregmap, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,\n+\t\t\t MT7531_GPIO0_INTERRUPT);\n \n \t/* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since\n \t * phy_device has not yet been created provided for\n@@ -2930,7 +2901,7 @@ static void mt7531_rgmii_setup(struct mt7530_priv *priv,\n {\n \tu32 val;\n \n-\tval = mt7530_read(priv, MT7531_CLKGEN_CTRL);\n+\tregmap_read(priv-\u003eregmap, MT7531_CLKGEN_CTRL, \u0026val);\n \tval |= GP_CLK_EN;\n \tval \u0026= ~GP_MODE_MASK;\n \tval |= GP_MODE(MT7531_GP_MODE_RGMII);\n@@ -2961,7 +2932,7 @@ static void mt7531_rgmii_setup(struct mt7530_priv *priv,\n \t\t}\n \t}\n \n-\tmt7530_write(priv, MT7531_CLKGEN_CTRL, val);\n+\tregmap_write(priv-\u003eregmap, MT7531_CLKGEN_CTRL, val);\n }\n \n static void\n@@ -3014,7 +2985,8 @@ mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode,\n \n \t/* Are we connected to external phy */\n \tif (port == 5 \u0026\u0026 dsa_is_user_port(ds, 5))\n-\t\tmt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);\n+\t\tregmap_set_bits(priv-\u003eregmap, MT753X_PMCR_P(port),\n+\t\t\t\tPMCR_EXT_PHY);\n }\n \n static void mt753x_phylink_mac_link_down(struct phylink_config *config,\n@@ -3024,7 +2996,8 @@ static void mt753x_phylink_mac_link_down(struct phylink_config *config,\n \tstruct dsa_port *dp = dsa_phylink_to_port(config);\n \tstruct mt7530_priv *priv = dp-\u003eds-\u003epriv;\n \n-\tmt7530_clear(priv, MT753X_PMCR_P(dp-\u003eindex), PMCR_LINK_SETTINGS_MASK);\n+\tregmap_clear_bits(priv-\u003eregmap, MT753X_PMCR_P(dp-\u003eindex),\n+\t\t\t PMCR_LINK_SETTINGS_MASK);\n }\n \n static void mt753x_phylink_mac_link_up(struct phylink_config *config,\n@@ -3058,7 +3031,7 @@ static void mt753x_phylink_mac_link_up(struct phylink_config *config,\n \t\t\tmcr |= PMCR_FORCE_RX_FC_EN;\n \t}\n \n-\tmt7530_set(priv, MT753X_PMCR_P(dp-\u003eindex), mcr);\n+\tregmap_set_bits(priv-\u003eregmap, MT753X_PMCR_P(dp-\u003eindex), mcr);\n }\n \n static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config)\n@@ -3066,8 +3039,8 @@ static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config)\n \tstruct dsa_port *dp = dsa_phylink_to_port(config);\n \tstruct mt7530_priv *priv = dp-\u003eds-\u003epriv;\n \n-\tmt7530_clear(priv, MT753X_PMCR_P(dp-\u003eindex),\n-\t\t PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100);\n+\tregmap_clear_bits(priv-\u003eregmap, MT753X_PMCR_P(dp-\u003eindex),\n+\t\t\t PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100);\n }\n \n static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config,\n@@ -3088,11 +3061,11 @@ static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config,\n \telse\n \t\tval = LPI_THRESH_MASK;\n \n-\tmt7530_rmw(priv, MT753X_PMEEECR_P(dp-\u003eindex),\n-\t\t LPI_THRESH_MASK | LPI_MODE_EN, val);\n+\tregmap_update_bits(priv-\u003eregmap, MT753X_PMEEECR_P(dp-\u003eindex),\n+\t\t\t LPI_THRESH_MASK | LPI_MODE_EN, val);\n \n-\tmt7530_set(priv, MT753X_PMCR_P(dp-\u003eindex),\n-\t\t PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100);\n+\tregmap_set_bits(priv-\u003eregmap, MT753X_PMCR_P(dp-\u003eindex),\n+\t\t\tPMCR_FORCE_EEE1G | PMCR_FORCE_EEE100);\n \n \treturn 0;\n }\n@@ -3107,7 +3080,7 @@ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,\n \n \tconfig-\u003elpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD;\n \n-\teeecr = mt7530_read(priv, MT753X_PMEEECR_P(port));\n+\tregmap_read(priv-\u003eregmap, MT753X_PMEEECR_P(port), \u0026eeecr);\n \t/* tx_lpi_timer should be in microseconds. The time units for\n \t * LPI threshold are unspecified.\n \t */\n@@ -3135,7 +3108,7 @@ static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,\n \tint port = pcs_to_mt753x_pcs(pcs)-\u003eport;\n \tu32 pmsr;\n \n-\tpmsr = mt7530_read(priv, MT7530_PMSR_P(port));\n+\tregmap_read(priv-\u003eregmap, MT7530_PMSR_P(port), \u0026pmsr);\n \n \tstate-\u003elink = (pmsr \u0026 PMSR_LINK);\n \tstate-\u003ean_complete = state-\u003elink;\n@@ -3240,6 +3213,43 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,\n \treturn 0;\n }\n \n+static int\n+mt753x_port_change_conduit(struct dsa_switch *ds, int port,\n+\t\t\t struct net_device *conduit,\n+\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tstruct dsa_port *new_cpu_dp = conduit-\u003edsa_ptr;\n+\tstruct dsa_port *dp = dsa_to_port(ds, port);\n+\tstruct mt7530_priv *priv = ds-\u003epriv;\n+\n+\tif (priv-\u003eid != ID_MT7531) {\n+\t\tNL_SET_ERR_MSG_MOD(extack,\n+\t\t\t\t \"Changing DSA conduit is only supported on MT7531\");\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\tif (new_cpu_dp-\u003eds != ds) {\n+\t\tNL_SET_ERR_MSG_MOD(extack,\n+\t\t\t\t \"Cannot assign a conduit on a different switch\");\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\n+\t/* dp-\u003ecpu_dp still points to the old CPU port */\n+\tpriv-\u003eports[port].pm \u0026= ~PCR_MATRIX(BIT(dp-\u003ecpu_dp-\u003eindex));\n+\tpriv-\u003eports[port].pm |= PCR_MATRIX(BIT(new_cpu_dp-\u003eindex));\n+\tif (priv-\u003eports[port].enable)\n+\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n+\t\t\t\t PCR_MATRIX_MASK, priv-\u003eports[port].pm);\n+\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+\n+\tmt7530_port_fast_age(ds, port);\n+\n+\treturn 0;\n+}\n+\n static void\n mt753x_conduit_state_change(struct dsa_switch *ds,\n \t\t\t const struct net_device *conduit,\n@@ -3269,7 +3279,8 @@ mt753x_conduit_state_change(struct dsa_switch *ds,\n \t\t MT7530_CPU_PORT(__ffs(priv-\u003eactive_cpu_ports));\n \t}\n \n-\tmt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);\n+\tregmap_update_bits(priv-\u003eregmap, MT753X_MFC,\n+\t\t\t MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);\n }\n \n static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port,\n@@ -3286,8 +3297,8 @@ static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port,\n \tcase TC_TBF_DESTROY: {\n \t\tu32 val, tick;\n \n-\t\tmt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK,\n-\t\t\t EGR_BC_CRC_IPG_PREAMBLE);\n+\t\tregmap_update_bits(priv-\u003eregmap, MT753X_GERLCR, EGR_BC_MASK,\n+\t\t\t\t EGR_BC_CRC_IPG_PREAMBLE);\n \n \t\t/* if rate is greater than 10Mbps tick is 1/32 ms,\n \t\t * 1ms otherwise\n@@ -3298,7 +3309,7 @@ static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port,\n \t\t FIELD_PREP(ERLCR_EXP_MASK, tick) |\n \t\t ERLCR_TBF_MODE_MASK |\n \t\t FIELD_PREP(ERLCR_MANT_MASK, 0xf);\n-\t\tmt7530_write(priv, MT753X_ERLCR_P(port), val);\n+\t\tregmap_write(priv-\u003eregmap, MT753X_ERLCR_P(port), val);\n \t\tbreak;\n \t}\n \tdefault:\n@@ -3331,16 +3342,16 @@ static int mt7988_setup(struct dsa_switch *ds)\n \n \t/* AN7583 require additional tweak to CONN_CFG */\n \tif (priv-\u003eid == ID_AN7583)\n-\t\tmt7530_rmw(priv, AN7583_GEPHY_CONN_CFG,\n-\t\t\t AN7583_CSR_DPHY_CKIN_SEL |\n-\t\t\t AN7583_CSR_PHY_CORE_REG_CLK_SEL |\n-\t\t\t AN7583_CSR_ETHER_AFE_PWD,\n-\t\t\t AN7583_CSR_DPHY_CKIN_SEL |\n-\t\t\t AN7583_CSR_PHY_CORE_REG_CLK_SEL |\n-\t\t\t FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0));\n+\t\tregmap_update_bits(priv-\u003eregmap, AN7583_GEPHY_CONN_CFG,\n+\t\t\t\t AN7583_CSR_DPHY_CKIN_SEL |\n+\t\t\t\t AN7583_CSR_PHY_CORE_REG_CLK_SEL |\n+\t\t\t\t AN7583_CSR_ETHER_AFE_PWD,\n+\t\t\t\t AN7583_CSR_DPHY_CKIN_SEL |\n+\t\t\t\t AN7583_CSR_PHY_CORE_REG_CLK_SEL |\n+\t\t\t\t FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0));\n \n \t/* Reset the switch PHYs */\n-\tmt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);\n+\tregmap_write(priv-\u003eregmap, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);\n \n \treturn mt7531_setup_common(ds);\n }\n@@ -3350,6 +3361,7 @@ static const struct dsa_switch_ops mt7530_switch_ops = {\n \t.setup\t\t\t= mt753x_setup,\n \t.teardown\t\t= mt753x_teardown,\n \t.preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port,\n+\t.port_change_conduit\t= mt753x_port_change_conduit,\n \t.get_strings\t\t= mt7530_get_strings,\n \t.get_ethtool_stats\t= mt7530_get_ethtool_stats,\n \t.get_sset_count\t\t= mt7530_get_sset_count,\n@@ -3367,6 +3379,7 @@ static const struct dsa_switch_ops mt7530_switch_ops = {\n \t.port_bridge_flags\t= mt7530_port_bridge_flags,\n \t.port_bridge_join\t= mt7530_port_bridge_join,\n \t.port_bridge_leave\t= mt7530_port_bridge_leave,\n+\t.port_fast_age\t\t= mt7530_port_fast_age,\n \t.port_fdb_add\t\t= mt7530_port_fdb_add,\n \t.port_fdb_del\t\t= mt7530_port_fdb_del,\n \t.port_fdb_dump\t\t= mt7530_port_fdb_dump,\ndiff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h\nindex dd33b0df3419e3..241e3d4603577f 100644\n--- a/drivers/net/dsa/mt7530.h\n+++ b/drivers/net/dsa/mt7530.h\n@@ -6,6 +6,8 @@\n #ifndef __MT7530_H\n #define __MT7530_H\n \n+#include \u003clinux/bitfield.h\u003e\n+\n #define MT7530_NUM_PORTS\t\t7\n #define MT7530_NUM_PHYS\t\t\t5\n #define MT7530_NUM_FDB_RECORDS\t\t2048\n@@ -146,20 +148,24 @@ enum mt753x_to_cpu_fw {\n #define STATIC_ENT\t\t\t3\n #define MT7530_ATA2\t\t\t0x78\n #define ATA2_IVL\t\t\tBIT(15)\n-#define ATA2_FID(x)\t\t\t(((x) \u0026 0x7) \u003c\u003c 12)\n+#define ATA2_FID_MASK\t\t\tGENMASK(14, 12)\n+#define ATA2_FID(x)\t\t\tFIELD_PREP(ATA2_FID_MASK, x)\n \n /* Register for address table write data */\n #define MT7530_ATWD\t\t\t0x7c\n \n /* Register for address table control */\n #define MT7530_ATC\t\t\t0x80\n-#define ATC_HASH\t\t\t(((x) \u0026 0xfff) \u003c\u003c 16)\n+#define ATC_HASH_MASK\t\t\tGENMASK(27, 16)\n+#define ATC_HASH(x)\t\t\tFIELD_PREP(ATC_HASH_MASK, x)\n #define ATC_BUSY\t\t\tBIT(15)\n #define ATC_SRCH_END\t\t\tBIT(14)\n #define ATC_SRCH_HIT\t\t\tBIT(13)\n #define ATC_INVALID\t\t\tBIT(12)\n-#define ATC_MAT(x)\t\t\t(((x) \u0026 0xf) \u003c\u003c 8)\n+#define ATC_MAT_MASK\t\t\tGENMASK(11, 8)\n+#define ATC_MAT(x)\t\t\tFIELD_PREP(ATC_MAT_MASK, x)\n #define ATC_MAT_MACTAB\t\t\tATC_MAT(0)\n+#define ATC_MAT_NON_STATIC_MAC\t\tATC_MAT(4)\n \n enum mt7530_fdb_cmd {\n \tMT7530_FDB_READ\t= 0,\n@@ -171,32 +177,29 @@ enum mt7530_fdb_cmd {\n \n /* Registers for table search read address */\n #define MT7530_TSRA1\t\t\t0x84\n-#define MAC_BYTE_0\t\t\t24\n-#define MAC_BYTE_1\t\t\t16\n-#define MAC_BYTE_2\t\t\t8\n-#define MAC_BYTE_3\t\t\t0\n-#define MAC_BYTE_MASK\t\t\t0xff\n+#define MAC_BYTE_0_MASK\t\tGENMASK(31, 24)\n+#define MAC_BYTE_1_MASK\t\tGENMASK(23, 16)\n+#define MAC_BYTE_2_MASK\t\tGENMASK(15, 8)\n+#define MAC_BYTE_3_MASK\t\tGENMASK(7, 0)\n \n #define MT7530_TSRA2\t\t\t0x88\n-#define MAC_BYTE_4\t\t\t24\n-#define MAC_BYTE_5\t\t\t16\n-#define CVID\t\t\t\t0\n-#define CVID_MASK\t\t\t0xfff\n+#define MAC_BYTE_4_MASK\t\tGENMASK(31, 24)\n+#define MAC_BYTE_5_MASK\t\tGENMASK(23, 16)\n+#define CVID_MASK\t\t\tGENMASK(11, 0)\n \n #define MT7530_ATRD\t\t\t0x8C\n-#define\t AGE_TIMER\t\t\t24\n-#define AGE_TIMER_MASK\t\t\t0xff\n-#define PORT_MAP\t\t\t4\n-#define PORT_MAP_MASK\t\t\t0xff\n-#define ENT_STATUS\t\t\t2\n-#define ENT_STATUS_MASK\t\t0x3\n+#define AGE_TIMER_MASK\t\t\tGENMASK(31, 24)\n+#define PORT_MAP_MASK\t\t\tGENMASK(11, 4)\n+#define ENT_STATUS_MASK\t\tGENMASK(3, 2)\n \n /* Register for vlan table control */\n #define MT7530_VTCR\t\t\t0x90\n #define VTCR_BUSY\t\t\tBIT(31)\n #define VTCR_INVALID\t\t\tBIT(16)\n-#define VTCR_FUNC(x)\t\t\t(((x) \u0026 0xf) \u003c\u003c 12)\n-#define VTCR_VID\t\t\t((x) \u0026 0xfff)\n+#define VTCR_FUNC_MASK\t\t\tGENMASK(15, 12)\n+#define VTCR_FUNC(x)\t\t\tFIELD_PREP(VTCR_FUNC_MASK, x)\n+#define VTCR_VID_MASK\t\t\tGENMASK(11, 0)\n+#define VTCR_VID(x)\t\t\tFIELD_PREP(VTCR_VID_MASK, x)\n \n enum mt7530_vlan_cmd {\n \t/* Read/Write the specified VID entry from VAWD register based\n@@ -216,13 +219,13 @@ enum mt7530_vlan_cmd {\n /* Per VLAN Egress Tag Control */\n #define VTAG_EN\t\t\tBIT(28)\n /* VLAN Member Control */\n-#define PORT_MEM(x)\t\t\t(((x) \u0026 0xff) \u003c\u003c 16)\n+#define PORT_MEM_MASK\t\t\tGENMASK(23, 16)\n+#define PORT_MEM(x)\t\t\tFIELD_PREP(PORT_MEM_MASK, x)\n /* Filter ID */\n-#define FID(x)\t\t\t\t(((x) \u0026 0x7) \u003c\u003c 1)\n+#define FID_MASK\t\t\tGENMASK(3, 1)\n+#define FID(x)\t\t\t\tFIELD_PREP(FID_MASK, x)\n /* VLAN Entry Valid */\n #define VLAN_VALID\t\t\tBIT(0)\n-#define PORT_MEM_SHFT\t\t\t16\n-#define PORT_MEM_MASK\t\t\t0xff\n \n enum mt7530_fid {\n \tFID_STANDALONE = 0,\n@@ -247,11 +250,11 @@ enum mt7530_vlan_egress_attr {\n /* Age count */\n #define AGE_CNT_MASK\t\t\tGENMASK(19, 12)\n #define AGE_CNT_MAX\t\t\t0xff\n-#define AGE_CNT(x)\t\t\t(AGE_CNT_MASK \u0026 ((x) \u003c\u003c 12))\n+#define AGE_CNT(x)\t\t\tFIELD_PREP(AGE_CNT_MASK, x)\n /* Age unit */\n #define AGE_UNIT_MASK\t\t\tGENMASK(11, 0)\n #define AGE_UNIT_MAX\t\t\t0xfff\n-#define AGE_UNIT(x)\t\t\t(AGE_UNIT_MASK \u0026 (x))\n+#define AGE_UNIT(x)\t\t\tFIELD_PREP(AGE_UNIT_MASK, x)\n \n #define MT753X_ERLCR_P(x)\t\t(0x1040 + ((x) * 0x100))\n #define ERLCR_CIR_MASK\t\t\tGENMASK(31, 16)\n@@ -282,30 +285,31 @@ enum mt7530_stp_state {\n #define MT7530_PCR_P(x)\t\t\t(0x2004 + ((x) * 0x100))\n #define PORT_TX_MIR\t\t\tBIT(9)\n #define PORT_RX_MIR\t\t\tBIT(8)\n-#define PORT_VLAN(x)\t\t\t((x) \u0026 0x3)\n+#define PCR_PORT_VLAN_MASK\t\tGENMASK(1, 0)\n \n enum mt7530_port_mode {\n \t/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */\n-\tMT7530_PORT_MATRIX_MODE = PORT_VLAN(0),\n+\tMT7530_PORT_MATRIX_MODE = 0,\n \n \t/* Fallback Mode: Forward received frames with ingress ports that do\n \t * not belong to the VLAN member. Frames whose VID is not listed on\n \t * the VLAN table are forwarded by the PCR_MATRIX members.\n \t */\n-\tMT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),\n+\tMT7530_PORT_FALLBACK_MODE = 1,\n \n \t/* Security Mode: Discard any frame due to ingress membership\n \t * violation or VID missed on the VLAN table.\n \t */\n-\tMT7530_PORT_SECURITY_MODE = PORT_VLAN(3),\n+\tMT7530_PORT_SECURITY_MODE = 3,\n };\n \n-#define PCR_MATRIX(x)\t\t\t(((x) \u0026 0xff) \u003c\u003c 16)\n-#define PORT_PRI(x)\t\t\t(((x) \u0026 0x7) \u003c\u003c 24)\n-#define EG_TAG(x)\t\t\t(((x) \u0026 0x3) \u003c\u003c 28)\n-#define PCR_MATRIX_MASK\t\tPCR_MATRIX(0xff)\n+#define PCR_MATRIX_MASK\t\tGENMASK(23, 16)\n+#define PCR_MATRIX(x)\t\t\tFIELD_PREP(PCR_MATRIX_MASK, x)\n+#define PORT_PRI_MASK\t\t\tGENMASK(26, 24)\n+#define PORT_PRI(x)\t\t\tFIELD_PREP(PORT_PRI_MASK, x)\n+#define EG_TAG_MASK\t\t\tGENMASK(29, 28)\n+#define EG_TAG(x)\t\t\tFIELD_PREP(EG_TAG_MASK, x)\n #define PCR_MATRIX_CLR\t\t\tPCR_MATRIX(0)\n-#define PCR_PORT_VLAN_MASK\t\tPORT_VLAN(3)\n \n /* Register for port security control */\n #define MT7530_PSC_P(x)\t\t\t(0x200c + ((x) * 0x100))\n@@ -314,10 +318,10 @@ enum mt7530_port_mode {\n /* Register for port vlan control */\n #define MT7530_PVC_P(x)\t\t\t(0x2010 + ((x) * 0x100))\n #define PORT_SPEC_TAG\t\t\tBIT(5)\n-#define PVC_EG_TAG(x)\t\t\t(((x) \u0026 0x7) \u003c\u003c 8)\n-#define PVC_EG_TAG_MASK\t\tPVC_EG_TAG(7)\n-#define VLAN_ATTR(x)\t\t\t(((x) \u0026 0x3) \u003c\u003c 6)\n-#define VLAN_ATTR_MASK\t\t\tVLAN_ATTR(3)\n+#define PVC_EG_TAG_MASK\t\tGENMASK(10, 8)\n+#define PVC_EG_TAG(x)\t\t\tFIELD_PREP(PVC_EG_TAG_MASK, x)\n+#define VLAN_ATTR_MASK\t\t\tGENMASK(7, 6)\n+#define VLAN_ATTR(x)\t\t\tFIELD_PREP(VLAN_ATTR_MASK, x)\n #define ACC_FRM_MASK\t\t\tGENMASK(1, 0)\n \n enum mt7530_vlan_port_eg_tag {\n@@ -337,12 +341,13 @@ enum mt7530_vlan_port_acc_frm {\n \tMT7530_VLAN_ACC_UNTAGGED = 2,\n };\n \n-#define STAG_VPID\t\t\t(((x) \u0026 0xffff) \u003c\u003c 16)\n+#define STAG_VPID_MASK\t\t\tGENMASK(31, 16)\n+#define STAG_VPID(x)\t\t\tFIELD_PREP(STAG_VPID_MASK, x)\n \n /* Register for port port-and-protocol based vlan 1 control */\n #define MT7530_PPBV1_P(x)\t\t(0x2014 + ((x) * 0x100))\n-#define G0_PORT_VID(x)\t\t\t(((x) \u0026 0xfff) \u003c\u003c 0)\n-#define G0_PORT_VID_MASK\t\tG0_PORT_VID(0xfff)\n+#define G0_PORT_VID_MASK\t\tGENMASK(11, 0)\n+#define G0_PORT_VID(x)\t\t\tFIELD_PREP(G0_PORT_VID_MASK, x)\n #define G0_PORT_VID_DEF\t\tG0_PORT_VID(0)\n \n /* Register for port MAC control register */\n@@ -418,8 +423,8 @@ enum mt7530_vlan_port_acc_frm {\n #define MT7531_DIS_CLR\t\t\tBIT(31)\n \n #define MT7530_GMACCR\t\t\t0x30e0\n-#define MAX_RX_JUMBO(x)\t\t((x) \u003c\u003c 2)\n #define MAX_RX_JUMBO_MASK\t\tGENMASK(5, 2)\n+#define MAX_RX_JUMBO(x)\t\tFIELD_PREP(MAX_RX_JUMBO_MASK, x)\n #define MAX_RX_PKT_LEN_MASK\t\tGENMASK(1, 0)\n #define MAX_RX_PKT_LEN_1522\t\t0x0\n #define MAX_RX_PKT_LEN_1536\t\t0x1\n@@ -505,16 +510,16 @@ enum mt7530_vlan_port_acc_frm {\n /* Register for PHY Indirect Access Control */\n #define MT7531_PHY_IAC\t\t\t0x701C\n #define MT7531_PHY_ACS_ST\t\tBIT(31)\n-#define MT7531_MDIO_REG_ADDR_MASK\t(0x1f \u003c\u003c 25)\n-#define MT7531_MDIO_PHY_ADDR_MASK\t(0x1f \u003c\u003c 20)\n-#define MT7531_MDIO_CMD_MASK\t\t(0x3 \u003c\u003c 18)\n-#define MT7531_MDIO_ST_MASK\t\t(0x3 \u003c\u003c 16)\n-#define MT7531_MDIO_RW_DATA_MASK\t(0xffff)\n-#define MT7531_MDIO_REG_ADDR(x)\t(((x) \u0026 0x1f) \u003c\u003c 25)\n-#define MT7531_MDIO_DEV_ADDR(x)\t(((x) \u0026 0x1f) \u003c\u003c 25)\n-#define MT7531_MDIO_PHY_ADDR(x)\t(((x) \u0026 0x1f) \u003c\u003c 20)\n-#define MT7531_MDIO_CMD(x)\t\t(((x) \u0026 0x3) \u003c\u003c 18)\n-#define MT7531_MDIO_ST(x)\t\t(((x) \u0026 0x3) \u003c\u003c 16)\n+#define MT7531_MDIO_REG_ADDR_MASK\tGENMASK(29, 25)\n+#define MT7531_MDIO_PHY_ADDR_MASK\tGENMASK(24, 20)\n+#define MT7531_MDIO_CMD_MASK\t\tGENMASK(19, 18)\n+#define MT7531_MDIO_ST_MASK\t\tGENMASK(17, 16)\n+#define MT7531_MDIO_RW_DATA_MASK\tGENMASK(15, 0)\n+#define MT7531_MDIO_REG_ADDR(x)\tFIELD_PREP(MT7531_MDIO_REG_ADDR_MASK, x)\n+#define MT7531_MDIO_DEV_ADDR(x)\tFIELD_PREP(MT7531_MDIO_REG_ADDR_MASK, x)\n+#define MT7531_MDIO_PHY_ADDR(x)\tFIELD_PREP(MT7531_MDIO_PHY_ADDR_MASK, x)\n+#define MT7531_MDIO_CMD(x)\t\tFIELD_PREP(MT7531_MDIO_CMD_MASK, x)\n+#define MT7531_MDIO_ST(x)\t\tFIELD_PREP(MT7531_MDIO_ST_MASK, x)\n \n enum mt7531_phy_iac_cmd {\n \tMT7531_MDIO_ADDR = 0,\n@@ -542,14 +547,14 @@ enum mt7531_mdio_st {\n \n /* Register for RGMII clock phase */\n #define MT7531_CLKGEN_CTRL\t\t0x7500\n-#define CLK_SKEW_OUT(x)\t\t(((x) \u0026 0x3) \u003c\u003c 8)\n #define CLK_SKEW_OUT_MASK\t\tGENMASK(9, 8)\n-#define CLK_SKEW_IN(x)\t\t\t(((x) \u0026 0x3) \u003c\u003c 6)\n+#define CLK_SKEW_OUT(x)\t\tFIELD_PREP(CLK_SKEW_OUT_MASK, x)\n #define CLK_SKEW_IN_MASK\t\tGENMASK(7, 6)\n+#define CLK_SKEW_IN(x)\t\t\tFIELD_PREP(CLK_SKEW_IN_MASK, x)\n #define RXCLK_NO_DELAY\t\t\tBIT(5)\n #define TXCLK_NO_REVERSE\t\tBIT(4)\n-#define GP_MODE(x)\t\t\t(((x) \u0026 0x3) \u003c\u003c 1)\n #define GP_MODE_MASK\t\t\tGENMASK(2, 1)\n+#define GP_MODE(x)\t\t\tFIELD_PREP(GP_MODE_MASK, x)\n #define GP_CLK_EN\t\t\tBIT(0)\n \n enum mt7531_gp_mode {\n@@ -599,8 +604,10 @@ enum mt7531_xtal_fsel {\n #define PAD_MCM_SMI_EN\t\t\tBIT(0)\n \n #define MT7530_IO_DRV_CR\t\t0x7810\n-#define P5_IO_CLK_DRV(x)\t\t((x) \u0026 0x3)\n-#define P5_IO_DATA_DRV(x)\t\t(((x) \u0026 0x3) \u003c\u003c 4)\n+#define P5_IO_CLK_DRV_MASK\t\tGENMASK(1, 0)\n+#define P5_IO_CLK_DRV(x)\t\tFIELD_PREP(P5_IO_CLK_DRV_MASK, x)\n+#define P5_IO_DATA_DRV_MASK\t\tGENMASK(5, 4)\n+#define P5_IO_DATA_DRV(x)\t\tFIELD_PREP(P5_IO_DATA_DRV_MASK, x)\n \n #define MT7531_CHIP_REV\t\t\t0x781C\n \n@@ -610,15 +617,15 @@ enum mt7531_xtal_fsel {\n #define SW_PLLGP\t\t\tBIT(0)\n \n #define MT7530_P6ECR\t\t\t0x7830\n-#define P6_INTF_MODE_MASK\t\t0x3\n-#define P6_INTF_MODE(x)\t\t((x) \u0026 0x3)\n+#define P6_INTF_MODE_MASK\t\tGENMASK(1, 0)\n+#define P6_INTF_MODE(x)\t\tFIELD_PREP(P6_INTF_MODE_MASK, x)\n \n #define MT7531_PLLGP_CR0\t\t0x78a8\n #define RG_COREPLL_EN\t\t\tBIT(22)\n-#define RG_COREPLL_POSDIV_S\t\t23\n-#define RG_COREPLL_POSDIV_M\t\t0x3800000\n-#define RG_COREPLL_SDM_PCW_S\t\t1\n-#define RG_COREPLL_SDM_PCW_M\t\t0x3ffffe\n+#define RG_COREPLL_POSDIV_MASK\t\tGENMASK(25, 23)\n+#define RG_COREPLL_POSDIV(x)\t\tFIELD_PREP(RG_COREPLL_POSDIV_MASK, x)\n+#define RG_COREPLL_SDM_PCW_MASK\tGENMASK(21, 1)\n+#define RG_COREPLL_SDM_PCW(x)\t\tFIELD_PREP(RG_COREPLL_SDM_PCW_MASK, x)\n #define RG_COREPLL_SDM_PCW_CHG\t\tBIT(0)\n \n /* Registers for RGMII and SGMII PLL clock */\n@@ -629,10 +636,10 @@ enum mt7531_xtal_fsel {\n #define MT7530_TRGMII_RCK_CTRL\t\t0x7a00\n #define RX_RST\t\t\t\tBIT(31)\n #define RXC_DQSISEL\t\t\tBIT(30)\n-#define DQSI1_TAP_MASK\t\t\t(0x7f \u003c\u003c 8)\n-#define DQSI0_TAP_MASK\t\t\t0x7f\n-#define DQSI1_TAP(x)\t\t\t(((x) \u0026 0x7f) \u003c\u003c 8)\n-#define DQSI0_TAP(x)\t\t\t((x) \u0026 0x7f)\n+#define DQSI1_TAP_MASK\t\t\tGENMASK(14, 8)\n+#define DQSI0_TAP_MASK\t\t\tGENMASK(6, 0)\n+#define DQSI1_TAP(x)\t\t\tFIELD_PREP(DQSI1_TAP_MASK, x)\n+#define DQSI0_TAP(x)\t\t\tFIELD_PREP(DQSI0_TAP_MASK, x)\n \n #define MT7530_TRGMII_RCK_RTT\t\t0x7a04\n #define DQS1_GATE\t\t\tBIT(31)\n@@ -641,8 +648,8 @@ enum mt7531_xtal_fsel {\n #define MT7530_TRGMII_RD(x)\t\t(0x7a10 + (x) * 8)\n #define BSLIP_EN\t\t\tBIT(31)\n #define EDGE_CHK\t\t\tBIT(30)\n-#define RD_TAP_MASK\t\t\t0x7f\n-#define RD_TAP(x)\t\t\t((x) \u0026 0x7f)\n+#define RD_TAP_MASK\t\t\tGENMASK(6, 0)\n+#define RD_TAP(x)\t\t\tFIELD_PREP(RD_TAP_MASK, x)\n \n #define MT7530_TRGMII_TXCTRL\t\t0x7a40\n #define TRAIN_TXEN\t\t\tBIT(31)\n@@ -650,18 +657,23 @@ enum mt7531_xtal_fsel {\n #define TX_RST\t\t\t\tBIT(28)\n \n #define MT7530_TRGMII_TD_ODT(i)\t\t(0x7a54 + 8 * (i))\n-#define TD_DM_DRVP(x)\t\t\t((x) \u0026 0xf)\n-#define TD_DM_DRVN(x)\t\t\t(((x) \u0026 0xf) \u003c\u003c 4)\n+#define TD_DM_DRVP_MASK\t\tGENMASK(3, 0)\n+#define TD_DM_DRVP(x)\t\t\tFIELD_PREP(TD_DM_DRVP_MASK, x)\n+#define TD_DM_DRVN_MASK\t\tGENMASK(7, 4)\n+#define TD_DM_DRVN(x)\t\t\tFIELD_PREP(TD_DM_DRVN_MASK, x)\n \n #define MT7530_TRGMII_TCK_CTRL\t\t0x7a78\n-#define TCK_TAP(x)\t\t\t(((x) \u0026 0xf) \u003c\u003c 8)\n+#define TCK_TAP_MASK\t\t\tGENMASK(11, 8)\n+#define TCK_TAP(x)\t\t\tFIELD_PREP(TCK_TAP_MASK, x)\n \n #define MT7530_P5RGMIIRXCR\t\t0x7b00\n #define CSR_RGMII_EDGE_ALIGN\t\tBIT(8)\n-#define CSR_RGMII_RXC_0DEG_CFG(x)\t((x) \u0026 0xf)\n+#define CSR_RGMII_RXC_0DEG_CFG_MASK\tGENMASK(3, 0)\n+#define CSR_RGMII_RXC_0DEG_CFG(x)\tFIELD_PREP(CSR_RGMII_RXC_0DEG_CFG_MASK, x)\n \n #define MT7530_P5RGMIITXCR\t\t0x7b04\n-#define CSR_RGMII_TXC_CFG(x)\t\t((x) \u0026 0x1f)\n+#define CSR_RGMII_TXC_CFG_MASK\t\tGENMASK(4, 0)\n+#define CSR_RGMII_TXC_CFG(x)\t\tFIELD_PREP(CSR_RGMII_TXC_CFG_MASK, x)\n \n /* Registers for GPIO mode */\n #define MT7531_GPIO_MODE0\t\t0x7c0c\n@@ -670,9 +682,9 @@ enum mt7531_xtal_fsel {\n \n #define MT7531_GPIO_MODE1\t\t0x7c10\n #define MT7531_GPIO11_RG_RXD2_MASK\tGENMASK(15, 12)\n-#define MT7531_EXT_P_MDC_11\t\t(2 \u003c\u003c 12)\n+#define MT7531_EXT_P_MDC_11\t\tFIELD_PREP(MT7531_GPIO11_RG_RXD2_MASK, 2)\n #define MT7531_GPIO12_RG_RXD3_MASK\tGENMASK(19, 16)\n-#define MT7531_EXT_P_MDIO_12\t\t(2 \u003c\u003c 16)\n+#define MT7531_EXT_P_MDIO_12\t\tFIELD_PREP(MT7531_GPIO12_RG_RXD3_MASK, 2)\n \n #define MT753X_CPORT_SPTAG_CFG\t\t0x7c10\n #define CPORT_SW2FE_STAG_EN\t\tBIT(1)\n@@ -704,7 +716,7 @@ enum mt7531_xtal_fsel {\n #define MT7530_LED_GPIO_DATA\t\t0x7d18\n \n #define MT7530_CREV\t\t\t0x7ffc\n-#define CHIP_NAME_SHIFT\t\t16\n+#define CHIP_NAME_MASK\t\t\tGENMASK(31, 16)\n #define MT7530_ID\t\t\t0x7530\n \n #define MT7531_CREV\t\t\t0x781C\n@@ -716,10 +728,13 @@ enum mt7531_xtal_fsel {\n #define RG_SYSPLL_EN_NORMAL\t\tBIT(15)\n #define RG_SYSPLL_VODEN\t\tBIT(14)\n #define RG_SYSPLL_LF\t\t\tBIT(13)\n-#define RG_SYSPLL_RST_DLY(x)\t\t(((x) \u0026 0x3) \u003c\u003c 12)\n+#define RG_SYSPLL_RST_DLY_MASK\t\tGENMASK(13, 12)\n+#define RG_SYSPLL_RST_DLY(x)\t\tFIELD_PREP(RG_SYSPLL_RST_DLY_MASK, x)\n #define RG_SYSPLL_LVROD_EN\t\tBIT(10)\n-#define RG_SYSPLL_PREDIV(x)\t\t(((x) \u0026 0x3) \u003c\u003c 8)\n-#define RG_SYSPLL_POSDIV(x)\t\t(((x) \u0026 0x3) \u003c\u003c 5)\n+#define RG_SYSPLL_PREDIV_MASK\t\tGENMASK(9, 8)\n+#define RG_SYSPLL_PREDIV(x)\t\tFIELD_PREP(RG_SYSPLL_PREDIV_MASK, x)\n+#define RG_SYSPLL_POSDIV_MASK\t\tGENMASK(6, 5)\n+#define RG_SYSPLL_POSDIV(x)\t\tFIELD_PREP(RG_SYSPLL_POSDIV_MASK, x)\n #define RG_SYSPLL_FBKSEL\t\tBIT(4)\n #define RT_SYSPLL_EN_AFE_OLT\t\tBIT(0)\n \n@@ -731,38 +746,48 @@ enum mt7531_xtal_fsel {\n #define MT7531_PHY_PLL_OFF\t\tBIT(5)\n #define MT7531_PHY_PLL_BYPASS_MODE\tBIT(4)\n \n-#define MT753X_CTRL_PHY_ADDR(addr)\t((addr + 1) \u0026 0x1f)\n+#define MT753X_CTRL_PHY_ADDR(addr)\t(((addr) + 1) \u0026 (PHY_MAX_ADDR - 1))\n \n #define CORE_PLL_GROUP5\t\t\t0x404\n-#define RG_LCDDS_PCW_NCPO1(x)\t\t((x) \u0026 0xffff)\n+#define RG_LCDDS_PCW_NCPO1_MASK\tGENMASK(15, 0)\n+#define RG_LCDDS_PCW_NCPO1(x)\t\tFIELD_PREP(RG_LCDDS_PCW_NCPO1_MASK, x)\n \n #define CORE_PLL_GROUP6\t\t\t0x405\n-#define RG_LCDDS_PCW_NCPO0(x)\t\t((x) \u0026 0xffff)\n+#define RG_LCDDS_PCW_NCPO0_MASK\tGENMASK(15, 0)\n+#define RG_LCDDS_PCW_NCPO0(x)\t\tFIELD_PREP(RG_LCDDS_PCW_NCPO0_MASK, x)\n \n #define CORE_PLL_GROUP7\t\t\t0x406\n #define RG_LCDDS_PWDB\t\t\tBIT(15)\n #define RG_LCDDS_ISO_EN\t\tBIT(13)\n-#define RG_LCCDS_C(x)\t\t\t(((x) \u0026 0x7) \u003c\u003c 4)\n+#define RG_LCCDS_C_MASK\t\tGENMASK(6, 4)\n+#define RG_LCCDS_C(x)\t\t\tFIELD_PREP(RG_LCCDS_C_MASK, x)\n #define RG_LCDDS_PCW_NCPO_CHG\t\tBIT(3)\n \n #define CORE_PLL_GROUP10\t\t0x409\n-#define RG_LCDDS_SSC_DELTA(x)\t\t((x) \u0026 0xfff)\n+#define RG_LCDDS_SSC_DELTA_MASK\tGENMASK(11, 0)\n+#define RG_LCDDS_SSC_DELTA(x)\t\tFIELD_PREP(RG_LCDDS_SSC_DELTA_MASK, x)\n \n #define CORE_PLL_GROUP11\t\t0x40a\n-#define RG_LCDDS_SSC_DELTA1(x)\t\t((x) \u0026 0xfff)\n+#define RG_LCDDS_SSC_DELTA1_MASK\tGENMASK(11, 0)\n+#define RG_LCDDS_SSC_DELTA1(x)\t\tFIELD_PREP(RG_LCDDS_SSC_DELTA1_MASK, x)\n \n #define CORE_GSWPLL_GRP1\t\t0x40d\n-#define RG_GSWPLL_PREDIV(x)\t\t(((x) \u0026 0x3) \u003c\u003c 14)\n-#define RG_GSWPLL_POSDIV_200M(x)\t(((x) \u0026 0x3) \u003c\u003c 12)\n+#define RG_GSWPLL_PREDIV_MASK\t\tGENMASK(15, 14)\n+#define RG_GSWPLL_PREDIV(x)\t\tFIELD_PREP(RG_GSWPLL_PREDIV_MASK, x)\n+#define RG_GSWPLL_POSDIV_200M_MASK\tGENMASK(13, 12)\n+#define RG_GSWPLL_POSDIV_200M(x)\tFIELD_PREP(RG_GSWPLL_POSDIV_200M_MASK, x)\n #define RG_GSWPLL_EN_PRE\t\tBIT(11)\n #define RG_GSWPLL_FBKSEL\t\tBIT(10)\n #define RG_GSWPLL_BP\t\t\tBIT(9)\n #define RG_GSWPLL_BR\t\t\tBIT(8)\n-#define RG_GSWPLL_FBKDIV_200M(x)\t((x) \u0026 0xff)\n+#define RG_GSWPLL_FBKDIV_200M_MASK\tGENMASK(7, 0)\n+#define RG_GSWPLL_FBKDIV_200M(x)\tFIELD_PREP(RG_GSWPLL_FBKDIV_200M_MASK, x)\n \n #define CORE_GSWPLL_GRP2\t\t0x40e\n-#define RG_GSWPLL_POSDIV_500M(x)\t(((x) \u0026 0x3) \u003c\u003c 8)\n-#define RG_GSWPLL_FBKDIV_500M(x)\t((x) \u0026 0xff)\n+#define RG_GSWPLL_POSDIV_500M_MASK\tGENMASK(9, 8)\n+#define RG_GSWPLL_POSDIV_500M(x)\tFIELD_PREP(RG_GSWPLL_POSDIV_500M_MASK, x)\n+#define RG_GSWPLL_FBKDIV_500M_MASK\tGENMASK(7, 0)\n+#define RG_GSWPLL_FBKDIV_500M(x)\tFIELD_PREP(RG_GSWPLL_FBKDIV_500M_MASK, x)\n \n #define CORE_TRGMII_GSW_CLK_CG\t\t0x410\n #define REG_GSWCK_EN\t\t\tBIT(0)\n"
} |
| 2/1 | 2026/07/19 18:30 | agent | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: {
"EnableConfigs": [
"NET_DSA_MT7530",
"NET_DSA_MT7530_MDIO"
],
"FocusSymbols": [
"mt753x_port_change_conduit",
"mt7530_port_fast_age"
],
"Reasoning": "The patch replaces custom register access functions with the regmap API, which changes locking and error handling behavior. It also adds new DSA switch operations `port_change_conduit` and `port_fast_age`.",
"WorthFuzzing": true
}Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Do not list too generic configs (we already have them enabled). Only list those that specifically cover the modified code. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes:
commit 7d2dc209a34612ab3ddf502404476b81e1f49f47
Author: syz-cluster <triage@syzkaller.com>
Date: Sun Jul 19 18:30:55 2026 +0000
syz-cluster: applied patch under review
diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c
index 11ea924a9f3577..b1178924eb06f7 100644
--- a/drivers/net/dsa/mt7530-mdio.c
+++ b/drivers/net/dsa/mt7530-mdio.c
@@ -48,6 +48,9 @@ mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
u16 page, r, lo, hi;
int ret;
+ /* Callers do not check for errors, keep the value deterministic */
+ *val = 0;
+
page = (reg >> 6) & 0x3ff;
r = (reg >> 2) & 0xf;
@@ -141,12 +144,14 @@ static const struct regmap_config regmap_config = {
.val_bits = 32,
.reg_stride = 4,
.max_register = MT7530_CREV,
- .disable_locking = true,
+ .lock = mt7530_mdio_regmap_lock,
+ .unlock = mt7530_mdio_regmap_unlock,
};
static int
mt7530_probe(struct mdio_device *mdiodev)
{
+ struct regmap_config rc = regmap_config;
struct mt7530_priv *priv;
struct device_node *dn;
int ret;
@@ -200,8 +205,9 @@ mt7530_probe(struct mdio_device *mdiodev)
return PTR_ERR(priv->io_pwr);
}
- priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
- ®map_config);
+ rc.lock_arg = &priv->bus->mdio_lock;
+ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
+ priv, &rc);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 3c2a3029b10cfb..6fe6783dfe3f5f 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -150,99 +150,17 @@ core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
core_rmw(priv, reg, val, 0);
}
-static int
-mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
-{
- int ret;
-
- ret = regmap_write(priv->regmap, reg, val);
-
- if (ret < 0)
- dev_err(priv->dev,
- "failed to write mt7530 register\n");
-
- return ret;
-}
static u32
-mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
+mt7530_mii_poll(struct mt7530_dummy_poll *p)
{
- int ret;
u32 val;
- ret = regmap_read(priv->regmap, reg, &val);
- if (ret) {
- WARN_ON_ONCE(1);
- dev_err(priv->dev,
- "failed to read mt7530 register\n");
- return 0;
- }
+ regmap_read(p->priv->regmap, p->reg, &val);
return val;
}
-static void
-mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
-{
- mt7530_mutex_lock(priv);
-
- mt7530_mii_write(priv, reg, val);
-
- mt7530_mutex_unlock(priv);
-}
-
-static u32
-_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
-{
- return mt7530_mii_read(p->priv, p->reg);
-}
-
-static u32
-_mt7530_read(struct mt7530_dummy_poll *p)
-{
- u32 val;
-
- mt7530_mutex_lock(p->priv);
-
- val = mt7530_mii_read(p->priv, p->reg);
-
- mt7530_mutex_unlock(p->priv);
-
- return val;
-}
-
-static u32
-mt7530_read(struct mt7530_priv *priv, u32 reg)
-{
- struct mt7530_dummy_poll p;
-
- INIT_MT7530_DUMMY_POLL(&p, priv, reg);
- return _mt7530_read(&p);
-}
-
-static void
-mt7530_rmw(struct mt7530_priv *priv, u32 reg,
- u32 mask, u32 set)
-{
- mt7530_mutex_lock(priv);
-
- regmap_update_bits(priv->regmap, reg, mask, set);
-
- mt7530_mutex_unlock(priv);
-}
-
-static void
-mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
-{
- mt7530_rmw(priv, reg, val, val);
-}
-
-static void
-mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
-{
- mt7530_rmw(priv, reg, val, 0);
-}
-
static int
mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
{
@@ -252,10 +170,10 @@ mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
/* Set the command operating upon the MAC address entries */
val = ATC_BUSY | ATC_MAT(0) | cmd;
- mt7530_write(priv, MT7530_ATC, val);
+ regmap_write(priv->regmap, MT7530_ATC, val);
INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
- ret = readx_poll_timeout(_mt7530_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & ATC_BUSY), 20, 20000);
if (ret < 0) {
dev_err(priv->dev, "reset timeout\n");
@@ -265,7 +183,7 @@ mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
/* Additional sanity for read command if the specified
* entry is invalid
*/
- val = mt7530_read(priv, MT7530_ATC);
+ regmap_read(priv->regmap, MT7530_ATC, &val);
if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
return -EINVAL;
@@ -275,6 +193,28 @@ mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
return 0;
}
+static void mt7530_port_fast_age(struct dsa_switch *ds, int port)
+{
+ struct mt7530_priv *priv = ds->priv;
+ struct mt7530_dummy_poll p;
+ u32 val;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Flush all non-static MAC address entries */
+ val = ATC_BUSY | ATC_MAT_NON_STATIC_MAC | MT7530_FDB_FLUSH;
+ regmap_write(priv->regmap, MT7530_ATC, val);
+
+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
+ !(val & ATC_BUSY), 20, 20000);
+ if (ret < 0)
+ dev_err(priv->dev, "fast age timeout\n");
+
+ mutex_unlock(&priv->reg_mutex);
+}
+
static void
mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
{
@@ -283,22 +223,23 @@ mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
/* Read from ARL table into an array */
for (i = 0; i < 3; i++) {
- reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
+ regmap_read(priv->regmap, MT7530_TSRA1 + (i * 4),
+ ®[i]);
dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
__func__, __LINE__, i, reg[i]);
}
- fdb->vid = (reg[1] >> CVID) & CVID_MASK;
- fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
- fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
- fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
- fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
- fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
- fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
- fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
- fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
- fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
+ fdb->vid = FIELD_GET(CVID_MASK, reg[1]);
+ fdb->aging = FIELD_GET(AGE_TIMER_MASK, reg[2]);
+ fdb->port_mask = FIELD_GET(PORT_MAP_MASK, reg[2]);
+ fdb->mac[0] = FIELD_GET(MAC_BYTE_0_MASK, reg[0]);
+ fdb->mac[1] = FIELD_GET(MAC_BYTE_1_MASK, reg[0]);
+ fdb->mac[2] = FIELD_GET(MAC_BYTE_2_MASK, reg[0]);
+ fdb->mac[3] = FIELD_GET(MAC_BYTE_3_MASK, reg[0]);
+ fdb->mac[4] = FIELD_GET(MAC_BYTE_4_MASK, reg[1]);
+ fdb->mac[5] = FIELD_GET(MAC_BYTE_5_MASK, reg[1]);
+ fdb->noarp = FIELD_GET(ENT_STATUS_MASK, reg[2]) == STATIC_ENT;
}
static void
@@ -309,26 +250,26 @@ mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
u32 reg[3] = { 0 };
int i;
- reg[1] |= vid & CVID_MASK;
+ reg[1] |= FIELD_PREP(CVID_MASK, vid);
reg[1] |= ATA2_IVL;
reg[1] |= ATA2_FID(FID_BRIDGED);
- reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
- reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
+ reg[2] |= FIELD_PREP(AGE_TIMER_MASK, aging);
+ reg[2] |= FIELD_PREP(PORT_MAP_MASK, port_mask);
/* STATIC_ENT indicate that entry is static wouldn't
* be aged out and STATIC_EMP specified as erasing an
* entry
*/
- reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
- reg[1] |= mac[5] << MAC_BYTE_5;
- reg[1] |= mac[4] << MAC_BYTE_4;
- reg[0] |= mac[3] << MAC_BYTE_3;
- reg[0] |= mac[2] << MAC_BYTE_2;
- reg[0] |= mac[1] << MAC_BYTE_1;
- reg[0] |= mac[0] << MAC_BYTE_0;
+ reg[2] |= FIELD_PREP(ENT_STATUS_MASK, type);
+ reg[1] |= FIELD_PREP(MAC_BYTE_5_MASK, mac[5]);
+ reg[1] |= FIELD_PREP(MAC_BYTE_4_MASK, mac[4]);
+ reg[0] |= FIELD_PREP(MAC_BYTE_3_MASK, mac[3]);
+ reg[0] |= FIELD_PREP(MAC_BYTE_2_MASK, mac[2]);
+ reg[0] |= FIELD_PREP(MAC_BYTE_1_MASK, mac[1]);
+ reg[0] |= FIELD_PREP(MAC_BYTE_0_MASK, mac[0]);
/* Write array into the ARL table */
for (i = 0; i < 3; i++)
- mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
+ regmap_write(priv->regmap, MT7530_ATA1 + (i * 4), reg[i]);
}
/* Set up switch core clock for MT7530 */
@@ -382,14 +323,16 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)
core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
if (interface == PHY_INTERFACE_MODE_RGMII) {
- mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
- P6_INTF_MODE(0));
+ regmap_update_bits(priv->regmap, MT7530_P6ECR,
+ P6_INTF_MODE_MASK, P6_INTF_MODE(0));
return;
}
- mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+ regmap_update_bits(priv->regmap, MT7530_P6ECR, P6_INTF_MODE_MASK,
+ P6_INTF_MODE(1));
- xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
+ regmap_read(priv->regmap, MT753X_MTRAP, &xtal);
+ xtal &= MT7530_XTAL_MASK;
if (xtal == MT7530_XTAL_25MHZ)
ssc_delta = 0x57;
@@ -433,9 +376,9 @@ mt7531_pll_setup(struct mt7530_priv *priv)
u32 hwstrap;
u32 val;
- val = mt7530_read(priv, MT7531_CREV);
- top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
- hwstrap = mt7530_read(priv, MT753X_TRAP);
+ regmap_read(priv->regmap, MT7531_CREV, &val);
+ regmap_read(priv->regmap, MT7531_TOP_SIG_SR, &top_sig);
+ regmap_read(priv->regmap, MT753X_TRAP, &hwstrap);
if ((val & CHIP_REV_M) > 0)
xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
MT7531_XTAL_FSEL_25MHZ;
@@ -444,72 +387,72 @@ mt7531_pll_setup(struct mt7530_priv *priv)
MT7531_XTAL_FSEL_40MHZ;
/* Step 1 : Disable MT7531 COREPLL */
- val = mt7530_read(priv, MT7531_PLLGP_EN);
+ regmap_read(priv->regmap, MT7531_PLLGP_EN, &val);
val &= ~EN_COREPLL;
- mt7530_write(priv, MT7531_PLLGP_EN, val);
+ regmap_write(priv->regmap, MT7531_PLLGP_EN, val);
/* Step 2: switch to XTAL output */
- val = mt7530_read(priv, MT7531_PLLGP_EN);
+ regmap_read(priv->regmap, MT7531_PLLGP_EN, &val);
val |= SW_CLKSW;
- mt7530_write(priv, MT7531_PLLGP_EN, val);
+ regmap_write(priv->regmap, MT7531_PLLGP_EN, val);
- val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val);
val &= ~RG_COREPLL_EN;
- mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ regmap_write(priv->regmap, MT7531_PLLGP_CR0, val);
/* Step 3: disable PLLGP and enable program PLLGP */
- val = mt7530_read(priv, MT7531_PLLGP_EN);
+ regmap_read(priv->regmap, MT7531_PLLGP_EN, &val);
val |= SW_PLLGP;
- mt7530_write(priv, MT7531_PLLGP_EN, val);
+ regmap_write(priv->regmap, MT7531_PLLGP_EN, val);
/* Step 4: program COREPLL output frequency to 500MHz */
- val = mt7530_read(priv, MT7531_PLLGP_CR0);
- val &= ~RG_COREPLL_POSDIV_M;
- val |= 2 << RG_COREPLL_POSDIV_S;
- mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val);
+ val &= ~RG_COREPLL_POSDIV_MASK;
+ val |= RG_COREPLL_POSDIV(2);
+ regmap_write(priv->regmap, MT7531_PLLGP_CR0, val);
usleep_range(25, 35);
switch (xtal) {
case MT7531_XTAL_FSEL_25MHZ:
- val = mt7530_read(priv, MT7531_PLLGP_CR0);
- val &= ~RG_COREPLL_SDM_PCW_M;
- val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
- mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val);
+ val &= ~RG_COREPLL_SDM_PCW_MASK;
+ val |= RG_COREPLL_SDM_PCW(0x140000);
+ regmap_write(priv->regmap, MT7531_PLLGP_CR0, val);
break;
case MT7531_XTAL_FSEL_40MHZ:
- val = mt7530_read(priv, MT7531_PLLGP_CR0);
- val &= ~RG_COREPLL_SDM_PCW_M;
- val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
- mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val);
+ val &= ~RG_COREPLL_SDM_PCW_MASK;
+ val |= RG_COREPLL_SDM_PCW(0x190000);
+ regmap_write(priv->regmap, MT7531_PLLGP_CR0, val);
break;
}
/* Set feedback divide ratio update signal to high */
- val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val);
val |= RG_COREPLL_SDM_PCW_CHG;
- mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ regmap_write(priv->regmap, MT7531_PLLGP_CR0, val);
/* Wait for at least 16 XTAL clocks */
usleep_range(10, 20);
/* Step 5: set feedback divide ratio update signal to low */
- val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val);
val &= ~RG_COREPLL_SDM_PCW_CHG;
- mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ regmap_write(priv->regmap, MT7531_PLLGP_CR0, val);
/* Enable 325M clock for SGMII */
- mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
+ regmap_write(priv->regmap, MT7531_ANA_PLLGP_CR5, 0xad0000);
/* Enable 250SSC clock for RGMII */
- mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
+ regmap_write(priv->regmap, MT7531_ANA_PLLGP_CR2, 0x4f40000);
/* Step 6: Enable MT7531 PLL */
- val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ regmap_read(priv->regmap, MT7531_PLLGP_CR0, &val);
val |= RG_COREPLL_EN;
- mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ regmap_write(priv->regmap, MT7531_PLLGP_CR0, val);
- val = mt7530_read(priv, MT7531_PLLGP_EN);
+ regmap_read(priv->regmap, MT7531_PLLGP_EN, &val);
val |= EN_COREPLL;
- mt7530_write(priv, MT7531_PLLGP_EN, val);
+ regmap_write(priv->regmap, MT7531_PLLGP_EN, val);
usleep_range(25, 35);
}
@@ -518,8 +461,8 @@ mt7530_mib_reset(struct dsa_switch *ds)
{
struct mt7530_priv *priv = ds->priv;
- mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
- mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
+ regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_FLUSH);
+ regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
}
static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)
@@ -555,9 +498,9 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
- mt7530_mutex_lock(priv);
+ mutex_lock(&priv->reg_mutex);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -566,9 +509,9 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
MT7531_MDIO_DEV_ADDR(devad) | regnum;
- mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
+ regmap_write(priv->regmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -577,9 +520,9 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
MT7531_MDIO_DEV_ADDR(devad);
- mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
+ regmap_write(priv->regmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -588,7 +531,7 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
ret = val & MT7531_MDIO_RW_DATA_MASK;
out:
- mt7530_mutex_unlock(priv);
+ mutex_unlock(&priv->reg_mutex);
return ret;
}
@@ -603,9 +546,9 @@ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
- mt7530_mutex_lock(priv);
+ mutex_lock(&priv->reg_mutex);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -614,9 +557,9 @@ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
MT7531_MDIO_DEV_ADDR(devad) | regnum;
- mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
+ regmap_write(priv->regmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -625,9 +568,9 @@ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
MT7531_MDIO_DEV_ADDR(devad) | data;
- mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
+ regmap_write(priv->regmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -635,7 +578,7 @@ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
}
out:
- mt7530_mutex_unlock(priv);
+ mutex_unlock(&priv->reg_mutex);
return ret;
}
@@ -649,9 +592,9 @@ mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
- mt7530_mutex_lock(priv);
+ mutex_lock(&priv->reg_mutex);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -661,9 +604,9 @@ mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
MT7531_MDIO_REG_ADDR(regnum);
- mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
+ regmap_write(priv->regmap, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -672,7 +615,7 @@ mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
ret = val & MT7531_MDIO_RW_DATA_MASK;
out:
- mt7530_mutex_unlock(priv);
+ mutex_unlock(&priv->reg_mutex);
return ret;
}
@@ -687,9 +630,9 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
- mt7530_mutex_lock(priv);
+ mutex_lock(&priv->reg_mutex);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, reg,
!(reg & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -699,9 +642,9 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
MT7531_MDIO_REG_ADDR(regnum) | data;
- mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
+ regmap_write(priv->regmap, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, reg,
!(reg & MT7531_PHY_ACS_ST), 20, 100000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
@@ -709,7 +652,7 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
}
out:
- mt7530_mutex_unlock(priv);
+ mutex_unlock(&priv->reg_mutex);
return ret;
}
@@ -766,11 +709,11 @@ mt7530_read_port_stats(struct mt7530_priv *priv, int port,
{
u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset;
- val = mt7530_read(priv, reg);
+ regmap_read(priv->regmap, reg, &val);
*data = val;
if (size == 2) {
- val = mt7530_read(priv, reg + 4);
+ regmap_read(priv->regmap, reg + 4, &val);
*data |= (u64)val << 32;
}
}
@@ -1052,7 +995,8 @@ mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
}
}
- mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
+ regmap_write(priv->regmap, MT7530_AAC,
+ AGE_CNT(age_count) | AGE_UNIT(age_unit));
return 0;
}
@@ -1073,11 +1017,11 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
{
struct mt7530_priv *priv = ds->priv;
u8 tx_delay = 0;
- int val;
+ u32 val;
mutex_lock(&priv->reg_mutex);
- val = mt7530_read(priv, MT753X_MTRAP);
+ regmap_read(priv->regmap, MT753X_MTRAP, &val);
val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
@@ -1090,7 +1034,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
case MUX_PHY_P4:
/* Setup the MAC by default for the cpu port */
- mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ regmap_write(priv->regmap, MT753X_PMCR_P(5), 0x56300);
break;
/* GMAC5: P5 -> SoC MAC or external PHY */
@@ -1104,7 +1048,8 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
val |= MT7530_P5_RGMII_MODE;
/* P5 RGMII RX Clock Control: delay setting for 1000M */
- mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
+ regmap_write(priv->regmap, MT7530_P5RGMIIRXCR,
+ CSR_RGMII_EDGE_ALIGN);
/* Don't set delay in DSA mode */
if (!dsa_is_dsa_port(priv->ds, 5) &&
@@ -1113,15 +1058,15 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
tx_delay = 4; /* n * 0.5 ns */
/* P5 RGMII TX Clock Control: delay x */
- mt7530_write(priv, MT7530_P5RGMIITXCR,
+ regmap_write(priv->regmap, MT7530_P5RGMIITXCR,
CSR_RGMII_TXC_CFG(0x10 + tx_delay));
/* reduce P5 RGMII Tx driving, 8mA */
- mt7530_write(priv, MT7530_IO_DRV_CR,
+ regmap_write(priv->regmap, MT7530_IO_DRV_CR,
P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
}
- mt7530_write(priv, MT753X_MTRAP, val);
+ regmap_write(priv->regmap, MT753X_MTRAP, val);
dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
@@ -1306,35 +1251,35 @@ mt753x_trap_frames(struct mt7530_priv *priv)
* switch egress VLAN tag processing. This preserves VLAN tags
* for reception on VLAN sub-interfaces.
*/
- mt7530_rmw(priv, MT753X_BPC,
- PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
- BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
- PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
- BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
+ regmap_update_bits(priv->regmap, MT753X_BPC,
+ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
+ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
+ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) |
+ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
+ BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) |
+ TO_CPU_FW_CPU_ONLY);
/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and
* egress them with EG_TAG disabled.
*/
- mt7530_rmw(priv, MT753X_RGAC1,
- R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
- R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
- R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
- R01_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
+ regmap_update_bits(priv->regmap, MT753X_RGAC1,
+ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
+ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
+ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) |
+ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
+ R01_EG_TAG(MT7530_VLAN_EG_DISABLED) |
+ TO_CPU_FW_CPU_ONLY);
/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and
* egress them with EG_TAG disabled.
*/
- mt7530_rmw(priv, MT753X_RGAC2,
- R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
- R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
- R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
- R03_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
+ regmap_update_bits(priv->regmap, MT753X_RGAC2,
+ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
+ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
+ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) |
+ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
+ R03_EG_TAG(MT7530_VLAN_EG_DISABLED) |
+ TO_CPU_FW_CPU_ONLY);
}
static void
@@ -1343,12 +1288,11 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
struct mt7530_priv *priv = ds->priv;
/* Enable Mediatek header mode on the cpu port */
- mt7530_write(priv, MT7530_PVC_P(port),
- PORT_SPEC_TAG);
+ regmap_write(priv->regmap, MT7530_PVC_P(port), PORT_SPEC_TAG);
/* Enable flooding on the CPU port */
- mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
- UNU_FFP(BIT(port)));
+ regmap_set_bits(priv->regmap, MT753X_MFC,
+ BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
* the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
@@ -1356,17 +1300,18 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
*/
if (priv->id == ID_MT7531 || priv->id == ID_MT7988 ||
priv->id == ID_EN7581 || priv->id == ID_AN7583)
- mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));
+ regmap_set_bits(priv->regmap, MT7531_CFC,
+ MT7531_CPU_PMAP(BIT(port)));
/* CPU port gets connected to all user ports of
* the switch.
*/
- mt7530_write(priv, MT7530_PCR_P(port),
+ regmap_write(priv->regmap, MT7530_PCR_P(port),
PCR_MATRIX(dsa_user_ports(priv->ds)));
/* Set to fallback mode for independent VLAN learning */
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
- MT7530_PORT_FALLBACK_MODE);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
+ PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE);
}
static int
@@ -1388,8 +1333,8 @@ mt7530_port_enable(struct dsa_switch *ds, int port,
priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
}
priv->ports[port].enable = true;
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
- priv->ports[port].pm);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port), PCR_MATRIX_MASK,
+ priv->ports[port].pm);
mutex_unlock(&priv->reg_mutex);
@@ -1397,9 +1342,9 @@ mt7530_port_enable(struct dsa_switch *ds, int port,
return 0;
if (port == 5)
- mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ regmap_clear_bits(priv->regmap, MT753X_MTRAP, MT7530_P5_DIS);
else if (port == 6)
- mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ regmap_clear_bits(priv->regmap, MT753X_MTRAP, MT7530_P6_DIS);
return 0;
}
@@ -1415,8 +1360,8 @@ mt7530_port_disable(struct dsa_switch *ds, int port)
* enablement for the port.
*/
priv->ports[port].enable = false;
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
- PCR_MATRIX_CLR);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port), PCR_MATRIX_MASK,
+ PCR_MATRIX_CLR);
mutex_unlock(&priv->reg_mutex);
@@ -1425,9 +1370,9 @@ mt7530_port_disable(struct dsa_switch *ds, int port)
/* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */
if (port == 5 && priv->p5_mode == GMAC5)
- mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ regmap_set_bits(priv->regmap, MT753X_MTRAP, MT7530_P5_DIS);
else if (port == 6)
- mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ regmap_set_bits(priv->regmap, MT753X_MTRAP, MT7530_P6_DIS);
}
static int
@@ -1444,9 +1389,7 @@ mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
if (!dsa_is_cpu_port(ds, port))
return 0;
- mt7530_mutex_lock(priv);
-
- val = mt7530_mii_read(priv, MT7530_GMACCR);
+ regmap_read(priv->regmap, MT7530_GMACCR, &val);
val &= ~MAX_RX_PKT_LEN_MASK;
/* RX length also includes Ethernet header, MTK tag, and FCS length */
@@ -1463,9 +1406,7 @@ mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
val |= MAX_RX_PKT_LEN_JUMBO;
}
- mt7530_mii_write(priv, MT7530_GMACCR, val);
-
- mt7530_mutex_unlock(priv);
+ regmap_write(priv->regmap, MT7530_GMACCR, val);
return 0;
}
@@ -1501,8 +1442,9 @@ mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
break;
}
- mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
- FID_PST(FID_BRIDGED, stp_state));
+ regmap_update_bits(priv->regmap, MT7530_SSP_P(port),
+ FID_PST_MASK(FID_BRIDGED),
+ FID_PST(FID_BRIDGED, stp_state));
}
static void mt7530_update_port_member(struct mt7530_priv *priv, int port,
@@ -1541,8 +1483,9 @@ static void mt7530_update_port_member(struct mt7530_priv *priv, int port,
}
if (other_p->enable)
- mt7530_rmw(priv, MT7530_PCR_P(other_port),
- PCR_MATRIX_MASK, other_p->pm);
+ regmap_update_bits(priv->regmap,
+ MT7530_PCR_P(other_port),
+ PCR_MATRIX_MASK, other_p->pm);
}
/* Add/remove the all other ports to this port matrix. For !join
@@ -1551,7 +1494,8 @@ static void mt7530_update_port_member(struct mt7530_priv *priv, int port,
*/
p->pm = PCR_MATRIX(port_bitmap);
if (priv->ports[port].enable)
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
+ PCR_MATRIX_MASK, p->pm);
}
static int
@@ -1574,20 +1518,23 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
struct mt7530_priv *priv = ds->priv;
if (flags.mask & BR_LEARNING)
- mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
- flags.val & BR_LEARNING ? 0 : SA_DIS);
+ regmap_update_bits(priv->regmap, MT7530_PSC_P(port), SA_DIS,
+ flags.val & BR_LEARNING ? 0 : SA_DIS);
if (flags.mask & BR_FLOOD)
- mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
- flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
+ regmap_update_bits(priv->regmap, MT753X_MFC,
+ UNU_FFP(BIT(port)),
+ flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
if (flags.mask & BR_MCAST_FLOOD)
- mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
- flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
+ regmap_update_bits(priv->regmap, MT753X_MFC,
+ UNM_FFP(BIT(port)),
+ flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
if (flags.mask & BR_BCAST_FLOOD)
- mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
- flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
+ regmap_update_bits(priv->regmap, MT753X_MFC,
+ BC_FFP(BIT(port)),
+ flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
if (flags.mask & BR_ISOLATED) {
struct dsa_port *dp = dsa_to_port(ds, port);
@@ -1615,8 +1562,8 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int port,
mt7530_update_port_member(priv, port, bridge.dev, true);
/* Set to fallback mode for independent VLAN learning */
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
- MT7530_PORT_FALLBACK_MODE);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
+ PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE);
mutex_unlock(&priv->reg_mutex);
@@ -1630,18 +1577,18 @@ mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
u32 val;
int ret;
- val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
- mt7530_write(priv, MT7530_VTCR, val);
+ val = VTCR_BUSY | VTCR_FUNC(cmd) | VTCR_VID(vid);
+ regmap_write(priv->regmap, MT7530_VTCR, val);
INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
- ret = readx_poll_timeout(_mt7530_read, &p, val,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val,
!(val & VTCR_BUSY), 20, 20000);
if (ret < 0) {
dev_err(priv->dev, "poll timeout\n");
return ret;
}
- val = mt7530_read(priv, MT7530_VTCR);
+ regmap_read(priv->regmap, MT7530_VTCR, &val);
if (val & VTCR_INVALID) {
dev_err(priv->dev, "read VTCR invalid\n");
return -EINVAL;
@@ -1660,8 +1607,8 @@ mt7530_setup_vlan0(struct mt7530_priv *priv)
*/
val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
VLAN_VALID;
- mt7530_write(priv, MT7530_VAWD1, val);
- mt7530_write(priv, MT7530_VAWD2, 0);
+ regmap_write(priv->regmap, MT7530_VAWD1, val);
+ regmap_write(priv->regmap, MT7530_VAWD2, 0);
return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
}
@@ -1677,18 +1624,19 @@ mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
* bridge. Don't set standalone ports to fallback mode.
*/
if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
- MT7530_PORT_FALLBACK_MODE);
-
- mt7530_rmw(priv, MT7530_PVC_P(port),
- VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
- VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
- PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
- MT7530_VLAN_ACC_ALL);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
+ PCR_PORT_VLAN_MASK,
+ MT7530_PORT_FALLBACK_MODE);
+
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
+ VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
+ VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
+ PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
+ MT7530_VLAN_ACC_ALL);
/* Set PVID to 0 */
- mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
- G0_PORT_VID_DEF);
+ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
+ G0_PORT_VID_MASK, G0_PORT_VID_DEF);
for (i = 0; i < priv->ds->num_ports; i++) {
if (i == port)
@@ -1719,24 +1667,27 @@ mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
* table lookup.
*/
if (dsa_is_user_port(ds, port)) {
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
- MT7530_PORT_SECURITY_MODE);
- mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
- G0_PORT_VID(priv->ports[port].pvid));
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
+ PCR_PORT_VLAN_MASK,
+ MT7530_PORT_SECURITY_MODE);
+ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
+ G0_PORT_VID_MASK,
+ G0_PORT_VID(priv->ports[port].pvid));
/* Only accept tagged frames if PVID is not set */
if (!priv->ports[port].pvid)
- mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
+ ACC_FRM_MASK,
+ MT7530_VLAN_ACC_TAGGED);
/* Set the port as a user port which is to be able to recognize
* VID from incoming packets before fetching entry within the
* VLAN table.
*/
- mt7530_rmw(priv, MT7530_PVC_P(port),
- VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
- VLAN_ATTR(MT7530_VLAN_USER) |
- PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
+ VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
+ VLAN_ATTR(MT7530_VLAN_USER) |
+ PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
} else {
/* Also set CPU ports to the "user" VLAN port attribute, to
* allow VLAN classification, but keep the EG_TAG attribute as
@@ -1745,8 +1696,9 @@ mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
* are forwarded to user ports as tagged, and untagged as
* untagged.
*/
- mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
- VLAN_ATTR(MT7530_VLAN_USER));
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
+ VLAN_ATTR_MASK,
+ VLAN_ATTR(MT7530_VLAN_USER));
}
}
@@ -1764,8 +1716,8 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
* back to the default as is at initial boot which is a VLAN-unaware
* port.
*/
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
- MT7530_PORT_MATRIX_MODE);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
+ PCR_PORT_VLAN_MASK, MT7530_PORT_MATRIX_MODE);
mutex_unlock(&priv->reg_mutex);
}
@@ -1848,14 +1800,16 @@ mt7530_port_mdb_add(struct dsa_switch *ds, int port,
const u8 *addr = mdb->addr;
u16 vid = mdb->vid;
u8 port_mask = 0;
+ u32 val;
int ret;
mutex_lock(&priv->reg_mutex);
mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
- if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
- port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
- & PORT_MAP_MASK;
+ if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {
+ regmap_read(priv->regmap, MT7530_ATRD, &val);
+ port_mask = FIELD_GET(PORT_MAP_MASK, val);
+ }
port_mask |= BIT(port);
mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
@@ -1875,14 +1829,16 @@ mt7530_port_mdb_del(struct dsa_switch *ds, int port,
const u8 *addr = mdb->addr;
u16 vid = mdb->vid;
u8 port_mask = 0;
+ u32 val;
int ret;
mutex_lock(&priv->reg_mutex);
mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
- if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
- port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
- & PORT_MAP_MASK;
+ if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {
+ regmap_read(priv->regmap, MT7530_ATRD, &val);
+ port_mask = FIELD_GET(PORT_MAP_MASK, val);
+ }
port_mask &= ~BIT(port);
mt7530_fdb_write(priv, vid, port_mask, addr, -1,
@@ -1931,7 +1887,7 @@ mt7530_hw_vlan_add(struct mt7530_priv *priv,
*/
val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
VLAN_VALID;
- mt7530_write(priv, MT7530_VAWD1, val);
+ regmap_write(priv->regmap, MT7530_VAWD1, val);
/* Decide whether adding tag or not for those outgoing packets from the
* port inside the VLAN.
@@ -1946,9 +1902,9 @@ mt7530_hw_vlan_add(struct mt7530_priv *priv,
val = MT7530_VLAN_EGRESS_UNTAG;
else
val = MT7530_VLAN_EGRESS_TAG;
- mt7530_rmw(priv, MT7530_VAWD2,
- ETAG_CTRL_P_MASK(entry->port),
- ETAG_CTRL_P(entry->port, val));
+ regmap_update_bits(priv->regmap, MT7530_VAWD2,
+ ETAG_CTRL_P_MASK(entry->port),
+ ETAG_CTRL_P(entry->port, val));
}
static void
@@ -1960,7 +1916,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *priv,
new_members = entry->old_members & ~BIT(entry->port);
- val = mt7530_read(priv, MT7530_VAWD1);
+ regmap_read(priv->regmap, MT7530_VAWD1, &val);
if (!(val & VLAN_VALID)) {
dev_err(priv->dev,
"Cannot be deleted due to invalid entry\n");
@@ -1970,10 +1926,10 @@ mt7530_hw_vlan_del(struct mt7530_priv *priv,
if (new_members) {
val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
VLAN_VALID;
- mt7530_write(priv, MT7530_VAWD1, val);
+ regmap_write(priv->regmap, MT7530_VAWD1, val);
} else {
- mt7530_write(priv, MT7530_VAWD1, 0);
- mt7530_write(priv, MT7530_VAWD2, 0);
+ regmap_write(priv->regmap, MT7530_VAWD1, 0);
+ regmap_write(priv->regmap, MT7530_VAWD2, 0);
}
}
@@ -1987,9 +1943,9 @@ mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
/* Fetch entry */
mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
- val = mt7530_read(priv, MT7530_VAWD1);
+ regmap_read(priv->regmap, MT7530_VAWD1, &val);
- entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
+ entry->old_members = FIELD_GET(PORT_MEM_MASK, val);
/* Manipulate entry */
vlan_op(priv, entry);
@@ -2026,25 +1982,26 @@ mt7530_port_vlan_add(struct dsa_switch *ds, int port,
priv->ports[port].pvid = vlan->vid;
/* Accept all frames if PVID is set */
- mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
- MT7530_VLAN_ACC_ALL);
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
+ ACC_FRM_MASK, MT7530_VLAN_ACC_ALL);
/* Only configure PVID if VLAN filtering is enabled */
if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- mt7530_rmw(priv, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK,
- G0_PORT_VID(vlan->vid));
+ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
+ G0_PORT_VID_MASK,
+ G0_PORT_VID(vlan->vid));
} else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
/* This VLAN is overwritten without PVID, so unset it */
priv->ports[port].pvid = G0_PORT_VID_DEF;
/* Only accept tagged frames if the port is VLAN-aware */
if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
+ ACC_FRM_MASK,
+ MT7530_VLAN_ACC_TAGGED);
- mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
- G0_PORT_VID_DEF);
+ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
+ G0_PORT_VID_MASK, G0_PORT_VID_DEF);
}
mutex_unlock(&priv->reg_mutex);
@@ -2078,11 +2035,12 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int port,
/* Only accept tagged frames if the port is VLAN-aware */
if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
+ ACC_FRM_MASK,
+ MT7530_VLAN_ACC_TAGGED);
- mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
- G0_PORT_VID_DEF);
+ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
+ G0_PORT_VID_MASK, G0_PORT_VID_DEF);
}
@@ -2103,7 +2061,7 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
return -EEXIST;
- val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
+ regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val);
/* MT7530 only supports one monitor port */
monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
@@ -2114,9 +2072,9 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
val |= MT753X_MIRROR_EN(priv->id);
val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
- mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
+ regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val);
- val = mt7530_read(priv, MT7530_PCR_P(port));
+ regmap_read(priv->regmap, MT7530_PCR_P(port), &val);
if (ingress) {
val |= PORT_RX_MIR;
priv->mirror_rx |= BIT(port);
@@ -2124,7 +2082,7 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
val |= PORT_TX_MIR;
priv->mirror_tx |= BIT(port);
}
- mt7530_write(priv, MT7530_PCR_P(port), val);
+ regmap_write(priv->regmap, MT7530_PCR_P(port), val);
return 0;
}
@@ -2135,7 +2093,7 @@ static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
struct mt7530_priv *priv = ds->priv;
u32 val;
- val = mt7530_read(priv, MT7530_PCR_P(port));
+ regmap_read(priv->regmap, MT7530_PCR_P(port), &val);
if (mirror->ingress) {
val &= ~PORT_RX_MIR;
priv->mirror_rx &= ~BIT(port);
@@ -2143,12 +2101,12 @@ static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
val &= ~PORT_TX_MIR;
priv->mirror_tx &= ~BIT(port);
}
- mt7530_write(priv, MT7530_PCR_P(port), val);
+ regmap_write(priv->regmap, MT7530_PCR_P(port), val);
if (!priv->mirror_rx && !priv->mirror_tx) {
- val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
+ regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val);
val &= ~MT753X_MIRROR_EN(priv->id);
- mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
+ regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val);
}
}
@@ -2178,8 +2136,11 @@ mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct mt7530_priv *priv = gpiochip_get_data(gc);
u32 bit = mt7530_gpio_to_bit(offset);
+ u32 val;
+
+ regmap_read(priv->regmap, MT7530_LED_GPIO_DATA, &val);
- return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
+ return !!(val & bit);
}
static int
@@ -2189,9 +2150,9 @@ mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
u32 bit = mt7530_gpio_to_bit(offset);
if (value)
- mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
+ regmap_set_bits(priv->regmap, MT7530_LED_GPIO_DATA, bit);
else
- mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
+ regmap_clear_bits(priv->regmap, MT7530_LED_GPIO_DATA, bit);
return 0;
}
@@ -2201,8 +2162,11 @@ mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct mt7530_priv *priv = gpiochip_get_data(gc);
u32 bit = mt7530_gpio_to_bit(offset);
+ u32 val;
+
+ regmap_read(priv->regmap, MT7530_LED_GPIO_DIR, &val);
- return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
+ return (val & bit) ?
GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
}
@@ -2212,8 +2176,8 @@ mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
struct mt7530_priv *priv = gpiochip_get_data(gc);
u32 bit = mt7530_gpio_to_bit(offset);
- mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
- mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
+ regmap_clear_bits(priv->regmap, MT7530_LED_GPIO_OE, bit);
+ regmap_clear_bits(priv->regmap, MT7530_LED_GPIO_DIR, bit);
return 0;
}
@@ -2224,14 +2188,14 @@ mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int valu
struct mt7530_priv *priv = gpiochip_get_data(gc);
u32 bit = mt7530_gpio_to_bit(offset);
- mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
+ regmap_set_bits(priv->regmap, MT7530_LED_GPIO_DIR, bit);
if (value)
- mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
+ regmap_set_bits(priv->regmap, MT7530_LED_GPIO_DATA, bit);
else
- mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
+ regmap_clear_bits(priv->regmap, MT7530_LED_GPIO_DATA, bit);
- mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
+ regmap_set_bits(priv->regmap, MT7530_LED_GPIO_OE, bit);
return 0;
}
@@ -2246,9 +2210,9 @@ mt7530_setup_gpio(struct mt7530_priv *priv)
if (!gc)
return -ENOMEM;
- mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
- mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
- mt7530_write(priv, MT7530_LED_IO_MODE, 0);
+ regmap_write(priv->regmap, MT7530_LED_GPIO_OE, 0);
+ regmap_write(priv->regmap, MT7530_LED_GPIO_DIR, 0);
+ regmap_write(priv->regmap, MT7530_LED_IO_MODE, 0);
gc->label = "mt7530";
gc->parent = dev;
@@ -2337,7 +2301,8 @@ mt7530_setup_irq(struct mt7530_priv *priv)
/* This register must be set for MT7530 to properly fire interrupts */
if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
- mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
+ regmap_set_bits(priv->regmap, MT7530_TOP_SIG_CTRL,
+ TOP_SIG_CTRL_NORMAL);
ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev),
priv->regmap, irq,
@@ -2485,15 +2450,15 @@ mt7530_setup(struct dsa_switch *ds)
/* Waiting for MT7530 got to stable */
INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
- ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val, val != 0,
20, 1000000);
if (ret < 0) {
dev_err(priv->dev, "reset timeout\n");
return ret;
}
- id = mt7530_read(priv, MT7530_CREV);
- id >>= CHIP_NAME_SHIFT;
+ regmap_read(priv->regmap, MT7530_CREV, &id);
+ id = FIELD_GET(CHIP_NAME_MASK, id);
if (id != MT7530_ID) {
dev_err(priv->dev, "chip %x can't be supported\n", id);
return -ENODEV;
@@ -2506,24 +2471,24 @@ mt7530_setup(struct dsa_switch *ds)
}
/* Reset the switch through internal reset */
- mt7530_write(priv, MT7530_SYS_CTRL,
- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
- SYS_CTRL_REG_RST);
+ regmap_write(priv->regmap, MT7530_SYS_CTRL,
+ SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
/* Lower Tx driving for TRGMII path */
for (i = 0; i < NUM_TRGMII_CTRL; i++)
- mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
+ regmap_write(priv->regmap, MT7530_TRGMII_TD_ODT(i),
TD_DM_DRVP(8) | TD_DM_DRVN(8));
for (i = 0; i < NUM_TRGMII_CTRL; i++)
- mt7530_rmw(priv, MT7530_TRGMII_RD(i),
- RD_TAP_MASK, RD_TAP(16));
+ regmap_update_bits(priv->regmap, MT7530_TRGMII_RD(i),
+ RD_TAP_MASK, RD_TAP(16));
/* Allow modifying the trap and directly access PHY registers via the
* MDIO bus the switch is on.
*/
- mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
- MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+ regmap_update_bits(priv->regmap, MT753X_MTRAP,
+ MT7530_CHG_TRAP | MT7530_PHY_INDIRECT_ACCESS,
+ MT7530_CHG_TRAP);
if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
mt7530_pll_setup(priv);
@@ -2537,17 +2502,16 @@ mt7530_setup(struct dsa_switch *ds)
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
- mt7530_rmw(priv, MT753X_PMCR_P(i),
- PMCR_LINK_SETTINGS_MASK |
- MT753X_FORCE_MODE(priv->id),
- MT753X_FORCE_MODE(priv->id));
+ regmap_update_bits(priv->regmap, MT753X_PMCR_P(i),
+ PMCR_LINK_SETTINGS_MASK | MT753X_FORCE_MODE(priv->id),
+ MT753X_FORCE_MODE(priv->id));
/* Disable forwarding by default on all ports */
- mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
- PCR_MATRIX_CLR);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(i),
+ PCR_MATRIX_MASK, PCR_MATRIX_CLR);
/* Disable learning by default on all ports */
- mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
+ regmap_set_bits(priv->regmap, MT7530_PSC_P(i), SA_DIS);
if (dsa_is_cpu_port(ds, i)) {
mt753x_cpu_port_enable(ds, i);
@@ -2555,16 +2519,17 @@ mt7530_setup(struct dsa_switch *ds)
mt7530_port_disable(ds, i);
/* Set default PVID to 0 on all user ports */
- mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
- G0_PORT_VID_DEF);
+ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i),
+ G0_PORT_VID_MASK, G0_PORT_VID_DEF);
}
/* Enable consistent egress tag */
- mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
- PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(i),
+ PVC_EG_TAG_MASK,
+ PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
}
/* Allow mirroring frames received on the local port (monitor port). */
- mt7530_set(priv, MT753X_AGC, LOCAL_EN);
+ regmap_set_bits(priv->regmap, MT753X_AGC, LOCAL_EN);
/* Setup VLAN ID 0 for VLAN-unaware bridges */
ret = mt7530_setup_vlan0(priv);
@@ -2611,7 +2576,8 @@ mt7530_setup(struct dsa_switch *ds)
if (priv->p5_mode == MUX_PHY_P0 ||
priv->p5_mode == MUX_PHY_P4) {
- mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ regmap_clear_bits(priv->regmap, MT753X_MTRAP,
+ MT7530_P5_DIS);
mt7530_setup_port5(ds, interface);
}
}
@@ -2650,26 +2616,26 @@ mt7531_setup_common(struct dsa_switch *ds)
mt7530_mib_reset(ds);
/* Disable flooding on all ports */
- mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
- UNU_FFP_MASK);
+ regmap_clear_bits(priv->regmap, MT753X_MFC,
+ BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK);
for (i = 0; i < priv->ds->num_ports; i++) {
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
- mt7530_rmw(priv, MT753X_PMCR_P(i),
- PMCR_LINK_SETTINGS_MASK |
- MT753X_FORCE_MODE(priv->id),
- MT753X_FORCE_MODE(priv->id));
+ regmap_update_bits(priv->regmap, MT753X_PMCR_P(i),
+ PMCR_LINK_SETTINGS_MASK | MT753X_FORCE_MODE(priv->id),
+ MT753X_FORCE_MODE(priv->id));
/* Disable forwarding by default on all ports */
- mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
- PCR_MATRIX_CLR);
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(i),
+ PCR_MATRIX_MASK, PCR_MATRIX_CLR);
/* Disable learning by default on all ports */
- mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
+ regmap_set_bits(priv->regmap, MT7530_PSC_P(i), SA_DIS);
- mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
+ regmap_set_bits(priv->regmap, MT7531_DBG_CNT(i),
+ MT7531_DIS_CLR);
if (dsa_is_cpu_port(ds, i)) {
mt753x_cpu_port_enable(ds, i);
@@ -2677,21 +2643,22 @@ mt7531_setup_common(struct dsa_switch *ds)
mt7530_port_disable(ds, i);
/* Set default PVID to 0 on all user ports */
- mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
- G0_PORT_VID_DEF);
+ regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i),
+ G0_PORT_VID_MASK, G0_PORT_VID_DEF);
}
/* Enable consistent egress tag */
- mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
- PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
+ regmap_update_bits(priv->regmap, MT7530_PVC_P(i),
+ PVC_EG_TAG_MASK,
+ PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
}
/* Allow mirroring frames received on the local port (monitor port). */
- mt7530_set(priv, MT753X_AGC, LOCAL_EN);
+ regmap_set_bits(priv->regmap, MT753X_AGC, LOCAL_EN);
/* Enable Special Tag for rx frames */
if (priv->id == ID_EN7581 || priv->id == ID_AN7583)
- mt7530_write(priv, MT753X_CPORT_SPTAG_CFG,
+ regmap_write(priv->regmap, MT753X_CPORT_SPTAG_CFG,
CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN);
/* Flush the FDB table */
@@ -2726,15 +2693,15 @@ mt7531_setup(struct dsa_switch *ds)
/* Waiting for MT7530 got to stable */
INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
- ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ ret = readx_poll_timeout(mt7530_mii_poll, &p, val, val != 0,
20, 1000000);
if (ret < 0) {
dev_err(priv->dev, "reset timeout\n");
return ret;
}
- id = mt7530_read(priv, MT7531_CREV);
- id >>= CHIP_NAME_SHIFT;
+ regmap_read(priv->regmap, MT7531_CREV, &id);
+ id = FIELD_GET(CHIP_NAME_MASK, id);
if (id != MT7531_ID) {
dev_err(priv->dev, "chip %x can't be supported\n", id);
@@ -2744,15 +2711,17 @@ mt7531_setup(struct dsa_switch *ds)
/* MT7531AE has got two SGMII units. One for port 5, one for port 6.
* MT7531BE has got only one SGMII unit which is for port 6.
*/
- val = mt7530_read(priv, MT7531_TOP_SIG_SR);
+ regmap_read(priv->regmap, MT7531_TOP_SIG_SR, &val);
priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
/* Force link down on all ports before internal reset */
for (i = 0; i < priv->ds->num_ports; i++)
- mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+ regmap_write(priv->regmap, MT753X_PMCR_P(i),
+ MT7531_FORCE_MODE_LNK);
/* Reset the switch through internal reset */
- mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+ regmap_write(priv->regmap, MT7530_SYS_CTRL,
+ SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
if (!priv->p5_sgmii) {
mt7531_pll_setup(priv);
@@ -2761,14 +2730,16 @@ mt7531_setup(struct dsa_switch *ds)
* MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO
* to expose the MDIO bus of the switch.
*/
- mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
- MT7531_EXT_P_MDC_11);
- mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
- MT7531_EXT_P_MDIO_12);
+ regmap_update_bits(priv->regmap, MT7531_GPIO_MODE1,
+ MT7531_GPIO11_RG_RXD2_MASK,
+ MT7531_EXT_P_MDC_11);
+ regmap_update_bits(priv->regmap, MT7531_GPIO_MODE1,
+ MT7531_GPIO12_RG_RXD3_MASK,
+ MT7531_EXT_P_MDIO_12);
}
- mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
- MT7531_GPIO0_INTERRUPT);
+ regmap_update_bits(priv->regmap, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
/* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
* phy_device has not yet been created provided for
@@ -2930,7 +2901,7 @@ static void mt7531_rgmii_setup(struct mt7530_priv *priv,
{
u32 val;
- val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
+ regmap_read(priv->regmap, MT7531_CLKGEN_CTRL, &val);
val |= GP_CLK_EN;
val &= ~GP_MODE_MASK;
val |= GP_MODE(MT7531_GP_MODE_RGMII);
@@ -2961,7 +2932,7 @@ static void mt7531_rgmii_setup(struct mt7530_priv *priv,
}
}
- mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
+ regmap_write(priv->regmap, MT7531_CLKGEN_CTRL, val);
}
static void
@@ -3014,7 +2985,8 @@ mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode,
/* Are we connected to external phy */
if (port == 5 && dsa_is_user_port(ds, 5))
- mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
+ regmap_set_bits(priv->regmap, MT753X_PMCR_P(port),
+ PMCR_EXT_PHY);
}
static void mt753x_phylink_mac_link_down(struct phylink_config *config,
@@ -3024,7 +2996,8 @@ static void mt753x_phylink_mac_link_down(struct phylink_config *config,
struct dsa_port *dp = dsa_phylink_to_port(config);
struct mt7530_priv *priv = dp->ds->priv;
- mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ regmap_clear_bits(priv->regmap, MT753X_PMCR_P(dp->index),
+ PMCR_LINK_SETTINGS_MASK);
}
static void mt753x_phylink_mac_link_up(struct phylink_config *config,
@@ -3058,7 +3031,7 @@ static void mt753x_phylink_mac_link_up(struct phylink_config *config,
mcr |= PMCR_FORCE_RX_FC_EN;
}
- mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
+ regmap_set_bits(priv->regmap, MT753X_PMCR_P(dp->index), mcr);
}
static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config)
@@ -3066,8 +3039,8 @@ static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config)
struct dsa_port *dp = dsa_phylink_to_port(config);
struct mt7530_priv *priv = dp->ds->priv;
- mt7530_clear(priv, MT753X_PMCR_P(dp->index),
- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100);
+ regmap_clear_bits(priv->regmap, MT753X_PMCR_P(dp->index),
+ PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100);
}
static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config,
@@ -3088,11 +3061,11 @@ static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config,
else
val = LPI_THRESH_MASK;
- mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index),
- LPI_THRESH_MASK | LPI_MODE_EN, val);
+ regmap_update_bits(priv->regmap, MT753X_PMEEECR_P(dp->index),
+ LPI_THRESH_MASK | LPI_MODE_EN, val);
- mt7530_set(priv, MT753X_PMCR_P(dp->index),
- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100);
+ regmap_set_bits(priv->regmap, MT753X_PMCR_P(dp->index),
+ PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100);
return 0;
}
@@ -3107,7 +3080,7 @@ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD;
- eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port));
+ regmap_read(priv->regmap, MT753X_PMEEECR_P(port), &eeecr);
/* tx_lpi_timer should be in microseconds. The time units for
* LPI threshold are unspecified.
*/
@@ -3135,7 +3108,7 @@ static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
int port = pcs_to_mt753x_pcs(pcs)->port;
u32 pmsr;
- pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
+ regmap_read(priv->regmap, MT7530_PMSR_P(port), &pmsr);
state->link = (pmsr & PMSR_LINK);
state->an_complete = state->link;
@@ -3240,6 +3213,43 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
return 0;
}
+static int
+mt753x_port_change_conduit(struct dsa_switch *ds, int port,
+ struct net_device *conduit,
+ struct netlink_ext_ack *extack)
+{
+ struct dsa_port *new_cpu_dp = conduit->dsa_ptr;
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct mt7530_priv *priv = ds->priv;
+
+ if (priv->id != ID_MT7531) {
+ NL_SET_ERR_MSG_MOD(extack,
+ "Changing DSA conduit is only supported on MT7531");
+ return -EOPNOTSUPP;
+ }
+
+ if (new_cpu_dp->ds != ds) {
+ NL_SET_ERR_MSG_MOD(extack,
+ "Cannot assign a conduit on a different switch");
+ return -EOPNOTSUPP;
+ }
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* dp->cpu_dp still points to the old CPU port */
+ priv->ports[port].pm &= ~PCR_MATRIX(BIT(dp->cpu_dp->index));
+ priv->ports[port].pm |= PCR_MATRIX(BIT(new_cpu_dp->index));
+ if (priv->ports[port].enable)
+ regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
+ PCR_MATRIX_MASK, priv->ports[port].pm);
+
+ mutex_unlock(&priv->reg_mutex);
+
+ mt7530_port_fast_age(ds, port);
+
+ return 0;
+}
+
static void
mt753x_conduit_state_change(struct dsa_switch *ds,
const struct net_device *conduit,
@@ -3269,7 +3279,8 @@ mt753x_conduit_state_change(struct dsa_switch *ds,
MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
}
- mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
+ regmap_update_bits(priv->regmap, MT753X_MFC,
+ MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
}
static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port,
@@ -3286,8 +3297,8 @@ static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port,
case TC_TBF_DESTROY: {
u32 val, tick;
- mt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK,
- EGR_BC_CRC_IPG_PREAMBLE);
+ regmap_update_bits(priv->regmap, MT753X_GERLCR, EGR_BC_MASK,
+ EGR_BC_CRC_IPG_PREAMBLE);
/* if rate is greater than 10Mbps tick is 1/32 ms,
* 1ms otherwise
@@ -3298,7 +3309,7 @@ static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port,
FIELD_PREP(ERLCR_EXP_MASK, tick) |
ERLCR_TBF_MODE_MASK |
FIELD_PREP(ERLCR_MANT_MASK, 0xf);
- mt7530_write(priv, MT753X_ERLCR_P(port), val);
+ regmap_write(priv->regmap, MT753X_ERLCR_P(port), val);
break;
}
default:
@@ -3331,16 +3342,16 @@ static int mt7988_setup(struct dsa_switch *ds)
/* AN7583 require additional tweak to CONN_CFG */
if (priv->id == ID_AN7583)
- mt7530_rmw(priv, AN7583_GEPHY_CONN_CFG,
- AN7583_CSR_DPHY_CKIN_SEL |
- AN7583_CSR_PHY_CORE_REG_CLK_SEL |
- AN7583_CSR_ETHER_AFE_PWD,
- AN7583_CSR_DPHY_CKIN_SEL |
- AN7583_CSR_PHY_CORE_REG_CLK_SEL |
- FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0));
+ regmap_update_bits(priv->regmap, AN7583_GEPHY_CONN_CFG,
+ AN7583_CSR_DPHY_CKIN_SEL |
+ AN7583_CSR_PHY_CORE_REG_CLK_SEL |
+ AN7583_CSR_ETHER_AFE_PWD,
+ AN7583_CSR_DPHY_CKIN_SEL |
+ AN7583_CSR_PHY_CORE_REG_CLK_SEL |
+ FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0));
/* Reset the switch PHYs */
- mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
+ regmap_write(priv->regmap, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
return mt7531_setup_common(ds);
}
@@ -3350,6 +3361,7 @@ static const struct dsa_switch_ops mt7530_switch_ops = {
.setup = mt753x_setup,
.teardown = mt753x_teardown,
.preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port,
+ .port_change_conduit = mt753x_port_change_conduit,
.get_strings = mt7530_get_strings,
.get_ethtool_stats = mt7530_get_ethtool_stats,
.get_sset_count = mt7530_get_sset_count,
@@ -3367,6 +3379,7 @@ static const struct dsa_switch_ops mt7530_switch_ops = {
.port_bridge_flags = mt7530_port_bridge_flags,
.port_bridge_join = mt7530_port_bridge_join,
.port_bridge_leave = mt7530_port_bridge_leave,
+ .port_fast_age = mt7530_port_fast_age,
.port_fdb_add = mt7530_port_fdb_add,
.port_fdb_del = mt7530_port_fdb_del,
.port_fdb_dump = mt7530_port_fdb_dump,
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index dd33b0df3419e3..241e3d4603577f 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -6,6 +6,8 @@
#ifndef __MT7530_H
#define __MT7530_H
+#include <linux/bitfield.h>
+
#define MT7530_NUM_PORTS 7
#define MT7530_NUM_PHYS 5
#define MT7530_NUM_FDB_RECORDS 2048
@@ -146,20 +148,24 @@ enum mt753x_to_cpu_fw {
#define STATIC_ENT 3
#define MT7530_ATA2 0x78
#define ATA2_IVL BIT(15)
-#define ATA2_FID(x) (((x) & 0x7) << 12)
+#define ATA2_FID_MASK GENMASK(14, 12)
+#define ATA2_FID(x) FIELD_PREP(ATA2_FID_MASK, x)
/* Register for address table write data */
#define MT7530_ATWD 0x7c
/* Register for address table control */
#define MT7530_ATC 0x80
-#define ATC_HASH (((x) & 0xfff) << 16)
+#define ATC_HASH_MASK GENMASK(27, 16)
+#define ATC_HASH(x) FIELD_PREP(ATC_HASH_MASK, x)
#define ATC_BUSY BIT(15)
#define ATC_SRCH_END BIT(14)
#define ATC_SRCH_HIT BIT(13)
#define ATC_INVALID BIT(12)
-#define ATC_MAT(x) (((x) & 0xf) << 8)
+#define ATC_MAT_MASK GENMASK(11, 8)
+#define ATC_MAT(x) FIELD_PREP(ATC_MAT_MASK, x)
#define ATC_MAT_MACTAB ATC_MAT(0)
+#define ATC_MAT_NON_STATIC_MAC ATC_MAT(4)
enum mt7530_fdb_cmd {
MT7530_FDB_READ = 0,
@@ -171,32 +177,29 @@ enum mt7530_fdb_cmd {
/* Registers for table search read address */
#define MT7530_TSRA1 0x84
-#define MAC_BYTE_0 24
-#define MAC_BYTE_1 16
-#define MAC_BYTE_2 8
-#define MAC_BYTE_3 0
-#define MAC_BYTE_MASK 0xff
+#define MAC_BYTE_0_MASK GENMASK(31, 24)
+#define MAC_BYTE_1_MASK GENMASK(23, 16)
+#define MAC_BYTE_2_MASK GENMASK(15, 8)
+#define MAC_BYTE_3_MASK GENMASK(7, 0)
#define MT7530_TSRA2 0x88
-#define MAC_BYTE_4 24
-#define MAC_BYTE_5 16
-#define CVID 0
-#define CVID_MASK 0xfff
+#define MAC_BYTE_4_MASK GENMASK(31, 24)
+#define MAC_BYTE_5_MASK GENMASK(23, 16)
+#define CVID_MASK GENMASK(11, 0)
#define MT7530_ATRD 0x8C
-#define AGE_TIMER 24
-#define AGE_TIMER_MASK 0xff
-#define PORT_MAP 4
-#define PORT_MAP_MASK 0xff
-#define ENT_STATUS 2
-#define ENT_STATUS_MASK 0x3
+#define AGE_TIMER_MASK GENMASK(31, 24)
+#define PORT_MAP_MASK GENMASK(11, 4)
+#define ENT_STATUS_MASK GENMASK(3, 2)
/* Register for vlan table control */
#define MT7530_VTCR 0x90
#define VTCR_BUSY BIT(31)
#define VTCR_INVALID BIT(16)
-#define VTCR_FUNC(x) (((x) & 0xf) << 12)
-#define VTCR_VID ((x) & 0xfff)
+#define VTCR_FUNC_MASK GENMASK(15, 12)
+#define VTCR_FUNC(x) FIELD_PREP(VTCR_FUNC_MASK, x)
+#define VTCR_VID_MASK GENMASK(11, 0)
+#define VTCR_VID(x) FIELD_PREP(VTCR_VID_MASK, x)
enum mt7530_vlan_cmd {
/* Read/Write the specified VID entry from VAWD register based
@@ -216,13 +219,13 @@ enum mt7530_vlan_cmd {
/* Per VLAN Egress Tag Control */
#define VTAG_EN BIT(28)
/* VLAN Member Control */
-#define PORT_MEM(x) (((x) & 0xff) << 16)
+#define PORT_MEM_MASK GENMASK(23, 16)
+#define PORT_MEM(x) FIELD_PREP(PORT_MEM_MASK, x)
/* Filter ID */
-#define FID(x) (((x) & 0x7) << 1)
+#define FID_MASK GENMASK(3, 1)
+#define FID(x) FIELD_PREP(FID_MASK, x)
/* VLAN Entry Valid */
#define VLAN_VALID BIT(0)
-#define PORT_MEM_SHFT 16
-#define PORT_MEM_MASK 0xff
enum mt7530_fid {
FID_STANDALONE = 0,
@@ -247,11 +250,11 @@ enum mt7530_vlan_egress_attr {
/* Age count */
#define AGE_CNT_MASK GENMASK(19, 12)
#define AGE_CNT_MAX 0xff
-#define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12))
+#define AGE_CNT(x) FIELD_PREP(AGE_CNT_MASK, x)
/* Age unit */
#define AGE_UNIT_MASK GENMASK(11, 0)
#define AGE_UNIT_MAX 0xfff
-#define AGE_UNIT(x) (AGE_UNIT_MASK & (x))
+#define AGE_UNIT(x) FIELD_PREP(AGE_UNIT_MASK, x)
#define MT753X_ERLCR_P(x) (0x1040 + ((x) * 0x100))
#define ERLCR_CIR_MASK GENMASK(31, 16)
@@ -282,30 +285,31 @@ enum mt7530_stp_state {
#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
#define PORT_TX_MIR BIT(9)
#define PORT_RX_MIR BIT(8)
-#define PORT_VLAN(x) ((x) & 0x3)
+#define PCR_PORT_VLAN_MASK GENMASK(1, 0)
enum mt7530_port_mode {
/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
- MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
+ MT7530_PORT_MATRIX_MODE = 0,
/* Fallback Mode: Forward received frames with ingress ports that do
* not belong to the VLAN member. Frames whose VID is not listed on
* the VLAN table are forwarded by the PCR_MATRIX members.
*/
- MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
+ MT7530_PORT_FALLBACK_MODE = 1,
/* Security Mode: Discard any frame due to ingress membership
* violation or VID missed on the VLAN table.
*/
- MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
+ MT7530_PORT_SECURITY_MODE = 3,
};
-#define PCR_MATRIX(x) (((x) & 0xff) << 16)
-#define PORT_PRI(x) (((x) & 0x7) << 24)
-#define EG_TAG(x) (((x) & 0x3) << 28)
-#define PCR_MATRIX_MASK PCR_MATRIX(0xff)
+#define PCR_MATRIX_MASK GENMASK(23, 16)
+#define PCR_MATRIX(x) FIELD_PREP(PCR_MATRIX_MASK, x)
+#define PORT_PRI_MASK GENMASK(26, 24)
+#define PORT_PRI(x) FIELD_PREP(PORT_PRI_MASK, x)
+#define EG_TAG_MASK GENMASK(29, 28)
+#define EG_TAG(x) FIELD_PREP(EG_TAG_MASK, x)
#define PCR_MATRIX_CLR PCR_MATRIX(0)
-#define PCR_PORT_VLAN_MASK PORT_VLAN(3)
/* Register for port security control */
#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
@@ -314,10 +318,10 @@ enum mt7530_port_mode {
/* Register for port vlan control */
#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
#define PORT_SPEC_TAG BIT(5)
-#define PVC_EG_TAG(x) (((x) & 0x7) << 8)
-#define PVC_EG_TAG_MASK PVC_EG_TAG(7)
-#define VLAN_ATTR(x) (((x) & 0x3) << 6)
-#define VLAN_ATTR_MASK VLAN_ATTR(3)
+#define PVC_EG_TAG_MASK GENMASK(10, 8)
+#define PVC_EG_TAG(x) FIELD_PREP(PVC_EG_TAG_MASK, x)
+#define VLAN_ATTR_MASK GENMASK(7, 6)
+#define VLAN_ATTR(x) FIELD_PREP(VLAN_ATTR_MASK, x)
#define ACC_FRM_MASK GENMASK(1, 0)
enum mt7530_vlan_port_eg_tag {
@@ -337,12 +341,13 @@ enum mt7530_vlan_port_acc_frm {
MT7530_VLAN_ACC_UNTAGGED = 2,
};
-#define STAG_VPID (((x) & 0xffff) << 16)
+#define STAG_VPID_MASK GENMASK(31, 16)
+#define STAG_VPID(x) FIELD_PREP(STAG_VPID_MASK, x)
/* Register for port port-and-protocol based vlan 1 control */
#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
-#define G0_PORT_VID(x) (((x) & 0xfff) << 0)
-#define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
+#define G0_PORT_VID_MASK GENMASK(11, 0)
+#define G0_PORT_VID(x) FIELD_PREP(G0_PORT_VID_MASK, x)
#define G0_PORT_VID_DEF G0_PORT_VID(0)
/* Register for port MAC control register */
@@ -418,8 +423,8 @@ enum mt7530_vlan_port_acc_frm {
#define MT7531_DIS_CLR BIT(31)
#define MT7530_GMACCR 0x30e0
-#define MAX_RX_JUMBO(x) ((x) << 2)
#define MAX_RX_JUMBO_MASK GENMASK(5, 2)
+#define MAX_RX_JUMBO(x) FIELD_PREP(MAX_RX_JUMBO_MASK, x)
#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
#define MAX_RX_PKT_LEN_1522 0x0
#define MAX_RX_PKT_LEN_1536 0x1
@@ -505,16 +510,16 @@ enum mt7530_vlan_port_acc_frm {
/* Register for PHY Indirect Access Control */
#define MT7531_PHY_IAC 0x701C
#define MT7531_PHY_ACS_ST BIT(31)
-#define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
-#define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
-#define MT7531_MDIO_CMD_MASK (0x3 << 18)
-#define MT7531_MDIO_ST_MASK (0x3 << 16)
-#define MT7531_MDIO_RW_DATA_MASK (0xffff)
-#define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
-#define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
-#define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
-#define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
-#define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
+#define MT7531_MDIO_REG_ADDR_MASK GENMASK(29, 25)
+#define MT7531_MDIO_PHY_ADDR_MASK GENMASK(24, 20)
+#define MT7531_MDIO_CMD_MASK GENMASK(19, 18)
+#define MT7531_MDIO_ST_MASK GENMASK(17, 16)
+#define MT7531_MDIO_RW_DATA_MASK GENMASK(15, 0)
+#define MT7531_MDIO_REG_ADDR(x) FIELD_PREP(MT7531_MDIO_REG_ADDR_MASK, x)
+#define MT7531_MDIO_DEV_ADDR(x) FIELD_PREP(MT7531_MDIO_REG_ADDR_MASK, x)
+#define MT7531_MDIO_PHY_ADDR(x) FIELD_PREP(MT7531_MDIO_PHY_ADDR_MASK, x)
+#define MT7531_MDIO_CMD(x) FIELD_PREP(MT7531_MDIO_CMD_MASK, x)
+#define MT7531_MDIO_ST(x) FIELD_PREP(MT7531_MDIO_ST_MASK, x)
enum mt7531_phy_iac_cmd {
MT7531_MDIO_ADDR = 0,
@@ -542,14 +547,14 @@ enum mt7531_mdio_st {
/* Register for RGMII clock phase */
#define MT7531_CLKGEN_CTRL 0x7500
-#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
#define CLK_SKEW_OUT_MASK GENMASK(9, 8)
-#define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
+#define CLK_SKEW_OUT(x) FIELD_PREP(CLK_SKEW_OUT_MASK, x)
#define CLK_SKEW_IN_MASK GENMASK(7, 6)
+#define CLK_SKEW_IN(x) FIELD_PREP(CLK_SKEW_IN_MASK, x)
#define RXCLK_NO_DELAY BIT(5)
#define TXCLK_NO_REVERSE BIT(4)
-#define GP_MODE(x) (((x) & 0x3) << 1)
#define GP_MODE_MASK GENMASK(2, 1)
+#define GP_MODE(x) FIELD_PREP(GP_MODE_MASK, x)
#define GP_CLK_EN BIT(0)
enum mt7531_gp_mode {
@@ -599,8 +604,10 @@ enum mt7531_xtal_fsel {
#define PAD_MCM_SMI_EN BIT(0)
#define MT7530_IO_DRV_CR 0x7810
-#define P5_IO_CLK_DRV(x) ((x) & 0x3)
-#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
+#define P5_IO_CLK_DRV_MASK GENMASK(1, 0)
+#define P5_IO_CLK_DRV(x) FIELD_PREP(P5_IO_CLK_DRV_MASK, x)
+#define P5_IO_DATA_DRV_MASK GENMASK(5, 4)
+#define P5_IO_DATA_DRV(x) FIELD_PREP(P5_IO_DATA_DRV_MASK, x)
#define MT7531_CHIP_REV 0x781C
@@ -610,15 +617,15 @@ enum mt7531_xtal_fsel {
#define SW_PLLGP BIT(0)
#define MT7530_P6ECR 0x7830
-#define P6_INTF_MODE_MASK 0x3
-#define P6_INTF_MODE(x) ((x) & 0x3)
+#define P6_INTF_MODE_MASK GENMASK(1, 0)
+#define P6_INTF_MODE(x) FIELD_PREP(P6_INTF_MODE_MASK, x)
#define MT7531_PLLGP_CR0 0x78a8
#define RG_COREPLL_EN BIT(22)
-#define RG_COREPLL_POSDIV_S 23
-#define RG_COREPLL_POSDIV_M 0x3800000
-#define RG_COREPLL_SDM_PCW_S 1
-#define RG_COREPLL_SDM_PCW_M 0x3ffffe
+#define RG_COREPLL_POSDIV_MASK GENMASK(25, 23)
+#define RG_COREPLL_POSDIV(x) FIELD_PREP(RG_COREPLL_POSDIV_MASK, x)
+#define RG_COREPLL_SDM_PCW_MASK GENMASK(21, 1)
+#define RG_COREPLL_SDM_PCW(x) FIELD_PREP(RG_COREPLL_SDM_PCW_MASK, x)
#define RG_COREPLL_SDM_PCW_CHG BIT(0)
/* Registers for RGMII and SGMII PLL clock */
@@ -629,10 +636,10 @@ enum mt7531_xtal_fsel {
#define MT7530_TRGMII_RCK_CTRL 0x7a00
#define RX_RST BIT(31)
#define RXC_DQSISEL BIT(30)
-#define DQSI1_TAP_MASK (0x7f << 8)
-#define DQSI0_TAP_MASK 0x7f
-#define DQSI1_TAP(x) (((x) & 0x7f) << 8)
-#define DQSI0_TAP(x) ((x) & 0x7f)
+#define DQSI1_TAP_MASK GENMASK(14, 8)
+#define DQSI0_TAP_MASK GENMASK(6, 0)
+#define DQSI1_TAP(x) FIELD_PREP(DQSI1_TAP_MASK, x)
+#define DQSI0_TAP(x) FIELD_PREP(DQSI0_TAP_MASK, x)
#define MT7530_TRGMII_RCK_RTT 0x7a04
#define DQS1_GATE BIT(31)
@@ -641,8 +648,8 @@ enum mt7531_xtal_fsel {
#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
#define BSLIP_EN BIT(31)
#define EDGE_CHK BIT(30)
-#define RD_TAP_MASK 0x7f
-#define RD_TAP(x) ((x) & 0x7f)
+#define RD_TAP_MASK GENMASK(6, 0)
+#define RD_TAP(x) FIELD_PREP(RD_TAP_MASK, x)
#define MT7530_TRGMII_TXCTRL 0x7a40
#define TRAIN_TXEN BIT(31)
@@ -650,18 +657,23 @@ enum mt7531_xtal_fsel {
#define TX_RST BIT(28)
#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
-#define TD_DM_DRVP(x) ((x) & 0xf)
-#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
+#define TD_DM_DRVP_MASK GENMASK(3, 0)
+#define TD_DM_DRVP(x) FIELD_PREP(TD_DM_DRVP_MASK, x)
+#define TD_DM_DRVN_MASK GENMASK(7, 4)
+#define TD_DM_DRVN(x) FIELD_PREP(TD_DM_DRVN_MASK, x)
#define MT7530_TRGMII_TCK_CTRL 0x7a78
-#define TCK_TAP(x) (((x) & 0xf) << 8)
+#define TCK_TAP_MASK GENMASK(11, 8)
+#define TCK_TAP(x) FIELD_PREP(TCK_TAP_MASK, x)
#define MT7530_P5RGMIIRXCR 0x7b00
#define CSR_RGMII_EDGE_ALIGN BIT(8)
-#define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
+#define CSR_RGMII_RXC_0DEG_CFG_MASK GENMASK(3, 0)
+#define CSR_RGMII_RXC_0DEG_CFG(x) FIELD_PREP(CSR_RGMII_RXC_0DEG_CFG_MASK, x)
#define MT7530_P5RGMIITXCR 0x7b04
-#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
+#define CSR_RGMII_TXC_CFG_MASK GENMASK(4, 0)
+#define CSR_RGMII_TXC_CFG(x) FIELD_PREP(CSR_RGMII_TXC_CFG_MASK, x)
/* Registers for GPIO mode */
#define MT7531_GPIO_MODE0 0x7c0c
@@ -670,9 +682,9 @@ enum mt7531_xtal_fsel {
#define MT7531_GPIO_MODE1 0x7c10
#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
-#define MT7531_EXT_P_MDC_11 (2 << 12)
+#define MT7531_EXT_P_MDC_11 FIELD_PREP(MT7531_GPIO11_RG_RXD2_MASK, 2)
#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
-#define MT7531_EXT_P_MDIO_12 (2 << 16)
+#define MT7531_EXT_P_MDIO_12 FIELD_PREP(MT7531_GPIO12_RG_RXD3_MASK, 2)
#define MT753X_CPORT_SPTAG_CFG 0x7c10
#define CPORT_SW2FE_STAG_EN BIT(1)
@@ -704,7 +716,7 @@ enum mt7531_xtal_fsel {
#define MT7530_LED_GPIO_DATA 0x7d18
#define MT7530_CREV 0x7ffc
-#define CHIP_NAME_SHIFT 16
+#define CHIP_NAME_MASK GENMASK(31, 16)
#define MT7530_ID 0x7530
#define MT7531_CREV 0x781C
@@ -716,10 +728,13 @@ enum mt7531_xtal_fsel {
#define RG_SYSPLL_EN_NORMAL BIT(15)
#define RG_SYSPLL_VODEN BIT(14)
#define RG_SYSPLL_LF BIT(13)
-#define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
+#define RG_SYSPLL_RST_DLY_MASK GENMASK(13, 12)
+#define RG_SYSPLL_RST_DLY(x) FIELD_PREP(RG_SYSPLL_RST_DLY_MASK, x)
#define RG_SYSPLL_LVROD_EN BIT(10)
-#define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
-#define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
+#define RG_SYSPLL_PREDIV_MASK GENMASK(9, 8)
+#define RG_SYSPLL_PREDIV(x) FIELD_PREP(RG_SYSPLL_PREDIV_MASK, x)
+#define RG_SYSPLL_POSDIV_MASK GENMASK(6, 5)
+#define RG_SYSPLL_POSDIV(x) FIELD_PREP(RG_SYSPLL_POSDIV_MASK, x)
#define RG_SYSPLL_FBKSEL BIT(4)
#define RT_SYSPLL_EN_AFE_OLT BIT(0)
@@ -731,38 +746,48 @@ enum mt7531_xtal_fsel {
#define MT7531_PHY_PLL_OFF BIT(5)
#define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
-#define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f)
+#define MT753X_CTRL_PHY_ADDR(addr) (((addr) + 1) & (PHY_MAX_ADDR - 1))
#define CORE_PLL_GROUP5 0x404
-#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
+#define RG_LCDDS_PCW_NCPO1_MASK GENMASK(15, 0)
+#define RG_LCDDS_PCW_NCPO1(x) FIELD_PREP(RG_LCDDS_PCW_NCPO1_MASK, x)
#define CORE_PLL_GROUP6 0x405
-#define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
+#define RG_LCDDS_PCW_NCPO0_MASK GENMASK(15, 0)
+#define RG_LCDDS_PCW_NCPO0(x) FIELD_PREP(RG_LCDDS_PCW_NCPO0_MASK, x)
#define CORE_PLL_GROUP7 0x406
#define RG_LCDDS_PWDB BIT(15)
#define RG_LCDDS_ISO_EN BIT(13)
-#define RG_LCCDS_C(x) (((x) & 0x7) << 4)
+#define RG_LCCDS_C_MASK GENMASK(6, 4)
+#define RG_LCCDS_C(x) FIELD_PREP(RG_LCCDS_C_MASK, x)
#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
#define CORE_PLL_GROUP10 0x409
-#define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
+#define RG_LCDDS_SSC_DELTA_MASK GENMASK(11, 0)
+#define RG_LCDDS_SSC_DELTA(x) FIELD_PREP(RG_LCDDS_SSC_DELTA_MASK, x)
#define CORE_PLL_GROUP11 0x40a
-#define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
+#define RG_LCDDS_SSC_DELTA1_MASK GENMASK(11, 0)
+#define RG_LCDDS_SSC_DELTA1(x) FIELD_PREP(RG_LCDDS_SSC_DELTA1_MASK, x)
#define CORE_GSWPLL_GRP1 0x40d
-#define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
-#define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
+#define RG_GSWPLL_PREDIV_MASK GENMASK(15, 14)
+#define RG_GSWPLL_PREDIV(x) FIELD_PREP(RG_GSWPLL_PREDIV_MASK, x)
+#define RG_GSWPLL_POSDIV_200M_MASK GENMASK(13, 12)
+#define RG_GSWPLL_POSDIV_200M(x) FIELD_PREP(RG_GSWPLL_POSDIV_200M_MASK, x)
#define RG_GSWPLL_EN_PRE BIT(11)
#define RG_GSWPLL_FBKSEL BIT(10)
#define RG_GSWPLL_BP BIT(9)
#define RG_GSWPLL_BR BIT(8)
-#define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
+#define RG_GSWPLL_FBKDIV_200M_MASK GENMASK(7, 0)
+#define RG_GSWPLL_FBKDIV_200M(x) FIELD_PREP(RG_GSWPLL_FBKDIV_200M_MASK, x)
#define CORE_GSWPLL_GRP2 0x40e
-#define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
-#define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
+#define RG_GSWPLL_POSDIV_500M_MASK GENMASK(9, 8)
+#define RG_GSWPLL_POSDIV_500M(x) FIELD_PREP(RG_GSWPLL_POSDIV_500M_MASK, x)
+#define RG_GSWPLL_FBKDIV_500M_MASK GENMASK(7, 0)
+#define RG_GSWPLL_FBKDIV_500M(x) FIELD_PREP(RG_GSWPLL_FBKDIV_500M_MASK, x)
#define CORE_TRGMII_GSW_CLK_CG 0x410
#define REG_GSWCK_EN BIT(0)
|
| 3/2 | 2026/07/19 18:30 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 41847 output: 32 thoughts: 401 Thoughts: **Analyzing the MT7530 DSA Switch Driver Patch** Okay, so I've got this patch for the `mt7530` DSA switch driver. It looks like it's focused on refactoring the driver, specifically touching both `mt7530-mdio.c` and `mt7530.c`. My initial assessment is that they're aiming for a cleaner, more maintainable code base. It seems like the core of the change is replacing all the custom read/write functions – `mt7530_mii_read`, `mt7530_mii_write`, `mt7530_read`, `mt7530_write`, `mt7530_rmw`, `mt7530_set`, `mt7530_clear` – with the standard `regmap` API calls: `regmap_read`, `regmap_write`, `regmap_update_bits`, `regmap_set_bits`, and `regmap_clear_bits`. Good, that's a solid move; simplifies things and leverages the existing infrastructure. The other thing that immediately jumps out is the replacement of bitwise operations with `FIELD_GET` and `FIELD_PREP` from `linux/bitfield.h`. This is another welcome improvement – it makes the code more readable and less prone to bit-twiddling errors. Now, there are a couple of new functions introduced: `mt753x_port_change_conduit` and `mt7530_port_fast_age`. Hold on, let's see where those are used. Right, they're assigned to the `mt7530_switch_ops` struct. `mt753x_port_change_conduit` to `.port_change_conduit` and `mt7530_port_fast_age` to `.port_fast_age`. Those are functional changes, then. Need to dig into what those new operations do. Let me quickly verify where the driver itself is located. Okay, `drivers/net/dsa/mt7530.c`. And a quick grep of the `drivers/net/dsa/Kconfig` and `drivers/net/dsa/Makefile` to confirm the module build options and dependencies. |
| 4/2 | 2026/07/19 18:31 | tool | grepper |
0mArgs:{
"Expression": "mt7530",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "\nFull output is too long, showing 500 out of 1409 lines.\nUse more precise expression if possible.\n\ndrivers/net/dsa/Makefile=5=obj-$(CONFIG_NET_DSA_KS8995) \t+= ks8995.o\ndrivers/net/dsa/Makefile:6:obj-$(CONFIG_NET_DSA_MT7530)\t+= mt7530.o\ndrivers/net/dsa/Makefile:7:obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o\ndrivers/net/dsa/Makefile:8:obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o\ndrivers/net/dsa/Makefile-9-obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o\n--\ndrivers/net/dsa/mt7530-mdio.c-15-\ndrivers/net/dsa/mt7530-mdio.c:16:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530-mdio.c-17-\ndrivers/net/dsa/mt7530-mdio.c=18=static int\ndrivers/net/dsa/mt7530-mdio.c:19:mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)\ndrivers/net/dsa/mt7530-mdio.c-20-{\ndrivers/net/dsa/mt7530-mdio.c:21:\tstruct mt7530_priv *priv = context;\ndrivers/net/dsa/mt7530-mdio.c-22-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/net/dsa/mt7530-mdio.c=43=static int\ndrivers/net/dsa/mt7530-mdio.c:44:mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)\ndrivers/net/dsa/mt7530-mdio.c-45-{\ndrivers/net/dsa/mt7530-mdio.c:46:\tstruct mt7530_priv *priv = context;\ndrivers/net/dsa/mt7530-mdio.c-47-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/net/dsa/mt7530-mdio.c=69=static void\ndrivers/net/dsa/mt7530-mdio.c:70:mt7530_mdio_regmap_lock(void *mdio_lock)\ndrivers/net/dsa/mt7530-mdio.c-71-{\n--\ndrivers/net/dsa/mt7530-mdio.c=75=static void\ndrivers/net/dsa/mt7530-mdio.c:76:mt7530_mdio_regmap_unlock(void *mdio_lock)\ndrivers/net/dsa/mt7530-mdio.c-77-{\n--\ndrivers/net/dsa/mt7530-mdio.c-80-\ndrivers/net/dsa/mt7530-mdio.c:81:static const struct regmap_bus mt7530_regmap_bus = {\ndrivers/net/dsa/mt7530-mdio.c:82:\t.reg_write = mt7530_regmap_write,\ndrivers/net/dsa/mt7530-mdio.c:83:\t.reg_read = mt7530_regmap_read,\ndrivers/net/dsa/mt7530-mdio.c-84-};\n--\ndrivers/net/dsa/mt7530-mdio.c=86=static int\ndrivers/net/dsa/mt7530-mdio.c:87:mt7531_create_sgmii(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530-mdio.c-88-{\n--\ndrivers/net/dsa/mt7530-mdio.c-108-\t\tmt7531_pcs_config[i]-\u003emax_register = 0x17c;\ndrivers/net/dsa/mt7530-mdio.c:109:\t\tmt7531_pcs_config[i]-\u003elock = mt7530_mdio_regmap_lock;\ndrivers/net/dsa/mt7530-mdio.c:110:\t\tmt7531_pcs_config[i]-\u003eunlock = mt7530_mdio_regmap_unlock;\ndrivers/net/dsa/mt7530-mdio.c-111-\t\tmt7531_pcs_config[i]-\u003elock_arg = \u0026priv-\u003ebus-\u003emdio_lock;\ndrivers/net/dsa/mt7530-mdio.c-112-\ndrivers/net/dsa/mt7530-mdio.c:113:\t\tregmap = devm_regmap_init(priv-\u003edev, \u0026mt7530_regmap_bus, priv,\ndrivers/net/dsa/mt7530-mdio.c-114-\t\t\t\t\t mt7531_pcs_config[i]);\n--\ndrivers/net/dsa/mt7530-mdio.c-133-\ndrivers/net/dsa/mt7530-mdio.c:134:static const struct of_device_id mt7530_of_match[] = {\ndrivers/net/dsa/mt7530-mdio.c-135-\t{ .compatible = \"mediatek,mt7621\", .data = \u0026mt753x_table[ID_MT7621], },\ndrivers/net/dsa/mt7530-mdio.c:136:\t{ .compatible = \"mediatek,mt7530\", .data = \u0026mt753x_table[ID_MT7530], },\ndrivers/net/dsa/mt7530-mdio.c-137-\t{ .compatible = \"mediatek,mt7531\", .data = \u0026mt753x_table[ID_MT7531], },\n--\ndrivers/net/dsa/mt7530-mdio.c-139-};\ndrivers/net/dsa/mt7530-mdio.c:140:MODULE_DEVICE_TABLE(of, mt7530_of_match);\ndrivers/net/dsa/mt7530-mdio.c-141-\ndrivers/net/dsa/mt7530-mdio.c=142=static const struct regmap_config regmap_config = {\n--\ndrivers/net/dsa/mt7530-mdio.c-146-\t.max_register = MT7530_CREV,\ndrivers/net/dsa/mt7530-mdio.c:147:\t.lock = mt7530_mdio_regmap_lock,\ndrivers/net/dsa/mt7530-mdio.c:148:\t.unlock = mt7530_mdio_regmap_unlock,\ndrivers/net/dsa/mt7530-mdio.c-149-};\n--\ndrivers/net/dsa/mt7530-mdio.c=151=static int\ndrivers/net/dsa/mt7530-mdio.c:152:mt7530_probe(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-153-{\ndrivers/net/dsa/mt7530-mdio.c-154-\tstruct regmap_config rc = regmap_config;\ndrivers/net/dsa/mt7530-mdio.c:155:\tstruct mt7530_priv *priv;\ndrivers/net/dsa/mt7530-mdio.c-156-\tstruct device_node *dn;\n--\ndrivers/net/dsa/mt7530-mdio.c-168-\ndrivers/net/dsa/mt7530-mdio.c:169:\tret = mt7530_probe_common(priv);\ndrivers/net/dsa/mt7530-mdio.c-170-\tif (ret)\n--\ndrivers/net/dsa/mt7530-mdio.c-208-\trc.lock_arg = \u0026priv-\u003ebus-\u003emdio_lock;\ndrivers/net/dsa/mt7530-mdio.c:209:\tpriv-\u003eregmap = devm_regmap_init(priv-\u003edev, \u0026mt7530_regmap_bus,\ndrivers/net/dsa/mt7530-mdio.c-210-\t\t\t\t\tpriv, \u0026rc);\n--\ndrivers/net/dsa/mt7530-mdio.c=220=static void\ndrivers/net/dsa/mt7530-mdio.c:221:mt7530_remove(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-222-{\ndrivers/net/dsa/mt7530-mdio.c:223:\tstruct mt7530_priv *priv = dev_get_drvdata(\u0026mdiodev-\u003edev);\ndrivers/net/dsa/mt7530-mdio.c-224-\tint ret = 0, i;\n--\ndrivers/net/dsa/mt7530-mdio.c-238-\ndrivers/net/dsa/mt7530-mdio.c:239:\tmt7530_remove_common(priv);\ndrivers/net/dsa/mt7530-mdio.c-240-\n--\ndrivers/net/dsa/mt7530-mdio.c-244-\ndrivers/net/dsa/mt7530-mdio.c:245:static void mt7530_shutdown(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-246-{\ndrivers/net/dsa/mt7530-mdio.c:247:\tstruct mt7530_priv *priv = dev_get_drvdata(\u0026mdiodev-\u003edev);\ndrivers/net/dsa/mt7530-mdio.c-248-\n--\ndrivers/net/dsa/mt7530-mdio.c-256-\ndrivers/net/dsa/mt7530-mdio.c:257:static struct mdio_driver mt7530_mdio_driver = {\ndrivers/net/dsa/mt7530-mdio.c:258:\t.probe = mt7530_probe,\ndrivers/net/dsa/mt7530-mdio.c:259:\t.remove = mt7530_remove,\ndrivers/net/dsa/mt7530-mdio.c:260:\t.shutdown = mt7530_shutdown,\ndrivers/net/dsa/mt7530-mdio.c-261-\t.mdiodrv.driver = {\ndrivers/net/dsa/mt7530-mdio.c:262:\t\t.name = \"mt7530-mdio\",\ndrivers/net/dsa/mt7530-mdio.c:263:\t\t.of_match_table = mt7530_of_match,\ndrivers/net/dsa/mt7530-mdio.c-264-\t},\n--\ndrivers/net/dsa/mt7530-mdio.c-266-\ndrivers/net/dsa/mt7530-mdio.c:267:mdio_module_driver(mt7530_mdio_driver);\ndrivers/net/dsa/mt7530-mdio.c-268-\n--\ndrivers/net/dsa/mt7530-mmio.c-9-\ndrivers/net/dsa/mt7530-mmio.c:10:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530-mmio.c-11-\n--\ndrivers/net/dsa/mt7530-mmio.c=29=mt7988_probe(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-30-{\ndrivers/net/dsa/mt7530-mmio.c:31:\tstruct mt7530_priv *priv;\ndrivers/net/dsa/mt7530-mmio.c-32-\tvoid __iomem *base_addr;\n--\ndrivers/net/dsa/mt7530-mmio.c-41-\ndrivers/net/dsa/mt7530-mmio.c:42:\tret = mt7530_probe_common(priv);\ndrivers/net/dsa/mt7530-mmio.c-43-\tif (ret)\n--\ndrivers/net/dsa/mt7530-mmio.c=66=static void mt7988_remove(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-67-{\ndrivers/net/dsa/mt7530-mmio.c:68:\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\ndrivers/net/dsa/mt7530-mmio.c-69-\ndrivers/net/dsa/mt7530-mmio.c-70-\tif (priv)\ndrivers/net/dsa/mt7530-mmio.c:71:\t\tmt7530_remove_common(priv);\ndrivers/net/dsa/mt7530-mmio.c-72-}\n--\ndrivers/net/dsa/mt7530-mmio.c=74=static void mt7988_shutdown(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-75-{\ndrivers/net/dsa/mt7530-mmio.c:76:\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\ndrivers/net/dsa/mt7530-mmio.c-77-\n--\ndrivers/net/dsa/mt7530-mmio.c=86=static struct platform_driver mt7988_platform_driver = {\n--\ndrivers/net/dsa/mt7530-mmio.c-90-\t.driver = {\ndrivers/net/dsa/mt7530-mmio.c:91:\t\t.name = \"mt7530-mmio\",\ndrivers/net/dsa/mt7530-mmio.c-92-\t\t.of_match_table = mt7988_of_match,\n--\ndrivers/net/dsa/mt7530.c-25-\ndrivers/net/dsa/mt7530.c:26:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530.c-27-\n--\ndrivers/net/dsa/mt7530.c=31=static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)\n--\ndrivers/net/dsa/mt7530.c-36-/* String, offset, and register size in bytes if different from 4 bytes */\ndrivers/net/dsa/mt7530.c:37:static const struct mt7530_mib_desc mt7530_mib[] = {\ndrivers/net/dsa/mt7530.c-38-\tMIB_DESC(1, MT7530_PORT_MIB_TX_DROP, \"TxDrop\"),\n--\ndrivers/net/dsa/mt7530.c=49=static void\ndrivers/net/dsa/mt7530.c:50:mt7530_mutex_lock(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-51-{\n--\ndrivers/net/dsa/mt7530.c=56=static void\ndrivers/net/dsa/mt7530.c:57:mt7530_mutex_unlock(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-58-{\n--\ndrivers/net/dsa/mt7530.c=63=static void\ndrivers/net/dsa/mt7530.c:64:core_write(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-65-{\n--\ndrivers/net/dsa/mt7530.c-68-\ndrivers/net/dsa/mt7530.c:69:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-70-\n--\ndrivers/net/dsa/mt7530.c-95-\ndrivers/net/dsa/mt7530.c:96:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-97-}\n--\ndrivers/net/dsa/mt7530.c=99=static void\ndrivers/net/dsa/mt7530.c:100:core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)\ndrivers/net/dsa/mt7530.c-101-{\n--\ndrivers/net/dsa/mt7530.c-105-\ndrivers/net/dsa/mt7530.c:106:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-107-\n--\ndrivers/net/dsa/mt7530.c-137-\ndrivers/net/dsa/mt7530.c:138:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-139-}\n--\ndrivers/net/dsa/mt7530.c=141=static void\ndrivers/net/dsa/mt7530.c:142:core_set(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-143-{\n--\ndrivers/net/dsa/mt7530.c=147=static void\ndrivers/net/dsa/mt7530.c:148:core_clear(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-149-{\n--\ndrivers/net/dsa/mt7530.c=154=static u32\ndrivers/net/dsa/mt7530.c:155:mt7530_mii_poll(struct mt7530_dummy_poll *p)\ndrivers/net/dsa/mt7530.c-156-{\n--\ndrivers/net/dsa/mt7530.c=164=static int\ndrivers/net/dsa/mt7530.c:165:mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)\ndrivers/net/dsa/mt7530.c-166-{\n--\ndrivers/net/dsa/mt7530.c-168-\tint ret;\ndrivers/net/dsa/mt7530.c:169:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-170-\n--\ndrivers/net/dsa/mt7530.c-175-\tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7530_ATC);\ndrivers/net/dsa/mt7530.c:176:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-177-\t\t\t\t !(val \u0026 ATC_BUSY), 20, 20000);\n--\ndrivers/net/dsa/mt7530.c-195-\ndrivers/net/dsa/mt7530.c:196:static void mt7530_port_fast_age(struct dsa_switch *ds, int port)\ndrivers/net/dsa/mt7530.c-197-{\ndrivers/net/dsa/mt7530.c:198:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c:199:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-200-\tu32 val;\n--\ndrivers/net/dsa/mt7530.c-209-\tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7530_ATC);\ndrivers/net/dsa/mt7530.c:210:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-211-\t\t\t\t !(val \u0026 ATC_BUSY), 20, 20000);\n--\ndrivers/net/dsa/mt7530.c=218=static void\ndrivers/net/dsa/mt7530.c:219:mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)\ndrivers/net/dsa/mt7530.c-220-{\n--\ndrivers/net/dsa/mt7530.c=245=static void\ndrivers/net/dsa/mt7530.c:246:mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,\ndrivers/net/dsa/mt7530.c-247-\t\t u8 port_mask, const u8 *mac,\n--\ndrivers/net/dsa/mt7530.c-275-/* Set up switch core clock for MT7530 */\ndrivers/net/dsa/mt7530.c:276:static void mt7530_pll_setup(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-277-{\n--\ndrivers/net/dsa/mt7530.c=316=static void\ndrivers/net/dsa/mt7530.c:317:mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)\ndrivers/net/dsa/mt7530.c-318-{\ndrivers/net/dsa/mt7530.c:319:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c-320-\tu32 ncpo1, ssc_delta, xtal;\n--\ndrivers/net/dsa/mt7530.c=371=static void\ndrivers/net/dsa/mt7530.c:372:mt7531_pll_setup(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-373-{\n--\ndrivers/net/dsa/mt7530.c=459=static void\ndrivers/net/dsa/mt7530.c:460:mt7530_mib_reset(struct dsa_switch *ds)\ndrivers/net/dsa/mt7530.c-461-{\ndrivers/net/dsa/mt7530.c:462:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c-463-\n--\ndrivers/net/dsa/mt7530.c-467-\ndrivers/net/dsa/mt7530.c:468:static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)\ndrivers/net/dsa/mt7530.c-469-{\n--\ndrivers/net/dsa/mt7530.c-472-\ndrivers/net/dsa/mt7530.c:473:static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum,\ndrivers/net/dsa/mt7530.c-474-\t\t\t\tu16 val)\n--\ndrivers/net/dsa/mt7530.c-478-\ndrivers/net/dsa/mt7530.c:479:static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port,\ndrivers/net/dsa/mt7530.c-480-\t\t\t int devad, int regnum)\n--\ndrivers/net/dsa/mt7530.c-484-\ndrivers/net/dsa/mt7530.c:485:static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-486-\t\t\t\tint regnum, u16 val)\n--\ndrivers/net/dsa/mt7530.c=491=static int\ndrivers/net/dsa/mt7530.c:492:mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-493-\t\t\tint regnum)\ndrivers/net/dsa/mt7530.c-494-{\ndrivers/net/dsa/mt7530.c:495:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-496-\tu32 reg, val;\n--\ndrivers/net/dsa/mt7530.c-502-\ndrivers/net/dsa/mt7530.c:503:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-504-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-513-\ndrivers/net/dsa/mt7530.c:514:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-515-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-524-\ndrivers/net/dsa/mt7530.c:525:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-526-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c=539=static int\ndrivers/net/dsa/mt7530.c:540:mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-541-\t\t\t int regnum, u16 data)\ndrivers/net/dsa/mt7530.c-542-{\ndrivers/net/dsa/mt7530.c:543:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-544-\tu32 val, reg;\n--\ndrivers/net/dsa/mt7530.c-550-\ndrivers/net/dsa/mt7530.c:551:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-552-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-561-\ndrivers/net/dsa/mt7530.c:562:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-563-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-572-\ndrivers/net/dsa/mt7530.c:573:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-574-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c=586=static int\ndrivers/net/dsa/mt7530.c:587:mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)\ndrivers/net/dsa/mt7530.c-588-{\ndrivers/net/dsa/mt7530.c:589:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-590-\tint ret;\n--\ndrivers/net/dsa/mt7530.c-596-\ndrivers/net/dsa/mt7530.c:597:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-598-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-608-\ndrivers/net/dsa/mt7530.c:609:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, val,\ndrivers/net/dsa/mt7530.c-610-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c=623=static int\ndrivers/net/dsa/mt7530.c:624:mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,\ndrivers/net/dsa/mt7530.c-625-\t\t\t u16 data)\ndrivers/net/dsa/mt7530.c-626-{\ndrivers/net/dsa/mt7530.c:627:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-628-\tint ret;\n--\ndrivers/net/dsa/mt7530.c-634-\ndrivers/net/dsa/mt7530.c:635:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, reg,\ndrivers/net/dsa/mt7530.c-636-\t\t\t\t !(reg \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-646-\ndrivers/net/dsa/mt7530.c:647:\tret = readx_poll_timeout(mt7530_mii_poll, \u0026p, reg,\ndrivers/net/dsa/mt7530.c-648-\t\t\t\t !(reg \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c=661=mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum)\ndrivers/net/dsa/mt7530.c-662-{\ndrivers/net/dsa/mt7530.c:663:\tstruct mt7530_priv *priv = bus-\u003epriv;\ndrivers/net/dsa/mt7530.c-664-\n--\ndrivers/net/dsa/mt7530.c=669=mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum)\ndrivers/net/dsa/mt7530.c-670-{\ndrivers/net/dsa/mt7530.c:671:\tstruct mt7530_priv *priv = bus-\u003epriv;\ndrivers/net/dsa/mt7530.c-672-\n--\ndrivers/net/dsa/mt7530.c=677=mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val)\ndrivers/net/dsa/mt7530.c-678-{\ndrivers/net/dsa/mt7530.c:679:\tstruct mt7530_priv *priv = bus-\u003epriv;\ndrivers/net/dsa/mt7530.c-680-\n--\ndrivers/net/dsa/mt7530.c=685=mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum,\n--\ndrivers/net/dsa/mt7530.c-687-{\ndrivers/net/dsa/mt7530.c:688:\tstruct mt7530_priv *priv = bus-\u003epriv;\ndrivers/net/dsa/mt7530.c-689-\n--\ndrivers/net/dsa/mt7530.c=693=static void\ndrivers/net/dsa/mt7530.c:694:mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,\ndrivers/net/dsa/mt7530.c-695-\t\t uint8_t *data)\n--\ndrivers/net/dsa/mt7530.c-701-\ndrivers/net/dsa/mt7530.c:702:\tfor (i = 0; i \u003c ARRAY_SIZE(mt7530_mib); i++)\ndrivers/net/dsa/mt7530.c:703:\t\tethtool_puts(\u0026data, mt7530_mib[i].name);\ndrivers/net/dsa/mt7530.c-704-}\n--\ndrivers/net/dsa/mt7530.c=706=static void\ndrivers/net/dsa/mt7530.c:707:mt7530_read_port_stats(struct mt7530_priv *priv, int port,\ndrivers/net/dsa/mt7530.c-708-\t\t u32 offset, u8 size, uint64_t *data)\n--\ndrivers/net/dsa/mt7530.c=721=static void\ndrivers/net/dsa/mt7530.c:722:mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,\ndrivers/net/dsa/mt7530.c-723-\t\t\t uint64_t *data)\ndrivers/net/dsa/mt7530.c-724-{\ndrivers/net/dsa/mt7530.c:725:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c:726:\tconst struct mt7530_mib_desc *mib;\ndrivers/net/dsa/mt7530.c-727-\tint i;\ndrivers/net/dsa/mt7530.c-728-\ndrivers/net/dsa/mt7530.c:729:\tfor (i = 0; i \u003c ARRAY_SIZE(mt7530_mib); i++) {\ndrivers/net/dsa/mt7530.c:730:\t\tmib = \u0026mt7530_mib[i];\ndrivers/net/dsa/mt7530.c-731-\ndrivers/net/dsa/mt7530.c:732:\t\tmt7530_read_port_stats(priv, port, mib-\u003eoffset, mib-\u003esize,\ndrivers/net/dsa/mt7530.c-733-\t\t\t\t data + i);\n--\ndrivers/net/dsa/mt7530.c=737=static int\ndrivers/net/dsa/mt7530.c:738:mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)\ndrivers/net/dsa/mt7530.c-739-{\n--\ndrivers/net/dsa/mt7530.c-742-\ndrivers/net/dsa/mt7530.c:743:\treturn ARRAY_SIZE(mt7530_mib);\ndrivers/net/dsa/mt7530.c-744-}\ndrivers/net/dsa/mt7530.c-745-\ndrivers/net/dsa/mt7530.c:746:static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port,\ndrivers/net/dsa/mt7530.c-747-\t\t\t\t struct ethtool_eth_mac_stats *mac_stats)\ndrivers/net/dsa/mt7530.c-748-{\ndrivers/net/dsa/mt7530.c:749:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c-750-\n--\ndrivers/net/dsa/mt7530.c-755-\t */\ndrivers/net/dsa/mt7530.c:756:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,\ndrivers/net/dsa/mt7530.c-757-\t\t\t \u0026mac_stats-\u003eFramesTransmittedOK);\ndrivers/net/dsa/mt7530.c-758-\ndrivers/net/dsa/mt7530.c:759:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1,\ndrivers/net/dsa/mt7530.c-760-\t\t\t \u0026mac_stats-\u003eSingleCollisionFrames);\ndrivers/net/dsa/mt7530.c-761-\ndrivers/net/dsa/mt7530.c:762:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1,\ndrivers/net/dsa/mt7530.c-763-\t\t\t \u0026mac_stats-\u003eMultipleCollisionFrames);\ndrivers/net/dsa/mt7530.c-764-\ndrivers/net/dsa/mt7530.c:765:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,\ndrivers/net/dsa/mt7530.c-766-\t\t\t \u0026mac_stats-\u003eFramesReceivedOK);\ndrivers/net/dsa/mt7530.c-767-\ndrivers/net/dsa/mt7530.c:768:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,\ndrivers/net/dsa/mt7530.c-769-\t\t\t \u0026mac_stats-\u003eOctetsTransmittedOK);\ndrivers/net/dsa/mt7530.c-770-\ndrivers/net/dsa/mt7530.c:771:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1,\ndrivers/net/dsa/mt7530.c-772-\t\t\t \u0026mac_stats-\u003eAlignmentErrors);\ndrivers/net/dsa/mt7530.c-773-\ndrivers/net/dsa/mt7530.c:774:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1,\ndrivers/net/dsa/mt7530.c-775-\t\t\t \u0026mac_stats-\u003eFramesWithDeferredXmissions);\ndrivers/net/dsa/mt7530.c-776-\ndrivers/net/dsa/mt7530.c:777:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1,\ndrivers/net/dsa/mt7530.c-778-\t\t\t \u0026mac_stats-\u003eLateCollisions);\ndrivers/net/dsa/mt7530.c-779-\ndrivers/net/dsa/mt7530.c:780:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1,\ndrivers/net/dsa/mt7530.c-781-\t\t\t \u0026mac_stats-\u003eFramesAbortedDueToXSColls);\ndrivers/net/dsa/mt7530.c-782-\ndrivers/net/dsa/mt7530.c:783:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,\ndrivers/net/dsa/mt7530.c-784-\t\t\t \u0026mac_stats-\u003eOctetsReceivedOK);\ndrivers/net/dsa/mt7530.c-785-\ndrivers/net/dsa/mt7530.c:786:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,\ndrivers/net/dsa/mt7530.c-787-\t\t\t \u0026mac_stats-\u003eMulticastFramesXmittedOK);\ndrivers/net/dsa/mt7530.c-788-\tmac_stats-\u003eFramesTransmittedOK += mac_stats-\u003eMulticastFramesXmittedOK;\ndrivers/net/dsa/mt7530.c:789:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,\ndrivers/net/dsa/mt7530.c-790-\t\t\t \u0026mac_stats-\u003eBroadcastFramesXmittedOK);\n--\ndrivers/net/dsa/mt7530.c-792-\ndrivers/net/dsa/mt7530.c:793:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,\ndrivers/net/dsa/mt7530.c-794-\t\t\t \u0026mac_stats-\u003eMulticastFramesReceivedOK);\ndrivers/net/dsa/mt7530.c-795-\tmac_stats-\u003eFramesReceivedOK += mac_stats-\u003eMulticastFramesReceivedOK;\ndrivers/net/dsa/mt7530.c:796:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,\ndrivers/net/dsa/mt7530.c-797-\t\t\t \u0026mac_stats-\u003eBroadcastFramesReceivedOK);\n--\ndrivers/net/dsa/mt7530.c-800-\ndrivers/net/dsa/mt7530.c:801:static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = {\ndrivers/net/dsa/mt7530.c-802-\t{ 0, 64 },\n--\ndrivers/net/dsa/mt7530.c-810-\ndrivers/net/dsa/mt7530.c:811:static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port,\ndrivers/net/dsa/mt7530.c-812-\t\t\t\t struct ethtool_rmon_stats *rmon_stats,\n--\ndrivers/net/dsa/mt7530.c-814-{\ndrivers/net/dsa/mt7530.c:815:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c-816-\ndrivers/net/dsa/mt7530.c:817:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1,\ndrivers/net/dsa/mt7530.c-818-\t\t\t \u0026rmon_stats-\u003eundersize_pkts);\ndrivers/net/dsa/mt7530.c:819:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1,\ndrivers/net/dsa/mt7530.c-820-\t\t\t \u0026rmon_stats-\u003eoversize_pkts);\ndrivers/net/dsa/mt7530.c:821:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1,\ndrivers/net/dsa/mt7530.c-822-\t\t\t \u0026rmon_stats-\u003efragments);\ndrivers/net/dsa/mt7530.c:823:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1,\ndrivers/net/dsa/mt7530.c-824-\t\t\t \u0026rmon_stats-\u003ejabbers);\ndrivers/net/dsa/mt7530.c-825-\ndrivers/net/dsa/mt7530.c:826:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1,\ndrivers/net/dsa/mt7530.c-827-\t\t\t \u0026rmon_stats-\u003ehist[0]);\ndrivers/net/dsa/mt7530.c:828:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1,\ndrivers/net/dsa/mt7530.c-829-\t\t\t \u0026rmon_stats-\u003ehist[1]);\ndrivers/net/dsa/mt7530.c:830:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1,\ndrivers/net/dsa/mt7530.c-831-\t\t\t \u0026rmon_stats-\u003ehist[2]);\ndrivers/net/dsa/mt7530.c:832:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1,\ndrivers/net/dsa/mt7530.c-833-\t\t\t \u0026rmon_stats-\u003ehist[3]);\ndrivers/net/dsa/mt7530.c:834:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1,\ndrivers/net/dsa/mt7530.c-835-\t\t\t \u0026rmon_stats-\u003ehist[4]);\ndrivers/net/dsa/mt7530.c:836:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1,\ndrivers/net/dsa/mt7530.c-837-\t\t\t \u0026rmon_stats-\u003ehist[5]);\ndrivers/net/dsa/mt7530.c-838-\ndrivers/net/dsa/mt7530.c:839:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1,\ndrivers/net/dsa/mt7530.c-840-\t\t\t \u0026rmon_stats-\u003ehist_tx[0]);\ndrivers/net/dsa/mt7530.c:841:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1,\ndrivers/net/dsa/mt7530.c-842-\t\t\t \u0026rmon_stats-\u003ehist_tx[1]);\ndrivers/net/dsa/mt7530.c:843:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1,\ndrivers/net/dsa/mt7530.c-844-\t\t\t \u0026rmon_stats-\u003ehist_tx[2]);\ndrivers/net/dsa/mt7530.c:845:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1,\ndrivers/net/dsa/mt7530.c-846-\t\t\t \u0026rmon_stats-\u003ehist_tx[3]);\ndrivers/net/dsa/mt7530.c:847:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1,\ndrivers/net/dsa/mt7530.c-848-\t\t\t \u0026rmon_stats-\u003ehist_tx[4]);\ndrivers/net/dsa/mt7530.c:849:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1,\ndrivers/net/dsa/mt7530.c-850-\t\t\t \u0026rmon_stats-\u003ehist_tx[5]);\ndrivers/net/dsa/mt7530.c-851-\ndrivers/net/dsa/mt7530.c:852:\t*ranges = mt7530_rmon_ranges;\ndrivers/net/dsa/mt7530.c-853-}\ndrivers/net/dsa/mt7530.c-854-\ndrivers/net/dsa/mt7530.c:855:static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port,\ndrivers/net/dsa/mt7530.c-856-\t\t\t\t struct rtnl_link_stats64 *storage)\n--\ndrivers/net/dsa/mt7530.c-864-\t */\ndrivers/net/dsa/mt7530.c:865:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,\ndrivers/net/dsa/mt7530.c-866-\t\t\t \u0026storage-\u003erx_packets);\ndrivers/net/dsa/mt7530.c:867:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,\ndrivers/net/dsa/mt7530.c-868-\t\t\t \u0026storage-\u003emulticast);\ndrivers/net/dsa/mt7530.c-869-\tstorage-\u003erx_packets += storage-\u003emulticast;\ndrivers/net/dsa/mt7530.c:870:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,\ndrivers/net/dsa/mt7530.c-871-\t\t\t \u0026data);\n--\ndrivers/net/dsa/mt7530.c-873-\ndrivers/net/dsa/mt7530.c:874:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,\ndrivers/net/dsa/mt7530.c-875-\t\t\t \u0026storage-\u003etx_packets);\ndrivers/net/dsa/mt7530.c:876:\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,\ndrivers/net/dsa/mt7530.c-877-\t\t\t \u0026data);\n\n"
} |
| 5/2 | 2026/07/19 18:31 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 57148 output: 39 thoughts: 52 Thoughts: Okay, here's my take on those thoughts, framed as my own mental processing: **Examining the MT7530 Switch Driver Configuration** Right, so the system indicates the MT7530 switch driver is enabled via `CONFIG_NET_DSA_MT7530`. Naturally, my first step is to dig into the dependencies and requirements of that configuration option. I need to understand the full context. That means heading straight over to `drivers/net/dsa/Kconfig`. I'll cross-reference `CONFIG_NET_DSA_MT7530` within that file, see what other options it pulls in, what architecture dependencies it has, and any specific hardware considerations or prerequisites. Understanding the Kconfig dependencies is absolutely crucial for proper device integration and a full understanding of the driver's behaviour. |
| 6/2 | 2026/07/19 18:31 | tool | grepper |
0mArgs:{
"Expression": "config NET_DSA_MT7530",
"PathPrefix": "drivers/net/dsa/Kconfig"
}Results: {
"Output": "drivers/net/dsa/Kconfig=29=source \"drivers/net/dsa/lantiq/Kconfig\"\ndrivers/net/dsa/Kconfig-30-\ndrivers/net/dsa/Kconfig:31:config NET_DSA_MT7530\ndrivers/net/dsa/Kconfig-32-\ttristate \"MediaTek MT7530 and MT7531 Ethernet switch support\"\n--\ndrivers/net/dsa/Kconfig-42-\ndrivers/net/dsa/Kconfig:43:config NET_DSA_MT7530_MDIO\ndrivers/net/dsa/Kconfig-44-\ttristate \"MediaTek MT7530 MDIO interface driver\"\n--\ndrivers/net/dsa/Kconfig-53-\ndrivers/net/dsa/Kconfig:54:config NET_DSA_MT7530_MMIO\ndrivers/net/dsa/Kconfig-55-\ttristate \"MediaTek MT7530 MMIO interface driver\"\n"
} |
| 7/2 | 2026/07/19 18:31 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 57678 output: 36 thoughts: 21 Thoughts: Here's my take on the thought process, summarized as you requested: **Kconfig Dive for DSA Networking Drivers** Okay, time to dig into the `drivers/net/dsa/Kconfig` file. I'm specifically interested in line 31, which is where the heart of many networking drivers reside. This is where the configuration options for Distributed Switch Architecture (DSA) networking devices are likely defined, and I suspect some crucial variables are there. I need to refresh my memory on what options are available and how they're structured within the Kconfig system. This should give me a solid foundation for understanding the device drivers available and the configurations associated with them. Hopefully, this Kconfig file offers clues to device dependencies and limitations, or even opportunities for optimization, that are related to the Linux kernel. |
| 8/2 | 2026/07/19 18:31 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/Kconfig",
"FirstLine": 31,
"LineCount": 30
}Results: {
"Contents": " 31:\tconfig NET_DSA_MT7530\n 32:\t\ttristate \"MediaTek MT7530 and MT7531 Ethernet switch support\"\n 33:\t\tselect NET_DSA_TAG_MTK\n 34:\t\tselect REGMAP_IRQ\n 35:\t\timply NET_DSA_MT7530_MDIO\n 36:\t\timply NET_DSA_MT7530_MMIO\n 37:\t\thelp\n 38:\t\t This enables support for the MediaTek MT7530 and MT7531 Ethernet\n 39:\t\t switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,\n 40:\t\t MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are\n 41:\t\t supported as well.\n 42:\t\n 43:\tconfig NET_DSA_MT7530_MDIO\n 44:\t\ttristate \"MediaTek MT7530 MDIO interface driver\"\n 45:\t\tdepends on NET_DSA_MT7530\n 46:\t\tselect MEDIATEK_GE_PHY\n 47:\t\tselect PCS_MTK_LYNXI\n 48:\t\thelp\n 49:\t\t This enables support for the MediaTek MT7530 and MT7531 switch\n 50:\t\t chips which are connected via MDIO, as well as multi-chip\n 51:\t\t module MT7530 which can be found in the MT7621AT, MT7621DAT,\n 52:\t\t MT7621ST and MT7623AI SoCs.\n 53:\t\n 54:\tconfig NET_DSA_MT7530_MMIO\n 55:\t\ttristate \"MediaTek MT7530 MMIO interface driver\"\n 56:\t\tdepends on NET_DSA_MT7530\n 57:\t\tdepends on HAS_IOMEM\n 58:\t\timply MEDIATEK_GE_SOC_PHY\n 59:\t\thelp\n 60:\t\t This enables support for the built-in Ethernet switch found\n"
} |
| 9/2 | 2026/07/19 18:31 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 58464 output: 129 thoughts: 1661 Thoughts: **Patch Analysis: MediaTek MT7530 Switch Driver** Okay, let's break this down. From a configuration standpoint, `NET_DSA_MT7530` is the core, and the interface drivers are `NET_DSA_MT7530_MDIO` and likely `NET_DSA_MT7530_MMIO`, although the latter isn't explicitly mentioned, I'm inferring it. Since the patch touches `mt7530-mdio.c` and `mt7530.c`, I'll want to ensure both `NET_DSA_MT7530` and `NET_DSA_MT7530_MDIO` are enabled. Now, where are the key changes? The patch introduces `mt753x_port_change_conduit` and `mt7530_port_fast_age`. These are immediate candidates for deeper inspection, and worth prioritizing for fuzzing. However, it looks like there are significant changes to the register access logic as well. The patch's core function appears to be switching from custom `mt7530_read`/`mt7530_write` functions to the `regmap_read`/`regmap_write` API. This is significant because it shifts the locking mechanism and error handling to the `regmap` framework. This introduces a major functional change. Let me confirm the reachability of these new functions. Ah, yes, `mt753x_port_change_conduit` and `mt7530_port_fast_age` are registered in `mt7530_switch_ops`. Specifically, `mt7530_switch_ops.port_change_conduit` is called by the DSA core when the conduit setting changes, and `mt7530_switch_ops.port_fast_age` is called by the DSA core as well. The patch includes other modifications to functions like `mt7530_fdb_cmd`, `mt7530_fdb_read`, `mt7530_fdb_write`, `mt7530_vlan_cmd`, `mt7530_hw_vlan_add`, `mt7530_hw_vlan_del`, and `mt7530_hw_vlan_update`. Since the core function of `regmap` API changes are happening throughout the driver, I'm going to want to prioritize these as well. Wait, and there's a functional change in `mt7530-mdio.c`: the `mt7530_regmap_read` function has a change in the way it handles errors, which is important to consider. Therefore, this is a clear candidate for fuzzing due to the functional changes in register access and the addition of these new functions within the switch operations. **My Recommended Fuzzing Parameters:** * **WorthFuzzing:** True * **EnableConfigs:** `NET_DSA_MT7530`, `NET_DSA_MT7530_MDIO` * **FocusSymbols:** `mt753x_port_change_conduit`, `mt7530_port_fast_age`, and all the `mt7530_fdb` and `mt7530_vlan` functions, as well as considering the implications of the `regmap` changes throughout the driver. * **Reasoning:** The patch fundamentally changes how registers are accessed, introducing `regmap` with its own locking and error handling. It also adds new DSA switch operations. These are substantial changes that warrant thorough testing. |
| 10/2 | 2026/07/19 18:31 | tool | set-results |
0mArgs:{
"EnableConfigs": [
"NET_DSA_MT7530",
"NET_DSA_MT7530_MDIO"
],
"FocusSymbols": [
"mt753x_port_change_conduit",
"mt7530_port_fast_age"
],
"Reasoning": "The patch replaces custom register access functions with the regmap API, which changes locking and error handling behavior. It also adds new DSA switch operations `port_change_conduit` and `port_fast_age`.",
"WorthFuzzing": true
}Results: {
"EnableConfigs": [
"NET_DSA_MT7530",
"NET_DSA_MT7530_MDIO"
],
"FocusSymbols": [
"mt753x_port_change_conduit",
"mt7530_port_fast_age"
],
"Reasoning": "The patch replaces custom register access functions with the regmap API, which changes locking and error handling behavior. It also adds new DSA switch operations `port_change_conduit` and `port_fast_age`.",
"WorthFuzzing": true
} |
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