| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/09/20 00:17 | flow | patch-triage |
1mArgs:null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"KMSANReasoning": "",
"NeedsKMSAN": false,
"Reasoning": "The patch adds cros_typec_altmodes_stop() to cros_unregister_ports() in drivers/platform/chrome/cros_ec_typec.c and cros_typec_altmode.c. This driver requires ChromeOS Embedded Controller hardware (probed via ACPI GOOG0014 or ChromeOS Devicetree), which is not present or emulated in standard QEMU/GCE virtualized environments. Additionally, the modified logic resides strictly in probe error and driver teardown cleanup paths. Consequently, the modified code is structurally unreachable for syzkaller fuzzing.",
"WorthFuzzing": false
} |
| 1/1 | 2026/09/20 00:17 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit 8c83adeab6b9c04475825ae8531d9bf894b4a110\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Sun Sep 20 00:17:10 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c\nindex 50a68819ceb7b..e91bbc219c077 100644\n--- a/drivers/platform/chrome/cros_ec_typec.c\n+++ b/drivers/platform/chrome/cros_ec_typec.c\n@@ -378,6 +378,7 @@ static void cros_unregister_ports(struct cros_typec_data *typec)\n \t\tif (!typec-\u003eports[i])\n \t\t\tcontinue;\n \n+\t\tcros_typec_altmodes_stop(typec-\u003eports[i]);\n \t\tcros_typec_remove_partner(typec, i);\n \t\tcros_typec_remove_cable(typec, i);\n \ndiff --git a/drivers/platform/chrome/cros_typec_altmode.c b/drivers/platform/chrome/cros_typec_altmode.c\nindex 66c546bf89b53..2492058d98b8e 100644\n--- a/drivers/platform/chrome/cros_typec_altmode.c\n+++ b/drivers/platform/chrome/cros_typec_altmode.c\n@@ -37,6 +37,21 @@ struct cros_typec_dp_data {\n \tbool pending_status_update;\n };\n \n+void cros_typec_altmodes_stop(struct cros_typec_port *port)\n+{\n+\tstruct cros_typec_altmode_data *adata;\n+\tint i;\n+\n+\tfor (i = 0; i \u003c CROS_EC_ALTMODE_MAX; i++) {\n+\t\tif (!port-\u003eport_altmode[i])\n+\t\t\tcontinue;\n+\n+\t\tadata = typec_altmode_get_drvdata(port-\u003eport_altmode[i]);\n+\t\tif (adata)\n+\t\t\tdisable_work_sync(\u0026adata-\u003ework);\n+\t}\n+}\n+\n static void cros_typec_altmode_work(struct work_struct *work)\n {\n \tstruct cros_typec_altmode_data *data =\ndiff --git a/drivers/platform/chrome/cros_typec_altmode.h b/drivers/platform/chrome/cros_typec_altmode.h\nindex 3f2aa95d065af..9e67f82ba031d 100644\n--- a/drivers/platform/chrome/cros_typec_altmode.h\n+++ b/drivers/platform/chrome/cros_typec_altmode.h\n@@ -11,6 +11,12 @@ struct typec_altmode;\n struct typec_altmode_desc;\n struct typec_displayport_data;\n \n+#if IS_ENABLED(CONFIG_CROS_EC_TYPEC_ALTMODES)\n+void cros_typec_altmodes_stop(struct cros_typec_port *port);\n+#else\n+static inline void cros_typec_altmodes_stop(struct cros_typec_port *port) {}\n+#endif\n+\n #if IS_ENABLED(CONFIG_TYPEC_DP_ALTMODE)\n struct typec_altmode *\n cros_typec_register_displayport(struct cros_typec_port *port,\n"
} |
| 2/1 | 2026/09/20 00:17 | agent | patch-evaluator |
1mModel:core Args: null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch adds cros_typec_altmodes_stop() to cros_unregister_ports() in drivers/platform/chrome/cros_ec_typec.c and cros_typec_altmode.c. This driver requires ChromeOS Embedded Controller hardware (probed via ACPI GOOG0014 or ChromeOS Devicetree), which is not present or emulated in standard QEMU/GCE virtualized environments. Additionally, the modified logic resides strictly in probe error and driver teardown cleanup paths. Consequently, the modified code is structurally unreachable for syzkaller fuzzing.",
"WorthFuzzing": false
}Instruction: You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.
IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.
================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.
- REACHABILITY IS THE PRIMARY GATE:
Fuzzing can only discover bugs in code that can actually execute in standard virtualized
environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
regardless of whether it adds assertions or complex logic.
- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
Patch authors routinely label changes as "cleanups", "refactorings", or state
"No functional change intended". Do NOT take these claims at face value.
Code refactorings that rearrange logic, introduce helper functions, or alter state management
in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
If reachable executable code is modified or refactored, it MUST be fuzzed.
- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
Even if the author believes the invariant always holds, fuzzing is essential to verify whether
an unusual sequence of operations can violate it.
================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:
- Non-kernel and non-executable changes:
* Modifications to Documentation/, comments, or spelling fixes.
* User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
that do not affect the compiled kernel image (vmlinux) or kernel modules.
* Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
that do not alter control flow or data structures.
* Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
* Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
* Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
physical PCI hot-unplug or manual sysfs driver unbinding.
* Code paths exclusive to architectures other than the target architecture.
================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
* Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
* Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
* Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
* Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).
================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:
- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
Do NOT list generic, ubiquitous functions called by almost every program in the corpus
(including, but not limited to: general memory allocators and deallocators, page fault
and trap handlers, or core synchronization primitives; this is not an exhaustive list).
Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
which severely dilutes fuzzing effort away from the actual changes.
- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
List functions that specifically implement the logic being added or altered, or direct API entrypoints
for the subsystem feature under review.
- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).
================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.
Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.
Prompt: Target architecture: amd64
For your convenience, here is the diff of the changes:
commit 8c83adeab6b9c04475825ae8531d9bf894b4a110
Author: syz-cluster <triage@syzkaller.com>
Date: Sun Sep 20 00:17:10 2026 +0000
syz-cluster: applied patch under review
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
index 50a68819ceb7b..e91bbc219c077 100644
--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -378,6 +378,7 @@ static void cros_unregister_ports(struct cros_typec_data *typec)
if (!typec->ports[i])
continue;
+ cros_typec_altmodes_stop(typec->ports[i]);
cros_typec_remove_partner(typec, i);
cros_typec_remove_cable(typec, i);
diff --git a/drivers/platform/chrome/cros_typec_altmode.c b/drivers/platform/chrome/cros_typec_altmode.c
index 66c546bf89b53..2492058d98b8e 100644
--- a/drivers/platform/chrome/cros_typec_altmode.c
+++ b/drivers/platform/chrome/cros_typec_altmode.c
@@ -37,6 +37,21 @@ struct cros_typec_dp_data {
bool pending_status_update;
};
+void cros_typec_altmodes_stop(struct cros_typec_port *port)
+{
+ struct cros_typec_altmode_data *adata;
+ int i;
+
+ for (i = 0; i < CROS_EC_ALTMODE_MAX; i++) {
+ if (!port->port_altmode[i])
+ continue;
+
+ adata = typec_altmode_get_drvdata(port->port_altmode[i]);
+ if (adata)
+ disable_work_sync(&adata->work);
+ }
+}
+
static void cros_typec_altmode_work(struct work_struct *work)
{
struct cros_typec_altmode_data *data =
diff --git a/drivers/platform/chrome/cros_typec_altmode.h b/drivers/platform/chrome/cros_typec_altmode.h
index 3f2aa95d065af..9e67f82ba031d 100644
--- a/drivers/platform/chrome/cros_typec_altmode.h
+++ b/drivers/platform/chrome/cros_typec_altmode.h
@@ -11,6 +11,12 @@ struct typec_altmode;
struct typec_altmode_desc;
struct typec_displayport_data;
+#if IS_ENABLED(CONFIG_CROS_EC_TYPEC_ALTMODES)
+void cros_typec_altmodes_stop(struct cros_typec_port *port);
+#else
+static inline void cros_typec_altmodes_stop(struct cros_typec_port *port) {}
+#endif
+
#if IS_ENABLED(CONFIG_TYPEC_DP_ALTMODE)
struct typec_altmode *
cros_typec_register_displayport(struct cros_typec_port *port,
|
| 3/2 | 2026/09/20 00:17 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 3504 output: 32 thoughts: 165 Thoughts: **Analyzing this Patch for Vulnerabilities** Okay, let's dive into this patch. My initial thought is to zero in on these file modifications: `drivers/platform/chrome/cros_ec_typec.c`, `drivers/platform/chrome/cros_typec_altmode.c`, and `drivers/platform/chrome/cros_typec_altmode.h`. The fact that we're touching `cros_ec_typec` immediately has me on alert. I need to understand the role of `cros_unregister_ports` here, how it's called, and the overall functionality of `cros_ec_typec`. Is this driver remotely accessible? Can I trigger this in typical fuzzing setups like QEMU or Google Compute Engine, or maybe via virtual buses? Hold on... I need to check something quickly. Is `cros_ec_typec` exposed in syzkaller? If it is, that dramatically changes my approach. Let's dig into `cros_ec_typec.c` directly and start there. |
| 4/2 | 2026/09/20 00:17 | tool | grepper |
0mArgs:{
"Expression": "cros_unregister_ports",
"PathPrefix": "drivers/platform/chrome/"
}Results: {
"Output": "drivers/platform/chrome/cros_ec_typec.c=365=static void cros_typec_unregister_port_altmodes(struct cros_typec_port *port)\n--\ndrivers/platform/chrome/cros_ec_typec.c-372-\ndrivers/platform/chrome/cros_ec_typec.c:373:static void cros_unregister_ports(struct cros_typec_data *typec)\ndrivers/platform/chrome/cros_ec_typec.c-374-{\n--\ndrivers/platform/chrome/cros_ec_typec.c=439=static int cros_typec_init_ports(struct cros_typec_data *typec)\n--\ndrivers/platform/chrome/cros_ec_typec.c-530-\tfwnode_handle_put(fwnode);\ndrivers/platform/chrome/cros_ec_typec.c:531:\tcros_unregister_ports(typec);\ndrivers/platform/chrome/cros_ec_typec.c-532-\treturn ret;\n--\ndrivers/platform/chrome/cros_ec_typec.c=1350=static int cros_typec_probe(struct platform_device *pdev)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1423-unregister_ports:\ndrivers/platform/chrome/cros_ec_typec.c:1424:\tcros_unregister_ports(typec);\ndrivers/platform/chrome/cros_ec_typec.c-1425-\treturn ret;\n--\ndrivers/platform/chrome/cros_ec_typec.c=1428=static void cros_typec_remove(struct platform_device *pdev)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1433-\tcancel_work_sync(\u0026typec-\u003eport_work);\ndrivers/platform/chrome/cros_ec_typec.c:1434:\tcros_unregister_ports(typec);\ndrivers/platform/chrome/cros_ec_typec.c-1435-}\n"
} |
| 5/2 | 2026/09/20 00:17 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 4475 output: 43 thoughts: 51 Thoughts: Here's my analysis of the provided text, summarized in the first person, assuming an expert-level understanding: **Digging into the Cros_EC Type-C Driver** Okay, so I need to understand the control flow for the `cros_ec_typec` platform driver. My immediate focus is on `drivers/platform/chrome/cros_ec_typec.c`, specifically around lines 370-400. That section is likely handling the core operations – the probe and remove functions are probably defined within that block. I want to see *exactly* how the driver is registered with the system, and then the steps involved when the probe routine is executed. This should shed light on the resources it's claiming, what hardware it's interacting with, and what steps it takes during initialisation and teardown. It'll also likely show how it's interacting with the EC (Embedded Controller) itself and how it's managing the Type-C functionality. This will give me a solid understanding of its operational behaviour. |
| 6/2 | 2026/09/20 00:17 | tool | read-file |
0mArgs:{
"File": "drivers/platform/chrome/cros_ec_typec.c",
"FirstLine": 365,
"LineCount": 40
}Results: {
"Contents": " 365:\tstatic void cros_typec_unregister_port_altmodes(struct cros_typec_port *port)\n 366:\t{\n 367:\t\tint i;\n 368:\t\n 369:\t\tfor (i = 0; i \u003c CROS_EC_ALTMODE_MAX; i++)\n 370:\t\t\ttypec_unregister_altmode(port-\u003eport_altmode[i]);\n 371:\t}\n 372:\t\n 373:\tstatic void cros_unregister_ports(struct cros_typec_data *typec)\n 374:\t{\n 375:\t\tint i;\n 376:\t\n 377:\t\tfor (i = 0; i \u003c typec-\u003enum_ports; i++) {\n 378:\t\t\tif (!typec-\u003eports[i])\n 379:\t\t\t\tcontinue;\n 380:\t\n 381:\t\t\tcros_typec_altmodes_stop(typec-\u003eports[i]);\n 382:\t\t\tcros_typec_remove_partner(typec, i);\n 383:\t\t\tcros_typec_remove_cable(typec, i);\n 384:\t\n 385:\t\t\tusb_role_switch_put(typec-\u003eports[i]-\u003erole_sw);\n 386:\t\t\ttypec_switch_put(typec-\u003eports[i]-\u003eori_sw);\n 387:\t\t\ttypec_mux_put(typec-\u003eports[i]-\u003emux);\n 388:\t\t\tcros_typec_unregister_port_altmodes(typec-\u003eports[i]);\n 389:\t\t\ttypec_unregister_port(typec-\u003eports[i]-\u003eport);\n 390:\t\t}\n 391:\t}\n 392:\t\n 393:\t/*\n 394:\t * Register port alt modes with known values till we start retrieving\n 395:\t * port capabilities from the EC.\n 396:\t */\n 397:\tstatic int cros_typec_register_port_altmodes(struct cros_typec_data *typec,\n 398:\t\t\t\t\t\t int port_num)\n 399:\t{\n 400:\t\tstruct cros_typec_port *port = typec-\u003eports[port_num];\n 401:\t\tstruct typec_altmode_desc desc;\n 402:\t\tstruct typec_altmode *amode;\n 403:\t\n 404:\t\t/* All PD capable CrOS devices are assumed to support DP altmode. */\n"
} |
| 7/2 | 2026/09/20 00:17 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 5450 output: 44 thoughts: 81 Thoughts: Here's my analysis of the provided thought process, summarized as if I were having these thoughts myself: **Diving into the Cros EC Type-C Driver** Okay, time to get a handle on this `drivers/platform/chrome/cros_ec_typec.c` file. My first question is always, "What kind of platform driver are we dealing with here?" That's the baseline. Then, I need to understand the instantiation. How exactly is this `cros_ec_typec` driver brought into existence on the system? Is it the ChromeOS Embedded Controller (EC) Multi-Function Device (MFD) that's taking care of it, or are we looking at an ACPI or Device Tree (OF) driven initialization? Gotta check the `cros_ec_typec.c` probe function and driver structure; that's where the answers are going to be found. Let's dig in and see what the code reveals. |
| 8/2 | 2026/09/20 00:17 | tool | read-file |
0mArgs:{
"File": "drivers/platform/chrome/cros_ec_typec.c",
"FirstLine": 1420,
"LineCount": 50
}Results: {
"Contents": "1420:\t\n1421:\t\treturn 0;\n1422:\t\n1423:\tunregister_ports:\n1424:\t\tcros_unregister_ports(typec);\n1425:\t\treturn ret;\n1426:\t}\n1427:\t\n1428:\tstatic void cros_typec_remove(struct platform_device *pdev)\n1429:\t{\n1430:\t\tstruct cros_typec_data *typec = platform_get_drvdata(pdev);\n1431:\t\n1432:\t\tcros_usbpd_unregister_notify(\u0026typec-\u003enb);\n1433:\t\tcancel_work_sync(\u0026typec-\u003eport_work);\n1434:\t\tcros_unregister_ports(typec);\n1435:\t}\n1436:\t\n1437:\tstatic int __maybe_unused cros_typec_suspend(struct device *dev)\n1438:\t{\n1439:\t\tstruct cros_typec_data *typec = dev_get_drvdata(dev);\n1440:\t\n1441:\t\tcancel_work_sync(\u0026typec-\u003eport_work);\n1442:\t\n1443:\t\treturn 0;\n1444:\t}\n1445:\t\n1446:\tstatic int __maybe_unused cros_typec_resume(struct device *dev)\n1447:\t{\n1448:\t\tstruct cros_typec_data *typec = dev_get_drvdata(dev);\n1449:\t\n1450:\t\t/* Refresh port state. */\n1451:\t\tschedule_work(\u0026typec-\u003eport_work);\n1452:\t\n1453:\t\treturn 0;\n1454:\t}\n1455:\t\n1456:\tstatic const struct dev_pm_ops cros_typec_pm_ops = {\n1457:\t\tSET_SYSTEM_SLEEP_PM_OPS(cros_typec_suspend, cros_typec_resume)\n1458:\t};\n1459:\t\n1460:\tstatic struct platform_driver cros_typec_driver = {\n1461:\t\t.driver\t= {\n1462:\t\t\t.name = DRV_NAME,\n1463:\t\t\t.acpi_match_table = ACPI_PTR(cros_typec_acpi_id),\n1464:\t\t\t.of_match_table = of_match_ptr(cros_typec_of_match),\n1465:\t\t\t.pm = \u0026cros_typec_pm_ops,\n1466:\t\t},\n1467:\t\t.probe = cros_typec_probe,\n1468:\t\t.remove = cros_typec_remove,\n1469:\t};\n"
} |
| 9/2 | 2026/09/20 00:17 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 6517 output: 39 thoughts: 51 Thoughts: Here's my take on those thoughts: **Analyzing the `cros_typec_driver`** Okay, so I'm looking at `cros_typec_driver`. It's a platform driver, which is standard. But what's interesting are the match tables – it uses both `acpi_match_table` and `of_match_table`. That's a little more versatile than some. I'm wondering what `DRV_NAME` is actually defined as. I need to nail down that driver name to understand how it's being registered and what it's trying to match with. Let's dig into that definition. |
| 10/2 | 2026/09/20 00:17 | tool | grepper |
0mArgs:{
"Expression": "DRV_NAME",
"PathPrefix": "drivers/platform/chrome/cros_ec_typec.c"
}Results: {
"Output": "drivers/platform/chrome/cros_ec_typec.c-22-\ndrivers/platform/chrome/cros_ec_typec.c:23:#define DRV_NAME \"cros-ec-typec\"\ndrivers/platform/chrome/cros_ec_typec.c-24-\n--\ndrivers/platform/chrome/cros_ec_typec.c=1460=static struct platform_driver cros_typec_driver = {\ndrivers/platform/chrome/cros_ec_typec.c-1461-\t.driver\t= {\ndrivers/platform/chrome/cros_ec_typec.c:1462:\t\t.name = DRV_NAME,\ndrivers/platform/chrome/cros_ec_typec.c-1463-\t\t.acpi_match_table = ACPI_PTR(cros_typec_acpi_id),\n"
} |
| 11/2 | 2026/09/20 00:17 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 6978 output: 21 thoughts: 62 Thoughts: **Analyzing the `cros_typec_driver` Registration** Okay, so I see that the `cros_typec_driver` is being registered using `module_platform_driver`. That's standard practice, nothing surprising there. Now, the key is figuring out how the corresponding platform device, the `cros-ec-typec`, is instantiated. I need to trace back where the device with that name is created. Time to get the grep command out and search for that exact string, "cros-ec-typec". Let's see what the code reveals. |
| 12/2 | 2026/09/20 00:17 | tool | grepper |
0mArgs:{
"Expression": "cros-ec-typec"
}Results: {
"Output": "Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-3----\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml:4:$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml=16=description:\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-19- control the Type C ports. This binding is compatible with both the\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml:20: cros-ec-typec and cros-ec-ucsi drivers. The cros-ec-typec driver\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-21- supports the host command interface used by the Chrome OS EC with a\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml=28=properties:\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-30- enum:\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml:31: - google,cros-ec-typec\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-32- - google,cros-ec-ucsi\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml=51=examples:\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-62- typec {\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml:63: compatible = \"google,cros-ec-typec\";\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-64-\n--\nDocumentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml=19=properties:\n--\nDocumentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml-101- typec:\nDocumentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml:102: $ref: /schemas/chrome/google,cros-ec-typec.yaml#\nDocumentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml-103-\n--\narch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi=885=\t\ttypec {\narch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi:886:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi-887-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi=1642=\t\ttypec {\narch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi:1643:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi-1644-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi=1441=\t\ttypec {\narch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi:1442:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi-1443-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi=1457=\t\ttypec {\narch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi:1458:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi-1459-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi=670=\t\ttypec {\narch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi:671:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi-672-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi=570=\t\ttypec {\narch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi:571:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi-572-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi=36=\t\ttypec {\narch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi:37:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi-38-\t\t\t#address-cells = \u003c1\u003e;\n--\ndrivers/platform/chrome/Kconfig=246=config CROS_EC_TYPEC\n--\ndrivers/platform/chrome/Kconfig-258-\t To compile this driver as a module, choose M here: the module will be\ndrivers/platform/chrome/Kconfig:259:\t called cros-ec-typec.\ndrivers/platform/chrome/Kconfig-260-\n--\ndrivers/platform/chrome/Makefile=20=cros_ec_lpcs-objs\t\t\t:= cros_ec_lpc.o cros_ec_lpc_mec.o\ndrivers/platform/chrome/Makefile:21:cros-ec-typec-objs\t\t\t:= cros_ec_typec.o cros_typec_vdm.o\ndrivers/platform/chrome/Makefile-22-ifneq ($(CONFIG_CROS_EC_TYPEC_ALTMODES),)\ndrivers/platform/chrome/Makefile:23:\tcros-ec-typec-objs\t\t+= cros_typec_altmode.o\ndrivers/platform/chrome/Makefile-24-endif\ndrivers/platform/chrome/Makefile:25:obj-$(CONFIG_CROS_EC_TYPEC)\t\t+= cros-ec-typec.o\ndrivers/platform/chrome/Makefile-26-\n--\ndrivers/platform/chrome/cros_ec_typec.c-22-\ndrivers/platform/chrome/cros_ec_typec.c:23:#define DRV_NAME \"cros-ec-typec\"\ndrivers/platform/chrome/cros_ec_typec.c-24-\n--\ndrivers/platform/chrome/cros_ec_typec.c=1343=static const struct of_device_id cros_typec_of_match[] = {\ndrivers/platform/chrome/cros_ec_typec.c:1344:\t{ .compatible = \"google,cros-ec-typec\", },\ndrivers/platform/chrome/cros_ec_typec.c-1345-\t{}\n"
} |
| 13/2 | 2026/09/20 00:17 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 9260 output: 36 thoughts: 65 Thoughts: Here's my take: **Analyzing the `cros-ec-typec` Driver Matching** Alright, let's break this down. It looks like the `cros-ec-typec` driver is being matched rather straightforwardly. It's either coming through the device tree using `of_match_table` with the `google,cros-ec-typec` entry or via the ACPI table. That's a classic setup. But that `cros_typec_acpi_id` part... that's the one I need to focus on. I need to get into the code and see exactly how ACPI is handling this. What is this `cros_typec_acpi_id`? What's going on behind the scenes with ACPI to get this driver loaded? That's the next step; time to dig in. |
| 14/2 | 2026/09/20 00:17 | tool | grepper |
0mArgs:{
"Expression": "cros_typec_acpi_id",
"PathPrefix": "drivers/platform/chrome/"
}Results: {
"Output": "drivers/platform/chrome/cros_ec_typec.c=1323=static int cros_ec_typec_event(struct notifier_block *nb,\n--\ndrivers/platform/chrome/cros_ec_typec.c-1334-#ifdef CONFIG_ACPI\ndrivers/platform/chrome/cros_ec_typec.c:1335:static const struct acpi_device_id cros_typec_acpi_id[] = {\ndrivers/platform/chrome/cros_ec_typec.c-1336-\t{ \"GOOG0014\", 0 },\n--\ndrivers/platform/chrome/cros_ec_typec.c-1338-};\ndrivers/platform/chrome/cros_ec_typec.c:1339:MODULE_DEVICE_TABLE(acpi, cros_typec_acpi_id);\ndrivers/platform/chrome/cros_ec_typec.c-1340-#endif\n--\ndrivers/platform/chrome/cros_ec_typec.c=1460=static struct platform_driver cros_typec_driver = {\n--\ndrivers/platform/chrome/cros_ec_typec.c-1462-\t\t.name = DRV_NAME,\ndrivers/platform/chrome/cros_ec_typec.c:1463:\t\t.acpi_match_table = ACPI_PTR(cros_typec_acpi_id),\ndrivers/platform/chrome/cros_ec_typec.c-1464-\t\t.of_match_table = of_match_ptr(cros_typec_of_match),\n"
} |
| 15/2 | 2026/09/20 00:17 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 9960 output: 20 thoughts: 52 Thoughts: Okay, let me think this through... **Digging into Device Instantiation in x86/amd64** Hmm, so how *exactly* are these devices being brought into existence in the x86/amd64 environment? That's the core question here. I need to understand the underlying mechanism. My initial hunch is that the Chrome Embedded Controller (cros_ec) might be playing a role in this, specifically in creating MFD (Multi-Function Device) cells. It's a plausible pathway. To confirm or refute this, I should dig into the kernel source. The most logical place to start would be in the `drivers/mfd/cros_ec*` directory, and perhaps also the general `drivers/platform/chrome/` location, since those are the most likely areas to deal with the Chrome-specific platform devices and their interactions. That should give me a solid clue! |
| 16/2 | 2026/09/20 00:18 | tool | grepper |
0mArgs:{
"Expression": "GOOG0014"
}Results: {
"Output": "drivers/platform/chrome/cros_ec_typec.c=1335=static const struct acpi_device_id cros_typec_acpi_id[] = {\ndrivers/platform/chrome/cros_ec_typec.c:1336:\t{ \"GOOG0014\", 0 },\ndrivers/platform/chrome/cros_ec_typec.c-1337-\t{}\n"
} |
| 17/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 10339 output: 36 thoughts: 28 Thoughts: Here's my thought process, as requested: **Investigating `cros-ec-typec` References** Okay, so I need to track down where the `cros-ec-typec` string is being used within the kernel. My first instinct, given its name, is to look within the `drivers/mfd/` directory, as `mfd` (multi-function devices) is often involved with power and peripheral management, which sounds likely for Type-C. However, I can't be too narrow, it could be referenced elsewhere, so I'll need to broaden the search to the entire driver's tree or perhaps even the wider kernel source. This could be a module, a binding to a DT node, or a function that is used to call it. I know that device drivers are often responsible for power management and communication to other peripherals, so it could show up in a lot of places. I'll need to devise an efficient search strategy to cover all the bases. |
| 18/2 | 2026/09/20 00:18 | tool | grepper |
0mError:no matches Args: {
"Expression": "cros[-_]ec[-_]typec",
"PathPrefix": "drivers/mfd/"
}Results: {
"error": "no matches"
} |
| 19/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 10628 output: 31 thoughts: 263 Thoughts: **My Thought Process on Tracking Down "cros-ec-typec" Usage** Okay, time to dig into this "cros-ec-typec" business. First, let's cast a wide net and see where that string, or even "google,cros-ec-typec," actually shows up across the entire kernel source tree. We've already done a basic search for "cros-ec-typec" and it looks like we found some interesting spots: device tree bindings, a few architecture-specific directories like Mediatek and Qualcomm, and the usual suspects in the `drivers/platform/chrome` directory: the Kconfig, Makefile, and the `cros_ec_typec.c` file. Now, I need to understand *how* this thing is actually getting instantiated. Is there a platform device being created *explicitly* with the name "cros-ec-typec"? That's the key. Let me see... If `platform_driver_register` is called with `.name = DRV_NAME`, is it possible for a platform device to register with that exact name? It probably is. But let's keep going. Hang on. Could syzkaller be involved in creating a device with this name? No, syzkaller runs in standard QEMU/GCE amd64 instances. Not relevant in this case. Also, can a platform device even be created from userspace directly? Only through something like configfs, but platform devices aren't typically dynamically created that way. So, this device is most likely created during the boot process. Alright, let's broaden the search a bit. Could there be some kind of "virtual" or abstracted `cros_ec` component in play? Let me check specifically the `drivers/platform/chrome/cros_ec*` files. I need to be thorough and check all the related files. |
| 20/2 | 2026/09/20 00:18 | tool | grepper |
0mArgs:{
"Expression": "cros_ec",
"PathPrefix": "drivers/platform/chrome/Makefile"
}Results: {
"Output": "drivers/platform/chrome/Makefile-3-# tell define_trace.h where to find the cros ec trace header\ndrivers/platform/chrome/Makefile:4:CFLAGS_cros_ec_trace.o:=\t\t-I$(src)\ndrivers/platform/chrome/Makefile:5:CFLAGS_cros_ec_sensorhub_ring.o:=\t-I$(src)\ndrivers/platform/chrome/Makefile-6-\n--\ndrivers/platform/chrome/Makefile=12=obj-$(CONFIG_CHROMEOS_TBMC)\t\t+= chromeos_tbmc.o\ndrivers/platform/chrome/Makefile:13:obj-$(CONFIG_CROS_EC)\t\t\t+= cros_ec.o\ndrivers/platform/chrome/Makefile:14:obj-$(CONFIG_CROS_EC_I2C)\t\t+= cros_ec_i2c.o\ndrivers/platform/chrome/Makefile:15:obj-$(CONFIG_CROS_EC_ISHTP)\t\t+= cros_ec_ishtp.o\ndrivers/platform/chrome/Makefile-16-obj-$(CONFIG_CROS_TYPEC_SWITCH)\t\t+= cros_typec_switch.o\ndrivers/platform/chrome/Makefile:17:obj-$(CONFIG_CROS_EC_RPMSG)\t\t+= cros_ec_rpmsg.o\ndrivers/platform/chrome/Makefile:18:obj-$(CONFIG_CROS_EC_SPI)\t\t+= cros_ec_spi.o\ndrivers/platform/chrome/Makefile:19:obj-$(CONFIG_CROS_EC_UART)\t\t+= cros_ec_uart.o\ndrivers/platform/chrome/Makefile:20:cros_ec_lpcs-objs\t\t\t:= cros_ec_lpc.o cros_ec_lpc_mec.o\ndrivers/platform/chrome/Makefile:21:cros-ec-typec-objs\t\t\t:= cros_ec_typec.o cros_typec_vdm.o\ndrivers/platform/chrome/Makefile-22-ifneq ($(CONFIG_CROS_EC_TYPEC_ALTMODES),)\n--\ndrivers/platform/chrome/Makefile=25=obj-$(CONFIG_CROS_EC_TYPEC)\t\t+= cros-ec-typec.o\ndrivers/platform/chrome/Makefile-26-\ndrivers/platform/chrome/Makefile:27:obj-$(CONFIG_CROS_EC_LPC)\t\t+= cros_ec_lpcs.o\ndrivers/platform/chrome/Makefile:28:cros-ec-proto-objs\t\t\t:= cros_ec_proto.o cros_ec_trace.o\ndrivers/platform/chrome/Makefile-29-obj-$(CONFIG_CROS_EC_PROTO)\t\t+= cros-ec-proto.o\ndrivers/platform/chrome/Makefile=30=obj-$(CONFIG_CROS_KBD_LED_BACKLIGHT)\t+= cros_kbd_led_backlight.o\ndrivers/platform/chrome/Makefile:31:obj-$(CONFIG_CROS_EC_CHARDEV)\t\t+= cros_ec_chardev.o\ndrivers/platform/chrome/Makefile:32:obj-$(CONFIG_CROS_EC_LIGHTBAR)\t\t+= cros_ec_lightbar.o\ndrivers/platform/chrome/Makefile:33:obj-$(CONFIG_CROS_EC_VBC)\t\t+= cros_ec_vbc.o\ndrivers/platform/chrome/Makefile:34:obj-$(CONFIG_CROS_EC_DEBUGFS)\t\t+= cros_ec_debugfs.o\ndrivers/platform/chrome/Makefile:35:cros-ec-sensorhub-objs\t\t\t:= cros_ec_sensorhub.o cros_ec_sensorhub_ring.o\ndrivers/platform/chrome/Makefile-36-obj-$(CONFIG_CROS_EC_SENSORHUB)\t\t+= cros-ec-sensorhub.o\ndrivers/platform/chrome/Makefile:37:obj-$(CONFIG_CROS_EC_SYSFS)\t\t+= cros_ec_sysfs.o\ndrivers/platform/chrome/Makefile-38-obj-$(CONFIG_CROS_HPS_I2C)\t\t+= cros_hps_i2c.o\n--\ndrivers/platform/chrome/Makefile=45=obj-$(CONFIG_CROS_KUNIT_EC_PROTO_TEST)\t+= cros_kunit_proto_test.o\ndrivers/platform/chrome/Makefile:46:cros_kunit_proto_test-objs\t\t:= cros_ec_proto_test_util.o cros_ec_proto_test.o\n"
} |
| 21/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 12388 output: 44 thoughts: 17 Thoughts: Here's a summary of my thought process: **Diving into cros_ec_typec Probe Requirements** Okay, so I need to understand the dependencies and prerequisites for the `cros_ec_typec` probe. I can't just launch into fixing or modifying something without a solid grasp of what it's expecting to find and what needs to be in place for it to function correctly. The probe itself is just a mechanism for the driver to be initialized, so I need to find out what resources, hardware states, or other drivers are essential for this particular probe to even trigger successfully, let alone do its job effectively. This is the starting point for effective debugging or modification. Time to investigate! |
| 22/2 | 2026/09/20 00:18 | tool | read-file |
0mArgs:{
"File": "drivers/platform/chrome/cros_ec_typec.c",
"FirstLine": 1350,
"LineCount": 75
}Results: {
"Contents": "1350:\tstatic int cros_typec_probe(struct platform_device *pdev)\n1351:\t{\n1352:\t\tstruct cros_ec_dev *ec_dev = NULL;\n1353:\t\tstruct device *dev = \u0026pdev-\u003edev;\n1354:\t\tstruct cros_typec_data *typec;\n1355:\t\tstruct ec_response_usb_pd_ports resp;\n1356:\t\tint ret, i;\n1357:\t\n1358:\t\ttypec = devm_kzalloc(dev, sizeof(*typec), GFP_KERNEL);\n1359:\t\tif (!typec)\n1360:\t\t\treturn -ENOMEM;\n1361:\t\n1362:\t\ttypec-\u003edev = dev;\n1363:\t\n1364:\t\ttypec-\u003eec = dev_get_drvdata(pdev-\u003edev.parent);\n1365:\t\tif (!typec-\u003eec || !typec-\u003eec-\u003eec) {\n1366:\t\t\tdev_warn(dev, \"couldn't find parent EC device\\n\");\n1367:\t\t\treturn -EPROBE_DEFER;\n1368:\t\t}\n1369:\t\n1370:\t\tplatform_set_drvdata(pdev, typec);\n1371:\t\n1372:\t\tret = cros_typec_get_cmd_version(typec);\n1373:\t\tif (ret \u003c 0) {\n1374:\t\t\tdev_err(dev, \"failed to get PD command version info\\n\");\n1375:\t\t\treturn ret;\n1376:\t\t}\n1377:\t\n1378:\t\tec_dev = dev_get_drvdata(\u0026typec-\u003eec-\u003eec-\u003edev);\n1379:\t\tif (!ec_dev)\n1380:\t\t\treturn -EPROBE_DEFER;\n1381:\t\n1382:\t\ttypec-\u003etypec_cmd_supported = cros_ec_check_features(ec_dev, EC_FEATURE_TYPEC_CMD);\n1383:\t\ttypec-\u003eneeds_mux_ack = cros_ec_check_features(ec_dev, EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK);\n1384:\t\ttypec-\u003eap_driven_altmode = cros_ec_check_features(\n1385:\t\t\tec_dev, EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY);\n1386:\t\n1387:\t\tret = cros_ec_cmd(typec-\u003eec, 0, EC_CMD_USB_PD_PORTS, NULL, 0,\n1388:\t\t\t\t \u0026resp, sizeof(resp));\n1389:\t\tif (ret \u003c 0)\n1390:\t\t\treturn ret;\n1391:\t\n1392:\t\ttypec-\u003enum_ports = resp.num_ports;\n1393:\t\tif (typec-\u003enum_ports \u003e EC_USB_PD_MAX_PORTS) {\n1394:\t\t\tdev_warn(typec-\u003edev,\n1395:\t\t\t\t \"Too many ports reported: %d, limiting to max: %d\\n\",\n1396:\t\t\t\t typec-\u003enum_ports, EC_USB_PD_MAX_PORTS);\n1397:\t\t\ttypec-\u003enum_ports = EC_USB_PD_MAX_PORTS;\n1398:\t\t}\n1399:\t\n1400:\t\tret = cros_typec_init_ports(typec);\n1401:\t\tif (ret \u003c 0)\n1402:\t\t\treturn ret;\n1403:\t\n1404:\t\tINIT_WORK(\u0026typec-\u003eport_work, cros_typec_port_work);\n1405:\t\n1406:\t\t/*\n1407:\t\t * Safe to call port update here, since we haven't registered the\n1408:\t\t * PD notifier yet.\n1409:\t\t */\n1410:\t\tfor (i = 0; i \u003c typec-\u003enum_ports; i++) {\n1411:\t\t\tret = cros_typec_port_update(typec, i);\n1412:\t\t\tif (ret \u003c 0)\n1413:\t\t\t\tgoto unregister_ports;\n1414:\t\t}\n1415:\t\n1416:\t\ttypec-\u003enb.notifier_call = cros_ec_typec_event;\n1417:\t\tret = cros_usbpd_register_notify(\u0026typec-\u003enb);\n1418:\t\tif (ret \u003c 0)\n1419:\t\t\tgoto unregister_ports;\n1420:\t\n1421:\t\treturn 0;\n1422:\t\n1423:\tunregister_ports:\n1424:\t\tcros_unregister_ports(typec);\n"
} |
| 23/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 13827 output: 29 thoughts: 132 Thoughts: **Dissecting the `cros_typec_probe` Function** Okay, let's break this down. My immediate focus is on `cros_typec_probe`. I see it relies on `dev_get_drvdata(pdev->dev.parent)`. Right, so that's retrieving driver data from the parent device of the platform device `pdev`. And that data is going to be either a `struct cros_ec_dev *` or a `struct cros_ec_platform *`, which makes perfect sense given the naming. Now, where is this `pdev` coming from? I need to trace back the creation of this platform device to understand the device tree hierarchy and how the driver gets initialized. I'll need to look for where "GOOG0014" or "cros-ec-typec" are defined, or anything that's a child device of `cros_ec`. Time to grep the relevant source trees. I'll focus on `drivers/platform/chrome/` and `drivers/mfd/`. That's where I'd expect to find the platform device definition or initialization related to `cros_ec_dev` or its child cells. A quick search with those terms should turn up the right code. Let's see what we can find! |
| 24/2 | 2026/09/20 00:18 | tool | grepper |
0mArgs:{
"Expression": "cros-ec",
"PathPrefix": "drivers/mfd/"
}Results: {
"Output": "drivers/mfd/Kconfig=253=config MFD_CROS_EC_DEV\n--\ndrivers/mfd/Kconfig-263-\t To compile this driver as a module, choose M here: the module will be\ndrivers/mfd/Kconfig:264:\t called cros-ec-dev.\ndrivers/mfd/Kconfig-265-\n--\ndrivers/mfd/cros_ec_dev.c-19-\ndrivers/mfd/cros_ec_dev.c:20:#define DRV_NAME \"cros-ec-dev\"\ndrivers/mfd/cros_ec_dev.c-21-\n--\ndrivers/mfd/cros_ec_dev.c=73=static const struct mfd_cell cros_ec_cec_cells[] = {\ndrivers/mfd/cros_ec_dev.c:74:\t{ .name = \"cros-ec-cec\", },\ndrivers/mfd/cros_ec_dev.c-75-};\n--\ndrivers/mfd/cros_ec_dev.c=77=static const struct mfd_cell cros_ec_gpio_cells[] = {\ndrivers/mfd/cros_ec_dev.c:78:\t{ .name = \"cros-ec-gpio\", },\ndrivers/mfd/cros_ec_dev.c-79-};\n--\ndrivers/mfd/cros_ec_dev.c=81=static const struct mfd_cell cros_ec_rtc_cells[] = {\ndrivers/mfd/cros_ec_dev.c:82:\t{ .name = \"cros-ec-rtc\", },\ndrivers/mfd/cros_ec_dev.c-83-};\n--\ndrivers/mfd/cros_ec_dev.c=85=static const struct mfd_cell cros_ec_sensorhub_cells[] = {\ndrivers/mfd/cros_ec_dev.c:86:\t{ .name = \"cros-ec-sensorhub\", },\ndrivers/mfd/cros_ec_dev.c-87-};\n--\ndrivers/mfd/cros_ec_dev.c=98=static const struct mfd_cell cros_ec_wdt_cells[] = {\ndrivers/mfd/cros_ec_dev.c:99:\t{ .name = \"cros-ec-wdt\", }\ndrivers/mfd/cros_ec_dev.c-100-};\n--\ndrivers/mfd/cros_ec_dev.c=102=static const struct mfd_cell cros_ec_led_cells[] = {\ndrivers/mfd/cros_ec_dev.c:103:\t{ .name = \"cros-ec-led\", },\ndrivers/mfd/cros_ec_dev.c-104-};\n--\ndrivers/mfd/cros_ec_dev.c=156=static const struct mfd_cell cros_ec_platform_cells[] = {\ndrivers/mfd/cros_ec_dev.c:157:\t{ .name = \"cros-ec-chardev\", },\ndrivers/mfd/cros_ec_dev.c:158:\t{ .name = \"cros-ec-debugfs\", },\ndrivers/mfd/cros_ec_dev.c:159:\t{ .name = \"cros-ec-hwmon\", },\ndrivers/mfd/cros_ec_dev.c:160:\t{ .name = \"cros-ec-sysfs\", },\ndrivers/mfd/cros_ec_dev.c-161-};\n--\ndrivers/mfd/cros_ec_dev.c=163=static const struct mfd_cell cros_ec_pchg_cells[] = {\ndrivers/mfd/cros_ec_dev.c:164:\t{ .name = \"cros-ec-pchg\", },\ndrivers/mfd/cros_ec_dev.c-165-};\n--\ndrivers/mfd/cros_ec_dev.c=167=static const struct mfd_cell cros_ec_lightbar_cells[] = {\ndrivers/mfd/cros_ec_dev.c:168:\t{ .name = \"cros-ec-lightbar\", }\ndrivers/mfd/cros_ec_dev.c-169-};\n--\ndrivers/mfd/cros_ec_dev.c=171=static const struct mfd_cell cros_ec_vbc_cells[] = {\ndrivers/mfd/cros_ec_dev.c:172:\t{ .name = \"cros-ec-vbc\", }\ndrivers/mfd/cros_ec_dev.c-173-};\n--\ndrivers/mfd/cros_ec_dev.c=180=static int ec_device_probe(struct platform_device *pdev)\n--\ndrivers/mfd/cros_ec_dev.c-270-\t !acpi_dev_found(\"GOOG0021\") \u0026\u0026\ndrivers/mfd/cros_ec_dev.c:271:\t !of_find_compatible_node(NULL, NULL, \"google,cros-ec-ucsi\")) {\ndrivers/mfd/cros_ec_dev.c-272-\t\tretval = mfd_add_hotplug_devices(ec-\u003edev,\n--\ndrivers/mfd/cros_ec_dev.c-348-\t\tdev_warn(ec-\u003edev,\ndrivers/mfd/cros_ec_dev.c:349:\t\t\t \"failed to add cros-ec platform devices: %d\\n\",\ndrivers/mfd/cros_ec_dev.c-350-\t\t\t retval);\n"
} |
| 25/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 15697 output: 41 thoughts: 60 Thoughts: Here's my summary, as if I were thinking these thoughts: **Analyzing `cros_ec_dev.c` - Potential Issue in Data Handling?** Okay, hold on a second! I need to zero in on a specific section of this `cros_ec_dev.c` driver. I've got a feeling something might be happening in there that I need to clarify. I want to concentrate on lines 260 to 290, but I need to make sure I understand the context, so I will start by focusing my attention on line 270-272 to get the precise context. I will check that section of the code carefully... it might be handling data in an unexpected way or there might be something important there I am missing. |
| 26/2 | 2026/09/20 00:18 | tool | read-file |
0mArgs:{
"File": "drivers/mfd/cros_ec_dev.c",
"FirstLine": 260,
"LineCount": 40
}Results: {
"Contents": " 260:\t\t\t}\n 261:\t\t}\n 262:\t\n 263:\t\t/*\n 264:\t\t * FW nodes can load cros_ec_ucsi, but early PDC devices did not define\n 265:\t\t * the required nodes. On PDC systems without FW nodes for cros_ec_ucsi,\n 266:\t\t * the driver should be added as an mfd subdevice.\n 267:\t\t */\n 268:\t\tif (cros_ec_check_features(ec, EC_FEATURE_USB_PD) \u0026\u0026\n 269:\t\t cros_ec_check_features(ec, EC_FEATURE_UCSI_PPM) \u0026\u0026\n 270:\t\t !acpi_dev_found(\"GOOG0021\") \u0026\u0026\n 271:\t\t !of_find_compatible_node(NULL, NULL, \"google,cros-ec-ucsi\")) {\n 272:\t\t\tretval = mfd_add_hotplug_devices(ec-\u003edev,\n 273:\t\t\t\t\t\t\t cros_ec_ucsi_cells,\n 274:\t\t\t\t\t\t\t ARRAY_SIZE(cros_ec_ucsi_cells));\n 275:\t\n 276:\t\t\tif (retval)\n 277:\t\t\t\tdev_warn(ec-\u003edev, \"failed to add cros_ec_ucsi: %d\\n\", retval);\n 278:\t\t}\n 279:\t\n 280:\t\t/*\n 281:\t\t * UCSI provides power supply information so we don't need to separately\n 282:\t\t * load the cros_usbpd_charger driver.\n 283:\t\t */\n 284:\t\tif (cros_ec_check_features(ec, EC_FEATURE_USB_PD) \u0026\u0026\n 285:\t\t !cros_ec_check_features(ec, EC_FEATURE_UCSI_PPM)) {\n 286:\t\t\tretval = mfd_add_hotplug_devices(ec-\u003edev,\n 287:\t\t\t\t\t\t\t cros_usbpd_charger_cells,\n 288:\t\t\t\t\t\t\t ARRAY_SIZE(cros_usbpd_charger_cells));\n 289:\t\n 290:\t\t\tif (retval)\n 291:\t\t\t\tdev_warn(ec-\u003edev, \"failed to add usbpd-charger: %d\\n\",\n 292:\t\t\t\t\t retval);\n 293:\t\t}\n 294:\t\n 295:\t\t/*\n 296:\t\t * Lightbar is a special case. Newer devices support autodetection,\n 297:\t\t * but older ones do not.\n 298:\t\t */\n 299:\t\tif (cros_ec_check_features(ec, EC_FEATURE_LIGHTBAR) ||\n"
} |
| 27/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 16656 output: 21 thoughts: 230 Thoughts: **My Investigation into the `cros-ec-typec` Instantiation** Okay, so I'm digging into this `cros-ec-typec` driver and I see it's *not* being added by the usual suspects, `mfd_add_devices` or `mfd_add_hotplug_devices`. That's strange. How is this thing actually getting instantiated on real hardware? I remember seeing something about it... Ah, right! For ACPI systems, the ACPI tables are defining a device that uses the HID "GOOG0014". Got it. And for Device Tree systems, the devicetree has a node that's compatible with "google,cros-ec-typec", like what I see in the mt8183-kukui, sc7180-trogdor, and similar ARM64 Chromebooks. But now I have to ask myself, does QEMU or Google Compute Engine even *have* ACPI tables that include "GOOG0014"? No. No they don't. Okay, okay... Does QEMU even have any ChromeOS EC hardware at all? That's the real question. Because remember, ChromeOS EC (or `cros_ec`) is meant to communicate with an actual embedded controller chip, over LPC, I2C, SPI, or ISHTP. So I need to go look to see if QEMU even *emulates* a ChromeOS EC device, or if there's any kernel-level emulation in place. Gotta investigate further. |
| 28/2 | 2026/09/20 00:18 | tool | grepper |
0mArgs:{
"Expression": "cros_ec_lpc"
}Results: {
"Output": "drivers/platform/chrome/Kconfig=143=config CROS_EC_LPC\n--\ndrivers/platform/chrome/Kconfig-154-\t To compile this driver as a module, choose M here: the\ndrivers/platform/chrome/Kconfig:155:\t module will be called cros_ec_lpcs.\ndrivers/platform/chrome/Kconfig-156-\n--\ndrivers/platform/chrome/Makefile=19=obj-$(CONFIG_CROS_EC_UART)\t\t+= cros_ec_uart.o\ndrivers/platform/chrome/Makefile:20:cros_ec_lpcs-objs\t\t\t:= cros_ec_lpc.o cros_ec_lpc_mec.o\ndrivers/platform/chrome/Makefile-21-cros-ec-typec-objs\t\t\t:= cros_ec_typec.o cros_typec_vdm.o\n--\ndrivers/platform/chrome/Makefile=25=obj-$(CONFIG_CROS_EC_TYPEC)\t\t+= cros-ec-typec.o\ndrivers/platform/chrome/Makefile-26-\ndrivers/platform/chrome/Makefile:27:obj-$(CONFIG_CROS_EC_LPC)\t\t+= cros_ec_lpcs.o\ndrivers/platform/chrome/Makefile-28-cros-ec-proto-objs\t\t\t:= cros_ec_proto.o cros_ec_trace.o\n--\ndrivers/platform/chrome/cros_ec_lpc.c-28-#include \"cros_ec.h\"\ndrivers/platform/chrome/cros_ec_lpc.c:29:#include \"cros_ec_lpc_mec.h\"\ndrivers/platform/chrome/cros_ec_lpc.c-30-\ndrivers/platform/chrome/cros_ec_lpc.c:31:#define DRV_NAME \"cros_ec_lpcs\"\ndrivers/platform/chrome/cros_ec_lpc.c-32-#define ACPI_DRV_NAME \"GOOG0004\"\n--\ndrivers/platform/chrome/cros_ec_lpc.c-35-/* True if ACPI device is present */\ndrivers/platform/chrome/cros_ec_lpc.c:36:static bool cros_ec_lpc_acpi_device_found;\ndrivers/platform/chrome/cros_ec_lpc.c-37-\n--\ndrivers/platform/chrome/cros_ec_lpc.c=64=struct lpc_driver_data {\n--\ndrivers/platform/chrome/cros_ec_lpc.c-71-/**\ndrivers/platform/chrome/cros_ec_lpc.c:72: * struct cros_ec_lpc - LPC device-specific data\ndrivers/platform/chrome/cros_ec_lpc.c-73- * @mmio_memory_base: The first I/O port addressing EC mapped memory.\n--\ndrivers/platform/chrome/cros_ec_lpc.c-82- */\ndrivers/platform/chrome/cros_ec_lpc.c:83:struct cros_ec_lpc {\ndrivers/platform/chrome/cros_ec_lpc.c-84-\tu16 mmio_memory_base;\n--\ndrivers/platform/chrome/cros_ec_lpc.c-86-\tstruct acpi_resource_fixed_memory32 mem32;\ndrivers/platform/chrome/cros_ec_lpc.c:87:\tint (*read)(struct cros_ec_lpc *ec_lpc, unsigned int offset,\ndrivers/platform/chrome/cros_ec_lpc.c-88-\t\t unsigned int length, u8 *dest);\ndrivers/platform/chrome/cros_ec_lpc.c:89:\tint (*write)(struct cros_ec_lpc *ec_lpc, unsigned int offset,\ndrivers/platform/chrome/cros_ec_lpc.c-90-\t\t unsigned int length, const u8 *msg);\n--\ndrivers/platform/chrome/cros_ec_lpc.c-96- */\ndrivers/platform/chrome/cros_ec_lpc.c:97:static int cros_ec_lpc_read_bytes(struct cros_ec_lpc *_, unsigned int offset, unsigned int length,\ndrivers/platform/chrome/cros_ec_lpc.c-98-\t\t\t\t u8 *dest)\n--\ndrivers/platform/chrome/cros_ec_lpc.c-115- */\ndrivers/platform/chrome/cros_ec_lpc.c:116:static int cros_ec_lpc_write_bytes(struct cros_ec_lpc *_, unsigned int offset, unsigned int length,\ndrivers/platform/chrome/cros_ec_lpc.c-117-\t\t\t\t const u8 *msg)\n--\ndrivers/platform/chrome/cros_ec_lpc.c-134- */\ndrivers/platform/chrome/cros_ec_lpc.c:135:static int cros_ec_lpc_mec_read_bytes(struct cros_ec_lpc *ec_lpc, unsigned int offset,\ndrivers/platform/chrome/cros_ec_lpc.c-136-\t\t\t\t unsigned int length, u8 *dest)\ndrivers/platform/chrome/cros_ec_lpc.c-137-{\ndrivers/platform/chrome/cros_ec_lpc.c:138:\tint in_range = cros_ec_lpc_mec_in_range(offset, length);\ndrivers/platform/chrome/cros_ec_lpc.c-139-\n--\ndrivers/platform/chrome/cros_ec_lpc.c-143-\treturn in_range ?\ndrivers/platform/chrome/cros_ec_lpc.c:144:\t\tcros_ec_lpc_io_bytes_mec(MEC_IO_READ,\ndrivers/platform/chrome/cros_ec_lpc.c-145-\t\t\t\t\t offset - EC_HOST_CMD_REGION0,\ndrivers/platform/chrome/cros_ec_lpc.c-146-\t\t\t\t\t length, dest) :\ndrivers/platform/chrome/cros_ec_lpc.c:147:\t\tcros_ec_lpc_read_bytes(ec_lpc, offset, length, dest);\ndrivers/platform/chrome/cros_ec_lpc.c-148-}\n--\ndrivers/platform/chrome/cros_ec_lpc.c-153- */\ndrivers/platform/chrome/cros_ec_lpc.c:154:static int cros_ec_lpc_mec_write_bytes(struct cros_ec_lpc *ec_lpc, unsigned int offset,\ndrivers/platform/chrome/cros_ec_lpc.c-155-\t\t\t\t unsigned int length, const u8 *msg)\ndrivers/platform/chrome/cros_ec_lpc.c-156-{\ndrivers/platform/chrome/cros_ec_lpc.c:157:\tint in_range = cros_ec_lpc_mec_in_range(offset, length);\ndrivers/platform/chrome/cros_ec_lpc.c-158-\n--\ndrivers/platform/chrome/cros_ec_lpc.c-162-\treturn in_range ?\ndrivers/platform/chrome/cros_ec_lpc.c:163:\t\tcros_ec_lpc_io_bytes_mec(MEC_IO_WRITE,\ndrivers/platform/chrome/cros_ec_lpc.c-164-\t\t\t\t\t offset - EC_HOST_CMD_REGION0,\ndrivers/platform/chrome/cros_ec_lpc.c-165-\t\t\t\t\t length, (u8 *)msg) :\ndrivers/platform/chrome/cros_ec_lpc.c:166:\t\tcros_ec_lpc_write_bytes(ec_lpc, offset, length, msg);\ndrivers/platform/chrome/cros_ec_lpc.c-167-}\ndrivers/platform/chrome/cros_ec_lpc.c-168-\ndrivers/platform/chrome/cros_ec_lpc.c:169:static int cros_ec_lpc_direct_read(struct cros_ec_lpc *ec_lpc, unsigned int offset,\ndrivers/platform/chrome/cros_ec_lpc.c-170-\t\t\t\t unsigned int length, u8 *dest)\n--\ndrivers/platform/chrome/cros_ec_lpc.c-176-\t\t\tEC_MEMMAP_SIZE) {\ndrivers/platform/chrome/cros_ec_lpc.c:177:\t\treturn cros_ec_lpc_read_bytes(ec_lpc, offset, length, dest);\ndrivers/platform/chrome/cros_ec_lpc.c-178-\t}\n--\ndrivers/platform/chrome/cros_ec_lpc.c-188-\ndrivers/platform/chrome/cros_ec_lpc.c:189:static int cros_ec_lpc_direct_write(struct cros_ec_lpc *ec_lpc, unsigned int offset,\ndrivers/platform/chrome/cros_ec_lpc.c-190-\t\t\t\t unsigned int length, const u8 *msg)\n--\ndrivers/platform/chrome/cros_ec_lpc.c-196-\t\t\tEC_MEMMAP_SIZE) {\ndrivers/platform/chrome/cros_ec_lpc.c:197:\t\treturn cros_ec_lpc_write_bytes(ec_lpc, offset, length, msg);\ndrivers/platform/chrome/cros_ec_lpc.c-198-\t}\n--\ndrivers/platform/chrome/cros_ec_lpc.c-208-\ndrivers/platform/chrome/cros_ec_lpc.c:209:static int ec_response_timed_out(struct cros_ec_lpc *ec_lpc)\ndrivers/platform/chrome/cros_ec_lpc.c-210-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c=228=static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec,\n--\ndrivers/platform/chrome/cros_ec_lpc.c-230-{\ndrivers/platform/chrome/cros_ec_lpc.c:231:\tstruct cros_ec_lpc *ec_lpc = ec-\u003epriv;\ndrivers/platform/chrome/cros_ec_lpc.c-232-\tstruct ec_host_response response;\n--\ndrivers/platform/chrome/cros_ec_lpc.c=310=static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec,\n--\ndrivers/platform/chrome/cros_ec_lpc.c-312-{\ndrivers/platform/chrome/cros_ec_lpc.c:313:\tstruct cros_ec_lpc *ec_lpc = ec-\u003epriv;\ndrivers/platform/chrome/cros_ec_lpc.c-314-\tstruct ec_lpc_host_args args;\n--\ndrivers/platform/chrome/cros_ec_lpc.c-410-/* Returns num bytes read, or negative on error. Doesn't need locking. */\ndrivers/platform/chrome/cros_ec_lpc.c:411:static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset,\ndrivers/platform/chrome/cros_ec_lpc.c-412-\t\t\t unsigned int bytes, void *dest)\ndrivers/platform/chrome/cros_ec_lpc.c-413-{\ndrivers/platform/chrome/cros_ec_lpc.c:414:\tstruct cros_ec_lpc *ec_lpc = ec-\u003epriv;\ndrivers/platform/chrome/cros_ec_lpc.c-415-\tint i = offset;\n--\ndrivers/platform/chrome/cros_ec_lpc.c-443-\ndrivers/platform/chrome/cros_ec_lpc.c:444:static void cros_ec_lpc_acpi_notify(acpi_handle device, u32 value, void *data)\ndrivers/platform/chrome/cros_ec_lpc.c-445-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-476-\ndrivers/platform/chrome/cros_ec_lpc.c:477:static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level,\ndrivers/platform/chrome/cros_ec_lpc.c-478-\t\t\t\t\t void *context, void **retval)\n--\ndrivers/platform/chrome/cros_ec_lpc.c-483-\ndrivers/platform/chrome/cros_ec_lpc.c:484:static struct acpi_device *cros_ec_lpc_get_device(const char *id)\ndrivers/platform/chrome/cros_ec_lpc.c-485-{\ndrivers/platform/chrome/cros_ec_lpc.c-486-\tstruct acpi_device *adev = NULL;\ndrivers/platform/chrome/cros_ec_lpc.c:487:\tacpi_status status = acpi_get_devices(id, cros_ec_lpc_parse_device,\ndrivers/platform/chrome/cros_ec_lpc.c-488-\t\t\t\t\t \u0026adev, NULL);\n--\ndrivers/platform/chrome/cros_ec_lpc.c-496-\ndrivers/platform/chrome/cros_ec_lpc.c:497:static acpi_status cros_ec_lpc_resources(struct acpi_resource *res, void *data)\ndrivers/platform/chrome/cros_ec_lpc.c-498-{\ndrivers/platform/chrome/cros_ec_lpc.c:499:\tstruct cros_ec_lpc *ec_lpc = data;\ndrivers/platform/chrome/cros_ec_lpc.c-500-\n--\ndrivers/platform/chrome/cros_ec_lpc.c-510-\ndrivers/platform/chrome/cros_ec_lpc.c:511:static int cros_ec_lpc_probe(struct platform_device *pdev)\ndrivers/platform/chrome/cros_ec_lpc.c-512-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-516-\tstruct cros_ec_device *ec_dev;\ndrivers/platform/chrome/cros_ec_lpc.c:517:\tstruct cros_ec_lpc *ec_lpc;\ndrivers/platform/chrome/cros_ec_lpc.c-518-\tconst struct lpc_driver_data *driver_data;\n--\ndrivers/platform/chrome/cros_ec_lpc.c-542-\t\tif (quirks \u0026 CROS_EC_LPC_QUIRK_ACPI_ID) {\ndrivers/platform/chrome/cros_ec_lpc.c:543:\t\t\tadev = cros_ec_lpc_get_device(driver_data-\u003equirk_acpi_id);\ndrivers/platform/chrome/cros_ec_lpc.c-544-\t\t\tif (!adev) {\n--\ndrivers/platform/chrome/cros_ec_lpc.c-553-\t\t\tconst char *name = driver_data-\u003equirk_aml_mutex_name;\ndrivers/platform/chrome/cros_ec_lpc.c:554:\t\t\tret = cros_ec_lpc_mec_acpi_mutex(ACPI_COMPANION(dev), name);\ndrivers/platform/chrome/cros_ec_lpc.c-555-\t\t\tif (ret) {\n--\ndrivers/platform/chrome/cros_ec_lpc.c-567-\t\tstatus = acpi_walk_resources(adev-\u003ehandle, METHOD_NAME__CRS,\ndrivers/platform/chrome/cros_ec_lpc.c:568:\t\t\t\t\t cros_ec_lpc_resources, ec_lpc);\ndrivers/platform/chrome/cros_ec_lpc.c-569-\t\tif (ACPI_SUCCESS(status) \u0026\u0026 ec_lpc-\u003emem32.address_length) {\n--\ndrivers/platform/chrome/cros_ec_lpc.c-575-\ndrivers/platform/chrome/cros_ec_lpc.c:576:\t\t\tec_lpc-\u003eread = cros_ec_lpc_direct_read;\ndrivers/platform/chrome/cros_ec_lpc.c:577:\t\t\tec_lpc-\u003ewrite = cros_ec_lpc_direct_write;\ndrivers/platform/chrome/cros_ec_lpc.c-578-\t\t}\n--\ndrivers/platform/chrome/cros_ec_lpc.c-591-\ndrivers/platform/chrome/cros_ec_lpc.c:592:\t\tcros_ec_lpc_mec_init(EC_HOST_CMD_REGION0,\ndrivers/platform/chrome/cros_ec_lpc.c-593-\t\t\t\t EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE);\n--\ndrivers/platform/chrome/cros_ec_lpc.c-600-\t\t */\ndrivers/platform/chrome/cros_ec_lpc.c:601:\t\tec_lpc-\u003eread = cros_ec_lpc_mec_read_bytes;\ndrivers/platform/chrome/cros_ec_lpc.c:602:\t\tec_lpc-\u003ewrite = cros_ec_lpc_mec_write_bytes;\ndrivers/platform/chrome/cros_ec_lpc.c-603-\t}\n--\ndrivers/platform/chrome/cros_ec_lpc.c-614-\t\t/* Re-assign read/write operations for the non MEC variant */\ndrivers/platform/chrome/cros_ec_lpc.c:615:\t\tec_lpc-\u003eread = cros_ec_lpc_read_bytes;\ndrivers/platform/chrome/cros_ec_lpc.c:616:\t\tec_lpc-\u003ewrite = cros_ec_lpc_write_bytes;\ndrivers/platform/chrome/cros_ec_lpc.c-617-\t\tret = ec_lpc-\u003eread(ec_lpc, ec_lpc-\u003emmio_memory_base + EC_MEMMAP_ID, 2,\n--\ndrivers/platform/chrome/cros_ec_lpc.c-647-\tec_dev-\u003epkt_xfer = cros_ec_pkt_xfer_lpc;\ndrivers/platform/chrome/cros_ec_lpc.c:648:\tec_dev-\u003ecmd_readmem = cros_ec_lpc_readmem;\ndrivers/platform/chrome/cros_ec_lpc.c-649-\tec_dev-\u003epriv = ec_lpc;\n--\ndrivers/platform/chrome/cros_ec_lpc.c-651-\t/*\ndrivers/platform/chrome/cros_ec_lpc.c:652:\t * Some boards do not have an IRQ allotted for cros_ec_lpc,\ndrivers/platform/chrome/cros_ec_lpc.c-653-\t * which makes ENXIO an expected (and safe) scenario.\n--\ndrivers/platform/chrome/cros_ec_lpc.c-675-\t\t\t\t\t\t ACPI_ALL_NOTIFY,\ndrivers/platform/chrome/cros_ec_lpc.c:676:\t\t\t\t\t\t cros_ec_lpc_acpi_notify,\ndrivers/platform/chrome/cros_ec_lpc.c-677-\t\t\t\t\t\t ec_dev);\n--\ndrivers/platform/chrome/cros_ec_lpc.c-685-\ndrivers/platform/chrome/cros_ec_lpc.c:686:static void cros_ec_lpc_remove(struct platform_device *pdev)\ndrivers/platform/chrome/cros_ec_lpc.c-687-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-693-\t\tacpi_remove_notify_handler(adev-\u003ehandle, ACPI_ALL_NOTIFY,\ndrivers/platform/chrome/cros_ec_lpc.c:694:\t\t\t\t\t cros_ec_lpc_acpi_notify);\ndrivers/platform/chrome/cros_ec_lpc.c-695-\n--\ndrivers/platform/chrome/cros_ec_lpc.c=704=static const struct lpc_driver_data framework_laptop_mec_lpc_driver_data __initconst = {\n--\ndrivers/platform/chrome/cros_ec_lpc.c-709-\ndrivers/platform/chrome/cros_ec_lpc.c:710:static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = {\ndrivers/platform/chrome/cros_ec_lpc.c-711-\t{ ACPI_DRV_NAME, 0 },\n--\ndrivers/platform/chrome/cros_ec_lpc.c-714-};\ndrivers/platform/chrome/cros_ec_lpc.c:715:MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids);\ndrivers/platform/chrome/cros_ec_lpc.c-716-\ndrivers/platform/chrome/cros_ec_lpc.c:717:static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = {\ndrivers/platform/chrome/cros_ec_lpc.c-718-\t{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-806-};\ndrivers/platform/chrome/cros_ec_lpc.c:807:MODULE_DEVICE_TABLE(dmi, cros_ec_lpc_dmi_table);\ndrivers/platform/chrome/cros_ec_lpc.c-808-\ndrivers/platform/chrome/cros_ec_lpc.c-809-#ifdef CONFIG_PM_SLEEP\ndrivers/platform/chrome/cros_ec_lpc.c:810:static int cros_ec_lpc_prepare(struct device *dev)\ndrivers/platform/chrome/cros_ec_lpc.c-811-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-815-\ndrivers/platform/chrome/cros_ec_lpc.c:816:static void cros_ec_lpc_complete(struct device *dev)\ndrivers/platform/chrome/cros_ec_lpc.c-817-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-821-\ndrivers/platform/chrome/cros_ec_lpc.c:822:static int cros_ec_lpc_suspend_late(struct device *dev)\ndrivers/platform/chrome/cros_ec_lpc.c-823-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-828-\ndrivers/platform/chrome/cros_ec_lpc.c:829:static int cros_ec_lpc_resume_early(struct device *dev)\ndrivers/platform/chrome/cros_ec_lpc.c-830-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-836-\ndrivers/platform/chrome/cros_ec_lpc.c:837:static const struct dev_pm_ops cros_ec_lpc_pm_ops = {\ndrivers/platform/chrome/cros_ec_lpc.c-838-#ifdef CONFIG_PM_SLEEP\ndrivers/platform/chrome/cros_ec_lpc.c:839:\t.prepare = cros_ec_lpc_prepare,\ndrivers/platform/chrome/cros_ec_lpc.c:840:\t.complete = cros_ec_lpc_complete,\ndrivers/platform/chrome/cros_ec_lpc.c-841-#endif\ndrivers/platform/chrome/cros_ec_lpc.c:842:\tSET_LATE_SYSTEM_SLEEP_PM_OPS(cros_ec_lpc_suspend_late, cros_ec_lpc_resume_early)\ndrivers/platform/chrome/cros_ec_lpc.c-843-};\ndrivers/platform/chrome/cros_ec_lpc.c-844-\ndrivers/platform/chrome/cros_ec_lpc.c:845:static struct platform_driver cros_ec_lpc_driver = {\ndrivers/platform/chrome/cros_ec_lpc.c-846-\t.driver = {\ndrivers/platform/chrome/cros_ec_lpc.c-847-\t\t.name = DRV_NAME,\ndrivers/platform/chrome/cros_ec_lpc.c:848:\t\t.acpi_match_table = cros_ec_lpc_acpi_device_ids,\ndrivers/platform/chrome/cros_ec_lpc.c:849:\t\t.pm = \u0026cros_ec_lpc_pm_ops,\ndrivers/platform/chrome/cros_ec_lpc.c-850-\t\t/*\n--\ndrivers/platform/chrome/cros_ec_lpc.c-856-\t},\ndrivers/platform/chrome/cros_ec_lpc.c:857:\t.probe = cros_ec_lpc_probe,\ndrivers/platform/chrome/cros_ec_lpc.c:858:\t.remove = cros_ec_lpc_remove,\ndrivers/platform/chrome/cros_ec_lpc.c-859-};\ndrivers/platform/chrome/cros_ec_lpc.c-860-\ndrivers/platform/chrome/cros_ec_lpc.c:861:static struct platform_device cros_ec_lpc_device = {\ndrivers/platform/chrome/cros_ec_lpc.c-862-\t.name = DRV_NAME\n--\ndrivers/platform/chrome/cros_ec_lpc.c-864-\ndrivers/platform/chrome/cros_ec_lpc.c:865:static int __init cros_ec_lpc_init(void)\ndrivers/platform/chrome/cros_ec_lpc.c-866-{\n--\ndrivers/platform/chrome/cros_ec_lpc.c-869-\ndrivers/platform/chrome/cros_ec_lpc.c:870:\tcros_ec_lpc_acpi_device_found = !!cros_ec_lpc_get_device(ACPI_DRV_NAME) ||\ndrivers/platform/chrome/cros_ec_lpc.c:871:\t\t!!cros_ec_lpc_get_device(FRMW_ACPI_DRV_NAME);\ndrivers/platform/chrome/cros_ec_lpc.c-872-\ndrivers/platform/chrome/cros_ec_lpc.c:873:\tdmi_match = dmi_first_match(cros_ec_lpc_dmi_table);\ndrivers/platform/chrome/cros_ec_lpc.c-874-\ndrivers/platform/chrome/cros_ec_lpc.c:875:\tif (!cros_ec_lpc_acpi_device_found \u0026\u0026 !dmi_match) {\ndrivers/platform/chrome/cros_ec_lpc.c-876-\t\tpr_err(DRV_NAME \": unsupported system.\\n\");\n--\ndrivers/platform/chrome/cros_ec_lpc.c-880-\t/* Register the driver */\ndrivers/platform/chrome/cros_ec_lpc.c:881:\tret = platform_driver_register(\u0026cros_ec_lpc_driver);\ndrivers/platform/chrome/cros_ec_lpc.c-882-\tif (ret) {\n--\ndrivers/platform/chrome/cros_ec_lpc.c-886-\ndrivers/platform/chrome/cros_ec_lpc.c:887:\tif (!cros_ec_lpc_acpi_device_found) {\ndrivers/platform/chrome/cros_ec_lpc.c-888-\t\t/* Pass the DMI match's driver data down to the platform device */\ndrivers/platform/chrome/cros_ec_lpc.c:889:\t\tplatform_set_drvdata(\u0026cros_ec_lpc_device, dmi_match-\u003edriver_data);\ndrivers/platform/chrome/cros_ec_lpc.c-890-\ndrivers/platform/chrome/cros_ec_lpc.c-891-\t\t/* Register the device, and it'll get hooked up automatically */\ndrivers/platform/chrome/cros_ec_lpc.c:892:\t\tret = platform_device_register(\u0026cros_ec_lpc_device);\ndrivers/platform/chrome/cros_ec_lpc.c-893-\t\tif (ret) {\ndrivers/platform/chrome/cros_ec_lpc.c-894-\t\t\tpr_err(DRV_NAME \": can't register device: %d\\n\", ret);\ndrivers/platform/chrome/cros_ec_lpc.c:895:\t\t\tplatform_driver_unregister(\u0026cros_ec_lpc_driver);\ndrivers/platform/chrome/cros_ec_lpc.c-896-\t\t}\n--\ndrivers/platform/chrome/cros_ec_lpc.c-901-\ndrivers/platform/chrome/cros_ec_lpc.c:902:static void __exit cros_ec_lpc_exit(void)\ndrivers/platform/chrome/cros_ec_lpc.c-903-{\ndrivers/platform/chrome/cros_ec_lpc.c:904:\tif (!cros_ec_lpc_acpi_device_found)\ndrivers/platform/chrome/cros_ec_lpc.c:905:\t\tplatform_device_unregister(\u0026cros_ec_lpc_device);\ndrivers/platform/chrome/cros_ec_lpc.c:906:\tplatform_driver_unregister(\u0026cros_ec_lpc_driver);\ndrivers/platform/chrome/cros_ec_lpc.c-907-}\ndrivers/platform/chrome/cros_ec_lpc.c-908-\ndrivers/platform/chrome/cros_ec_lpc.c:909:module_init(cros_ec_lpc_init);\ndrivers/platform/chrome/cros_ec_lpc.c:910:module_exit(cros_ec_lpc_exit);\ndrivers/platform/chrome/cros_ec_lpc.c-911-\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-10-\ndrivers/platform/chrome/cros_ec_lpc_mec.c:11:#include \"cros_ec_lpc_mec.h\"\ndrivers/platform/chrome/cros_ec_lpc_mec.c-12-\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c=27=static u16 mec_emi_base, mec_emi_end;\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-29-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.c:30: * cros_ec_lpc_mec_lock() - Acquire mutex for EMI\ndrivers/platform/chrome/cros_ec_lpc_mec.c-31- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-33- */\ndrivers/platform/chrome/cros_ec_lpc_mec.c:34:static int cros_ec_lpc_mec_lock(void)\ndrivers/platform/chrome/cros_ec_lpc_mec.c-35-{\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-51-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.c:52: * cros_ec_lpc_mec_unlock() - Release mutex for EMI\ndrivers/platform/chrome/cros_ec_lpc_mec.c-53- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-55- */\ndrivers/platform/chrome/cros_ec_lpc_mec.c:56:static int cros_ec_lpc_mec_unlock(void)\ndrivers/platform/chrome/cros_ec_lpc_mec.c-57-{\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-72-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.c:73: * cros_ec_lpc_mec_emi_write_address() - Initialize EMI at a given address.\ndrivers/platform/chrome/cros_ec_lpc_mec.c-74- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-77- */\ndrivers/platform/chrome/cros_ec_lpc_mec.c:78:static void cros_ec_lpc_mec_emi_write_address(u16 addr,\ndrivers/platform/chrome/cros_ec_lpc_mec.c:79:\t\t\tenum cros_ec_lpc_mec_emi_access_mode access_type)\ndrivers/platform/chrome/cros_ec_lpc_mec.c-80-{\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-85-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.c:86: * cros_ec_lpc_mec_in_range() - Determine if addresses are in MEC EMI range.\ndrivers/platform/chrome/cros_ec_lpc_mec.c-87- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-93- */\ndrivers/platform/chrome/cros_ec_lpc_mec.c:94:int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length)\ndrivers/platform/chrome/cros_ec_lpc_mec.c-95-{\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-111-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.c:112: * cros_ec_lpc_io_bytes_mec() - Read / write bytes to MEC EMI port.\ndrivers/platform/chrome/cros_ec_lpc_mec.c-113- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-121- */\ndrivers/platform/chrome/cros_ec_lpc_mec.c:122:int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type,\ndrivers/platform/chrome/cros_ec_lpc_mec.c-123-\t\t\t unsigned int offset, unsigned int length,\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-128-\tu8 sum = 0;\ndrivers/platform/chrome/cros_ec_lpc_mec.c:129:\tenum cros_ec_lpc_mec_emi_access_mode access, new_access;\ndrivers/platform/chrome/cros_ec_lpc_mec.c-130-\tint ret;\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-148-\ndrivers/platform/chrome/cros_ec_lpc_mec.c:149:\tret = cros_ec_lpc_mec_lock();\ndrivers/platform/chrome/cros_ec_lpc_mec.c-150-\tif (ret)\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-153-\t/* Initialize I/O at desired address */\ndrivers/platform/chrome/cros_ec_lpc_mec.c:154:\tcros_ec_lpc_mec_emi_write_address(offset, access);\ndrivers/platform/chrome/cros_ec_lpc_mec.c-155-\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-184-\t\t\taccess = new_access;\ndrivers/platform/chrome/cros_ec_lpc_mec.c:185:\t\t\tcros_ec_lpc_mec_emi_write_address(offset, access);\ndrivers/platform/chrome/cros_ec_lpc_mec.c-186-\t\t}\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-192-done:\ndrivers/platform/chrome/cros_ec_lpc_mec.c:193:\tret = cros_ec_lpc_mec_unlock();\ndrivers/platform/chrome/cros_ec_lpc_mec.c-194-\tif (ret)\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-198-}\ndrivers/platform/chrome/cros_ec_lpc_mec.c:199:EXPORT_SYMBOL(cros_ec_lpc_io_bytes_mec);\ndrivers/platform/chrome/cros_ec_lpc_mec.c-200-\ndrivers/platform/chrome/cros_ec_lpc_mec.c:201:void cros_ec_lpc_mec_init(unsigned int base, unsigned int end)\ndrivers/platform/chrome/cros_ec_lpc_mec.c-202-{\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-205-}\ndrivers/platform/chrome/cros_ec_lpc_mec.c:206:EXPORT_SYMBOL(cros_ec_lpc_mec_init);\ndrivers/platform/chrome/cros_ec_lpc_mec.c-207-\ndrivers/platform/chrome/cros_ec_lpc_mec.c:208:int cros_ec_lpc_mec_acpi_mutex(struct acpi_device *adev, const char *pathname)\ndrivers/platform/chrome/cros_ec_lpc_mec.c-209-{\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.c-220-}\ndrivers/platform/chrome/cros_ec_lpc_mec.c:221:EXPORT_SYMBOL(cros_ec_lpc_mec_acpi_mutex);\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.h-12-\ndrivers/platform/chrome/cros_ec_lpc_mec.h:13:enum cros_ec_lpc_mec_emi_access_mode {\ndrivers/platform/chrome/cros_ec_lpc_mec.h-14-\t/* 8-bit access */\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.h-26-\ndrivers/platform/chrome/cros_ec_lpc_mec.h:27:enum cros_ec_lpc_mec_io_type {\ndrivers/platform/chrome/cros_ec_lpc_mec.h-28-\tMEC_IO_READ,\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.h-42-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.h:43: * cros_ec_lpc_mec_init() - Initialize MEC I/O.\ndrivers/platform/chrome/cros_ec_lpc_mec.h-44- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.h-47- */\ndrivers/platform/chrome/cros_ec_lpc_mec.h:48:void cros_ec_lpc_mec_init(unsigned int base, unsigned int end);\ndrivers/platform/chrome/cros_ec_lpc_mec.h-49-\ndrivers/platform/chrome/cros_ec_lpc_mec.h-50-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.h:51: * cros_ec_lpc_mec_acpi_mutex() - Find and set ACPI mutex for MEC\ndrivers/platform/chrome/cros_ec_lpc_mec.h-52- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.h-56- */\ndrivers/platform/chrome/cros_ec_lpc_mec.h:57:int cros_ec_lpc_mec_acpi_mutex(struct acpi_device *adev, const char *pathname);\ndrivers/platform/chrome/cros_ec_lpc_mec.h-58-\ndrivers/platform/chrome/cros_ec_lpc_mec.h-59-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.h:60: * cros_ec_lpc_mec_in_range() - Determine if addresses are in MEC EMI range.\ndrivers/platform/chrome/cros_ec_lpc_mec.h-61- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.h-67- */\ndrivers/platform/chrome/cros_ec_lpc_mec.h:68:int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length);\ndrivers/platform/chrome/cros_ec_lpc_mec.h-69-\ndrivers/platform/chrome/cros_ec_lpc_mec.h-70-/**\ndrivers/platform/chrome/cros_ec_lpc_mec.h:71: * cros_ec_lpc_io_bytes_mec - Read / write bytes to MEC EMI port\ndrivers/platform/chrome/cros_ec_lpc_mec.h-72- *\n--\ndrivers/platform/chrome/cros_ec_lpc_mec.h-80- */\ndrivers/platform/chrome/cros_ec_lpc_mec.h:81:int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type,\ndrivers/platform/chrome/cros_ec_lpc_mec.h-82-\t\t\t unsigned int offset, unsigned int length, u8 *buf);\n--\ndrivers/platform/chrome/wilco_ec/core.c-16-\ndrivers/platform/chrome/wilco_ec/core.c:17:#include \"../cros_ec_lpc_mec.h\"\ndrivers/platform/chrome/wilco_ec/core.c-18-\n--\ndrivers/platform/chrome/wilco_ec/core.c=37=static int wilco_ec_probe(struct platform_device *pdev)\n--\ndrivers/platform/chrome/wilco_ec/core.c-63-\t/* Initialize cros_ec register interface for communication */\ndrivers/platform/chrome/wilco_ec/core.c:64:\tcros_ec_lpc_mec_init(ec-\u003eio_packet-\u003estart,\ndrivers/platform/chrome/wilco_ec/core.c-65-\t\t\t ec-\u003eio_packet-\u003estart + EC_MAILBOX_DATA_SIZE);\n--\ndrivers/platform/chrome/wilco_ec/mailbox.c-23-\ndrivers/platform/chrome/wilco_ec/mailbox.c:24:#include \"../cros_ec_lpc_mec.h\"\ndrivers/platform/chrome/wilco_ec/mailbox.c-25-\n--\ndrivers/platform/chrome/wilco_ec/mailbox.c=115=static int wilco_ec_transfer(struct wilco_ec_device *ec,\n--\ndrivers/platform/chrome/wilco_ec/mailbox.c-123-\t/* Write request header, then data */\ndrivers/platform/chrome/wilco_ec/mailbox.c:124:\tret = cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, 0, sizeof(*rq), (u8 *)rq);\ndrivers/platform/chrome/wilco_ec/mailbox.c-125-\tif (ret \u003c 0)\ndrivers/platform/chrome/wilco_ec/mailbox.c-126-\t\treturn ret;\ndrivers/platform/chrome/wilco_ec/mailbox.c:127:\tret = cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, sizeof(*rq), msg-\u003erequest_size,\ndrivers/platform/chrome/wilco_ec/mailbox.c-128-\t\t\t\t msg-\u003erequest_data);\n--\ndrivers/platform/chrome/wilco_ec/mailbox.c-155-\trs = ec-\u003edata_buffer;\ndrivers/platform/chrome/wilco_ec/mailbox.c:156:\tret = cros_ec_lpc_io_bytes_mec(MEC_IO_READ, 0,\ndrivers/platform/chrome/wilco_ec/mailbox.c-157-\t\t\t\t sizeof(*rs) + EC_MAILBOX_DATA_SIZE,\n--\ndrivers/usb/typec/ucsi/cros_ec_ucsi.c=331=static void __maybe_unused cros_ucsi_complete(struct device *dev)\n--\ndrivers/usb/typec/ucsi/cros_ec_ucsi.c-339- * UCSI protocol is also used on ChromeOS platforms which reply on\ndrivers/usb/typec/ucsi/cros_ec_ucsi.c:340: * cros_ec_lpc.c driver for communication with embedded controller (EC).\ndrivers/usb/typec/ucsi/cros_ec_ucsi.c-341- * On such platforms communication with the EC is not available until\ndrivers/usb/typec/ucsi/cros_ec_ucsi.c:342: * the .complete() callback of the cros_ec_lpc driver is executed.\ndrivers/usb/typec/ucsi/cros_ec_ucsi.c-343- * For this reason we delay ucsi_resume() until the .complete() stage\n"
} |
| 29/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 28752 output: 24 thoughts: 251 Thoughts: **My Initial Assessment of `cros_ec_lpc_init`** Alright, let's break down this `cros_ec_lpc_init` function. It seems to be the entry point for initializing the ChromeOS embedded controller (EC) over the LPC bus. The first thing that jumps out is the check for an ACPI device using `cros_ec_lpc_acpi_device_found`. It's looking for either "GOOG0004" (which I recognize as a common EC ACPI ID) or "PNP0C09", and it does this through the `cros_ec_lpc_get_device` function. Hmm, the code uses a double negation (`!!`) – that's a clever way to ensure a boolean result from the get_device calls, ensuring 0/1 rather than negative numbers, right? Then, there's a DMI table lookup with `dmi_match` using `cros_ec_lpc_dmi_table`. If *neither* the ACPI device nor a matching DMI entry are found, it errors out with `-ENODEV`, indicating an unsupported system. A solid, albeit simple, check for platform compatibility. Now, considering the context of QEMU/GCE, which are environments commonly used for syzkaller fuzzing, I'm trying to mentally map how this translates to those virtualized systems. The important question here is, are these ACPI devices present in these environments? My initial gut feeling is that it might depend on the specific QEMU setup and the chosen device tree/ACPI tables. Oh, wait, what's `FRMW_ACPI_DRV_NAME`? I'd better double check that macro. It could be significant. Let me go check that... |
| 30/2 | 2026/09/20 00:18 | tool | grepper |
0mArgs:{
"Expression": "FRMW_ACPI_DRV_NAME"
}Results: {
"Output": "drivers/platform/chrome/cros_ec_lpc.c-32-#define ACPI_DRV_NAME \"GOOG0004\"\ndrivers/platform/chrome/cros_ec_lpc.c:33:#define FRMW_ACPI_DRV_NAME \"FRMWC004\"\ndrivers/platform/chrome/cros_ec_lpc.c-34-\n--\ndrivers/platform/chrome/cros_ec_lpc.c=710=static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = {\ndrivers/platform/chrome/cros_ec_lpc.c-711-\t{ ACPI_DRV_NAME, 0 },\ndrivers/platform/chrome/cros_ec_lpc.c:712:\t{ FRMW_ACPI_DRV_NAME, (kernel_ulong_t)\u0026framework_laptop_npcx_lpc_driver_data },\ndrivers/platform/chrome/cros_ec_lpc.c-713-\t{ }\n--\ndrivers/platform/chrome/cros_ec_lpc.c=865=static int __init cros_ec_lpc_init(void)\n--\ndrivers/platform/chrome/cros_ec_lpc.c-870-\tcros_ec_lpc_acpi_device_found = !!cros_ec_lpc_get_device(ACPI_DRV_NAME) ||\ndrivers/platform/chrome/cros_ec_lpc.c:871:\t\t!!cros_ec_lpc_get_device(FRMW_ACPI_DRV_NAME);\ndrivers/platform/chrome/cros_ec_lpc.c-872-\n"
} |
| 31/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 29852 output: 29 thoughts: 262 Thoughts: **My Analysis of the `cros-ec-typec` Driver's Registration** Okay, so I'm trying to figure out why this `cros-ec-typec` driver isn't registering properly. My immediate thought is, what's the deal with this driver? I was looking at Framework laptops versus Google Chromebooks when I noticed this. First, I had the idea to check the Device Manager Interface (DMI) table in `cros_ec_lpc_dmi_table` – does it somehow identify "GOOGLE" or "Framework" and influence the probing? The table *does* seem to match those, but that doesn't explain the whole picture. Then, I thought about `cros_ec_lpc` itself. Even if that driver *is* probed successfully, I'm not seeing `cros-ec-typec` register as a consequence. That's a key observation. The real question is: *what* is registering `cros-ec-typec`? Time to do some serious detective work. I'm going to systematically comb through the kernel code. I need to find every single place where either `google,cros-ec-typec`, `cros-ec-typec`, or even the ACPI ID `GOOG0014` is mentioned or registered. The ACPI ID seems to *only* be `GOOG0014`, and the only `of_device_id` I'm finding is `google,cros-ec-typec`. This is interesting. Neither QEMU nor GCE seems to be presenting a GOOG0014 ACPI device, and standard amd64 QEMU doesn't use a devicetree with the `google,cros-ec-typec` identifier. That's a bit perplexing. Wait a second… could this be a virtual or mocked setup? Could this driver be probed via some virtual mechanism, a mock driver, or a test environment? I've got to check for any mock drivers, kunit tests, or virtual buses that might be related to `cros-ec-typec` or even just the broader `cros_ec` framework. I need to look for that. That might explain this! |
| 32/2 | 2026/09/20 00:18 | tool | grepper |
0mArgs:{
"Expression": "cros[-_]typec",
"PathPrefix": "drivers/"
}Results: {
"Output": "\nFull output is too long, showing 500 out of 866 lines.\nUse more precise expression if possible.\n\ndrivers/platform/chrome/Kconfig=308=config CROS_TYPEC_SWITCH\n--\ndrivers/platform/chrome/Kconfig-316-\t To compile this driver as a module, choose M here: the module will be\ndrivers/platform/chrome/Kconfig:317:\t called cros_typec_switch.\ndrivers/platform/chrome/Kconfig-318-\n--\ndrivers/platform/chrome/Makefile=15=obj-$(CONFIG_CROS_EC_ISHTP)\t\t+= cros_ec_ishtp.o\ndrivers/platform/chrome/Makefile:16:obj-$(CONFIG_CROS_TYPEC_SWITCH)\t\t+= cros_typec_switch.o\ndrivers/platform/chrome/Makefile-17-obj-$(CONFIG_CROS_EC_RPMSG)\t\t+= cros_ec_rpmsg.o\n--\ndrivers/platform/chrome/Makefile=20=cros_ec_lpcs-objs\t\t\t:= cros_ec_lpc.o cros_ec_lpc_mec.o\ndrivers/platform/chrome/Makefile:21:cros-ec-typec-objs\t\t\t:= cros_ec_typec.o cros_typec_vdm.o\ndrivers/platform/chrome/Makefile-22-ifneq ($(CONFIG_CROS_EC_TYPEC_ALTMODES),)\ndrivers/platform/chrome/Makefile:23:\tcros-ec-typec-objs\t\t+= cros_typec_altmode.o\ndrivers/platform/chrome/Makefile-24-endif\n--\ndrivers/platform/chrome/cros_ec_typec.c-19-#include \"cros_ec_typec.h\"\ndrivers/platform/chrome/cros_ec_typec.c:20:#include \"cros_typec_vdm.h\"\ndrivers/platform/chrome/cros_ec_typec.c:21:#include \"cros_typec_altmode.h\"\ndrivers/platform/chrome/cros_ec_typec.c-22-\n--\ndrivers/platform/chrome/cros_ec_typec.c-29-\ndrivers/platform/chrome/cros_ec_typec.c:30:static void cros_typec_role_switch_quirk(struct fwnode_handle *fwnode)\ndrivers/platform/chrome/cros_ec_typec.c-31-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-46-\ndrivers/platform/chrome/cros_ec_typec.c:47:static int cros_typec_enter_usb_mode(struct typec_port *tc_port, enum usb_mode mode)\ndrivers/platform/chrome/cros_ec_typec.c-48-{\ndrivers/platform/chrome/cros_ec_typec.c:49:\tstruct cros_typec_port *port = typec_get_drvdata(tc_port);\ndrivers/platform/chrome/cros_ec_typec.c-50-\tstruct ec_params_typec_control req = {\n--\ndrivers/platform/chrome/cros_ec_typec.c-60-\ndrivers/platform/chrome/cros_ec_typec.c:61:static int cros_typec_perform_role_swap(struct typec_port *tc_port, int target_role, u8 swap_type)\ndrivers/platform/chrome/cros_ec_typec.c-62-{\ndrivers/platform/chrome/cros_ec_typec.c:63:\tstruct cros_typec_port *port = typec_get_drvdata(tc_port);\ndrivers/platform/chrome/cros_ec_typec.c:64:\tstruct cros_typec_data *data = port-\u003etypec_data;\ndrivers/platform/chrome/cros_ec_typec.c-65-\tstruct ec_response_usb_pd_control_v2 resp;\n--\ndrivers/platform/chrome/cros_ec_typec.c-131-\ndrivers/platform/chrome/cros_ec_typec.c:132:static int cros_typec_dr_swap(struct typec_port *port, enum typec_data_role role)\ndrivers/platform/chrome/cros_ec_typec.c-133-{\ndrivers/platform/chrome/cros_ec_typec.c:134:\treturn cros_typec_perform_role_swap(port, role, USB_PD_CTRL_SWAP_DATA);\ndrivers/platform/chrome/cros_ec_typec.c-135-}\ndrivers/platform/chrome/cros_ec_typec.c-136-\ndrivers/platform/chrome/cros_ec_typec.c:137:static int cros_typec_pr_swap(struct typec_port *port, enum typec_role role)\ndrivers/platform/chrome/cros_ec_typec.c-138-{\ndrivers/platform/chrome/cros_ec_typec.c:139:\treturn cros_typec_perform_role_swap(port, role, USB_PD_CTRL_SWAP_POWER);\ndrivers/platform/chrome/cros_ec_typec.c-140-}\ndrivers/platform/chrome/cros_ec_typec.c-141-\ndrivers/platform/chrome/cros_ec_typec.c:142:static const struct typec_operations cros_typec_usb_mode_ops = {\ndrivers/platform/chrome/cros_ec_typec.c:143:\t.enter_usb_mode = cros_typec_enter_usb_mode,\ndrivers/platform/chrome/cros_ec_typec.c:144:\t.dr_set = cros_typec_dr_swap,\ndrivers/platform/chrome/cros_ec_typec.c:145:\t.pr_set = cros_typec_pr_swap,\ndrivers/platform/chrome/cros_ec_typec.c-146-};\ndrivers/platform/chrome/cros_ec_typec.c-147-\ndrivers/platform/chrome/cros_ec_typec.c:148:static int cros_typec_parse_port_props(struct typec_capability *cap,\ndrivers/platform/chrome/cros_ec_typec.c-149-\t\t\t\t struct fwnode_handle *fwnode,\n--\ndrivers/platform/chrome/cros_ec_typec.c-196-\ndrivers/platform/chrome/cros_ec_typec.c:197:\tcros_typec_role_switch_quirk(fwnode);\ndrivers/platform/chrome/cros_ec_typec.c-198-\n--\ndrivers/platform/chrome/cros_ec_typec.c-203-\ndrivers/platform/chrome/cros_ec_typec.c:204:static int cros_typec_get_switch_handles(struct cros_typec_port *port,\ndrivers/platform/chrome/cros_ec_typec.c-205-\t\t\t\t\t struct fwnode_handle *fwnode,\n--\ndrivers/platform/chrome/cros_ec_typec.c-252-\ndrivers/platform/chrome/cros_ec_typec.c:253:static int cros_typec_add_partner(struct cros_typec_data *typec, int port_num,\ndrivers/platform/chrome/cros_ec_typec.c-254-\t\t\t\t bool pd_en)\ndrivers/platform/chrome/cros_ec_typec.c-255-{\ndrivers/platform/chrome/cros_ec_typec.c:256:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-257-\tstruct typec_partner_desc p_desc = {\n--\ndrivers/platform/chrome/cros_ec_typec.c-276-\ndrivers/platform/chrome/cros_ec_typec.c:277:static void cros_typec_unregister_altmodes(struct cros_typec_data *typec, int port_num,\ndrivers/platform/chrome/cros_ec_typec.c-278-\t\t\t\t\t bool is_partner)\ndrivers/platform/chrome/cros_ec_typec.c-279-{\ndrivers/platform/chrome/cros_ec_typec.c:280:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c:281:\tstruct cros_typec_altmode_node *node, *tmp;\ndrivers/platform/chrome/cros_ec_typec.c-282-\tstruct list_head *head;\n--\ndrivers/platform/chrome/cros_ec_typec.c-295- */\ndrivers/platform/chrome/cros_ec_typec.c:296:static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_mux_state state)\ndrivers/platform/chrome/cros_ec_typec.c-297-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-306-\ndrivers/platform/chrome/cros_ec_typec.c:307:static int cros_typec_usb_disconnect_state(struct cros_typec_port *port)\ndrivers/platform/chrome/cros_ec_typec.c-308-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-314-\ttypec_switch_set(port-\u003eori_sw, TYPEC_ORIENTATION_NONE);\ndrivers/platform/chrome/cros_ec_typec.c:315:\tcros_typec_retimer_set(port-\u003eretimer, port-\u003estate);\ndrivers/platform/chrome/cros_ec_typec.c-316-\n--\ndrivers/platform/chrome/cros_ec_typec.c-319-\ndrivers/platform/chrome/cros_ec_typec.c:320:static void cros_typec_remove_partner(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-321-\t\t\t\t int port_num)\ndrivers/platform/chrome/cros_ec_typec.c-322-{\ndrivers/platform/chrome/cros_ec_typec.c:323:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-324-\n--\ndrivers/platform/chrome/cros_ec_typec.c-327-\ndrivers/platform/chrome/cros_ec_typec.c:328:\tcros_typec_unregister_altmodes(typec, port_num, true);\ndrivers/platform/chrome/cros_ec_typec.c-329-\n--\ndrivers/platform/chrome/cros_ec_typec.c-337-\ndrivers/platform/chrome/cros_ec_typec.c:338:\tcros_typec_usb_disconnect_state(port);\ndrivers/platform/chrome/cros_ec_typec.c-339-\tport-\u003emux_flags = USB_PD_MUX_NONE;\n--\ndrivers/platform/chrome/cros_ec_typec.c-346-\ndrivers/platform/chrome/cros_ec_typec.c:347:static void cros_typec_remove_cable(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-348-\t\t\t\t int port_num)\ndrivers/platform/chrome/cros_ec_typec.c-349-{\ndrivers/platform/chrome/cros_ec_typec.c:350:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-351-\n--\ndrivers/platform/chrome/cros_ec_typec.c-354-\ndrivers/platform/chrome/cros_ec_typec.c:355:\tcros_typec_unregister_altmodes(typec, port_num, false);\ndrivers/platform/chrome/cros_ec_typec.c-356-\n--\ndrivers/platform/chrome/cros_ec_typec.c-364-\ndrivers/platform/chrome/cros_ec_typec.c:365:static void cros_typec_unregister_port_altmodes(struct cros_typec_port *port)\ndrivers/platform/chrome/cros_ec_typec.c-366-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-372-\ndrivers/platform/chrome/cros_ec_typec.c:373:static void cros_unregister_ports(struct cros_typec_data *typec)\ndrivers/platform/chrome/cros_ec_typec.c-374-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-380-\ndrivers/platform/chrome/cros_ec_typec.c:381:\t\tcros_typec_altmodes_stop(typec-\u003eports[i]);\ndrivers/platform/chrome/cros_ec_typec.c:382:\t\tcros_typec_remove_partner(typec, i);\ndrivers/platform/chrome/cros_ec_typec.c:383:\t\tcros_typec_remove_cable(typec, i);\ndrivers/platform/chrome/cros_ec_typec.c-384-\n--\ndrivers/platform/chrome/cros_ec_typec.c-387-\t\ttypec_mux_put(typec-\u003eports[i]-\u003emux);\ndrivers/platform/chrome/cros_ec_typec.c:388:\t\tcros_typec_unregister_port_altmodes(typec-\u003eports[i]);\ndrivers/platform/chrome/cros_ec_typec.c-389-\t\ttypec_unregister_port(typec-\u003eports[i]-\u003eport);\n--\ndrivers/platform/chrome/cros_ec_typec.c-396- */\ndrivers/platform/chrome/cros_ec_typec.c:397:static int cros_typec_register_port_altmodes(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-398-\t\t\t\t\t int port_num)\ndrivers/platform/chrome/cros_ec_typec.c-399-{\ndrivers/platform/chrome/cros_ec_typec.c:400:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-401-\tstruct typec_altmode_desc desc;\n--\ndrivers/platform/chrome/cros_ec_typec.c-408-\tdesc.vdo = DP_PORT_VDO;\ndrivers/platform/chrome/cros_ec_typec.c:409:\tamode = cros_typec_register_displayport(port, \u0026desc,\ndrivers/platform/chrome/cros_ec_typec.c-410-\t\t\t\t\t\ttypec-\u003eap_driven_altmode);\n--\ndrivers/platform/chrome/cros_ec_typec.c-425-\t\tdesc.inactive = true;\ndrivers/platform/chrome/cros_ec_typec.c:426:\t\tamode = cros_typec_register_thunderbolt(port, \u0026desc);\ndrivers/platform/chrome/cros_ec_typec.c-427-\t\tif (IS_ERR(amode))\n--\ndrivers/platform/chrome/cros_ec_typec.c-438-\ndrivers/platform/chrome/cros_ec_typec.c:439:static int cros_typec_init_ports(struct cros_typec_data *typec)\ndrivers/platform/chrome/cros_ec_typec.c-440-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-443-\tstruct fwnode_handle *fwnode;\ndrivers/platform/chrome/cros_ec_typec.c:444:\tstruct cros_typec_port *cros_port;\ndrivers/platform/chrome/cros_ec_typec.c-445-\tconst char *port_prop;\n--\ndrivers/platform/chrome/cros_ec_typec.c-488-\ndrivers/platform/chrome/cros_ec_typec.c:489:\t\tret = cros_typec_parse_port_props(cap, fwnode, dev);\ndrivers/platform/chrome/cros_ec_typec.c-490-\t\tif (ret \u003c 0)\n--\ndrivers/platform/chrome/cros_ec_typec.c-493-\t\tcap-\u003edriver_data = cros_port;\ndrivers/platform/chrome/cros_ec_typec.c:494:\t\tcap-\u003eops = \u0026cros_typec_usb_mode_ops;\ndrivers/platform/chrome/cros_ec_typec.c-495-\t\tcap-\u003eno_mode_control = !typec-\u003eap_driven_altmode;\n--\ndrivers/platform/chrome/cros_ec_typec.c-503-\ndrivers/platform/chrome/cros_ec_typec.c:504:\t\tret = cros_typec_get_switch_handles(cros_port, fwnode, dev);\ndrivers/platform/chrome/cros_ec_typec.c-505-\t\tif (ret) {\n--\ndrivers/platform/chrome/cros_ec_typec.c-510-\ndrivers/platform/chrome/cros_ec_typec.c:511:\t\tret = cros_typec_register_port_altmodes(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c-512-\t\tif (ret) {\n--\ndrivers/platform/chrome/cros_ec_typec.c-534-\ndrivers/platform/chrome/cros_ec_typec.c:535:static int cros_typec_usb_safe_state(struct cros_typec_port *port)\ndrivers/platform/chrome/cros_ec_typec.c-536-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-539-\ndrivers/platform/chrome/cros_ec_typec.c:540:\tret = cros_typec_retimer_set(port-\u003eretimer, port-\u003estate);\ndrivers/platform/chrome/cros_ec_typec.c-541-\tif (!ret)\n--\ndrivers/platform/chrome/cros_ec_typec.c-547-/**\ndrivers/platform/chrome/cros_ec_typec.c:548: * cros_typec_get_cable_vdo() - Get Cable VDO of the connected cable\ndrivers/platform/chrome/cros_ec_typec.c-549- * @port: Type-C port data\n--\ndrivers/platform/chrome/cros_ec_typec.c-553- */\ndrivers/platform/chrome/cros_ec_typec.c:554:static int cros_typec_get_cable_vdo(struct cros_typec_port *port, u16 svid)\ndrivers/platform/chrome/cros_ec_typec.c-555-{\ndrivers/platform/chrome/cros_ec_typec.c-556-\tstruct list_head *head = \u0026port-\u003eplug_mode_list;\ndrivers/platform/chrome/cros_ec_typec.c:557:\tstruct cros_typec_altmode_node *node;\ndrivers/platform/chrome/cros_ec_typec.c-558-\tu32 ret = 0;\n--\ndrivers/platform/chrome/cros_ec_typec.c-571- */\ndrivers/platform/chrome/cros_ec_typec.c:572:static int cros_typec_enable_tbt(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-573-\t\t\t\t int port_num,\n--\ndrivers/platform/chrome/cros_ec_typec.c-575-{\ndrivers/platform/chrome/cros_ec_typec.c:576:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-577-\tstruct typec_thunderbolt_data data;\n--\ndrivers/platform/chrome/cros_ec_typec.c-594-\ndrivers/platform/chrome/cros_ec_typec.c:595:\tdata.cable_mode |= cros_typec_get_cable_vdo(port, USB_TYPEC_TBT_SID);\ndrivers/platform/chrome/cros_ec_typec.c-596-\n--\ndrivers/platform/chrome/cros_ec_typec.c-614-\t\tport-\u003estate.alt = port-\u003eport_altmode[CROS_EC_ALTMODE_TBT];\ndrivers/platform/chrome/cros_ec_typec.c:615:\t\tret = cros_typec_usb_safe_state(port);\ndrivers/platform/chrome/cros_ec_typec.c-616-\t\tif (ret)\n--\ndrivers/platform/chrome/cros_ec_typec.c-626-/* Spoof the VDOs that were likely communicated by the partner. */\ndrivers/platform/chrome/cros_ec_typec.c:627:static int cros_typec_enable_dp(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-628-\t\t\t\tint port_num,\n--\ndrivers/platform/chrome/cros_ec_typec.c-630-{\ndrivers/platform/chrome/cros_ec_typec.c:631:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-632-\tstruct typec_displayport_data dp_data;\n--\ndrivers/platform/chrome/cros_ec_typec.c-658-\t\tport-\u003estate.alt = port-\u003eport_altmode[CROS_EC_ALTMODE_DP];\ndrivers/platform/chrome/cros_ec_typec.c:659:\t\tret = cros_typec_usb_safe_state(port);\ndrivers/platform/chrome/cros_ec_typec.c-660-\t\tif (ret)\n--\ndrivers/platform/chrome/cros_ec_typec.c-667-\t/* Get cable VDO for cables with DPSID to check DPAM2.1 is supported */\ndrivers/platform/chrome/cros_ec_typec.c:668:\tcable_dp_vdo = cros_typec_get_cable_vdo(port, USB_TYPEC_DP_SID);\ndrivers/platform/chrome/cros_ec_typec.c-669-\n--\ndrivers/platform/chrome/cros_ec_typec.c-673-\t */\ndrivers/platform/chrome/cros_ec_typec.c:674:\tcable_tbt_vdo = cros_typec_get_cable_vdo(port, USB_TYPEC_TBT_SID);\ndrivers/platform/chrome/cros_ec_typec.c-675-\n--\ndrivers/platform/chrome/cros_ec_typec.c-692-\ndrivers/platform/chrome/cros_ec_typec.c:693:\tret = cros_typec_retimer_set(port-\u003eretimer, port-\u003estate);\ndrivers/platform/chrome/cros_ec_typec.c-694-\tif (!ret)\n--\ndrivers/platform/chrome/cros_ec_typec.c-697-\tif (!ret)\ndrivers/platform/chrome/cros_ec_typec.c:698:\t\tret = cros_typec_displayport_status_update(port-\u003estate.alt,\ndrivers/platform/chrome/cros_ec_typec.c-699-\t\t\t\t\t\t\t port-\u003estate.data);\n--\ndrivers/platform/chrome/cros_ec_typec.c-703-\ndrivers/platform/chrome/cros_ec_typec.c:704:static int cros_typec_enable_usb4(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-705-\t\t\t\t int port_num,\n--\ndrivers/platform/chrome/cros_ec_typec.c-707-{\ndrivers/platform/chrome/cros_ec_typec.c:708:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-709-\tstruct enter_usb_data data;\n--\ndrivers/platform/chrome/cros_ec_typec.c-718-\t\tdata.eudo |= EUDO_CABLE_TYPE_OPTICAL \u003c\u003c EUDO_CABLE_TYPE_SHIFT;\ndrivers/platform/chrome/cros_ec_typec.c:719:\telse if (cros_typec_get_cable_vdo(port, USB_TYPEC_TBT_SID) \u0026 TBT_CABLE_RETIMER)\ndrivers/platform/chrome/cros_ec_typec.c-720-\t\tdata.eudo |= EUDO_CABLE_TYPE_RE_TIMER \u003c\u003c EUDO_CABLE_TYPE_SHIFT;\n--\ndrivers/platform/chrome/cros_ec_typec.c-733-\ndrivers/platform/chrome/cros_ec_typec.c:734:static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num,\ndrivers/platform/chrome/cros_ec_typec.c-735-\t\t\t\tstruct ec_response_usb_pd_control_v2 *pd_ctrl)\ndrivers/platform/chrome/cros_ec_typec.c-736-{\ndrivers/platform/chrome/cros_ec_typec.c:737:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-738-\tstruct ec_response_usb_pd_mux_info resp;\n--\ndrivers/platform/chrome/cros_ec_typec.c-743-\tenum typec_orientation orientation;\ndrivers/platform/chrome/cros_ec_typec.c:744:\tstruct cros_typec_altmode_node *node;\ndrivers/platform/chrome/cros_ec_typec.c-745-\tint ret;\n--\ndrivers/platform/chrome/cros_ec_typec.c-762-\tif (port-\u003emux_flags == USB_PD_MUX_NONE) {\ndrivers/platform/chrome/cros_ec_typec.c:763:\t\tret = cros_typec_usb_disconnect_state(port);\ndrivers/platform/chrome/cros_ec_typec.c-764-\t\tgoto mux_ack;\n--\ndrivers/platform/chrome/cros_ec_typec.c-782-\tif (port-\u003emux_flags \u0026 USB_PD_MUX_USB4_ENABLED) {\ndrivers/platform/chrome/cros_ec_typec.c:783:\t\tret = cros_typec_enable_usb4(typec, port_num, pd_ctrl);\ndrivers/platform/chrome/cros_ec_typec.c-784-\t} else if (port-\u003emux_flags \u0026 USB_PD_MUX_TBT_COMPAT_ENABLED) {\ndrivers/platform/chrome/cros_ec_typec.c:785:\t\tret = cros_typec_enable_tbt(typec, port_num, pd_ctrl);\ndrivers/platform/chrome/cros_ec_typec.c-786-\t} else if (port-\u003emux_flags \u0026 USB_PD_MUX_DP_ENABLED) {\ndrivers/platform/chrome/cros_ec_typec.c:787:\t\tret = cros_typec_enable_dp(typec, port_num, pd_ctrl);\ndrivers/platform/chrome/cros_ec_typec.c-788-\t} else if (port-\u003emux_flags \u0026 USB_PD_MUX_SAFE_MODE) {\ndrivers/platform/chrome/cros_ec_typec.c:789:\t\tret = cros_typec_usb_safe_state(port);\ndrivers/platform/chrome/cros_ec_typec.c-790-\t} else if (port-\u003emux_flags \u0026 USB_PD_MUX_USB_ENABLED) {\n--\ndrivers/platform/chrome/cros_ec_typec.c-793-\ndrivers/platform/chrome/cros_ec_typec.c:794:\t\tret = cros_typec_retimer_set(port-\u003eretimer, port-\u003estate);\ndrivers/platform/chrome/cros_ec_typec.c-795-\t\tif (!ret)\n--\ndrivers/platform/chrome/cros_ec_typec.c-826-\ndrivers/platform/chrome/cros_ec_typec.c:827:static void cros_typec_set_port_params_v0(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-828-\t\tint port_num, struct ec_response_usb_pd_control *resp)\n--\ndrivers/platform/chrome/cros_ec_typec.c-843-\ndrivers/platform/chrome/cros_ec_typec.c:844:static void cros_typec_set_port_params_v1(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-845-\t\tint port_num, struct ec_response_usb_pd_control_v1 *resp)\n--\ndrivers/platform/chrome/cros_ec_typec.c-871-\t\tpd_en = resp-\u003eenabled \u0026 PD_CTRL_RESP_ENABLED_PD_CAPABLE;\ndrivers/platform/chrome/cros_ec_typec.c:872:\t\tret = cros_typec_add_partner(typec, port_num, pd_en);\ndrivers/platform/chrome/cros_ec_typec.c-873-\t\tif (ret)\n--\ndrivers/platform/chrome/cros_ec_typec.c-877-\t} else {\ndrivers/platform/chrome/cros_ec_typec.c:878:\t\tcros_typec_remove_partner(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c:879:\t\tcros_typec_remove_cable(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c-880-\t}\n--\ndrivers/platform/chrome/cros_ec_typec.c-885- */\ndrivers/platform/chrome/cros_ec_typec.c:886:static int cros_typec_register_altmodes(struct cros_typec_data *typec, int port_num,\ndrivers/platform/chrome/cros_ec_typec.c-887-\t\t\t\t\tbool is_partner)\ndrivers/platform/chrome/cros_ec_typec.c-888-{\ndrivers/platform/chrome/cros_ec_typec.c:889:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-890-\tstruct ec_response_typec_discovery *sop_disc = port-\u003edisc_data;\ndrivers/platform/chrome/cros_ec_typec.c:891:\tstruct cros_typec_altmode_node *node;\ndrivers/platform/chrome/cros_ec_typec.c-892-\tstruct typec_altmode_desc desc;\n--\ndrivers/platform/chrome/cros_ec_typec.c-946-err_cleanup:\ndrivers/platform/chrome/cros_ec_typec.c:947:\tcros_typec_unregister_altmodes(typec, port_num, is_partner);\ndrivers/platform/chrome/cros_ec_typec.c-948-\treturn ret;\n--\ndrivers/platform/chrome/cros_ec_typec.c-954- */\ndrivers/platform/chrome/cros_ec_typec.c:955:static void cros_typec_parse_pd_identity(struct usb_pd_identity *id,\ndrivers/platform/chrome/cros_ec_typec.c-956-\t\t\t\t\t struct ec_response_typec_discovery *disc)\n--\ndrivers/platform/chrome/cros_ec_typec.c-972-\ndrivers/platform/chrome/cros_ec_typec.c:973:static int cros_typec_handle_sop_prime_disc(struct cros_typec_data *typec, int port_num, u16 pd_revision)\ndrivers/platform/chrome/cros_ec_typec.c-974-{\ndrivers/platform/chrome/cros_ec_typec.c:975:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-976-\tstruct ec_response_typec_discovery *disc = port-\u003edisc_data;\n--\ndrivers/platform/chrome/cros_ec_typec.c-994-\t/* Parse the PD identity data, even if only 0s were returned. */\ndrivers/platform/chrome/cros_ec_typec.c:995:\tcros_typec_parse_pd_identity(\u0026port-\u003ec_identity, disc);\ndrivers/platform/chrome/cros_ec_typec.c-996-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1035-\ndrivers/platform/chrome/cros_ec_typec.c:1036:\tret = cros_typec_register_altmodes(typec, port_num, false);\ndrivers/platform/chrome/cros_ec_typec.c-1037-\tif (ret \u003c 0) {\n--\ndrivers/platform/chrome/cros_ec_typec.c-1044-sop_prime_disc_exit:\ndrivers/platform/chrome/cros_ec_typec.c:1045:\tcros_typec_remove_cable(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c-1046-\treturn ret;\n--\ndrivers/platform/chrome/cros_ec_typec.c-1048-\ndrivers/platform/chrome/cros_ec_typec.c:1049:static int cros_typec_handle_sop_disc(struct cros_typec_data *typec, int port_num, u16 pd_revision)\ndrivers/platform/chrome/cros_ec_typec.c-1050-{\ndrivers/platform/chrome/cros_ec_typec.c:1051:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-1052-\tstruct ec_response_typec_discovery *sop_disc = port-\u003edisc_data;\n--\ndrivers/platform/chrome/cros_ec_typec.c-1076-\ndrivers/platform/chrome/cros_ec_typec.c:1077:\tcros_typec_parse_pd_identity(\u0026port-\u003ep_identity, sop_disc);\ndrivers/platform/chrome/cros_ec_typec.c-1078-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1084-\ndrivers/platform/chrome/cros_ec_typec.c:1085:\tret = cros_typec_register_altmodes(typec, port_num, true);\ndrivers/platform/chrome/cros_ec_typec.c-1086-\tif (ret \u003c 0) {\n--\ndrivers/platform/chrome/cros_ec_typec.c-1094-\ndrivers/platform/chrome/cros_ec_typec.c:1095:static int cros_typec_send_clear_event(struct cros_typec_data *typec, int port_num, u32 events_mask)\ndrivers/platform/chrome/cros_ec_typec.c-1096-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-1106-\ndrivers/platform/chrome/cros_ec_typec.c:1107:static void cros_typec_register_partner_pdos(struct cros_typec_data *typec,\ndrivers/platform/chrome/cros_ec_typec.c-1108-\t\t\t\t\t struct ec_response_typec_status *resp, int port_num)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1113-\t};\ndrivers/platform/chrome/cros_ec_typec.c:1114:\tstruct cros_typec_port *port = typec-\u003eports[port_num];\ndrivers/platform/chrome/cros_ec_typec.c-1115-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1152-\ndrivers/platform/chrome/cros_ec_typec.c:1153:static void cros_typec_handle_status(struct cros_typec_data *typec, int port_num)\ndrivers/platform/chrome/cros_ec_typec.c-1154-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-1169-\tif (resp.events \u0026 PD_STATUS_EVENT_HARD_RESET) {\ndrivers/platform/chrome/cros_ec_typec.c:1170:\t\tcros_typec_remove_partner(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c:1171:\t\tcros_typec_remove_cable(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c-1172-\ndrivers/platform/chrome/cros_ec_typec.c:1173:\t\tret = cros_typec_send_clear_event(typec, port_num,\ndrivers/platform/chrome/cros_ec_typec.c-1174-\t\t\t\t\t\t PD_STATUS_EVENT_HARD_RESET);\n--\ndrivers/platform/chrome/cros_ec_typec.c-1186-\t\tsop_revision = (le16_to_cpu(resp.sop_revision) \u0026 0xff00) \u003e\u003e 4;\ndrivers/platform/chrome/cros_ec_typec.c:1187:\t\tret = cros_typec_handle_sop_disc(typec, port_num, sop_revision);\ndrivers/platform/chrome/cros_ec_typec.c-1188-\t\tif (ret \u003c 0)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1191-\t\t\ttypec-\u003eports[port_num]-\u003esop_disc_done = true;\ndrivers/platform/chrome/cros_ec_typec.c:1192:\t\t\tret = cros_typec_send_clear_event(typec, port_num,\ndrivers/platform/chrome/cros_ec_typec.c-1193-\t\t\t\t\t\t\t PD_STATUS_EVENT_SOP_DISC_DONE);\n--\ndrivers/platform/chrome/cros_ec_typec.c-1200-\ndrivers/platform/chrome/cros_ec_typec.c:1201:\t\tcros_typec_register_partner_pdos(typec, \u0026resp, port_num);\ndrivers/platform/chrome/cros_ec_typec.c-1202-\t}\n--\ndrivers/platform/chrome/cros_ec_typec.c-1209-\t\tsop_prime_revision = (le16_to_cpu(resp.sop_prime_revision) \u0026 0xff00) \u003e\u003e 4;\ndrivers/platform/chrome/cros_ec_typec.c:1210:\t\tret = cros_typec_handle_sop_prime_disc(typec, port_num, sop_prime_revision);\ndrivers/platform/chrome/cros_ec_typec.c-1211-\t\tif (ret \u003c 0)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1214-\t\t\ttypec-\u003eports[port_num]-\u003esop_prime_disc_done = true;\ndrivers/platform/chrome/cros_ec_typec.c:1215:\t\t\tret = cros_typec_send_clear_event(typec, port_num,\ndrivers/platform/chrome/cros_ec_typec.c-1216-\t\t\t\t\t\t\t PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);\n--\ndrivers/platform/chrome/cros_ec_typec.c-1223-\tif (resp.events \u0026 PD_STATUS_EVENT_VDM_REQ_REPLY) {\ndrivers/platform/chrome/cros_ec_typec.c:1224:\t\tcros_typec_handle_vdm_response(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c:1225:\t\tret = cros_typec_send_clear_event(typec, port_num, PD_STATUS_EVENT_VDM_REQ_REPLY);\ndrivers/platform/chrome/cros_ec_typec.c-1226-\t\tif (ret \u003c 0)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1230-\tif (resp.events \u0026 PD_STATUS_EVENT_VDM_ATTENTION) {\ndrivers/platform/chrome/cros_ec_typec.c:1231:\t\tcros_typec_handle_vdm_attention(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c:1232:\t\tret = cros_typec_send_clear_event(typec, port_num, PD_STATUS_EVENT_VDM_ATTENTION);\ndrivers/platform/chrome/cros_ec_typec.c-1233-\t\tif (ret \u003c 0)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1238-\ndrivers/platform/chrome/cros_ec_typec.c:1239:static int cros_typec_port_update(struct cros_typec_data *typec, int port_num)\ndrivers/platform/chrome/cros_ec_typec.c-1240-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-1262-\t/* Update the switches if they exist, according to requested state */\ndrivers/platform/chrome/cros_ec_typec.c:1263:\tret = cros_typec_configure_mux(typec, port_num, \u0026resp);\ndrivers/platform/chrome/cros_ec_typec.c-1264-\tif (ret)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1272-\tif (typec-\u003epd_ctrl_ver != 0)\ndrivers/platform/chrome/cros_ec_typec.c:1273:\t\tcros_typec_set_port_params_v1(typec, port_num,\ndrivers/platform/chrome/cros_ec_typec.c-1274-\t\t\t(struct ec_response_usb_pd_control_v1 *)\u0026resp);\ndrivers/platform/chrome/cros_ec_typec.c-1275-\telse\ndrivers/platform/chrome/cros_ec_typec.c:1276:\t\tcros_typec_set_port_params_v0(typec, port_num,\ndrivers/platform/chrome/cros_ec_typec.c-1277-\t\t\t(struct ec_response_usb_pd_control *) \u0026resp);\n--\ndrivers/platform/chrome/cros_ec_typec.c-1279-\tif (typec-\u003etypec_cmd_supported)\ndrivers/platform/chrome/cros_ec_typec.c:1280:\t\tcros_typec_handle_status(typec, port_num);\ndrivers/platform/chrome/cros_ec_typec.c-1281-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1284-\ndrivers/platform/chrome/cros_ec_typec.c:1285:static int cros_typec_get_cmd_version(struct cros_typec_data *typec)\ndrivers/platform/chrome/cros_ec_typec.c-1286-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-1310-\ndrivers/platform/chrome/cros_ec_typec.c:1311:static void cros_typec_port_work(struct work_struct *work)\ndrivers/platform/chrome/cros_ec_typec.c-1312-{\ndrivers/platform/chrome/cros_ec_typec.c:1313:\tstruct cros_typec_data *typec = container_of(work, struct cros_typec_data, port_work);\ndrivers/platform/chrome/cros_ec_typec.c-1314-\tint ret, i;\n--\ndrivers/platform/chrome/cros_ec_typec.c-1316-\tfor (i = 0; i \u003c typec-\u003enum_ports; i++) {\ndrivers/platform/chrome/cros_ec_typec.c:1317:\t\tret = cros_typec_port_update(typec, i);\ndrivers/platform/chrome/cros_ec_typec.c-1318-\t\tif (ret \u003c 0)\n--\ndrivers/platform/chrome/cros_ec_typec.c=1323=static int cros_ec_typec_event(struct notifier_block *nb,\n--\ndrivers/platform/chrome/cros_ec_typec.c-1325-{\ndrivers/platform/chrome/cros_ec_typec.c:1326:\tstruct cros_typec_data *typec = container_of(nb, struct cros_typec_data, nb);\ndrivers/platform/chrome/cros_ec_typec.c-1327-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1334-#ifdef CONFIG_ACPI\ndrivers/platform/chrome/cros_ec_typec.c:1335:static const struct acpi_device_id cros_typec_acpi_id[] = {\ndrivers/platform/chrome/cros_ec_typec.c-1336-\t{ \"GOOG0014\", 0 },\n--\ndrivers/platform/chrome/cros_ec_typec.c-1338-};\ndrivers/platform/chrome/cros_ec_typec.c:1339:MODULE_DEVICE_TABLE(acpi, cros_typec_acpi_id);\ndrivers/platform/chrome/cros_ec_typec.c-1340-#endif\n--\ndrivers/platform/chrome/cros_ec_typec.c-1342-#ifdef CONFIG_OF\ndrivers/platform/chrome/cros_ec_typec.c:1343:static const struct of_device_id cros_typec_of_match[] = {\ndrivers/platform/chrome/cros_ec_typec.c-1344-\t{ .compatible = \"google,cros-ec-typec\", },\n--\ndrivers/platform/chrome/cros_ec_typec.c-1346-};\ndrivers/platform/chrome/cros_ec_typec.c:1347:MODULE_DEVICE_TABLE(of, cros_typec_of_match);\ndrivers/platform/chrome/cros_ec_typec.c-1348-#endif\ndrivers/platform/chrome/cros_ec_typec.c-1349-\ndrivers/platform/chrome/cros_ec_typec.c:1350:static int cros_typec_probe(struct platform_device *pdev)\ndrivers/platform/chrome/cros_ec_typec.c-1351-{\n--\ndrivers/platform/chrome/cros_ec_typec.c-1353-\tstruct device *dev = \u0026pdev-\u003edev;\ndrivers/platform/chrome/cros_ec_typec.c:1354:\tstruct cros_typec_data *typec;\ndrivers/platform/chrome/cros_ec_typec.c-1355-\tstruct ec_response_usb_pd_ports resp;\n--\ndrivers/platform/chrome/cros_ec_typec.c-1371-\ndrivers/platform/chrome/cros_ec_typec.c:1372:\tret = cros_typec_get_cmd_version(typec);\ndrivers/platform/chrome/cros_ec_typec.c-1373-\tif (ret \u003c 0) {\n--\ndrivers/platform/chrome/cros_ec_typec.c-1399-\ndrivers/platform/chrome/cros_ec_typec.c:1400:\tret = cros_typec_init_ports(typec);\ndrivers/platform/chrome/cros_ec_typec.c-1401-\tif (ret \u003c 0)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1403-\ndrivers/platform/chrome/cros_ec_typec.c:1404:\tINIT_WORK(\u0026typec-\u003eport_work, cros_typec_port_work);\ndrivers/platform/chrome/cros_ec_typec.c-1405-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1410-\tfor (i = 0; i \u003c typec-\u003enum_ports; i++) {\ndrivers/platform/chrome/cros_ec_typec.c:1411:\t\tret = cros_typec_port_update(typec, i);\ndrivers/platform/chrome/cros_ec_typec.c-1412-\t\tif (ret \u003c 0)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1427-\ndrivers/platform/chrome/cros_ec_typec.c:1428:static void cros_typec_remove(struct platform_device *pdev)\ndrivers/platform/chrome/cros_ec_typec.c-1429-{\ndrivers/platform/chrome/cros_ec_typec.c:1430:\tstruct cros_typec_data *typec = platform_get_drvdata(pdev);\ndrivers/platform/chrome/cros_ec_typec.c-1431-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1436-\ndrivers/platform/chrome/cros_ec_typec.c:1437:static int __maybe_unused cros_typec_suspend(struct device *dev)\ndrivers/platform/chrome/cros_ec_typec.c-1438-{\ndrivers/platform/chrome/cros_ec_typec.c:1439:\tstruct cros_typec_data *typec = dev_get_drvdata(dev);\ndrivers/platform/chrome/cros_ec_typec.c-1440-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1445-\ndrivers/platform/chrome/cros_ec_typec.c:1446:static int __maybe_unused cros_typec_resume(struct device *dev)\ndrivers/platform/chrome/cros_ec_typec.c-1447-{\ndrivers/platform/chrome/cros_ec_typec.c:1448:\tstruct cros_typec_data *typec = dev_get_drvdata(dev);\ndrivers/platform/chrome/cros_ec_typec.c-1449-\n--\ndrivers/platform/chrome/cros_ec_typec.c-1455-\ndrivers/platform/chrome/cros_ec_typec.c:1456:static const struct dev_pm_ops cros_typec_pm_ops = {\ndrivers/platform/chrome/cros_ec_typec.c:1457:\tSET_SYSTEM_SLEEP_PM_OPS(cros_typec_suspend, cros_typec_resume)\ndrivers/platform/chrome/cros_ec_typec.c-1458-};\ndrivers/platform/chrome/cros_ec_typec.c-1459-\n\n"
} |
| 33/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 44040 output: 25 thoughts: 147 Thoughts: **Analyzing the Feasibility of `cros_ec_typec` in a Virtual Environment** Okay, so I'm looking at `cros_ec_typec` – a platform driver for the ChromeOS EC Type-C controller. The real question is, can this *ever* be reached, let alone probed, within the QEMU or GCE VMs that syzkaller uses? And my instinct immediately says *no*, this is hardware specific. Does QEMU even *emulate* the ChromeOS EC? No, it doesn't. And that's because the ChromeOS EC is deeply tied to the specific hardware of Chromebooks. Alright, so direct probing is probably out of the question. Maybe, just *maybe*, there's a back door. Could `cros-ec-typec` be reached or triggered somehow through a mock driver? A clever test setup might be able to inject something. I'm going to run a quick search for "cros_ec_typec" and "cros-ec-typec" across the entire codebase. Tests, tools, anything. Gotta see if *anyone* has attempted to interact with this driver in a virtual context, or even just touched it at all. |
| 34/2 | 2026/09/20 00:18 | tool | grepper |
0mArgs:{
"Expression": "cros[-_]ec[-_]typec"
}Results: {
"Output": "Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-3----\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml:4:$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml=16=description:\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-19- control the Type C ports. This binding is compatible with both the\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml:20: cros-ec-typec and cros-ec-ucsi drivers. The cros-ec-typec driver\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-21- supports the host command interface used by the Chrome OS EC with a\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml=28=properties:\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-30- enum:\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml:31: - google,cros-ec-typec\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-32- - google,cros-ec-ucsi\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml=51=examples:\n--\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-62- typec {\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml:63: compatible = \"google,cros-ec-typec\";\nDocumentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml-64-\n--\nDocumentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml=19=properties:\n--\nDocumentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml-101- typec:\nDocumentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml:102: $ref: /schemas/chrome/google,cros-ec-typec.yaml#\nDocumentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml-103-\n--\nMAINTAINERS=6208=S:\tMaintained\nMAINTAINERS:6209:F:\tdrivers/platform/chrome/cros_ec_typec.*\nMAINTAINERS-6210-F:\tdrivers/platform/chrome/cros_typec_altmode.*\n--\narch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi=885=\t\ttypec {\narch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi:886:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi-887-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi=1642=\t\ttypec {\narch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi:1643:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi-1644-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi=1441=\t\ttypec {\narch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi:1442:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi-1443-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi=1457=\t\ttypec {\narch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi:1458:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi-1459-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi=670=\t\ttypec {\narch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi:671:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi-672-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi=570=\t\ttypec {\narch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi:571:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi-572-\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi=36=\t\ttypec {\narch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi:37:\t\t\tcompatible = \"google,cros-ec-typec\";\narch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi-38-\t\t\t#address-cells = \u003c1\u003e;\n--\ndrivers/platform/chrome/Kconfig=246=config CROS_EC_TYPEC\n--\ndrivers/platform/chrome/Kconfig-258-\t To compile this driver as a module, choose M here: the module will be\ndrivers/platform/chrome/Kconfig:259:\t called cros-ec-typec.\ndrivers/platform/chrome/Kconfig-260-\n--\ndrivers/platform/chrome/Makefile=20=cros_ec_lpcs-objs\t\t\t:= cros_ec_lpc.o cros_ec_lpc_mec.o\ndrivers/platform/chrome/Makefile:21:cros-ec-typec-objs\t\t\t:= cros_ec_typec.o cros_typec_vdm.o\ndrivers/platform/chrome/Makefile-22-ifneq ($(CONFIG_CROS_EC_TYPEC_ALTMODES),)\ndrivers/platform/chrome/Makefile:23:\tcros-ec-typec-objs\t\t+= cros_typec_altmode.o\ndrivers/platform/chrome/Makefile-24-endif\ndrivers/platform/chrome/Makefile:25:obj-$(CONFIG_CROS_EC_TYPEC)\t\t+= cros-ec-typec.o\ndrivers/platform/chrome/Makefile-26-\n--\ndrivers/platform/chrome/cros_ec_typec.c-18-\ndrivers/platform/chrome/cros_ec_typec.c:19:#include \"cros_ec_typec.h\"\ndrivers/platform/chrome/cros_ec_typec.c-20-#include \"cros_typec_vdm.h\"\n--\ndrivers/platform/chrome/cros_ec_typec.c-22-\ndrivers/platform/chrome/cros_ec_typec.c:23:#define DRV_NAME \"cros-ec-typec\"\ndrivers/platform/chrome/cros_ec_typec.c-24-\n--\ndrivers/platform/chrome/cros_ec_typec.c=1311=static void cros_typec_port_work(struct work_struct *work)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1322-\ndrivers/platform/chrome/cros_ec_typec.c:1323:static int cros_ec_typec_event(struct notifier_block *nb,\ndrivers/platform/chrome/cros_ec_typec.c-1324-\t\t\t unsigned long host_event, void *_notify)\n--\ndrivers/platform/chrome/cros_ec_typec.c=1343=static const struct of_device_id cros_typec_of_match[] = {\ndrivers/platform/chrome/cros_ec_typec.c:1344:\t{ .compatible = \"google,cros-ec-typec\", },\ndrivers/platform/chrome/cros_ec_typec.c-1345-\t{}\n--\ndrivers/platform/chrome/cros_ec_typec.c=1350=static int cros_typec_probe(struct platform_device *pdev)\n--\ndrivers/platform/chrome/cros_ec_typec.c-1415-\ndrivers/platform/chrome/cros_ec_typec.c:1416:\ttypec-\u003enb.notifier_call = cros_ec_typec_event;\ndrivers/platform/chrome/cros_ec_typec.c-1417-\tret = cros_usbpd_register_notify(\u0026typec-\u003enb);\n--\ndrivers/platform/chrome/cros_typec_altmode.c-7- */\ndrivers/platform/chrome/cros_typec_altmode.c:8:#include \"cros_ec_typec.h\"\ndrivers/platform/chrome/cros_typec_altmode.c-9-\n--\ndrivers/platform/chrome/cros_typec_altmode.c=217=static int cros_typec_thunderbolt_vdm(struct typec_altmode *alt, u32 header,\n--\ndrivers/platform/chrome/cros_typec_altmode.c-246-\t\t\t * triggers mux configuration. This is handled directly\ndrivers/platform/chrome/cros_typec_altmode.c:247:\t\t\t * by the cros_ec_typec driver so the Thunderbolt driver\ndrivers/platform/chrome/cros_typec_altmode.c-248-\t\t\t * doesn't need to be involved.\n--\ndrivers/platform/chrome/cros_typec_vdm.c-12-\ndrivers/platform/chrome/cros_typec_vdm.c:13:#include \"cros_ec_typec.h\"\ndrivers/platform/chrome/cros_typec_vdm.c-14-#include \"cros_typec_vdm.h\"\n"
} |
| 35/2 | 2026/09/20 00:18 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 47314 output: 157 thoughts: 1809 Thoughts: **Analysis of the `cros_ec_typec` Driver Patch: Not Worth Fuzzing**
Okay, let's break this down. The `cros_ec_typec` driver, which is the focus of this patch, is only instantiated in two very specific ways: either through an ACPI device with the HID "GOOG0014" (which is only present on Google Chromebook hardware's ACPI tables) or via a Device Tree entry "google,cros-ec-typec," which is found on ARM/ARM64 Chromebooks. Thinking about where these are used, and the triage instructions, it’s clear this isn't relevant for fuzzing, given that standard QEMU or GCE environments don't emulate these ChromeOS-specific hardware components.
Now, looking at the triage instructions, specifically section 2 ("WHEN TO RETURN WorthFuzzing=false"), this falls under the "Structurally unreachable hardware" category. The ChromeOS EC Type-C controller driver, specifically, needs ChromeOS Embedded Controller hardware with either the GOOG0014 ACPI entry or the "google,cros-ec-typec" Device Tree entry. These entries are only present in real ChromeOS hardware, and neither QEMU nor GCE emulates the ChromeOS EC Type-C hardware. This, by itself, is a strong indication we should not be fuzzing it.
Digging further, the patch adds a call to `cros_typec_altmodes_stop()`. Where is `cros_unregister_ports()` is called? It's only called from `cros_typec_remove()` (the driver teardown callback), and from error paths in `cros_typec_probe()` and `cros_typec_init_ports()`. Essentially, it's about cleanup. The patch's core modification, `cros_typec_altmodes_stop()`, is only invoked during driver teardown.
Can we trick it into running in QEMU? Could ACPI configfs create an ACPI device? No, syzkaller doesn't load custom ACPI tables, and even if it did, the driver requires a parent ChromeOS EC device, which also requires an LPC/I2C/SPI ChromeOS EC controller communicating with the EC firmware, which doesn’t exist in QEMU. There’s no realistic scenario where this code would be executed in a QEMU/GCE environment, especially on amd64, our target architecture.
So, to summarize concisely, the patch modifies a function (`cros_typec_altmodes_stop()`) which is called only in driver teardown or during probe errors, within the ChromeOS EC Type-C driver. This driver specifically binds to hardware-specific ACPI/Device Tree entries that exist only on physical ChromeOS devices and is unreachable on standard QEMU/GCE environments, thus making the code structurally unreachable and therefore, not worth fuzzing.
|
| 36/2 | 2026/09/20 00:19 | tool | set-results |
0mArgs:{
"EnableConfigs": [],
"FocusSymbols": [],
"Reasoning": "The patch adds cros_typec_altmodes_stop() to cros_unregister_ports() in drivers/platform/chrome/cros_ec_typec.c and cros_typec_altmode.c. This driver requires ChromeOS Embedded Controller hardware (probed via ACPI GOOG0014 or ChromeOS Devicetree), which is not present or emulated in standard QEMU/GCE virtualized environments. Additionally, the modified logic resides strictly in probe error and driver teardown cleanup paths. Consequently, the modified code is structurally unreachable for syzkaller fuzzing.",
"WorthFuzzing": false
}Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch adds cros_typec_altmodes_stop() to cros_unregister_ports() in drivers/platform/chrome/cros_ec_typec.c and cros_typec_altmode.c. This driver requires ChromeOS Embedded Controller hardware (probed via ACPI GOOG0014 or ChromeOS Devicetree), which is not present or emulated in standard QEMU/GCE virtualized environments. Additionally, the modified logic resides strictly in probe error and driver teardown cleanup paths. Consequently, the modified code is structurally unreachable for syzkaller fuzzing.",
"WorthFuzzing": false
} |
| 37/1 | 2026/09/20 00:19 | action | If |
0mArgs:{
"WorthFuzzing": false
}Results: null |
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