AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/10/01 08:48	flow	patch-triage	0m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The changes are strictly confined to the Intel wireless driver (iwlwifi), which drives vendor-specific Intel PCIe Wi-Fi adapters. Because standard virtualized environments (QEMU/GCE) lack emulation for this physical PCIe hardware, the modified driver code paths cannot be probed or executed during fuzzing, making them structurally unreachable.", "WorthFuzzing": false }
1/1	2026/10/01 08:48	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit 3f251a1e32cc7686e741e402cd3ebb5513c6fd71\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Thu Oct 1 08:48:03 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/wireless/intel/iwlwifi/Makefile b/drivers/net/wireless/intel/iwlwifi/Makefile\nindex 6746281350e0e..504381b4aac7c 100644\n--- a/drivers/net/wireless/intel/iwlwifi/Makefile\n+++ b/drivers/net/wireless/intel/iwlwifi/Makefile\n@@ -1,7 +1,6 @@\n # SPDX-License-Identifier: GPL-2.0\n # common\n obj-$(CONFIG_IWLWIFI)\t+= iwlwifi.o\n-iwlwifi-objs\t\t+= iwl-io.o\n iwlwifi-objs\t\t+= iwl-drv.o\n iwlwifi-objs\t\t+= iwl-debug.o\n iwlwifi-objs\t\t+= iwl-nvm-utils.o\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c\nindex ec94c43ba28c1..799599efdd06e 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c\n@@ -2,7 +2,7 @@\n /*****************************************************************************\n \n * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2018, 2025 Intel Corporation\n+ * Copyright (C) 2018, 2025-2026 Intel Corporation\n ****************************************************************************/\n \n #include \u003clinux/slab.h\u003e\n@@ -14,7 +14,6 @@\n \n #include \"iwl-debug.h\"\n #include \"iwl-trans.h\"\n-#include \"iwl-io.h\"\n #include \"dev.h\"\n #include \"agn.h\"\n \n@@ -1788,7 +1787,7 @@ static ssize_t iwl_dbgfs_power_save_status_read(struct file file,\n \tconst size_t bufsz = sizeof(buf);\n \tu32 pwrsave_status;\n \n-\tpwrsave_status = iwl_read32(priv-\u003etrans, CSR_GP_CNTRL) \u0026\n+\tpwrsave_status = iwl_trans_read32(priv-\u003etrans, CSR_GP_CNTRL) \u0026\n \t\t\tCSR_GP_REG_POWER_SAVE_STATUS_MSK;\n \n \tpos += scnprintf(buf + pos, bufsz - pos, \"Power Save Status: \");\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/devices.c b/drivers/net/wireless/intel/iwlwifi/dvm/devices.c\nindex 7f83f1bbdaad8..b7bd5e6deb5d1 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/devices.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/devices.c\n@@ -2,7 +2,7 @@\n /*****************************************************************************\n \n * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2019, 2025 Intel Corporation\n+ * Copyright (C) 2019, 2025-2026 Intel Corporation\n ****************************************************************************/\n \n #include \u003clinux/units.h\u003e\n@@ -10,7 +10,7 @@\n /\n * DVM device-specific data \u0026 functions\n /\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-nvm-utils.h\"\n \n@@ -45,10 +45,10 @@ static void iwl1000_set_ct_threshold(struct iwl_priv priv)\n static void iwl1000_nic_config(struct iwl_priv priv)\n {\n \t/ Setting digital SVR for 1000 card to 1.32V /\n-\t/ locking is acquired in iwl_set_bits_mask_prph() function /\n-\tiwl_set_bits_mask_prph(priv-\u003etrans, APMG_DIGITAL_SVR_REG,\n-\t\t\t\tAPMG_SVR_DIGITAL_VOLTAGE_1_32,\n-\t\t\t\t~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);\n+\t/ locking is acquired in iwl_trans_set_bits_mask_prph() function /\n+\tiwl_trans_set_bits_mask_prph(priv-\u003etrans, APMG_DIGITAL_SVR_REG,\n+\t\t\t\t APMG_SVR_DIGITAL_VOLTAGE_1_32,\n+\t\t\t\t ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);\n }\n \n /\n@@ -184,8 +184,8 @@ static void iwl2000_set_ct_threshold(struct iwl_priv priv)\n /* NIC configuration for 2000 series /\n static void iwl2000_nic_config(struct iwl_priv priv)\n {\n-\tiwl_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);\n+\tiwl_trans_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);\n }\n \n static const struct iwl_sensitivity_ranges iwl2000_sensitivity = {\n@@ -490,22 +490,22 @@ static void iwl6000_nic_config(struct iwl_priv priv)\n \t\tbreak;\n \tcase IWL_DEVICE_FAMILY_6000i:\n \t\t/ 2x2 IPA phy type /\n-\t\tiwl_write32(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t\t CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);\n+\t\tiwl_trans_write32(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t\t CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);\n \t\tbreak;\n \tcase IWL_DEVICE_FAMILY_6050:\n \t\t/ Indicate calibration version to uCode. /\n \t\tif (priv-\u003envm_data-\u003ecalib_version \u003e= 6)\n-\t\t\tiwl_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t\t\t\tCSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);\n+\t\t\tiwl_trans_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t\t\t CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);\n \t\tbreak;\n \tcase IWL_DEVICE_FAMILY_6150:\n \t\t/ Indicate calibration version to uCode. /\n \t\tif (priv-\u003envm_data-\u003ecalib_version \u003e= 6)\n-\t\t\tiwl_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t\t\t\tCSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);\n-\t\tiwl_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t\t CSR_GP_DRIVER_REG_BIT_6050_1x2);\n+\t\t\tiwl_trans_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t\t\t CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);\n+\t\tiwl_trans_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t\t CSR_GP_DRIVER_REG_BIT_6050_1x2);\n \t\tbreak;\n \tdefault:\n \t\tWARN_ON(1);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c b/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c\nindex 6de2517188f73..190e482849ac2 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c\n@@ -1,6 +1,6 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /\n- * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2025 Intel Corporation\n+ * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2026 Intel Corporation\n /\n #include \u003clinux/types.h\u003e\n #include \u003clinux/slab.h\u003e\n@@ -8,7 +8,7 @@\n \n #include \"iwl-drv.h\"\n #include \"iwl-debug.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"agn.h\"\n@@ -672,13 +672,13 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans trans)\n \n \tfor (count = 0; count \u003c IWL_EEPROM_SEM_RETRY_LIMIT; count++) {\n \t\t/* Request semaphore /\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);\n \n \t\t/ See if we got it /\n-\t\tret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t\t CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,\n-\t\t\t\t IWL_EEPROM_SEM_TIMEOUT);\n+\t\tret = iwl_trans_poll_bits(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t\t CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,\n+\t\t\t\t\t IWL_EEPROM_SEM_TIMEOUT);\n \t\tif (!ret) {\n \t\t\tIWL_DEBUG_EEPROM(trans-\u003edev,\n \t\t\t\t\t \"Acquired semaphore after %d tries.\\n\",\n@@ -692,13 +692,13 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans trans)\n \n static void iwl_eeprom_release_semaphore(struct iwl_trans trans)\n {\n-\tiwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);\n+\tiwl_trans_clear_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);\n }\n \n static int iwl_eeprom_verify_signature(struct iwl_trans trans, bool nvm_is_otp)\n {\n-\tu32 gp = iwl_read32(trans, CSR_EEPROM_GP) \u0026 CSR_EEPROM_GP_VALID_MSK;\n+\tu32 gp = iwl_trans_read32(trans, CSR_EEPROM_GP) \u0026 CSR_EEPROM_GP_VALID_MSK;\n \n \tIWL_DEBUG_EEPROM(trans-\u003edev, \"EEPROM signature=0x%08x\\n\", gp);\n \n@@ -734,10 +734,10 @@ static int iwl_eeprom_verify_signature(struct iwl_trans trans, bool nvm_is_otp)\n \n static void iwl_set_otp_access_absolute(struct iwl_trans trans)\n {\n-\tiwl_read32(trans, CSR_OTP_GP_REG);\n+\tiwl_trans_read32(trans, CSR_OTP_GP_REG);\n \n-\tiwl_clear_bit(trans, CSR_OTP_GP_REG,\n-\t\t CSR_OTP_GP_REG_OTP_ACCESS_MODE);\n+\tiwl_trans_clear_bit(trans, CSR_OTP_GP_REG,\n+\t\t\t CSR_OTP_GP_REG_OTP_ACCESS_MODE);\n }\n \n static int iwl_nvm_is_otp(struct iwl_trans trans)\n@@ -755,7 +755,7 @@ static int iwl_nvm_is_otp(struct iwl_trans trans)\n \tcase CSR_HW_REV_TYPE_5150:\n \t\treturn 0;\n \tdefault:\n-\t\totpgp = iwl_read32(trans, CSR_OTP_GP_REG);\n+\t\totpgp = iwl_trans_read32(trans, CSR_OTP_GP_REG);\n \t\tif (otpgp \u0026 CSR_OTP_GP_REG_DEVICE_SELECT)\n \t\t\treturn 1;\n \t\treturn 0;\n@@ -770,19 +770,19 @@ static int iwl_init_otp_access(struct iwl_trans trans)\n \tif (ret)\n \t\treturn ret;\n \n-\tiwl_set_bits_prph(trans, APMG_PS_CTRL_REG,\n-\t\t\t APMG_PS_CTRL_VAL_RESET_REQ);\n+\tiwl_trans_set_bits_prph(trans, APMG_PS_CTRL_REG,\n+\t\t\t\tAPMG_PS_CTRL_VAL_RESET_REQ);\n \tudelay(5);\n-\tiwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,\n-\t\t\t APMG_PS_CTRL_VAL_RESET_REQ);\n+\tiwl_trans_clear_bits_prph(trans, APMG_PS_CTRL_REG,\n+\t\t\t\t APMG_PS_CTRL_VAL_RESET_REQ);\n \n \t/\n \t * CSR auto clock gate disable bit -\n \t * this is only applicable for HW with OTP shadow RAM\n \t /\n \tif (trans-\u003emac_cfg-\u003ebase-\u003eshadow_ram_support)\n-\t\tiwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\tiwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n \n \treturn 0;\n }\n@@ -794,31 +794,31 @@ static int iwl_read_otp_word(struct iwl_trans trans, u16 addr,\n \tu32 r;\n \tu32 otpgp;\n \n-\tiwl_write32(trans, CSR_EEPROM_REG,\n-\t\t CSR_EEPROM_REG_MSK_ADDR \u0026 (addr \u003c\u003c 1));\n-\tret = iwl_poll_bits(trans, CSR_EEPROM_REG,\n-\t\t\t CSR_EEPROM_REG_READ_VALID_MSK,\n-\t\t\t IWL_EEPROM_ACCESS_TIMEOUT);\n+\tiwl_trans_write32(trans, CSR_EEPROM_REG,\n+\t\t\t CSR_EEPROM_REG_MSK_ADDR \u0026 (addr \u003c\u003c 1));\n+\tret = iwl_trans_poll_bits(trans, CSR_EEPROM_REG,\n+\t\t\t\t CSR_EEPROM_REG_READ_VALID_MSK,\n+\t\t\t\t IWL_EEPROM_ACCESS_TIMEOUT);\n \tif (ret) {\n \t\tIWL_ERR(trans, \"Time out reading OTP[%d]\\n\", addr);\n \t\treturn ret;\n \t}\n-\tr = iwl_read32(trans, CSR_EEPROM_REG);\n+\tr = iwl_trans_read32(trans, CSR_EEPROM_REG);\n \t/* check for ECC errors: /\n-\totpgp = iwl_read32(trans, CSR_OTP_GP_REG);\n+\totpgp = iwl_trans_read32(trans, CSR_OTP_GP_REG);\n \tif (otpgp \u0026 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {\n \t\t/ stop in this case /\n \t\t/ set the uncorrectable OTP ECC bit for acknowledgment /\n-\t\tiwl_set_bit(trans, CSR_OTP_GP_REG,\n-\t\t\t CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);\n+\t\tiwl_trans_set_bit(trans, CSR_OTP_GP_REG,\n+\t\t\t\t CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);\n \t\tIWL_ERR(trans, \"Uncorrectable OTP ECC error, abort OTP read\\n\");\n \t\treturn -EINVAL;\n \t}\n \tif (otpgp \u0026 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {\n \t\t/ continue in this case /\n \t\t/ set the correctable OTP ECC bit for acknowledgment /\n-\t\tiwl_set_bit(trans, CSR_OTP_GP_REG,\n-\t\t\t CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);\n+\t\tiwl_trans_set_bit(trans, CSR_OTP_GP_REG,\n+\t\t\t\t CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);\n \t\tIWL_ERR(trans, \"Correctable OTP ECC error, continue read\\n\");\n \t}\n \teeprom_data = cpu_to_le16(r \u003e\u003e 16);\n@@ -918,7 +918,7 @@ static int iwl_find_otp_image(struct iwl_trans trans,\n int iwl_read_eeprom(struct iwl_trans trans, u8 *eeprom, size_t eeprom_size)\n {\n \t__le16 e;\n-\tu32 gp = iwl_read32(trans, CSR_EEPROM_GP);\n+\tu32 gp = iwl_trans_read32(trans, CSR_EEPROM_GP);\n \tint sz;\n \tint ret;\n \tu16 addr;\n@@ -960,13 +960,13 @@ int iwl_read_eeprom(struct iwl_trans trans, u8 *eeprom, size_t eeprom_size)\n \t\t\tgoto err_unlock;\n \t\t}\n \n-\t\tiwl_write32(trans, CSR_EEPROM_GP,\n-\t\t\t iwl_read32(trans, CSR_EEPROM_GP) \u0026\n-\t\t\t ~CSR_EEPROM_GP_IF_OWNER_MSK);\n+\t\tiwl_trans_write32(trans, CSR_EEPROM_GP,\n+\t\t\t\t iwl_trans_read32(trans, CSR_EEPROM_GP) \u0026\n+\t\t\t\t ~CSR_EEPROM_GP_IF_OWNER_MSK);\n \n-\t\tiwl_set_bit(trans, CSR_OTP_GP_REG,\n-\t\t\t CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK \|\n-\t\t\t CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);\n+\t\tiwl_trans_set_bit(trans, CSR_OTP_GP_REG,\n+\t\t\t\t CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK \|\n+\t\t\t\t CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);\n \t\t/* traversing the linked list if no shadow ram supported /\n \t\tif (!trans-\u003emac_cfg-\u003ebase-\u003eshadow_ram_support) {\n \t\t\tret = iwl_find_otp_image(trans, \u0026validblockaddr);\n@@ -988,18 +988,18 @@ int iwl_read_eeprom(struct iwl_trans trans, u8 *eeprom, size_t eeprom_size)\n \t\tfor (addr = 0; addr \u003c sz; addr += sizeof(u16)) {\n \t\t\tu32 r;\n \n-\t\t\tiwl_write32(trans, CSR_EEPROM_REG,\n-\t\t\t\t CSR_EEPROM_REG_MSK_ADDR \u0026 (addr \u003c\u003c 1));\n+\t\t\tiwl_trans_write32(trans, CSR_EEPROM_REG,\n+\t\t\t\t\t CSR_EEPROM_REG_MSK_ADDR \u0026 (addr \u003c\u003c 1));\n \n-\t\t\tret = iwl_poll_bits(trans, CSR_EEPROM_REG,\n-\t\t\t\t\t CSR_EEPROM_REG_READ_VALID_MSK,\n-\t\t\t\t\t IWL_EEPROM_ACCESS_TIMEOUT);\n+\t\t\tret = iwl_trans_poll_bits(trans, CSR_EEPROM_REG,\n+\t\t\t\t\t\t CSR_EEPROM_REG_READ_VALID_MSK,\n+\t\t\t\t\t\t IWL_EEPROM_ACCESS_TIMEOUT);\n \t\t\tif (ret) {\n \t\t\t\tIWL_ERR(trans,\n \t\t\t\t\t\"Time out reading EEPROM[%d]\\n\", addr);\n \t\t\t\tgoto err_unlock;\n \t\t\t}\n-\t\t\tr = iwl_read32(trans, CSR_EEPROM_REG);\n+\t\t\tr = iwl_trans_read32(trans, CSR_EEPROM_REG);\n \t\t\te[addr / 2] = cpu_to_le16(r \u003e\u003e 16);\n \t\t}\n \t}\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/led.c b/drivers/net/wireless/intel/iwlwifi/dvm/led.c\nindex cec2ebdfd6519..17b045ddb910c 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/led.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/led.c\n@@ -2,7 +2,7 @@\n /*****************************************************************************\n \n * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2019, 2025 Intel Corporation\n+ * Copyright (C) 2019, 2025-2026 Intel Corporation\n ****************************************************************************/\n \n \n@@ -14,7 +14,6 @@\n #include \u003cnet/mac80211.h\u003e\n #include \u003clinux/etherdevice.h\u003e\n #include \u003clinux/unaligned.h\u003e\n-#include \"iwl-io.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-modparams.h\"\n #include \"dev.h\"\n@@ -49,7 +48,7 @@ static const struct ieee80211_tpt_blink iwl_blink[] = {\n / Set led register off /\n void iwlagn_led_enable(struct iwl_priv priv)\n {\n-\tiwl_write32(priv-\u003etrans, CSR_LED_REG, CSR_LED_REG_TURN_ON);\n+\tiwl_trans_write32(priv-\u003etrans, CSR_LED_REG, CSR_LED_REG_TURN_ON);\n }\n \n /\n@@ -85,10 +84,10 @@ static int iwl_send_led_cmd(struct iwl_priv priv, struct iwl_led_cmd led_cmd)\n \t};\n \tu32 reg;\n \n-\treg = iwl_read32(priv-\u003etrans, CSR_LED_REG);\n+\treg = iwl_trans_read32(priv-\u003etrans, CSR_LED_REG);\n \tif (reg != (reg \u0026 CSR_LED_BSM_CTRL_MSK))\n-\t\tiwl_write32(priv-\u003etrans, CSR_LED_REG,\n-\t\t\t reg \u0026 CSR_LED_BSM_CTRL_MSK);\n+\t\tiwl_trans_write32(priv-\u003etrans, CSR_LED_REG,\n+\t\t\t\t reg \u0026 CSR_LED_BSM_CTRL_MSK);\n \n \treturn iwl_dvm_send_cmd(priv, \u0026cmd);\n }\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/lib.c b/drivers/net/wireless/intel/iwlwifi/dvm/lib.c\nindex 2e16799818e47..37d6f2cf7efb7 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/lib.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/lib.c\n@@ -2,6 +2,7 @@\n /****************************************************************************\n \n * Copyright(c) 2008 - 2014, 2022 Intel Corporation. All rights reserved.\n+ * Copyright (C) 2026 Intel Corporation\n ***************************************************************************/\n #include \u003clinux/etherdevice.h\u003e\n #include \u003clinux/kernel.h\u003e\n@@ -9,7 +10,6 @@\n #include \u003clinux/sched.h\u003e\n #include \u003cnet/mac80211.h\u003e\n \n-#include \"iwl-io.h\"\n #include \"iwl-agn-hw.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-modparams.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c\nindex a0a26ef482a5e..e83bf615c1617 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c\n@@ -2,7 +2,7 @@\n /***************************************************************************\n \n * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.\n- * Copyright(C) 2018 - 2019, 2022 - 2025 Intel Corporation\n+ * Copyright(C) 2018 - 2019, 2022 - 2026 Intel Corporation\n \n Portions of this file are derived from the ipw3945 project, as well\n * as portions of the ieee80211 subsystem header files.\n@@ -23,7 +23,6 @@\n \n #include \u003casm/div64.h\u003e\n \n-#include \"iwl-io.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-op-mode.h\"\n #include \"iwl-modparams.h\"\n@@ -375,8 +374,8 @@ static int iwlagn_mac_suspend(struct ieee80211_hw hw,\n \t\tgoto error;\n \n \t/ let the ucode operate on its own /\n-\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n-\t\t CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);\n+\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n+\t\t\t CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);\n \n \tiwl_trans_d3_suspend(priv-\u003etrans, true);\n \n@@ -455,8 +454,8 @@ static int iwlagn_mac_resume(struct ieee80211_hw hw)\n \t\tgoto out_unlock;\n \n \t/* uCode is no longer operating by itself /\n-\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);\n+\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);\n \n \tbase = priv-\u003edevice_pointers.error_event_table;\n \tif (!iwlagn_hw_valid_rtc_data_addr(base)) {\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/main.c b/drivers/net/wireless/intel/iwlwifi/dvm/main.c\nindex 6bd5b6d84b2a9..4bf69f7a35a64 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/main.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/main.c\n@@ -2,7 +2,7 @@\n /****************************************************************************\n \n * Copyright(c) 2003 - 2014, 2018 - 2022 Intel Corporation. All rights reserved.\n- * Copyright(c) 2024-2025 Intel Corporation. All rights reserved.\n+ * Copyright(c) 2024-2026 Intel Corporation. All rights reserved.\n * Copyright(c) 2015 Intel Deutschland GmbH\n \n Portions of this file are derived from the ipw3945 project, as well\n@@ -27,8 +27,8 @@\n #include \u003casm/div64.h\u003e\n \n #include \"iwl-nvm-utils.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-trans.h\"\n+#include \"iwl-devtrace.h\"\n #include \"iwl-op-mode.h\"\n #include \"iwl-drv.h\"\n #include \"iwl-modparams.h\"\n@@ -413,7 +413,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv priv, u32 base,\n \t\treturn;\n \n \t/ Set starting address; reads will auto-increment /\n-\tiwl_write32(priv-\u003etrans, HBUS_TARG_MEM_RADDR, ptr);\n+\tiwl_trans_write32(priv-\u003etrans, HBUS_TARG_MEM_RADDR, ptr);\n \n \t/\n \t * Refuse to read more than would have fit into the log from\n@@ -429,13 +429,13 @@ static void iwl_print_cont_event_trace(struct iwl_priv priv, u32 base,\n \t place event id # at far right for easier visual parsing.\n \t /\n \tfor (i = 0; i \u003c num_events; i++) {\n-\t\tev = iwl_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n-\t\ttime = iwl_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n+\t\tev = iwl_trans_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n+\t\ttime = iwl_trans_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n \t\tif (mode == 0) {\n \t\t\ttrace_iwlwifi_dev_ucode_cont_event(\n \t\t\t\t\tpriv-\u003etrans-\u003edev, 0, time, ev);\n \t\t} else {\n-\t\t\tdata = iwl_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n+\t\t\tdata = iwl_trans_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n \t\t\ttrace_iwlwifi_dev_ucode_cont_event(\n \t\t\t\t\tpriv-\u003etrans-\u003edev, time, data, ev);\n \t\t}\n@@ -661,8 +661,8 @@ static void iwl_rf_kill_ct_config(struct iwl_priv priv)\n \tstruct iwl_ct_kill_throttling_config adv_cmd;\n \tint ret = 0;\n \n-\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n+\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n \n \tpriv-\u003ethermal_throttle.ct_kill_toggle = false;\n \n@@ -1731,13 +1731,13 @@ static int iwl_print_event_log(struct iwl_priv priv, u32 start_idx,\n \t\treturn pos;\n \n \t/ Set starting address; reads will auto-increment /\n-\tiwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);\n+\tiwl_trans_write32(trans, HBUS_TARG_MEM_RADDR, ptr);\n \n \t/ \"time\" is actually \"data\" for mode 0 (no timestamp).\n \t* place event id # at far right for easier visual parsing. /\n \tfor (i = 0; i \u003c num_events; i++) {\n-\t\tev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);\n-\t\ttime = iwl_read32(trans, HBUS_TARG_MEM_RDAT);\n+\t\tev = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);\n+\t\ttime = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);\n \t\tif (mode == 0) {\n \t\t\t/ data, ev /\n \t\t\tif (bufsz) {\n@@ -1751,7 +1751,7 @@ static int iwl_print_event_log(struct iwl_priv priv, u32 start_idx,\n \t\t\t\t\ttime, ev);\n \t\t\t}\n \t\t} else {\n-\t\t\tdata = iwl_read32(trans, HBUS_TARG_MEM_RDAT);\n+\t\t\tdata = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);\n \t\t\tif (bufsz) {\n \t\t\t\tpos += scnprintf(buf + pos, bufsz - pos,\n \t\t\t\t\t\t\"EVT_LOGT:%010u:0x%08x:%04u\\n\",\n@@ -2028,17 +2028,17 @@ static void iwl_nic_config(struct iwl_op_mode op_mode)\n \t}\n \n \t/* set CSR_HW_CONFIG_REG for uCode use /\n-\tiwl_set_bit(priv-\u003etrans, CSR_HW_IF_CONFIG_REG,\n-\t\t CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI \|\n-\t\t CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);\n+\tiwl_trans_set_bit(priv-\u003etrans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI \|\n+\t\t\t CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);\n \n \t/ W/A : NIC is stuck in a reset state after Early PCIe power off\n \t * (PCIe power is lost before PERST# is asserted),\n \t * causing ME FW to lose ownership and not being able to obtain it back.\n \t /\n-\tiwl_set_bits_mask_prph(priv-\u003etrans, APMG_PS_CTRL_REG,\n-\t\t\t APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,\n-\t\t\t ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);\n+\tiwl_trans_set_bits_mask_prph(priv-\u003etrans, APMG_PS_CTRL_REG,\n+\t\t\t\t APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,\n+\t\t\t\t ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);\n \n \tif (priv-\u003elib-\u003enic_config)\n \t\tpriv-\u003elib-\u003enic_config(priv);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/power.c b/drivers/net/wireless/intel/iwlwifi/dvm/power.c\nindex e7dbba7134f72..4e19799d15d75 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/power.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/power.c\n@@ -2,7 +2,7 @@\n /****************************************************************************\n \n * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2019, 2025 Intel Corporation\n+ * Copyright (C) 2019, 2025-2026 Intel Corporation\n \n Portions of this file are derived from the ipw3945 project, as well\n * as portions of the ieee80211 subsystem header files.\n@@ -13,7 +13,6 @@\n #include \u003clinux/module.h\u003e\n #include \u003clinux/slab.h\u003e\n #include \u003cnet/mac80211.h\u003e\n-#include \"iwl-io.h\"\n #include \"iwl-debug.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-modparams.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/rx.c b/drivers/net/wireless/intel/iwlwifi/dvm/rx.c\nindex 088302a238dec..fa2aff5bea6c0 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/rx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/rx.c\n@@ -3,7 +3,7 @@\n \n Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2015 Intel Deutschland GmbH\n- * Copyright(c) 2018, 2020-2021, 2025 Intel Corporation\n+ * Copyright(c) 2018, 2020-2021, 2025-2026 Intel Corporation\n \n Portions of this file are derived from the ipw3945 project, as well\n * as portionhelp of the ieee80211 subsystem header files.\n@@ -16,7 +16,6 @@\n #include \u003clinux/unaligned.h\u003e\n \n #include \"iwl-trans.h\"\n-#include \"iwl-io.h\"\n #include \"dev.h\"\n #include \"calib.h\"\n #include \"agn.h\"\n@@ -482,17 +481,17 @@ static void iwlagn_rx_card_state_notif(struct iwl_priv priv,\n \tif (flags \u0026 (SW_CARD_DISABLED \| HW_CARD_DISABLED \|\n \t\t CT_CARD_DISABLED)) {\n \n-\t\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n-\t\t\t CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n+\t\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n+\t\t\t\t CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n \n-\t\tiwl_write_direct32(priv-\u003etrans, HBUS_TARG_MBX_C,\n-\t\t\t\t\tHBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);\n+\t\tiwl_trans_write_direct32(priv-\u003etrans, HBUS_TARG_MBX_C,\n+\t\t\t\t\t HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);\n \n \t\tif (!(flags \u0026 RXON_CARD_DISABLED)) {\n-\t\t\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t\t\t CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n-\t\t\tiwl_write_direct32(priv-\u003etrans, HBUS_TARG_MBX_C,\n-\t\t\t\t\tHBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);\n+\t\t\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t\t\t CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n+\t\t\tiwl_trans_write_direct32(priv-\u003etrans, HBUS_TARG_MBX_C,\n+\t\t\t\t\t\t HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);\n \t\t}\n \t\tif (flags \u0026 CT_CARD_DISABLED)\n \t\t\tiwl_tt_enter_ct_kill(priv);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/tt.c b/drivers/net/wireless/intel/iwlwifi/dvm/tt.c\nindex fc9cf0531024a..a414eb7c24460 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/tt.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/tt.c\n@@ -2,7 +2,7 @@\n /****************************************************************************\n \n * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2018, 2020 Intel Corporation\n+ * Copyright (C) 2018, 2020, 2026 Intel Corporation\n \n Portions of this file are derived from the ipw3945 project, as well\n * as portions of the ieee80211 subsystem header files.\n@@ -13,7 +13,7 @@\n #include \u003clinux/module.h\u003e\n #include \u003clinux/slab.h\u003e\n #include \u003cnet/mac80211.h\u003e\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-modparams.h\"\n #include \"iwl-debug.h\"\n #include \"agn.h\"\n@@ -146,15 +146,15 @@ static void iwl_tt_check_exit_ct_kill(struct timer_list t)\n \n \tif (tt-\u003estate == IWL_TI_CT_KILL) {\n \t\tif (priv-\u003ethermal_throttle.ct_kill_toggle) {\n-\t\t\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t\t\t CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n+\t\t\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t\t\t CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n \t\t\tpriv-\u003ethermal_throttle.ct_kill_toggle = false;\n \t\t} else {\n-\t\t\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n-\t\t\t\t CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n+\t\t\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n+\t\t\t\t\t CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n \t\t\tpriv-\u003ethermal_throttle.ct_kill_toggle = true;\n \t\t}\n-\t\tiwl_read32(priv-\u003etrans, CSR_UCODE_DRV_GP1);\n+\t\tiwl_trans_read32(priv-\u003etrans, CSR_UCODE_DRV_GP1);\n \t\tif (iwl_trans_grab_nic_access(priv-\u003etrans))\n \t\t\tiwl_trans_release_nic_access(priv-\u003etrans);\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/tx.c b/drivers/net/wireless/intel/iwlwifi/dvm/tx.c\nindex 1a0167f67c7bd..8dbc52971e7bb 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/tx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/tx.c\n@@ -3,14 +3,13 @@\n \n * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.\n * Copyright (C) 2019 Intel Corporation\n- * Copyright (C) 2023, 2025 Intel Corporation\n+ * Copyright (C) 2023, 2025-2026 Intel Corporation\n ****************************************************************************/\n \n #include \u003clinux/kernel.h\u003e\n #include \u003clinux/module.h\u003e\n #include \u003clinux/sched.h\u003e\n #include \u003clinux/ieee80211.h\u003e\n-#include \"iwl-io.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-agn-hw.h\"\n #include \"dev.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c b/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c\nindex ac90191a39735..2ab1a32d774e5 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c\n@@ -3,12 +3,11 @@\n \n * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2015 Intel Deutschland GmbH\n- * Copyright (C) 2025 Intel Corporation\n+ * Copyright (C) 2025-2026 Intel Corporation\n ****************************************************************************/\n \n #include \u003clinux/kernel.h\u003e\n \n-#include \"iwl-io.h\"\n #include \"iwl-agn-hw.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-fh.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h\nindex d3bed0216df48..9f7407c4f980c 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h\n@@ -1,6 +1,6 @@\n / SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /\n /\n- * Copyright (C) 2012-2014, 2018-2025 Intel Corporation\n+ * Copyright (C) 2012-2014, 2018-2026 Intel Corporation\n * Copyright (C) 2013-2014 Intel Mobile Communications GmbH\n * Copyright (C) 2015-2017 Intel Deutschland GmbH\n /\n@@ -366,7 +366,6 @@ enum iwl_wowlan_flags {\n \tENABLE_L3_FILTERING\t= BIT(1),\n \tENABLE_NBNS_FILTERING\t= BIT(2),\n \tENABLE_DHCP_FILTERING\t= BIT(3),\n-\tENABLE_STORE_BEACON\t= BIT(4),\n \tHAS_BEACON_PROTECTION\t= BIT(5),\n };\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h\nindex 31d3336726b42..9d9eb320db7b0 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h\n@@ -1,6 +1,6 @@\n / SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /\n /\n- * Copyright (C) 2012-2014, 2018-2025 Intel Corporation\n+ * Copyright (C) 2012-2014, 2018-2026 Intel Corporation\n * Copyright (C) 2016-2017 Intel Deutschland GmbH\n /\n #ifndef __iwl_fw_api_tx_h__\n@@ -292,6 +292,9 @@ struct iwl_tx_cmd_v9 {\n @dram_info: FW internal DRAM storage\n * @rate_n_flags: rate for all Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is\n \tcleared. Combination of RATE_MCS_; format depends on version\n+ * @driver_timestamp: gp2 time, in microseconds, assigned before queueing the\n+ \tMPDU. Firmware uses it to detect frames blocked for too long.\n+ \tZero means no timestamp. Used from TX_CMD_API_S_VER_12.\n * @reserved: reserved\n * @hdr: 802.11 header\n /\n@@ -301,10 +304,12 @@ struct iwl_tx_cmd {\n \t__le32 offload_assist;\n \tstruct iwl_dram_sec_info dram_info;\n \t__le32 rate_n_flags;\n-\tu8 reserved[8];\n+\t__le32 driver_timestamp;\n+\tu8 reserved[4];\n \tstruct ieee80211_hdr hdr[];\n } __packed; / TX_CMD_API_S_VER_10,\n-\t * TX_CMD_API_S_VER_11\n+\t * TX_CMD_API_S_VER_11,\n+\t * TX_CMD_API_S_VER_12\n \t /\n \n /\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c\nindex 19b1bfd0abee4..09c798d2eba33 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c\n@@ -9,7 +9,7 @@\n #include \"runtime.h\"\n #include \"dbg.h\"\n #include \"debugfs.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"iwl-fh.h\"\n@@ -47,8 +47,8 @@ static void iwl_read_radio_regs(struct iwl_fw_runtime fwrt,\n \t\tu32 rd_cmd = RADIO_RSP_RD_CMD;\n \n \t\trd_cmd \|= i \u003c\u003c RADIO_RSP_ADDR_POS;\n-\t\tiwl_trans_write_prph(fwrt-\u003etrans, RSP_RADIO_CMD, rd_cmd);\n-\t\tpos = (u8)iwl_trans_read_prph(fwrt-\u003etrans, RSP_RADIO_RDDAT);\n+\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RSP_RADIO_CMD, rd_cmd);\n+\t\tpos = (u8)iwl_trans_read_prph_no_grab(fwrt-\u003etrans, RSP_RADIO_RDDAT);\n \n \t\tpos++;\n \t}\n@@ -81,35 +81,35 @@ static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime fwrt,\n \n \tfifo_hdr-\u003efifo_num = cpu_to_le32(fifo_num);\n \tfifo_hdr-\u003eavailable_bytes =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_RD_D_SPACE + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_RD_D_SPACE + offset));\n \tfifo_hdr-\u003ewr_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_RD_WR_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_RD_WR_PTR + offset));\n \tfifo_hdr-\u003erd_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_RD_RD_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_RD_RD_PTR + offset));\n \tfifo_hdr-\u003efence_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_RD_FENCE_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_RD_FENCE_PTR + offset));\n \tfifo_hdr-\u003efence_mode =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_SET_FENCE_MODE + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_SET_FENCE_MODE + offset));\n \n \t/* Lock fence /\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_SET_FENCE_MODE + offset, 0x1);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_SET_FENCE_MODE + offset, 0x1);\n \t/ Set fence pointer to the same place like WR pointer /\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_LD_WR2FENCE + offset, 0x1);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_LD_WR2FENCE + offset, 0x1);\n \t/ Set fence offset /\n-\tiwl_trans_write_prph(fwrt-\u003etrans,\n-\t\t\t RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);\n \n \t/ Read FIFO /\n \tfifo_len /= sizeof(u32); / Size in DWORDS /\n \tfor (i = 0; i \u003c fifo_len; i++)\n-\t\tfifo_data[i] = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t RXF_FIFO_RD_FENCE_INC +\n-\t\t\t\t\t\t offset);\n+\t\tfifo_data[i] = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t RXF_FIFO_RD_FENCE_INC +\n+\t\t\t\t\t\t\t offset);\n \tdump_data = iwl_fw_error_next_data(dump_data);\n }\n \n@@ -136,33 +136,33 @@ static void iwl_fwrt_dump_txf(struct iwl_fw_runtime fwrt,\n \n \tfifo_hdr-\u003efifo_num = cpu_to_le32(fifo_num);\n \tfifo_hdr-\u003eavailable_bytes =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_FIFO_ITEM_CNT + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_FIFO_ITEM_CNT + offset));\n \tfifo_hdr-\u003ewr_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_WR_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_WR_PTR + offset));\n \tfifo_hdr-\u003erd_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_RD_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_RD_PTR + offset));\n \tfifo_hdr-\u003efence_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_FENCE_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_FENCE_PTR + offset));\n \tfifo_hdr-\u003efence_mode =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_LOCK_FENCE + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_LOCK_FENCE + offset));\n \n \t/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR /\n-\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_READ_MODIFY_ADDR + offset,\n-\t\t\t TXF_WR_PTR + offset);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_READ_MODIFY_ADDR + offset,\n+\t\t\t\t TXF_WR_PTR + offset);\n \n \t/ Dummy-read to advance the read pointer to the head /\n-\tiwl_trans_read_prph(fwrt-\u003etrans, TXF_READ_MODIFY_DATA + offset);\n+\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans, TXF_READ_MODIFY_DATA + offset);\n \n \t/ Read FIFO /\n \tfor (i = 0; i \u003c fifo_len / sizeof(u32); i++)\n-\t\tfifo_data[i] = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t TXF_READ_MODIFY_DATA +\n-\t\t\t\t\t\t offset);\n+\t\tfifo_data[i] = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t TXF_READ_MODIFY_DATA +\n+\t\t\t\t\t\t\t offset);\n \n \tif (fwrt-\u003esanitize_ops \u0026\u0026 fwrt-\u003esanitize_ops-\u003efrob_txf)\n \t\tfwrt-\u003esanitize_ops-\u003efrob_txf(fwrt-\u003esanitize_ctx,\n@@ -217,7 +217,7 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime fwrt,\n \t\t/* Pull TXF data from LMAC1 /\n \t\tfor (i = 0; i \u003c fwrt-\u003esmem_cfg.num_txfifo_entries; i++) {\n \t\t\t/ Mark the number of TXF we're pulling now /\n-\t\t\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_LARC_NUM, i);\n+\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_LARC_NUM, i);\n \t\t\tiwl_fwrt_dump_txf(fwrt, dump_data,\n \t\t\t\t\t cfg-\u003elmac[0].txfifo_size[i], 0, i);\n \t\t}\n@@ -227,9 +227,9 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime fwrt,\n \t\t\tfor (i = 0; i \u003c fwrt-\u003esmem_cfg.num_txfifo_entries;\n \t\t\t i++) {\n \t\t\t\t/* Mark the number of TXF we're pulling now /\n-\t\t\t\tiwl_trans_write_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t TXF_LARC_NUM +\n-\t\t\t\t\t\t LMAC2_PRPH_OFFSET, i);\n+\t\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t TXF_LARC_NUM +\n+\t\t\t\t\t\t\t LMAC2_PRPH_OFFSET, i);\n \t\t\t\tiwl_fwrt_dump_txf(fwrt, dump_data,\n \t\t\t\t\t\t cfg-\u003elmac[1].txfifo_size[i],\n \t\t\t\t\t\t LMAC2_PRPH_OFFSET,\n@@ -262,40 +262,40 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime fwrt,\n \t\t\tfifo_hdr-\u003efifo_num = cpu_to_le32(i);\n \n \t\t\t/* Mark the number of TXF we're pulling now /\n-\t\t\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_CPU2_NUM, i +\n-\t\t\t\tfwrt-\u003esmem_cfg.num_txfifo_entries);\n+\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_CPU2_NUM, i +\n+\t\t\t\t\t\t fwrt-\u003esmem_cfg.num_txfifo_entries);\n \n \t\t\tfifo_hdr-\u003eavailable_bytes =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_FIFO_ITEM_CNT));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_FIFO_ITEM_CNT));\n \t\t\tfifo_hdr-\u003ewr_ptr =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_WR_PTR));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_WR_PTR));\n \t\t\tfifo_hdr-\u003erd_ptr =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_RD_PTR));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_RD_PTR));\n \t\t\tfifo_hdr-\u003efence_ptr =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_FENCE_PTR));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_FENCE_PTR));\n \t\t\tfifo_hdr-\u003efence_mode =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_LOCK_FENCE));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_LOCK_FENCE));\n \n \t\t\t/ Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR /\n-\t\t\tiwl_trans_write_prph(fwrt-\u003etrans,\n-\t\t\t\t\t TXF_CPU2_READ_MODIFY_ADDR,\n-\t\t\t\t\t TXF_CPU2_WR_PTR);\n+\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t TXF_CPU2_READ_MODIFY_ADDR,\n+\t\t\t\t\t\t TXF_CPU2_WR_PTR);\n \n \t\t\t/ Dummy-read to advance the read pointer to head /\n-\t\t\tiwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t TXF_CPU2_READ_MODIFY_DATA);\n+\t\t\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t TXF_CPU2_READ_MODIFY_DATA);\n \n \t\t\t/ Read FIFO /\n \t\t\tfifo_len /= sizeof(u32); / Size in DWORDS /\n \t\t\tfor (j = 0; j \u003c fifo_len; j++)\n \t\t\t\tfifo_data[j] =\n-\t\t\t\t\tiwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t TXF_CPU2_READ_MODIFY_DATA);\n+\t\t\t\t\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t TXF_CPU2_READ_MODIFY_DATA);\n \t\t\tdump_data = iwl_fw_error_next_data(dump_data);\n \t\t}\n \t}\n@@ -514,7 +514,7 @@ static void iwl_read_prph_block(struct iwl_trans trans, u32 start,\n \tu32 i;\n \n \tfor (i = 0; i \u003c len_bytes; i += 4)\n-\t\tdata++ = cpu_to_le32(iwl_trans_read_prph(trans, start + i));\n+\t\tdata++ = cpu_to_le32(iwl_trans_read_prph_no_grab(trans, start + i));\n }\n \n static void iwl_dump_prph(struct iwl_fw_runtime fwrt,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c\nindex 897538066b7de..1d34ad59bb71f 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c\n@@ -9,7 +9,7 @@\n #include \"runtime.h\"\n #include \"dbg.h\"\n #include \"debugfs.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"iwl-fh.h\"\n@@ -103,7 +103,7 @@ static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime fwrt,\n \trange-\u003einternal_base_addr = cpu_to_le32(addr);\n \trange-\u003erange_data_size = size;\n \tfor (i = 0; i \u003c le32_to_cpu(size); i += 4)\n-\t\tval++ = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans, addr + i));\n+\t\tval++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans, addr + i));\n \n \treturn sizeof(range) + le32_to_cpu(range-\u003erange_data_size);\n }\n@@ -159,7 +159,7 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime fwrt,\n \tindirect_rd_addr += le32_to_cpu(offset);\n \n \tdphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;\n-\tdphy_state = iwl_read_umac_prph_no_grab(fwrt-\u003etrans, dphy_addr);\n+\tdphy_state = iwl_trans_read_umac_prph_no_grab(fwrt-\u003etrans, dphy_addr);\n \n \tfor (i = 0; i \u003c le32_to_cpu(size); i += 4) {\n \t\tif (dphy_state == HBUS_TIMEOUT \|\|\n@@ -169,16 +169,16 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime fwrt,\n \t\t\tcontinue;\n \t\t}\n \n-\t\tiwl_trans_write_prph(fwrt-\u003etrans, indirect_wr_addr,\n-\t\t\t\t WMAL_INDRCT_CMD(addr + i));\n+\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, indirect_wr_addr,\n+\t\t\t\t\t WMAL_INDRCT_CMD(addr + i));\n \n \t\tif (fwrt-\u003etrans-\u003einfo.hw_rf_id != IWL_CFG_RF_TYPE_JF1 \u0026\u0026\n \t\t fwrt-\u003etrans-\u003einfo.hw_rf_id != IWL_CFG_RF_TYPE_JF2 \u0026\u0026\n \t\t fwrt-\u003etrans-\u003einfo.hw_rf_id != IWL_CFG_RF_TYPE_HR1 \u0026\u0026\n \t\t fwrt-\u003etrans-\u003einfo.hw_rf_id != IWL_CFG_RF_TYPE_HR2) {\n \t\t\tudelay(2);\n-\t\t\tprph_stts = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\tWMAL_MRSPF_STTS);\n+\t\t\tprph_stts = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\tWMAL_MRSPF_STTS);\n \n \t\t\t/ Abort dump if status is 0xA5A5A5A2 or FIFO1 empty /\n \t\t\tif (prph_stts == WMAL_TIMEOUT_VAL \|\|\n@@ -186,8 +186,8 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime fwrt,\n \t\t\t\tbreak;\n \t\t}\n \n-\t\tprph_val = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t indirect_rd_addr);\n+\t\tprph_val = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t indirect_rd_addr);\n \t\tval++ = cpu_to_le32(prph_val);\n \t}\n \n@@ -446,7 +446,7 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime fwrt,\n \trange-\u003efifo_hdr.num_of_registers = cpu_to_le32(registers_num);\n \trange-\u003erange_data_size = cpu_to_le32(iter-\u003efifo_size + registers_size);\n \n-\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_LARC_NUM + offs, iter-\u003efifo);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_LARC_NUM + offs, iter-\u003efifo);\n \n \t/\n \t read txf registers. for each register, write to the dump the\n@@ -456,8 +456,8 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime fwrt,\n \t\taddr = le32_to_cpu(reg-\u003eaddrs[i]) + offs;\n \n \t\treg_dump-\u003eaddr = cpu_to_le32(addr);\n-\t\treg_dump-\u003edata = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\t addr));\n+\t\treg_dump-\u003edata = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\t addr));\n \n \t\treg_dump++;\n \t}\n@@ -468,17 +468,17 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime fwrt,\n \t}\n \n \t/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR /\n-\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_READ_MODIFY_ADDR + offs,\n-\t\t\t TXF_WR_PTR + offs);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_READ_MODIFY_ADDR + offs,\n+\t\t\t\t TXF_WR_PTR + offs);\n \n \t/ Dummy-read to advance the read pointer to the head /\n-\tiwl_trans_read_prph(fwrt-\u003etrans, TXF_READ_MODIFY_DATA + offs);\n+\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans, TXF_READ_MODIFY_DATA + offs);\n \n \t/ Read FIFO /\n \taddr = TXF_READ_MODIFY_DATA + offs;\n \tdata = (void )reg_dump;\n \tfor (i = 0; i \u003c iter-\u003efifo_size; i += sizeof(data))\n-\t\tdata++ = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans, addr));\n+\t\tdata++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans, addr));\n \n \tif (fwrt-\u003esanitize_ops \u0026\u0026 fwrt-\u003esanitize_ops-\u003efrob_txf)\n \t\tfwrt-\u003esanitize_ops-\u003efrob_txf(fwrt-\u003esanitize_ctx,\n@@ -508,7 +508,7 @@ iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime fwrt,\n \tindirect_rd_wr_addr += le32_to_cpu(offset);\n \n \tdphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;\n-\tdphy_state = iwl_read_umac_prph_no_grab(fwrt-\u003etrans, dphy_addr);\n+\tdphy_state = iwl_trans_read_umac_prph_no_grab(fwrt-\u003etrans, dphy_addr);\n \n \tfor (i = 0; i \u003c le32_to_cpu(reg-\u003edev_addr.size); i += 4) {\n \t\tif (dphy_state == HBUS_TIMEOUT \|\|\n@@ -518,12 +518,12 @@ iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime fwrt,\n \t\t\tcontinue;\n \t\t}\n \n-\t\tiwl_trans_write_prph(fwrt-\u003etrans, indirect_rd_wr_addr,\n-\t\t\t\t addr + i);\n+\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, indirect_rd_wr_addr,\n+\t\t\t\t\t addr + i);\n \t\t/ wait a bit for value to be ready in register /\n \t\tudelay(1);\n-\t\tprph_val = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t indirect_rd_wr_addr);\n+\t\tprph_val = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t indirect_rd_wr_addr);\n \t\tval++ = cpu_to_le32((prph_val \u0026 DPHYIP_INDIRECT_RD_MSK) \u003e\u003e\n \t\t\t\t DPHYIP_INDIRECT_RD_SHIFT);\n \t}\n@@ -586,13 +586,13 @@ static void iwl_ini_get_rxf_data(struct iwl_fw_runtime fwrt,\n \t\tswitch (fifo_idx) {\n \t\tcase 0:\n \t\t\tdata-\u003esize = fwrt-\u003esmem_cfg.rxfifo2_size;\n-\t\t\tdata-\u003eoffset = iwl_umac_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t RXF_DIFF_FROM_PREV);\n+\t\t\tdata-\u003eoffset = iwl_trans_umac_prph(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t RXF_DIFF_FROM_PREV);\n \t\t\tbreak;\n \t\tcase 1:\n \t\t\tdata-\u003esize = fwrt-\u003esmem_cfg.rxfifo2_control_size;\n-\t\t\tdata-\u003eoffset = iwl_umac_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t RXF2C_DIFF_FROM_PREV);\n+\t\t\tdata-\u003eoffset = iwl_trans_umac_prph(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t RXF2C_DIFF_FROM_PREV);\n \t\t\tbreak;\n \t\t}\n \t}\n@@ -628,8 +628,8 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime fwrt,\n \t\taddr = le32_to_cpu(reg-\u003eaddrs[i]) + offs;\n \n \t\treg_dump-\u003eaddr = cpu_to_le32(addr);\n-\t\treg_dump-\u003edata = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\t addr));\n+\t\treg_dump-\u003edata = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\t addr));\n \n \t\treg_dump++;\n \t}\n@@ -642,17 +642,17 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime fwrt,\n \toffs = rxf_data.offset;\n \n \t/ Lock fence /\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_SET_FENCE_MODE + offs, 0x1);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_SET_FENCE_MODE + offs, 0x1);\n \t/ Set fence pointer to the same place like WR pointer /\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_LD_WR2FENCE + offs, 0x1);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_LD_WR2FENCE + offs, 0x1);\n \t/ Set fence offset /\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_LD_FENCE_OFFSET_ADDR + offs, 0x0);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_LD_FENCE_OFFSET_ADDR + offs, 0x0);\n \n \t/ Read FIFO /\n \taddr = RXF_FIFO_RD_FENCE_INC + offs;\n \tdata = (void )reg_dump;\n \tfor (i = 0; i \u003c rxf_data.size; i += sizeof(data))\n-\t\tdata++ = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans, addr));\n+\t\tdata++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans, addr));\n \n out:\n \treturn sizeof(range) + le32_to_cpu(range-\u003erange_data_size);\n@@ -712,10 +712,10 @@ iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime fwrt,\n \trange-\u003erange_data_size = reg-\u003edev_addr.size;\n \tfor (i = 0; i \u003c (le32_to_cpu(reg-\u003edev_addr.size) / 4); i++) {\n \t\tprph_data =\n-\t\t\tiwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t (i % 2) ?\n-\t\t\t\t\t\tDBGI_SRAM_TARGET_ACCESS_RDATA_MSB :\n-\t\t\t\t\t\tDBGI_SRAM_TARGET_ACCESS_RDATA_LSB);\n+\t\t\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t (i % 2) ?\n+\t\t\t\t\t\t DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :\n+\t\t\t\t\t\t DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);\n \t\tif (iwl_trans_is_hw_error_value(prph_data))\n \t\t\treturn -EBUSY;\n \t\tval++ = cpu_to_le32(prph_data);\n@@ -812,7 +812,7 @@ static __le32 iwl_get_mon_reg(struct iwl_fw_runtime fwrt, u32 alloc_id,\n \tif (!reg_info \|\| !reg_info-\u003eaddr \|\| !reg_info-\u003emask)\n \t\treturn 0;\n \n-\tval = iwl_trans_read_prph(fwrt-\u003etrans, reg_info-\u003eaddr + offs);\n+\tval = iwl_trans_read_prph_no_grab(fwrt-\u003etrans, reg_info-\u003eaddr + offs);\n \n \treturn cpu_to_le32(mask_apply_and_normalize(val, reg_info-\u003emask));\n }\n@@ -1820,14 +1820,14 @@ static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime fwrt,\n \t\t\tcpu_to_le32(IWL_FW_INI_APPLY_POLICY_SPLIT_DUMP_RESET)) {\n \t\tsize += iwl_dump_ini_dump_entries(fwrt, list,\n \t\t\t\t\t\t IWL_INI_DUMP_EARLY_REGIONS);\n-\t\tiwl_trans_pcie_fw_reset_handshake(fwrt-\u003etrans);\n+\t\tiwl_trans_fw_reset_handshake(fwrt-\u003etrans);\n \t\tsize += iwl_dump_ini_dump_entries(fwrt, list,\n \t\t\t\t\t\t IWL_INI_DUMP_LATE_REGIONS);\n \t} else {\n \t\tif (fw_has_capa(\u0026fwrt-\u003efw-\u003eucode_capa,\n \t\t\t\tIWL_UCODE_TLV_CAPA_RESET_DURING_ASSERT) \u0026\u0026\n \t\t iwl_dump_due_to_error(tp_id))\n-\t\t\tiwl_trans_pcie_fw_reset_handshake(fwrt-\u003etrans);\n+\t\t\tiwl_trans_fw_reset_handshake(fwrt-\u003etrans);\n \t\tsize += iwl_dump_ini_dump_entries(fwrt, list,\n \t\t\t\t\t\t IWL_INI_DUMP_ALL_REGIONS);\n \t}\n@@ -2381,21 +2381,21 @@ static void iwl_fw_dbg_stop_recording(struct iwl_trans trans,\n \t\t\t\t struct iwl_fw_dbg_params params)\n {\n \tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_7000) {\n-\t\tiwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);\n+\t\tiwl_trans_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);\n \t\treturn;\n \t}\n \n \tif (params) {\n-\t\tparams-\u003ein_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);\n-\t\tparams-\u003eout_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);\n+\t\tparams-\u003ein_sample = iwl_trans_read_umac_prph(trans, DBGC_IN_SAMPLE);\n+\t\tparams-\u003eout_ctrl = iwl_trans_read_umac_prph(trans, DBGC_OUT_CTRL);\n \t}\n \n-\tiwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);\n+\tiwl_trans_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);\n \t/* wait for the DBGC to finish writing the internal buffer to DRAM to\n \t * avoid halting the HW while writing\n \t /\n \tusleep_range(700, 1000);\n-\tiwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);\n+\tiwl_trans_write_umac_prph(trans, DBGC_OUT_CTRL, 0);\n }\n \n static int iwl_fw_dbg_restart_recording(struct iwl_trans trans,\n@@ -2405,12 +2405,12 @@ static int iwl_fw_dbg_restart_recording(struct iwl_trans trans,\n \t\treturn -EIO;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_7000) {\n-\t\tiwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);\n-\t\tiwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);\n-\t\tiwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);\n+\t\tiwl_trans_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);\n+\t\tiwl_trans_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);\n+\t\tiwl_trans_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);\n \t} else {\n-\t\tiwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params-\u003ein_sample);\n-\t\tiwl_write_umac_prph(trans, DBGC_OUT_CTRL, params-\u003eout_ctrl);\n+\t\tiwl_trans_write_umac_prph(trans, DBGC_IN_SAMPLE, params-\u003ein_sample);\n+\t\tiwl_trans_write_umac_prph(trans, DBGC_OUT_CTRL, params-\u003eout_ctrl);\n \t}\n \n \treturn 0;\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h\nindex fc962a3205833..70134d8f03c4d 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h\n@@ -10,7 +10,7 @@\n #include \u003cnet/cfg80211.h\u003e\n #include \"runtime.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"file.h\"\n #include \"error-dump.h\"\n #include \"api/commands.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/dump.c b/drivers/net/wireless/intel/iwlwifi/fw/dump.c\nindex bbbf3669a555d..b76abc77f4959 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/dump.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/dump.c\n@@ -9,7 +9,7 @@\n #include \"runtime.h\"\n #include \"dbg.h\"\n #include \"debugfs.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"pnvm.h\"\n@@ -309,7 +309,7 @@ static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime fwrt)\n \t\treturn;\n \t}\n \n-\terror = iwl_read_umac_prph(trans, error);\n+\terror = iwl_trans_read_umac_prph(trans, error);\n \n \tIWL_ERR(trans, \"IML/ROM dump:\\n\");\n \n@@ -318,11 +318,11 @@ static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime fwrt)\n \n \tIWL_ERR(fwrt, \"0x%08X \| IML/ROM error/state\\n\", error);\n \tIWL_ERR(fwrt, \"0x%08X \| IML/ROM data1\\n\",\n-\t\tiwl_read_umac_prph(trans, data1));\n+\t\tiwl_trans_read_umac_prph(trans, data1));\n \n \tif (fwrt-\u003etrans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_22000)\n \t\tIWL_ERR(fwrt, \"0x%08X \| IML/ROM WFPM_AUTH_KEY_0\\n\",\n-\t\t\tiwl_read_umac_prph(trans, SB_MODIFY_CFG_FLAG));\n+\t\t\tiwl_trans_read_umac_prph(trans, SB_MODIFY_CFG_FLAG));\n }\n \n #define FSEQ_REG(x) { .addr = (x), .str = #x, }\n@@ -360,7 +360,7 @@ static void iwl_fwrt_dump_fseq_regs(struct iwl_fw_runtime fwrt)\n \n \tfor (i = 0; i \u003c ARRAY_SIZE(fseq_regs); i++)\n \t\tIWL_ERR(fwrt, \"0x%08X \| %s\\n\",\n-\t\t\tiwl_read_prph_no_grab(trans, fseq_regs[i].addr),\n+\t\t\tiwl_trans_read_prph_no_grab(trans, fseq_regs[i].addr),\n \t\t\tfseq_regs[i].str);\n \n \tiwl_trans_release_nic_access(trans);\n@@ -398,13 +398,13 @@ void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime fwrt)\n \t\t count++, pc_data++)\n \t\t\tIWL_ERR(fwrt, \"%s: 0x%x\\n\",\n \t\t\t\tpc_data-\u003epc_name,\n-\t\t\t\tiwl_read_prph_no_grab(fwrt-\u003etrans,\n-\t\t\t\t\t\t pc_data-\u003epc_address));\n+\t\t\t\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t pc_data-\u003epc_address));\n \t\tiwl_trans_release_nic_access(fwrt-\u003etrans);\n \t}\n \n \tif (fwrt-\u003etrans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tu32 scratch = iwl_read32(fwrt-\u003etrans, CSR_FUNC_SCRATCH);\n+\t\tu32 scratch = iwl_trans_read32(fwrt-\u003etrans, CSR_FUNC_SCRATCH);\n \n \t\tIWL_ERR(fwrt, \"Function Scratch status:\\n\");\n \t\tIWL_ERR(fwrt, \"0x%08X \| Func Scratch\\n\", scratch);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c\nindex 545a213df71d2..ccd190ab8a552 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c\n@@ -6,7 +6,7 @@\n #include \"iwl-drv.h\"\n #include \"pnvm.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"fw/api/commands.h\"\n #include \"fw/api/nvm-reg.h\"\n #include \"fw/api/alive.h\"\n@@ -485,8 +485,8 @@ int iwl_pnvm_load(struct iwl_trans trans,\n \t\t\t\t iwl_pnvm_complete_fn, trans);\n \n \t/* kick the doorbell /\n-\tiwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n-\t\t\t UREG_DOORBELL_TO_ISR6_PNVM);\n+\tiwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n+\t\t\t\t UREG_DOORBELL_TO_ISR6_PNVM);\n \n \treturn iwl_wait_notification(notif_wait, \u0026pnvm_wait,\n \t\t\t\t MVM_UCODE_PNVM_TIMEOUT);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c\nindex dffd5e68f41da..89a0f722cad94 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c\n@@ -6,7 +6,7 @@\n #include \"iwl-drv.h\"\n #include \"pnvm.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n \n #include \"fw/uefi.h\"\n #include \"fw/api/alive.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h\nindex d2fa80a3dd040..11f2b31f6df7e 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h\n@@ -14,9 +14,9 @@\n low power states due to driver-invoked device resets\n * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.\n \n- Use iwl_write32() and iwl_read32() family to access these registers;\n+ * Use iwl_trans_write32() and iwl_trans_read32() family to access these registers;\n * these provide simple PCI bus access, without waking up the MAC.\n- * Do not use iwl_write_direct32() family for these registers;\n+ * Do not use iwl_trans_write_direct32() family for these registers;\n * no need to \"grab nic access\" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.\n * The MAC (uCode processor, etc.) does not need to be powered up for accessing\n * the CSR registers.\n@@ -36,7 +36,7 @@\n #define CSR_GP_CNTRL (CSR_BASE+0x024)\n #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg /\n \n-/ 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! /\n+/ 2nd byte of CSR_INT_COALESCING, not accessible via iwl_trans_write32()! /\n #define CSR_INT_PERIODIC_REG\t(CSR_BASE+0x005)\n \n /\n@@ -474,7 +474,7 @@ enum {\n * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and\n * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.\n \n- Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW\n+ * Use iwl_trans_write32()/iwl_trans_read32() family to access these registers. The MAC HW\n * need not be powered up so no \"grab inc access\" is required.\n /\n \n@@ -501,12 +501,13 @@ enum {\n to indirectly access device's internal memory or registers that\n * may be powered-down.\n \n- Use iwl_write_direct32()/iwl_read_direct32() family for these registers;\n+ * Use iwl_trans_write_direct32() family for writing to these registers;\n+ * A read operation doesn't exist, can be added if needed.\n * host must \"grab nic access\" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ\n * to make sure the MAC (uCode processor, etc.) is powered up for accessing\n * internal resources.\n \n- Do not use iwl_write32()/iwl_read32() family to access these registers;\n+ * Do not use iwl_trans_write32()/iwl_trans_read32() family to access these registers;\n * these provide only simple PCI bus access, without waking up the MAC.\n /\n #define HBUS_BASE\t(0x400)\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c\nindex 4372a171172b0..cc6044222b5cf 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c\n@@ -912,7 +912,7 @@ static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime fwrt,\n \t\t\tfor (count = 0; count \u003c len; count++) {\n \t\t\t\taddress = le32_to_cpu(config_list-\u003eaddr_val[count].address);\n \t\t\t\tvalue = le32_to_cpu(config_list-\u003eaddr_val[count].value);\n-\t\t\t\tiwl_trans_write_prph(fwrt-\u003etrans, address + offset, value);\n+\t\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, address + offset, value);\n \t\t\t}\n \t\t\tiwl_trans_release_nic_access(fwrt-\u003etrans);\n \t\tbreak;\n@@ -931,7 +931,7 @@ static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime fwrt,\n \t\t\tfor (count = 0; count \u003c len; count++) {\n \t\t\t\taddress = le32_to_cpu(config_list-\u003eaddr_val[count].address);\n \t\t\t\tvalue = le32_to_cpu(config_list-\u003eaddr_val[count].value);\n-\t\t\t\tiwl_write32(fwrt-\u003etrans, address + offset, value);\n+\t\t\t\tiwl_trans_write32(fwrt-\u003etrans, address + offset, value);\n \t\t\t\tIWL_DEBUG_FW(fwrt, \"WRT: CSR: count %u, add: %u val: %u\\n\",\n \t\t\t\t\t count, address, value);\n \t\t\t}\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h b/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h\nindex 0af9d8362c5b8..a0cc401198908 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h\n@@ -3,6 +3,7 @@\n \n * Copyright(c) 2009 - 2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2016-2017 Intel Deutschland GmbH\n+ * Copyright (C) 2026 Intel Corporation\n ****************************************************************************/\n \n #if !defined(__IWLWIFI_DEVICE_TRACE_IO) \|\| defined(TRACE_HEADER_MULTI_READ)\n@@ -65,23 +66,6 @@ TRACE_EVENT(iwlwifi_dev_iowrite32,\n \t\t __get_str(dev), __entry-\u003eoffs, __entry-\u003eval)\n );\n \n-TRACE_EVENT(iwlwifi_dev_iowrite64,\n-\tTP_PROTO(const struct device dev, u64 offs, u64 val),\n-\tTP_ARGS(dev, offs, val),\n-\tTP_STRUCT__entry(\n-\t\tDEV_ENTRY\n-\t\t__field(u64, offs)\n-\t\t__field(u64, val)\n-\t),\n-\tTP_fast_assign(\n-\t\tDEV_ASSIGN;\n-\t\t__entry-\u003eoffs = offs;\n-\t\t__entry-\u003eval = val;\n-\t),\n-\tTP_printk(\"[%s] write io[%llu] = %llu)\",\n-\t\t __get_str(dev), __entry-\u003eoffs, __entry-\u003eval)\n-);\n-\n TRACE_EVENT(iwlwifi_dev_iowrite_prph32,\n \tTP_PROTO(const struct device dev, u32 offs, u32 val),\n \tTP_ARGS(dev, offs, val),\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.c b/drivers/net/wireless/intel/iwlwifi/iwl-io.c\ndeleted file mode 100644\nindex cc6bf4ea5055d..0000000000000\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-io.c\n+++ /dev/null\n@@ -1,217 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n-/\n- * Copyright (C) 2003-2014, 2018-2022, 2024-2026 Intel Corporation\n- * Copyright (C) 2015-2016 Intel Deutschland GmbH\n- /\n-#include \u003clinux/device.h\u003e\n-#include \u003clinux/export.h\u003e\n-\n-#include \"iwl-drv.h\"\n-#include \"iwl-io.h\"\n-#include \"iwl-csr.h\"\n-#include \"iwl-debug.h\"\n-\n-void iwl_write8(struct iwl_trans trans, u32 ofs, u8 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite8(trans-\u003edev, ofs, val);\n-\tiwl_trans_write8(trans, ofs, val);\n-}\n-IWL_EXPORT_SYMBOL(iwl_write8);\n-\n-void iwl_write32(struct iwl_trans trans, u32 ofs, u32 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite32(trans-\u003edev, ofs, val);\n-\tiwl_trans_write32(trans, ofs, val);\n-}\n-IWL_EXPORT_SYMBOL(iwl_write32);\n-\n-void iwl_write64(struct iwl_trans trans, u64 ofs, u64 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite64(trans-\u003edev, ofs, val);\n-\tiwl_trans_write32(trans, ofs, lower_32_bits(val));\n-\tiwl_trans_write32(trans, ofs + 4, upper_32_bits(val));\n-}\n-IWL_EXPORT_SYMBOL(iwl_write64);\n-\n-u32 iwl_read32(struct iwl_trans trans, u32 ofs)\n-{\n-\tu32 val = iwl_trans_read32(trans, ofs);\n-\n-\ttrace_iwlwifi_dev_ioread32(trans-\u003edev, ofs, val);\n-\treturn val;\n-}\n-IWL_EXPORT_SYMBOL(iwl_read32);\n-\n-#define IWL_POLL_INTERVAL 10\t/ microseconds /\n-\n-int iwl_poll_bits_mask(struct iwl_trans trans, u32 addr,\n-\t\t u32 bits, u32 mask, int timeout)\n-{\n-\tint t = 0;\n-\n-\tdo {\n-\t\tif ((iwl_read32(trans, addr) \u0026 mask) == (bits \u0026 mask))\n-\t\t\treturn 0;\n-\t\tudelay(IWL_POLL_INTERVAL);\n-\t\tt += IWL_POLL_INTERVAL;\n-\t} while (t \u003c timeout);\n-\n-\treturn -ETIMEDOUT;\n-}\n-IWL_EXPORT_SYMBOL(iwl_poll_bits_mask);\n-\n-u32 iwl_read_direct32(struct iwl_trans trans, u32 reg)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tu32 value = iwl_read32(trans, reg);\n-\n-\t\tiwl_trans_release_nic_access(trans);\n-\t\treturn value;\n-\t}\n-\n-\t/ return as if we have a HW timeout/failure /\n-\treturn 0x5a5a5a5a;\n-}\n-\n-void iwl_write_direct32(struct iwl_trans trans, u32 reg, u32 value)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write32(trans, reg, value);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_write_direct32);\n-\n-void iwl_write_direct64(struct iwl_trans trans, u64 reg, u64 value)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write64(trans, reg, value);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-\n-int iwl_poll_direct_bit(struct iwl_trans trans, u32 addr, u32 mask,\n-\t\t\tint timeout)\n-{\n-\tint t = 0;\n-\n-\tdo {\n-\t\tif ((iwl_read_direct32(trans, addr) \u0026 mask) == mask)\n-\t\t\treturn t;\n-\t\tudelay(IWL_POLL_INTERVAL);\n-\t\tt += IWL_POLL_INTERVAL;\n-\t} while (t \u003c timeout);\n-\n-\treturn -ETIMEDOUT;\n-}\n-\n-u32 iwl_read_prph_no_grab(struct iwl_trans trans, u32 ofs)\n-{\n-\tu32 val = iwl_trans_read_prph(trans, ofs);\n-\ttrace_iwlwifi_dev_ioread_prph32(trans-\u003edev, ofs, val);\n-\treturn val;\n-}\n-\n-void iwl_write_prph_no_grab(struct iwl_trans trans, u32 ofs, u32 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite_prph32(trans-\u003edev, ofs, val);\n-\tiwl_trans_write_prph(trans, ofs, val);\n-}\n-\n-void iwl_write_prph64_no_grab(struct iwl_trans trans, u64 ofs, u64 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite_prph64(trans-\u003edev, ofs, val);\n-\tiwl_write_prph_no_grab(trans, ofs, val \u0026 0xffffffff);\n-\tiwl_write_prph_no_grab(trans, ofs + 4, val \u003e\u003e 32);\n-}\n-\n-u32 iwl_read_prph(struct iwl_trans trans, u32 ofs)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tu32 val = iwl_read_prph_no_grab(trans, ofs);\n-\n-\t\tiwl_trans_release_nic_access(trans);\n-\n-\t\treturn val;\n-\t}\n-\n-\t/* return as if we have a HW timeout/failure /\n-\treturn 0x5a5a5a5a;\n-}\n-IWL_EXPORT_SYMBOL(iwl_read_prph);\n-\n-void iwl_write_prph_delay(struct iwl_trans trans, u32 ofs, u32 val, u32 delay_ms)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tmdelay(delay_ms);\n-\t\tiwl_write_prph_no_grab(trans, ofs, val);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_write_prph_delay);\n-\n-int iwl_poll_prph_bit(struct iwl_trans trans, u32 addr,\n-\t\t u32 bits, u32 mask, int timeout)\n-{\n-\tint t = 0;\n-\n-\tdo {\n-\t\tif ((iwl_read_prph(trans, addr) \u0026 mask) == (bits \u0026 mask))\n-\t\t\treturn 0;\n-\t\tudelay(IWL_POLL_INTERVAL);\n-\t\tt += IWL_POLL_INTERVAL;\n-\t} while (t \u003c timeout);\n-\n-\treturn -ETIMEDOUT;\n-}\n-\n-int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans trans, u32 addr,\n-\t\t\t\t u32 bits, u32 mask, int timeout)\n-{\n-\tint t = 0;\n-\n-\tdo {\n-\t\tif ((iwl_read_umac_prph_no_grab(trans, addr) \u0026 mask) ==\n-\t\t (bits \u0026 mask))\n-\t\t\treturn 0;\n-\t\tudelay(IWL_POLL_INTERVAL);\n-\t\tt += IWL_POLL_INTERVAL;\n-\t} while (t \u003c timeout);\n-\n-\treturn -ETIMEDOUT;\n-}\n-\n-void iwl_set_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write_prph_no_grab(trans, ofs,\n-\t\t\t\t iwl_read_prph_no_grab(trans, ofs) \|\n-\t\t\t\t mask);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_set_bits_prph);\n-\n-void iwl_set_bits_mask_prph(struct iwl_trans trans, u32 ofs,\n-\t\t\t u32 bits, u32 mask)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write_prph_no_grab(trans, ofs,\n-\t\t\t\t (iwl_read_prph_no_grab(trans, ofs) \u0026\n-\t\t\t\t\tmask) \| bits);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);\n-\n-void iwl_clear_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask)\n-{\n-\tu32 val;\n-\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tval = iwl_read_prph_no_grab(trans, ofs);\n-\t\tiwl_write_prph_no_grab(trans, ofs, (val \u0026 ~mask));\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.h b/drivers/net/wireless/intel/iwlwifi/iwl-io.h\ndeleted file mode 100644\nindex e4a9f2ba0de93..0000000000000\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-io.h\n+++ /dev/null\n@@ -1,103 +0,0 @@\n-/ SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /\n-/\n- * Copyright (C) 2018-2021, 2025-2026 Intel Corporation\n- /\n-#ifndef __iwl_io_h__\n-#define __iwl_io_h__\n-\n-#include \"iwl-devtrace.h\"\n-#include \"iwl-trans.h\"\n-\n-void iwl_write8(struct iwl_trans trans, u32 ofs, u8 val);\n-void iwl_write32(struct iwl_trans trans, u32 ofs, u32 val);\n-void iwl_write64(struct iwl_trans trans, u64 ofs, u64 val);\n-u32 iwl_read32(struct iwl_trans trans, u32 ofs);\n-\n-static inline void iwl_set_bit(struct iwl_trans trans, u32 reg, u32 mask)\n-{\n-\tiwl_trans_set_bits_mask(trans, reg, mask, mask);\n-}\n-\n-static inline void iwl_clear_bit(struct iwl_trans trans, u32 reg, u32 mask)\n-{\n-\tiwl_trans_set_bits_mask(trans, reg, mask, 0);\n-}\n-\n-int iwl_poll_bits_mask(struct iwl_trans trans, u32 addr,\n-\t\t u32 bits, u32 mask, int timeout);\n-static inline int iwl_poll_bits(struct iwl_trans trans, u32 addr, u32 bits,\n-\t\t\t\tint timeout)\n-{\n-\treturn iwl_poll_bits_mask(trans, addr, bits, bits, timeout);\n-}\n-int iwl_poll_direct_bit(struct iwl_trans trans, u32 addr, u32 mask,\n-\t\t\tint timeout);\n-\n-u32 iwl_read_direct32(struct iwl_trans trans, u32 reg);\n-void iwl_write_direct32(struct iwl_trans trans, u32 reg, u32 value);\n-void iwl_write_direct64(struct iwl_trans trans, u64 reg, u64 value);\n-\n-\n-u32 iwl_read_prph_no_grab(struct iwl_trans trans, u32 ofs);\n-u32 iwl_read_prph(struct iwl_trans trans, u32 ofs);\n-void iwl_write_prph_no_grab(struct iwl_trans trans, u32 ofs, u32 val);\n-void iwl_write_prph64_no_grab(struct iwl_trans trans, u64 ofs, u64 val);\n-void iwl_write_prph_delay(struct iwl_trans trans, u32 ofs,\n-\t\t\t u32 val, u32 delay_ms);\n-static inline void iwl_write_prph(struct iwl_trans trans, u32 ofs, u32 val)\n-{\n-\tiwl_write_prph_delay(trans, ofs, val, 0);\n-}\n-\n-int iwl_poll_prph_bit(struct iwl_trans trans, u32 addr,\n-\t\t u32 bits, u32 mask, int timeout);\n-int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans trans, u32 addr,\n-\t\t\t\t u32 bits, u32 mask, int timeout);\n-void iwl_set_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask);\n-void iwl_set_bits_mask_prph(struct iwl_trans trans, u32 ofs,\n-\t\t\t u32 bits, u32 mask);\n-void iwl_clear_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask);\n-\n-/\n- UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from\n- * device family AX200. So peripheries used in families above and below AX200\n- * should go through iwl_..._umac_..._prph.\n- /\n-static inline u32 iwl_umac_prph(struct iwl_trans trans, u32 ofs)\n-{\n-\treturn ofs + trans-\u003emac_cfg-\u003eumac_prph_offset;\n-}\n-\n-static inline u32 iwl_read_umac_prph_no_grab(struct iwl_trans trans, u32 ofs)\n-{\n-\treturn iwl_read_prph_no_grab(trans, ofs +\n-\t\t\t\t trans-\u003emac_cfg-\u003eumac_prph_offset);\n-}\n-\n-static inline u32 iwl_read_umac_prph(struct iwl_trans trans, u32 ofs)\n-{\n-\treturn iwl_read_prph(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset);\n-}\n-\n-static inline void iwl_write_umac_prph_no_grab(struct iwl_trans trans, u32 ofs,\n-\t\t\t\t\t u32 val)\n-{\n-\tiwl_write_prph_no_grab(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset,\n-\t\t\t val);\n-}\n-\n-static inline void iwl_write_umac_prph(struct iwl_trans trans, u32 ofs,\n-\t\t\t\t u32 val)\n-{\n-\tiwl_write_prph(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset, val);\n-}\n-\n-static inline int iwl_poll_umac_prph_bit(struct iwl_trans trans, u32 addr,\n-\t\t\t\t\t u32 bits, u32 mask, int timeout)\n-{\n-\treturn iwl_poll_prph_bit(trans, addr +\n-\t\t\t\t trans-\u003emac_cfg-\u003eumac_prph_offset,\n-\t\t\t\t bits, mask, timeout);\n-}\n-\n-#endif\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c\nindex 413dd55115f8f..ed2b094c1ad78 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c\n@@ -16,7 +16,7 @@\n #include \"iwl-modparams.h\"\n #include \"iwl-nvm-parse.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-csr.h\"\n #include \"fw/api/nvm-reg.h\"\n #include \"fw/api/commands.h\"\n@@ -1312,10 +1312,10 @@ static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 dest)\n static void iwl_set_hw_address_from_csr(struct iwl_trans trans,\n \t\t\t\t\tstruct iwl_nvm_data data)\n {\n-\t__le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,\n-\t\t\t\t\t\t CSR_MAC_ADDR0_STRAP(trans)));\n-\t__le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,\n-\t\t\t\t\t\t CSR_MAC_ADDR1_STRAP(trans)));\n+\t__le32 mac_addr0 = cpu_to_le32(iwl_trans_read32(trans,\n+\t\t\t\t\t\t\tCSR_MAC_ADDR0_STRAP(trans)));\n+\t__le32 mac_addr1 = cpu_to_le32(iwl_trans_read32(trans,\n+\t\t\t\t\t\t\tCSR_MAC_ADDR1_STRAP(trans)));\n \n \tiwl_flip_hw_address(mac_addr0, mac_addr1, data-\u003ehw_addr);\n \t/\n@@ -1325,8 +1325,8 @@ static void iwl_set_hw_address_from_csr(struct iwl_trans trans,\n \tif (is_valid_ether_addr(data-\u003ehw_addr))\n \t\treturn;\n \n-\tmac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));\n-\tmac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));\n+\tmac_addr0 = cpu_to_le32(iwl_trans_read32(trans, CSR_MAC_ADDR0_OTP(trans)));\n+\tmac_addr1 = cpu_to_le32(iwl_trans_read32(trans, CSR_MAC_ADDR1_OTP(trans)));\n \n \tiwl_flip_hw_address(mac_addr0, mac_addr1, data-\u003ehw_addr);\n }\n@@ -1367,10 +1367,10 @@ static void iwl_set_hw_address_family_8000(struct iwl_trans trans,\n \n \tif (nvm_hw) {\n \t\t/ read the mac address from WFMP registers /\n-\t\t__le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,\n-\t\t\t\t\t\tWFMP_MAC_ADDR_0));\n-\t\t__le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,\n-\t\t\t\t\t\tWFMP_MAC_ADDR_1));\n+\t\t__le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph_no_grab(trans,\n+\t\t\t\t\t\t\t\t\t WFMP_MAC_ADDR_0));\n+\t\t__le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph_no_grab(trans,\n+\t\t\t\t\t\t\t\t\t WFMP_MAC_ADDR_1));\n \n \t\tiwl_flip_hw_address(mac_addr0, mac_addr1, data-\u003ehw_addr);\n \n@@ -1410,7 +1410,7 @@ static int iwl_set_hw_address(struct iwl_trans trans,\n \n \tif (!trans-\u003ecsme_own)\n \t\tIWL_INFO(trans, \"base HW address: %pM, OTP minor version: 0x%x\\n\",\n-\t\t\t data-\u003ehw_addr, iwl_read_prph(trans, REG_OTP_MINOR));\n+\t\t\t data-\u003ehw_addr, iwl_trans_read_prph(trans, REG_OTP_MINOR));\n \n \treturn 0;\n }\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-scd.h b/drivers/net/wireless/intel/iwlwifi/iwl-scd.h\nindex 1eaff898ca3ca..f13568d3094bf 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-scd.h\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-scd.h\n@@ -1,52 +1,52 @@\n /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /\n /\n * Copyright (C) 2014 Intel Mobile Communications GmbH\n+ * Copyright (C) 2026 Intel Corporation\n /\n #ifndef __iwl_scd_h__\n #define __iwl_scd_h__\n \n #include \"iwl-trans.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-prph.h\"\n \n \n static inline void iwl_scd_txq_set_chain(struct iwl_trans trans,\n \t\t\t\t\t u16 txq_id)\n {\n-\tiwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));\n+\tiwl_trans_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));\n }\n \n static inline void iwl_scd_txq_enable_agg(struct iwl_trans trans,\n \t\t\t\t\t u16 txq_id)\n {\n-\tiwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));\n+\tiwl_trans_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));\n }\n \n static inline void iwl_scd_txq_disable_agg(struct iwl_trans trans,\n \t\t\t\t\t u16 txq_id)\n {\n-\tiwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));\n+\tiwl_trans_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));\n }\n \n static inline void iwl_scd_disable_agg(struct iwl_trans trans)\n {\n-\tiwl_set_bits_prph(trans, SCD_AGGR_SEL, 0);\n+\tiwl_trans_set_bits_prph(trans, SCD_AGGR_SEL, 0);\n }\n \n static inline void iwl_scd_activate_fifos(struct iwl_trans trans)\n {\n-\tiwl_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7));\n+\tiwl_trans_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7));\n }\n \n static inline void iwl_scd_deactivate_fifos(struct iwl_trans trans)\n {\n-\tiwl_write_prph(trans, SCD_TXFACT, 0);\n+\tiwl_trans_write_prph(trans, SCD_TXFACT, 0);\n }\n \n static inline void iwl_scd_enable_set_active(struct iwl_trans trans,\n \t\t\t\t\t u32 value)\n {\n-\tiwl_write_prph(trans, SCD_EN_CTRL, value);\n+\tiwl_trans_write_prph(trans, SCD_EN_CTRL, value);\n }\n \n static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)\n@@ -76,9 +76,9 @@ static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)\n static inline void iwl_scd_txq_set_inactive(struct iwl_trans trans,\n \t\t\t\t\t u16 txq_id)\n {\n-\tiwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),\n-\t\t (0 \u003c\u003c SCD_QUEUE_STTS_REG_POS_ACTIVE)\|\n-\t\t (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));\n+\tiwl_trans_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),\n+\t\t\t (0 \u003c\u003c SCD_QUEUE_STTS_REG_POS_ACTIVE)\|\n+\t\t\t (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));\n }\n \n #endif\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.c b/drivers/net/wireless/intel/iwlwifi/iwl-trans.c\nindex 0a6b7b264aa23..6e068f19af7fb 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.c\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.c\n@@ -6,6 +6,7 @@\n /\n #include \u003clinux/kernel.h\u003e\n #include \u003clinux/bsearch.h\u003e\n+#include \u003clinux/delay.h\u003e\n #include \u003clinux/list.h\u003e\n \n #include \"iwl-trans.h\"\n@@ -260,13 +261,14 @@ static void iwl_trans_restart_wk(struct work_struct wk)\n \t\tiwl_trans_schedule_reprobe(trans, 0);\n \t\tbreak;\n \tdefault:\n-\t\tiwl_trans_pcie_reset(trans, mode);\n+\t\tiwl_trans_reset(trans, mode);\n \t\tbreak;\n \t}\n }\n \n struct iwl_trans iwl_trans_alloc(unsigned int priv_size,\n \t\t\t\t struct device dev,\n+\t\t\t\t const struct iwl_trans_ops ops,\n \t\t\t\t const struct iwl_mac_cfg mac_cfg)\n {\n \tstruct iwl_trans trans;\n@@ -278,6 +280,7 @@ struct iwl_trans iwl_trans_alloc(unsigned int priv_size,\n \tif (!trans)\n \t\treturn NULL;\n \n+\ttrans-\u003eops = ops;\n \ttrans-\u003emac_cfg = mac_cfg;\n \n #ifdef CONFIG_LOCKDEP\n@@ -428,45 +431,130 @@ void iwl_trans_op_mode_leave(struct iwl_trans trans)\n }\n IWL_EXPORT_SYMBOL(iwl_trans_op_mode_leave);\n \n-void iwl_trans_write8(struct iwl_trans trans, u32 ofs, u8 val)\n-{\n-\tiwl_trans_pcie_write8(trans, ofs, val);\n-}\n-\n void iwl_trans_write32(struct iwl_trans trans, u32 ofs, u32 val)\n {\n \tiwl_trans_pcie_write32(trans, ofs, val);\n }\n+IWL_EXPORT_SYMBOL(iwl_trans_write32);\n \n u32 iwl_trans_read32(struct iwl_trans trans, u32 ofs)\n {\n \treturn iwl_trans_pcie_read32(trans, ofs);\n }\n+IWL_EXPORT_SYMBOL(iwl_trans_read32);\n \n-u32 iwl_trans_read_prph(struct iwl_trans trans, u32 ofs)\n+u32 iwl_trans_read_prph_no_grab(struct iwl_trans trans, u32 ofs)\n {\n \treturn iwl_trans_pcie_read_prph(trans, ofs);\n }\n \n-void iwl_trans_write_prph(struct iwl_trans trans, u32 ofs, u32 val)\n+void iwl_trans_write_prph_no_grab(struct iwl_trans trans, u32 ofs, u32 val)\n+{\n+\treturn iwl_pcie_write_prph_no_grab(trans, ofs, val);\n+}\n+\n+#define IWL_POLL_INTERVAL 10\t/ microseconds /\n+\n+int iwl_trans_poll_bits_mask(struct iwl_trans trans, u32 addr,\n+\t\t\t u32 bits, u32 mask, int timeout)\n+{\n+\tint t = 0;\n+\n+\tdo {\n+\t\tif ((iwl_trans_read32(trans, addr) \u0026 mask) == (bits \u0026 mask))\n+\t\t\treturn 0;\n+\t\tudelay(IWL_POLL_INTERVAL);\n+\t\tt += IWL_POLL_INTERVAL;\n+\t} while (t \u003c timeout);\n+\n+\treturn -ETIMEDOUT;\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_poll_bits_mask);\n+\n+void iwl_trans_write_direct32(struct iwl_trans trans, u32 reg, u32 value)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tiwl_trans_write32(trans, reg, value);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_write_direct32);\n+\n+u32 iwl_trans_read_prph(struct iwl_trans trans, u32 ofs)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tu32 val = iwl_trans_read_prph_no_grab(trans, ofs);\n+\n+\t\tiwl_trans_release_nic_access(trans);\n+\n+\t\treturn val;\n+\t}\n+\n+\t/* return as if we have a HW timeout/failure /\n+\treturn 0x5a5a5a5a;\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_read_prph);\n+\n+void iwl_trans_write_prph_delay(struct iwl_trans trans, u32 ofs, u32 val,\n+\t\t\t\tu32 delay_ms)\n {\n-\treturn iwl_trans_pcie_write_prph(trans, ofs, val);\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tmdelay(delay_ms);\n+\t\tiwl_trans_write_prph_no_grab(trans, ofs, val);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_write_prph_delay);\n+\n+void iwl_trans_set_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tiwl_trans_write_prph_no_grab(trans, ofs,\n+\t\t\t\t\t iwl_trans_read_prph_no_grab(trans, ofs) \|\n+\t\t\t\t\t mask);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_set_bits_prph);\n+\n+void iwl_trans_set_bits_mask_prph(struct iwl_trans trans, u32 ofs,\n+\t\t\t\t u32 bits, u32 mask)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tiwl_trans_write_prph_no_grab(trans, ofs,\n+\t\t\t\t\t (iwl_trans_read_prph_no_grab(trans, ofs) \u0026\n+\t\t\t\t\t mask) \| bits);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n }\n+IWL_EXPORT_SYMBOL(iwl_trans_set_bits_mask_prph);\n+\n+void iwl_trans_clear_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask)\n+{\n+\tu32 val;\n+\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tval = iwl_trans_read_prph_no_grab(trans, ofs);\n+\t\tiwl_trans_write_prph_no_grab(trans, ofs, (val \u0026 ~mask));\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_clear_bits_prph);\n \n void iwl_trans_force_nmi(struct iwl_trans trans)\n {\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_9000)\n-\t\tiwl_write_prph_delay(trans, DEVICE_SET_NMI_REG,\n-\t\t\t\t DEVICE_SET_NMI_VAL_DRV, 1);\n+\t\tiwl_trans_write_prph_delay(trans, DEVICE_SET_NMI_REG,\n+\t\t\t\t\t DEVICE_SET_NMI_VAL_DRV, 1);\n \telse if (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_AX210)\n-\t\tiwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,\n-\t\t\t\t UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,\n+\t\t\t\t\t UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);\n \telse if (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n-\t\t\t\t UREG_DOORBELL_TO_ISR6_NMI_BIT);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n+\t\t\t\t\t UREG_DOORBELL_TO_ISR6_NMI_BIT);\n \telse\n-\t\tiwl_write32(trans, CSR_DOORBELL_VECTOR,\n-\t\t\t UREG_DOORBELL_TO_ISR6_NMI_BIT);\n+\t\tiwl_trans_write32(trans, CSR_DOORBELL_VECTOR,\n+\t\t\t\t UREG_DOORBELL_TO_ISR6_NMI_BIT);\n }\n IWL_EXPORT_SYMBOL(iwl_trans_force_nmi);\n \n@@ -490,10 +578,10 @@ int iwl_trans_write_mem(struct iwl_trans trans, u32 addr,\n \tconst u32 vals = buf;\n \n \tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);\n+\t\tiwl_trans_write32(trans, HBUS_TARG_MEM_WADDR, addr);\n \t\tfor (offs = 0; offs \u003c dwords; offs++)\n-\t\t\tiwl_write32(trans, HBUS_TARG_MEM_WDAT,\n-\t\t\t\t vals ? vals[offs] : 0);\n+\t\t\tiwl_trans_write32(trans, HBUS_TARG_MEM_WDAT,\n+\t\t\t\t\t vals ? vals[offs] : 0);\n \t\tiwl_trans_release_nic_access(trans);\n \t} else {\n \t\tret = -EBUSY;\n@@ -843,3 +931,17 @@ int iwl_trans_activate_nic(struct iwl_trans trans)\n }\n IWL_EXPORT_SYMBOL(iwl_trans_activate_nic);\n \n+\n+void iwl_trans_reset(struct iwl_trans trans, enum iwl_reset_mode mode)\n+{\n+\tif (!WARN_ON_ONCE(!trans-\u003eops-\u003ereset))\n+\t\ttrans-\u003eops-\u003ereset(trans, mode);\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_reset);\n+\n+void iwl_trans_fw_reset_handshake(struct iwl_trans trans)\n+{\n+\tif (!WARN_ON_ONCE(!trans-\u003eops-\u003efw_reset_handshake))\n+\t\ttrans-\u003eops-\u003efw_reset_handshake(trans);\n+}\n+\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h\nindex 56c5e61b614ad..90100f16ddd52 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h\n@@ -734,12 +734,15 @@ struct iwl_trans_info {\n \tu8 num_rxqs;\n };\n \n+struct iwl_trans_ops;\n+\n /\n struct iwl_trans - transport common data\n \n @csme_own: true if we couldn't get ownership on the device\n * @op_mode: pointer to the op_mode\n * @mac_cfg: the trans-specific configuration part\n+ * @ops: bus-specific transport operations, see \u0026struct iwl_trans_ops\n * @cfg: pointer to the configuration\n * @drv: pointer to iwl_drv\n * @conf: configuration set by the opmode before enter\n@@ -773,6 +776,7 @@ struct iwl_trans {\n \tbool csme_own;\n \tstruct iwl_op_mode op_mode;\n \tconst struct iwl_mac_cfg mac_cfg;\n+\tconst struct iwl_trans_ops ops;\n \tconst struct iwl_rf_cfg cfg;\n \tstruct iwl_drv drv;\n \tstruct iwl_trans_config conf;\n@@ -910,15 +914,13 @@ int iwl_trans_wait_tx_queues_empty(struct iwl_trans trans, u32 txqs);\n \n int iwl_trans_wait_txq_empty(struct iwl_trans trans, int queue);\n \n-void iwl_trans_write8(struct iwl_trans trans, u32 ofs, u8 val);\n-\n void iwl_trans_write32(struct iwl_trans trans, u32 ofs, u32 val);\n \n u32 iwl_trans_read32(struct iwl_trans trans, u32 ofs);\n \n-u32 iwl_trans_read_prph(struct iwl_trans trans, u32 ofs);\n+u32 iwl_trans_read_prph_no_grab(struct iwl_trans trans, u32 ofs);\n \n-void iwl_trans_write_prph(struct iwl_trans trans, u32 ofs, u32 val);\n+void iwl_trans_write_prph_no_grab(struct iwl_trans trans, u32 ofs, u32 val);\n \n int iwl_trans_read_mem(struct iwl_trans trans, u32 addr,\n \t\t void buf, int dwords);\n@@ -979,6 +981,66 @@ int iwl_trans_sw_reset(struct iwl_trans trans);\n void iwl_trans_set_bits_mask(struct iwl_trans trans, u32 reg,\n \t\t\t u32 mask, u32 value);\n \n+static inline void iwl_trans_set_bit(struct iwl_trans trans, u32 reg, u32 mask)\n+{\n+\tiwl_trans_set_bits_mask(trans, reg, mask, mask);\n+}\n+\n+static inline void iwl_trans_clear_bit(struct iwl_trans trans, u32 reg, u32 mask)\n+{\n+\tiwl_trans_set_bits_mask(trans, reg, mask, 0);\n+}\n+\n+int iwl_trans_poll_bits_mask(struct iwl_trans trans, u32 addr,\n+\t\t\t u32 bits, u32 mask, int timeout);\n+static inline int iwl_trans_poll_bits(struct iwl_trans trans, u32 addr, u32 bits,\n+\t\t\t\t int timeout)\n+{\n+\treturn iwl_trans_poll_bits_mask(trans, addr, bits, bits, timeout);\n+}\n+\n+void iwl_trans_write_direct32(struct iwl_trans trans, u32 reg, u32 value);\n+\n+u32 iwl_trans_read_prph(struct iwl_trans trans, u32 ofs);\n+void iwl_trans_write_prph_delay(struct iwl_trans trans, u32 ofs,\n+\t\t\t\tu32 val, u32 delay_ms);\n+static inline void iwl_trans_write_prph(struct iwl_trans trans, u32 ofs, u32 val)\n+{\n+\tiwl_trans_write_prph_delay(trans, ofs, val, 0);\n+}\n+\n+void iwl_trans_set_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask);\n+void iwl_trans_set_bits_mask_prph(struct iwl_trans trans, u32 ofs,\n+\t\t\t\t u32 bits, u32 mask);\n+void iwl_trans_clear_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask);\n+\n+/\n+ * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from\n+ * device family AX200. So peripheries used in families above and below AX200\n+ * should go through iwl_trans_..._umac_..._prph.\n+ /\n+static inline u32 iwl_trans_umac_prph(struct iwl_trans trans, u32 ofs)\n+{\n+\treturn ofs + trans-\u003emac_cfg-\u003eumac_prph_offset;\n+}\n+\n+static inline u32 iwl_trans_read_umac_prph_no_grab(struct iwl_trans trans, u32 ofs)\n+{\n+\treturn iwl_trans_read_prph_no_grab(trans, ofs +\n+\t\t\t\t\t trans-\u003emac_cfg-\u003eumac_prph_offset);\n+}\n+\n+static inline u32 iwl_trans_read_umac_prph(struct iwl_trans trans, u32 ofs)\n+{\n+\treturn iwl_trans_read_prph(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset);\n+}\n+\n+static inline void iwl_trans_write_umac_prph(struct iwl_trans trans, u32 ofs,\n+\t\t\t\t\t u32 val)\n+{\n+\tiwl_trans_write_prph(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset, val);\n+}\n+\n bool iwl_trans_grab_nic_access(struct iwl_trans trans);\n \n /*\n@@ -1088,6 +1150,7 @@ static inline void iwl_trans_finish_sw_reset(struct iwl_trans trans)\n ****************************************************/\n struct iwl_trans iwl_trans_alloc(unsigned int priv_size,\n \t\t\t\t struct device dev,\n+\t\t\t\t const struct iwl_trans_ops ops,\n \t\t\t\t const struct iwl_mac_cfg mac_cfg);\n void iwl_trans_free(struct iwl_trans trans);\n \n@@ -1158,8 +1221,148 @@ enum iwl_reset_mode {\n \tIWL_RESET_MODE_BACKOFF,\n };\n \n-void iwl_trans_pcie_reset(struct iwl_trans trans, enum iwl_reset_mode mode);\n-void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans trans);\n+void iwl_trans_reset(struct iwl_trans trans, enum iwl_reset_mode mode);\n+void iwl_trans_fw_reset_handshake(struct iwl_trans trans);\n+\n+/*\n+ struct iwl_trans_ops - bus-specific transport operations\n+ \n+ Function-pointer table filled in by the bus implementation. Unless noted\n+ * otherwise, each callback implements the identically named iwl_trans_()\n+ API, see its documentation.\n+ \n+ @op_mode_enter: the op_mode took ownership of the transport\n+ * @start_hw: start the hardware\n+ * @op_mode_leave: the op_mode released the transport\n+ * @send_cmd: send a host command to the firmware\n+ * @alloc_tx_cmd: allocate a device TX command\n+ * @free_tx_cmd: free a device TX command\n+ * @write8: write a byte to a device register\n+ * @write32: write a dword to a device register\n+ * @read32: read a dword from a device register\n+ * @read_prph: read a peripheral register\n+ * @write_prph: write a peripheral register\n+ * @read_mem: read device memory, taking NIC access\n+ * @read_mem_no_grab: read device memory, NIC access already taken\n+ * @set_bits_mask: read-modify-write a device register\n+ * @read_config32: read a dword from the bus configuration space\n+ * @grab_nic_access: keep the NIC awake for register access\n+ * @release_nic_access: release the NIC access taken by @grab_nic_access\n+ * @resched_with_nic_access: reschedule while holding NIC access\n+ * @sw_reset: perform a software reset of the device\n+ * @reset: reset the device, see \u0026enum iwl_reset_mode\n+ * @fw_reset_handshake: do a firmware reset handshake.\n+ * @dump_data: collect a firmware error dump\n+ * @d3_suspend: prepare the device for D3 (WoWLAN)\n+ * @d3_resume: resume the device from D3 (WoWLAN)\n+ * @sync_nmi: trigger an NMI and wait for it to be handled\n+ * @write_imr_mem: write to the IMR memory region\n+ * @fw_alive: Notify trans that the firmware sent the ALIVE notification\n+ * @start_fw: download firmware code to the device and and start the firmware\n+ * @stop_device: stop the device and the firmware\n+ * @tx: transmit an MPDU\n+ * @reclaim: free TX MPDUs up to the given sequence number\n+ * @txq_disable: disable a TX queue (gen1)\n+ * @txq_enable: enable a TX queue (gen1)\n+ * @wait_txq_empty: wait for a single TX queue to become empty\n+ * @wait_txqs_empty: wait for the given TX queues to become empty\n+ * @freeze_txq_timer: freeze/unfreeze the watchdog of the given TX queues\n+ * @txq_set_shared_mode: mark a TX queue as shared between TIDs\n+ * @set_q_ptrs: set the write pointer of a TX queue\n+ * @txq_alloc: allocate a TX queue (gen2)\n+ * @txq_free: free a TX queue allocated by @txq_alloc\n+ * @rxq_dma_data: get the DMA addresses of an RX queue\n+ * @load_pnvm: load the PNVM image\n+ * @set_pnvm: tell the firmware to use the loaded PNVM\n+ * @load_reduce_power: load the reduced power table\n+ * @set_reduce_power: tell the firmware to use the reduced power table\n+ * @is_pm_supported: whether bus power management is supported\n+ * @is_ltr_enabled: whether LTR is enabled on the bus\n+ * @activate_nic: bring the NIC out of low power and make it accessible\n+ /\n+struct iwl_trans_ops {\n+\tvoid (op_mode_enter)(struct iwl_trans trans);\n+\tint (start_hw)(struct iwl_trans trans);\n+\tvoid (op_mode_leave)(struct iwl_trans trans);\n+\n+\tint (send_cmd)(struct iwl_trans trans, struct iwl_host_cmd cmd);\n+\tstruct iwl_device_tx_cmd (alloc_tx_cmd)(struct iwl_trans trans);\n+\tvoid (free_tx_cmd)(struct iwl_trans trans,\n+\t\t\t struct iwl_device_tx_cmd dev_cmd);\n+\n+\tvoid (write8)(struct iwl_trans trans, u32 ofs, u8 val);\n+\tvoid (write32)(struct iwl_trans trans, u32 ofs, u32 val);\n+\tu32 (read32)(struct iwl_trans trans, u32 ofs);\n+\tu32 (read_prph)(struct iwl_trans trans, u32 ofs);\n+\tvoid (write_prph)(struct iwl_trans trans, u32 ofs, u32 val);\n+\tint (read_mem)(struct iwl_trans trans, u32 addr,\n+\t\t\tvoid buf, int dwords);\n+\tint (read_mem_no_grab)(struct iwl_trans trans, u32 addr,\n+\t\t\t\tvoid buf, u32 dwords);\n+\tvoid (set_bits_mask)(struct iwl_trans trans, u32 reg,\n+\t\t\t u32 mask, u32 value);\n+\tint (read_config32)(struct iwl_trans trans, u32 ofs, u32 val);\n+\tbool (grab_nic_access)(struct iwl_trans trans);\n+\tvoid (release_nic_access)(struct iwl_trans trans);\n+\tvoid (resched_with_nic_access)(struct iwl_trans trans);\n+\n+\tint (sw_reset)(struct iwl_trans trans, bool retake_ownership);\n+\tvoid (reset)(struct iwl_trans trans, enum iwl_reset_mode mode);\n+\tvoid (fw_reset_handshake)(struct iwl_trans trans);\n+\n+\tstruct iwl_trans_dump_data (dump_data)(struct iwl_trans trans,\n+\t\t\t\t\t\t u32 dump_mask,\n+\t\t\t\t\t\t const struct iwl_dump_sanitize_ops sanitize_ops,\n+\t\t\t\t\t\t void sanitize_ctx);\n+\tint (d3_suspend)(struct iwl_trans trans, bool reset);\n+\tint (d3_resume)(struct iwl_trans trans, bool reset);\n+\n+\tvoid (sync_nmi)(struct iwl_trans trans);\n+\tint (write_imr_mem)(struct iwl_trans trans, u32 dst_addr,\n+\t\t\t u64 src_addr, u32 byte_cnt);\n+\n+\tvoid (fw_alive)(struct iwl_trans trans);\n+\tint (start_fw)(struct iwl_trans trans, const struct iwl_fw fw,\n+\t\t\tconst struct fw_img img, bool run_in_rfkill);\n+\tvoid (stop_device)(struct iwl_trans trans);\n+\n+\tint (tx)(struct iwl_trans trans, struct sk_buff skb,\n+\t\t struct iwl_device_tx_cmd dev_cmd, int queue);\n+\tvoid (reclaim)(struct iwl_trans trans, int queue, int ssn,\n+\t\t\tstruct sk_buff_head skbs, bool is_flush);\n+\tvoid (txq_disable)(struct iwl_trans trans, int queue,\n+\t\t\t bool configure_scd);\n+\tbool (txq_enable)(struct iwl_trans trans, int queue, u16 ssn,\n+\t\t\t const struct iwl_trans_txq_scd_cfg cfg,\n+\t\t\t unsigned int queue_wdg_timeout);\n+\tint (wait_txq_empty)(struct iwl_trans trans, int queue);\n+\tint (wait_txqs_empty)(struct iwl_trans trans, u32 txqs);\n+\tvoid (freeze_txq_timer)(struct iwl_trans trans,\n+\t\t\t\t unsigned long txqs, bool freeze);\n+\tvoid (txq_set_shared_mode)(struct iwl_trans trans, u32 txq_id,\n+\t\t\t\t bool shared_mode);\n+\tvoid (set_q_ptrs)(struct iwl_trans trans, int queue, int ptr);\n+\tint (txq_alloc)(struct iwl_trans trans, u32 flags, u32 sta_mask,\n+\t\t\t u8 tid, int size, unsigned int wdg_timeout);\n+\tvoid (txq_free)(struct iwl_trans trans, int queue);\n+\tint (rxq_dma_data)(struct iwl_trans trans, int queue,\n+\t\t\t struct iwl_trans_rxq_dma_data data);\n+\n+\tint (load_pnvm)(struct iwl_trans trans,\n+\t\t\t const struct iwl_pnvm_image pnvm_data,\n+\t\t\t const struct iwl_ucode_capabilities capa);\n+\tvoid (set_pnvm)(struct iwl_trans trans,\n+\t\t\t const struct iwl_ucode_capabilities capa);\n+\tint (load_reduce_power)(struct iwl_trans trans,\n+\t\t\t\t const struct iwl_pnvm_image payloads,\n+\t\t\t\t const struct iwl_ucode_capabilities capa);\n+\tvoid (set_reduce_power)(struct iwl_trans trans,\n+\t\t\t\t const struct iwl_ucode_capabilities capa);\n+\n+\tbool (is_pm_supported)(struct iwl_trans trans);\n+\tbool (is_ltr_enabled)(struct iwl_trans trans);\n+\tint (activate_nic)(struct iwl_trans trans);\n+};\n \n / Internal helper /\n static inline void iwl_trans_set_info(struct iwl_trans trans,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/constants.h b/drivers/net/wireless/intel/iwlwifi/mld/constants.h\nindex 890abcab38374..bfd5398510ee3 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/constants.h\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/constants.h\n@@ -39,6 +39,10 @@\n \n #define IWL_MLD_TPT_COUNT_WINDOW (5 * HZ)\n \n+#define IWL_MLD_TX_GP2_VALID_PERIOD\t(10 * HZ)\n+#define IWL_MLD_TX_GP2_REFRESH_MARGIN\t(5 * HZ)\n+#define IWL_MLD_TX_GP2_RETRY_PERIOD\tHZ\n+\n #define IWL_MLD_DIS_RANDOM_FW_ID false\n #define IWL_MLD_D3_DEBUG false\n #define IWL_MLD_NON_TRANSMITTING_AP\t false\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/d3.c b/drivers/net/wireless/intel/iwlwifi/mld/d3.c\nindex 6d8ede336d59b..7a7d07a7914dd 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/d3.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/d3.c\n@@ -5,6 +5,7 @@\n #include \"mld.h\"\n \n #include \"d3.h\"\n+#include \"tx.h\"\n #include \"power.h\"\n #include \"hcmd.h\"\n #include \"iface.h\"\n@@ -1610,6 +1611,8 @@ int iwl_mld_no_wowlan_suspend(struct iwl_mld mld)\n \n \tiwl_mld_low_latency_stop(mld);\n \n+\tiwl_mld_tx_gp2_stop(mld);\n+\n \tret = iwl_mld_update_device_power(mld, true);\n \tif (ret) {\n \t\tIWL_ERR(mld,\n@@ -1663,6 +1666,8 @@ int iwl_mld_no_wowlan_resume(struct iwl_mld mld)\n \n \tiwl_mld_low_latency_restart(mld);\n \n+\tiwl_mld_tx_gp2_start(mld);\n+\n \treturn iwl_mld_update_device_power(mld, false);\n }\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c\nindex dd4bf7cb6a791..b8793b71494d8 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c\n@@ -5,7 +5,7 @@\n \n #include \"mld.h\"\n #include \"debugfs.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"hcmd.h\"\n #include \"iface.h\"\n #include \"sta.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c\nindex a4b8037b5c765..a6a4f9672e4f9 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c\n@@ -8,7 +8,7 @@\n #include \"mld.h\"\n #include \"iface.h\"\n #include \"phy.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"constants.h\"\n #include \"fw/api/location.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/fw.c b/drivers/net/wireless/intel/iwlwifi/mld/fw.c\nindex e5866d89176d1..3b9f412cdff2b 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/fw.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/fw.c\n@@ -1,9 +1,10 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /\n- Copyright (C) 2024-2025 Intel Corporation\n+ * Copyright (C) 2024-2026 Intel Corporation\n /\n \n #include \"mld.h\"\n+#include \"tx.h\"\n \n #include \"fw/api/alive.h\"\n #include \"fw/api/scan.h\"\n@@ -206,11 +207,11 @@ static void iwl_mld_print_alive_notif_timeout(struct iwl_mld mld)\n \n \tIWL_ERR(mld,\n \t\t\"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\\n\",\n-\t\tiwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),\n-\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t UMAG_SB_CPU_2_STATUS));\n+\t\tiwl_trans_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),\n+\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t UMAG_SB_CPU_2_STATUS));\n #define IWL_FW_PRINT_REG_INFO(reg_name) \\\n-\tIWL_ERR(mld, #reg_name \": 0x%x\\n\", iwl_read_umac_prph(trans, reg_name))\n+\tIWL_ERR(mld, #reg_name \": 0x%x\\n\", iwl_trans_read_umac_prph(trans, reg_name))\n \n \tIWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION);\n \n@@ -355,6 +356,8 @@ void iwl_mld_stop_fw(struct iwl_mld mld)\n {\n \tlockdep_assert_wiphy(mld-\u003ewiphy);\n \n+\tiwl_mld_tx_gp2_stop(mld);\n+\n \tiwl_abort_notification_waits(\u0026mld-\u003enotif_wait);\n \n \tiwl_fw_dbg_stop_sync(\u0026mld-\u003efwrt);\n@@ -542,6 +545,8 @@ int iwl_mld_start_fw(struct iwl_mld mld)\n \tif (ret)\n \t\tgoto error;\n \n+\tiwl_mld_tx_gp2_start(mld);\n+\n \treturn 0;\n \n error:\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c\nindex 0b121114d47ca..e05bdbd3e1a9a 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c\n@@ -2168,6 +2168,8 @@ static int iwl_mld_resume(struct ieee80211_hw hw)\n \n \tiwl_mld_low_latency_restart(mld);\n \n+\tiwl_mld_tx_gp2_start(mld);\n+\n \treturn 0;\n }\n #endif\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/mld.c b/drivers/net/wireless/intel/iwlwifi/mld/mld.c\nindex b7b1e3686336c..71832d92024d0 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/mld.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/mld.c\n@@ -35,6 +35,17 @@ MODULE_IMPORT_NS(\"IWLWIFI\");\n \n static const struct iwl_op_mode_ops iwl_mld_ops;\n \n+int iwl_mld_get_systime(struct iwl_mld mld, u32 gp2)\n+{\n+\tgp2 = iwl_trans_read_prph(mld-\u003etrans,\n+\t\t\t mld-\u003etrans-\u003emac_cfg-\u003ebase-\u003egp2_reg_addr);\n+\n+\tif (gp2 == 0x5a5a5a5a)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n static int __init iwl_mld_init(void)\n {\n \tint ret = iwl_opmode_register(\"iwlmld\", \u0026iwl_mld_ops);\n@@ -425,6 +436,8 @@ iwl_op_mode_mld_start(struct iwl_trans trans, const struct iwl_rf_cfg cfg,\n \t/ Configure transport layer with the opmode specific params /\n \tiwl_mld_configure_trans(op_mode);\n \n+\tiwl_mld_tx_gp2_init(mld);\n+\n \t/ needed for regulatory init /\n \trtnl_lock();\n \t/ Needed for sending commands /\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/mld.h b/drivers/net/wireless/intel/iwlwifi/mld/mld.h\nindex 37f41b504b54c..a9e65b216fd39 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/mld.h\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/mld.h\n@@ -29,6 +29,7 @@\n #include \"notif.h\"\n #include \"scan.h\"\n #include \"rx.h\"\n+#include \"tx.h\"\n #include \"thermal.h\"\n #include \"low_latency.h\"\n #include \"constants.h\"\n@@ -196,6 +197,7 @@\n \tbeing IBSS manager for that time and needing to respond to probe\n \trequests\n @ptp_data: data of the PTP clock\n+ * @tx_gp2: gp2 timestamping state for TX commands\n * @time_sync: time sync data.\n * @ftm_initiator: FTM initiator data\n * @nan_device_vif: points to the NAN device vif if exists\n@@ -306,6 +308,8 @@ struct iwl_mld {\n \n \tstruct ptp_data ptp_data;\n \n+\tstruct iwl_mld_tx_gp2 tx_gp2;\n+\n \tstruct iwl_mld_time_sync_data __rcu time_sync;\n \n \tstruct ftm_initiator_data ftm_initiator;\n@@ -572,6 +576,8 @@ iwl_mld_fw_id_to_link_conf(struct iwl_mld mld, u8 fw_link_id)\n \n #define MSEC_TO_TU(_msec)\t((_msec) * 1000 / 1024)\n \n+int iwl_mld_get_systime(struct iwl_mld mld, u32 gp2);\n+\n void iwl_mld_add_vif_debugfs(struct ieee80211_hw hw,\n \t\t\t struct ieee80211_vif vif);\n void iwl_mld_add_link_debugfs(struct ieee80211_hw hw,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c\nindex 1ac85d6ce1d79..9f7d17dbdee16 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c\n@@ -1,6 +1,6 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /\n- * Copyright (C) 2025 Intel Corporation\n+ * Copyright (C) 2025 - 2026 Intel Corporation\n /\n \n #include \"mld.h\"\n@@ -19,16 +19,6 @@\n #define IWL_PTP_WRAP_TIME\t(3600 HZ)\n #define IWL_PTP_WRAP_THRESHOLD_USEC\t(5000)\n \n-static int iwl_mld_get_systime(struct iwl_mld mld, u32 gp2)\n-{\n-\tgp2 = iwl_read_prph(mld-\u003etrans, mld-\u003etrans-\u003emac_cfg-\u003ebase-\u003egp2_reg_addr);\n-\n-\tif (gp2 == 0x5a5a5a5a)\n-\t\treturn -EINVAL;\n-\n-\treturn 0;\n-}\n-\n static void iwl_mld_ptp_update_new_read(struct iwl_mld mld, u32 gp2)\n {\n \tIWL_DEBUG_PTP(mld, \"PTP: last_gp2=%u, new gp2 read=%u\\n\",\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/rx.c b/drivers/net/wireless/intel/iwlwifi/mld/rx.c\nindex 5f18aa551af52..8fa438fd78153 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/rx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/rx.c\n@@ -553,7 +553,10 @@ iwl_mld_decode_he_tb_phy_data(struct iwl_mld_rx_phy_data phy_data,\n \n \tnsts = le32_get_bits(phy_data-\u003entfy-\u003esigs.he_tb.tb_rx1,\n \t\t\t OFDM_UCODE_TRIG_BASE_RX_NSTS) + 1;\n-\trx_status-\u003enss = nsts \u003e\u003e !!(rate_n_flags \u0026 RATE_MCS_STBC_MSK);\n+\n+\trx_status-\u003enss = nsts;\n+\tif (rate_n_flags \u0026 RATE_MCS_STBC_MSK)\n+\t\trx_status-\u003enss = 1;\n }\n \n static void\n@@ -589,7 +592,9 @@ iwl_mld_decode_he_phy_data(struct iwl_mld_rx_phy_data phy_data,\n \t\tbreak;\n \t}\n \n-\trx_status-\u003enss = nsts \u003e\u003e !!(rate_n_flags \u0026 RATE_MCS_STBC_MSK);\n+\trx_status-\u003enss = nsts;\n+\tif (rate_n_flags \u0026 RATE_MCS_STBC_MSK)\n+\t\trx_status-\u003enss = 1;\n \n \the-\u003edata1 \|= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN \|\n \t\t\t\t IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/scan.c b/drivers/net/wireless/intel/iwlwifi/mld/scan.c\nindex e44b24904c19a..b942ac1e7ccca 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/scan.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/scan.c\n@@ -2273,6 +2273,7 @@ void iwl_mld_handle_channel_survey_notif(struct iwl_mld mld,\n \t/* Times are all in ms /\n \tinfo-\u003etime = le32_to_cpu(notif-\u003eactive_time);\n \tinfo-\u003etime_busy = le32_to_cpu(notif-\u003ebusy_time);\n+\tinfo-\u003etime_rx = le32_to_cpu(notif-\u003erx_time);\n \tinfo-\u003enoise =\n \t\tiwl_average_neg_dbm(notif-\u003enoise, ARRAY_SIZE(notif-\u003enoise));\n }\n@@ -2321,9 +2322,11 @@ int iwl_mld_mac80211_get_survey(struct ieee80211_hw hw, int idx,\n \t\t\t/* Found (the next) channel to report /\n \t\t\tsurvey-\u003echannel = \u0026sband-\u003echannels[per_band_idx];\n \t\t\tsurvey-\u003efilled = SURVEY_INFO_TIME \|\n-\t\t\t\t\t SURVEY_INFO_TIME_BUSY;\n+\t\t\t\t\t SURVEY_INFO_TIME_BUSY \|\n+\t\t\t\t\t SURVEY_INFO_TIME_RX;\n \t\t\tsurvey-\u003etime = info-\u003etime;\n \t\t\tsurvey-\u003etime_busy = info-\u003etime_busy;\n+\t\t\tsurvey-\u003etime_rx = info-\u003etime_rx;\n \t\t\tsurvey-\u003enoise = info-\u003enoise;\n \t\t\tif (survey-\u003enoise \u003c 0)\n \t\t\t\tsurvey-\u003efilled \|= SURVEY_INFO_NOISE_DBM;\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/scan.h b/drivers/net/wireless/intel/iwlwifi/mld/scan.h\nindex dc299fe2f999c..74ebe8296693f 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/scan.h\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/scan.h\n@@ -1,6 +1,6 @@\n / SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /\n /\n- * Copyright (C) 2024-2025 Intel Corporation\n+ * Copyright (C) 2024-2026 Intel Corporation\n /\n #ifndef __iwl_mld_scan_h__\n #define __iwl_mld_scan_h__\n@@ -151,11 +151,13 @@ struct iwl_mld_scan {\n \n * @time: time in ms the radio was on the channel\n * @time_busy: time in ms the channel was sensed busy\n+ * @time_rx: time in ms the channel was sensed to carry Wi-Fi frames\n * @noise: channel noise in dBm\n /\n struct iwl_mld_survey_channel {\n \tu32 time;\n \tu32 time_busy;\n+\tu32 time_rx;\n \ts8 noise;\n };\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/sta.c b/drivers/net/wireless/intel/iwlwifi/mld/sta.c\nindex 7957ac11b0cd5..97f013330f068 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/sta.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/sta.c\n@@ -465,8 +465,8 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld mld,\n \tstruct iwl_mld_sta mld_sta = iwl_mld_sta_from_mac80211(sta);\n \tstruct iwl_sta_cfg_cmd cmd = {};\n \tint fw_id = iwl_mld_fw_sta_id_from_link_sta(mld, link_sta);\n-\tbool is_6ghz, uora_exists;\n \tu32 link_mask;\n+\tbool is_6ghz;\n \n \tlockdep_assert_wiphy(mld-\u003ewiphy);\n \n@@ -479,7 +479,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld mld,\n \t\t\treturn -EINVAL;\n \n \t\tis_6ghz = false;\n-\t\tuora_exists = false;\n \n \t\tlink_mask = iwl_mld_get_nan_link_mask(mld);\n \t} else {\n@@ -495,7 +494,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld mld,\n \n \t\tlink_mask = BIT(mld_link-\u003efw_id);\n \t\tis_6ghz = link-\u003echanreq.oper.chan-\u003eband == NL80211_BAND_6GHZ;\n-\t\tuora_exists = link-\u003euora_exists;\n \t}\n \n \tcmd.sta_id = cpu_to_le32(fw_id);\n@@ -554,9 +552,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld mld,\n \t}\n \n \tif (link_sta-\u003ehe_cap.has_he) {\n-\t\tcmd.trig_rnd_alloc =\n-\t\t\tcpu_to_le32(uora_exists ? 1 : 0);\n-\n \t\t/* PPE Thresholds /\n \t\tiwl_mld_fill_pkt_ext(mld, link_sta, \u0026cmd.pkt_ext);\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile b/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile\nindex efa61638b8eeb..730185be3fa82 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile\n@@ -1,6 +1,6 @@\n # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n iwlmld-tests-y += module.o hcmd.o utils.o link.o rx.o agg.o link-selection.o\n-iwlmld-tests-y += chan_load_thresh.o\n+iwlmld-tests-y += chan_load_thresh.o tx-gp2.o\n \n ccflags-y += -I$(src)/../\n obj-$(CONFIG_IWLWIFI_KUNIT_TESTS) += iwlmld-tests.o\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c b/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c\nnew file mode 100644\nindex 0000000000000..535140eb17c47\n--- /dev/null\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c\n@@ -0,0 +1,154 @@\n+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n+/\n+ * KUnit tests for TX gp2 timestamp handling\n+ \n+ Copyright (C) 2026 Intel Corporation\n+ /\n+#include \u003ckunit/test.h\u003e\n+\n+#include \"mld.h\"\n+#include \"tx.h\"\n+\n+MODULE_IMPORT_NS(\"EXPORTED_FOR_KUNIT_TESTING\");\n+\n+static const struct tx_gp2_case {\n+\tconst char desc;\n+\tu32 est_gp2_us;\n+\tu32 est_host_us;\n+\tu32 tx_host_us;\n+\tlong valid_for;\n+\tu32 expected_gp2_us;\n+\tbool expected_refresh;\n+} tx_gp2_cases[] = {\n+\t{\n+\t\t.desc = \"zero offset is valid\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 2000,\n+\t\t.tx_host_us = 3500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 3500,\n+\t},\n+\t{\n+\t\t.desc = \"gp2 behind host\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 3500,\n+\t},\n+\t{\n+\t\t.desc = \"gp2 ahead of host\",\n+\t\t.est_gp2_us = 10000,\n+\t\t.est_host_us = 2000,\n+\t\t.tx_host_us = 3500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 11500,\n+\t},\n+\t{\n+\t\t.desc = \"gp2 wraps after the estimate\",\n+\t\t.est_gp2_us = U32_MAX - 999,\n+\t\t.est_host_us = 1000,\n+\t\t.tx_host_us = 2500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 500,\n+\t},\n+\t{\n+\t\t.desc = \"host time wraps after the estimate\",\n+\t\t.est_gp2_us = 5000,\n+\t\t.est_host_us = U32_MAX - 999,\n+\t\t.tx_host_us = 500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 6500,\n+\t},\n+\t{\n+\t\t.desc = \"gp2 landing on 0 is reported as 1\",\n+\t\t.est_gp2_us = U32_MAX - 1499,\n+\t\t.est_host_us = 1000,\n+\t\t.tx_host_us = 2500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 1,\n+\t},\n+\t{\n+\t\t.desc = \"within the refresh margin: still timestamped\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN - 1,\n+\t\t.expected_gp2_us = 3500,\n+\t\t.expected_refresh = true,\n+\t},\n+\t{\n+\t\t.desc = \"outside the refresh margin: no refresh\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN + 1,\n+\t\t.expected_gp2_us = 3500,\n+\t},\n+\t{\n+\t\t.desc = \"at the refresh threshold\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN,\n+\t\t.expected_gp2_us = 3500,\n+\t\t.expected_refresh = true,\n+\t},\n+\t{\n+\t\t.desc = \"last valid tick\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = 1,\n+\t\t.expected_gp2_us = 3500,\n+\t\t.expected_refresh = true,\n+\t},\n+\t{\n+\t\t.desc = \"validity reached: leave the frame unstamped\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = 0,\n+\t\t.expected_refresh = true,\n+\t},\n+\t{\n+\t\t.desc = \"validity passed: leave the frame unstamped\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = -1,\n+\t\t.expected_refresh = true,\n+\t},\n+};\n+\n+KUNIT_ARRAY_PARAM_DESC(tx_gp2, tx_gp2_cases, desc);\n+\n+static void test_tx_gp2(struct kunit test)\n+{\n+\t/ Pin time near wraparound to exercise wrapped validity deadlines. /\n+\tconst unsigned long now =\n+\t\tULONG_MAX - IWL_MLD_TX_GP2_REFRESH_MARGIN - 1;\n+\tconst struct tx_gp2_case test_case = test-\u003eparam_value;\n+\tu32 delta_us = test_case-\u003eest_gp2_us - test_case-\u003eest_host_us;\n+\tunsigned long valid_until = now + test_case-\u003evalid_for;\n+\tbool refresh = !test_case-\u003eexpected_refresh;\n+\tu32 timestamp;\n+\n+\ttimestamp = iwl_mld_tx_gp2_from_est(delta_us, valid_until,\n+\t\t\t\t\t test_case-\u003etx_host_us, now,\n+\t\t\t\t\t \u0026refresh);\n+\tKUNIT_EXPECT_EQ(test, timestamp, test_case-\u003eexpected_gp2_us);\n+\tKUNIT_EXPECT_EQ(test, refresh, test_case-\u003eexpected_refresh);\n+}\n+\n+static struct kunit_case tx_gp2_test_cases[] = {\n+\tKUNIT_CASE_PARAM(test_tx_gp2, tx_gp2_gen_params),\n+\t{}\n+};\n+\n+static struct kunit_suite tx_gp2_test_suite = {\n+\t.name = \"iwl_mld_tx_gp2\",\n+\t.test_cases = tx_gp2_test_cases,\n+};\n+\n+kunit_test_suite(tx_gp2_test_suite);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/tx.c b/drivers/net/wireless/intel/iwlwifi/mld/tx.c\nindex 2df6643a5aa80..fc501ac0c1f29 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/tx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/tx.c\n@@ -2,6 +2,7 @@\n /\n Copyright (C) 2024 - 2026 Intel Corporation\n /\n+#include \u003clinux/timekeeping.h\u003e\n #include \u003cnet/ip.h\u003e\n \n #include \"tx.h\"\n@@ -20,6 +21,133 @@\n \n #define MAX_ANT_NUM 2\n \n+static u32 iwl_mld_tx_gp2_host_us(void)\n+{\n+\treturn div_u64(ktime_get_boottime_ns(), NSEC_PER_USEC);\n+}\n+\n+/ Returns the gp2 for the TX command, or 0 to leave the frame unstamped.\n+ * Sets @refresh when the estimate expired or is about to.\n+ /\n+VISIBLE_IF_IWLWIFI_KUNIT u32\n+iwl_mld_tx_gp2_from_est(u32 delta_us, unsigned long valid_until, u32 host_us,\n+\t\t\tunsigned long now, bool refresh)\n+{\n+\tu32 gp2;\n+\n+\trefresh = time_after_eq(now, valid_until -\n+\t\t\t\t IWL_MLD_TX_GP2_REFRESH_MARGIN);\n+\n+\tif (time_after_eq(now, valid_until))\n+\t\treturn 0;\n+\n+\tgp2 = host_us + delta_us;\n+\n+\t/ 0 means no timestamp; use 1 for a valid wrapped value. /\n+\treturn gp2 ?: 1;\n+}\n+EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_mld_tx_gp2_from_est);\n+\n+static u32\n+iwl_mld_tx_gp2_timestamp(struct iwl_mld mld)\n+{\n+\tunsigned long valid_until =\n+\t\tatomic_long_read_acquire(\u0026mld-\u003etx_gp2.valid_until);\n+\tbool refresh = false;\n+\tu32 gp2;\n+\n+\tif (!valid_until)\n+\t\treturn 0;\n+\n+\tgp2 = iwl_mld_tx_gp2_from_est(atomic_read(\u0026mld-\u003etx_gp2.delta_us),\n+\t\t\t\t valid_until, iwl_mld_tx_gp2_host_us(),\n+\t\t\t\t jiffies, \u0026refresh);\n+\n+\tif (refresh)\n+\t\twiphy_delayed_work_queue(mld-\u003ewiphy, \u0026mld-\u003etx_gp2.wk, 0);\n+\n+\treturn gp2;\n+}\n+\n+static void iwl_mld_tx_gp2_refresh(struct iwl_mld mld)\n+{\n+\tunsigned long valid_until, delay;\n+\tu32 gp2, host_us;\n+\n+\tlockdep_assert_wiphy(mld-\u003ewiphy);\n+\n+\tif (!mld-\u003efw_status.running)\n+\t\treturn;\n+\n+#ifdef CONFIG_PM_SLEEP\n+\tif (mld-\u003efw_status.in_d3)\n+\t\treturn;\n+#endif\n+\n+\tif (iwl_mld_get_systime(mld, \u0026gp2))\n+\t\tgoto retry;\n+\n+\thost_us = iwl_mld_tx_gp2_host_us();\n+\tvalid_until = jiffies + IWL_MLD_TX_GP2_VALID_PERIOD;\n+\n+\t/ Keep arithmetic in u32 to match firmware wraparound semantics. /\n+\tatomic_set(\u0026mld-\u003etx_gp2.delta_us, gp2 - host_us);\n+\tatomic_long_set_release(\u0026mld-\u003etx_gp2.valid_until, valid_until ?: 1);\n+\n+\tIWL_DEBUG_TX(mld, \"gp2 sync: gp2=%u host_us=%u delta_us=%u\\n\",\n+\t\t gp2, host_us, gp2 - host_us);\n+\treturn;\n+\n+retry:\n+\t/ Stop new TX readers from requesting immediate retries. /\n+\tatomic_long_set(\u0026mld-\u003etx_gp2.valid_until, 0);\n+\tdelay = round_jiffies_relative(IWL_MLD_TX_GP2_RETRY_PERIOD);\n+\twiphy_delayed_work_queue(mld-\u003ewiphy, \u0026mld-\u003etx_gp2.wk, delay);\n+}\n+\n+static void iwl_mld_tx_gp2_wk(struct wiphy wiphy, struct wiphy_work wk)\n+{\n+\tstruct iwl_mld mld = container_of(wk, struct iwl_mld, tx_gp2.wk.work);\n+\tunsigned long valid_until = atomic_long_read(\u0026mld-\u003etx_gp2.valid_until);\n+\n+\t/* TX may have queued this work using an older estimate. /\n+\tif (valid_until \u0026\u0026\n+\t time_before(jiffies, valid_until - IWL_MLD_TX_GP2_REFRESH_MARGIN))\n+\t\treturn;\n+\n+\tiwl_mld_tx_gp2_refresh(mld);\n+}\n+\n+void iwl_mld_tx_gp2_init(struct iwl_mld mld)\n+{\n+\tatomic_set(\u0026mld-\u003etx_gp2.delta_us, 0);\n+\tatomic_long_set(\u0026mld-\u003etx_gp2.valid_until, 0);\n+\twiphy_delayed_work_init(\u0026mld-\u003etx_gp2.wk, iwl_mld_tx_gp2_wk);\n+}\n+\n+void iwl_mld_tx_gp2_start(struct iwl_mld mld)\n+{\n+\tlockdep_assert_wiphy(mld-\u003ewiphy);\n+\n+\tif (iwl_fw_lookup_cmd_ver(mld-\u003efw, TX_CMD, 0) \u003c 12)\n+\t\treturn;\n+\n+\tiwl_mld_tx_gp2_refresh(mld);\n+}\n+\n+/ TX is quiesced before stopping the refresh work. /\n+void iwl_mld_tx_gp2_stop(struct iwl_mld mld)\n+{\n+\tlockdep_assert_wiphy(mld-\u003ewiphy);\n+\n+\tif (iwl_fw_lookup_cmd_ver(mld-\u003efw, TX_CMD, 0) \u003c 12)\n+\t\treturn;\n+\n+\twiphy_delayed_work_cancel(mld-\u003ewiphy, \u0026mld-\u003etx_gp2.wk);\n+\n+\tatomic_long_set(\u0026mld-\u003etx_gp2.valid_until, 0);\n+}\n+\n /* Toggles between TX antennas. Receives the bitmask of valid TX antennas and\n * the index used for the last TX, and returns the next valid index to use.\n * In order to set it in the tx_cmd, must do BIT(idx).\n@@ -588,6 +716,9 @@ iwl_mld_fill_tx_cmd(struct iwl_mld mld, struct sk_buff skb,\n \ttx_cmd-\u003eflags = cpu_to_le16(flags);\n \n \ttx_cmd-\u003erate_n_flags = rate_n_flags;\n+\n+\ttx_cmd-\u003edriver_timestamp =\n+\t\tcpu_to_le32(iwl_mld_tx_gp2_timestamp(mld));\n }\n \n /* Caller of this need to check that info-\u003econtrol.vif is not NULL /\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/tx.h b/drivers/net/wireless/intel/iwlwifi/mld/tx.h\nindex 520f15f9d33ca..a376e8c9c5005 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/tx.h\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/tx.h\n@@ -1,11 +1,15 @@\n / SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /\n /\n- * Copyright (C) 2024 Intel Corporation\n+ * Copyright (C) 2024, 2026 Intel Corporation\n /\n #ifndef __iwl_mld_tx_h__\n #define __iwl_mld_tx_h__\n \n-#include \"mld.h\"\n+#include \u003clinux/atomic.h\u003e\n+#include \u003cnet/mac80211.h\u003e\n+\n+struct iwl_mld;\n+struct iwl_rx_packet;\n \n #define IWL_MLD_INVALID_QUEUE\t\t0xFFFF\n #define IWL_MLD_INVALID_DROP_TX\t\t0xFFFE\n@@ -74,4 +78,37 @@ u8 iwl_mld_get_lowest_rate(struct iwl_mld mld,\n void iwl_mld_tx_skb(struct iwl_mld mld, struct sk_buff skb,\n \t\t struct ieee80211_txq txq);\n \n+/\n+ struct iwl_mld_tx_gp2 - gp2 timestamping state for TX commands\n+ \n+ Reading gp2 directly in the TX path is too costly. Instead, TX lazily\n+ * schedules @wk to refresh gp2 in process context and adds @delta_us to the\n+ * host clock to timestamp queued frames.\n+ \n+ A zero @valid_until leaves frames unstamped, including on older firmware\n+ * without TX_CMD v12. A deadline that wraps to zero is published as one.\n+ * Failed refreshes clear @valid_until, leaving @delta_us for old readers, and\n+ * schedule a retry with %IWL_MLD_TX_GP2_RETRY_PERIOD rounded for timer\n+ * coalescing, even without further TX traffic. Old readers may retry sooner.\n+ \n+ @delta_us: gp2 minus host time, in microseconds, modulo 2^32;\n+ \tvalid while @valid_until is nonzero and has not expired\n+ @valid_until: jiffies deadline for the offset, or zero when disabled\n+ * @wk: worker that refreshes the offset and retries failures\n+ /\n+struct iwl_mld_tx_gp2 {\n+\tatomic_t delta_us;\n+\tatomic_long_t valid_until;\n+\tstruct wiphy_delayed_work wk;\n+};\n+\n+void iwl_mld_tx_gp2_init(struct iwl_mld mld);\n+void iwl_mld_tx_gp2_start(struct iwl_mld mld);\n+void iwl_mld_tx_gp2_stop(struct iwl_mld mld);\n+\n+#if IS_ENABLED(CONFIG_IWLWIFI_KUNIT_TESTS)\n+u32 iwl_mld_tx_gp2_from_est(u32 delta_us, unsigned long valid_until,\n+\t\t\t u32 host_us, unsigned long now, bool refresh);\n+#endif\n+\n #endif / __iwl_mld_tx_h__ /\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c\nindex 06502f57e823e..90175307a7db2 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c\n@@ -13,7 +13,7 @@\n \n #include \"mvm.h\"\n #include \"sta.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"debugfs.h\"\n #include \"iwl-modparams.h\"\n #include \"iwl-drv.h\"\n@@ -1548,7 +1548,7 @@ iwl_dbgfs_prph_reg_read(struct file file,\n \n \tpos += scnprintf(buf + pos, bufsz - pos, \"Reg 0x%x: (0x%x)\\n\",\n \t\tmvm-\u003edbgfs_prph_reg_addr,\n-\t\tiwl_read_prph(mvm-\u003etrans, mvm-\u003edbgfs_prph_reg_addr));\n+\t\tiwl_trans_read_prph(mvm-\u003etrans, mvm-\u003edbgfs_prph_reg_addr));\n \n \treturn simple_read_from_buffer(user_buf, count, ppos, buf, pos);\n }\n@@ -1569,7 +1569,7 @@ iwl_dbgfs_prph_reg_write(struct iwl_mvm mvm, char buf,\n \tif (args != 2)\n \t\treturn -EINVAL;\n \n-\tiwl_write_prph(mvm-\u003etrans, mvm-\u003edbgfs_prph_reg_addr, value);\n+\tiwl_trans_write_prph(mvm-\u003etrans, mvm-\u003edbgfs_prph_reg_addr, value);\n \n out:\n \treturn count;\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c\nindex 8d7f60dcd0270..4c39a452564da 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c\n@@ -7,7 +7,7 @@\n #include \u003clinux/math64.h\u003e\n #include \u003cnet/cfg80211.h\u003e\n #include \"mvm.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"constants.h\"\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c\nindex c3402f5e47a03..ae109e3ea141c 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c\n@@ -263,7 +263,7 @@ static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data notif_wait,\n static void iwl_mvm_print_pd_notification(struct iwl_mvm mvm)\n {\n #define IWL_FW_PRINT_REG_INFO(reg_name) \\\n-\tIWL_ERR(mvm, #reg_name \": 0x%x\\n\", iwl_read_umac_prph(trans, reg_name))\n+\tIWL_ERR(mvm, #reg_name \": 0x%x\\n\", iwl_trans_read_umac_prph(trans, reg_name))\n \n \tstruct iwl_trans trans = mvm-\u003etrans;\n \tenum iwl_device_family device_family = trans-\u003emac_cfg-\u003edevice_family;\n@@ -332,13 +332,13 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm mvm,\n \t IWL_DEVICE_FAMILY_AX210) {\n \t\t/* print these registers regardless of alive fail/success /\n \t\tIWL_INFO(mvm, \"WFPM_UMAC_PD_NOTIFICATION: 0x%x\\n\",\n-\t\t\t iwl_read_umac_prph(mvm-\u003etrans, WFPM_ARC1_PD_NOTIFICATION));\n+\t\t\t iwl_trans_read_umac_prph(mvm-\u003etrans, WFPM_ARC1_PD_NOTIFICATION));\n \t\tIWL_INFO(mvm, \"WFPM_LMAC2_PD_NOTIFICATION: 0x%x\\n\",\n-\t\t\t iwl_read_umac_prph(mvm-\u003etrans, WFPM_LMAC2_PD_NOTIFICATION));\n+\t\t\t iwl_trans_read_umac_prph(mvm-\u003etrans, WFPM_LMAC2_PD_NOTIFICATION));\n \t\tIWL_INFO(mvm, \"WFPM_AUTH_KEY_0: 0x%x\\n\",\n-\t\t\t iwl_read_umac_prph(mvm-\u003etrans, SB_MODIFY_CFG_FLAG));\n+\t\t\t iwl_trans_read_umac_prph(mvm-\u003etrans, SB_MODIFY_CFG_FLAG));\n \t\tIWL_INFO(mvm, \"CNVI_SCU_SEQ_DATA_DW9: 0x%x\\n\",\n-\t\t\t iwl_read_prph(mvm-\u003etrans, CNVI_SCU_SEQ_DATA_DW9));\n+\t\t\t iwl_trans_read_prph(mvm-\u003etrans, CNVI_SCU_SEQ_DATA_DW9));\n \t}\n \n \tif (ret) {\n@@ -349,15 +349,15 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm mvm,\n \t\t\t\t\tIWL_DEVICE_FAMILY_22000) {\n \t\t\tIWL_ERR(mvm,\n \t\t\t\t\"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\\n\",\n-\t\t\t\tiwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),\n-\t\t\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t\t\t UMAG_SB_CPU_2_STATUS));\n+\t\t\t\tiwl_trans_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),\n+\t\t\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t\t\t UMAG_SB_CPU_2_STATUS));\n \t\t} else if (trans-\u003emac_cfg-\u003edevice_family \u003e=\n \t\t\t IWL_DEVICE_FAMILY_8000) {\n \t\t\tIWL_ERR(mvm,\n \t\t\t\t\"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\\n\",\n-\t\t\t\tiwl_read_prph(trans, SB_CPU_1_STATUS),\n-\t\t\t\tiwl_read_prph(trans, SB_CPU_2_STATUS));\n+\t\t\t\tiwl_trans_read_prph(trans, SB_CPU_1_STATUS),\n+\t\t\t\tiwl_trans_read_prph(trans, SB_CPU_2_STATUS));\n \t\t}\n \n \t\tiwl_mvm_print_pd_notification(mvm);\n@@ -374,15 +374,15 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm mvm,\n \t\t} else if (trans-\u003emac_cfg-\u003edevice_family \u003e=\n \t\t\t\t\tIWL_DEVICE_FAMILY_9000) {\n \t\t\tIWL_ERR(mvm, \"UMAC PC: 0x%x\\n\",\n-\t\t\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t\t\t UREG_UMAC_CURRENT_PC));\n+\t\t\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t\t\t UREG_UMAC_CURRENT_PC));\n \t\t\tIWL_ERR(mvm, \"LMAC PC: 0x%x\\n\",\n-\t\t\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t\t\t UREG_LMAC1_CURRENT_PC));\n+\t\t\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t\t\t UREG_LMAC1_CURRENT_PC));\n \t\t\tif (iwl_mvm_is_cdb_supported(mvm))\n \t\t\t\tIWL_ERR(mvm, \"LMAC2 PC: 0x%x\\n\",\n-\t\t\t\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t\t\tUREG_LMAC2_CURRENT_PC));\n+\t\t\t\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t\t\t\t UREG_LMAC2_CURRENT_PC));\n \t\t}\n \n \t\tif (ret == -ETIMEDOUT \u0026\u0026 !mvm-\u003efw_product_reset)\n@@ -616,7 +616,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm mvm)\n \tmvm-\u003erfkill_safe_init_done = false;\n \n \tif (mvm-\u003etrans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210) {\n-\t\tsb_cfg = iwl_read_umac_prph(mvm-\u003etrans, SB_MODIFY_CFG_FLAG);\n+\t\tsb_cfg = iwl_trans_read_umac_prph(mvm-\u003etrans, SB_MODIFY_CFG_FLAG);\n \t\t/* if needed, we'll reset this on our way out later /\n \t\tmvm-\u003efw_product_reset = sb_cfg == SB_CFG_RESIDES_IN_ROM;\n \t\tif (mvm-\u003efw_product_reset \u0026\u0026 iwl_mei_pldr_req())\n@@ -640,8 +640,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm mvm)\n \t\t/* if we needed reset then fail here, but notify and remove /\n \t\tif (mvm-\u003efw_product_reset) {\n \t\t\tiwl_mei_alive_notif(false);\n-\t\t\tiwl_trans_pcie_reset(mvm-\u003etrans,\n-\t\t\t\t\t IWL_RESET_MODE_RESCAN);\n+\t\t\tiwl_trans_reset(mvm-\u003etrans, IWL_RESET_MODE_RESCAN);\n \t\t}\n \n \t\tgoto error;\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/led.c b/drivers/net/wireless/intel/iwlwifi/mvm/led.c\nindex c3cc1ea3ccc93..ac238c9638559 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/led.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/led.c\n@@ -1,10 +1,10 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /\n- * Copyright (C) 2012-2014, 2018-2019, 2025 Intel Corporation\n+ * Copyright (C) 2012-2014, 2018-2019, 2025-2026 Intel Corporation\n * Copyright (C) 2017 Intel Deutschland GmbH\n /\n #include \u003clinux/leds.h\u003e\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-csr.h\"\n #include \"mvm.h\"\n \n@@ -38,8 +38,8 @@ static void iwl_mvm_led_set(struct iwl_mvm mvm, bool on)\n \t\treturn;\n \t}\n \n-\tiwl_write32(mvm-\u003etrans, CSR_LED_REG,\n-\t\t on ? CSR_LED_REG_TURN_ON : CSR_LED_REG_TURN_OFF);\n+\tiwl_trans_write32(mvm-\u003etrans, CSR_LED_REG,\n+\t\t\t on ? CSR_LED_REG_TURN_ON : CSR_LED_REG_TURN_OFF);\n }\n \n static void iwl_led_brightness_set(struct led_classdev led_cdev,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c\nindex b2c5be22c293c..509e80fa0df5e 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c\n@@ -7,7 +7,7 @@\n #include \u003clinux/etherdevice.h\u003e\n #include \u003clinux/crc32.h\u003e\n #include \u003cnet/mac80211.h\u003e\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"fw-api.h\"\n #include \"mvm.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c\nindex a4f3d3c2bd350..daa05339e3fbf 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c\n@@ -19,7 +19,7 @@\n \n #include \"iwl-drv.h\"\n #include \"iwl-op-mode.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"mvm.h\"\n #include \"sta.h\"\n #include \"time-event.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c\nindex 93d5cab87f645..1832514573612 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c\n@@ -20,7 +20,6 @@\n #include \"iwl-phy-db.h\"\n #include \"iwl-nvm-utils.h\"\n #include \"iwl-csr.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-prph.h\"\n #include \"rs.h\"\n #include \"fw/api/scan.h\"\n@@ -138,9 +137,9 @@ static void iwl_mvm_nic_config(struct iwl_op_mode op_mode)\n \t * to lose ownership and not being able to obtain it back.\n \t /\n \tif (!mvm-\u003etrans-\u003emac_cfg-\u003ebase-\u003eapmg_not_supported)\n-\t\tiwl_set_bits_mask_prph(mvm-\u003etrans, APMG_PS_CTRL_REG,\n-\t\t\t\t APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,\n-\t\t\t\t ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);\n+\t\tiwl_trans_set_bits_mask_prph(mvm-\u003etrans, APMG_PS_CTRL_REG,\n+\t\t\t\t\t APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,\n+\t\t\t\t\t ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);\n }\n \n static void iwl_mvm_rx_monitor_notif(struct iwl_mvm mvm,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c\nindex a94eaca0b3ed5..c12eda75317d1 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c\n@@ -10,7 +10,7 @@\n \n #include \"mvm.h\"\n #include \"fw/api/scan.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-utils.h\"\n \n #define IWL_DENSE_EBS_SCAN_RATIO 5\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c b/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c\nindex a7cd2e4ba1ae9..6aac71cfccb3e 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c\n@@ -2,12 +2,12 @@\n /\n Copyright (C) 2014 Intel Mobile Communications GmbH\n * Copyright (C) 2017 Intel Deutschland GmbH\n- * Copyright (C) 2018-2020, 2022-2025 Intel Corporation\n+ * Copyright (C) 2018-2020, 2022-2026 Intel Corporation\n /\n #include \u003clinux/etherdevice.h\u003e\n #include \"mvm.h\"\n #include \"time-event.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n \n #define TU_TO_US(x) (x 1024)\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c\nindex 93b46c9e2333d..5a800d3f2a98f 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c\n@@ -12,7 +12,6 @@\n #include \"fw-api.h\"\n #include \"time-event.h\"\n #include \"mvm.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-prph.h\"\n \n /\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c\nindex 2fd4a99611450..e97ab2c9e5ba7 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c\n@@ -7,7 +7,7 @@\n #include \u003cnet/mac80211.h\u003e\n \n #include \"iwl-debug.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"mvm.h\"\n@@ -1159,7 +1159,7 @@ u32 iwl_mvm_get_systime(struct iwl_mvm mvm)\n \t mvm-\u003etrans-\u003emac_cfg-\u003ebase-\u003egp2_reg_addr)\n \t\treg_addr = mvm-\u003etrans-\u003emac_cfg-\u003ebase-\u003egp2_reg_addr;\n \n-\treturn iwl_read_prph(mvm-\u003etrans, reg_addr);\n+\treturn iwl_trans_read_prph(mvm-\u003etrans, reg_addr);\n }\n \n void iwl_mvm_get_sync_time(struct iwl_mvm mvm, int clock_type,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c\nindex c75210829ec94..0009a05511af1 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c\n@@ -7,6 +7,7 @@\n #include \"iwl-fh.h\"\n #include \"iwl-context-info-v2.h\"\n #include \"internal.h\"\n+#include \"pcie/utils.h\"\n #include \"iwl-prph.h\"\n \n static const struct dmi_system_id dmi_force_scu_active_approved_list[] = {\n@@ -314,12 +315,12 @@ void iwl_pcie_ctxt_info_v2_kick(struct iwl_trans trans)\n \tiwl_enable_fw_load_int_ctx_info(trans, trans-\u003edo_top_reset);\n \n \t/* kick FW self load /\n-\tiwl_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie-\u003ectxt_info_dma_addr);\n-\tiwl_write64(trans, CSR_IML_DATA_ADDR, trans_pcie-\u003eiml_dma_addr);\n-\tiwl_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie-\u003eiml_len);\n+\tiwl_pcie_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie-\u003ectxt_info_dma_addr);\n+\tiwl_pcie_write64(trans, CSR_IML_DATA_ADDR, trans_pcie-\u003eiml_dma_addr);\n+\tiwl_trans_pcie_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie-\u003eiml_len);\n \n-\tiwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,\n-\t\t CSR_AUTO_FUNC_BOOT_ENA);\n+\tiwl_trans_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,\n+\t\t\t CSR_AUTO_FUNC_BOOT_ENA);\n }\n \n void iwl_pcie_ctxt_info_v2_free(struct iwl_trans trans, bool alive)\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c\nindex 23ec968577bd9..bc90a2714251a 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c\n@@ -7,6 +7,7 @@\n #include \"iwl-fh.h\"\n #include \"iwl-context-info.h\"\n #include \"internal.h\"\n+#include \"utils.h\"\n #include \"iwl-prph.h\"\n \n static void _iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans trans,\n@@ -245,7 +246,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans trans,\n \t\tiwl_pcie_apply_destination(trans);\n \n \t/ kick FW self load /\n-\tiwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie-\u003ectxt_info_dma_addr);\n+\tiwl_pcie_write64(trans, CSR_CTXT_INFO_BA, trans_pcie-\u003ectxt_info_dma_addr);\n \n \t/ Context info will be released upon alive or failure to get one /\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c\nindex 905482419a9af..24012005ccb87 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c\n@@ -1252,7 +1252,7 @@ static int _iwl_pci_resume(struct device device, bool restore)\n \t\t * For older devices, just try silently to grab the NIC.\n \t\t /\n \t\tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\t\tu32 scratch = iwl_read32(trans, CSR_FUNC_SCRATCH);\n+\t\t\tu32 scratch = iwl_trans_pcie_read32(trans, CSR_FUNC_SCRATCH);\n \n \t\t\tif (!(scratch \u0026 CSR_FUNC_SCRATCH_POWER_OFF_MASK) \|\|\n \t\t\t scratch == ~0U) {\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h\nindex e6b1cb559a0a6..01bfc1492c848 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h\n@@ -18,12 +18,22 @@\n #include \"iwl-fh.h\"\n #include \"iwl-csr.h\"\n #include \"iwl-trans.h\"\n+#include \"iwl-devtrace.h\"\n #include \"iwl-debug.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-op-mode.h\"\n #include \"iwl-drv.h\"\n #include \"iwl-context-info.h\"\n \n+/ transport-specific register accessors (bus implementation) /\n+void iwl_trans_pcie_write8(struct iwl_trans trans, u32 ofs, u8 val);\n+void iwl_trans_pcie_write32(struct iwl_trans trans, u32 ofs, u32 val);\n+u32 iwl_trans_pcie_read32(struct iwl_trans trans, u32 ofs);\n+u32 iwl_trans_pcie_read_prph(struct iwl_trans trans, u32 reg);\n+void iwl_pcie_write_prph_no_grab(struct iwl_trans trans, u32 addr, u32 val);\n+\n+/* bus-specific transport operations table /\n+extern const struct iwl_trans_ops iwl_trans_pcie_ops;\n+\n /\n * RX related structures and functions\n /\n@@ -593,7 +603,7 @@ static inline void iwl_pcie_clear_irq(struct iwl_trans trans, int queue)\n \t * write 1 clear (W1C) register, meaning that it's being clear\n \t * by writing 1 to the bit.\n \t /\n-\tiwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));\n }\n \n static inline struct iwl_trans \n@@ -889,18 +899,18 @@ static inline void _iwl_disable_interrupts(struct iwl_trans trans)\n \tclear_bit(STATUS_INT_ENABLED, \u0026trans-\u003estatus);\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\t/ disable interrupts from uCode/NIC to host /\n-\t\tiwl_write32(trans, CSR_INT_MASK, 0x00000000);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, 0x00000000);\n \n \t\t/ acknowledge/clear/reset any interrupts still pending\n \t\t * from uCode or flow handler (Rx/Tx DMA) /\n-\t\tiwl_write32(trans, CSR_INT, 0xffffffff);\n-\t\tiwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT, 0xffffffff);\n+\t\tiwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);\n \t} else {\n \t\t/ disable all the interrupt we might use /\n-\t\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n-\t\t\t trans_pcie-\u003efh_init_mask);\n-\t\tiwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n-\t\t\t trans_pcie-\u003ehw_init_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n+\t\t\t\t trans_pcie-\u003efh_init_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n+\t\t\t\t trans_pcie-\u003ehw_init_mask);\n \t\ttrans_pcie-\u003efh_mask = 0;\n \t\ttrans_pcie-\u003ehw_mask = 0;\n \t}\n@@ -958,7 +968,7 @@ static inline void _iwl_enable_interrupts(struct iwl_trans trans)\n \tset_bit(STATUS_INT_ENABLED, \u0026trans-\u003estatus);\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\ttrans_pcie-\u003einta_mask = CSR_INI_SET_MASK;\n-\t\tiwl_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n \t} else {\n \t\t/\n \t\t fh/hw_mask keeps all the unmasked causes.\n@@ -966,10 +976,10 @@ static inline void _iwl_enable_interrupts(struct iwl_trans trans)\n \t\t /\n \t\ttrans_pcie-\u003ehw_mask = trans_pcie-\u003ehw_init_mask;\n \t\ttrans_pcie-\u003efh_mask = trans_pcie-\u003efh_init_mask;\n-\t\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n-\t\t\t ~trans_pcie-\u003efh_mask);\n-\t\tiwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n-\t\t\t ~trans_pcie-\u003ehw_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n+\t\t\t\t ~trans_pcie-\u003efh_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n+\t\t\t\t ~trans_pcie-\u003ehw_mask);\n \t}\n }\n \n@@ -985,7 +995,7 @@ static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans trans, u32 msk)\n {\n \tstruct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \n-\tiwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);\n \ttrans_pcie-\u003ehw_mask = msk;\n }\n \n@@ -993,7 +1003,7 @@ static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans trans, u32 msk)\n {\n \tstruct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \n-\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);\n \ttrans_pcie-\u003efh_mask = msk;\n }\n \n@@ -1004,10 +1014,10 @@ static inline void iwl_enable_fw_load_int(struct iwl_trans trans)\n \tIWL_DEBUG_ISR(trans, \"Enabling FW load interrupt\\n\");\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\ttrans_pcie-\u003einta_mask = CSR_INT_BIT_FH_TX;\n-\t\tiwl_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n \t} else {\n-\t\tiwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n-\t\t\t trans_pcie-\u003ehw_init_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n+\t\t\t\t trans_pcie-\u003ehw_init_mask);\n \t\tiwl_enable_fh_int_msk_msix(trans,\n \t\t\t\t\t MSIX_FH_INT_CAUSES_D2S_CH0_NUM);\n \t}\n@@ -1034,7 +1044,7 @@ static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans trans,\n \t\telse\n \t\t\ttrans_pcie-\u003einta_mask = CSR_INT_BIT_ALIVE \|\n \t\t\t\t\t\t CSR_INT_BIT_FH_RX;\n-\t\tiwl_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n \t} else {\n \t\tu32 val = top_reset ? MSIX_HW_INT_CAUSES_REG_RESET_DONE\n \t\t\t\t : MSIX_HW_INT_CAUSES_REG_ALIVE;\n@@ -1081,10 +1091,10 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans trans)\n \tIWL_DEBUG_ISR(trans, \"Enabling rfkill interrupt\\n\");\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\ttrans_pcie-\u003einta_mask = CSR_INT_BIT_RF_KILL;\n-\t\tiwl_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n \t} else {\n-\t\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n-\t\t\t trans_pcie-\u003efh_init_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n+\t\t\t\t trans_pcie-\u003efh_init_mask);\n \t\ttrans_pcie-\u003efh_mask = 0;\n \t\tiwl_enable_hw_int_msk_msix(trans,\n \t\t\t\t\t MSIX_HW_INT_CAUSES_REG_RF_KILL);\n@@ -1096,8 +1106,8 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans trans)\n \t\t * when we power down the device we need set the bit to allow it\n \t\t * to wake up the PCI-E bus for RF-kill interrupts.\n \t\t /\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);\n \t}\n }\n \n@@ -1112,7 +1122,7 @@ static inline bool iwl_is_rfkill_set(struct iwl_trans trans)\n \tif (trans_pcie-\u003edebug_rfkill == 1)\n \t\treturn true;\n \n-\treturn !(iwl_read32(trans, CSR_GP_CNTRL) \u0026\n+\treturn !(iwl_trans_pcie_read32(trans, CSR_GP_CNTRL) \u0026\n \t\tCSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);\n }\n \n@@ -1136,16 +1146,12 @@ void iwl_trans_pcie_op_mode_enter(struct iwl_trans trans);\n int _iwl_trans_pcie_start_hw(struct iwl_trans trans);\n int iwl_trans_pcie_start_hw(struct iwl_trans trans);\n void iwl_trans_pcie_op_mode_leave(struct iwl_trans trans);\n-void iwl_trans_pcie_write8(struct iwl_trans trans, u32 ofs, u8 val);\n-void iwl_trans_pcie_write32(struct iwl_trans trans, u32 ofs, u32 val);\n-u32 iwl_trans_pcie_read32(struct iwl_trans trans, u32 ofs);\n-u32 iwl_trans_pcie_read_prph(struct iwl_trans trans, u32 reg);\n-void iwl_trans_pcie_write_prph(struct iwl_trans trans, u32 addr, u32 val);\n int iwl_trans_pcie_read_mem(struct iwl_trans trans, u32 addr,\n \t\t\t void buf, int dwords);\n int iwl_trans_pcie_read_mem_no_grab(struct iwl_trans trans, u32 addr,\n \t\t\t\t void buf, u32 dwords);\n int iwl_trans_pcie_sw_reset(struct iwl_trans trans, bool retake_ownership);\n+void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans trans);\n struct iwl_trans_dump_data \n iwl_trans_pcie_dump_data(struct iwl_trans trans, u32 dump_mask,\n \t\t\t const struct iwl_dump_sanitize_ops sanitize_ops,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c\nindex db3933b0d1979..f033bb51dcca3 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c\n@@ -9,8 +9,9 @@\n #include \u003clinux/gfp.h\u003e\n \n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"internal.h\"\n+#include \"pcie/utils.h\"\n #include \"iwl-op-mode.h\"\n #include \"iwl-context-info-v2.h\"\n #include \"fw/dbg.h\"\n@@ -146,18 +147,18 @@ int iwl_pcie_rx_stop(struct iwl_trans trans)\n {\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_AX210) {\n \t\t/ TODO: remove this once fw does it /\n-\t\tiwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0);\n-\t\treturn iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210,\n-\t\t\t\t\t RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);\n+\t\tiwl_trans_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0);\n+\t\treturn iwl_pcie_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210,\n+\t\t\t\t\t\t RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);\n \t} else if (trans-\u003emac_cfg-\u003emq_rx_supported) {\n-\t\tiwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);\n-\t\treturn iwl_poll_prph_bit(trans, RFH_GEN_STATUS,\n-\t\t\t\t\t RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);\n+\t\tiwl_trans_write_prph(trans, RFH_RXF_DMA_CFG, 0);\n+\t\treturn iwl_pcie_poll_prph_bit(trans, RFH_GEN_STATUS,\n+\t\t\t\t\t RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);\n \t} else {\n-\t\tiwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);\n-\t\treturn iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,\n-\t\t\t\t\t FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,\n-\t\t\t\t\t 1000);\n+\t\tiwl_trans_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);\n+\t\treturn iwl_pcie_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,\n+\t\t\t\t\t\tFH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,\n+\t\t\t\t\t\t1000);\n \t}\n }\n \n@@ -178,13 +179,13 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans trans,\n \t /\n \tif (!trans-\u003emac_cfg-\u003ebase-\u003eshadow_reg_enable \u0026\u0026\n \t test_bit(STATUS_TPOWER_PMI, \u0026trans-\u003estatus)) {\n-\t\treg = iwl_read32(trans, CSR_UCODE_DRV_GP1);\n+\t\treg = iwl_trans_pcie_read32(trans, CSR_UCODE_DRV_GP1);\n \n \t\tif (reg \u0026 CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {\n \t\t\tIWL_DEBUG_INFO(trans, \"Rx queue requesting wakeup, GP1 = 0x%x\\n\",\n \t\t\t\t reg);\n-\t\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \t\t\trxq-\u003eneed_update = true;\n \t\t\treturn;\n \t\t}\n@@ -192,13 +193,13 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans trans,\n \n \trxq-\u003ewrite_actual = round_down(rxq-\u003ewrite, 8);\n \tif (!trans-\u003emac_cfg-\u003emq_rx_supported)\n-\t\tiwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq-\u003ewrite_actual);\n+\t\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq-\u003ewrite_actual);\n \telse if (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_write32(trans, HBUS_TARG_WRPTR, rxq-\u003ewrite_actual \|\n-\t\t\t HBUS_TARG_WRPTR_RX_Q(rxq-\u003eid));\n+\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, rxq-\u003ewrite_actual \|\n+\t\t\t\t HBUS_TARG_WRPTR_RX_Q(rxq-\u003eid));\n \telse\n-\t\tiwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq-\u003eid),\n-\t\t\t rxq-\u003ewrite_actual);\n+\t\tiwl_trans_pcie_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq-\u003eid),\n+\t\t\t\t rxq-\u003ewrite_actual);\n }\n \n static void iwl_pcie_rxq_check_wrptr(struct iwl_trans trans)\n@@ -854,22 +855,22 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans trans, struct iwl_rxq rxq)\n \t\treturn;\n \n \t/ Stop Rx DMA /\n-\tiwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);\n+\tiwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);\n \t/ reset and flush pointers /\n-\tiwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);\n-\tiwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);\n-\tiwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);\n+\tiwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);\n+\tiwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);\n+\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);\n \n \t/ Reset driver's Rx queue write index /\n-\tiwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);\n+\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);\n \n \t/ Tell device where to find RBD circular buffer in DRAM /\n-\tiwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,\n-\t\t (u32)(rxq-\u003ebd_dma \u003e\u003e 8));\n+\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,\n+\t\t\t (u32)(rxq-\u003ebd_dma \u003e\u003e 8));\n \n \t/ Tell device where in DRAM to update its Rx status /\n-\tiwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,\n-\t\t rxq-\u003erb_stts_dma \u003e\u003e 4);\n+\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,\n+\t\t\t rxq-\u003erb_stts_dma \u003e\u003e 4);\n \n \t/ Enable Rx DMA\n \t * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in\n@@ -879,22 +880,22 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans trans, struct iwl_rxq rxq)\n \t * RB timeout 0x10\n \t * 256 RBDs\n \t /\n-\tiwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,\n-\t\t FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL \|\n-\t\t FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY \|\n-\t\t FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL \|\n-\t\t rb_size \|\n-\t\t (RX_RB_TIMEOUT \u003c\u003c FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) \|\n-\t\t (rfdnlog \u003c\u003c FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));\n+\tiwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,\n+\t\t\t FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL \|\n+\t\t\t FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY \|\n+\t\t\t FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL \|\n+\t\t\t rb_size \|\n+\t\t\t (RX_RB_TIMEOUT \u003c\u003c FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) \|\n+\t\t\t (rfdnlog \u003c\u003c FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));\n \n \tiwl_trans_release_nic_access(trans);\n \n \t/ Set interrupt coalescing timer to default (2048 usecs) /\n-\tiwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n+\tiwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n \n \t/ W/A for interrupt coalescing bug in 7260 and 3160 /\n \tif (trans-\u003ecfg-\u003ehost_interrupt_operation_mode)\n-\t\tiwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);\n+\t\tiwl_trans_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);\n }\n \n static void iwl_pcie_rx_mq_hw_init(struct iwl_trans trans)\n@@ -925,27 +926,27 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans trans)\n \t\treturn;\n \n \t/ Stop Rx DMA /\n-\tiwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);\n \t/ disable free amd used rx queue operation /\n-\tiwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);\n \n \tfor (i = 0; i \u003c trans-\u003einfo.num_rxqs; i++) {\n \t\t/ Tell device where to find RBD free table in DRAM /\n-\t\tiwl_write_prph64_no_grab(trans,\n-\t\t\t\t\t RFH_Q_FRBDCB_BA_LSB(i),\n-\t\t\t\t\t trans_pcie-\u003erxq[i].bd_dma);\n+\t\tiwl_pcie_write_prph64_no_grab(trans,\n+\t\t\t\t\t RFH_Q_FRBDCB_BA_LSB(i),\n+\t\t\t\t\t trans_pcie-\u003erxq[i].bd_dma);\n \t\t/ Tell device where to find RBD used table in DRAM /\n-\t\tiwl_write_prph64_no_grab(trans,\n-\t\t\t\t\t RFH_Q_URBDCB_BA_LSB(i),\n-\t\t\t\t\t trans_pcie-\u003erxq[i].used_bd_dma);\n+\t\tiwl_pcie_write_prph64_no_grab(trans,\n+\t\t\t\t\t RFH_Q_URBDCB_BA_LSB(i),\n+\t\t\t\t\t trans_pcie-\u003erxq[i].used_bd_dma);\n \t\t/ Tell device where in DRAM to update its Rx status /\n-\t\tiwl_write_prph64_no_grab(trans,\n-\t\t\t\t\t RFH_Q_URBD_STTS_WPTR_LSB(i),\n-\t\t\t\t\t trans_pcie-\u003erxq[i].rb_stts_dma);\n+\t\tiwl_pcie_write_prph64_no_grab(trans,\n+\t\t\t\t\t RFH_Q_URBD_STTS_WPTR_LSB(i),\n+\t\t\t\t\t trans_pcie-\u003erxq[i].rb_stts_dma);\n \t\t/ Reset device indice tables /\n-\t\tiwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);\n-\t\tiwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);\n-\t\tiwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);\n+\t\tiwl_pcie_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);\n+\t\tiwl_pcie_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);\n+\t\tiwl_pcie_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);\n \n \t\tenabled \|= BIT(i) \| BIT(i + 16);\n \t}\n@@ -957,32 +958,32 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans trans)\n \t * Drop frames that exceed RB size\n \t * 512 RBDs\n \t /\n-\tiwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,\n-\t\t\t RFH_DMA_EN_ENABLE_VAL \| rb_size \|\n-\t\t\t RFH_RXF_DMA_MIN_RB_4_8 \|\n-\t\t\t RFH_RXF_DMA_DROP_TOO_LARGE_MASK \|\n-\t\t\t RFH_RXF_DMA_RBDCB_SIZE_512);\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,\n+\t\t\t\t RFH_DMA_EN_ENABLE_VAL \| rb_size \|\n+\t\t\t\t RFH_RXF_DMA_MIN_RB_4_8 \|\n+\t\t\t\t RFH_RXF_DMA_DROP_TOO_LARGE_MASK \|\n+\t\t\t\t RFH_RXF_DMA_RBDCB_SIZE_512);\n \n \t/\n \t * Activate DMA snooping.\n \t * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe\n \t * Default queue is 0\n \t /\n-\tiwl_write_prph_no_grab(trans, RFH_GEN_CFG,\n-\t\t\t RFH_GEN_CFG_RFH_DMA_SNOOP \|\n-\t\t\t RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) \|\n-\t\t\t RFH_GEN_CFG_SERVICE_DMA_SNOOP \|\n-\t\t\t RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,\n-\t\t\t\t\t trans-\u003emac_cfg-\u003eintegrated ?\n-\t\t\t\t\t RFH_GEN_CFG_RB_CHUNK_SIZE_64 :\n-\t\t\t\t\t RFH_GEN_CFG_RB_CHUNK_SIZE_128));\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_GEN_CFG,\n+\t\t\t\t RFH_GEN_CFG_RFH_DMA_SNOOP \|\n+\t\t\t\t RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) \|\n+\t\t\t\t RFH_GEN_CFG_SERVICE_DMA_SNOOP \|\n+\t\t\t\t RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,\n+\t\t\t\t\t\t trans-\u003emac_cfg-\u003eintegrated ?\n+\t\t\t\t\t\t RFH_GEN_CFG_RB_CHUNK_SIZE_64 :\n+\t\t\t\t\t\t RFH_GEN_CFG_RB_CHUNK_SIZE_128));\n \t/ Enable the relevant rx queues /\n-\tiwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);\n \n \tiwl_trans_release_nic_access(trans);\n \n \t/ Set interrupt coalescing timer to default (2048 usecs) /\n-\tiwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n+\tiwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n }\n \n void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq rxq)\n@@ -1189,7 +1190,7 @@ int iwl_pcie_rx_init(struct iwl_trans trans)\n int iwl_pcie_gen2_rx_init(struct iwl_trans trans)\n {\n \t/* Set interrupt coalescing timer to default (2048 usecs) /\n-\tiwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n+\tiwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n \n \t/\n \t * We don't configure the RFH.\n@@ -1691,9 +1692,9 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans trans)\n \t/ W/A for WiFi/WiMAX coex and WiMAX own the RF /\n \tif (trans-\u003ecfg-\u003einternal_wimax_coex \u0026\u0026\n \t !trans-\u003emac_cfg-\u003ebase-\u003eapmg_not_supported \u0026\u0026\n-\t (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) \u0026\n+\t (!(iwl_trans_read_prph(trans, APMG_CLK_CTRL_REG) \u0026\n \t\t\t APMS_CLK_VAL_MRB_FUNC_MODE) \|\|\n-\t (iwl_read_prph(trans, APMG_PS_CTRL_REG) \u0026\n+\t (iwl_trans_read_prph(trans, APMG_PS_CTRL_REG) \u0026\n \t\t\t APMG_PS_CTRL_VAL_RESET_REQ))) {\n \t\tclear_bit(STATUS_SYNC_HCMD_ACTIVE, \u0026trans-\u003estatus);\n \t\tiwl_op_mode_wimax_active(trans-\u003eop_mode);\n@@ -1708,7 +1709,7 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans trans)\n \t}\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_SC) {\n-\t\tu32 val = iwl_read32(trans, CSR_IPC_STATE);\n+\t\tu32 val = iwl_trans_pcie_read32(trans, CSR_IPC_STATE);\n \n \t\tif (val \u0026 CSR_IPC_STATE_TOP_RESET_REQ) {\n \t\t\tIWL_ERR(trans, \"FW requested TOP reset for FSEQ\\n\");\n@@ -1733,7 +1734,7 @@ static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans trans)\n \ttrace_iwlwifi_dev_irq(trans-\u003edev);\n \n \t/ Discover which interrupts are active/pending /\n-\tinta = iwl_read32(trans, CSR_INT);\n+\tinta = iwl_trans_pcie_read32(trans, CSR_INT);\n \n \t/ the thread will service interrupts and re-enable them /\n \treturn inta;\n@@ -1850,7 +1851,7 @@ static void iwl_trans_pcie_handle_reset_interrupt(struct iwl_trans trans)\n \tu32 state;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_SC) {\n-\t\tu32 val = iwl_read32(trans, CSR_IPC_STATE);\n+\t\tu32 val = iwl_trans_pcie_read32(trans, CSR_IPC_STATE);\n \n \t\tstate = u32_get_bits(val, CSR_IPC_STATE_RESET);\n \t\tIWL_DEBUG_ISR(trans, \"IPC state = 0x%x/%d\\n\", val, state);\n@@ -1922,8 +1923,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id)\n \t\tIWL_DEBUG_ISR(trans,\n \t\t\t \"ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\\n\",\n \t\t\t inta, trans_pcie-\u003einta_mask,\n-\t\t\t iwl_read32(trans, CSR_INT_MASK),\n-\t\t\t iwl_read32(trans, CSR_FH_INT_STATUS));\n+\t\t\t iwl_trans_pcie_read32(trans, CSR_INT_MASK),\n+\t\t\t iwl_trans_pcie_read32(trans, CSR_FH_INT_STATUS));\n \t\tif (inta \u0026 (~trans_pcie-\u003einta_mask))\n \t\t\tIWL_DEBUG_ISR(trans,\n \t\t\t\t \"We got a masked interrupt (0x%08x)\\n\",\n@@ -1971,11 +1972,11 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id)\n \t * hardware bugs here by ACKing all the possible interrupts so that\n \t * interrupt coalescing can still be achieved.\n \t /\n-\tiwl_write32(trans, CSR_INT, inta \| ~trans_pcie-\u003einta_mask);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, inta \| ~trans_pcie-\u003einta_mask);\n \n \tif (iwl_have_debug_level(IWL_DL_ISR))\n \t\tIWL_DEBUG_ISR(trans, \"inta 0x%08x, enabled 0x%08x\\n\",\n-\t\t\t inta, iwl_read32(trans, CSR_INT_MASK));\n+\t\t\t inta, iwl_trans_pcie_read32(trans, CSR_INT_MASK));\n \n \tspin_unlock_bh(\u0026trans_pcie-\u003eirq_lock);\n \n@@ -2070,13 +2071,13 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id)\n \t\tIWL_DEBUG_ISR(trans, \"Rx interrupt\\n\");\n \t\tif (inta \u0026 (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX)) {\n \t\t\thandled \|= (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX);\n-\t\t\tiwl_write32(trans, CSR_FH_INT_STATUS,\n-\t\t\t\t\tCSR_FH_INT_RX_MASK);\n+\t\t\tiwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS,\n+\t\t\t\t\t CSR_FH_INT_RX_MASK);\n \t\t}\n \t\tif (inta \u0026 CSR_INT_BIT_RX_PERIODIC) {\n \t\t\thandled \|= CSR_INT_BIT_RX_PERIODIC;\n-\t\t\tiwl_write32(trans,\n-\t\t\t\tCSR_INT, CSR_INT_BIT_RX_PERIODIC);\n+\t\t\tiwl_trans_pcie_write32(trans,\n+\t\t\t\t\t CSR_INT, CSR_INT_BIT_RX_PERIODIC);\n \t\t}\n \t\t/* Sending RX interrupt require many steps to be done in the\n \t\t * device:\n@@ -2090,8 +2091,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id)\n \t\t /\n \n \t\t/* Disable periodic interrupt; we use it as just a one-shot. /\n-\t\tiwl_write8(trans, CSR_INT_PERIODIC_REG,\n-\t\t\t CSR_INT_PERIODIC_DIS);\n+\t\tiwl_trans_pcie_write8(trans, CSR_INT_PERIODIC_REG,\n+\t\t\t\t CSR_INT_PERIODIC_DIS);\n \n \t\t/\n \t\t * Enable periodic interrupt in 8 msec only if we received\n@@ -2101,8 +2102,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id)\n \t\t to extend the periodic interrupt; one-shot is enough.\n \t\t /\n \t\tif (inta \u0026 (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX))\n-\t\t\tiwl_write8(trans, CSR_INT_PERIODIC_REG,\n-\t\t\t\t CSR_INT_PERIODIC_ENA);\n+\t\t\tiwl_trans_pcie_write8(trans, CSR_INT_PERIODIC_REG,\n+\t\t\t\t\t CSR_INT_PERIODIC_ENA);\n \n \t\tisr_stats-\u003erx++;\n \n@@ -2116,7 +2117,7 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id)\n \n \t/* This \"Tx\" DMA channel is used only for loading uCode /\n \tif (inta \u0026 CSR_INT_BIT_FH_TX) {\n-\t\tiwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);\n+\t\tiwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);\n \t\tIWL_DEBUG_ISR(trans, \"uCode load interrupt\\n\");\n \t\tisr_stats-\u003etx++;\n \t\thandled \|= CSR_INT_BIT_FH_TX;\n@@ -2230,10 +2231,10 @@ void iwl_pcie_reset_ict(struct iwl_trans trans)\n \n \tIWL_DEBUG_ISR(trans, \"CSR_DRAM_INT_TBL_REG =0x%x\\n\", val);\n \n-\tiwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);\n+\tiwl_trans_pcie_write32(trans, CSR_DRAM_INT_TBL_REG, val);\n \ttrans_pcie-\u003euse_ict = true;\n \ttrans_pcie-\u003eict_index = 0;\n-\tiwl_write32(trans, CSR_INT, trans_pcie-\u003einta_mask);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, trans_pcie-\u003einta_mask);\n \t_iwl_enable_interrupts(trans);\n \tspin_unlock_bh(\u0026trans_pcie-\u003eirq_lock);\n }\n@@ -2260,7 +2261,7 @@ irqreturn_t iwl_pcie_isr(int irq, void data)\n \t If we have something to service, the tasklet will re-enable ints.\n \t * If we don't have something, we'll re-enable before leaving here.\n \t /\n-\tiwl_write32(trans, CSR_INT_MASK, 0x00000000);\n+\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, 0x00000000);\n \n \treturn IRQ_WAKE_THREAD;\n }\n@@ -2290,13 +2291,13 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void dev_id)\n \tlock_map_acquire(\u0026trans-\u003esync_cmd_lockdep_map);\n \n \tspin_lock_bh(\u0026trans_pcie-\u003eirq_lock);\n-\tinta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);\n-\tinta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);\n+\tinta_fh = iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);\n+\tinta_hw = iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);\n \t/\n \t Clear causes registers to avoid being handling the same cause.\n \t /\n-\tiwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh \u0026 inta_fh_msk);\n-\tiwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh \u0026 inta_fh_msk);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);\n \tspin_unlock_bh(\u0026trans_pcie-\u003eirq_lock);\n \n \ttrace_iwlwifi_dev_irq_msix(trans-\u003edev, entry, true, inta_fh, inta_hw);\n@@ -2311,7 +2312,7 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void dev_id)\n \t\tIWL_DEBUG_ISR(trans,\n \t\t\t \"ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\\n\",\n \t\t\t entry-\u003eentry, inta_fh, trans_pcie-\u003efh_mask,\n-\t\t\t iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));\n+\t\t\t iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_MASK_AD));\n \t\tif (inta_fh \u0026 ~trans_pcie-\u003efh_mask)\n \t\t\tIWL_DEBUG_ISR(trans,\n \t\t\t\t \"We got a masked interrupt (0x%08x)\\n\",\n@@ -2413,7 +2414,7 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void dev_id)\n \t\tIWL_DEBUG_ISR(trans,\n \t\t\t \"ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\\n\",\n \t\t\t entry-\u003eentry, inta_hw, trans_pcie-\u003ehw_mask,\n-\t\t\t iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));\n+\t\t\t iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_MASK_AD));\n \t\tif (inta_hw \u0026 ~trans_pcie-\u003ehw_mask)\n \t\t\tIWL_DEBUG_ISR(trans,\n \t\t\t\t \"We got a masked interrupt 0x%08x\\n\",\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c\nindex 39dd963920b31..dce6043fe9627 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c\n@@ -32,18 +32,18 @@ int iwl_pcie_gen2_apm_init(struct iwl_trans trans)\n \t * Disable L0s without affecting L1;\n \t * don't wait for ICH L0s (ICH bug W/A)\n \t /\n-\tiwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n-\t\t CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);\n+\tiwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n+\t\t\t CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);\n \n \t/ Set FH wait threshold to maximum (HW error during stress W/A) /\n-\tiwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);\n+\tiwl_trans_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);\n \n \t/\n \t * Enable HAP INTA (interrupt from management bus) to\n \t * wake device's PCI Express link L1a -\u003e L0s\n \t /\n-\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t CSR_HW_IF_CONFIG_REG_HAP_WAKE);\n+\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t CSR_HW_IF_CONFIG_REG_HAP_WAKE);\n \n \tiwl_pcie_apm_config(trans);\n \n@@ -65,14 +65,14 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans trans, bool op_mode_leave)\n \t\t\tiwl_pcie_gen2_apm_init(trans);\n \n \t\t/* inform ME that we are leaving /\n-\t\tiwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME \|\n-\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);\n+\t\tiwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME \|\n+\t\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);\n \t\tmdelay(1);\n-\t\tiwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\tiwl_trans_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n \t\tmdelay(5);\n \t}\n \n@@ -88,11 +88,11 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans trans, bool op_mode_leave)\n \t * D0A* (powered-up Active) --\u003e D0U* (Uninitialized) state.\n \t /\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n \telse\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n }\n \n static void\n@@ -105,14 +105,14 @@ _iwl_trans_pcie_fw_reset_handshake(struct iwl_trans trans,\n \ttrans_pcie-\u003efw_reset_state = FW_RESET_REQUESTED;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_AX210)\n-\t\tiwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,\n-\t\t\t\t UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,\n+\t\t\t\t\t UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);\n \telse if (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210)\n-\t\tiwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n-\t\t\t\t UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n+\t\t\t\t\t UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);\n \telse\n-\t\tiwl_write32(trans, CSR_DOORBELL_VECTOR,\n-\t\t\t UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);\n+\t\tiwl_trans_pcie_write32(trans, CSR_DOORBELL_VECTOR,\n+\t\t\t\t UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);\n \n \t/* wait 200ms /\n \tret = wait_event_timeout(trans_pcie-\u003efw_reset_waitq,\n@@ -123,11 +123,11 @@ _iwl_trans_pcie_fw_reset_handshake(struct iwl_trans trans,\n \t\tu32 inta_hw;\n \n \t\tif (trans_pcie-\u003emsix_enabled) {\n-\t\t\tinta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);\n+\t\t\tinta_hw = iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);\n \t\t\treset_done =\n \t\t\t\tinta_hw \u0026 MSIX_HW_INT_CAUSES_REG_RESET_DONE;\n \t\t} else {\n-\t\t\tinta_hw = iwl_read32(trans, CSR_INT);\n+\t\t\tinta_hw = iwl_trans_pcie_read32(trans, CSR_INT);\n \t\t\treset_done = inta_hw \u0026 CSR_INT_BIT_RESET_DONE;\n \t\t}\n \n@@ -281,7 +281,7 @@ static int iwl_pcie_gen2_nic_init(struct iwl_trans trans)\n \t\treturn -ENOMEM;\n \n \t/ enable shadow regs in HW /\n-\tiwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);\n+\tiwl_trans_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);\n \tIWL_DEBUG_INFO(trans, \"Enabling shadow registers in device\\n\");\n \n \treturn 0;\n@@ -342,7 +342,7 @@ static void iwl_pcie_get_rf_name(struct iwl_trans trans)\n \tcase CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):\n \tcase CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):\n \tcase CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):\n-\t\tversion = iwl_read_prph(trans, CNVI_MBOX_C);\n+\t\tversion = iwl_trans_read_prph(trans, CNVI_MBOX_C);\n \t\tswitch (version) {\n \t\tcase 0x20000:\n \t\t\tpos += scnprintf(buf + pos, buflen - pos, \" B3\");\n@@ -410,7 +410,7 @@ void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans trans)\n \n \tstep_reg = trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_SC ?\n \t\t CNVI_PMU_STEP_FLOW_SC : CNVI_PMU_STEP_FLOW_BZ;\n-\ttrans-\u003estep_urm = !!(iwl_read_prph(trans, step_reg) \u0026\n+\ttrans-\u003estep_urm = !!(iwl_trans_read_prph(trans, step_reg) \u0026\n \t\t\t CNVI_PMU_STEP_FLOW_FORCE_URM);\n }\n \n@@ -434,21 +434,21 @@ static bool iwl_pcie_set_ltr(struct iwl_trans trans)\n \tif ((trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210 \|\|\n \t trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_22000) \u0026\u0026\n \t !trans-\u003emac_cfg-\u003eintegrated) {\n-\t\tiwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);\n+\t\tiwl_trans_pcie_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);\n \t\treturn true;\n \t}\n \n \tif (trans-\u003emac_cfg-\u003eintegrated \u0026\u0026\n \t trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_22000) {\n-\t\tiwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);\n-\t\tiwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);\n+\t\tiwl_trans_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);\n+\t\tiwl_trans_write_prph(trans, HPM_UMAC_LTR, ltr_val);\n \t\treturn true;\n \t}\n \n \tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210) {\n \t\t/* First clear the interrupt, just in case /\n-\t\tiwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,\n-\t\t\t MSIX_HW_INT_CAUSES_REG_IML);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,\n+\t\t\t\t MSIX_HW_INT_CAUSES_REG_IML);\n \t\t/ In this case, unfortunately the same ROM bug exists in the\n \t\t * device (not setting LTR correctly), but we don't have control\n \t\t * over the settings from the host due to some hardware security\n@@ -475,18 +475,18 @@ static void iwl_pcie_spin_for_iml(struct iwl_trans trans)\n \tif (WARN_ON(!trans_pcie-\u003eiml))\n \t\treturn;\n \n-\tvalue = iwl_read32(trans, CSR_LTR_LAST_MSG);\n+\tvalue = iwl_trans_pcie_read32(trans, CSR_LTR_LAST_MSG);\n \tIWL_DEBUG_INFO(trans, \"Polling for IML load - CSR_LTR_LAST_MSG=0x%x\\n\",\n \t\t value);\n \n \twhile (time_before(jiffies, end_time)) {\n-\t\tif (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) \u0026\n+\t\tif (iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) \u0026\n \t\t\t\tMSIX_HW_INT_CAUSES_REG_IML) {\n \t\t\tirq = true;\n \t\t\tbreak;\n \t\t}\n \t\t/ Keep the CPU and device busy. /\n-\t\tvalue = iwl_read32(trans, CSR_LTR_LAST_MSG);\n+\t\tvalue = iwl_trans_pcie_read32(trans, CSR_LTR_LAST_MSG);\n \t\tloops++;\n \t}\n \n@@ -522,7 +522,7 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans trans,\n \n \tiwl_enable_rfkill_int(trans);\n \n-\tiwl_write32(trans, CSR_INT, 0xFFFFFFFF);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);\n \n \t/\n \t We enabled the RF-Kill interrupt and the handler may very\n@@ -550,12 +550,12 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans trans,\n \t}\n \n \t/ make sure rfkill handshake bits are cleared /\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n \n \t/ clear (again), then enable host interrupts /\n-\tiwl_write32(trans, CSR_INT, 0xFFFFFFFF);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);\n \n \tret = iwl_pcie_gen2_nic_init(trans);\n \tif (ret) {\n@@ -591,14 +591,14 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans trans,\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n \t\tIWL_DEBUG_POWER(trans, \"function scratch register value is 0x%08x\\n\",\n-\t\t\t\tiwl_read32(trans, CSR_FUNC_SCRATCH));\n-\t\tiwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_ROM_START);\n+\t\t\t\tiwl_trans_pcie_read32(trans, CSR_FUNC_SCRATCH));\n+\t\tiwl_trans_pcie_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_ROM_START);\n \t} else if (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_AX210) {\n-\t\tiwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);\n \t} else {\n-\t\tiwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);\n+\t\tiwl_trans_write_prph(trans, UREG_CPU_INIT_RUN, 1);\n \t}\n \n \tif (keep_ram_busy)\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c\nindex bda069a6f7ebf..eda88940dd074 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c\n@@ -44,10 +44,10 @@ static void iwl_dump_host_monitor_block(struct iwl_trans trans,\n \tint i;\n \n \tIWL_ERR(trans, \"Host monitor block 0x%x vector 0x%x\\n\", block, vec);\n-\tiwl_write32(trans, CSR_MONITOR_CFG_REG, (block \u003c\u003c 8) \| vec);\n+\tiwl_trans_pcie_write32(trans, CSR_MONITOR_CFG_REG, (block \u003c\u003c 8) \| vec);\n \tfor (i = 0; i \u003c iter; i++)\n \t\tIWL_ERR(trans, \" value [iter %d]: 0x%08x\\n\",\n-\t\t\ti, iwl_read32(trans, CSR_MONITOR_STATUS_REG));\n+\t\t\ti, iwl_trans_pcie_read32(trans, CSR_MONITOR_STATUS_REG));\n }\n \n static void iwl_pcie_dump_host_monitor(struct iwl_trans trans)\n@@ -56,7 +56,7 @@ static void iwl_pcie_dump_host_monitor(struct iwl_trans trans)\n \tcase IWL_DEVICE_FAMILY_22000:\n \tcase IWL_DEVICE_FAMILY_AX210:\n \t\tIWL_ERR(trans, \"CSR_RESET = 0x%x\\n\",\n-\t\t\tiwl_read32(trans, CSR_RESET));\n+\t\t\tiwl_trans_pcie_read32(trans, CSR_RESET));\n \t\tiwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,\n \t\t\t\t\t IWL_HOST_MON_BLOCK_PEMON_VEC0, 15);\n \t\tiwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,\n@@ -79,12 +79,12 @@ int iwl_trans_pcie_sw_reset(struct iwl_trans trans, bool retake_ownership)\n {\n \t/* Reset entire device - do controller reset (results in SHRD_HW_RST) /\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_SW_RESET);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_SW_RESET);\n \t\tusleep_range(10000, 20000);\n \t} else {\n-\t\tiwl_set_bit(trans, CSR_RESET,\n-\t\t\t CSR_RESET_REG_FLAG_SW_RESET);\n+\t\tiwl_trans_set_bit(trans, CSR_RESET,\n+\t\t\t\t CSR_RESET_REG_FLAG_SW_RESET);\n \t\tusleep_range(5000, 6000);\n \t}\n \n@@ -170,16 +170,16 @@ void iwl_pcie_alloc_fw_monitor(struct iwl_trans trans, u8 max_power)\n \n static u32 iwl_trans_pcie_read_shr(struct iwl_trans trans, u32 reg)\n {\n-\tiwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,\n-\t\t ((reg \u0026 0x0000ffff) \| (2 \u003c\u003c 28)));\n-\treturn iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);\n+\tiwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,\n+\t\t\t ((reg \u0026 0x0000ffff) \| (2 \u003c\u003c 28)));\n+\treturn iwl_trans_pcie_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);\n }\n \n static void iwl_trans_pcie_write_shr(struct iwl_trans trans, u32 reg, u32 val)\n {\n-\tiwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);\n-\tiwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,\n-\t\t ((reg \u0026 0x0000ffff) \| (3 \u003c\u003c 28)));\n+\tiwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);\n+\tiwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,\n+\t\t\t ((reg \u0026 0x0000ffff) \| (3 \u003c\u003c 28)));\n }\n \n static void iwl_pcie_set_pwr(struct iwl_trans trans, bool vaux)\n@@ -188,13 +188,13 @@ static void iwl_pcie_set_pwr(struct iwl_trans trans, bool vaux)\n \t\treturn;\n \n \tif (vaux \u0026\u0026 pci_pme_capable(to_pci_dev(trans-\u003edev), PCI_D3cold))\n-\t\tiwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,\n-\t\t\t\t APMG_PS_CTRL_VAL_PWR_SRC_VAUX,\n-\t\t\t\t ~APMG_PS_CTRL_MSK_PWR_SRC);\n+\t\tiwl_trans_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,\n+\t\t\t\t\t APMG_PS_CTRL_VAL_PWR_SRC_VAUX,\n+\t\t\t\t\t ~APMG_PS_CTRL_MSK_PWR_SRC);\n \telse\n-\t\tiwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,\n-\t\t\t\t APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,\n-\t\t\t\t ~APMG_PS_CTRL_MSK_PWR_SRC);\n+\t\tiwl_trans_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,\n+\t\t\t\t\t APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,\n+\t\t\t\t\t ~APMG_PS_CTRL_MSK_PWR_SRC);\n }\n \n /* PCI registers /\n@@ -211,7 +211,7 @@ void iwl_pcie_apm_config(struct iwl_trans trans)\n \t * and in newer hardware they are not officially supported at\n \t * all, so we must always set the L0S_DISABLED bit.\n \t /\n-\tiwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);\n+\tiwl_trans_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);\n \n \tpcie_capability_read_word(trans_pcie-\u003epci_dev, PCI_EXP_LNKCTL, \u0026lctl);\n \ttrans_pcie-\u003epm_support = !(lctl \u0026 PCI_EXP_LNKCTL_ASPM_L0S);\n@@ -241,31 +241,31 @@ static int iwl_pcie_apm_init(struct iwl_trans trans)\n \n \t/* Disable L0S exit timer (platform NMI Work/Around) /\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_8000)\n-\t\tiwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n-\t\t\t CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);\n+\t\tiwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n+\t\t\t\t CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);\n \n \t/\n \t * Disable L0s without affecting L1;\n \t * don't wait for ICH L0s (ICH bug W/A)\n \t /\n-\tiwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n-\t\t CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);\n+\tiwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n+\t\t\t CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);\n \n \t/ Set FH wait threshold to maximum (HW error during stress W/A) /\n-\tiwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);\n+\tiwl_trans_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);\n \n \t/\n \t * Enable HAP INTA (interrupt from management bus) to\n \t * wake device's PCI Express link L1a -\u003e L0s\n \t /\n-\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t CSR_HW_IF_CONFIG_REG_HAP_WAKE);\n+\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t CSR_HW_IF_CONFIG_REG_HAP_WAKE);\n \n \tiwl_pcie_apm_config(trans);\n \n \t/ Configure analog phase-lock-loop before activating to D0A /\n \tif (trans-\u003emac_cfg-\u003ebase-\u003epll_cfg)\n-\t\tiwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);\n+\t\tiwl_trans_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);\n \n \tret = iwl_trans_activate_nic(trans);\n \tif (ret)\n@@ -286,11 +286,11 @@ static int iwl_pcie_apm_init(struct iwl_trans trans)\n \t\t * just to discard the value. But that's the way the hardware\n \t\t * seems to like it.\n \t\t /\n-\t\tiwl_read_prph(trans, OSC_CLK);\n-\t\tiwl_read_prph(trans, OSC_CLK);\n-\t\tiwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);\n-\t\tiwl_read_prph(trans, OSC_CLK);\n-\t\tiwl_read_prph(trans, OSC_CLK);\n+\t\tiwl_trans_read_prph(trans, OSC_CLK);\n+\t\tiwl_trans_read_prph(trans, OSC_CLK);\n+\t\tiwl_trans_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);\n+\t\tiwl_trans_read_prph(trans, OSC_CLK);\n+\t\tiwl_trans_read_prph(trans, OSC_CLK);\n \t}\n \n \t/\n@@ -301,17 +301,17 @@ static int iwl_pcie_apm_init(struct iwl_trans trans)\n \t bits already set by default in \"CLK_CTRL_REG\" after reset.\n \t /\n \tif (!trans-\u003emac_cfg-\u003ebase-\u003eapmg_not_supported) {\n-\t\tiwl_write_prph(trans, APMG_CLK_EN_REG,\n-\t\t\t APMG_CLK_VAL_DMA_CLK_RQT);\n+\t\tiwl_trans_write_prph(trans, APMG_CLK_EN_REG,\n+\t\t\t\t APMG_CLK_VAL_DMA_CLK_RQT);\n \t\tudelay(20);\n \n \t\t/ Disable L1-Active /\n-\t\tiwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,\n-\t\t\t\t APMG_PCIDEV_STT_VAL_L1_ACT_DIS);\n+\t\tiwl_trans_set_bits_prph(trans, APMG_PCIDEV_STT_REG,\n+\t\t\t\t\tAPMG_PCIDEV_STT_VAL_L1_ACT_DIS);\n \n \t\t/ Clear the interrupt in APMG if the NIC is in RFKILL /\n-\t\tiwl_write_prph(trans, APMG_RTC_INT_STT_REG,\n-\t\t\t APMG_RTC_INT_STT_RFKILL);\n+\t\tiwl_trans_write_prph(trans, APMG_RTC_INT_STT_REG,\n+\t\t\t\t APMG_RTC_INT_STT_RFKILL);\n \t}\n \n \tset_bit(STATUS_DEVICE_ENABLED, \u0026trans-\u003estatus);\n@@ -334,8 +334,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans trans)\n \tu32 dl_cfg_reg;\n \n \t/* Force XTAL ON /\n-\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n+\tiwl_pcie_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n \n \tret = iwl_trans_pcie_sw_reset(trans, true);\n \n@@ -344,8 +344,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans trans)\n \n \tif (WARN_ON(ret)) {\n \t\t/* Release XTAL ON request /\n-\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n+\t\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n \t\treturn;\n \t}\n \n@@ -353,8 +353,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans trans)\n \t * Clear \"disable persistence\" to avoid LP XTAL resetting when\n \t * SHRD_HW_RST is applied in S3.\n \t /\n-\tiwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,\n-\t\t\t\t APMG_PCIDEV_STT_VAL_PERSIST_DIS);\n+\tiwl_trans_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,\n+\t\t\t\t APMG_PCIDEV_STT_VAL_PERSIST_DIS);\n \n \t/\n \t * Force APMG XTAL to be active to prevent its disabling by HW\n@@ -386,22 +386,22 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans trans)\n \t Enable persistence mode to avoid LP XTAL resetting when\n \t * SHRD_HW_RST is applied in S3.\n \t /\n-\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t CSR_HW_IF_CONFIG_REG_PERSISTENCE);\n+\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t CSR_HW_IF_CONFIG_REG_PERSISTENCE);\n \n \t/\n \t * Clear \"initialization complete\" bit to move adapter from\n \t * D0A* (powered-up Active) --\u003e D0U* (Uninitialized) state.\n \t /\n-\tiwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n \n \t/ Activates XTAL resources monitor /\n-\tiwl_trans_set_bit(trans, CSR_MONITOR_CFG_REG,\n-\t\t\t CSR_MONITOR_XTAL_RESOURCES);\n+\tiwl_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,\n+\t\t\t CSR_MONITOR_XTAL_RESOURCES);\n \n \t/ Release XTAL ON request /\n-\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n+\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n \tudelay(10);\n \n \t/ Release APMG XTAL /\n@@ -417,18 +417,18 @@ void iwl_pcie_apm_stop_master(struct iwl_trans trans)\n \t/* stop device's busmaster DMA activity /\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);\n \n-\t\tret = iwl_poll_bits(trans, CSR_GP_CNTRL,\n-\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,\n-\t\t\t\t 100);\n+\t\tret = iwl_trans_poll_bits(trans, CSR_GP_CNTRL,\n+\t\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,\n+\t\t\t\t\t 100);\n \t\tusleep_range(10000, 20000);\n \t} else {\n-\t\tiwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);\n+\t\tiwl_trans_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);\n \n-\t\tret = iwl_poll_bits(trans, CSR_RESET,\n-\t\t\t\t CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);\n+\t\tret = iwl_trans_poll_bits(trans, CSR_RESET,\n+\t\t\t\t\t CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);\n \t}\n \n \tif (ret)\n@@ -447,18 +447,18 @@ static void iwl_pcie_apm_stop(struct iwl_trans trans, bool op_mode_leave)\n \n \t\t/* inform ME that we are leaving /\n \t\tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_7000)\n-\t\t\tiwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,\n-\t\t\t\t\t APMG_PCIDEV_STT_VAL_WAKE_ME);\n+\t\t\tiwl_trans_set_bits_prph(trans, APMG_PCIDEV_STT_REG,\n+\t\t\t\t\t\tAPMG_PCIDEV_STT_VAL_WAKE_ME);\n \t\telse if (trans-\u003emac_cfg-\u003edevice_family \u003e=\n \t\t\t IWL_DEVICE_FAMILY_8000) {\n-\t\t\tiwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n-\t\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME \|\n-\t\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);\n+\t\t\tiwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME \|\n+\t\t\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);\n \t\t\tmdelay(1);\n-\t\t\tiwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\t\tiwl_trans_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n \t\t}\n \t\tmdelay(5);\n \t}\n@@ -479,7 +479,7 @@ static void iwl_pcie_apm_stop(struct iwl_trans trans, bool op_mode_leave)\n \t * Clear \"initialization complete\" bit to move adapter from\n \t * D0A* (powered-up Active) --\u003e D0U* (Uninitialized) state.\n \t /\n-\tiwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n }\n \n static int iwl_pcie_nic_init(struct iwl_trans trans)\n@@ -512,7 +512,7 @@ static int iwl_pcie_nic_init(struct iwl_trans trans)\n \n \tif (trans-\u003emac_cfg-\u003ebase-\u003eshadow_reg_enable) {\n \t\t/ enable shadow regs in HW /\n-\t\tiwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);\n+\t\tiwl_trans_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);\n \t\tIWL_DEBUG_INFO(trans, \"Enabling shadow registers in device\\n\");\n \t}\n \n@@ -525,16 +525,16 @@ static int iwl_pcie_set_hw_ready(struct iwl_trans trans)\n {\n \tint ret;\n \n-\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);\n+\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);\n \n \t/* See if we got it /\n-\tret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,\n-\t\t\t HW_READY_TIMEOUT);\n+\tret = iwl_trans_poll_bits(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,\n+\t\t\t\t HW_READY_TIMEOUT);\n \n \tif (!ret)\n-\t\tiwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);\n+\t\tiwl_trans_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);\n \n \tIWL_DEBUG_INFO(trans, \"hardware%s ready\\n\", ret ? \" not\" : \"\");\n \treturn ret;\n@@ -555,16 +555,16 @@ int iwl_pcie_prepare_card_hw(struct iwl_trans trans)\n \t\treturn 0;\n \t}\n \n-\tiwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\tiwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t CSR_RESET_LINK_PWR_MGMT_DISABLED);\n \tusleep_range(1000, 2000);\n \n \tfor (iter = 0; iter \u003c 10; iter++) {\n \t\tint t = 0;\n \n \t\t/* If HW is not ready, prepare the conditions to check again /\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t CSR_HW_IF_CONFIG_REG_WAKE_ME);\n \n \t\tdo {\n \t\t\tret = iwl_pcie_set_hw_ready(trans);\n@@ -603,28 +603,28 @@ static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans trans,\n \t\t\t\t\t u32 dst_addr, dma_addr_t phy_addr,\n \t\t\t\t\t u32 byte_cnt)\n {\n-\tiwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),\n-\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);\n+\tiwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),\n+\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);\n \n-\tiwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),\n-\t\t dst_addr);\n+\tiwl_trans_pcie_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),\n+\t\t\t dst_addr);\n \n-\tiwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),\n-\t\t phy_addr \u0026 FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);\n+\tiwl_trans_pcie_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),\n+\t\t\t phy_addr \u0026 FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);\n \n-\tiwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),\n-\t\t (iwl_get_dma_hi_addr(phy_addr)\n-\t\t\t\u003c\u003c FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) \| byte_cnt);\n+\tiwl_trans_pcie_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),\n+\t\t\t (iwl_get_dma_hi_addr(phy_addr)\n+\t\t\t\t\u003c\u003c FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) \| byte_cnt);\n \n-\tiwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),\n-\t\t BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) \|\n-\t\t BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) \|\n-\t\t FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);\n+\tiwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),\n+\t\t\t BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) \|\n+\t\t\t BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) \|\n+\t\t\t FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);\n \n-\tiwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),\n-\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \|\n-\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE \|\n-\t\t FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);\n+\tiwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),\n+\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \|\n+\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE \|\n+\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);\n }\n \n static int iwl_pcie_load_firmware_chunk(struct iwl_trans trans,\n@@ -688,16 +688,16 @@ static int iwl_pcie_load_section(struct iwl_trans trans, u8 section_num,\n \t\t\textended_addr = true;\n \n \t\tif (extended_addr)\n-\t\t\tiwl_set_bits_prph(trans, LMPM_CHICK,\n-\t\t\t\t\t LMPM_CHICK_EXTENDED_ADDR_SPACE);\n+\t\t\tiwl_trans_set_bits_prph(trans, LMPM_CHICK,\n+\t\t\t\t\t\tLMPM_CHICK_EXTENDED_ADDR_SPACE);\n \n \t\tmemcpy(v_addr, (const u8 )section-\u003edata + offset, copy_size);\n \t\tret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,\n \t\t\t\t\t\t copy_size);\n \n \t\tif (extended_addr)\n-\t\t\tiwl_clear_bits_prph(trans, LMPM_CHICK,\n-\t\t\t\t\t LMPM_CHICK_EXTENDED_ADDR_SPACE);\n+\t\t\tiwl_trans_clear_bits_prph(trans, LMPM_CHICK,\n+\t\t\t\t\t\t LMPM_CHICK_EXTENDED_ADDR_SPACE);\n \n \t\tif (ret) {\n \t\t\tIWL_ERR(trans,\n@@ -751,9 +751,9 @@ static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans trans,\n \t\t\treturn ret;\n \n \t\t/* Notify ucode of loaded section number and status /\n-\t\tval = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);\n+\t\tval = iwl_pcie_read_direct32(trans, FH_UCODE_LOAD_STATUS);\n \t\tval = val \| (sec_num \u003c\u003c shift_param);\n-\t\tiwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);\n+\t\tiwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);\n \n \t\tsec_num = (sec_num \u003c\u003c 1) \| 0x1;\n \t}\n@@ -764,18 +764,18 @@ static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans trans,\n \n \tif (trans-\u003emac_cfg-\u003egen2) {\n \t\tif (cpu == 1)\n-\t\t\tiwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,\n-\t\t\t\t 0xFFFF);\n+\t\t\tiwl_trans_write_prph(trans, UREG_UCODE_LOAD_STATUS,\n+\t\t\t\t\t 0xFFFF);\n \t\telse\n-\t\t\tiwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,\n-\t\t\t\t 0xFFFFFFFF);\n+\t\t\tiwl_trans_write_prph(trans, UREG_UCODE_LOAD_STATUS,\n+\t\t\t\t\t 0xFFFFFFFF);\n \t} else {\n \t\tif (cpu == 1)\n-\t\t\tiwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,\n-\t\t\t\t\t 0xFFFF);\n+\t\t\tiwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS,\n+\t\t\t\t\t\t 0xFFFF);\n \t\telse\n-\t\t\tiwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,\n-\t\t\t\t\t 0xFFFFFFFF);\n+\t\t\tiwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS,\n+\t\t\t\t\t\t 0xFFFFFFFF);\n \t}\n \n \treturn 0;\n@@ -836,8 +836,8 @@ static void iwl_pcie_apply_destination_ini(struct iwl_trans trans)\n \t IWL_FW_INI_LOCATION_SRAM_PATH) {\n \t\tIWL_DEBUG_FW(trans, \"WRT: Applying SMEM buffer destination\\n\");\n \t\t/ set sram monitor by enabling bit 7 /\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);\n \n \t\treturn;\n \t}\n@@ -852,11 +852,11 @@ static void iwl_pcie_apply_destination_ini(struct iwl_trans trans)\n \tIWL_DEBUG_FW(trans, \"WRT: Applying DRAM destination (alloc_id=%u)\\n\",\n \t\t alloc_id);\n \n-\tiwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,\n-\t\t\t frag-\u003ephysical \u003e\u003e MON_BUFF_SHIFT_VER2);\n-\tiwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,\n-\t\t\t (frag-\u003ephysical + frag-\u003esize - 256) \u003e\u003e\n-\t\t\t MON_BUFF_SHIFT_VER2);\n+\tiwl_trans_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,\n+\t\t\t\t frag-\u003ephysical \u003e\u003e MON_BUFF_SHIFT_VER2);\n+\tiwl_trans_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,\n+\t\t\t\t (frag-\u003ephysical + frag-\u003esize - 256) \u003e\u003e\n+\t\t\t\t MON_BUFF_SHIFT_VER2);\n }\n \n void iwl_pcie_apply_destination(struct iwl_trans trans)\n@@ -884,25 +884,25 @@ void iwl_pcie_apply_destination(struct iwl_trans trans)\n \n \t\tswitch (dest-\u003ereg_ops[i].op) {\n \t\tcase CSR_ASSIGN:\n-\t\t\tiwl_write32(trans, addr, val);\n+\t\t\tiwl_trans_pcie_write32(trans, addr, val);\n \t\t\tbreak;\n \t\tcase CSR_SETBIT:\n-\t\t\tiwl_set_bit(trans, addr, BIT(val));\n+\t\t\tiwl_trans_set_bit(trans, addr, BIT(val));\n \t\t\tbreak;\n \t\tcase CSR_CLEARBIT:\n-\t\t\tiwl_clear_bit(trans, addr, BIT(val));\n+\t\t\tiwl_trans_clear_bit(trans, addr, BIT(val));\n \t\t\tbreak;\n \t\tcase PRPH_ASSIGN:\n-\t\t\tiwl_write_prph(trans, addr, val);\n+\t\t\tiwl_trans_write_prph(trans, addr, val);\n \t\t\tbreak;\n \t\tcase PRPH_SETBIT:\n-\t\t\tiwl_set_bits_prph(trans, addr, BIT(val));\n+\t\t\tiwl_trans_set_bits_prph(trans, addr, BIT(val));\n \t\t\tbreak;\n \t\tcase PRPH_CLEARBIT:\n-\t\t\tiwl_clear_bits_prph(trans, addr, BIT(val));\n+\t\t\tiwl_trans_clear_bits_prph(trans, addr, BIT(val));\n \t\t\tbreak;\n \t\tcase PRPH_BLOCKBIT:\n-\t\t\tif (iwl_read_prph(trans, addr) \u0026 BIT(val)) {\n+\t\t\tif (iwl_trans_read_prph(trans, addr) \u0026 BIT(val)) {\n \t\t\t\tIWL_ERR(trans,\n \t\t\t\t\t\"BIT(%u) in address 0x%x is 1, stopping FW configuration\\n\",\n \t\t\t\t\tval, addr);\n@@ -918,16 +918,16 @@ void iwl_pcie_apply_destination(struct iwl_trans trans)\n \n monitor:\n \tif (dest-\u003emonitor_mode == EXTERNAL_MODE \u0026\u0026 fw_mon-\u003esize) {\n-\t\tiwl_write_prph(trans, le32_to_cpu(dest-\u003ebase_reg),\n-\t\t\t fw_mon-\u003ephysical \u003e\u003e dest-\u003ebase_shift);\n+\t\tiwl_trans_write_prph(trans, le32_to_cpu(dest-\u003ebase_reg),\n+\t\t\t\t fw_mon-\u003ephysical \u003e\u003e dest-\u003ebase_shift);\n \t\tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_8000)\n-\t\t\tiwl_write_prph(trans, le32_to_cpu(dest-\u003eend_reg),\n-\t\t\t\t (fw_mon-\u003ephysical + fw_mon-\u003esize -\n-\t\t\t\t\t256) \u003e\u003e dest-\u003eend_shift);\n+\t\t\tiwl_trans_write_prph(trans, le32_to_cpu(dest-\u003eend_reg),\n+\t\t\t\t\t (fw_mon-\u003ephysical + fw_mon-\u003esize -\n+\t\t\t\t\t 256) \u003e\u003e dest-\u003eend_shift);\n \t\telse\n-\t\t\tiwl_write_prph(trans, le32_to_cpu(dest-\u003eend_reg),\n-\t\t\t\t (fw_mon-\u003ephysical + fw_mon-\u003esize) \u003e\u003e\n-\t\t\t\t dest-\u003eend_shift);\n+\t\t\tiwl_trans_write_prph(trans, le32_to_cpu(dest-\u003eend_reg),\n+\t\t\t\t\t (fw_mon-\u003ephysical + fw_mon-\u003esize) \u003e\u003e\n+\t\t\t\t\t dest-\u003eend_shift);\n \t}\n }\n \n@@ -947,9 +947,9 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans trans,\n \n \tif (image-\u003eis_dual_cpus) {\n \t\t/* set CPU2 header address /\n-\t\tiwl_write_prph(trans,\n-\t\t\t LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,\n-\t\t\t LMPM_SECURE_CPU2_HDR_MEM_SPACE);\n+\t\tiwl_trans_write_prph(trans,\n+\t\t\t\t LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,\n+\t\t\t\t LMPM_SECURE_CPU2_HDR_MEM_SPACE);\n \n \t\t/ load to FW the binary sections of CPU2 /\n \t\tret = iwl_pcie_load_cpu_sections(trans, image, 2,\n@@ -964,7 +964,7 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans trans,\n \tiwl_enable_interrupts(trans);\n \n \t/* release CPU reset /\n-\tiwl_write32(trans, CSR_RESET, 0);\n+\tiwl_trans_pcie_write32(trans, CSR_RESET, 0);\n \n \treturn 0;\n }\n@@ -982,18 +982,18 @@ static int iwl_pcie_load_given_ucode_8000(struct iwl_trans trans,\n \t\tiwl_pcie_apply_destination(trans);\n \n \tIWL_DEBUG_POWER(trans, \"Original WFPM value = 0x%08X\\n\",\n-\t\t\tiwl_read_prph(trans, WFPM_GP2));\n+\t\t\tiwl_trans_read_prph(trans, WFPM_GP2));\n \n \t/\n \t Set default value. On resume reading the values that were\n \t * zeored can provide debug data on the resume flow.\n \t * This is for debugging only and has no functional impact.\n \t /\n-\tiwl_write_prph(trans, WFPM_GP2, 0x01010101);\n+\tiwl_trans_write_prph(trans, WFPM_GP2, 0x01010101);\n \n \t/ configure the ucode to be ready to get the secured image /\n \t/ release CPU reset /\n-\tiwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);\n+\tiwl_trans_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);\n \n \t/ load to FW the binary Secured sections of CPU1 /\n \tret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,\n@@ -1079,9 +1079,9 @@ static void iwl_pcie_map_list(struct iwl_trans trans,\n \tint i;\n \n \tfor (i = 0; i \u003c arr_size; i++) {\n-\t\tiwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);\n-\t\tiwl_clear_bit(trans, causes[i].mask_reg,\n-\t\t\t BIT(causes[i].bit));\n+\t\tiwl_trans_pcie_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);\n+\t\tiwl_trans_clear_bit(trans, causes[i].mask_reg,\n+\t\t\t\t BIT(causes[i].bit));\n \t}\n }\n \n@@ -1119,19 +1119,19 @@ static void iwl_pcie_map_rx_causes(struct iwl_trans trans)\n \t /\n \tval = BIT(MSIX_FH_INT_CAUSES_Q(0));\n \tfor (idx = 1; idx \u003c trans-\u003einfo.num_rxqs; idx++) {\n-\t\tiwl_write8(trans, CSR_MSIX_RX_IVAR(idx),\n-\t\t\t MSIX_FH_INT_CAUSES_Q(idx - offset));\n+\t\tiwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(idx),\n+\t\t\t\t MSIX_FH_INT_CAUSES_Q(idx - offset));\n \t\tval \|= BIT(MSIX_FH_INT_CAUSES_Q(idx));\n \t}\n-\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);\n \n \tval = MSIX_FH_INT_CAUSES_Q(0);\n \tif (trans_pcie-\u003eshared_vec_mask \u0026 IWL_SHARED_IRQ_NON_RX)\n \t\tval \|= MSIX_NON_AUTO_CLEAR_CAUSE;\n-\tiwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);\n+\tiwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(0), val);\n \n \tif (trans_pcie-\u003eshared_vec_mask \u0026 IWL_SHARED_IRQ_FIRST_RSS)\n-\t\tiwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);\n+\t\tiwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(1), val);\n }\n \n void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie trans_pcie)\n@@ -1141,8 +1141,8 @@ void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie trans_pcie)\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\tif (trans-\u003emac_cfg-\u003emq_rx_supported \u0026\u0026\n \t\t test_bit(STATUS_DEVICE_ENABLED, \u0026trans-\u003estatus))\n-\t\t\tiwl_write_umac_prph(trans, UREG_CHICK,\n-\t\t\t\t\t UREG_CHICK_MSI_ENABLE);\n+\t\t\tiwl_trans_write_umac_prph(trans, UREG_CHICK,\n+\t\t\t\t\t\t UREG_CHICK_MSI_ENABLE);\n \t\treturn;\n \t}\n \t/\n@@ -1151,7 +1151,7 @@ void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie trans_pcie)\n \t * prph.\n \t /\n \tif (test_bit(STATUS_DEVICE_ENABLED, \u0026trans-\u003estatus))\n-\t\tiwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);\n \n \t/\n \t * Each cause from the causes list above and the RX causes is\n@@ -1174,9 +1174,9 @@ static void iwl_pcie_init_msix(struct iwl_trans_pcie trans_pcie)\n \tif (!trans_pcie-\u003emsix_enabled)\n \t\treturn;\n \n-\ttrans_pcie-\u003efh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);\n+\ttrans_pcie-\u003efh_init_mask = ~iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_MASK_AD);\n \ttrans_pcie-\u003efh_mask = trans_pcie-\u003efh_init_mask;\n-\ttrans_pcie-\u003ehw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);\n+\ttrans_pcie-\u003ehw_init_mask = ~iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_MASK_AD);\n \ttrans_pcie-\u003ehw_mask = trans_pcie-\u003ehw_init_mask;\n }\n \n@@ -1215,19 +1215,19 @@ static void _iwl_trans_pcie_stop_device(struct iwl_trans trans, bool from_irq)\n \n \t\t/* Power-down device's busmaster DMA clocks /\n \t\tif (!trans-\u003emac_cfg-\u003ebase-\u003eapmg_not_supported) {\n-\t\t\tiwl_write_prph(trans, APMG_CLK_DIS_REG,\n-\t\t\t\t APMG_CLK_VAL_DMA_CLK_RQT);\n+\t\t\tiwl_trans_write_prph(trans, APMG_CLK_DIS_REG,\n+\t\t\t\t\t APMG_CLK_VAL_DMA_CLK_RQT);\n \t\t\tudelay(5);\n \t\t}\n \t}\n \n \t/ Make sure (redundant) we've released our request to stay awake /\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n \telse\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \n \t/ Stop the device, and put it in low power state /\n \tiwl_pcie_apm_stop(trans, false);\n@@ -1288,6 +1288,10 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans,\n \tbool hw_rfkill;\n \tint ret;\n \n+\tif (trans-\u003emac_cfg-\u003egen2)\n+\t\treturn iwl_trans_pcie_gen2_start_fw(trans, fw, img,\n+\t\t\t\t\t\t run_in_rfkill);\n+\n \t/* This may fail if AMT took ownership of the device /\n \tif (iwl_pcie_prepare_card_hw(trans)) {\n \t\tIWL_WARN(trans, \"Exit HW not ready\\n\");\n@@ -1296,7 +1300,7 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans,\n \n \tiwl_enable_rfkill_int(trans);\n \n-\tiwl_write32(trans, CSR_INT, 0xFFFFFFFF);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);\n \n \t/\n \t We enabled the RF-Kill interrupt and the handler may very\n@@ -1326,12 +1330,12 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans,\n \t}\n \n \t/ make sure rfkill handshake bits are cleared /\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n \n \t/ clear (again), then enable host interrupts /\n-\tiwl_write32(trans, CSR_INT, 0xFFFFFFFF);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);\n \n \tret = iwl_pcie_nic_init(trans);\n \tif (ret) {\n@@ -1349,8 +1353,8 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans,\n \tiwl_enable_fw_load_int(trans);\n \n \t/* really make sure rfkill handshake bits are cleared /\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n \n \t/ Load the given image to the HW /\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_8000)\n@@ -1370,6 +1374,11 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans,\n \n void iwl_trans_pcie_fw_alive(struct iwl_trans trans)\n {\n+\tif (trans-\u003emac_cfg-\u003egen2) {\n+\t\tiwl_trans_pcie_gen2_fw_alive(trans);\n+\t\treturn;\n+\t}\n+\n \tiwl_pcie_reset_ict(trans);\n \tiwl_pcie_tx_start(trans);\n }\n@@ -1408,6 +1417,11 @@ void iwl_trans_pcie_stop_device(struct iwl_trans trans)\n \tstruct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \tbool was_in_rfkill;\n \n+\tif (trans-\u003emac_cfg-\u003egen2) {\n+\t\tiwl_trans_pcie_gen2_stop_device(trans);\n+\t\treturn;\n+\t}\n+\n \tiwl_op_mode_time_point(trans-\u003eop_mode,\n \t\t\t IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,\n \t\t\t NULL);\n@@ -1444,15 +1458,15 @@ static void iwl_pcie_d3_complete_suspend(struct iwl_trans trans,\n \tiwl_pcie_synchronize_irqs(trans);\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n \t} else {\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n \t}\n \n \tif (reset) {\n@@ -1478,13 +1492,13 @@ static int iwl_pcie_d3_handshake(struct iwl_trans trans, bool suspend)\n \ttrans_pcie-\u003esx_state = IWL_SX_WAITING;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210)\n-\t\tiwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n-\t\t\t\t suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :\n-\t\t\t\t\t UREG_DOORBELL_TO_ISR6_RESUME);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n+\t\t\t\t\t suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :\n+\t\t\t\t\t UREG_DOORBELL_TO_ISR6_RESUME);\n \telse\n-\t\tiwl_write32(trans, CSR_IPC_SLEEP_CONTROL,\n-\t\t\t suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :\n-\t\t\t\t CSR_IPC_SLEEP_CONTROL_RESUME);\n+\t\tiwl_trans_pcie_write32(trans, CSR_IPC_SLEEP_CONTROL,\n+\t\t\t\t suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :\n+\t\t\t\t\t\t CSR_IPC_SLEEP_CONTROL_RESUME);\n \n \tret = wait_event_timeout(trans_pcie-\u003esx_waitq,\n \t\t\t\t trans_pcie-\u003esx_state != IWL_SX_WAITING,\n@@ -1515,8 +1529,8 @@ int iwl_trans_pcie_d3_suspend(struct iwl_trans trans, bool reset)\n \n \tif (!reset)\n \t\t/* Enable persistence mode to avoid reset /\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t CSR_HW_IF_CONFIG_REG_PERSISTENCE);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t CSR_HW_IF_CONFIG_REG_PERSISTENCE);\n \n \tret = iwl_pcie_d3_handshake(trans, true);\n \tif (ret)\n@@ -1535,11 +1549,11 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans trans,\n \tint ret;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n \telse\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \n \tret = iwl_trans_activate_nic(trans);\n \tif (ret) {\n@@ -1563,8 +1577,8 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans trans,\n \tiwl_pcie_set_pwr(trans, false);\n \n \tif (!reset) {\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \t} else {\n \t\tiwl_trans_pcie_tx_reset(trans);\n \n@@ -1577,9 +1591,9 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans trans,\n \t}\n \n \tIWL_DEBUG_POWER(trans, \"WFPM value upon resume = 0x%08X\\n\",\n-\t\t\tiwl_read_umac_prph(trans, WFPM_GP2));\n+\t\t\tiwl_trans_read_umac_prph(trans, WFPM_GP2));\n \n-\tval = iwl_read32(trans, CSR_RESET);\n+\tval = iwl_trans_pcie_read32(trans, CSR_RESET);\n \tif (val \u0026 CSR_RESET_REG_FLAG_NEVO_RESET) {\n \t\tIWL_INFO(trans, \"Device was reset during suspend\\n\");\n \t\ttrans-\u003estate = IWL_TRANS_NO_FW;\n@@ -1745,17 +1759,17 @@ static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans trans)\n \t\treturn 0;\n \t}\n \n-\thpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);\n+\thpm = iwl_trans_read_umac_prph_no_grab(trans, HPM_DEBUG);\n \tif (!iwl_trans_is_hw_error_value(hpm) \u0026\u0026 (hpm \u0026 PERSISTENCE_BIT)) {\n-\t\tu32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);\n+\t\tu32 wprot_val = iwl_trans_read_umac_prph_no_grab(trans, wprot);\n \n \t\tif (wprot_val \u0026 PREG_WFPM_ACCESS) {\n \t\t\tIWL_ERR(trans,\n \t\t\t\t\"Error, can not clear persistence bit\\n\");\n \t\t\treturn -EPERM;\n \t\t}\n-\t\tiwl_write_umac_prph_no_grab(trans, HPM_DEBUG,\n-\t\t\t\t\t hpm \u0026 ~PERSISTENCE_BIT);\n+\t\tiwl_pcie_write_umac_prph_no_grab(trans, HPM_DEBUG,\n+\t\t\t\t\t\t hpm \u0026 ~PERSISTENCE_BIT);\n \t}\n \n \treturn 0;\n@@ -1769,15 +1783,15 @@ static int iwl_pcie_gen2_force_power_gating(struct iwl_trans trans)\n \tif (ret \u003c 0)\n \t\treturn ret;\n \n-\tiwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,\n-\t\t\t HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);\n+\tiwl_trans_set_bits_prph(trans, HPM_HIPM_GEN_CFG,\n+\t\t\t\tHPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);\n \tudelay(20);\n-\tiwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,\n-\t\t\t HPM_HIPM_GEN_CFG_CR_PG_EN \|\n-\t\t\t HPM_HIPM_GEN_CFG_CR_SLP_EN);\n+\tiwl_trans_set_bits_prph(trans, HPM_HIPM_GEN_CFG,\n+\t\t\t\tHPM_HIPM_GEN_CFG_CR_PG_EN \|\n+\t\t\t\tHPM_HIPM_GEN_CFG_CR_SLP_EN);\n \tudelay(20);\n-\tiwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,\n-\t\t\t HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);\n+\tiwl_trans_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,\n+\t\t\t\t HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);\n \n \treturn iwl_trans_pcie_sw_reset(trans, true);\n }\n@@ -1846,6 +1860,11 @@ void iwl_trans_pcie_op_mode_leave(struct iwl_trans trans)\n {\n \tstruct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \n+\tif (trans-\u003emac_cfg-\u003egen2) {\n+\t\tiwl_trans_pcie_gen2_op_mode_leave(trans);\n+\t\treturn;\n+\t}\n+\n \tmutex_lock(\u0026trans_pcie-\u003emutex);\n \n \t/* disable interrupts - don't enable HW RF kill interrupt /\n@@ -1864,17 +1883,22 @@ void iwl_trans_pcie_op_mode_leave(struct iwl_trans trans)\n \n void iwl_trans_pcie_write8(struct iwl_trans trans, u32 ofs, u8 val)\n {\n+\ttrace_iwlwifi_dev_iowrite8(trans-\u003edev, ofs, val);\n \twriteb(val, IWL_TRANS_GET_PCIE_TRANS(trans)-\u003ehw_base + ofs);\n }\n \n void iwl_trans_pcie_write32(struct iwl_trans trans, u32 ofs, u32 val)\n {\n+\ttrace_iwlwifi_dev_iowrite32(trans-\u003edev, ofs, val);\n \twritel(val, IWL_TRANS_GET_PCIE_TRANS(trans)-\u003ehw_base + ofs);\n }\n \n u32 iwl_trans_pcie_read32(struct iwl_trans trans, u32 ofs)\n {\n-\treturn readl(IWL_TRANS_GET_PCIE_TRANS(trans)-\u003ehw_base + ofs);\n+\tu32 val = readl(IWL_TRANS_GET_PCIE_TRANS(trans)-\u003ehw_base + ofs);\n+\n+\ttrace_iwlwifi_dev_ioread32(trans-\u003edev, ofs, val);\n+\treturn val;\n }\n \n static u32 iwl_trans_pcie_prph_msk(struct iwl_trans trans)\n@@ -1888,16 +1912,20 @@ static u32 iwl_trans_pcie_prph_msk(struct iwl_trans trans)\n u32 iwl_trans_pcie_read_prph(struct iwl_trans trans, u32 reg)\n {\n \tu32 mask = iwl_trans_pcie_prph_msk(trans);\n+\tu32 val;\n \n \tiwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,\n \t\t\t ((reg \u0026 mask) \| (3 \u003c\u003c 24)));\n-\treturn iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);\n+\tval = iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);\n+\ttrace_iwlwifi_dev_ioread_prph32(trans-\u003edev, reg, val);\n+\treturn val;\n }\n \n-void iwl_trans_pcie_write_prph(struct iwl_trans trans, u32 addr, u32 val)\n+void iwl_pcie_write_prph_no_grab(struct iwl_trans trans, u32 addr, u32 val)\n {\n \tu32 mask = iwl_trans_pcie_prph_msk(trans);\n \n+\ttrace_iwlwifi_dev_iowrite_prph32(trans-\u003edev, addr, val);\n \tiwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,\n \t\t\t ((addr \u0026 mask) \| (3 \u003c\u003c 24)));\n \tiwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);\n@@ -2265,7 +2293,7 @@ static void iwl_trans_pcie_removal_wk(struct work_struct wk)\n \tmodule_put(THIS_MODULE);\n }\n \n-void iwl_trans_pcie_reset(struct iwl_trans trans, enum iwl_reset_mode mode)\n+static void iwl_trans_pcie_reset(struct iwl_trans trans, enum iwl_reset_mode mode)\n {\n \tstruct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \tstruct iwl_trans_pcie_removal removal;\n@@ -2320,7 +2348,6 @@ void iwl_trans_pcie_reset(struct iwl_trans trans, enum iwl_reset_mode mode)\n \tpci_dev_get(removal-\u003epdev);\n \tschedule_work(\u0026removal-\u003ework);\n }\n-EXPORT_SYMBOL(iwl_trans_pcie_reset);\n \n /\n This version doesn't disable BHs but rather assumes they're\n@@ -2350,7 +2377,7 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans trans, bool silent)\n \t}\n \n \t/ this bit wakes up the NIC /\n-\tiwl_trans_set_bit(trans, CSR_GP_CNTRL, write);\n+\tiwl_pcie_set_bit(trans, CSR_GP_CNTRL, write);\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_8000)\n \t\tudelay(2);\n \n@@ -2374,9 +2401,9 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans trans, bool silent)\n \t * 5000 series and later (including 1000 series) have non-volatile SRAM,\n \t * and do not save/restore SRAM when power cycling.\n \t /\n-\tret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);\n+\tret = iwl_trans_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);\n \tif (unlikely(ret)) {\n-\t\tu32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);\n+\t\tu32 cntrl = iwl_trans_pcie_read32(trans, CSR_GP_CNTRL);\n \n \t\tif (silent) {\n \t\t\tspin_unlock(\u0026trans_pcie-\u003ereg_lock);\n@@ -2393,8 +2420,8 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans trans, bool silent)\n \t\t\tiwl_trans_pcie_reset(trans,\n \t\t\t\t\t IWL_RESET_MODE_REMOVE_ONLY);\n \t\telse\n-\t\t\tiwl_write32(trans, CSR_RESET,\n-\t\t\t\t CSR_RESET_REG_FLAG_FORCE_NMI);\n+\t\t\tiwl_trans_pcie_write32(trans, CSR_RESET,\n+\t\t\t\t\t CSR_RESET_REG_FLAG_FORCE_NMI);\n \n \t\tspin_unlock(\u0026trans_pcie-\u003ereg_lock);\n \t\treturn false;\n@@ -2443,11 +2470,11 @@ void iwl_trans_pcie_release_nic_access(struct iwl_trans trans)\n \tif (trans_pcie-\u003ecmd_hold_nic_awake)\n \t\tgoto out;\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n+\t\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n \telse\n-\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \t/\n \t * Above we read the CSR_GP_CNTRL register, which will flush\n \t * any previous writes, but we need the write that clears the\n@@ -2472,12 +2499,12 @@ int iwl_trans_pcie_read_mem(struct iwl_trans trans, u32 addr,\n \t\tbool resched = false;\n \n \t\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\t\tiwl_write32(trans, HBUS_TARG_MEM_RADDR,\n-\t\t\t\t addr + 4 offs);\n+\t\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_MEM_RADDR,\n+\t\t\t\t\t addr + 4 * offs);\n \n \t\t\twhile (offs \u003c dwords) {\n-\t\t\t\tvals[offs] = iwl_read32(trans,\n-\t\t\t\t\t\t\tHBUS_TARG_MEM_RDAT);\n+\t\t\t\tvals[offs] = iwl_trans_pcie_read32(trans,\n+\t\t\t\t\t\t\t\t HBUS_TARG_MEM_RDAT);\n \n \t\t\t\tif (iwl_trans_is_hw_error_value(vals[offs]))\n \t\t\t\t\tnum_consec_hw_errors++;\n@@ -2524,11 +2551,11 @@ int iwl_trans_pcie_read_mem_no_grab(struct iwl_trans trans, u32 addr,\n \t\tunsigned long end = jiffies + HZ / 2;\n \t\tbool resched = false;\n \n-\t\tiwl_write32(trans, HBUS_TARG_MEM_RADDR,\n-\t\t\t addr + 4 offs);\n+\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_MEM_RADDR,\n+\t\t\t\t addr + 4 * offs);\n \n \t\twhile (offs \u003c dwords) {\n-\t\t\tvals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);\n+\t\t\tvals[offs] = iwl_trans_pcie_read32(trans, HBUS_TARG_MEM_RDAT);\n \n \t\t\tif (iwl_trans_is_hw_error_value(vals[offs]))\n \t\t\t\tnum_consec_hw_errors++;\n@@ -2672,7 +2699,7 @@ void iwl_trans_pcie_set_bits_mask(struct iwl_trans trans, u32 reg,\n \tstruct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \n \tspin_lock_bh(\u0026trans_pcie-\u003ereg_lock);\n-\t_iwl_trans_set_bits_mask(trans, reg, mask, value);\n+\tiwl_pcie_set_bits_mask(trans, reg, mask, value);\n \tspin_unlock_bh(\u0026trans_pcie-\u003ereg_lock);\n }\n \n@@ -2745,7 +2772,7 @@ void iwl_pcie_dump_csr(struct iwl_trans trans)\n \tfor (i = 0; i \u003c ARRAY_SIZE(csr_tbl); i++) {\n \t\tIWL_ERR(trans, \" %25s: 0X%08x\\n\",\n \t\t\tget_csr_string(csr_tbl[i]),\n-\t\t\tiwl_read32(trans, csr_tbl[i]));\n+\t\t\tiwl_trans_pcie_read32(trans, csr_tbl[i]));\n \t}\n }\n \n@@ -3021,7 +3048,7 @@ static ssize_t iwl_dbgfs_rfkill_read(struct file file,\n \n \tpos = scnprintf(buf, sizeof(buf), \"debug: %d\\nhw: %d\\n\",\n \t\t\ttrans_pcie-\u003edebug_rfkill,\n-\t\t\t!(iwl_read32(trans, CSR_GP_CNTRL) \u0026\n+\t\t\t!(iwl_trans_pcie_read32(trans, CSR_GP_CNTRL) \u0026\n \t\t\t\tCSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));\n \n \treturn simple_read_from_buffer(user_buf, count, ppos, buf, pos);\n@@ -3228,8 +3255,8 @@ static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans trans,\n \t\t i += sizeof(u32))\n \t\t\tval++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));\n \telse\n-\t\tfor (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);\n-\t\t i \u003c iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);\n+\t\tfor (i = iwl_trans_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);\n+\t\t i \u003c iwl_trans_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);\n \t\t i += sizeof(u32))\n \t\t\tval++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,\n \t\t\t\t\t\t\t\t i));\n@@ -3253,11 +3280,11 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans trans,\n \tif (!iwl_trans_grab_nic_access(trans))\n \t\treturn 0;\n \n-\tiwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);\n+\tiwl_pcie_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);\n \tfor (i = 0; i \u003c buf_size_in_dwords; i++)\n-\t\tbuffer[i] = iwl_read_umac_prph_no_grab(trans,\n-\t\t\t\t\t\t MON_DMARB_RD_DATA_ADDR);\n-\tiwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);\n+\t\tbuffer[i] = iwl_trans_read_umac_prph_no_grab(trans,\n+\t\t\t\t\t\t\t MON_DMARB_RD_DATA_ADDR);\n+\tiwl_pcie_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);\n \n \tiwl_trans_release_nic_access(trans);\n \n@@ -3285,14 +3312,14 @@ iwl_trans_pcie_dump_pointers(struct iwl_trans trans,\n \t\twrap_cnt = MON_BUFF_CYCLE_CNT;\n \t}\n \n-\twrite_ptr_val = iwl_read_prph(trans, write_ptr);\n+\twrite_ptr_val = iwl_trans_read_prph(trans, write_ptr);\n \tfw_mon_data-\u003efw_mon_cycle_cnt =\n-\t\tcpu_to_le32(iwl_read_prph(trans, wrap_cnt));\n+\t\tcpu_to_le32(iwl_trans_read_prph(trans, wrap_cnt));\n \tfw_mon_data-\u003efw_mon_base_ptr =\n-\t\tcpu_to_le32(iwl_read_prph(trans, base));\n+\t\tcpu_to_le32(iwl_trans_read_prph(trans, base));\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_AX210) {\n \t\tfw_mon_data-\u003efw_mon_base_high_ptr =\n-\t\t\tcpu_to_le32(iwl_read_prph(trans, base_high));\n+\t\t\tcpu_to_le32(iwl_trans_read_prph(trans, base_high));\n \t\twrite_ptr_val \u0026= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;\n \t\t/ convert wrtPtr to DWs, to align with all HWs /\n \t\twrite_ptr_val \u003e\u003e= 2;\n@@ -3330,13 +3357,13 @@ iwl_trans_pcie_dump_monitor(struct iwl_trans trans,\n \t\t\t * shifting\n \t\t\t /\n \t\t\tif (trans-\u003edbg.dest_tlv-\u003eversion) {\n-\t\t\t\tbase = (iwl_read_prph(trans, base) \u0026\n+\t\t\t\tbase = (iwl_trans_read_prph(trans, base) \u0026\n \t\t\t\t\tIWL_LDBG_M2S_BUF_BA_MSK) \u003c\u003c\n \t\t\t\t trans-\u003edbg.dest_tlv-\u003ebase_shift;\n \t\t\t\tbase = IWL_M2S_UNIT_SIZE;\n \t\t\t\tbase += trans-\u003emac_cfg-\u003ebase-\u003esmem_offset;\n \t\t\t} else {\n-\t\t\t\tbase = iwl_read_prph(trans, base) \u003c\u003c\n+\t\t\t\tbase = iwl_trans_read_prph(trans, base) \u003c\u003c\n \t\t\t\t trans-\u003edbg.dest_tlv-\u003ebase_shift;\n \t\t\t}\n \n@@ -3371,7 +3398,7 @@ static int iwl_trans_get_fw_monitor_len(struct iwl_trans trans, u32 len)\n \n \t\tif (trans-\u003edbg.dest_tlv-\u003eversion == 1) {\n \t\t\tcfg_reg = le32_to_cpu(trans-\u003edbg.dest_tlv-\u003ebase_reg);\n-\t\t\tcfg_reg = iwl_read_prph(trans, cfg_reg);\n+\t\t\tcfg_reg = iwl_trans_read_prph(trans, cfg_reg);\n \t\t\tbase = (cfg_reg \u0026 IWL_LDBG_M2S_BUF_BA_MSK) \u003c\u003c\n \t\t\t\ttrans-\u003edbg.dest_tlv-\u003ebase_shift;\n \t\t\tbase = IWL_M2S_UNIT_SIZE;\n@@ -3385,9 +3412,9 @@ static int iwl_trans_get_fw_monitor_len(struct iwl_trans trans, u32 len)\n \t\t\tbase = le32_to_cpu(trans-\u003edbg.dest_tlv-\u003ebase_reg);\n \t\t\tend = le32_to_cpu(trans-\u003edbg.dest_tlv-\u003eend_reg);\n \n-\t\t\tbase = iwl_read_prph(trans, base) \u003c\u003c\n+\t\t\tbase = iwl_trans_read_prph(trans, base) \u003c\u003c\n \t\t\t trans-\u003edbg.dest_tlv-\u003ebase_shift;\n-\t\t\tend = iwl_read_prph(trans, end) \u003c\u003c\n+\t\t\tend = iwl_trans_read_prph(trans, end) \u003c\u003c\n \t\t\t trans-\u003edbg.dest_tlv-\u003eend_shift;\n \n \t\t\t/ Make \"end\" point to the actual end /\n@@ -3445,8 +3472,8 @@ iwl_trans_pcie_dump_data(struct iwl_trans trans, u32 dump_mask,\n \tif (dump_mask \u0026 BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {\n \t\tif (trans-\u003emac_cfg-\u003egen2)\n \t\t\tlen += sizeof(data) +\n-\t\t\t (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -\n-\t\t\t\tiwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));\n+\t\t\t (iwl_trans_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -\n+\t\t\t\tiwl_trans_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));\n \t\telse\n \t\t\tlen += sizeof(data) +\n \t\t\t (FH_MEM_UPPER_BOUND -\n@@ -3592,12 +3619,12 @@ void iwl_trans_pcie_sync_nmi(struct iwl_trans trans)\n \n \tiwl_trans_force_nmi(trans);\n \twhile (time_after(timeout, jiffies)) {\n-\t\tu32 inta_hw = iwl_read32(trans, inta_addr);\n+\t\tu32 inta_hw = iwl_trans_pcie_read32(trans, inta_addr);\n \n \t\t/ Error detected by uCode /\n \t\tif (inta_hw \u0026 sw_err_bit) {\n \t\t\t/ Clear causes register /\n-\t\t\tiwl_write32(trans, inta_addr, inta_hw \u0026 sw_err_bit);\n+\t\t\tiwl_trans_pcie_write32(trans, inta_addr, inta_hw \u0026 sw_err_bit);\n \t\t\tbreak;\n \t\t}\n \n@@ -3651,6 +3678,66 @@ static int iwl_trans_pcie_alloc_txcmd_pool(struct iwl_trans trans)\n \treturn 0;\n }\n \n+const struct iwl_trans_ops iwl_trans_pcie_ops = {\n+\t.op_mode_enter = iwl_trans_pcie_op_mode_enter,\n+\t.start_hw = iwl_trans_pcie_start_hw,\n+\t.op_mode_leave = iwl_trans_pcie_op_mode_leave,\n+\n+\t.send_cmd = iwl_trans_pcie_send_hcmd,\n+\t.alloc_tx_cmd = iwl_pcie_alloc_tx_cmd,\n+\t.free_tx_cmd = iwl_pcie_free_tx_cmd,\n+\n+\t.write8 = iwl_trans_pcie_write8,\n+\t.write32 = iwl_trans_pcie_write32,\n+\t.read32 = iwl_trans_pcie_read32,\n+\t.read_prph = iwl_trans_pcie_read_prph,\n+\t.write_prph = iwl_pcie_write_prph_no_grab,\n+\t.read_mem = iwl_trans_pcie_read_mem,\n+\t.read_mem_no_grab = iwl_trans_pcie_read_mem_no_grab,\n+\t.set_bits_mask = iwl_trans_pcie_set_bits_mask,\n+\t.read_config32 = iwl_trans_pcie_read_config32,\n+\t.grab_nic_access = iwl_trans_pcie_grab_nic_access,\n+\t.release_nic_access = iwl_trans_pcie_release_nic_access,\n+\t.resched_with_nic_access = iwl_trans_pcie_resched_with_nic_access,\n+\n+\t.sw_reset = iwl_trans_pcie_sw_reset,\n+\t.reset = iwl_trans_pcie_reset,\n+\t.fw_reset_handshake = iwl_trans_pcie_fw_reset_handshake,\n+\n+\t.dump_data = iwl_trans_pcie_dump_data,\n+\t.d3_suspend = iwl_trans_pcie_d3_suspend,\n+\t.d3_resume = iwl_trans_pcie_d3_resume,\n+\n+\t.sync_nmi = iwl_trans_pcie_sync_nmi,\n+\t.write_imr_mem = iwl_trans_pcie_copy_imr,\n+\n+\t.fw_alive = iwl_trans_pcie_fw_alive,\n+\t.start_fw = iwl_trans_pcie_start_fw,\n+\t.stop_device = iwl_trans_pcie_stop_device,\n+\n+\t.tx = iwl_trans_pcie_tx,\n+\t.reclaim = iwl_pcie_reclaim,\n+\t.txq_disable = iwl_trans_pcie_txq_disable,\n+\t.txq_enable = iwl_trans_pcie_txq_enable,\n+\t.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,\n+\t.wait_txqs_empty = iwl_trans_pcie_wait_txqs_empty,\n+\t.freeze_txq_timer = iwl_pcie_freeze_txq_timer,\n+\t.txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,\n+\t.set_q_ptrs = iwl_pcie_set_q_ptrs,\n+\t.txq_alloc = iwl_txq_dyn_alloc,\n+\t.txq_free = iwl_txq_dyn_free,\n+\t.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,\n+\n+\t.load_pnvm = iwl_trans_pcie_ctx_info_v2_load_pnvm,\n+\t.set_pnvm = iwl_trans_pcie_ctx_info_v2_set_pnvm,\n+\t.load_reduce_power = iwl_trans_pcie_ctx_info_v2_load_reduce_power,\n+\t.set_reduce_power = iwl_trans_pcie_ctx_info_v2_set_reduce_power,\n+\n+\t.is_pm_supported = iwl_pcie_gen1_is_pm_supported,\n+\t.is_ltr_enabled = iwl_pcie_is_ltr_enabled,\n+\t.activate_nic = iwl_pcie_activate_nic,\n+};\n+\n static struct iwl_trans \n iwl_trans_pcie_alloc(struct pci_dev pdev,\n \t\t const struct iwl_mac_cfg mac_cfg,\n@@ -3662,7 +3749,7 @@ iwl_trans_pcie_alloc(struct pci_dev pdev,\n \tint ret, addr_size;\n \n \ttrans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), \u0026pdev-\u003edev,\n-\t\t\t\tmac_cfg);\n+\t\t\t\t\u0026iwl_trans_pcie_ops, mac_cfg);\n \tif (!trans)\n \t\treturn ERR_PTR(-ENOMEM);\n \n@@ -3851,19 +3938,19 @@ iwl_trans_pcie_alloc(struct pci_dev pdev,\n void iwl_trans_pcie_copy_imr_fh(struct iwl_trans trans,\n \t\t\t\tu32 dst_addr, u64 src_addr, u32 byte_cnt)\n {\n-\tiwl_write_prph(trans, IMR_UREG_CHICK,\n-\t\t iwl_read_prph(trans, IMR_UREG_CHICK) \|\n-\t\t IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,\n-\t\t (u32)(src_addr \u0026 0xFFFFFFFF));\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,\n-\t\t iwl_get_dma_hi_addr(src_addr));\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,\n-\t\t IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS \|\n-\t\t IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS \|\n-\t\t IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);\n+\tiwl_trans_write_prph(trans, IMR_UREG_CHICK,\n+\t\t\t iwl_trans_read_prph(trans, IMR_UREG_CHICK) \|\n+\t\t\t IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,\n+\t\t\t (u32)(src_addr \u0026 0xFFFFFFFF));\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,\n+\t\t\t iwl_get_dma_hi_addr(src_addr));\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,\n+\t\t\t IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS \|\n+\t\t\t IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS \|\n+\t\t\t IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);\n }\n \n int iwl_trans_pcie_copy_imr(struct iwl_trans trans,\n@@ -3905,8 +3992,8 @@ static void get_crf_id(struct iwl_trans iwl_trans,\n \t/* wait until the device is ready to access the prph registers /\n \tif (iwl_trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_DR \|\|\n \t iwl_trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_SC) {\n-\t\tu32 req = iwl_read_umac_prph_no_grab(iwl_trans,\n-\t\t\t\t\t\t WFPM_RSRCS_4PHS_REQ_STTS);\n+\t\tu32 req = iwl_trans_read_umac_prph_no_grab(iwl_trans,\n+\t\t\t\t\t\t\t WFPM_RSRCS_4PHS_REQ_STTS);\n \t\tint ret;\n \n \t\tif (!(req \u0026 RSRC_REQ_CNVR_TOP)) {\n@@ -3916,26 +4003,26 @@ static void get_crf_id(struct iwl_trans iwl_trans,\n \t\t\treturn;\n \t\t}\n \n-\t\tret = iwl_poll_umac_prph_bits_no_grab(iwl_trans,\n-\t\t\t\t\t\t WFPM_RSRCS_4PHS_ACK_STTS,\n-\t\t\t\t\t\t RSRC_ACK_CNVR_TOP,\n-\t\t\t\t\t\t RSRC_ACK_CNVR_TOP,\n-\t\t\t\t\t\t 50 * 1000);\n+\t\tret = iwl_pcie_poll_umac_prph_bits_no_grab(iwl_trans,\n+\t\t\t\t\t\t\t WFPM_RSRCS_4PHS_ACK_STTS,\n+\t\t\t\t\t\t\t RSRC_ACK_CNVR_TOP,\n+\t\t\t\t\t\t\t RSRC_ACK_CNVR_TOP,\n+\t\t\t\t\t\t\t 50 * 1000);\n \t\tif (ret \u003c 0)\n \t\t\tIWL_ERR(iwl_trans,\n \t\t\t\t\"WFPM_RSRCS_4PHS_ACK_STTS bit 6 is clear\\n\");\n \t}\n \n \t/* Enable access to peripheral registers /\n-\tval = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);\n+\tval = iwl_trans_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);\n \tval \|= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;\n-\tiwl_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val);\n+\tiwl_pcie_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val);\n \n \t/ Read crf info /\n-\tinfo-\u003ehw_crf_id = iwl_read_prph_no_grab(iwl_trans, sd_reg_ver_addr);\n+\tinfo-\u003ehw_crf_id = iwl_trans_pcie_read_prph(iwl_trans, sd_reg_ver_addr);\n \n \t/ Read cnv info /\n-\tinfo-\u003ehw_cnv_id = iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP);\n+\tinfo-\u003ehw_cnv_id = iwl_trans_pcie_read_prph(iwl_trans, CNVI_AUX_MISC_CHIP);\n \n \t/ For BZ-W, take B step also when A step is indicated /\n \tif (CSR_HW_REV_TYPE(info-\u003ehw_rev) == IWL_CFG_MAC_TYPE_BZ_W)\n@@ -3959,7 +4046,7 @@ static void get_crf_id(struct iwl_trans iwl_trans,\n \t}\n \n \t/* Read cdb info (also contains the jacket info if needed in the future /\n-\thw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);\n+\thw_wfpm_id = iwl_trans_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);\n \n \tIWL_INFO(iwl_trans, \"Detected crf-id 0x%x, cnv-id 0x%x wfpm id 0x%x\\n\",\n \t\t info-\u003ehw_crf_id, info-\u003ehw_cnv_id, hw_wfpm_id);\n@@ -3976,8 +4063,8 @@ static int map_crf_id(struct iwl_trans iwl_trans,\n \tu32 val = info-\u003ehw_crf_id;\n \tu32 step_id = REG_CRF_ID_STEP(val);\n \tu32 slave_id = REG_CRF_ID_SLAVE(val);\n-\tu32 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans,\n-\t\t\t\t\t\t WFPM_OTP_CFG1_ADDR);\n+\tu32 hw_wfpm_id = iwl_trans_read_umac_prph_no_grab(iwl_trans,\n+\t\t\t\t\t\t\t WFPM_OTP_CFG1_ADDR);\n \tu32 cdb_id_wfpm = WFPM_OTP_CFG1_IS_CDB(hw_wfpm_id);\n \n \t/* Map between crf id to rf id /\n@@ -4043,7 +4130,7 @@ static void iwl_pcie_recheck_me_status(struct work_struct wk)\n \t\t\t\t\t\t\t me_recheck_wk.work);\n \tu32 val;\n \n-\tval = iwl_read32(trans_pcie-\u003etrans, CSR_HW_IF_CONFIG_REG);\n+\tval = iwl_trans_pcie_read32(trans_pcie-\u003etrans, CSR_HW_IF_CONFIG_REG);\n \ttrans_pcie-\u003eme_present = !!(val \u0026 CSR_HW_IF_CONFIG_REG_IAMT_UP);\n }\n \n@@ -4061,14 +4148,14 @@ static void iwl_pcie_check_me_status(struct iwl_trans trans)\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_BZ)\n \t\treturn;\n \n-\tval = iwl_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1);\n+\tval = iwl_trans_pcie_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1);\n \tif (val \u0026 CNVI_SCU_REG_FOR_ECO_1_WIAMT_KNOWN) {\n \t\ttrans_pcie-\u003eme_present =\n \t\t\t!!(val \u0026 CNVI_SCU_REG_FOR_ECO_1_WIAMT_PRESENT);\n \t\treturn;\n \t}\n \n-\tval = iwl_read32(trans, CSR_HW_IF_CONFIG_REG);\n+\tval = iwl_trans_pcie_read32(trans, CSR_HW_IF_CONFIG_REG);\n \tif (val \u0026 (CSR_HW_IF_CONFIG_REG_ME_OWN \|\n \t\t CSR_HW_IF_CONFIG_REG_IAMT_UP)) {\n \t\ttrans_pcie-\u003eme_present = 1;\n@@ -4126,7 +4213,7 @@ int _iwl_pci_probe(struct pci_dev pdev, const struct pci_device_id ent,\n \t\t}\n \t}\n \n-\tinfo.hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID);\n+\tinfo.hw_rf_id = iwl_trans_pcie_read32(iwl_trans, CSR_HW_RF_ID);\n \n \t/\n \t * The RF_ID is set to zero in blank OTP so read version to\n@@ -4247,13 +4334,13 @@ int iwl_pcie_activate_nic(struct iwl_trans trans)\n \t D0U* --\u003e D0A* (powered-up active) state.\n \t /\n \tif (mac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ \|\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ \|\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n \t\tpoll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;\n \t} else {\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n \t\tpoll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY;\n \t}\n \n@@ -4262,10 +4349,10 @@ int iwl_pcie_activate_nic(struct iwl_trans trans)\n \n \t/\n \t Wait for clock stabilization; once stabilized, access to\n-\t * device-internal resources is supported, e.g. iwl_write_prph()\n+\t * device-internal resources is supported, e.g. iwl_trans_write_prph()\n \t * and accesses to uCode SRAM.\n \t /\n-\terr = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);\n+\terr = iwl_trans_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);\n \tif (err \u003c 0) {\n \t\tIWL_DEBUG_INFO(trans, \"Failed to wake NIC\\n\");\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c\nindex 27f4973791d00..e6bebd37417f7 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c\n@@ -1,14 +1,14 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /\n * Copyright (C) 2017 Intel Deutschland GmbH\n- * Copyright (C) 2018-2020, 2023-2025 Intel Corporation\n+ * Copyright (C) 2018-2020, 2023-2026 Intel Corporation\n /\n #include \u003cnet/tso.h\u003e\n #include \u003clinux/tcp.h\u003e\n \n #include \"iwl-debug.h\"\n #include \"iwl-csr.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"internal.h\"\n #include \"fw/api/tx.h\"\n #include \"fw/api/commands.h\"\n@@ -711,7 +711,7 @@ static void iwl_txq_inc_wr_ptr(struct iwl_trans trans, struct iwl_txq txq)\n \t if not in power-save mode, uCode will never sleep when we're\n \t * trying to tx (during RFKILL, we're not trying to tx).\n \t /\n-\tiwl_write32(trans, HBUS_TARG_WRPTR, txq-\u003ewrite_ptr \| (txq-\u003eid \u003c\u003c 16));\n+\tiwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, txq-\u003ewrite_ptr \| (txq-\u003eid \u003c\u003c 16));\n }\n \n int iwl_txq_gen2_tx(struct iwl_trans trans, struct sk_buff skb,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c\nindex 496435ea93ee8..0c29fb6b9ca71 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c\n@@ -20,7 +20,7 @@\n #include \"iwl-debug.h\"\n #include \"iwl-csr.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-scd.h\"\n #include \"iwl-op-mode.h\"\n #include \"internal.h\"\n@@ -99,13 +99,13 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans trans,\n \t\t * uCode will wake up, and interrupt us again, so next\n \t\t * time we'll skip this part.\n \t\t /\n-\t\treg = iwl_read32(trans, CSR_UCODE_DRV_GP1);\n+\t\treg = iwl_trans_pcie_read32(trans, CSR_UCODE_DRV_GP1);\n \n \t\tif (reg \u0026 CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {\n \t\t\tIWL_DEBUG_INFO(trans, \"Tx queue %d requesting wakeup, GP1 = 0x%x\\n\",\n \t\t\t\t txq_id, reg);\n-\t\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \t\t\ttxq-\u003eneed_update = true;\n \t\t\treturn;\n \t\t}\n@@ -117,8 +117,8 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans trans,\n \t /\n \tIWL_DEBUG_TX(trans, \"Q:%d WR: 0x%x\\n\", txq_id, txq-\u003ewrite_ptr);\n \tif (!txq-\u003eblock)\n-\t\tiwl_write32(trans, HBUS_TARG_WRPTR,\n-\t\t\t txq-\u003ewrite_ptr \| (txq_id \u003c\u003c 8));\n+\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR,\n+\t\t\t\t txq-\u003ewrite_ptr \| (txq_id \u003c\u003c 8));\n }\n \n void iwl_pcie_txq_check_wrptrs(struct iwl_trans trans)\n@@ -205,8 +205,8 @@ static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans trans)\n \t}\n \n \ttrans_pcie-\u003ecmd_hold_nic_awake = false;\n-\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \tspin_unlock(\u0026trans_pcie-\u003ereg_lock);\n }\n \n@@ -493,21 +493,21 @@ void iwl_pcie_tx_start(struct iwl_trans trans)\n \t sizeof(trans_pcie-\u003etxqs.queue_used));\n \n \ttrans_pcie-\u003escd_base_addr =\n-\t\tiwl_read_prph(trans, SCD_SRAM_BASE_ADDR);\n+\t\tiwl_trans_read_prph(trans, SCD_SRAM_BASE_ADDR);\n \n \t/* reset context data, TX status and translation data /\n \tiwl_trans_write_mem(trans, trans_pcie-\u003escd_base_addr +\n \t\t\t\t SCD_CONTEXT_MEM_LOWER_BOUND,\n \t\t\t NULL, clear_dwords);\n \n-\tiwl_write_prph(trans, SCD_DRAM_BASE_ADDR,\n-\t\t trans_pcie-\u003etxqs.scd_bc_tbls.dma \u003e\u003e 10);\n+\tiwl_trans_write_prph(trans, SCD_DRAM_BASE_ADDR,\n+\t\t\t trans_pcie-\u003etxqs.scd_bc_tbls.dma \u003e\u003e 10);\n \n \t/ The chain extension of the SCD doesn't work well. This feature is\n \t * enabled by default by the HW, so we need to disable it manually.\n \t /\n \tif (trans-\u003emac_cfg-\u003ebase-\u003escd_chain_ext_wa)\n-\t\tiwl_write_prph(trans, SCD_CHAINEXT_EN, 0);\n+\t\tiwl_trans_write_prph(trans, SCD_CHAINEXT_EN, 0);\n \n \tiwl_trans_ac_txq_enable(trans, trans-\u003econf.cmd_queue,\n \t\t\t\ttrans-\u003econf.cmd_fifo,\n@@ -518,19 +518,19 @@ void iwl_pcie_tx_start(struct iwl_trans trans)\n \n \t/* Enable DMA channel /\n \tfor (chan = 0; chan \u003c FH_TCSR_CHNL_NUM; chan++)\n-\t\tiwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),\n-\t\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \|\n-\t\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);\n+\t\tiwl_trans_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),\n+\t\t\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \|\n+\t\t\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);\n \n \t/ Update FH chicken bits /\n-\treg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);\n-\tiwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,\n-\t\t\t reg_val \| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);\n+\treg_val = iwl_pcie_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);\n+\tiwl_trans_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,\n+\t\t\t\t reg_val \| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);\n \n \t/ Enable L1-Active /\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_8000)\n-\t\tiwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,\n-\t\t\t\t APMG_PCIDEV_STT_VAL_L1_ACT_DIS);\n+\t\tiwl_trans_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,\n+\t\t\t\t\t APMG_PCIDEV_STT_VAL_L1_ACT_DIS);\n }\n \n void iwl_trans_pcie_tx_reset(struct iwl_trans trans)\n@@ -549,21 +549,21 @@ void iwl_trans_pcie_tx_reset(struct iwl_trans trans)\n \t txq_id++) {\n \t\tstruct iwl_txq txq = trans_pcie-\u003etxqs.txq[txq_id];\n \t\tif (trans-\u003emac_cfg-\u003egen2)\n-\t\t\tiwl_write_direct64(trans,\n-\t\t\t\t\t FH_MEM_CBBC_QUEUE(trans, txq_id),\n-\t\t\t\t\t txq-\u003edma_addr);\n+\t\t\tiwl_pcie_write_direct64(trans,\n+\t\t\t\t\t\tFH_MEM_CBBC_QUEUE(trans, txq_id),\n+\t\t\t\t\t\ttxq-\u003edma_addr);\n \t\telse\n-\t\t\tiwl_write_direct32(trans,\n-\t\t\t\t\t FH_MEM_CBBC_QUEUE(trans, txq_id),\n-\t\t\t\t\t txq-\u003edma_addr \u003e\u003e 8);\n+\t\t\tiwl_trans_write_direct32(trans,\n+\t\t\t\t\t\t FH_MEM_CBBC_QUEUE(trans, txq_id),\n+\t\t\t\t\t\t txq-\u003edma_addr \u003e\u003e 8);\n \t\tiwl_pcie_txq_unmap(trans, txq_id);\n \t\ttxq-\u003eread_ptr = 0;\n \t\ttxq-\u003ewrite_ptr = 0;\n \t}\n \n \t/* Tell NIC where to find the \"keep warm\" buffer /\n-\tiwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,\n-\t\t\t trans_pcie-\u003ekw.dma \u003e\u003e 4);\n+\tiwl_trans_write_direct32(trans, FH_KW_MEM_ADDR_REG,\n+\t\t\t\t trans_pcie-\u003ekw.dma \u003e\u003e 4);\n \n \t/\n \t * Send 0 as the scd_base_addr since the device may have be reset\n@@ -586,16 +586,16 @@ static void iwl_pcie_tx_stop_fh(struct iwl_trans trans)\n \n \t/ Stop each Tx DMA channel /\n \tfor (ch = 0; ch \u003c FH_TCSR_CHNL_NUM; ch++) {\n-\t\tiwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);\n+\t\tiwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);\n \t\tmask \|= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);\n \t}\n \n \t/ Wait for DMA channels to be idle /\n-\tret = iwl_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);\n+\tret = iwl_trans_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);\n \tif (ret)\n \t\tIWL_ERR(trans,\n \t\t\t\"Failing on timeout while stopping DMA channel %d [0x%08x]\\n\",\n-\t\t\tch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));\n+\t\t\tch, iwl_trans_pcie_read32(trans, FH_TSSR_TX_STATUS_REG));\n \n \tiwl_trans_release_nic_access(trans);\n \n@@ -684,7 +684,7 @@ void iwl_txq_log_scd_error(struct iwl_trans trans, struct iwl_txq txq)\n \t\treturn;\n \t}\n \n-\tstatus = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));\n+\tstatus = iwl_trans_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));\n \tfifo = (status \u003e\u003e SCD_QUEUE_STTS_REG_POS_TXF) \u0026 0x7;\n \tactive = !!(status \u0026 BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));\n \n@@ -693,11 +693,11 @@ void iwl_txq_log_scd_error(struct iwl_trans trans, struct iwl_txq txq)\n \t\ttxq_id, active ? \"\" : \"in\", fifo,\n \t\tjiffies_to_msecs(txq-\u003ewd_timeout),\n \t\ttxq-\u003eread_ptr, txq-\u003ewrite_ptr,\n-\t\tiwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) \u0026\n+\t\tiwl_trans_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) \u0026\n \t\t\t(trans-\u003emac_cfg-\u003ebase-\u003emax_tfd_queue_size - 1),\n-\t\t\tiwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) \u0026\n+\t\t\tiwl_trans_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) \u0026\n \t\t\t(trans-\u003emac_cfg-\u003ebase-\u003emax_tfd_queue_size - 1),\n-\t\t\tiwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));\n+\t\t\tiwl_pcie_read_direct32(trans, FH_TX_TRB_REG(fifo)));\n }\n \n static void iwl_txq_stuck_timer(struct timer_list t)\n@@ -955,8 +955,8 @@ int iwl_pcie_tx_init(struct iwl_trans trans)\n \tiwl_scd_deactivate_fifos(trans);\n \n \t/ Tell NIC where to find the \"keep warm\" buffer /\n-\tiwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,\n-\t\t\t trans_pcie-\u003ekw.dma \u003e\u003e 4);\n+\tiwl_trans_write_direct32(trans, FH_KW_MEM_ADDR_REG,\n+\t\t\t\t trans_pcie-\u003ekw.dma \u003e\u003e 4);\n \n \tspin_unlock_bh(\u0026trans_pcie-\u003eirq_lock);\n \n@@ -984,14 +984,14 @@ int iwl_pcie_tx_init(struct iwl_trans trans)\n \t\t * queue.\n \t\t * Circular buffer (TFD queue in DRAM) physical base address\n \t\t /\n-\t\tiwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),\n-\t\t\t\t trans_pcie-\u003etxqs.txq[txq_id]-\u003edma_addr \u003e\u003e 8);\n+\t\tiwl_trans_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),\n+\t\t\t\t\t trans_pcie-\u003etxqs.txq[txq_id]-\u003edma_addr \u003e\u003e 8);\n \t}\n \n-\tiwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);\n+\tiwl_trans_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);\n \tif (trans-\u003emac_cfg-\u003ebase-\u003enum_of_queues \u003e 20)\n-\t\tiwl_set_bits_prph(trans, SCD_GP_CTRL,\n-\t\t\t\t SCD_GP_CTRL_ENABLE_31_QUEUES);\n+\t\tiwl_trans_set_bits_prph(trans, SCD_GP_CTRL,\n+\t\t\t\t\tSCD_GP_CTRL_ENABLE_31_QUEUES);\n \n \treturn 0;\n error:\n@@ -1222,13 +1222,13 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans trans, int txq_id, u16 ssn,\n \t * Assumes that ssn_idx is valid (!= 0xFFF) /\n \ttxq-\u003eread_ptr = (ssn \u0026 0xff);\n \ttxq-\u003ewrite_ptr = (ssn \u0026 0xff);\n-\tiwl_write_direct32(trans, HBUS_TARG_WRPTR,\n-\t\t\t (ssn \u0026 0xff) \| (txq_id \u003c\u003c 8));\n+\tiwl_trans_write_direct32(trans, HBUS_TARG_WRPTR,\n+\t\t\t\t (ssn \u0026 0xff) \| (txq_id \u003c\u003c 8));\n \n \tif (cfg) {\n \t\tu8 frame_limit = cfg-\u003eframe_limit;\n \n-\t\tiwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);\n+\t\tiwl_trans_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);\n \n \t\t/ Set up Tx window size and frame limit for this queue /\n \t\tiwl_trans_write_mem32(trans, trans_pcie-\u003escd_base_addr +\n@@ -1240,11 +1240,11 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans trans, int txq_id, u16 ssn,\n \t\t\tSCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));\n \n \t\t/* Set up status area in SRAM, map to Tx DMA/FIFO, activate /\n-\t\tiwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),\n-\t\t\t (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_ACTIVE) \|\n-\t\t\t (cfg-\u003efifo \u003c\u003c SCD_QUEUE_STTS_REG_POS_TXF) \|\n-\t\t\t (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_WSL) \|\n-\t\t\t SCD_QUEUE_STTS_REG_MSK);\n+\t\tiwl_trans_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),\n+\t\t\t\t (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_ACTIVE) \|\n+\t\t\t\t (cfg-\u003efifo \u003c\u003c SCD_QUEUE_STTS_REG_POS_TXF) \|\n+\t\t\t\t (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_WSL) \|\n+\t\t\t\t SCD_QUEUE_STTS_REG_MSK);\n \n \t\t/ enable the scheduler for this queue (only) /\n \t\tif (txq_id == trans-\u003econf.cmd_queue \u0026\u0026\n@@ -1335,8 +1335,8 @@ static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans trans, bool block)\n \t\tif (!block \u0026\u0026 !(WARN_ON_ONCE(!txq-\u003eblock))) {\n \t\t\ttxq-\u003eblock--;\n \t\t\tif (!txq-\u003eblock) {\n-\t\t\t\tiwl_write32(trans, HBUS_TARG_WRPTR,\n-\t\t\t\t\t txq-\u003ewrite_ptr \| (i \u003c\u003c 8));\n+\t\t\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR,\n+\t\t\t\t\t\t txq-\u003ewrite_ptr \| (i \u003c\u003c 8));\n \t\t\t}\n \t\t} else if (block) {\n \t\t\ttxq-\u003eblock++;\n@@ -2147,6 +2147,9 @@ int iwl_trans_pcie_tx(struct iwl_trans trans, struct sk_buff skb,\n \tu16 wifi_seq;\n \tbool amsdu;\n \n+\tif (trans-\u003emac_cfg-\u003egen2)\n+\t\treturn iwl_txq_gen2_tx(trans, skb, dev_cmd, txq_id);\n+\n \ttxq = trans_pcie-\u003etxqs.txq[txq_id];\n \n \tif (WARN_ONCE(!test_bit(txq_id, trans_pcie-\u003etxqs.queue_used),\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/utils.c b/drivers/net/wireless/intel/iwlwifi/pcie/utils.c\nindex 1bb274d8390c3..8aa43e5ac0e19 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/utils.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/utils.c\n@@ -1,12 +1,12 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /\n- Copyright (C) 2025 Intel Corporation\n+ * Copyright (C) 2025-2026 Intel Corporation\n /\n \n #include \u003clinux/pci.h\u003e\n #include \u003clinux/gfp.h\u003e\n \n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"pcie/utils.h\"\n \n void iwl_trans_pcie_dump_regs(struct iwl_trans trans, struct pci_dev pdev)\n@@ -51,7 +51,7 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans trans, struct pci_dev pdev)\n \n \tIWL_ERR(trans, \"iwlwifi device memory mapped registers:\\n\");\n \tfor (i = 0, ptr = buf; i \u003c PCI_MEM_DUMP_SIZE; i += 4, ptr++)\n-\t\tptr = iwl_read32(trans, i);\n+\t\tptr = iwl_trans_pcie_read32(trans, i);\n \tprint_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);\n \n \tpos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);\n@@ -102,3 +102,88 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans trans, struct pci_dev pdev)\n \tpcie_dbg_dumped_once = 1;\n \tkfree(buf);\n }\n+\n+u32 iwl_pcie_read_direct32(struct iwl_trans trans, u32 reg)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tu32 value = iwl_trans_pcie_read32(trans, reg);\n+\n+\t\tiwl_trans_release_nic_access(trans);\n+\t\treturn value;\n+\t}\n+\n+\t/* return as if we have a HW timeout/failure /\n+\treturn 0x5a5a5a5a;\n+}\n+\n+#define IWL_PCIE_POLL_INTERVAL 10\t/ microseconds /\n+\n+int iwl_pcie_poll_direct_bit(struct iwl_trans trans,\n+\t\t\t u32 addr, u32 mask, int timeout)\n+{\n+\tint t = 0;\n+\n+\tdo {\n+\t\tif ((iwl_pcie_read_direct32(trans, addr) \u0026 mask) == mask)\n+\t\t\treturn t;\n+\t\tudelay(IWL_PCIE_POLL_INTERVAL);\n+\t\tt += IWL_PCIE_POLL_INTERVAL;\n+\t} while (t \u003c timeout);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+int iwl_pcie_poll_prph_bit(struct iwl_trans trans, u32 addr,\n+\t\t\t u32 bits, u32 mask, int timeout)\n+{\n+\tint t = 0;\n+\n+\tdo {\n+\t\tif ((iwl_trans_read_prph(trans, addr) \u0026 mask) == (bits \u0026 mask))\n+\t\t\treturn 0;\n+\t\tudelay(IWL_PCIE_POLL_INTERVAL);\n+\t\tt += IWL_PCIE_POLL_INTERVAL;\n+\t} while (t \u003c timeout);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+int iwl_pcie_poll_umac_prph_bit(struct iwl_trans trans,\n+\t\t\t\tu32 addr, u32 bits, u32 mask,\n+\t\t\t\tint timeout)\n+{\n+\treturn iwl_pcie_poll_prph_bit(trans, addr +\n+\t\t\t\t trans-\u003emac_cfg-\u003eumac_prph_offset,\n+\t\t\t\t bits, mask, timeout);\n+}\n+\n+int iwl_pcie_poll_umac_prph_bits_no_grab(struct iwl_trans trans, u32 addr,\n+\t\t\t\t\t u32 bits, u32 mask, int timeout)\n+{\n+\tint t = 0;\n+\n+\tdo {\n+\t\tif ((iwl_trans_read_umac_prph_no_grab(trans, addr) \u0026 mask) ==\n+\t\t (bits \u0026 mask))\n+\t\t\treturn 0;\n+\t\tudelay(IWL_PCIE_POLL_INTERVAL);\n+\t\tt += IWL_PCIE_POLL_INTERVAL;\n+\t} while (t \u003c timeout);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+void iwl_pcie_write_prph64_no_grab(struct iwl_trans trans, u32 ofs, u64 val)\n+{\n+\ttrace_iwlwifi_dev_iowrite_prph64(trans-\u003edev, ofs, val);\n+\tiwl_pcie_write_prph_no_grab(trans, ofs, val \u0026 0xffffffff);\n+\tiwl_pcie_write_prph_no_grab(trans, ofs + 4, val \u003e\u003e 32);\n+}\n+\n+void iwl_pcie_write_direct64(struct iwl_trans trans, u64 reg, u64 value)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tiwl_pcie_write64(trans, reg, value);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/utils.h b/drivers/net/wireless/intel/iwlwifi/pcie/utils.h\nindex 27437d5e099ba..ece1caaa49482 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/utils.h\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/utils.h\n@@ -1,17 +1,43 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /\n- * Copyright (C) 2025 Intel Corporation\n+ * Copyright (C) 2025-2026 Intel Corporation\n /\n \n #ifndef __iwl_pcie_utils_h__\n #define __iwl_pcie_utils_h__\n \n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n+#include \"internal.h\"\n \n void iwl_trans_pcie_dump_regs(struct iwl_trans trans, struct pci_dev pdev);\n \n-static inline void _iwl_trans_set_bits_mask(struct iwl_trans trans,\n-\t\t\t\t\t u32 reg, u32 mask, u32 value)\n+u32 iwl_pcie_read_direct32(struct iwl_trans trans, u32 reg);\n+int iwl_pcie_poll_direct_bit(struct iwl_trans trans,\n+\t\t\t u32 addr, u32 mask, int timeout);\n+int iwl_pcie_poll_prph_bit(struct iwl_trans trans, u32 addr,\n+\t\t\t u32 bits, u32 mask, int timeout);\n+int iwl_pcie_poll_umac_prph_bit(struct iwl_trans trans, u32 addr,\n+\t\t\t\tu32 bits, u32 mask, int timeout);\n+int iwl_pcie_poll_umac_prph_bits_no_grab(struct iwl_trans trans, u32 addr,\n+\t\t\t\t\t u32 bits, u32 mask, int timeout);\n+void iwl_pcie_write_prph64_no_grab(struct iwl_trans trans, u32 ofs, u64 val);\n+void iwl_pcie_write_direct64(struct iwl_trans trans, u64 reg, u64 value);\n+\n+static inline void iwl_pcie_write64(struct iwl_trans trans, u64 ofs, u64 val)\n+{\n+\tiwl_trans_pcie_write32(trans, ofs, lower_32_bits(val));\n+\tiwl_trans_pcie_write32(trans, ofs + 4, upper_32_bits(val));\n+}\n+\n+static inline void iwl_pcie_write_umac_prph_no_grab(struct iwl_trans trans,\n+\t\t\t\t\t\t u32 ofs, u32 val)\n+{\n+\tiwl_pcie_write_prph_no_grab(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset,\n+\t\t\t\t val);\n+}\n+\n+static inline void iwl_pcie_set_bits_mask(struct iwl_trans trans,\n+\t\t\t\t\t u32 reg, u32 mask, u32 value)\n {\n \tu32 v;\n \n@@ -19,22 +45,22 @@ static inline void _iwl_trans_set_bits_mask(struct iwl_trans trans,\n \tWARN_ON_ONCE(value \u0026 ~mask);\n #endif\n \n-\tv = iwl_read32(trans, reg);\n+\tv = iwl_trans_pcie_read32(trans, reg);\n \tv \u0026= ~mask;\n \tv \|= value;\n-\tiwl_write32(trans, reg, v);\n+\tiwl_trans_pcie_write32(trans, reg, v);\n }\n \n-static inline void iwl_trans_clear_bit(struct iwl_trans trans,\n+static inline void iwl_pcie_clear_bit(struct iwl_trans trans,\n \t\t\t\t u32 reg, u32 mask)\n {\n-\t_iwl_trans_set_bits_mask(trans, reg, mask, 0);\n+\tiwl_pcie_set_bits_mask(trans, reg, mask, 0);\n }\n \n-static inline void iwl_trans_set_bit(struct iwl_trans trans,\n+static inline void iwl_pcie_set_bit(struct iwl_trans trans,\n \t\t\t\t u32 reg, u32 mask)\n {\n-\t_iwl_trans_set_bits_mask(trans, reg, mask, mask);\n+\tiwl_pcie_set_bits_mask(trans, reg, mask, mask);\n }\n \n #endif / __iwl_pcie_utils_h__ */\n" }
2/1	2026/10/01 08:48	agent	patch-evaluator	0m Model: core Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The changes are strictly confined to the Intel wireless driver (iwlwifi), which drives vendor-specific Intel PCIe Wi-Fi adapters. Because standard virtualized environments (QEMU/GCE) lack emulation for this physical PCIe hardware, the modified driver code paths cannot be probed or executed during fuzzing, making them structurally unreachable.", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer and security engineer. Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on internal assumptions. You must actively use your code access tools to inspect the actual source code, callers, and surrounding context. ================================================================================ 1. CORE TRIAGE PHILOSOPHY ================================================================================ The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs, and newly triggered assertions introduced by the patch series. - REACHABILITY IS THE PRIMARY GATE: Fuzzing can only discover bugs in code that can actually execute in standard virtualized environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap). If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed, regardless of whether it adds assertions or complex logic. - DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS: Patch authors routinely label changes as "cleanups", "refactorings", or state "No functional change intended". Do NOT take these claims at face value. Code refactorings that rearrange logic, introduce helper functions, or alter state management in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs. If reachable executable code is modified or refactored, it MUST be fuzzed. - NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED: When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON, VM_WARN_ON, BUG_ON, lockdep_assert) in reachable code paths, it enforces new or stricter invariants. Even if the author believes the invariant always holds, fuzzing is essential to verify whether an unusual sequence of operations can violate it. ================================================================================ 2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA) ================================================================================ Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories: - Non-kernel and non-executable changes: * Modifications to Documentation/, comments, or spelling fixes. * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/) that do not affect the compiled kernel image (vmlinux) or kernel modules. * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints that do not alter control flow or data structures. * Build system or Kconfig changes that do not alter compiled C logic. - Structurally unreachable hardware: * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU. - Unreachable execution paths: * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during physical PCI hot-unplug or manual sysfs driver unbinding. * Code paths exclusive to architectures other than the target architecture. ================================================================================ 3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA) ================================================================================ Return WorthFuzzing=true whenever the patch touches reachable executable code, including: - Core Subsystems: * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/), BPF, scheduler, core networking, VFS, or syscall handling. - Refactorings and Code Cleanups: * Any restructuring of reachable data structures, helper abstractions, or algorithm flows. - Runtime Assertions and Defensive Checks: * Any introduction or alteration of assertions (WARN_ON, VM_WARN_ON, BUG_ON, etc.) in reachable paths. - Reachable Drivers and Protocols: Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.). ================================================================================ 4. EXTRACTING FocusSymbols (PREVENTING DILUTION) ================================================================================ When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer: - AVOID UBIQUITOUS LIFECYCLE HOT-PATHS: Do NOT list generic, ubiquitous functions called by almost every program in the corpus (including, but not limited to: general memory allocators and deallocators, page fault and trap handlers, or core synchronization primitives; this is not an exhaustive list). Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused", which severely dilutes fuzzing effort away from the actual changes. - TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS: List functions that specifically implement the logic being added or altered, or direct API entrypoints for the subsystem feature under review. - HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h): Compiler-inlined static functions (such as static inlines in mm/.h or include/linux/.h) lack distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters. If the changes are primarily in static inline helpers, identify non-static, feature-specific caller functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers). ================================================================================ 5. IDENTIFYING EnableConfigs ================================================================================ Identify any specific CONFIG_ options required to properly compile and reach the modified code: - Inspect Kconfig files and #ifdef guards; do not make assumptions. - Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed. - Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: Target architecture: amd64 For your convenience, here is the diff of the changes: commit 3f251a1e32cc7686e741e402cd3ebb5513c6fd71 Author: syz-cluster <triage@syzkaller.com> Date: Thu Oct 1 08:48:03 2026 +0000 syz-cluster: applied patch under review diff --git a/drivers/net/wireless/intel/iwlwifi/Makefile b/drivers/net/wireless/intel/iwlwifi/Makefile index 6746281350e0e..504381b4aac7c 100644 --- a/drivers/net/wireless/intel/iwlwifi/Makefile +++ b/drivers/net/wireless/intel/iwlwifi/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # common obj-$(CONFIG_IWLWIFI) += iwlwifi.o -iwlwifi-objs += iwl-io.o iwlwifi-objs += iwl-drv.o iwlwifi-objs += iwl-debug.o iwlwifi-objs += iwl-nvm-utils.o diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c index ec94c43ba28c1..799599efdd06e 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c @@ -2,7 +2,7 @@ /****************************************************************************** * * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. - * Copyright (C) 2018, 2025 Intel Corporation + * Copyright (C) 2018, 2025-2026 Intel Corporation ****************************************************************************/ #include <linux/slab.h> @@ -14,7 +14,6 @@ #include "iwl-debug.h" #include "iwl-trans.h" -#include "iwl-io.h" #include "dev.h" #include "agn.h" @@ -1788,7 +1787,7 @@ static ssize_t iwl_dbgfs_power_save_status_read(struct file file, const size_t bufsz = sizeof(buf); u32 pwrsave_status; - pwrsave_status = iwl_read32(priv->trans, CSR_GP_CNTRL) & + pwrsave_status = iwl_trans_read32(priv->trans, CSR_GP_CNTRL) & CSR_GP_REG_POWER_SAVE_STATUS_MSK; pos += scnprintf(buf + pos, bufsz - pos, "Power Save Status: "); diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/devices.c b/drivers/net/wireless/intel/iwlwifi/dvm/devices.c index 7f83f1bbdaad8..b7bd5e6deb5d1 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/devices.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/devices.c @@ -2,7 +2,7 @@ /****************************************************************************** * * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. - * Copyright (C) 2019, 2025 Intel Corporation + * Copyright (C) 2019, 2025-2026 Intel Corporation ****************************************************************************/ #include <linux/units.h> @@ -10,7 +10,7 @@ / * DVM device-specific data & functions / -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "iwl-nvm-utils.h" @@ -45,10 +45,10 @@ static void iwl1000_set_ct_threshold(struct iwl_priv priv) static void iwl1000_nic_config(struct iwl_priv priv) { / Setting digital SVR for 1000 card to 1.32V / - / locking is acquired in iwl_set_bits_mask_prph() function / - iwl_set_bits_mask_prph(priv->trans, APMG_DIGITAL_SVR_REG, - APMG_SVR_DIGITAL_VOLTAGE_1_32, - ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK); + / locking is acquired in iwl_trans_set_bits_mask_prph() function / + iwl_trans_set_bits_mask_prph(priv->trans, APMG_DIGITAL_SVR_REG, + APMG_SVR_DIGITAL_VOLTAGE_1_32, + ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK); } /* @@ -184,8 +184,8 @@ static void iwl2000_set_ct_threshold(struct iwl_priv priv) / NIC configuration for 2000 series / static void iwl2000_nic_config(struct iwl_priv priv) { - iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG, - CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER); + iwl_trans_set_bit(priv->trans, CSR_GP_DRIVER_REG, + CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER); } static const struct iwl_sensitivity_ranges iwl2000_sensitivity = { @@ -490,22 +490,22 @@ static void iwl6000_nic_config(struct iwl_priv priv) break; case IWL_DEVICE_FAMILY_6000i: / 2x2 IPA phy type / - iwl_write32(priv->trans, CSR_GP_DRIVER_REG, - CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA); + iwl_trans_write32(priv->trans, CSR_GP_DRIVER_REG, + CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA); break; case IWL_DEVICE_FAMILY_6050: / Indicate calibration version to uCode. / if (priv->nvm_data->calib_version >= 6) - iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG, - CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6); + iwl_trans_set_bit(priv->trans, CSR_GP_DRIVER_REG, + CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6); break; case IWL_DEVICE_FAMILY_6150: / Indicate calibration version to uCode. / if (priv->nvm_data->calib_version >= 6) - iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG, - CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6); - iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG, - CSR_GP_DRIVER_REG_BIT_6050_1x2); + iwl_trans_set_bit(priv->trans, CSR_GP_DRIVER_REG, + CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6); + iwl_trans_set_bit(priv->trans, CSR_GP_DRIVER_REG, + CSR_GP_DRIVER_REG_BIT_6050_1x2); break; default: WARN_ON(1); diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c b/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c index 6de2517188f73..190e482849ac2 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / - * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2025 Intel Corporation + * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2026 Intel Corporation / #include <linux/types.h> #include <linux/slab.h> @@ -8,7 +8,7 @@ #include "iwl-drv.h" #include "iwl-debug.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "iwl-csr.h" #include "agn.h" @@ -672,13 +672,13 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans trans) for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) { /* Request semaphore / - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM); / See if we got it / - ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM, - IWL_EEPROM_SEM_TIMEOUT); + ret = iwl_trans_poll_bits(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM, + IWL_EEPROM_SEM_TIMEOUT); if (!ret) { IWL_DEBUG_EEPROM(trans->dev, "Acquired semaphore after %d tries.\n", @@ -692,13 +692,13 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans trans) static void iwl_eeprom_release_semaphore(struct iwl_trans trans) { - iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM); + iwl_trans_clear_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM); } static int iwl_eeprom_verify_signature(struct iwl_trans trans, bool nvm_is_otp) { - u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; + u32 gp = iwl_trans_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp); @@ -734,10 +734,10 @@ static int iwl_eeprom_verify_signature(struct iwl_trans trans, bool nvm_is_otp) static void iwl_set_otp_access_absolute(struct iwl_trans trans) { - iwl_read32(trans, CSR_OTP_GP_REG); + iwl_trans_read32(trans, CSR_OTP_GP_REG); - iwl_clear_bit(trans, CSR_OTP_GP_REG, - CSR_OTP_GP_REG_OTP_ACCESS_MODE); + iwl_trans_clear_bit(trans, CSR_OTP_GP_REG, + CSR_OTP_GP_REG_OTP_ACCESS_MODE); } static int iwl_nvm_is_otp(struct iwl_trans trans) @@ -755,7 +755,7 @@ static int iwl_nvm_is_otp(struct iwl_trans trans) case CSR_HW_REV_TYPE_5150: return 0; default: - otpgp = iwl_read32(trans, CSR_OTP_GP_REG); + otpgp = iwl_trans_read32(trans, CSR_OTP_GP_REG); if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) return 1; return 0; @@ -770,19 +770,19 @@ static int iwl_init_otp_access(struct iwl_trans trans) if (ret) return ret; - iwl_set_bits_prph(trans, APMG_PS_CTRL_REG, - APMG_PS_CTRL_VAL_RESET_REQ); + iwl_trans_set_bits_prph(trans, APMG_PS_CTRL_REG, + APMG_PS_CTRL_VAL_RESET_REQ); udelay(5); - iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG, - APMG_PS_CTRL_VAL_RESET_REQ); + iwl_trans_clear_bits_prph(trans, APMG_PS_CTRL_REG, + APMG_PS_CTRL_VAL_RESET_REQ); / * CSR auto clock gate disable bit - * this is only applicable for HW with OTP shadow RAM / if (trans->mac_cfg->base->shadow_ram_support) - iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, - CSR_RESET_LINK_PWR_MGMT_DISABLED); + iwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, + CSR_RESET_LINK_PWR_MGMT_DISABLED); return 0; } @@ -794,31 +794,31 @@ static int iwl_read_otp_word(struct iwl_trans trans, u16 addr, u32 r; u32 otpgp; - iwl_write32(trans, CSR_EEPROM_REG, - CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); - ret = iwl_poll_bits(trans, CSR_EEPROM_REG, - CSR_EEPROM_REG_READ_VALID_MSK, - IWL_EEPROM_ACCESS_TIMEOUT); + iwl_trans_write32(trans, CSR_EEPROM_REG, + CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); + ret = iwl_trans_poll_bits(trans, CSR_EEPROM_REG, + CSR_EEPROM_REG_READ_VALID_MSK, + IWL_EEPROM_ACCESS_TIMEOUT); if (ret) { IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); return ret; } - r = iwl_read32(trans, CSR_EEPROM_REG); + r = iwl_trans_read32(trans, CSR_EEPROM_REG); /* check for ECC errors: / - otpgp = iwl_read32(trans, CSR_OTP_GP_REG); + otpgp = iwl_trans_read32(trans, CSR_OTP_GP_REG); if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { / stop in this case / / set the uncorrectable OTP ECC bit for acknowledgment / - iwl_set_bit(trans, CSR_OTP_GP_REG, - CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); + iwl_trans_set_bit(trans, CSR_OTP_GP_REG, + CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); return -EINVAL; } if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { / continue in this case / / set the correctable OTP ECC bit for acknowledgment / - iwl_set_bit(trans, CSR_OTP_GP_REG, - CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); + iwl_trans_set_bit(trans, CSR_OTP_GP_REG, + CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); IWL_ERR(trans, "Correctable OTP ECC error, continue read\n"); } eeprom_data = cpu_to_le16(r >> 16); @@ -918,7 +918,7 @@ static int iwl_find_otp_image(struct iwl_trans trans, int iwl_read_eeprom(struct iwl_trans trans, u8 *eeprom, size_t eeprom_size) { __le16 e; - u32 gp = iwl_read32(trans, CSR_EEPROM_GP); + u32 gp = iwl_trans_read32(trans, CSR_EEPROM_GP); int sz; int ret; u16 addr; @@ -960,13 +960,13 @@ int iwl_read_eeprom(struct iwl_trans trans, u8 *eeprom, size_t eeprom_size) goto err_unlock; } - iwl_write32(trans, CSR_EEPROM_GP, - iwl_read32(trans, CSR_EEPROM_GP) & - ~CSR_EEPROM_GP_IF_OWNER_MSK); + iwl_trans_write32(trans, CSR_EEPROM_GP, + iwl_trans_read32(trans, CSR_EEPROM_GP) & + ~CSR_EEPROM_GP_IF_OWNER_MSK); - iwl_set_bit(trans, CSR_OTP_GP_REG, - CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK \| - CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); + iwl_trans_set_bit(trans, CSR_OTP_GP_REG, + CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK \| + CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); /* traversing the linked list if no shadow ram supported / if (!trans->mac_cfg->base->shadow_ram_support) { ret = iwl_find_otp_image(trans, &validblockaddr); @@ -988,18 +988,18 @@ int iwl_read_eeprom(struct iwl_trans trans, u8 *eeprom, size_t eeprom_size) for (addr = 0; addr < sz; addr += sizeof(u16)) { u32 r; - iwl_write32(trans, CSR_EEPROM_REG, - CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); + iwl_trans_write32(trans, CSR_EEPROM_REG, + CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); - ret = iwl_poll_bits(trans, CSR_EEPROM_REG, - CSR_EEPROM_REG_READ_VALID_MSK, - IWL_EEPROM_ACCESS_TIMEOUT); + ret = iwl_trans_poll_bits(trans, CSR_EEPROM_REG, + CSR_EEPROM_REG_READ_VALID_MSK, + IWL_EEPROM_ACCESS_TIMEOUT); if (ret) { IWL_ERR(trans, "Time out reading EEPROM[%d]\n", addr); goto err_unlock; } - r = iwl_read32(trans, CSR_EEPROM_REG); + r = iwl_trans_read32(trans, CSR_EEPROM_REG); e[addr / 2] = cpu_to_le16(r >> 16); } } diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/led.c b/drivers/net/wireless/intel/iwlwifi/dvm/led.c index cec2ebdfd6519..17b045ddb910c 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/led.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/led.c @@ -2,7 +2,7 @@ /****************************************************************************** * * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. - * Copyright (C) 2019, 2025 Intel Corporation + * Copyright (C) 2019, 2025-2026 Intel Corporation ****************************************************************************/ @@ -14,7 +14,6 @@ #include <net/mac80211.h> #include <linux/etherdevice.h> #include <linux/unaligned.h> -#include "iwl-io.h" #include "iwl-trans.h" #include "iwl-modparams.h" #include "dev.h" @@ -49,7 +48,7 @@ static const struct ieee80211_tpt_blink iwl_blink[] = { / Set led register off / void iwlagn_led_enable(struct iwl_priv priv) { - iwl_write32(priv->trans, CSR_LED_REG, CSR_LED_REG_TURN_ON); + iwl_trans_write32(priv->trans, CSR_LED_REG, CSR_LED_REG_TURN_ON); } /* @@ -85,10 +84,10 @@ static int iwl_send_led_cmd(struct iwl_priv priv, struct iwl_led_cmd led_cmd) }; u32 reg; - reg = iwl_read32(priv->trans, CSR_LED_REG); + reg = iwl_trans_read32(priv->trans, CSR_LED_REG); if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) - iwl_write32(priv->trans, CSR_LED_REG, - reg & CSR_LED_BSM_CTRL_MSK); + iwl_trans_write32(priv->trans, CSR_LED_REG, + reg & CSR_LED_BSM_CTRL_MSK); return iwl_dvm_send_cmd(priv, &cmd); } diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/lib.c b/drivers/net/wireless/intel/iwlwifi/dvm/lib.c index 2e16799818e47..37d6f2cf7efb7 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/lib.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/lib.c @@ -2,6 +2,7 @@ /****************************************************************************** * * Copyright(c) 2008 - 2014, 2022 Intel Corporation. All rights reserved. + * Copyright (C) 2026 Intel Corporation ***************************************************************************/ #include <linux/etherdevice.h> #include <linux/kernel.h> @@ -9,7 +10,6 @@ #include <linux/sched.h> #include <net/mac80211.h> -#include "iwl-io.h" #include "iwl-agn-hw.h" #include "iwl-trans.h" #include "iwl-modparams.h" diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c index a0a26ef482a5e..e83bf615c1617 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c @@ -2,7 +2,7 @@ /**************************************************************************** * * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. - * Copyright(C) 2018 - 2019, 2022 - 2025 Intel Corporation + * Copyright(C) 2018 - 2019, 2022 - 2026 Intel Corporation * * Portions of this file are derived from the ipw3945 project, as well * as portions of the ieee80211 subsystem header files. @@ -23,7 +23,6 @@ #include <asm/div64.h> -#include "iwl-io.h" #include "iwl-trans.h" #include "iwl-op-mode.h" #include "iwl-modparams.h" @@ -375,8 +374,8 @@ static int iwlagn_mac_suspend(struct ieee80211_hw hw, goto error; / let the ucode operate on its own / - iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET, - CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); + iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_SET, + CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); iwl_trans_d3_suspend(priv->trans, true); @@ -455,8 +454,8 @@ static int iwlagn_mac_resume(struct ieee80211_hw hw) goto out_unlock; /* uCode is no longer operating by itself / - iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR, - CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); + iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR, + CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); base = priv->device_pointers.error_event_table; if (!iwlagn_hw_valid_rtc_data_addr(base)) { diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/main.c b/drivers/net/wireless/intel/iwlwifi/dvm/main.c index 6bd5b6d84b2a9..4bf69f7a35a64 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/main.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/main.c @@ -2,7 +2,7 @@ /***************************************************************************** * * Copyright(c) 2003 - 2014, 2018 - 2022 Intel Corporation. All rights reserved. - * Copyright(c) 2024-2025 Intel Corporation. All rights reserved. + * Copyright(c) 2024-2026 Intel Corporation. All rights reserved. * Copyright(c) 2015 Intel Deutschland GmbH * * Portions of this file are derived from the ipw3945 project, as well @@ -27,8 +27,8 @@ #include <asm/div64.h> #include "iwl-nvm-utils.h" -#include "iwl-io.h" #include "iwl-trans.h" +#include "iwl-devtrace.h" #include "iwl-op-mode.h" #include "iwl-drv.h" #include "iwl-modparams.h" @@ -413,7 +413,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv priv, u32 base, return; / Set starting address; reads will auto-increment / - iwl_write32(priv->trans, HBUS_TARG_MEM_RADDR, ptr); + iwl_trans_write32(priv->trans, HBUS_TARG_MEM_RADDR, ptr); / * Refuse to read more than would have fit into the log from @@ -429,13 +429,13 @@ static void iwl_print_cont_event_trace(struct iwl_priv priv, u32 base, place event id # at far right for easier visual parsing. / for (i = 0; i < num_events; i++) { - ev = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT); - time = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT); + ev = iwl_trans_read32(priv->trans, HBUS_TARG_MEM_RDAT); + time = iwl_trans_read32(priv->trans, HBUS_TARG_MEM_RDAT); if (mode == 0) { trace_iwlwifi_dev_ucode_cont_event( priv->trans->dev, 0, time, ev); } else { - data = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT); + data = iwl_trans_read32(priv->trans, HBUS_TARG_MEM_RDAT); trace_iwlwifi_dev_ucode_cont_event( priv->trans->dev, time, data, ev); } @@ -661,8 +661,8 @@ static void iwl_rf_kill_ct_config(struct iwl_priv priv) struct iwl_ct_kill_throttling_config adv_cmd; int ret = 0; - iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR, - CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); + iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR, + CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); priv->thermal_throttle.ct_kill_toggle = false; @@ -1731,13 +1731,13 @@ static int iwl_print_event_log(struct iwl_priv priv, u32 start_idx, return pos; / Set starting address; reads will auto-increment / - iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr); + iwl_trans_write32(trans, HBUS_TARG_MEM_RADDR, ptr); / "time" is actually "data" for mode 0 (no timestamp). * place event id # at far right for easier visual parsing. / for (i = 0; i < num_events; i++) { - ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT); - time = iwl_read32(trans, HBUS_TARG_MEM_RDAT); + ev = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT); + time = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT); if (mode == 0) { / data, ev / if (bufsz) { @@ -1751,7 +1751,7 @@ static int iwl_print_event_log(struct iwl_priv priv, u32 start_idx, time, ev); } } else { - data = iwl_read32(trans, HBUS_TARG_MEM_RDAT); + data = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT); if (bufsz) { pos += scnprintf(buf + pos, bufsz - pos, "EVT_LOGT:%010u:0x%08x:%04u\n", @@ -2028,17 +2028,17 @@ static void iwl_nic_config(struct iwl_op_mode op_mode) } /* set CSR_HW_CONFIG_REG for uCode use / - iwl_set_bit(priv->trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI \| - CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); + iwl_trans_set_bit(priv->trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI \| + CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); / W/A : NIC is stuck in a reset state after Early PCIe power off * (PCIe power is lost before PERST# is asserted), * causing ME FW to lose ownership and not being able to obtain it back. / - iwl_set_bits_mask_prph(priv->trans, APMG_PS_CTRL_REG, - APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, - ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); + iwl_trans_set_bits_mask_prph(priv->trans, APMG_PS_CTRL_REG, + APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, + ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); if (priv->lib->nic_config) priv->lib->nic_config(priv); diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/power.c b/drivers/net/wireless/intel/iwlwifi/dvm/power.c index e7dbba7134f72..4e19799d15d75 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/power.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/power.c @@ -2,7 +2,7 @@ /***************************************************************************** * * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. - * Copyright (C) 2019, 2025 Intel Corporation + * Copyright (C) 2019, 2025-2026 Intel Corporation * * Portions of this file are derived from the ipw3945 project, as well * as portions of the ieee80211 subsystem header files. @@ -13,7 +13,6 @@ #include <linux/module.h> #include <linux/slab.h> #include <net/mac80211.h> -#include "iwl-io.h" #include "iwl-debug.h" #include "iwl-trans.h" #include "iwl-modparams.h" diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/rx.c b/drivers/net/wireless/intel/iwlwifi/dvm/rx.c index 088302a238dec..fa2aff5bea6c0 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/rx.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/rx.c @@ -3,7 +3,7 @@ * * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. * Copyright(c) 2015 Intel Deutschland GmbH - * Copyright(c) 2018, 2020-2021, 2025 Intel Corporation + * Copyright(c) 2018, 2020-2021, 2025-2026 Intel Corporation * * Portions of this file are derived from the ipw3945 project, as well * as portionhelp of the ieee80211 subsystem header files. @@ -16,7 +16,6 @@ #include <linux/unaligned.h> #include "iwl-trans.h" -#include "iwl-io.h" #include "dev.h" #include "calib.h" #include "agn.h" @@ -482,17 +481,17 @@ static void iwlagn_rx_card_state_notif(struct iwl_priv priv, if (flags & (SW_CARD_DISABLED \| HW_CARD_DISABLED \| CT_CARD_DISABLED)) { - iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET, - CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); + iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_SET, + CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); - iwl_write_direct32(priv->trans, HBUS_TARG_MBX_C, - HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); + iwl_trans_write_direct32(priv->trans, HBUS_TARG_MBX_C, + HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); if (!(flags & RXON_CARD_DISABLED)) { - iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR, - CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); - iwl_write_direct32(priv->trans, HBUS_TARG_MBX_C, - HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); + iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR, + CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); + iwl_trans_write_direct32(priv->trans, HBUS_TARG_MBX_C, + HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); } if (flags & CT_CARD_DISABLED) iwl_tt_enter_ct_kill(priv); diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/tt.c b/drivers/net/wireless/intel/iwlwifi/dvm/tt.c index fc9cf0531024a..a414eb7c24460 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/tt.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/tt.c @@ -2,7 +2,7 @@ /***************************************************************************** * * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. - * Copyright (C) 2018, 2020 Intel Corporation + * Copyright (C) 2018, 2020, 2026 Intel Corporation * * Portions of this file are derived from the ipw3945 project, as well * as portions of the ieee80211 subsystem header files. @@ -13,7 +13,7 @@ #include <linux/module.h> #include <linux/slab.h> #include <net/mac80211.h> -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-modparams.h" #include "iwl-debug.h" #include "agn.h" @@ -146,15 +146,15 @@ static void iwl_tt_check_exit_ct_kill(struct timer_list t) if (tt->state == IWL_TI_CT_KILL) { if (priv->thermal_throttle.ct_kill_toggle) { - iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR, - CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); + iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR, + CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); priv->thermal_throttle.ct_kill_toggle = false; } else { - iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET, - CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); + iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_SET, + CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); priv->thermal_throttle.ct_kill_toggle = true; } - iwl_read32(priv->trans, CSR_UCODE_DRV_GP1); + iwl_trans_read32(priv->trans, CSR_UCODE_DRV_GP1); if (iwl_trans_grab_nic_access(priv->trans)) iwl_trans_release_nic_access(priv->trans); diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/tx.c b/drivers/net/wireless/intel/iwlwifi/dvm/tx.c index 1a0167f67c7bd..8dbc52971e7bb 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/tx.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/tx.c @@ -3,14 +3,13 @@ * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. * Copyright (C) 2019 Intel Corporation - * Copyright (C) 2023, 2025 Intel Corporation + * Copyright (C) 2023, 2025-2026 Intel Corporation ****************************************************************************/ #include <linux/kernel.h> #include <linux/module.h> #include <linux/sched.h> #include <linux/ieee80211.h> -#include "iwl-io.h" #include "iwl-trans.h" #include "iwl-agn-hw.h" #include "dev.h" diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c b/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c index ac90191a39735..2ab1a32d774e5 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c @@ -3,12 +3,11 @@ * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. * Copyright(c) 2015 Intel Deutschland GmbH - * Copyright (C) 2025 Intel Corporation + * Copyright (C) 2025-2026 Intel Corporation ****************************************************************************/ #include <linux/kernel.h> -#include "iwl-io.h" #include "iwl-agn-hw.h" #include "iwl-trans.h" #include "iwl-fh.h" diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h index d3bed0216df48..9f7407c4f980c 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h @@ -1,6 +1,6 @@ / SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / / - * Copyright (C) 2012-2014, 2018-2025 Intel Corporation + * Copyright (C) 2012-2014, 2018-2026 Intel Corporation * Copyright (C) 2013-2014 Intel Mobile Communications GmbH * Copyright (C) 2015-2017 Intel Deutschland GmbH / @@ -366,7 +366,6 @@ enum iwl_wowlan_flags { ENABLE_L3_FILTERING = BIT(1), ENABLE_NBNS_FILTERING = BIT(2), ENABLE_DHCP_FILTERING = BIT(3), - ENABLE_STORE_BEACON = BIT(4), HAS_BEACON_PROTECTION = BIT(5), }; diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h index 31d3336726b42..9d9eb320db7b0 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h @@ -1,6 +1,6 @@ / SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / / - * Copyright (C) 2012-2014, 2018-2025 Intel Corporation + * Copyright (C) 2012-2014, 2018-2026 Intel Corporation * Copyright (C) 2016-2017 Intel Deutschland GmbH / #ifndef __iwl_fw_api_tx_h__ @@ -292,6 +292,9 @@ struct iwl_tx_cmd_v9 { @dram_info: FW internal DRAM storage * @rate_n_flags: rate for all Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is * cleared. Combination of RATE_MCS_; format depends on version + @driver_timestamp: gp2 time, in microseconds, assigned before queueing the + * MPDU. Firmware uses it to detect frames blocked for too long. + * Zero means no timestamp. Used from TX_CMD_API_S_VER_12. * @reserved: reserved * @hdr: 802.11 header / @@ -301,10 +304,12 @@ struct iwl_tx_cmd { __le32 offload_assist; struct iwl_dram_sec_info dram_info; __le32 rate_n_flags; - u8 reserved[8]; + __le32 driver_timestamp; + u8 reserved[4]; struct ieee80211_hdr hdr[]; } __packed; / TX_CMD_API_S_VER_10, - * TX_CMD_API_S_VER_11 + * TX_CMD_API_S_VER_11, + * TX_CMD_API_S_VER_12 / / diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c index 19b1bfd0abee4..09c798d2eba33 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c +++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c @@ -9,7 +9,7 @@ #include "runtime.h" #include "dbg.h" #include "debugfs.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "iwl-csr.h" #include "iwl-fh.h" @@ -47,8 +47,8 @@ static void iwl_read_radio_regs(struct iwl_fw_runtime fwrt, u32 rd_cmd = RADIO_RSP_RD_CMD; rd_cmd \|= i << RADIO_RSP_ADDR_POS; - iwl_trans_write_prph(fwrt->trans, RSP_RADIO_CMD, rd_cmd); - pos = (u8)iwl_trans_read_prph(fwrt->trans, RSP_RADIO_RDDAT); + iwl_trans_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); + pos = (u8)iwl_trans_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); pos++; } @@ -81,35 +81,35 @@ static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime fwrt, fifo_hdr->fifo_num = cpu_to_le32(fifo_num); fifo_hdr->available_bytes = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - RXF_RD_D_SPACE + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + RXF_RD_D_SPACE + offset)); fifo_hdr->wr_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - RXF_RD_WR_PTR + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + RXF_RD_WR_PTR + offset)); fifo_hdr->rd_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - RXF_RD_RD_PTR + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + RXF_RD_RD_PTR + offset)); fifo_hdr->fence_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - RXF_RD_FENCE_PTR + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + RXF_RD_FENCE_PTR + offset)); fifo_hdr->fence_mode = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - RXF_SET_FENCE_MODE + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + RXF_SET_FENCE_MODE + offset)); /* Lock fence / - iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); + iwl_trans_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); / Set fence pointer to the same place like WR pointer / - iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); + iwl_trans_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); / Set fence offset / - iwl_trans_write_prph(fwrt->trans, - RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); + iwl_trans_write_prph_no_grab(fwrt->trans, + RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); / Read FIFO / fifo_len /= sizeof(u32); / Size in DWORDS / for (i = 0; i < fifo_len; i++) - fifo_data[i] = iwl_trans_read_prph(fwrt->trans, - RXF_FIFO_RD_FENCE_INC + - offset); + fifo_data[i] = iwl_trans_read_prph_no_grab(fwrt->trans, + RXF_FIFO_RD_FENCE_INC + + offset); dump_data = iwl_fw_error_next_data(dump_data); } @@ -136,33 +136,33 @@ static void iwl_fwrt_dump_txf(struct iwl_fw_runtime fwrt, fifo_hdr->fifo_num = cpu_to_le32(fifo_num); fifo_hdr->available_bytes = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_FIFO_ITEM_CNT + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_FIFO_ITEM_CNT + offset)); fifo_hdr->wr_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_WR_PTR + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_WR_PTR + offset)); fifo_hdr->rd_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_RD_PTR + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_RD_PTR + offset)); fifo_hdr->fence_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_FENCE_PTR + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_FENCE_PTR + offset)); fifo_hdr->fence_mode = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_LOCK_FENCE + offset)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_LOCK_FENCE + offset)); /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR / - iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, - TXF_WR_PTR + offset); + iwl_trans_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, + TXF_WR_PTR + offset); / Dummy-read to advance the read pointer to the head / - iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); + iwl_trans_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offset); / Read FIFO / for (i = 0; i < fifo_len / sizeof(u32); i++) - fifo_data[i] = iwl_trans_read_prph(fwrt->trans, - TXF_READ_MODIFY_DATA + - offset); + fifo_data[i] = iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_READ_MODIFY_DATA + + offset); if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, @@ -217,7 +217,7 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime fwrt, /* Pull TXF data from LMAC1 / for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { / Mark the number of TXF we're pulling now / - iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); + iwl_trans_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM, i); iwl_fwrt_dump_txf(fwrt, dump_data, cfg->lmac[0].txfifo_size[i], 0, i); } @@ -227,9 +227,9 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime fwrt, for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { /* Mark the number of TXF we're pulling now / - iwl_trans_write_prph(fwrt->trans, - TXF_LARC_NUM + - LMAC2_PRPH_OFFSET, i); + iwl_trans_write_prph_no_grab(fwrt->trans, + TXF_LARC_NUM + + LMAC2_PRPH_OFFSET, i); iwl_fwrt_dump_txf(fwrt, dump_data, cfg->lmac[1].txfifo_size[i], LMAC2_PRPH_OFFSET, @@ -262,40 +262,40 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime fwrt, fifo_hdr->fifo_num = cpu_to_le32(i); /* Mark the number of TXF we're pulling now / - iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + - fwrt->smem_cfg.num_txfifo_entries); + iwl_trans_write_prph_no_grab(fwrt->trans, TXF_CPU2_NUM, i + + fwrt->smem_cfg.num_txfifo_entries); fifo_hdr->available_bytes = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_CPU2_FIFO_ITEM_CNT)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_CPU2_FIFO_ITEM_CNT)); fifo_hdr->wr_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_CPU2_WR_PTR)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_CPU2_WR_PTR)); fifo_hdr->rd_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_CPU2_RD_PTR)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_CPU2_RD_PTR)); fifo_hdr->fence_ptr = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_CPU2_FENCE_PTR)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_CPU2_FENCE_PTR)); fifo_hdr->fence_mode = - cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - TXF_CPU2_LOCK_FENCE)); + cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_CPU2_LOCK_FENCE)); / Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR / - iwl_trans_write_prph(fwrt->trans, - TXF_CPU2_READ_MODIFY_ADDR, - TXF_CPU2_WR_PTR); + iwl_trans_write_prph_no_grab(fwrt->trans, + TXF_CPU2_READ_MODIFY_ADDR, + TXF_CPU2_WR_PTR); / Dummy-read to advance the read pointer to head / - iwl_trans_read_prph(fwrt->trans, - TXF_CPU2_READ_MODIFY_DATA); + iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_CPU2_READ_MODIFY_DATA); / Read FIFO / fifo_len /= sizeof(u32); / Size in DWORDS / for (j = 0; j < fifo_len; j++) fifo_data[j] = - iwl_trans_read_prph(fwrt->trans, - TXF_CPU2_READ_MODIFY_DATA); + iwl_trans_read_prph_no_grab(fwrt->trans, + TXF_CPU2_READ_MODIFY_DATA); dump_data = iwl_fw_error_next_data(dump_data); } } @@ -514,7 +514,7 @@ static void iwl_read_prph_block(struct iwl_trans trans, u32 start, u32 i; for (i = 0; i < len_bytes; i += 4) - data++ = cpu_to_le32(iwl_trans_read_prph(trans, start + i)); + data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(trans, start + i)); } static void iwl_dump_prph(struct iwl_fw_runtime fwrt, diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c index 897538066b7de..1d34ad59bb71f 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c +++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c @@ -9,7 +9,7 @@ #include "runtime.h" #include "dbg.h" #include "debugfs.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "iwl-csr.h" #include "iwl-fh.h" @@ -103,7 +103,7 @@ static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime fwrt, range->internal_base_addr = cpu_to_le32(addr); range->range_data_size = size; for (i = 0; i < le32_to_cpu(size); i += 4) - val++ = cpu_to_le32(iwl_trans_read_prph(fwrt->trans, addr + i)); + val++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, addr + i)); return sizeof(range) + le32_to_cpu(range->range_data_size); } @@ -159,7 +159,7 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime fwrt, indirect_rd_addr += le32_to_cpu(offset); dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; - dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); + dphy_state = iwl_trans_read_umac_prph_no_grab(fwrt->trans, dphy_addr); for (i = 0; i < le32_to_cpu(size); i += 4) { if (dphy_state == HBUS_TIMEOUT \|\| @@ -169,16 +169,16 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime fwrt, continue; } - iwl_trans_write_prph(fwrt->trans, indirect_wr_addr, - WMAL_INDRCT_CMD(addr + i)); + iwl_trans_write_prph_no_grab(fwrt->trans, indirect_wr_addr, + WMAL_INDRCT_CMD(addr + i)); if (fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_JF1 && fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_JF2 && fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_HR1 && fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_HR2) { udelay(2); - prph_stts = iwl_trans_read_prph(fwrt->trans, - WMAL_MRSPF_STTS); + prph_stts = iwl_trans_read_prph_no_grab(fwrt->trans, + WMAL_MRSPF_STTS); / Abort dump if status is 0xA5A5A5A2 or FIFO1 empty / if (prph_stts == WMAL_TIMEOUT_VAL \|\| @@ -186,8 +186,8 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime fwrt, break; } - prph_val = iwl_trans_read_prph(fwrt->trans, - indirect_rd_addr); + prph_val = iwl_trans_read_prph_no_grab(fwrt->trans, + indirect_rd_addr); val++ = cpu_to_le32(prph_val); } @@ -446,7 +446,7 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime fwrt, range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); - iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); + iwl_trans_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); /* * read txf registers. for each register, write to the dump the @@ -456,8 +456,8 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime fwrt, addr = le32_to_cpu(reg->addrs[i]) + offs; reg_dump->addr = cpu_to_le32(addr); - reg_dump->data = cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - addr)); + reg_dump->data = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + addr)); reg_dump++; } @@ -468,17 +468,17 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime fwrt, } /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR / - iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, - TXF_WR_PTR + offs); + iwl_trans_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, + TXF_WR_PTR + offs); / Dummy-read to advance the read pointer to the head / - iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offs); + iwl_trans_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); / Read FIFO / addr = TXF_READ_MODIFY_DATA + offs; data = (void )reg_dump; for (i = 0; i < iter->fifo_size; i += sizeof(data)) - data++ = cpu_to_le32(iwl_trans_read_prph(fwrt->trans, addr)); + data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, addr)); if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, @@ -508,7 +508,7 @@ iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime fwrt, indirect_rd_wr_addr += le32_to_cpu(offset); dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; - dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); + dphy_state = iwl_trans_read_umac_prph_no_grab(fwrt->trans, dphy_addr); for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { if (dphy_state == HBUS_TIMEOUT \|\| @@ -518,12 +518,12 @@ iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime fwrt, continue; } - iwl_trans_write_prph(fwrt->trans, indirect_rd_wr_addr, - addr + i); + iwl_trans_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr, + addr + i); / wait a bit for value to be ready in register / udelay(1); - prph_val = iwl_trans_read_prph(fwrt->trans, - indirect_rd_wr_addr); + prph_val = iwl_trans_read_prph_no_grab(fwrt->trans, + indirect_rd_wr_addr); val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >> DPHYIP_INDIRECT_RD_SHIFT); } @@ -586,13 +586,13 @@ static void iwl_ini_get_rxf_data(struct iwl_fw_runtime fwrt, switch (fifo_idx) { case 0: data->size = fwrt->smem_cfg.rxfifo2_size; - data->offset = iwl_umac_prph(fwrt->trans, - RXF_DIFF_FROM_PREV); + data->offset = iwl_trans_umac_prph(fwrt->trans, + RXF_DIFF_FROM_PREV); break; case 1: data->size = fwrt->smem_cfg.rxfifo2_control_size; - data->offset = iwl_umac_prph(fwrt->trans, - RXF2C_DIFF_FROM_PREV); + data->offset = iwl_trans_umac_prph(fwrt->trans, + RXF2C_DIFF_FROM_PREV); break; } } @@ -628,8 +628,8 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime fwrt, addr = le32_to_cpu(reg->addrs[i]) + offs; reg_dump->addr = cpu_to_le32(addr); - reg_dump->data = cpu_to_le32(iwl_trans_read_prph(fwrt->trans, - addr)); + reg_dump->data = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, + addr)); reg_dump++; } @@ -642,17 +642,17 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime fwrt, offs = rxf_data.offset; / Lock fence / - iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); + iwl_trans_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); / Set fence pointer to the same place like WR pointer / - iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); + iwl_trans_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); / Set fence offset / - iwl_trans_write_prph(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 0x0); + iwl_trans_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 0x0); / Read FIFO / addr = RXF_FIFO_RD_FENCE_INC + offs; data = (void )reg_dump; for (i = 0; i < rxf_data.size; i += sizeof(data)) - data++ = cpu_to_le32(iwl_trans_read_prph(fwrt->trans, addr)); + data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, addr)); out: return sizeof(range) + le32_to_cpu(range->range_data_size); @@ -712,10 +712,10 @@ iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime fwrt, range->range_data_size = reg->dev_addr.size; for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { prph_data = - iwl_trans_read_prph(fwrt->trans, - (i % 2) ? - DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : - DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); + iwl_trans_read_prph_no_grab(fwrt->trans, + (i % 2) ? + DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : + DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); if (iwl_trans_is_hw_error_value(prph_data)) return -EBUSY; val++ = cpu_to_le32(prph_data); @@ -812,7 +812,7 @@ static __le32 iwl_get_mon_reg(struct iwl_fw_runtime fwrt, u32 alloc_id, if (!reg_info \|\| !reg_info->addr \|\| !reg_info->mask) return 0; - val = iwl_trans_read_prph(fwrt->trans, reg_info->addr + offs); + val = iwl_trans_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); } @@ -1820,14 +1820,14 @@ static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime fwrt, cpu_to_le32(IWL_FW_INI_APPLY_POLICY_SPLIT_DUMP_RESET)) { size += iwl_dump_ini_dump_entries(fwrt, list, IWL_INI_DUMP_EARLY_REGIONS); - iwl_trans_pcie_fw_reset_handshake(fwrt->trans); + iwl_trans_fw_reset_handshake(fwrt->trans); size += iwl_dump_ini_dump_entries(fwrt, list, IWL_INI_DUMP_LATE_REGIONS); } else { if (fw_has_capa(&fwrt->fw->ucode_capa, IWL_UCODE_TLV_CAPA_RESET_DURING_ASSERT) && iwl_dump_due_to_error(tp_id)) - iwl_trans_pcie_fw_reset_handshake(fwrt->trans); + iwl_trans_fw_reset_handshake(fwrt->trans); size += iwl_dump_ini_dump_entries(fwrt, list, IWL_INI_DUMP_ALL_REGIONS); } @@ -2381,21 +2381,21 @@ static void iwl_fw_dbg_stop_recording(struct iwl_trans trans, struct iwl_fw_dbg_params params) { if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) { - iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); + iwl_trans_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); return; } if (params) { - params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); - params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); + params->in_sample = iwl_trans_read_umac_prph(trans, DBGC_IN_SAMPLE); + params->out_ctrl = iwl_trans_read_umac_prph(trans, DBGC_OUT_CTRL); } - iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); + iwl_trans_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); /* wait for the DBGC to finish writing the internal buffer to DRAM to * avoid halting the HW while writing / usleep_range(700, 1000); - iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); + iwl_trans_write_umac_prph(trans, DBGC_OUT_CTRL, 0); } static int iwl_fw_dbg_restart_recording(struct iwl_trans trans, @@ -2405,12 +2405,12 @@ static int iwl_fw_dbg_restart_recording(struct iwl_trans trans, return -EIO; if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) { - iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); - iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); - iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); + iwl_trans_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); + iwl_trans_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); + iwl_trans_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); } else { - iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); - iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); + iwl_trans_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); + iwl_trans_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); } return 0; diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h index fc962a3205833..70134d8f03c4d 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h @@ -10,7 +10,7 @@ #include <net/cfg80211.h> #include "runtime.h" #include "iwl-prph.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "file.h" #include "error-dump.h" #include "api/commands.h" diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dump.c b/drivers/net/wireless/intel/iwlwifi/fw/dump.c index bbbf3669a555d..b76abc77f4959 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/dump.c +++ b/drivers/net/wireless/intel/iwlwifi/fw/dump.c @@ -9,7 +9,7 @@ #include "runtime.h" #include "dbg.h" #include "debugfs.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "iwl-csr.h" #include "pnvm.h" @@ -309,7 +309,7 @@ static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime fwrt) return; } - error = iwl_read_umac_prph(trans, error); + error = iwl_trans_read_umac_prph(trans, error); IWL_ERR(trans, "IML/ROM dump:\n"); @@ -318,11 +318,11 @@ static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime fwrt) IWL_ERR(fwrt, "0x%08X \| IML/ROM error/state\n", error); IWL_ERR(fwrt, "0x%08X \| IML/ROM data1\n", - iwl_read_umac_prph(trans, data1)); + iwl_trans_read_umac_prph(trans, data1)); if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_22000) IWL_ERR(fwrt, "0x%08X \| IML/ROM WFPM_AUTH_KEY_0\n", - iwl_read_umac_prph(trans, SB_MODIFY_CFG_FLAG)); + iwl_trans_read_umac_prph(trans, SB_MODIFY_CFG_FLAG)); } #define FSEQ_REG(x) { .addr = (x), .str = #x, } @@ -360,7 +360,7 @@ static void iwl_fwrt_dump_fseq_regs(struct iwl_fw_runtime fwrt) for (i = 0; i < ARRAY_SIZE(fseq_regs); i++) IWL_ERR(fwrt, "0x%08X \| %s\n", - iwl_read_prph_no_grab(trans, fseq_regs[i].addr), + iwl_trans_read_prph_no_grab(trans, fseq_regs[i].addr), fseq_regs[i].str); iwl_trans_release_nic_access(trans); @@ -398,13 +398,13 @@ void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime fwrt) count++, pc_data++) IWL_ERR(fwrt, "%s: 0x%x\n", pc_data->pc_name, - iwl_read_prph_no_grab(fwrt->trans, - pc_data->pc_address)); + iwl_trans_read_prph_no_grab(fwrt->trans, + pc_data->pc_address)); iwl_trans_release_nic_access(fwrt->trans); } if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { - u32 scratch = iwl_read32(fwrt->trans, CSR_FUNC_SCRATCH); + u32 scratch = iwl_trans_read32(fwrt->trans, CSR_FUNC_SCRATCH); IWL_ERR(fwrt, "Function Scratch status:\n"); IWL_ERR(fwrt, "0x%08X \| Func Scratch\n", scratch); diff --git a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c index 545a213df71d2..ccd190ab8a552 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c +++ b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c @@ -6,7 +6,7 @@ #include "iwl-drv.h" #include "pnvm.h" #include "iwl-prph.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "fw/api/commands.h" #include "fw/api/nvm-reg.h" #include "fw/api/alive.h" @@ -485,8 +485,8 @@ int iwl_pnvm_load(struct iwl_trans trans, iwl_pnvm_complete_fn, trans); /* kick the doorbell / - iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, - UREG_DOORBELL_TO_ISR6_PNVM); + iwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, + UREG_DOORBELL_TO_ISR6_PNVM); return iwl_wait_notification(notif_wait, &pnvm_wait, MVM_UCODE_PNVM_TIMEOUT); diff --git a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c index dffd5e68f41da..89a0f722cad94 100644 --- a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c +++ b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c @@ -6,7 +6,7 @@ #include "iwl-drv.h" #include "pnvm.h" #include "iwl-prph.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "fw/uefi.h" #include "fw/api/alive.h" diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h index d2fa80a3dd040..11f2b31f6df7e 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h @@ -14,9 +14,9 @@ low power states due to driver-invoked device resets * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. * - * Use iwl_write32() and iwl_read32() family to access these registers; + * Use iwl_trans_write32() and iwl_trans_read32() family to access these registers; * these provide simple PCI bus access, without waking up the MAC. - * Do not use iwl_write_direct32() family for these registers; + * Do not use iwl_trans_write_direct32() family for these registers; * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. * The MAC (uCode processor, etc.) does not need to be powered up for accessing * the CSR registers. @@ -36,7 +36,7 @@ #define CSR_GP_CNTRL (CSR_BASE+0x024) #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg / -/ 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! / +/ 2nd byte of CSR_INT_COALESCING, not accessible via iwl_trans_write32()! / #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) / @@ -474,7 +474,7 @@ enum { * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. * - * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW + * Use iwl_trans_write32()/iwl_trans_read32() family to access these registers. The MAC HW * need not be powered up so no "grab inc access" is required. / @@ -501,12 +501,13 @@ enum { to indirectly access device's internal memory or registers that * may be powered-down. * - * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; + * Use iwl_trans_write_direct32() family for writing to these registers; + * A read operation doesn't exist, can be added if needed. * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ * to make sure the MAC (uCode processor, etc.) is powered up for accessing * internal resources. * - * Do not use iwl_write32()/iwl_read32() family to access these registers; + * Do not use iwl_trans_write32()/iwl_trans_read32() family to access these registers; * these provide only simple PCI bus access, without waking up the MAC. / #define HBUS_BASE (0x400) diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c index 4372a171172b0..cc6044222b5cf 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c +++ b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c @@ -912,7 +912,7 @@ static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime fwrt, for (count = 0; count < len; count++) { address = le32_to_cpu(config_list->addr_val[count].address); value = le32_to_cpu(config_list->addr_val[count].value); - iwl_trans_write_prph(fwrt->trans, address + offset, value); + iwl_trans_write_prph_no_grab(fwrt->trans, address + offset, value); } iwl_trans_release_nic_access(fwrt->trans); break; @@ -931,7 +931,7 @@ static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime fwrt, for (count = 0; count < len; count++) { address = le32_to_cpu(config_list->addr_val[count].address); value = le32_to_cpu(config_list->addr_val[count].value); - iwl_write32(fwrt->trans, address + offset, value); + iwl_trans_write32(fwrt->trans, address + offset, value); IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n", count, address, value); } diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h b/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h index 0af9d8362c5b8..a0cc401198908 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h @@ -3,6 +3,7 @@ * Copyright(c) 2009 - 2014 Intel Corporation. All rights reserved. * Copyright(c) 2016-2017 Intel Deutschland GmbH + * Copyright (C) 2026 Intel Corporation ****************************************************************************/ #if !defined(__IWLWIFI_DEVICE_TRACE_IO) \|\| defined(TRACE_HEADER_MULTI_READ) @@ -65,23 +66,6 @@ TRACE_EVENT(iwlwifi_dev_iowrite32, __get_str(dev), __entry->offs, __entry->val) ); -TRACE_EVENT(iwlwifi_dev_iowrite64, - TP_PROTO(const struct device dev, u64 offs, u64 val), - TP_ARGS(dev, offs, val), - TP_STRUCT__entry( - DEV_ENTRY - __field(u64, offs) - __field(u64, val) - ), - TP_fast_assign( - DEV_ASSIGN; - __entry->offs = offs; - __entry->val = val; - ), - TP_printk("[%s] write io[%llu] = %llu)", - __get_str(dev), __entry->offs, __entry->val) -); - TRACE_EVENT(iwlwifi_dev_iowrite_prph32, TP_PROTO(const struct device dev, u32 offs, u32 val), TP_ARGS(dev, offs, val), diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.c b/drivers/net/wireless/intel/iwlwifi/iwl-io.c deleted file mode 100644 index cc6bf4ea5055d..0000000000000 --- a/drivers/net/wireless/intel/iwlwifi/iwl-io.c +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -/ - * Copyright (C) 2003-2014, 2018-2022, 2024-2026 Intel Corporation - * Copyright (C) 2015-2016 Intel Deutschland GmbH - / -#include <linux/device.h> -#include <linux/export.h> - -#include "iwl-drv.h" -#include "iwl-io.h" -#include "iwl-csr.h" -#include "iwl-debug.h" - -void iwl_write8(struct iwl_trans trans, u32 ofs, u8 val) -{ - trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val); - iwl_trans_write8(trans, ofs, val); -} -IWL_EXPORT_SYMBOL(iwl_write8); - -void iwl_write32(struct iwl_trans trans, u32 ofs, u32 val) -{ - trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val); - iwl_trans_write32(trans, ofs, val); -} -IWL_EXPORT_SYMBOL(iwl_write32); - -void iwl_write64(struct iwl_trans trans, u64 ofs, u64 val) -{ - trace_iwlwifi_dev_iowrite64(trans->dev, ofs, val); - iwl_trans_write32(trans, ofs, lower_32_bits(val)); - iwl_trans_write32(trans, ofs + 4, upper_32_bits(val)); -} -IWL_EXPORT_SYMBOL(iwl_write64); - -u32 iwl_read32(struct iwl_trans trans, u32 ofs) -{ - u32 val = iwl_trans_read32(trans, ofs); - - trace_iwlwifi_dev_ioread32(trans->dev, ofs, val); - return val; -} -IWL_EXPORT_SYMBOL(iwl_read32); - -#define IWL_POLL_INTERVAL 10 / microseconds / - -int iwl_poll_bits_mask(struct iwl_trans trans, u32 addr, - u32 bits, u32 mask, int timeout) -{ - int t = 0; - - do { - if ((iwl_read32(trans, addr) & mask) == (bits & mask)) - return 0; - udelay(IWL_POLL_INTERVAL); - t += IWL_POLL_INTERVAL; - } while (t < timeout); - - return -ETIMEDOUT; -} -IWL_EXPORT_SYMBOL(iwl_poll_bits_mask); - -u32 iwl_read_direct32(struct iwl_trans trans, u32 reg) -{ - if (iwl_trans_grab_nic_access(trans)) { - u32 value = iwl_read32(trans, reg); - - iwl_trans_release_nic_access(trans); - return value; - } - - / return as if we have a HW timeout/failure / - return 0x5a5a5a5a; -} - -void iwl_write_direct32(struct iwl_trans trans, u32 reg, u32 value) -{ - if (iwl_trans_grab_nic_access(trans)) { - iwl_write32(trans, reg, value); - iwl_trans_release_nic_access(trans); - } -} -IWL_EXPORT_SYMBOL(iwl_write_direct32); - -void iwl_write_direct64(struct iwl_trans trans, u64 reg, u64 value) -{ - if (iwl_trans_grab_nic_access(trans)) { - iwl_write64(trans, reg, value); - iwl_trans_release_nic_access(trans); - } -} - -int iwl_poll_direct_bit(struct iwl_trans trans, u32 addr, u32 mask, - int timeout) -{ - int t = 0; - - do { - if ((iwl_read_direct32(trans, addr) & mask) == mask) - return t; - udelay(IWL_POLL_INTERVAL); - t += IWL_POLL_INTERVAL; - } while (t < timeout); - - return -ETIMEDOUT; -} - -u32 iwl_read_prph_no_grab(struct iwl_trans trans, u32 ofs) -{ - u32 val = iwl_trans_read_prph(trans, ofs); - trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val); - return val; -} - -void iwl_write_prph_no_grab(struct iwl_trans trans, u32 ofs, u32 val) -{ - trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val); - iwl_trans_write_prph(trans, ofs, val); -} - -void iwl_write_prph64_no_grab(struct iwl_trans trans, u64 ofs, u64 val) -{ - trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val); - iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff); - iwl_write_prph_no_grab(trans, ofs + 4, val >> 32); -} - -u32 iwl_read_prph(struct iwl_trans trans, u32 ofs) -{ - if (iwl_trans_grab_nic_access(trans)) { - u32 val = iwl_read_prph_no_grab(trans, ofs); - - iwl_trans_release_nic_access(trans); - - return val; - } - - /* return as if we have a HW timeout/failure / - return 0x5a5a5a5a; -} -IWL_EXPORT_SYMBOL(iwl_read_prph); - -void iwl_write_prph_delay(struct iwl_trans trans, u32 ofs, u32 val, u32 delay_ms) -{ - if (iwl_trans_grab_nic_access(trans)) { - mdelay(delay_ms); - iwl_write_prph_no_grab(trans, ofs, val); - iwl_trans_release_nic_access(trans); - } -} -IWL_EXPORT_SYMBOL(iwl_write_prph_delay); - -int iwl_poll_prph_bit(struct iwl_trans trans, u32 addr, - u32 bits, u32 mask, int timeout) -{ - int t = 0; - - do { - if ((iwl_read_prph(trans, addr) & mask) == (bits & mask)) - return 0; - udelay(IWL_POLL_INTERVAL); - t += IWL_POLL_INTERVAL; - } while (t < timeout); - - return -ETIMEDOUT; -} - -int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans trans, u32 addr, - u32 bits, u32 mask, int timeout) -{ - int t = 0; - - do { - if ((iwl_read_umac_prph_no_grab(trans, addr) & mask) == - (bits & mask)) - return 0; - udelay(IWL_POLL_INTERVAL); - t += IWL_POLL_INTERVAL; - } while (t < timeout); - - return -ETIMEDOUT; -} - -void iwl_set_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask) -{ - if (iwl_trans_grab_nic_access(trans)) { - iwl_write_prph_no_grab(trans, ofs, - iwl_read_prph_no_grab(trans, ofs) \| - mask); - iwl_trans_release_nic_access(trans); - } -} -IWL_EXPORT_SYMBOL(iwl_set_bits_prph); - -void iwl_set_bits_mask_prph(struct iwl_trans trans, u32 ofs, - u32 bits, u32 mask) -{ - if (iwl_trans_grab_nic_access(trans)) { - iwl_write_prph_no_grab(trans, ofs, - (iwl_read_prph_no_grab(trans, ofs) & - mask) \| bits); - iwl_trans_release_nic_access(trans); - } -} -IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph); - -void iwl_clear_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask) -{ - u32 val; - - if (iwl_trans_grab_nic_access(trans)) { - val = iwl_read_prph_no_grab(trans, ofs); - iwl_write_prph_no_grab(trans, ofs, (val & ~mask)); - iwl_trans_release_nic_access(trans); - } -} -IWL_EXPORT_SYMBOL(iwl_clear_bits_prph); diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.h b/drivers/net/wireless/intel/iwlwifi/iwl-io.h deleted file mode 100644 index e4a9f2ba0de93..0000000000000 --- a/drivers/net/wireless/intel/iwlwifi/iwl-io.h +++ /dev/null @@ -1,103 +0,0 @@ -/ SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / -/ - * Copyright (C) 2018-2021, 2025-2026 Intel Corporation - / -#ifndef __iwl_io_h__ -#define __iwl_io_h__ - -#include "iwl-devtrace.h" -#include "iwl-trans.h" - -void iwl_write8(struct iwl_trans trans, u32 ofs, u8 val); -void iwl_write32(struct iwl_trans trans, u32 ofs, u32 val); -void iwl_write64(struct iwl_trans trans, u64 ofs, u64 val); -u32 iwl_read32(struct iwl_trans trans, u32 ofs); - -static inline void iwl_set_bit(struct iwl_trans trans, u32 reg, u32 mask) -{ - iwl_trans_set_bits_mask(trans, reg, mask, mask); -} - -static inline void iwl_clear_bit(struct iwl_trans trans, u32 reg, u32 mask) -{ - iwl_trans_set_bits_mask(trans, reg, mask, 0); -} - -int iwl_poll_bits_mask(struct iwl_trans trans, u32 addr, - u32 bits, u32 mask, int timeout); -static inline int iwl_poll_bits(struct iwl_trans trans, u32 addr, u32 bits, - int timeout) -{ - return iwl_poll_bits_mask(trans, addr, bits, bits, timeout); -} -int iwl_poll_direct_bit(struct iwl_trans trans, u32 addr, u32 mask, - int timeout); - -u32 iwl_read_direct32(struct iwl_trans trans, u32 reg); -void iwl_write_direct32(struct iwl_trans trans, u32 reg, u32 value); -void iwl_write_direct64(struct iwl_trans trans, u64 reg, u64 value); - - -u32 iwl_read_prph_no_grab(struct iwl_trans trans, u32 ofs); -u32 iwl_read_prph(struct iwl_trans trans, u32 ofs); -void iwl_write_prph_no_grab(struct iwl_trans trans, u32 ofs, u32 val); -void iwl_write_prph64_no_grab(struct iwl_trans trans, u64 ofs, u64 val); -void iwl_write_prph_delay(struct iwl_trans trans, u32 ofs, - u32 val, u32 delay_ms); -static inline void iwl_write_prph(struct iwl_trans trans, u32 ofs, u32 val) -{ - iwl_write_prph_delay(trans, ofs, val, 0); -} - -int iwl_poll_prph_bit(struct iwl_trans trans, u32 addr, - u32 bits, u32 mask, int timeout); -int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans trans, u32 addr, - u32 bits, u32 mask, int timeout); -void iwl_set_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask); -void iwl_set_bits_mask_prph(struct iwl_trans trans, u32 ofs, - u32 bits, u32 mask); -void iwl_clear_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask); - -/* - * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from - * device family AX200. So peripheries used in families above and below AX200 - * should go through iwl_..._umac_..._prph. - / -static inline u32 iwl_umac_prph(struct iwl_trans trans, u32 ofs) -{ - return ofs + trans->mac_cfg->umac_prph_offset; -} - -static inline u32 iwl_read_umac_prph_no_grab(struct iwl_trans trans, u32 ofs) -{ - return iwl_read_prph_no_grab(trans, ofs + - trans->mac_cfg->umac_prph_offset); -} - -static inline u32 iwl_read_umac_prph(struct iwl_trans trans, u32 ofs) -{ - return iwl_read_prph(trans, ofs + trans->mac_cfg->umac_prph_offset); -} - -static inline void iwl_write_umac_prph_no_grab(struct iwl_trans trans, u32 ofs, - u32 val) -{ - iwl_write_prph_no_grab(trans, ofs + trans->mac_cfg->umac_prph_offset, - val); -} - -static inline void iwl_write_umac_prph(struct iwl_trans trans, u32 ofs, - u32 val) -{ - iwl_write_prph(trans, ofs + trans->mac_cfg->umac_prph_offset, val); -} - -static inline int iwl_poll_umac_prph_bit(struct iwl_trans trans, u32 addr, - u32 bits, u32 mask, int timeout) -{ - return iwl_poll_prph_bit(trans, addr + - trans->mac_cfg->umac_prph_offset, - bits, mask, timeout); -} - -#endif diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c index 413dd55115f8f..ed2b094c1ad78 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c +++ b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c @@ -16,7 +16,7 @@ #include "iwl-modparams.h" #include "iwl-nvm-parse.h" #include "iwl-prph.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-csr.h" #include "fw/api/nvm-reg.h" #include "fw/api/commands.h" @@ -1312,10 +1312,10 @@ static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 dest) static void iwl_set_hw_address_from_csr(struct iwl_trans trans, struct iwl_nvm_data data) { - __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, - CSR_MAC_ADDR0_STRAP(trans))); - __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, - CSR_MAC_ADDR1_STRAP(trans))); + __le32 mac_addr0 = cpu_to_le32(iwl_trans_read32(trans, + CSR_MAC_ADDR0_STRAP(trans))); + __le32 mac_addr1 = cpu_to_le32(iwl_trans_read32(trans, + CSR_MAC_ADDR1_STRAP(trans))); iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); /* @@ -1325,8 +1325,8 @@ static void iwl_set_hw_address_from_csr(struct iwl_trans trans, if (is_valid_ether_addr(data->hw_addr)) return; - mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans))); - mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans))); + mac_addr0 = cpu_to_le32(iwl_trans_read32(trans, CSR_MAC_ADDR0_OTP(trans))); + mac_addr1 = cpu_to_le32(iwl_trans_read32(trans, CSR_MAC_ADDR1_OTP(trans))); iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); } @@ -1367,10 +1367,10 @@ static void iwl_set_hw_address_family_8000(struct iwl_trans trans, if (nvm_hw) { /* read the mac address from WFMP registers / - __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, - WFMP_MAC_ADDR_0)); - __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, - WFMP_MAC_ADDR_1)); + __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph_no_grab(trans, + WFMP_MAC_ADDR_0)); + __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph_no_grab(trans, + WFMP_MAC_ADDR_1)); iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); @@ -1410,7 +1410,7 @@ static int iwl_set_hw_address(struct iwl_trans trans, if (!trans->csme_own) IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n", - data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR)); + data->hw_addr, iwl_trans_read_prph(trans, REG_OTP_MINOR)); return 0; } diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-scd.h b/drivers/net/wireless/intel/iwlwifi/iwl-scd.h index 1eaff898ca3ca..f13568d3094bf 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-scd.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-scd.h @@ -1,52 +1,52 @@ /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / / * Copyright (C) 2014 Intel Mobile Communications GmbH + * Copyright (C) 2026 Intel Corporation / #ifndef __iwl_scd_h__ #define __iwl_scd_h__ #include "iwl-trans.h" -#include "iwl-io.h" #include "iwl-prph.h" static inline void iwl_scd_txq_set_chain(struct iwl_trans trans, u16 txq_id) { - iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); + iwl_trans_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); } static inline void iwl_scd_txq_enable_agg(struct iwl_trans trans, u16 txq_id) { - iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); + iwl_trans_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); } static inline void iwl_scd_txq_disable_agg(struct iwl_trans trans, u16 txq_id) { - iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); + iwl_trans_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); } static inline void iwl_scd_disable_agg(struct iwl_trans trans) { - iwl_set_bits_prph(trans, SCD_AGGR_SEL, 0); + iwl_trans_set_bits_prph(trans, SCD_AGGR_SEL, 0); } static inline void iwl_scd_activate_fifos(struct iwl_trans trans) { - iwl_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7)); + iwl_trans_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7)); } static inline void iwl_scd_deactivate_fifos(struct iwl_trans trans) { - iwl_write_prph(trans, SCD_TXFACT, 0); + iwl_trans_write_prph(trans, SCD_TXFACT, 0); } static inline void iwl_scd_enable_set_active(struct iwl_trans trans, u32 value) { - iwl_write_prph(trans, SCD_EN_CTRL, value); + iwl_trans_write_prph(trans, SCD_EN_CTRL, value); } static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl) @@ -76,9 +76,9 @@ static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl) static inline void iwl_scd_txq_set_inactive(struct iwl_trans trans, u16 txq_id) { - iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), - (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)\| - (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); + iwl_trans_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), + (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)\| + (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); } #endif diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.c b/drivers/net/wireless/intel/iwlwifi/iwl-trans.c index 0a6b7b264aa23..6e068f19af7fb 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.c +++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.c @@ -6,6 +6,7 @@ / #include <linux/kernel.h> #include <linux/bsearch.h> +#include <linux/delay.h> #include <linux/list.h> #include "iwl-trans.h" @@ -260,13 +261,14 @@ static void iwl_trans_restart_wk(struct work_struct wk) iwl_trans_schedule_reprobe(trans, 0); break; default: - iwl_trans_pcie_reset(trans, mode); + iwl_trans_reset(trans, mode); break; } } struct iwl_trans iwl_trans_alloc(unsigned int priv_size, struct device dev, + const struct iwl_trans_ops ops, const struct iwl_mac_cfg mac_cfg) { struct iwl_trans trans; @@ -278,6 +280,7 @@ struct iwl_trans iwl_trans_alloc(unsigned int priv_size, if (!trans) return NULL; + trans->ops = ops; trans->mac_cfg = mac_cfg; #ifdef CONFIG_LOCKDEP @@ -428,45 +431,130 @@ void iwl_trans_op_mode_leave(struct iwl_trans trans) } IWL_EXPORT_SYMBOL(iwl_trans_op_mode_leave); -void iwl_trans_write8(struct iwl_trans trans, u32 ofs, u8 val) -{ - iwl_trans_pcie_write8(trans, ofs, val); -} - void iwl_trans_write32(struct iwl_trans trans, u32 ofs, u32 val) { iwl_trans_pcie_write32(trans, ofs, val); } +IWL_EXPORT_SYMBOL(iwl_trans_write32); u32 iwl_trans_read32(struct iwl_trans trans, u32 ofs) { return iwl_trans_pcie_read32(trans, ofs); } +IWL_EXPORT_SYMBOL(iwl_trans_read32); -u32 iwl_trans_read_prph(struct iwl_trans trans, u32 ofs) +u32 iwl_trans_read_prph_no_grab(struct iwl_trans trans, u32 ofs) { return iwl_trans_pcie_read_prph(trans, ofs); } -void iwl_trans_write_prph(struct iwl_trans trans, u32 ofs, u32 val) +void iwl_trans_write_prph_no_grab(struct iwl_trans trans, u32 ofs, u32 val) +{ + return iwl_pcie_write_prph_no_grab(trans, ofs, val); +} + +#define IWL_POLL_INTERVAL 10 / microseconds / + +int iwl_trans_poll_bits_mask(struct iwl_trans trans, u32 addr, + u32 bits, u32 mask, int timeout) +{ + int t = 0; + + do { + if ((iwl_trans_read32(trans, addr) & mask) == (bits & mask)) + return 0; + udelay(IWL_POLL_INTERVAL); + t += IWL_POLL_INTERVAL; + } while (t < timeout); + + return -ETIMEDOUT; +} +IWL_EXPORT_SYMBOL(iwl_trans_poll_bits_mask); + +void iwl_trans_write_direct32(struct iwl_trans trans, u32 reg, u32 value) +{ + if (iwl_trans_grab_nic_access(trans)) { + iwl_trans_write32(trans, reg, value); + iwl_trans_release_nic_access(trans); + } +} +IWL_EXPORT_SYMBOL(iwl_trans_write_direct32); + +u32 iwl_trans_read_prph(struct iwl_trans trans, u32 ofs) +{ + if (iwl_trans_grab_nic_access(trans)) { + u32 val = iwl_trans_read_prph_no_grab(trans, ofs); + + iwl_trans_release_nic_access(trans); + + return val; + } + + /* return as if we have a HW timeout/failure / + return 0x5a5a5a5a; +} +IWL_EXPORT_SYMBOL(iwl_trans_read_prph); + +void iwl_trans_write_prph_delay(struct iwl_trans trans, u32 ofs, u32 val, + u32 delay_ms) { - return iwl_trans_pcie_write_prph(trans, ofs, val); + if (iwl_trans_grab_nic_access(trans)) { + mdelay(delay_ms); + iwl_trans_write_prph_no_grab(trans, ofs, val); + iwl_trans_release_nic_access(trans); + } +} +IWL_EXPORT_SYMBOL(iwl_trans_write_prph_delay); + +void iwl_trans_set_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask) +{ + if (iwl_trans_grab_nic_access(trans)) { + iwl_trans_write_prph_no_grab(trans, ofs, + iwl_trans_read_prph_no_grab(trans, ofs) \| + mask); + iwl_trans_release_nic_access(trans); + } +} +IWL_EXPORT_SYMBOL(iwl_trans_set_bits_prph); + +void iwl_trans_set_bits_mask_prph(struct iwl_trans trans, u32 ofs, + u32 bits, u32 mask) +{ + if (iwl_trans_grab_nic_access(trans)) { + iwl_trans_write_prph_no_grab(trans, ofs, + (iwl_trans_read_prph_no_grab(trans, ofs) & + mask) \| bits); + iwl_trans_release_nic_access(trans); + } } +IWL_EXPORT_SYMBOL(iwl_trans_set_bits_mask_prph); + +void iwl_trans_clear_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask) +{ + u32 val; + + if (iwl_trans_grab_nic_access(trans)) { + val = iwl_trans_read_prph_no_grab(trans, ofs); + iwl_trans_write_prph_no_grab(trans, ofs, (val & ~mask)); + iwl_trans_release_nic_access(trans); + } +} +IWL_EXPORT_SYMBOL(iwl_trans_clear_bits_prph); void iwl_trans_force_nmi(struct iwl_trans trans) { if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_9000) - iwl_write_prph_delay(trans, DEVICE_SET_NMI_REG, - DEVICE_SET_NMI_VAL_DRV, 1); + iwl_trans_write_prph_delay(trans, DEVICE_SET_NMI_REG, + DEVICE_SET_NMI_VAL_DRV, 1); else if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) - iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, - UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER); + iwl_trans_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, + UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER); else if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ) - iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, - UREG_DOORBELL_TO_ISR6_NMI_BIT); + iwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, + UREG_DOORBELL_TO_ISR6_NMI_BIT); else - iwl_write32(trans, CSR_DOORBELL_VECTOR, - UREG_DOORBELL_TO_ISR6_NMI_BIT); + iwl_trans_write32(trans, CSR_DOORBELL_VECTOR, + UREG_DOORBELL_TO_ISR6_NMI_BIT); } IWL_EXPORT_SYMBOL(iwl_trans_force_nmi); @@ -490,10 +578,10 @@ int iwl_trans_write_mem(struct iwl_trans trans, u32 addr, const u32 vals = buf; if (iwl_trans_grab_nic_access(trans)) { - iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); + iwl_trans_write32(trans, HBUS_TARG_MEM_WADDR, addr); for (offs = 0; offs < dwords; offs++) - iwl_write32(trans, HBUS_TARG_MEM_WDAT, - vals ? vals[offs] : 0); + iwl_trans_write32(trans, HBUS_TARG_MEM_WDAT, + vals ? vals[offs] : 0); iwl_trans_release_nic_access(trans); } else { ret = -EBUSY; @@ -843,3 +931,17 @@ int iwl_trans_activate_nic(struct iwl_trans trans) } IWL_EXPORT_SYMBOL(iwl_trans_activate_nic); + +void iwl_trans_reset(struct iwl_trans trans, enum iwl_reset_mode mode) +{ + if (!WARN_ON_ONCE(!trans->ops->reset)) + trans->ops->reset(trans, mode); +} +IWL_EXPORT_SYMBOL(iwl_trans_reset); + +void iwl_trans_fw_reset_handshake(struct iwl_trans trans) +{ + if (!WARN_ON_ONCE(!trans->ops->fw_reset_handshake)) + trans->ops->fw_reset_handshake(trans); +} + diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h index 56c5e61b614ad..90100f16ddd52 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h @@ -734,12 +734,15 @@ struct iwl_trans_info { u8 num_rxqs; }; +struct iwl_trans_ops; + /* * struct iwl_trans - transport common data * * @csme_own: true if we couldn't get ownership on the device * @op_mode: pointer to the op_mode * @mac_cfg: the trans-specific configuration part + * @ops: bus-specific transport operations, see &struct iwl_trans_ops * @cfg: pointer to the configuration * @drv: pointer to iwl_drv * @conf: configuration set by the opmode before enter @@ -773,6 +776,7 @@ struct iwl_trans { bool csme_own; struct iwl_op_mode op_mode; const struct iwl_mac_cfg mac_cfg; + const struct iwl_trans_ops ops; const struct iwl_rf_cfg cfg; struct iwl_drv drv; struct iwl_trans_config conf; @@ -910,15 +914,13 @@ int iwl_trans_wait_tx_queues_empty(struct iwl_trans trans, u32 txqs); int iwl_trans_wait_txq_empty(struct iwl_trans trans, int queue); -void iwl_trans_write8(struct iwl_trans trans, u32 ofs, u8 val); - void iwl_trans_write32(struct iwl_trans trans, u32 ofs, u32 val); u32 iwl_trans_read32(struct iwl_trans trans, u32 ofs); -u32 iwl_trans_read_prph(struct iwl_trans trans, u32 ofs); +u32 iwl_trans_read_prph_no_grab(struct iwl_trans trans, u32 ofs); -void iwl_trans_write_prph(struct iwl_trans trans, u32 ofs, u32 val); +void iwl_trans_write_prph_no_grab(struct iwl_trans trans, u32 ofs, u32 val); int iwl_trans_read_mem(struct iwl_trans trans, u32 addr, void buf, int dwords); @@ -979,6 +981,66 @@ int iwl_trans_sw_reset(struct iwl_trans trans); void iwl_trans_set_bits_mask(struct iwl_trans trans, u32 reg, u32 mask, u32 value); +static inline void iwl_trans_set_bit(struct iwl_trans trans, u32 reg, u32 mask) +{ + iwl_trans_set_bits_mask(trans, reg, mask, mask); +} + +static inline void iwl_trans_clear_bit(struct iwl_trans trans, u32 reg, u32 mask) +{ + iwl_trans_set_bits_mask(trans, reg, mask, 0); +} + +int iwl_trans_poll_bits_mask(struct iwl_trans trans, u32 addr, + u32 bits, u32 mask, int timeout); +static inline int iwl_trans_poll_bits(struct iwl_trans trans, u32 addr, u32 bits, + int timeout) +{ + return iwl_trans_poll_bits_mask(trans, addr, bits, bits, timeout); +} + +void iwl_trans_write_direct32(struct iwl_trans trans, u32 reg, u32 value); + +u32 iwl_trans_read_prph(struct iwl_trans trans, u32 ofs); +void iwl_trans_write_prph_delay(struct iwl_trans trans, u32 ofs, + u32 val, u32 delay_ms); +static inline void iwl_trans_write_prph(struct iwl_trans trans, u32 ofs, u32 val) +{ + iwl_trans_write_prph_delay(trans, ofs, val, 0); +} + +void iwl_trans_set_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask); +void iwl_trans_set_bits_mask_prph(struct iwl_trans trans, u32 ofs, + u32 bits, u32 mask); +void iwl_trans_clear_bits_prph(struct iwl_trans trans, u32 ofs, u32 mask); + +/ + * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from + * device family AX200. So peripheries used in families above and below AX200 + * should go through iwl_trans_..._umac_..._prph. + / +static inline u32 iwl_trans_umac_prph(struct iwl_trans trans, u32 ofs) +{ + return ofs + trans->mac_cfg->umac_prph_offset; +} + +static inline u32 iwl_trans_read_umac_prph_no_grab(struct iwl_trans trans, u32 ofs) +{ + return iwl_trans_read_prph_no_grab(trans, ofs + + trans->mac_cfg->umac_prph_offset); +} + +static inline u32 iwl_trans_read_umac_prph(struct iwl_trans trans, u32 ofs) +{ + return iwl_trans_read_prph(trans, ofs + trans->mac_cfg->umac_prph_offset); +} + +static inline void iwl_trans_write_umac_prph(struct iwl_trans trans, u32 ofs, + u32 val) +{ + iwl_trans_write_prph(trans, ofs + trans->mac_cfg->umac_prph_offset, val); +} + bool iwl_trans_grab_nic_access(struct iwl_trans trans); /** @@ -1088,6 +1150,7 @@ static inline void iwl_trans_finish_sw_reset(struct iwl_trans trans) ***************************************************/ struct iwl_trans iwl_trans_alloc(unsigned int priv_size, struct device dev, + const struct iwl_trans_ops ops, const struct iwl_mac_cfg mac_cfg); void iwl_trans_free(struct iwl_trans trans); @@ -1158,8 +1221,148 @@ enum iwl_reset_mode { IWL_RESET_MODE_BACKOFF, }; -void iwl_trans_pcie_reset(struct iwl_trans trans, enum iwl_reset_mode mode); -void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans trans); +void iwl_trans_reset(struct iwl_trans trans, enum iwl_reset_mode mode); +void iwl_trans_fw_reset_handshake(struct iwl_trans trans); + +/** + * struct iwl_trans_ops - bus-specific transport operations + * + * Function-pointer table filled in by the bus implementation. Unless noted + * otherwise, each callback implements the identically named iwl_trans_() + API, see its documentation. + * + * @op_mode_enter: the op_mode took ownership of the transport + * @start_hw: start the hardware + * @op_mode_leave: the op_mode released the transport + * @send_cmd: send a host command to the firmware + * @alloc_tx_cmd: allocate a device TX command + * @free_tx_cmd: free a device TX command + * @write8: write a byte to a device register + * @write32: write a dword to a device register + * @read32: read a dword from a device register + * @read_prph: read a peripheral register + * @write_prph: write a peripheral register + * @read_mem: read device memory, taking NIC access + * @read_mem_no_grab: read device memory, NIC access already taken + * @set_bits_mask: read-modify-write a device register + * @read_config32: read a dword from the bus configuration space + * @grab_nic_access: keep the NIC awake for register access + * @release_nic_access: release the NIC access taken by @grab_nic_access + * @resched_with_nic_access: reschedule while holding NIC access + * @sw_reset: perform a software reset of the device + * @reset: reset the device, see &enum iwl_reset_mode + * @fw_reset_handshake: do a firmware reset handshake. + * @dump_data: collect a firmware error dump + * @d3_suspend: prepare the device for D3 (WoWLAN) + * @d3_resume: resume the device from D3 (WoWLAN) + * @sync_nmi: trigger an NMI and wait for it to be handled + * @write_imr_mem: write to the IMR memory region + * @fw_alive: Notify trans that the firmware sent the ALIVE notification + * @start_fw: download firmware code to the device and and start the firmware + * @stop_device: stop the device and the firmware + * @tx: transmit an MPDU + * @reclaim: free TX MPDUs up to the given sequence number + * @txq_disable: disable a TX queue (gen1) + * @txq_enable: enable a TX queue (gen1) + * @wait_txq_empty: wait for a single TX queue to become empty + * @wait_txqs_empty: wait for the given TX queues to become empty + * @freeze_txq_timer: freeze/unfreeze the watchdog of the given TX queues + * @txq_set_shared_mode: mark a TX queue as shared between TIDs + * @set_q_ptrs: set the write pointer of a TX queue + * @txq_alloc: allocate a TX queue (gen2) + * @txq_free: free a TX queue allocated by @txq_alloc + * @rxq_dma_data: get the DMA addresses of an RX queue + * @load_pnvm: load the PNVM image + * @set_pnvm: tell the firmware to use the loaded PNVM + * @load_reduce_power: load the reduced power table + * @set_reduce_power: tell the firmware to use the reduced power table + * @is_pm_supported: whether bus power management is supported + * @is_ltr_enabled: whether LTR is enabled on the bus + * @activate_nic: bring the NIC out of low power and make it accessible + / +struct iwl_trans_ops { + void (op_mode_enter)(struct iwl_trans trans); + int (start_hw)(struct iwl_trans trans); + void (op_mode_leave)(struct iwl_trans trans); + + int (send_cmd)(struct iwl_trans trans, struct iwl_host_cmd cmd); + struct iwl_device_tx_cmd (alloc_tx_cmd)(struct iwl_trans trans); + void (free_tx_cmd)(struct iwl_trans trans, + struct iwl_device_tx_cmd dev_cmd); + + void (write8)(struct iwl_trans trans, u32 ofs, u8 val); + void (write32)(struct iwl_trans trans, u32 ofs, u32 val); + u32 (read32)(struct iwl_trans trans, u32 ofs); + u32 (read_prph)(struct iwl_trans trans, u32 ofs); + void (write_prph)(struct iwl_trans trans, u32 ofs, u32 val); + int (read_mem)(struct iwl_trans trans, u32 addr, + void buf, int dwords); + int (read_mem_no_grab)(struct iwl_trans trans, u32 addr, + void buf, u32 dwords); + void (set_bits_mask)(struct iwl_trans trans, u32 reg, + u32 mask, u32 value); + int (read_config32)(struct iwl_trans trans, u32 ofs, u32 val); + bool (grab_nic_access)(struct iwl_trans trans); + void (release_nic_access)(struct iwl_trans trans); + void (resched_with_nic_access)(struct iwl_trans trans); + + int (sw_reset)(struct iwl_trans trans, bool retake_ownership); + void (reset)(struct iwl_trans trans, enum iwl_reset_mode mode); + void (fw_reset_handshake)(struct iwl_trans trans); + + struct iwl_trans_dump_data (dump_data)(struct iwl_trans trans, + u32 dump_mask, + const struct iwl_dump_sanitize_ops sanitize_ops, + void sanitize_ctx); + int (d3_suspend)(struct iwl_trans trans, bool reset); + int (d3_resume)(struct iwl_trans trans, bool reset); + + void (sync_nmi)(struct iwl_trans trans); + int (write_imr_mem)(struct iwl_trans trans, u32 dst_addr, + u64 src_addr, u32 byte_cnt); + + void (fw_alive)(struct iwl_trans trans); + int (start_fw)(struct iwl_trans trans, const struct iwl_fw fw, + const struct fw_img img, bool run_in_rfkill); + void (stop_device)(struct iwl_trans trans); + + int (tx)(struct iwl_trans trans, struct sk_buff skb, + struct iwl_device_tx_cmd dev_cmd, int queue); + void (reclaim)(struct iwl_trans trans, int queue, int ssn, + struct sk_buff_head skbs, bool is_flush); + void (txq_disable)(struct iwl_trans trans, int queue, + bool configure_scd); + bool (txq_enable)(struct iwl_trans trans, int queue, u16 ssn, + const struct iwl_trans_txq_scd_cfg cfg, + unsigned int queue_wdg_timeout); + int (wait_txq_empty)(struct iwl_trans trans, int queue); + int (wait_txqs_empty)(struct iwl_trans trans, u32 txqs); + void (freeze_txq_timer)(struct iwl_trans trans, + unsigned long txqs, bool freeze); + void (txq_set_shared_mode)(struct iwl_trans trans, u32 txq_id, + bool shared_mode); + void (set_q_ptrs)(struct iwl_trans trans, int queue, int ptr); + int (txq_alloc)(struct iwl_trans trans, u32 flags, u32 sta_mask, + u8 tid, int size, unsigned int wdg_timeout); + void (txq_free)(struct iwl_trans trans, int queue); + int (rxq_dma_data)(struct iwl_trans trans, int queue, + struct iwl_trans_rxq_dma_data data); + + int (load_pnvm)(struct iwl_trans trans, + const struct iwl_pnvm_image pnvm_data, + const struct iwl_ucode_capabilities capa); + void (set_pnvm)(struct iwl_trans trans, + const struct iwl_ucode_capabilities capa); + int (load_reduce_power)(struct iwl_trans trans, + const struct iwl_pnvm_image payloads, + const struct iwl_ucode_capabilities capa); + void (set_reduce_power)(struct iwl_trans trans, + const struct iwl_ucode_capabilities capa); + + bool (is_pm_supported)(struct iwl_trans trans); + bool (is_ltr_enabled)(struct iwl_trans trans); + int (activate_nic)(struct iwl_trans trans); +}; / Internal helper / static inline void iwl_trans_set_info(struct iwl_trans trans, diff --git a/drivers/net/wireless/intel/iwlwifi/mld/constants.h b/drivers/net/wireless/intel/iwlwifi/mld/constants.h index 890abcab38374..bfd5398510ee3 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/constants.h +++ b/drivers/net/wireless/intel/iwlwifi/mld/constants.h @@ -39,6 +39,10 @@ #define IWL_MLD_TPT_COUNT_WINDOW (5 * HZ) +#define IWL_MLD_TX_GP2_VALID_PERIOD (10 * HZ) +#define IWL_MLD_TX_GP2_REFRESH_MARGIN (5 * HZ) +#define IWL_MLD_TX_GP2_RETRY_PERIOD HZ + #define IWL_MLD_DIS_RANDOM_FW_ID false #define IWL_MLD_D3_DEBUG false #define IWL_MLD_NON_TRANSMITTING_AP false diff --git a/drivers/net/wireless/intel/iwlwifi/mld/d3.c b/drivers/net/wireless/intel/iwlwifi/mld/d3.c index 6d8ede336d59b..7a7d07a7914dd 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/d3.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/d3.c @@ -5,6 +5,7 @@ #include "mld.h" #include "d3.h" +#include "tx.h" #include "power.h" #include "hcmd.h" #include "iface.h" @@ -1610,6 +1611,8 @@ int iwl_mld_no_wowlan_suspend(struct iwl_mld mld) iwl_mld_low_latency_stop(mld); + iwl_mld_tx_gp2_stop(mld); + ret = iwl_mld_update_device_power(mld, true); if (ret) { IWL_ERR(mld, @@ -1663,6 +1666,8 @@ int iwl_mld_no_wowlan_resume(struct iwl_mld mld) iwl_mld_low_latency_restart(mld); + iwl_mld_tx_gp2_start(mld); + return iwl_mld_update_device_power(mld, false); } diff --git a/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c index dd4bf7cb6a791..b8793b71494d8 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c @@ -5,7 +5,7 @@ #include "mld.h" #include "debugfs.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "hcmd.h" #include "iface.h" #include "sta.h" diff --git a/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c index a4b8037b5c765..a6a4f9672e4f9 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c @@ -8,7 +8,7 @@ #include "mld.h" #include "iface.h" #include "phy.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "constants.h" #include "fw/api/location.h" diff --git a/drivers/net/wireless/intel/iwlwifi/mld/fw.c b/drivers/net/wireless/intel/iwlwifi/mld/fw.c index e5866d89176d1..3b9f412cdff2b 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/fw.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/fw.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* - * Copyright (C) 2024-2025 Intel Corporation + * Copyright (C) 2024-2026 Intel Corporation / #include "mld.h" +#include "tx.h" #include "fw/api/alive.h" #include "fw/api/scan.h" @@ -206,11 +207,11 @@ static void iwl_mld_print_alive_notif_timeout(struct iwl_mld mld) IWL_ERR(mld, "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", - iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), - iwl_read_umac_prph(trans, - UMAG_SB_CPU_2_STATUS)); + iwl_trans_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), + iwl_trans_read_umac_prph(trans, + UMAG_SB_CPU_2_STATUS)); #define IWL_FW_PRINT_REG_INFO(reg_name) \ - IWL_ERR(mld, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name)) + IWL_ERR(mld, #reg_name ": 0x%x\n", iwl_trans_read_umac_prph(trans, reg_name)) IWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION); @@ -355,6 +356,8 @@ void iwl_mld_stop_fw(struct iwl_mld mld) { lockdep_assert_wiphy(mld->wiphy); + iwl_mld_tx_gp2_stop(mld); + iwl_abort_notification_waits(&mld->notif_wait); iwl_fw_dbg_stop_sync(&mld->fwrt); @@ -542,6 +545,8 @@ int iwl_mld_start_fw(struct iwl_mld mld) if (ret) goto error; + iwl_mld_tx_gp2_start(mld); + return 0; error: diff --git a/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c index 0b121114d47ca..e05bdbd3e1a9a 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c @@ -2168,6 +2168,8 @@ static int iwl_mld_resume(struct ieee80211_hw hw) iwl_mld_low_latency_restart(mld); + iwl_mld_tx_gp2_start(mld); + return 0; } #endif diff --git a/drivers/net/wireless/intel/iwlwifi/mld/mld.c b/drivers/net/wireless/intel/iwlwifi/mld/mld.c index b7b1e3686336c..71832d92024d0 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/mld.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/mld.c @@ -35,6 +35,17 @@ MODULE_IMPORT_NS("IWLWIFI"); static const struct iwl_op_mode_ops iwl_mld_ops; +int iwl_mld_get_systime(struct iwl_mld mld, u32 gp2) +{ + gp2 = iwl_trans_read_prph(mld->trans, + mld->trans->mac_cfg->base->gp2_reg_addr); + + if (gp2 == 0x5a5a5a5a) + return -EINVAL; + + return 0; +} + static int __init iwl_mld_init(void) { int ret = iwl_opmode_register("iwlmld", &iwl_mld_ops); @@ -425,6 +436,8 @@ iwl_op_mode_mld_start(struct iwl_trans trans, const struct iwl_rf_cfg cfg, / Configure transport layer with the opmode specific params / iwl_mld_configure_trans(op_mode); + iwl_mld_tx_gp2_init(mld); + / needed for regulatory init / rtnl_lock(); / Needed for sending commands / diff --git a/drivers/net/wireless/intel/iwlwifi/mld/mld.h b/drivers/net/wireless/intel/iwlwifi/mld/mld.h index 37f41b504b54c..a9e65b216fd39 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/mld.h +++ b/drivers/net/wireless/intel/iwlwifi/mld/mld.h @@ -29,6 +29,7 @@ #include "notif.h" #include "scan.h" #include "rx.h" +#include "tx.h" #include "thermal.h" #include "low_latency.h" #include "constants.h" @@ -196,6 +197,7 @@ being IBSS manager for that time and needing to respond to probe * requests * @ptp_data: data of the PTP clock + * @tx_gp2: gp2 timestamping state for TX commands * @time_sync: time sync data. * @ftm_initiator: FTM initiator data * @nan_device_vif: points to the NAN device vif if exists @@ -306,6 +308,8 @@ struct iwl_mld { struct ptp_data ptp_data; + struct iwl_mld_tx_gp2 tx_gp2; + struct iwl_mld_time_sync_data __rcu time_sync; struct ftm_initiator_data ftm_initiator; @@ -572,6 +576,8 @@ iwl_mld_fw_id_to_link_conf(struct iwl_mld mld, u8 fw_link_id) #define MSEC_TO_TU(_msec) ((_msec) * 1000 / 1024) +int iwl_mld_get_systime(struct iwl_mld mld, u32 gp2); + void iwl_mld_add_vif_debugfs(struct ieee80211_hw hw, struct ieee80211_vif vif); void iwl_mld_add_link_debugfs(struct ieee80211_hw hw, diff --git a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c index 1ac85d6ce1d79..9f7d17dbdee16 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / - * Copyright (C) 2025 Intel Corporation + * Copyright (C) 2025 - 2026 Intel Corporation / #include "mld.h" @@ -19,16 +19,6 @@ #define IWL_PTP_WRAP_TIME (3600 HZ) #define IWL_PTP_WRAP_THRESHOLD_USEC (5000) -static int iwl_mld_get_systime(struct iwl_mld mld, u32 gp2) -{ - gp2 = iwl_read_prph(mld->trans, mld->trans->mac_cfg->base->gp2_reg_addr); - - if (gp2 == 0x5a5a5a5a) - return -EINVAL; - - return 0; -} - static void iwl_mld_ptp_update_new_read(struct iwl_mld mld, u32 gp2) { IWL_DEBUG_PTP(mld, "PTP: last_gp2=%u, new gp2 read=%u\n", diff --git a/drivers/net/wireless/intel/iwlwifi/mld/rx.c b/drivers/net/wireless/intel/iwlwifi/mld/rx.c index 5f18aa551af52..8fa438fd78153 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/rx.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/rx.c @@ -553,7 +553,10 @@ iwl_mld_decode_he_tb_phy_data(struct iwl_mld_rx_phy_data phy_data, nsts = le32_get_bits(phy_data->ntfy->sigs.he_tb.tb_rx1, OFDM_UCODE_TRIG_BASE_RX_NSTS) + 1; - rx_status->nss = nsts >> !!(rate_n_flags & RATE_MCS_STBC_MSK); + + rx_status->nss = nsts; + if (rate_n_flags & RATE_MCS_STBC_MSK) + rx_status->nss = 1; } static void @@ -589,7 +592,9 @@ iwl_mld_decode_he_phy_data(struct iwl_mld_rx_phy_data phy_data, break; } - rx_status->nss = nsts >> !!(rate_n_flags & RATE_MCS_STBC_MSK); + rx_status->nss = nsts; + if (rate_n_flags & RATE_MCS_STBC_MSK) + rx_status->nss = 1; he->data1 \|= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN \| IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN); diff --git a/drivers/net/wireless/intel/iwlwifi/mld/scan.c b/drivers/net/wireless/intel/iwlwifi/mld/scan.c index e44b24904c19a..b942ac1e7ccca 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/scan.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/scan.c @@ -2273,6 +2273,7 @@ void iwl_mld_handle_channel_survey_notif(struct iwl_mld mld, /* Times are all in ms / info->time = le32_to_cpu(notif->active_time); info->time_busy = le32_to_cpu(notif->busy_time); + info->time_rx = le32_to_cpu(notif->rx_time); info->noise = iwl_average_neg_dbm(notif->noise, ARRAY_SIZE(notif->noise)); } @@ -2321,9 +2322,11 @@ int iwl_mld_mac80211_get_survey(struct ieee80211_hw hw, int idx, /* Found (the next) channel to report / survey->channel = &sband->channels[per_band_idx]; survey->filled = SURVEY_INFO_TIME \| - SURVEY_INFO_TIME_BUSY; + SURVEY_INFO_TIME_BUSY \| + SURVEY_INFO_TIME_RX; survey->time = info->time; survey->time_busy = info->time_busy; + survey->time_rx = info->time_rx; survey->noise = info->noise; if (survey->noise < 0) survey->filled \|= SURVEY_INFO_NOISE_DBM; diff --git a/drivers/net/wireless/intel/iwlwifi/mld/scan.h b/drivers/net/wireless/intel/iwlwifi/mld/scan.h index dc299fe2f999c..74ebe8296693f 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/scan.h +++ b/drivers/net/wireless/intel/iwlwifi/mld/scan.h @@ -1,6 +1,6 @@ / SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / / - * Copyright (C) 2024-2025 Intel Corporation + * Copyright (C) 2024-2026 Intel Corporation / #ifndef __iwl_mld_scan_h__ #define __iwl_mld_scan_h__ @@ -151,11 +151,13 @@ struct iwl_mld_scan { * @time: time in ms the radio was on the channel * @time_busy: time in ms the channel was sensed busy + * @time_rx: time in ms the channel was sensed to carry Wi-Fi frames * @noise: channel noise in dBm / struct iwl_mld_survey_channel { u32 time; u32 time_busy; + u32 time_rx; s8 noise; }; diff --git a/drivers/net/wireless/intel/iwlwifi/mld/sta.c b/drivers/net/wireless/intel/iwlwifi/mld/sta.c index 7957ac11b0cd5..97f013330f068 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/sta.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/sta.c @@ -465,8 +465,8 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld mld, struct iwl_mld_sta mld_sta = iwl_mld_sta_from_mac80211(sta); struct iwl_sta_cfg_cmd cmd = {}; int fw_id = iwl_mld_fw_sta_id_from_link_sta(mld, link_sta); - bool is_6ghz, uora_exists; u32 link_mask; + bool is_6ghz; lockdep_assert_wiphy(mld->wiphy); @@ -479,7 +479,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld mld, return -EINVAL; is_6ghz = false; - uora_exists = false; link_mask = iwl_mld_get_nan_link_mask(mld); } else { @@ -495,7 +494,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld mld, link_mask = BIT(mld_link->fw_id); is_6ghz = link->chanreq.oper.chan->band == NL80211_BAND_6GHZ; - uora_exists = link->uora_exists; } cmd.sta_id = cpu_to_le32(fw_id); @@ -554,9 +552,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld mld, } if (link_sta->he_cap.has_he) { - cmd.trig_rnd_alloc = - cpu_to_le32(uora_exists ? 1 : 0); - /* PPE Thresholds / iwl_mld_fill_pkt_ext(mld, link_sta, &cmd.pkt_ext); diff --git a/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile b/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile index efa61638b8eeb..730185be3fa82 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile +++ b/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause iwlmld-tests-y += module.o hcmd.o utils.o link.o rx.o agg.o link-selection.o -iwlmld-tests-y += chan_load_thresh.o +iwlmld-tests-y += chan_load_thresh.o tx-gp2.o ccflags-y += -I$(src)/../ obj-$(CONFIG_IWLWIFI_KUNIT_TESTS) += iwlmld-tests.o diff --git a/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c b/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c new file mode 100644 index 0000000000000..535140eb17c47 --- /dev/null +++ b/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/ + * KUnit tests for TX gp2 timestamp handling + * + * Copyright (C) 2026 Intel Corporation + / +#include <kunit/test.h> + +#include "mld.h" +#include "tx.h" + +MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING"); + +static const struct tx_gp2_case { + const char desc; + u32 est_gp2_us; + u32 est_host_us; + u32 tx_host_us; + long valid_for; + u32 expected_gp2_us; + bool expected_refresh; +} tx_gp2_cases[] = { + { + .desc = "zero offset is valid", + .est_gp2_us = 2000, + .est_host_us = 2000, + .tx_host_us = 3500, + .valid_for = IWL_MLD_TX_GP2_VALID_PERIOD, + .expected_gp2_us = 3500, + }, + { + .desc = "gp2 behind host", + .est_gp2_us = 2000, + .est_host_us = 10000, + .tx_host_us = 11500, + .valid_for = IWL_MLD_TX_GP2_VALID_PERIOD, + .expected_gp2_us = 3500, + }, + { + .desc = "gp2 ahead of host", + .est_gp2_us = 10000, + .est_host_us = 2000, + .tx_host_us = 3500, + .valid_for = IWL_MLD_TX_GP2_VALID_PERIOD, + .expected_gp2_us = 11500, + }, + { + .desc = "gp2 wraps after the estimate", + .est_gp2_us = U32_MAX - 999, + .est_host_us = 1000, + .tx_host_us = 2500, + .valid_for = IWL_MLD_TX_GP2_VALID_PERIOD, + .expected_gp2_us = 500, + }, + { + .desc = "host time wraps after the estimate", + .est_gp2_us = 5000, + .est_host_us = U32_MAX - 999, + .tx_host_us = 500, + .valid_for = IWL_MLD_TX_GP2_VALID_PERIOD, + .expected_gp2_us = 6500, + }, + { + .desc = "gp2 landing on 0 is reported as 1", + .est_gp2_us = U32_MAX - 1499, + .est_host_us = 1000, + .tx_host_us = 2500, + .valid_for = IWL_MLD_TX_GP2_VALID_PERIOD, + .expected_gp2_us = 1, + }, + { + .desc = "within the refresh margin: still timestamped", + .est_gp2_us = 2000, + .est_host_us = 10000, + .tx_host_us = 11500, + .valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN - 1, + .expected_gp2_us = 3500, + .expected_refresh = true, + }, + { + .desc = "outside the refresh margin: no refresh", + .est_gp2_us = 2000, + .est_host_us = 10000, + .tx_host_us = 11500, + .valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN + 1, + .expected_gp2_us = 3500, + }, + { + .desc = "at the refresh threshold", + .est_gp2_us = 2000, + .est_host_us = 10000, + .tx_host_us = 11500, + .valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN, + .expected_gp2_us = 3500, + .expected_refresh = true, + }, + { + .desc = "last valid tick", + .est_gp2_us = 2000, + .est_host_us = 10000, + .tx_host_us = 11500, + .valid_for = 1, + .expected_gp2_us = 3500, + .expected_refresh = true, + }, + { + .desc = "validity reached: leave the frame unstamped", + .est_gp2_us = 2000, + .est_host_us = 10000, + .tx_host_us = 11500, + .valid_for = 0, + .expected_refresh = true, + }, + { + .desc = "validity passed: leave the frame unstamped", + .est_gp2_us = 2000, + .est_host_us = 10000, + .tx_host_us = 11500, + .valid_for = -1, + .expected_refresh = true, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(tx_gp2, tx_gp2_cases, desc); + +static void test_tx_gp2(struct kunit test) +{ + / Pin time near wraparound to exercise wrapped validity deadlines. / + const unsigned long now = + ULONG_MAX - IWL_MLD_TX_GP2_REFRESH_MARGIN - 1; + const struct tx_gp2_case test_case = test->param_value; + u32 delta_us = test_case->est_gp2_us - test_case->est_host_us; + unsigned long valid_until = now + test_case->valid_for; + bool refresh = !test_case->expected_refresh; + u32 timestamp; + + timestamp = iwl_mld_tx_gp2_from_est(delta_us, valid_until, + test_case->tx_host_us, now, + &refresh); + KUNIT_EXPECT_EQ(test, timestamp, test_case->expected_gp2_us); + KUNIT_EXPECT_EQ(test, refresh, test_case->expected_refresh); +} + +static struct kunit_case tx_gp2_test_cases[] = { + KUNIT_CASE_PARAM(test_tx_gp2, tx_gp2_gen_params), + {} +}; + +static struct kunit_suite tx_gp2_test_suite = { + .name = "iwl_mld_tx_gp2", + .test_cases = tx_gp2_test_cases, +}; + +kunit_test_suite(tx_gp2_test_suite); diff --git a/drivers/net/wireless/intel/iwlwifi/mld/tx.c b/drivers/net/wireless/intel/iwlwifi/mld/tx.c index 2df6643a5aa80..fc501ac0c1f29 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/tx.c +++ b/drivers/net/wireless/intel/iwlwifi/mld/tx.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2024 - 2026 Intel Corporation / +#include <linux/timekeeping.h> #include <net/ip.h> #include "tx.h" @@ -20,6 +21,133 @@ #define MAX_ANT_NUM 2 +static u32 iwl_mld_tx_gp2_host_us(void) +{ + return div_u64(ktime_get_boottime_ns(), NSEC_PER_USEC); +} + +/ Returns the gp2 for the TX command, or 0 to leave the frame unstamped. + * Sets @refresh when the estimate expired or is about to. + / +VISIBLE_IF_IWLWIFI_KUNIT u32 +iwl_mld_tx_gp2_from_est(u32 delta_us, unsigned long valid_until, u32 host_us, + unsigned long now, bool refresh) +{ + u32 gp2; + + refresh = time_after_eq(now, valid_until - + IWL_MLD_TX_GP2_REFRESH_MARGIN); + + if (time_after_eq(now, valid_until)) + return 0; + + gp2 = host_us + delta_us; + + / 0 means no timestamp; use 1 for a valid wrapped value. / + return gp2 ?: 1; +} +EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_mld_tx_gp2_from_est); + +static u32 +iwl_mld_tx_gp2_timestamp(struct iwl_mld mld) +{ + unsigned long valid_until = + atomic_long_read_acquire(&mld->tx_gp2.valid_until); + bool refresh = false; + u32 gp2; + + if (!valid_until) + return 0; + + gp2 = iwl_mld_tx_gp2_from_est(atomic_read(&mld->tx_gp2.delta_us), + valid_until, iwl_mld_tx_gp2_host_us(), + jiffies, &refresh); + + if (refresh) + wiphy_delayed_work_queue(mld->wiphy, &mld->tx_gp2.wk, 0); + + return gp2; +} + +static void iwl_mld_tx_gp2_refresh(struct iwl_mld mld) +{ + unsigned long valid_until, delay; + u32 gp2, host_us; + + lockdep_assert_wiphy(mld->wiphy); + + if (!mld->fw_status.running) + return; + +#ifdef CONFIG_PM_SLEEP + if (mld->fw_status.in_d3) + return; +#endif + + if (iwl_mld_get_systime(mld, &gp2)) + goto retry; + + host_us = iwl_mld_tx_gp2_host_us(); + valid_until = jiffies + IWL_MLD_TX_GP2_VALID_PERIOD; + + / Keep arithmetic in u32 to match firmware wraparound semantics. / + atomic_set(&mld->tx_gp2.delta_us, gp2 - host_us); + atomic_long_set_release(&mld->tx_gp2.valid_until, valid_until ?: 1); + + IWL_DEBUG_TX(mld, "gp2 sync: gp2=%u host_us=%u delta_us=%u\n", + gp2, host_us, gp2 - host_us); + return; + +retry: + / Stop new TX readers from requesting immediate retries. / + atomic_long_set(&mld->tx_gp2.valid_until, 0); + delay = round_jiffies_relative(IWL_MLD_TX_GP2_RETRY_PERIOD); + wiphy_delayed_work_queue(mld->wiphy, &mld->tx_gp2.wk, delay); +} + +static void iwl_mld_tx_gp2_wk(struct wiphy wiphy, struct wiphy_work wk) +{ + struct iwl_mld mld = container_of(wk, struct iwl_mld, tx_gp2.wk.work); + unsigned long valid_until = atomic_long_read(&mld->tx_gp2.valid_until); + + /* TX may have queued this work using an older estimate. / + if (valid_until && + time_before(jiffies, valid_until - IWL_MLD_TX_GP2_REFRESH_MARGIN)) + return; + + iwl_mld_tx_gp2_refresh(mld); +} + +void iwl_mld_tx_gp2_init(struct iwl_mld mld) +{ + atomic_set(&mld->tx_gp2.delta_us, 0); + atomic_long_set(&mld->tx_gp2.valid_until, 0); + wiphy_delayed_work_init(&mld->tx_gp2.wk, iwl_mld_tx_gp2_wk); +} + +void iwl_mld_tx_gp2_start(struct iwl_mld mld) +{ + lockdep_assert_wiphy(mld->wiphy); + + if (iwl_fw_lookup_cmd_ver(mld->fw, TX_CMD, 0) < 12) + return; + + iwl_mld_tx_gp2_refresh(mld); +} + +/ TX is quiesced before stopping the refresh work. / +void iwl_mld_tx_gp2_stop(struct iwl_mld mld) +{ + lockdep_assert_wiphy(mld->wiphy); + + if (iwl_fw_lookup_cmd_ver(mld->fw, TX_CMD, 0) < 12) + return; + + wiphy_delayed_work_cancel(mld->wiphy, &mld->tx_gp2.wk); + + atomic_long_set(&mld->tx_gp2.valid_until, 0); +} + /* Toggles between TX antennas. Receives the bitmask of valid TX antennas and * the index used for the last TX, and returns the next valid index to use. * In order to set it in the tx_cmd, must do BIT(idx). @@ -588,6 +716,9 @@ iwl_mld_fill_tx_cmd(struct iwl_mld mld, struct sk_buff skb, tx_cmd->flags = cpu_to_le16(flags); tx_cmd->rate_n_flags = rate_n_flags; + + tx_cmd->driver_timestamp = + cpu_to_le32(iwl_mld_tx_gp2_timestamp(mld)); } /* Caller of this need to check that info->control.vif is not NULL / diff --git a/drivers/net/wireless/intel/iwlwifi/mld/tx.h b/drivers/net/wireless/intel/iwlwifi/mld/tx.h index 520f15f9d33ca..a376e8c9c5005 100644 --- a/drivers/net/wireless/intel/iwlwifi/mld/tx.h +++ b/drivers/net/wireless/intel/iwlwifi/mld/tx.h @@ -1,11 +1,15 @@ / SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / / - * Copyright (C) 2024 Intel Corporation + * Copyright (C) 2024, 2026 Intel Corporation / #ifndef __iwl_mld_tx_h__ #define __iwl_mld_tx_h__ -#include "mld.h" +#include <linux/atomic.h> +#include <net/mac80211.h> + +struct iwl_mld; +struct iwl_rx_packet; #define IWL_MLD_INVALID_QUEUE 0xFFFF #define IWL_MLD_INVALID_DROP_TX 0xFFFE @@ -74,4 +78,37 @@ u8 iwl_mld_get_lowest_rate(struct iwl_mld mld, void iwl_mld_tx_skb(struct iwl_mld mld, struct sk_buff skb, struct ieee80211_txq txq); +/* + * struct iwl_mld_tx_gp2 - gp2 timestamping state for TX commands + * + * Reading gp2 directly in the TX path is too costly. Instead, TX lazily + * schedules @wk to refresh gp2 in process context and adds @delta_us to the + * host clock to timestamp queued frames. + * + * A zero @valid_until leaves frames unstamped, including on older firmware + * without TX_CMD v12. A deadline that wraps to zero is published as one. + * Failed refreshes clear @valid_until, leaving @delta_us for old readers, and + * schedule a retry with %IWL_MLD_TX_GP2_RETRY_PERIOD rounded for timer + * coalescing, even without further TX traffic. Old readers may retry sooner. + * + * @delta_us: gp2 minus host time, in microseconds, modulo 2^32; + * valid while @valid_until is nonzero and has not expired + * @valid_until: jiffies deadline for the offset, or zero when disabled + * @wk: worker that refreshes the offset and retries failures + / +struct iwl_mld_tx_gp2 { + atomic_t delta_us; + atomic_long_t valid_until; + struct wiphy_delayed_work wk; +}; + +void iwl_mld_tx_gp2_init(struct iwl_mld mld); +void iwl_mld_tx_gp2_start(struct iwl_mld mld); +void iwl_mld_tx_gp2_stop(struct iwl_mld mld); + +#if IS_ENABLED(CONFIG_IWLWIFI_KUNIT_TESTS) +u32 iwl_mld_tx_gp2_from_est(u32 delta_us, unsigned long valid_until, + u32 host_us, unsigned long now, bool refresh); +#endif + #endif / __iwl_mld_tx_h__ / diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c index 06502f57e823e..90175307a7db2 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c @@ -13,7 +13,7 @@ #include "mvm.h" #include "sta.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "debugfs.h" #include "iwl-modparams.h" #include "iwl-drv.h" @@ -1548,7 +1548,7 @@ iwl_dbgfs_prph_reg_read(struct file file, pos += scnprintf(buf + pos, bufsz - pos, "Reg 0x%x: (0x%x)\n", mvm->dbgfs_prph_reg_addr, - iwl_read_prph(mvm->trans, mvm->dbgfs_prph_reg_addr)); + iwl_trans_read_prph(mvm->trans, mvm->dbgfs_prph_reg_addr)); return simple_read_from_buffer(user_buf, count, ppos, buf, pos); } @@ -1569,7 +1569,7 @@ iwl_dbgfs_prph_reg_write(struct iwl_mvm mvm, char buf, if (args != 2) return -EINVAL; - iwl_write_prph(mvm->trans, mvm->dbgfs_prph_reg_addr, value); + iwl_trans_write_prph(mvm->trans, mvm->dbgfs_prph_reg_addr, value); out: return count; diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c index 8d7f60dcd0270..4c39a452564da 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c @@ -7,7 +7,7 @@ #include <linux/math64.h> #include <net/cfg80211.h> #include "mvm.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "constants.h" diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c index c3402f5e47a03..ae109e3ea141c 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c @@ -263,7 +263,7 @@ static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data notif_wait, static void iwl_mvm_print_pd_notification(struct iwl_mvm mvm) { #define IWL_FW_PRINT_REG_INFO(reg_name) \ - IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name)) + IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_trans_read_umac_prph(trans, reg_name)) struct iwl_trans trans = mvm->trans; enum iwl_device_family device_family = trans->mac_cfg->device_family; @@ -332,13 +332,13 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm mvm, IWL_DEVICE_FAMILY_AX210) { /* print these registers regardless of alive fail/success / IWL_INFO(mvm, "WFPM_UMAC_PD_NOTIFICATION: 0x%x\n", - iwl_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION)); + iwl_trans_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION)); IWL_INFO(mvm, "WFPM_LMAC2_PD_NOTIFICATION: 0x%x\n", - iwl_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION)); + iwl_trans_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION)); IWL_INFO(mvm, "WFPM_AUTH_KEY_0: 0x%x\n", - iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG)); + iwl_trans_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG)); IWL_INFO(mvm, "CNVI_SCU_SEQ_DATA_DW9: 0x%x\n", - iwl_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9)); + iwl_trans_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9)); } if (ret) { @@ -349,15 +349,15 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm mvm, IWL_DEVICE_FAMILY_22000) { IWL_ERR(mvm, "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", - iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), - iwl_read_umac_prph(trans, - UMAG_SB_CPU_2_STATUS)); + iwl_trans_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), + iwl_trans_read_umac_prph(trans, + UMAG_SB_CPU_2_STATUS)); } else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) { IWL_ERR(mvm, "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", - iwl_read_prph(trans, SB_CPU_1_STATUS), - iwl_read_prph(trans, SB_CPU_2_STATUS)); + iwl_trans_read_prph(trans, SB_CPU_1_STATUS), + iwl_trans_read_prph(trans, SB_CPU_2_STATUS)); } iwl_mvm_print_pd_notification(mvm); @@ -374,15 +374,15 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm mvm, } else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { IWL_ERR(mvm, "UMAC PC: 0x%x\n", - iwl_read_umac_prph(trans, - UREG_UMAC_CURRENT_PC)); + iwl_trans_read_umac_prph(trans, + UREG_UMAC_CURRENT_PC)); IWL_ERR(mvm, "LMAC PC: 0x%x\n", - iwl_read_umac_prph(trans, - UREG_LMAC1_CURRENT_PC)); + iwl_trans_read_umac_prph(trans, + UREG_LMAC1_CURRENT_PC)); if (iwl_mvm_is_cdb_supported(mvm)) IWL_ERR(mvm, "LMAC2 PC: 0x%x\n", - iwl_read_umac_prph(trans, - UREG_LMAC2_CURRENT_PC)); + iwl_trans_read_umac_prph(trans, + UREG_LMAC2_CURRENT_PC)); } if (ret == -ETIMEDOUT && !mvm->fw_product_reset) @@ -616,7 +616,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm mvm) mvm->rfkill_safe_init_done = false; if (mvm->trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { - sb_cfg = iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG); + sb_cfg = iwl_trans_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG); /* if needed, we'll reset this on our way out later / mvm->fw_product_reset = sb_cfg == SB_CFG_RESIDES_IN_ROM; if (mvm->fw_product_reset && iwl_mei_pldr_req()) @@ -640,8 +640,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm mvm) /* if we needed reset then fail here, but notify and remove / if (mvm->fw_product_reset) { iwl_mei_alive_notif(false); - iwl_trans_pcie_reset(mvm->trans, - IWL_RESET_MODE_RESCAN); + iwl_trans_reset(mvm->trans, IWL_RESET_MODE_RESCAN); } goto error; diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/led.c b/drivers/net/wireless/intel/iwlwifi/mvm/led.c index c3cc1ea3ccc93..ac238c9638559 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/led.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/led.c @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / - * Copyright (C) 2012-2014, 2018-2019, 2025 Intel Corporation + * Copyright (C) 2012-2014, 2018-2019, 2025-2026 Intel Corporation * Copyright (C) 2017 Intel Deutschland GmbH / #include <linux/leds.h> -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-csr.h" #include "mvm.h" @@ -38,8 +38,8 @@ static void iwl_mvm_led_set(struct iwl_mvm mvm, bool on) return; } - iwl_write32(mvm->trans, CSR_LED_REG, - on ? CSR_LED_REG_TURN_ON : CSR_LED_REG_TURN_OFF); + iwl_trans_write32(mvm->trans, CSR_LED_REG, + on ? CSR_LED_REG_TURN_ON : CSR_LED_REG_TURN_OFF); } static void iwl_led_brightness_set(struct led_classdev led_cdev, diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c index b2c5be22c293c..509e80fa0df5e 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c @@ -7,7 +7,7 @@ #include <linux/etherdevice.h> #include <linux/crc32.h> #include <net/mac80211.h> -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "fw-api.h" #include "mvm.h" diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c index a4f3d3c2bd350..daa05339e3fbf 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c @@ -19,7 +19,7 @@ #include "iwl-drv.h" #include "iwl-op-mode.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "mvm.h" #include "sta.h" #include "time-event.h" diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c index 93d5cab87f645..1832514573612 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c @@ -20,7 +20,6 @@ #include "iwl-phy-db.h" #include "iwl-nvm-utils.h" #include "iwl-csr.h" -#include "iwl-io.h" #include "iwl-prph.h" #include "rs.h" #include "fw/api/scan.h" @@ -138,9 +137,9 @@ static void iwl_mvm_nic_config(struct iwl_op_mode op_mode) * to lose ownership and not being able to obtain it back. / if (!mvm->trans->mac_cfg->base->apmg_not_supported) - iwl_set_bits_mask_prph(mvm->trans, APMG_PS_CTRL_REG, - APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, - ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); + iwl_trans_set_bits_mask_prph(mvm->trans, APMG_PS_CTRL_REG, + APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, + ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); } static void iwl_mvm_rx_monitor_notif(struct iwl_mvm mvm, diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c index a94eaca0b3ed5..c12eda75317d1 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c @@ -10,7 +10,7 @@ #include "mvm.h" #include "fw/api/scan.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-utils.h" #define IWL_DENSE_EBS_SCAN_RATIO 5 diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c b/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c index a7cd2e4ba1ae9..6aac71cfccb3e 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c @@ -2,12 +2,12 @@ /* * Copyright (C) 2014 Intel Mobile Communications GmbH * Copyright (C) 2017 Intel Deutschland GmbH - * Copyright (C) 2018-2020, 2022-2025 Intel Corporation + * Copyright (C) 2018-2020, 2022-2026 Intel Corporation / #include <linux/etherdevice.h> #include "mvm.h" #include "time-event.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #define TU_TO_US(x) (x 1024) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c index 93b46c9e2333d..5a800d3f2a98f 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c @@ -12,7 +12,6 @@ #include "fw-api.h" #include "time-event.h" #include "mvm.h" -#include "iwl-io.h" #include "iwl-prph.h" /* diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c index 2fd4a99611450..e97ab2c9e5ba7 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c @@ -7,7 +7,7 @@ #include <net/mac80211.h> #include "iwl-debug.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-prph.h" #include "iwl-csr.h" #include "mvm.h" @@ -1159,7 +1159,7 @@ u32 iwl_mvm_get_systime(struct iwl_mvm mvm) mvm->trans->mac_cfg->base->gp2_reg_addr) reg_addr = mvm->trans->mac_cfg->base->gp2_reg_addr; - return iwl_read_prph(mvm->trans, reg_addr); + return iwl_trans_read_prph(mvm->trans, reg_addr); } void iwl_mvm_get_sync_time(struct iwl_mvm mvm, int clock_type, diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c index c75210829ec94..0009a05511af1 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c @@ -7,6 +7,7 @@ #include "iwl-fh.h" #include "iwl-context-info-v2.h" #include "internal.h" +#include "pcie/utils.h" #include "iwl-prph.h" static const struct dmi_system_id dmi_force_scu_active_approved_list[] = { @@ -314,12 +315,12 @@ void iwl_pcie_ctxt_info_v2_kick(struct iwl_trans trans) iwl_enable_fw_load_int_ctx_info(trans, trans->do_top_reset); / kick FW self load / - iwl_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie->ctxt_info_dma_addr); - iwl_write64(trans, CSR_IML_DATA_ADDR, trans_pcie->iml_dma_addr); - iwl_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie->iml_len); + iwl_pcie_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie->ctxt_info_dma_addr); + iwl_pcie_write64(trans, CSR_IML_DATA_ADDR, trans_pcie->iml_dma_addr); + iwl_trans_pcie_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie->iml_len); - iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, - CSR_AUTO_FUNC_BOOT_ENA); + iwl_trans_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, + CSR_AUTO_FUNC_BOOT_ENA); } void iwl_pcie_ctxt_info_v2_free(struct iwl_trans trans, bool alive) diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c index 23ec968577bd9..bc90a2714251a 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c @@ -7,6 +7,7 @@ #include "iwl-fh.h" #include "iwl-context-info.h" #include "internal.h" +#include "utils.h" #include "iwl-prph.h" static void _iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans trans, @@ -245,7 +246,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans trans, iwl_pcie_apply_destination(trans); / kick FW self load / - iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr); + iwl_pcie_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr); / Context info will be released upon alive or failure to get one / diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c index 905482419a9af..24012005ccb87 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c @@ -1252,7 +1252,7 @@ static int _iwl_pci_resume(struct device device, bool restore) * For older devices, just try silently to grab the NIC. / if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { - u32 scratch = iwl_read32(trans, CSR_FUNC_SCRATCH); + u32 scratch = iwl_trans_pcie_read32(trans, CSR_FUNC_SCRATCH); if (!(scratch & CSR_FUNC_SCRATCH_POWER_OFF_MASK) \|\| scratch == ~0U) { diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h index e6b1cb559a0a6..01bfc1492c848 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h +++ b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h @@ -18,12 +18,22 @@ #include "iwl-fh.h" #include "iwl-csr.h" #include "iwl-trans.h" +#include "iwl-devtrace.h" #include "iwl-debug.h" -#include "iwl-io.h" #include "iwl-op-mode.h" #include "iwl-drv.h" #include "iwl-context-info.h" +/ transport-specific register accessors (bus implementation) / +void iwl_trans_pcie_write8(struct iwl_trans trans, u32 ofs, u8 val); +void iwl_trans_pcie_write32(struct iwl_trans trans, u32 ofs, u32 val); +u32 iwl_trans_pcie_read32(struct iwl_trans trans, u32 ofs); +u32 iwl_trans_pcie_read_prph(struct iwl_trans trans, u32 reg); +void iwl_pcie_write_prph_no_grab(struct iwl_trans trans, u32 addr, u32 val); + +/* bus-specific transport operations table / +extern const struct iwl_trans_ops iwl_trans_pcie_ops; + / * RX related structures and functions / @@ -593,7 +603,7 @@ static inline void iwl_pcie_clear_irq(struct iwl_trans trans, int queue) * write 1 clear (W1C) register, meaning that it's being clear * by writing 1 to the bit. / - iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue)); + iwl_trans_pcie_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue)); } static inline struct iwl_trans @@ -889,18 +899,18 @@ static inline void _iwl_disable_interrupts(struct iwl_trans trans) clear_bit(STATUS_INT_ENABLED, &trans->status); if (!trans_pcie->msix_enabled) { / disable interrupts from uCode/NIC to host / - iwl_write32(trans, CSR_INT_MASK, 0x00000000); + iwl_trans_pcie_write32(trans, CSR_INT_MASK, 0x00000000); / acknowledge/clear/reset any interrupts still pending * from uCode or flow handler (Rx/Tx DMA) / - iwl_write32(trans, CSR_INT, 0xffffffff); - iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); + iwl_trans_pcie_write32(trans, CSR_INT, 0xffffffff); + iwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); } else { / disable all the interrupt we might use / - iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, - trans_pcie->fh_init_mask); - iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, - trans_pcie->hw_init_mask); + iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, + trans_pcie->fh_init_mask); + iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD, + trans_pcie->hw_init_mask); trans_pcie->fh_mask = 0; trans_pcie->hw_mask = 0; } @@ -958,7 +968,7 @@ static inline void _iwl_enable_interrupts(struct iwl_trans trans) set_bit(STATUS_INT_ENABLED, &trans->status); if (!trans_pcie->msix_enabled) { trans_pcie->inta_mask = CSR_INI_SET_MASK; - iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); + iwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); } else { /* * fh/hw_mask keeps all the unmasked causes. @@ -966,10 +976,10 @@ static inline void _iwl_enable_interrupts(struct iwl_trans trans) / trans_pcie->hw_mask = trans_pcie->hw_init_mask; trans_pcie->fh_mask = trans_pcie->fh_init_mask; - iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, - ~trans_pcie->fh_mask); - iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, - ~trans_pcie->hw_mask); + iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, + ~trans_pcie->fh_mask); + iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD, + ~trans_pcie->hw_mask); } } @@ -985,7 +995,7 @@ static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans trans, u32 msk) { struct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); - iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); + iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); trans_pcie->hw_mask = msk; } @@ -993,7 +1003,7 @@ static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans trans, u32 msk) { struct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); - iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); + iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); trans_pcie->fh_mask = msk; } @@ -1004,10 +1014,10 @@ static inline void iwl_enable_fw_load_int(struct iwl_trans trans) IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); if (!trans_pcie->msix_enabled) { trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; - iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); + iwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); } else { - iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, - trans_pcie->hw_init_mask); + iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD, + trans_pcie->hw_init_mask); iwl_enable_fh_int_msk_msix(trans, MSIX_FH_INT_CAUSES_D2S_CH0_NUM); } @@ -1034,7 +1044,7 @@ static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans trans, else trans_pcie->inta_mask = CSR_INT_BIT_ALIVE \| CSR_INT_BIT_FH_RX; - iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); + iwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); } else { u32 val = top_reset ? MSIX_HW_INT_CAUSES_REG_RESET_DONE : MSIX_HW_INT_CAUSES_REG_ALIVE; @@ -1081,10 +1091,10 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans trans) IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); if (!trans_pcie->msix_enabled) { trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; - iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); + iwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); } else { - iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, - trans_pcie->fh_init_mask); + iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, + trans_pcie->fh_init_mask); trans_pcie->fh_mask = 0; iwl_enable_hw_int_msk_msix(trans, MSIX_HW_INT_CAUSES_REG_RF_KILL); @@ -1096,8 +1106,8 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans trans) * when we power down the device we need set the bit to allow it * to wake up the PCI-E bus for RF-kill interrupts. / - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); } } @@ -1112,7 +1122,7 @@ static inline bool iwl_is_rfkill_set(struct iwl_trans trans) if (trans_pcie->debug_rfkill == 1) return true; - return !(iwl_read32(trans, CSR_GP_CNTRL) & + return !(iwl_trans_pcie_read32(trans, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); } @@ -1136,16 +1146,12 @@ void iwl_trans_pcie_op_mode_enter(struct iwl_trans trans); int _iwl_trans_pcie_start_hw(struct iwl_trans trans); int iwl_trans_pcie_start_hw(struct iwl_trans trans); void iwl_trans_pcie_op_mode_leave(struct iwl_trans trans); -void iwl_trans_pcie_write8(struct iwl_trans trans, u32 ofs, u8 val); -void iwl_trans_pcie_write32(struct iwl_trans trans, u32 ofs, u32 val); -u32 iwl_trans_pcie_read32(struct iwl_trans trans, u32 ofs); -u32 iwl_trans_pcie_read_prph(struct iwl_trans trans, u32 reg); -void iwl_trans_pcie_write_prph(struct iwl_trans trans, u32 addr, u32 val); int iwl_trans_pcie_read_mem(struct iwl_trans trans, u32 addr, void buf, int dwords); int iwl_trans_pcie_read_mem_no_grab(struct iwl_trans trans, u32 addr, void buf, u32 dwords); int iwl_trans_pcie_sw_reset(struct iwl_trans trans, bool retake_ownership); +void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans trans); struct iwl_trans_dump_data iwl_trans_pcie_dump_data(struct iwl_trans trans, u32 dump_mask, const struct iwl_dump_sanitize_ops sanitize_ops, diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c index db3933b0d1979..f033bb51dcca3 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c @@ -9,8 +9,9 @@ #include <linux/gfp.h> #include "iwl-prph.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "internal.h" +#include "pcie/utils.h" #include "iwl-op-mode.h" #include "iwl-context-info-v2.h" #include "fw/dbg.h" @@ -146,18 +147,18 @@ int iwl_pcie_rx_stop(struct iwl_trans trans) { if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { / TODO: remove this once fw does it / - iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0); - return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210, - RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); + iwl_trans_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0); + return iwl_pcie_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210, + RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); } else if (trans->mac_cfg->mq_rx_supported) { - iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); - return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, - RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); + iwl_trans_write_prph(trans, RFH_RXF_DMA_CFG, 0); + return iwl_pcie_poll_prph_bit(trans, RFH_GEN_STATUS, + RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); } else { - iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); - return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, - FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, - 1000); + iwl_trans_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); + return iwl_pcie_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, + FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, + 1000); } } @@ -178,13 +179,13 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans trans, / if (!trans->mac_cfg->base->shadow_reg_enable && test_bit(STATUS_TPOWER_PMI, &trans->status)) { - reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); + reg = iwl_trans_pcie_read32(trans, CSR_UCODE_DRV_GP1); if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", reg); - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); rxq->need_update = true; return; } @@ -192,13 +193,13 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans trans, rxq->write_actual = round_down(rxq->write, 8); if (!trans->mac_cfg->mq_rx_supported) - iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); + iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) - iwl_write32(trans, HBUS_TARG_WRPTR, rxq->write_actual \| - HBUS_TARG_WRPTR_RX_Q(rxq->id)); + iwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, rxq->write_actual \| + HBUS_TARG_WRPTR_RX_Q(rxq->id)); else - iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), - rxq->write_actual); + iwl_trans_pcie_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), + rxq->write_actual); } static void iwl_pcie_rxq_check_wrptr(struct iwl_trans trans) @@ -854,22 +855,22 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans trans, struct iwl_rxq rxq) return; / Stop Rx DMA / - iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); + iwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); / reset and flush pointers / - iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); - iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); - iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); + iwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); + iwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); + iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); / Reset driver's Rx queue write index / - iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); + iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); / Tell device where to find RBD circular buffer in DRAM / - iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, - (u32)(rxq->bd_dma >> 8)); + iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, + (u32)(rxq->bd_dma >> 8)); / Tell device where in DRAM to update its Rx status / - iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, - rxq->rb_stts_dma >> 4); + iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, + rxq->rb_stts_dma >> 4); / Enable Rx DMA * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in @@ -879,22 +880,22 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans trans, struct iwl_rxq rxq) * RB timeout 0x10 * 256 RBDs / - iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, - FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL \| - FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY \| - FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL \| - rb_size \| - (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) \| - (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); + iwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, + FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL \| + FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY \| + FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL \| + rb_size \| + (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) \| + (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); iwl_trans_release_nic_access(trans); / Set interrupt coalescing timer to default (2048 usecs) / - iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); + iwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); / W/A for interrupt coalescing bug in 7260 and 3160 / if (trans->cfg->host_interrupt_operation_mode) - iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); + iwl_trans_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); } static void iwl_pcie_rx_mq_hw_init(struct iwl_trans trans) @@ -925,27 +926,27 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans trans) return; / Stop Rx DMA / - iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); + iwl_pcie_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); / disable free amd used rx queue operation / - iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); + iwl_pcie_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); for (i = 0; i < trans->info.num_rxqs; i++) { / Tell device where to find RBD free table in DRAM / - iwl_write_prph64_no_grab(trans, - RFH_Q_FRBDCB_BA_LSB(i), - trans_pcie->rxq[i].bd_dma); + iwl_pcie_write_prph64_no_grab(trans, + RFH_Q_FRBDCB_BA_LSB(i), + trans_pcie->rxq[i].bd_dma); / Tell device where to find RBD used table in DRAM / - iwl_write_prph64_no_grab(trans, - RFH_Q_URBDCB_BA_LSB(i), - trans_pcie->rxq[i].used_bd_dma); + iwl_pcie_write_prph64_no_grab(trans, + RFH_Q_URBDCB_BA_LSB(i), + trans_pcie->rxq[i].used_bd_dma); / Tell device where in DRAM to update its Rx status / - iwl_write_prph64_no_grab(trans, - RFH_Q_URBD_STTS_WPTR_LSB(i), - trans_pcie->rxq[i].rb_stts_dma); + iwl_pcie_write_prph64_no_grab(trans, + RFH_Q_URBD_STTS_WPTR_LSB(i), + trans_pcie->rxq[i].rb_stts_dma); / Reset device indice tables / - iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); - iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); - iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); + iwl_pcie_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); + iwl_pcie_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); + iwl_pcie_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); enabled \|= BIT(i) \| BIT(i + 16); } @@ -957,32 +958,32 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans trans) * Drop frames that exceed RB size * 512 RBDs / - iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, - RFH_DMA_EN_ENABLE_VAL \| rb_size \| - RFH_RXF_DMA_MIN_RB_4_8 \| - RFH_RXF_DMA_DROP_TOO_LARGE_MASK \| - RFH_RXF_DMA_RBDCB_SIZE_512); + iwl_pcie_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, + RFH_DMA_EN_ENABLE_VAL \| rb_size \| + RFH_RXF_DMA_MIN_RB_4_8 \| + RFH_RXF_DMA_DROP_TOO_LARGE_MASK \| + RFH_RXF_DMA_RBDCB_SIZE_512); / * Activate DMA snooping. * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe * Default queue is 0 / - iwl_write_prph_no_grab(trans, RFH_GEN_CFG, - RFH_GEN_CFG_RFH_DMA_SNOOP \| - RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) \| - RFH_GEN_CFG_SERVICE_DMA_SNOOP \| - RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, - trans->mac_cfg->integrated ? - RFH_GEN_CFG_RB_CHUNK_SIZE_64 : - RFH_GEN_CFG_RB_CHUNK_SIZE_128)); + iwl_pcie_write_prph_no_grab(trans, RFH_GEN_CFG, + RFH_GEN_CFG_RFH_DMA_SNOOP \| + RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) \| + RFH_GEN_CFG_SERVICE_DMA_SNOOP \| + RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, + trans->mac_cfg->integrated ? + RFH_GEN_CFG_RB_CHUNK_SIZE_64 : + RFH_GEN_CFG_RB_CHUNK_SIZE_128)); / Enable the relevant rx queues / - iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); + iwl_pcie_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); iwl_trans_release_nic_access(trans); / Set interrupt coalescing timer to default (2048 usecs) / - iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); + iwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); } void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq rxq) @@ -1189,7 +1190,7 @@ int iwl_pcie_rx_init(struct iwl_trans trans) int iwl_pcie_gen2_rx_init(struct iwl_trans trans) { /* Set interrupt coalescing timer to default (2048 usecs) / - iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); + iwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); / * We don't configure the RFH. @@ -1691,9 +1692,9 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans trans) / W/A for WiFi/WiMAX coex and WiMAX own the RF / if (trans->cfg->internal_wimax_coex && !trans->mac_cfg->base->apmg_not_supported && - (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & + (!(iwl_trans_read_prph(trans, APMG_CLK_CTRL_REG) & APMS_CLK_VAL_MRB_FUNC_MODE) \|\| - (iwl_read_prph(trans, APMG_PS_CTRL_REG) & + (iwl_trans_read_prph(trans, APMG_PS_CTRL_REG) & APMG_PS_CTRL_VAL_RESET_REQ))) { clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); iwl_op_mode_wimax_active(trans->op_mode); @@ -1708,7 +1709,7 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans trans) } if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_SC) { - u32 val = iwl_read32(trans, CSR_IPC_STATE); + u32 val = iwl_trans_pcie_read32(trans, CSR_IPC_STATE); if (val & CSR_IPC_STATE_TOP_RESET_REQ) { IWL_ERR(trans, "FW requested TOP reset for FSEQ\n"); @@ -1733,7 +1734,7 @@ static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans trans) trace_iwlwifi_dev_irq(trans->dev); / Discover which interrupts are active/pending / - inta = iwl_read32(trans, CSR_INT); + inta = iwl_trans_pcie_read32(trans, CSR_INT); / the thread will service interrupts and re-enable them / return inta; @@ -1850,7 +1851,7 @@ static void iwl_trans_pcie_handle_reset_interrupt(struct iwl_trans trans) u32 state; if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_SC) { - u32 val = iwl_read32(trans, CSR_IPC_STATE); + u32 val = iwl_trans_pcie_read32(trans, CSR_IPC_STATE); state = u32_get_bits(val, CSR_IPC_STATE_RESET); IWL_DEBUG_ISR(trans, "IPC state = 0x%x/%d\n", val, state); @@ -1922,8 +1923,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id) IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", inta, trans_pcie->inta_mask, - iwl_read32(trans, CSR_INT_MASK), - iwl_read32(trans, CSR_FH_INT_STATUS)); + iwl_trans_pcie_read32(trans, CSR_INT_MASK), + iwl_trans_pcie_read32(trans, CSR_FH_INT_STATUS)); if (inta & (~trans_pcie->inta_mask)) IWL_DEBUG_ISR(trans, "We got a masked interrupt (0x%08x)\n", @@ -1971,11 +1972,11 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id) * hardware bugs here by ACKing all the possible interrupts so that * interrupt coalescing can still be achieved. / - iwl_write32(trans, CSR_INT, inta \| ~trans_pcie->inta_mask); + iwl_trans_pcie_write32(trans, CSR_INT, inta \| ~trans_pcie->inta_mask); if (iwl_have_debug_level(IWL_DL_ISR)) IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", - inta, iwl_read32(trans, CSR_INT_MASK)); + inta, iwl_trans_pcie_read32(trans, CSR_INT_MASK)); spin_unlock_bh(&trans_pcie->irq_lock); @@ -2070,13 +2071,13 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id) IWL_DEBUG_ISR(trans, "Rx interrupt\n"); if (inta & (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX)) { handled \|= (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX); - iwl_write32(trans, CSR_FH_INT_STATUS, - CSR_FH_INT_RX_MASK); + iwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, + CSR_FH_INT_RX_MASK); } if (inta & CSR_INT_BIT_RX_PERIODIC) { handled \|= CSR_INT_BIT_RX_PERIODIC; - iwl_write32(trans, - CSR_INT, CSR_INT_BIT_RX_PERIODIC); + iwl_trans_pcie_write32(trans, + CSR_INT, CSR_INT_BIT_RX_PERIODIC); } /* Sending RX interrupt require many steps to be done in the * device: @@ -2090,8 +2091,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id) / /* Disable periodic interrupt; we use it as just a one-shot. / - iwl_write8(trans, CSR_INT_PERIODIC_REG, - CSR_INT_PERIODIC_DIS); + iwl_trans_pcie_write8(trans, CSR_INT_PERIODIC_REG, + CSR_INT_PERIODIC_DIS); / * Enable periodic interrupt in 8 msec only if we received @@ -2101,8 +2102,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id) to extend the periodic interrupt; one-shot is enough. / if (inta & (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX)) - iwl_write8(trans, CSR_INT_PERIODIC_REG, - CSR_INT_PERIODIC_ENA); + iwl_trans_pcie_write8(trans, CSR_INT_PERIODIC_REG, + CSR_INT_PERIODIC_ENA); isr_stats->rx++; @@ -2116,7 +2117,7 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void dev_id) /* This "Tx" DMA channel is used only for loading uCode / if (inta & CSR_INT_BIT_FH_TX) { - iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); + iwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); isr_stats->tx++; handled \|= CSR_INT_BIT_FH_TX; @@ -2230,10 +2231,10 @@ void iwl_pcie_reset_ict(struct iwl_trans trans) IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); - iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); + iwl_trans_pcie_write32(trans, CSR_DRAM_INT_TBL_REG, val); trans_pcie->use_ict = true; trans_pcie->ict_index = 0; - iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); + iwl_trans_pcie_write32(trans, CSR_INT, trans_pcie->inta_mask); _iwl_enable_interrupts(trans); spin_unlock_bh(&trans_pcie->irq_lock); } @@ -2260,7 +2261,7 @@ irqreturn_t iwl_pcie_isr(int irq, void data) If we have something to service, the tasklet will re-enable ints. * If we don't have something, we'll re-enable before leaving here. / - iwl_write32(trans, CSR_INT_MASK, 0x00000000); + iwl_trans_pcie_write32(trans, CSR_INT_MASK, 0x00000000); return IRQ_WAKE_THREAD; } @@ -2290,13 +2291,13 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void dev_id) lock_map_acquire(&trans->sync_cmd_lockdep_map); spin_lock_bh(&trans_pcie->irq_lock); - inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); - inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); + inta_fh = iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); + inta_hw = iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); /* * Clear causes registers to avoid being handling the same cause. / - iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk); - iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); + iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk); + iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); spin_unlock_bh(&trans_pcie->irq_lock); trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); @@ -2311,7 +2312,7 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void dev_id) IWL_DEBUG_ISR(trans, "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", entry->entry, inta_fh, trans_pcie->fh_mask, - iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); + iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); if (inta_fh & ~trans_pcie->fh_mask) IWL_DEBUG_ISR(trans, "We got a masked interrupt (0x%08x)\n", @@ -2413,7 +2414,7 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void dev_id) IWL_DEBUG_ISR(trans, "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", entry->entry, inta_hw, trans_pcie->hw_mask, - iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); + iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); if (inta_hw & ~trans_pcie->hw_mask) IWL_DEBUG_ISR(trans, "We got a masked interrupt 0x%08x\n", diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c index 39dd963920b31..dce6043fe9627 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c @@ -32,18 +32,18 @@ int iwl_pcie_gen2_apm_init(struct iwl_trans trans) * Disable L0s without affecting L1; * don't wait for ICH L0s (ICH bug W/A) / - iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, - CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); + iwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS, + CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); / Set FH wait threshold to maximum (HW error during stress W/A) / - iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); + iwl_trans_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); / * Enable HAP INTA (interrupt from management bus) to * wake device's PCI Express link L1a -> L0s / - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_HAP_WAKE); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_HAP_WAKE); iwl_pcie_apm_config(trans); @@ -65,14 +65,14 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans trans, bool op_mode_leave) iwl_pcie_gen2_apm_init(trans); /* inform ME that we are leaving / - iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, - CSR_RESET_LINK_PWR_MGMT_DISABLED); - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_WAKE_ME \| - CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN); + iwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, + CSR_RESET_LINK_PWR_MGMT_DISABLED); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_WAKE_ME \| + CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN); mdelay(1); - iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, - CSR_RESET_LINK_PWR_MGMT_DISABLED); + iwl_trans_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, + CSR_RESET_LINK_PWR_MGMT_DISABLED); mdelay(5); } @@ -88,11 +88,11 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans trans, bool op_mode_leave) * D0A* (powered-up Active) --> D0U* (Uninitialized) state. / if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_INIT); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_INIT); else - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_INIT_DONE); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_INIT_DONE); } static void @@ -105,14 +105,14 @@ _iwl_trans_pcie_fw_reset_handshake(struct iwl_trans trans, trans_pcie->fw_reset_state = FW_RESET_REQUESTED; if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) - iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, - UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE); + iwl_trans_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, + UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE); else if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) - iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, - UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); + iwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, + UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); else - iwl_write32(trans, CSR_DOORBELL_VECTOR, - UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); + iwl_trans_pcie_write32(trans, CSR_DOORBELL_VECTOR, + UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); /* wait 200ms / ret = wait_event_timeout(trans_pcie->fw_reset_waitq, @@ -123,11 +123,11 @@ _iwl_trans_pcie_fw_reset_handshake(struct iwl_trans trans, u32 inta_hw; if (trans_pcie->msix_enabled) { - inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); + inta_hw = iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); reset_done = inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE; } else { - inta_hw = iwl_read32(trans, CSR_INT); + inta_hw = iwl_trans_pcie_read32(trans, CSR_INT); reset_done = inta_hw & CSR_INT_BIT_RESET_DONE; } @@ -281,7 +281,7 @@ static int iwl_pcie_gen2_nic_init(struct iwl_trans trans) return -ENOMEM; / enable shadow regs in HW / - iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); + iwl_trans_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); return 0; @@ -342,7 +342,7 @@ static void iwl_pcie_get_rf_name(struct iwl_trans trans) case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): - version = iwl_read_prph(trans, CNVI_MBOX_C); + version = iwl_trans_read_prph(trans, CNVI_MBOX_C); switch (version) { case 0x20000: pos += scnprintf(buf + pos, buflen - pos, " B3"); @@ -410,7 +410,7 @@ void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans trans) step_reg = trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_SC ? CNVI_PMU_STEP_FLOW_SC : CNVI_PMU_STEP_FLOW_BZ; - trans->step_urm = !!(iwl_read_prph(trans, step_reg) & + trans->step_urm = !!(iwl_trans_read_prph(trans, step_reg) & CNVI_PMU_STEP_FLOW_FORCE_URM); } @@ -434,21 +434,21 @@ static bool iwl_pcie_set_ltr(struct iwl_trans trans) if ((trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210 \|\| trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000) && !trans->mac_cfg->integrated) { - iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val); + iwl_trans_pcie_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val); return true; } if (trans->mac_cfg->integrated && trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000) { - iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL); - iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val); + iwl_trans_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL); + iwl_trans_write_prph(trans, HPM_UMAC_LTR, ltr_val); return true; } if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { /* First clear the interrupt, just in case / - iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, - MSIX_HW_INT_CAUSES_REG_IML); + iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, + MSIX_HW_INT_CAUSES_REG_IML); / In this case, unfortunately the same ROM bug exists in the * device (not setting LTR correctly), but we don't have control * over the settings from the host due to some hardware security @@ -475,18 +475,18 @@ static void iwl_pcie_spin_for_iml(struct iwl_trans trans) if (WARN_ON(!trans_pcie->iml)) return; - value = iwl_read32(trans, CSR_LTR_LAST_MSG); + value = iwl_trans_pcie_read32(trans, CSR_LTR_LAST_MSG); IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n", value); while (time_before(jiffies, end_time)) { - if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) & + if (iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) & MSIX_HW_INT_CAUSES_REG_IML) { irq = true; break; } / Keep the CPU and device busy. / - value = iwl_read32(trans, CSR_LTR_LAST_MSG); + value = iwl_trans_pcie_read32(trans, CSR_LTR_LAST_MSG); loops++; } @@ -522,7 +522,7 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans trans, iwl_enable_rfkill_int(trans); - iwl_write32(trans, CSR_INT, 0xFFFFFFFF); + iwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF); /* * We enabled the RF-Kill interrupt and the handler may very @@ -550,12 +550,12 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans trans, } / make sure rfkill handshake bits are cleared / - iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); - iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, - CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); + iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); + iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, + CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); / clear (again), then enable host interrupts / - iwl_write32(trans, CSR_INT, 0xFFFFFFFF); + iwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF); ret = iwl_pcie_gen2_nic_init(trans); if (ret) { @@ -591,14 +591,14 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans trans, if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { IWL_DEBUG_POWER(trans, "function scratch register value is 0x%08x\n", - iwl_read32(trans, CSR_FUNC_SCRATCH)); - iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE); - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_ROM_START); + iwl_trans_pcie_read32(trans, CSR_FUNC_SCRATCH)); + iwl_trans_pcie_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_ROM_START); } else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { - iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); + iwl_trans_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); } else { - iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1); + iwl_trans_write_prph(trans, UREG_CPU_INIT_RUN, 1); } if (keep_ram_busy) diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c index bda069a6f7ebf..eda88940dd074 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c @@ -44,10 +44,10 @@ static void iwl_dump_host_monitor_block(struct iwl_trans trans, int i; IWL_ERR(trans, "Host monitor block 0x%x vector 0x%x\n", block, vec); - iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) \| vec); + iwl_trans_pcie_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) \| vec); for (i = 0; i < iter; i++) IWL_ERR(trans, " value [iter %d]: 0x%08x\n", - i, iwl_read32(trans, CSR_MONITOR_STATUS_REG)); + i, iwl_trans_pcie_read32(trans, CSR_MONITOR_STATUS_REG)); } static void iwl_pcie_dump_host_monitor(struct iwl_trans trans) @@ -56,7 +56,7 @@ static void iwl_pcie_dump_host_monitor(struct iwl_trans trans) case IWL_DEVICE_FAMILY_22000: case IWL_DEVICE_FAMILY_AX210: IWL_ERR(trans, "CSR_RESET = 0x%x\n", - iwl_read32(trans, CSR_RESET)); + iwl_trans_pcie_read32(trans, CSR_RESET)); iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON, IWL_HOST_MON_BLOCK_PEMON_VEC0, 15); iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON, @@ -79,12 +79,12 @@ int iwl_trans_pcie_sw_reset(struct iwl_trans trans, bool retake_ownership) { /* Reset entire device - do controller reset (results in SHRD_HW_RST) / if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_SW_RESET); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_SW_RESET); usleep_range(10000, 20000); } else { - iwl_set_bit(trans, CSR_RESET, - CSR_RESET_REG_FLAG_SW_RESET); + iwl_trans_set_bit(trans, CSR_RESET, + CSR_RESET_REG_FLAG_SW_RESET); usleep_range(5000, 6000); } @@ -170,16 +170,16 @@ void iwl_pcie_alloc_fw_monitor(struct iwl_trans trans, u8 max_power) static u32 iwl_trans_pcie_read_shr(struct iwl_trans trans, u32 reg) { - iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, - ((reg & 0x0000ffff) \| (2 << 28))); - return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); + iwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, + ((reg & 0x0000ffff) \| (2 << 28))); + return iwl_trans_pcie_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); } static void iwl_trans_pcie_write_shr(struct iwl_trans trans, u32 reg, u32 val) { - iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); - iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, - ((reg & 0x0000ffff) \| (3 << 28))); + iwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); + iwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, + ((reg & 0x0000ffff) \| (3 << 28))); } static void iwl_pcie_set_pwr(struct iwl_trans trans, bool vaux) @@ -188,13 +188,13 @@ static void iwl_pcie_set_pwr(struct iwl_trans trans, bool vaux) return; if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) - iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, - APMG_PS_CTRL_VAL_PWR_SRC_VAUX, - ~APMG_PS_CTRL_MSK_PWR_SRC); + iwl_trans_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, + APMG_PS_CTRL_VAL_PWR_SRC_VAUX, + ~APMG_PS_CTRL_MSK_PWR_SRC); else - iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, - APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, - ~APMG_PS_CTRL_MSK_PWR_SRC); + iwl_trans_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, + APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, + ~APMG_PS_CTRL_MSK_PWR_SRC); } /* PCI registers / @@ -211,7 +211,7 @@ void iwl_pcie_apm_config(struct iwl_trans trans) * and in newer hardware they are not officially supported at * all, so we must always set the L0S_DISABLED bit. / - iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); + iwl_trans_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); trans_pcie->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); @@ -241,31 +241,31 @@ static int iwl_pcie_apm_init(struct iwl_trans trans) /* Disable L0S exit timer (platform NMI Work/Around) / if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_8000) - iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, - CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); + iwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS, + CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); / * Disable L0s without affecting L1; * don't wait for ICH L0s (ICH bug W/A) / - iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, - CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); + iwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS, + CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); / Set FH wait threshold to maximum (HW error during stress W/A) / - iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); + iwl_trans_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); / * Enable HAP INTA (interrupt from management bus) to * wake device's PCI Express link L1a -> L0s / - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_HAP_WAKE); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_HAP_WAKE); iwl_pcie_apm_config(trans); / Configure analog phase-lock-loop before activating to D0A / if (trans->mac_cfg->base->pll_cfg) - iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); + iwl_trans_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); ret = iwl_trans_activate_nic(trans); if (ret) @@ -286,11 +286,11 @@ static int iwl_pcie_apm_init(struct iwl_trans trans) * just to discard the value. But that's the way the hardware * seems to like it. / - iwl_read_prph(trans, OSC_CLK); - iwl_read_prph(trans, OSC_CLK); - iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); - iwl_read_prph(trans, OSC_CLK); - iwl_read_prph(trans, OSC_CLK); + iwl_trans_read_prph(trans, OSC_CLK); + iwl_trans_read_prph(trans, OSC_CLK); + iwl_trans_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); + iwl_trans_read_prph(trans, OSC_CLK); + iwl_trans_read_prph(trans, OSC_CLK); } / @@ -301,17 +301,17 @@ static int iwl_pcie_apm_init(struct iwl_trans trans) bits already set by default in "CLK_CTRL_REG" after reset. / if (!trans->mac_cfg->base->apmg_not_supported) { - iwl_write_prph(trans, APMG_CLK_EN_REG, - APMG_CLK_VAL_DMA_CLK_RQT); + iwl_trans_write_prph(trans, APMG_CLK_EN_REG, + APMG_CLK_VAL_DMA_CLK_RQT); udelay(20); / Disable L1-Active / - iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, - APMG_PCIDEV_STT_VAL_L1_ACT_DIS); + iwl_trans_set_bits_prph(trans, APMG_PCIDEV_STT_REG, + APMG_PCIDEV_STT_VAL_L1_ACT_DIS); / Clear the interrupt in APMG if the NIC is in RFKILL / - iwl_write_prph(trans, APMG_RTC_INT_STT_REG, - APMG_RTC_INT_STT_RFKILL); + iwl_trans_write_prph(trans, APMG_RTC_INT_STT_REG, + APMG_RTC_INT_STT_RFKILL); } set_bit(STATUS_DEVICE_ENABLED, &trans->status); @@ -334,8 +334,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans trans) u32 dl_cfg_reg; /* Force XTAL ON / - iwl_trans_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_XTAL_ON); + iwl_pcie_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_XTAL_ON); ret = iwl_trans_pcie_sw_reset(trans, true); @@ -344,8 +344,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans trans) if (WARN_ON(ret)) { /* Release XTAL ON request / - iwl_trans_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_XTAL_ON); + iwl_pcie_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_XTAL_ON); return; } @@ -353,8 +353,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans trans) * Clear "disable persistence" to avoid LP XTAL resetting when * SHRD_HW_RST is applied in S3. / - iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, - APMG_PCIDEV_STT_VAL_PERSIST_DIS); + iwl_trans_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, + APMG_PCIDEV_STT_VAL_PERSIST_DIS); / * Force APMG XTAL to be active to prevent its disabling by HW @@ -386,22 +386,22 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans trans) Enable persistence mode to avoid LP XTAL resetting when * SHRD_HW_RST is applied in S3. / - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_PERSISTENCE); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_PERSISTENCE); / * Clear "initialization complete" bit to move adapter from * D0A* (powered-up Active) --> D0U* (Uninitialized) state. / - iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); / Activates XTAL resources monitor / - iwl_trans_set_bit(trans, CSR_MONITOR_CFG_REG, - CSR_MONITOR_XTAL_RESOURCES); + iwl_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, + CSR_MONITOR_XTAL_RESOURCES); / Release XTAL ON request / - iwl_trans_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_XTAL_ON); + iwl_pcie_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_XTAL_ON); udelay(10); / Release APMG XTAL / @@ -417,18 +417,18 @@ void iwl_pcie_apm_stop_master(struct iwl_trans trans) /* stop device's busmaster DMA activity / if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); - ret = iwl_poll_bits(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, - 100); + ret = iwl_trans_poll_bits(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, + 100); usleep_range(10000, 20000); } else { - iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); + iwl_trans_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); - ret = iwl_poll_bits(trans, CSR_RESET, - CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); + ret = iwl_trans_poll_bits(trans, CSR_RESET, + CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); } if (ret) @@ -447,18 +447,18 @@ static void iwl_pcie_apm_stop(struct iwl_trans trans, bool op_mode_leave) /* inform ME that we are leaving / if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) - iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, - APMG_PCIDEV_STT_VAL_WAKE_ME); + iwl_trans_set_bits_prph(trans, APMG_PCIDEV_STT_REG, + APMG_PCIDEV_STT_VAL_WAKE_ME); else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) { - iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, - CSR_RESET_LINK_PWR_MGMT_DISABLED); - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_WAKE_ME \| - CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN); + iwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, + CSR_RESET_LINK_PWR_MGMT_DISABLED); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_WAKE_ME \| + CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN); mdelay(1); - iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, - CSR_RESET_LINK_PWR_MGMT_DISABLED); + iwl_trans_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, + CSR_RESET_LINK_PWR_MGMT_DISABLED); } mdelay(5); } @@ -479,7 +479,7 @@ static void iwl_pcie_apm_stop(struct iwl_trans trans, bool op_mode_leave) * Clear "initialization complete" bit to move adapter from * D0A* (powered-up Active) --> D0U* (Uninitialized) state. / - iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); } static int iwl_pcie_nic_init(struct iwl_trans trans) @@ -512,7 +512,7 @@ static int iwl_pcie_nic_init(struct iwl_trans trans) if (trans->mac_cfg->base->shadow_reg_enable) { / enable shadow regs in HW / - iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); + iwl_trans_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); } @@ -525,16 +525,16 @@ static int iwl_pcie_set_hw_ready(struct iwl_trans trans) { int ret; - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_PCI_OWN_SET); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_PCI_OWN_SET); /* See if we got it / - ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_PCI_OWN_SET, - HW_READY_TIMEOUT); + ret = iwl_trans_poll_bits(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_PCI_OWN_SET, + HW_READY_TIMEOUT); if (!ret) - iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); + iwl_trans_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret ? " not" : ""); return ret; @@ -555,16 +555,16 @@ int iwl_pcie_prepare_card_hw(struct iwl_trans trans) return 0; } - iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, - CSR_RESET_LINK_PWR_MGMT_DISABLED); + iwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, + CSR_RESET_LINK_PWR_MGMT_DISABLED); usleep_range(1000, 2000); for (iter = 0; iter < 10; iter++) { int t = 0; /* If HW is not ready, prepare the conditions to check again / - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_WAKE_ME); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_WAKE_ME); do { ret = iwl_pcie_set_hw_ready(trans); @@ -603,28 +603,28 @@ static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans trans, u32 dst_addr, dma_addr_t phy_addr, u32 byte_cnt) { - iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), - FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); + iwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), + FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); - iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), - dst_addr); + iwl_trans_pcie_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), + dst_addr); - iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), - phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); + iwl_trans_pcie_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), + phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); - iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), - (iwl_get_dma_hi_addr(phy_addr) - << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) \| byte_cnt); + iwl_trans_pcie_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), + (iwl_get_dma_hi_addr(phy_addr) + << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) \| byte_cnt); - iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), - BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) \| - BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) \| - FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); + iwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), + BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) \| + BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) \| + FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); - iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), - FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \| - FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE \| - FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); + iwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), + FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \| + FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE \| + FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); } static int iwl_pcie_load_firmware_chunk(struct iwl_trans trans, @@ -688,16 +688,16 @@ static int iwl_pcie_load_section(struct iwl_trans trans, u8 section_num, extended_addr = true; if (extended_addr) - iwl_set_bits_prph(trans, LMPM_CHICK, - LMPM_CHICK_EXTENDED_ADDR_SPACE); + iwl_trans_set_bits_prph(trans, LMPM_CHICK, + LMPM_CHICK_EXTENDED_ADDR_SPACE); memcpy(v_addr, (const u8 )section->data + offset, copy_size); ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, copy_size); if (extended_addr) - iwl_clear_bits_prph(trans, LMPM_CHICK, - LMPM_CHICK_EXTENDED_ADDR_SPACE); + iwl_trans_clear_bits_prph(trans, LMPM_CHICK, + LMPM_CHICK_EXTENDED_ADDR_SPACE); if (ret) { IWL_ERR(trans, @@ -751,9 +751,9 @@ static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans trans, return ret; /* Notify ucode of loaded section number and status / - val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); + val = iwl_pcie_read_direct32(trans, FH_UCODE_LOAD_STATUS); val = val \| (sec_num << shift_param); - iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); + iwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); sec_num = (sec_num << 1) \| 0x1; } @@ -764,18 +764,18 @@ static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans trans, if (trans->mac_cfg->gen2) { if (cpu == 1) - iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, - 0xFFFF); + iwl_trans_write_prph(trans, UREG_UCODE_LOAD_STATUS, + 0xFFFF); else - iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, - 0xFFFFFFFF); + iwl_trans_write_prph(trans, UREG_UCODE_LOAD_STATUS, + 0xFFFFFFFF); } else { if (cpu == 1) - iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, - 0xFFFF); + iwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS, + 0xFFFF); else - iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, - 0xFFFFFFFF); + iwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS, + 0xFFFFFFFF); } return 0; @@ -836,8 +836,8 @@ static void iwl_pcie_apply_destination_ini(struct iwl_trans trans) IWL_FW_INI_LOCATION_SRAM_PATH) { IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); / set sram monitor by enabling bit 7 / - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); return; } @@ -852,11 +852,11 @@ static void iwl_pcie_apply_destination_ini(struct iwl_trans trans) IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", alloc_id); - iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, - frag->physical >> MON_BUFF_SHIFT_VER2); - iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, - (frag->physical + frag->size - 256) >> - MON_BUFF_SHIFT_VER2); + iwl_trans_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, + frag->physical >> MON_BUFF_SHIFT_VER2); + iwl_trans_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, + (frag->physical + frag->size - 256) >> + MON_BUFF_SHIFT_VER2); } void iwl_pcie_apply_destination(struct iwl_trans trans) @@ -884,25 +884,25 @@ void iwl_pcie_apply_destination(struct iwl_trans trans) switch (dest->reg_ops[i].op) { case CSR_ASSIGN: - iwl_write32(trans, addr, val); + iwl_trans_pcie_write32(trans, addr, val); break; case CSR_SETBIT: - iwl_set_bit(trans, addr, BIT(val)); + iwl_trans_set_bit(trans, addr, BIT(val)); break; case CSR_CLEARBIT: - iwl_clear_bit(trans, addr, BIT(val)); + iwl_trans_clear_bit(trans, addr, BIT(val)); break; case PRPH_ASSIGN: - iwl_write_prph(trans, addr, val); + iwl_trans_write_prph(trans, addr, val); break; case PRPH_SETBIT: - iwl_set_bits_prph(trans, addr, BIT(val)); + iwl_trans_set_bits_prph(trans, addr, BIT(val)); break; case PRPH_CLEARBIT: - iwl_clear_bits_prph(trans, addr, BIT(val)); + iwl_trans_clear_bits_prph(trans, addr, BIT(val)); break; case PRPH_BLOCKBIT: - if (iwl_read_prph(trans, addr) & BIT(val)) { + if (iwl_trans_read_prph(trans, addr) & BIT(val)) { IWL_ERR(trans, "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", val, addr); @@ -918,16 +918,16 @@ void iwl_pcie_apply_destination(struct iwl_trans trans) monitor: if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { - iwl_write_prph(trans, le32_to_cpu(dest->base_reg), - fw_mon->physical >> dest->base_shift); + iwl_trans_write_prph(trans, le32_to_cpu(dest->base_reg), + fw_mon->physical >> dest->base_shift); if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) - iwl_write_prph(trans, le32_to_cpu(dest->end_reg), - (fw_mon->physical + fw_mon->size - - 256) >> dest->end_shift); + iwl_trans_write_prph(trans, le32_to_cpu(dest->end_reg), + (fw_mon->physical + fw_mon->size - + 256) >> dest->end_shift); else - iwl_write_prph(trans, le32_to_cpu(dest->end_reg), - (fw_mon->physical + fw_mon->size) >> - dest->end_shift); + iwl_trans_write_prph(trans, le32_to_cpu(dest->end_reg), + (fw_mon->physical + fw_mon->size) >> + dest->end_shift); } } @@ -947,9 +947,9 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans trans, if (image->is_dual_cpus) { /* set CPU2 header address / - iwl_write_prph(trans, - LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, - LMPM_SECURE_CPU2_HDR_MEM_SPACE); + iwl_trans_write_prph(trans, + LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, + LMPM_SECURE_CPU2_HDR_MEM_SPACE); / load to FW the binary sections of CPU2 / ret = iwl_pcie_load_cpu_sections(trans, image, 2, @@ -964,7 +964,7 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans trans, iwl_enable_interrupts(trans); /* release CPU reset / - iwl_write32(trans, CSR_RESET, 0); + iwl_trans_pcie_write32(trans, CSR_RESET, 0); return 0; } @@ -982,18 +982,18 @@ static int iwl_pcie_load_given_ucode_8000(struct iwl_trans trans, iwl_pcie_apply_destination(trans); IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", - iwl_read_prph(trans, WFPM_GP2)); + iwl_trans_read_prph(trans, WFPM_GP2)); /* * Set default value. On resume reading the values that were * zeored can provide debug data on the resume flow. * This is for debugging only and has no functional impact. / - iwl_write_prph(trans, WFPM_GP2, 0x01010101); + iwl_trans_write_prph(trans, WFPM_GP2, 0x01010101); / configure the ucode to be ready to get the secured image / / release CPU reset / - iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); + iwl_trans_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); / load to FW the binary Secured sections of CPU1 / ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, @@ -1079,9 +1079,9 @@ static void iwl_pcie_map_list(struct iwl_trans trans, int i; for (i = 0; i < arr_size; i++) { - iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); - iwl_clear_bit(trans, causes[i].mask_reg, - BIT(causes[i].bit)); + iwl_trans_pcie_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); + iwl_trans_clear_bit(trans, causes[i].mask_reg, + BIT(causes[i].bit)); } } @@ -1119,19 +1119,19 @@ static void iwl_pcie_map_rx_causes(struct iwl_trans trans) / val = BIT(MSIX_FH_INT_CAUSES_Q(0)); for (idx = 1; idx < trans->info.num_rxqs; idx++) { - iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), - MSIX_FH_INT_CAUSES_Q(idx - offset)); + iwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(idx), + MSIX_FH_INT_CAUSES_Q(idx - offset)); val \|= BIT(MSIX_FH_INT_CAUSES_Q(idx)); } - iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); + iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); val = MSIX_FH_INT_CAUSES_Q(0); if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) val \|= MSIX_NON_AUTO_CLEAR_CAUSE; - iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); + iwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(0), val); if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) - iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); + iwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(1), val); } void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie trans_pcie) @@ -1141,8 +1141,8 @@ void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie trans_pcie) if (!trans_pcie->msix_enabled) { if (trans->mac_cfg->mq_rx_supported && test_bit(STATUS_DEVICE_ENABLED, &trans->status)) - iwl_write_umac_prph(trans, UREG_CHICK, - UREG_CHICK_MSI_ENABLE); + iwl_trans_write_umac_prph(trans, UREG_CHICK, + UREG_CHICK_MSI_ENABLE); return; } /* @@ -1151,7 +1151,7 @@ void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie trans_pcie) prph. / if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) - iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); + iwl_trans_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); / * Each cause from the causes list above and the RX causes is @@ -1174,9 +1174,9 @@ static void iwl_pcie_init_msix(struct iwl_trans_pcie trans_pcie) if (!trans_pcie->msix_enabled) return; - trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); + trans_pcie->fh_init_mask = ~iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_MASK_AD); trans_pcie->fh_mask = trans_pcie->fh_init_mask; - trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); + trans_pcie->hw_init_mask = ~iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_MASK_AD); trans_pcie->hw_mask = trans_pcie->hw_init_mask; } @@ -1215,19 +1215,19 @@ static void _iwl_trans_pcie_stop_device(struct iwl_trans trans, bool from_irq) /* Power-down device's busmaster DMA clocks / if (!trans->mac_cfg->base->apmg_not_supported) { - iwl_write_prph(trans, APMG_CLK_DIS_REG, - APMG_CLK_VAL_DMA_CLK_RQT); + iwl_trans_write_prph(trans, APMG_CLK_DIS_REG, + APMG_CLK_VAL_DMA_CLK_RQT); udelay(5); } } / Make sure (redundant) we've released our request to stay awake / if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); else - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); / Stop the device, and put it in low power state / iwl_pcie_apm_stop(trans, false); @@ -1288,6 +1288,10 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans, bool hw_rfkill; int ret; + if (trans->mac_cfg->gen2) + return iwl_trans_pcie_gen2_start_fw(trans, fw, img, + run_in_rfkill); + /* This may fail if AMT took ownership of the device / if (iwl_pcie_prepare_card_hw(trans)) { IWL_WARN(trans, "Exit HW not ready\n"); @@ -1296,7 +1300,7 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans, iwl_enable_rfkill_int(trans); - iwl_write32(trans, CSR_INT, 0xFFFFFFFF); + iwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF); /* * We enabled the RF-Kill interrupt and the handler may very @@ -1326,12 +1330,12 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans, } / make sure rfkill handshake bits are cleared / - iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); - iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, - CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); + iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); + iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, + CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); / clear (again), then enable host interrupts / - iwl_write32(trans, CSR_INT, 0xFFFFFFFF); + iwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF); ret = iwl_pcie_nic_init(trans); if (ret) { @@ -1349,8 +1353,8 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans, iwl_enable_fw_load_int(trans); /* really make sure rfkill handshake bits are cleared / - iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); - iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); + iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); + iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); / Load the given image to the HW / if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) @@ -1370,6 +1374,11 @@ int iwl_trans_pcie_start_fw(struct iwl_trans trans, void iwl_trans_pcie_fw_alive(struct iwl_trans trans) { + if (trans->mac_cfg->gen2) { + iwl_trans_pcie_gen2_fw_alive(trans); + return; + } + iwl_pcie_reset_ict(trans); iwl_pcie_tx_start(trans); } @@ -1408,6 +1417,11 @@ void iwl_trans_pcie_stop_device(struct iwl_trans trans) struct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); bool was_in_rfkill; + if (trans->mac_cfg->gen2) { + iwl_trans_pcie_gen2_stop_device(trans); + return; + } + iwl_op_mode_time_point(trans->op_mode, IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, NULL); @@ -1444,15 +1458,15 @@ static void iwl_pcie_d3_complete_suspend(struct iwl_trans trans, iwl_pcie_synchronize_irqs(trans); if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_INIT); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_INIT); } else { - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_INIT_DONE); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_INIT_DONE); } if (reset) { @@ -1478,13 +1492,13 @@ static int iwl_pcie_d3_handshake(struct iwl_trans trans, bool suspend) trans_pcie->sx_state = IWL_SX_WAITING; if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) - iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, - suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : - UREG_DOORBELL_TO_ISR6_RESUME); + iwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, + suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : + UREG_DOORBELL_TO_ISR6_RESUME); else - iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, - suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : - CSR_IPC_SLEEP_CONTROL_RESUME); + iwl_trans_pcie_write32(trans, CSR_IPC_SLEEP_CONTROL, + suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : + CSR_IPC_SLEEP_CONTROL_RESUME); ret = wait_event_timeout(trans_pcie->sx_waitq, trans_pcie->sx_state != IWL_SX_WAITING, @@ -1515,8 +1529,8 @@ int iwl_trans_pcie_d3_suspend(struct iwl_trans trans, bool reset) if (!reset) /* Enable persistence mode to avoid reset / - iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, - CSR_HW_IF_CONFIG_REG_PERSISTENCE); + iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG, + CSR_HW_IF_CONFIG_REG_PERSISTENCE); ret = iwl_pcie_d3_handshake(trans, true); if (ret) @@ -1535,11 +1549,11 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans trans, int ret; if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); else - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); ret = iwl_trans_activate_nic(trans); if (ret) { @@ -1563,8 +1577,8 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans trans, iwl_pcie_set_pwr(trans, false); if (!reset) { - iwl_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + iwl_trans_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); } else { iwl_trans_pcie_tx_reset(trans); @@ -1577,9 +1591,9 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans trans, } IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", - iwl_read_umac_prph(trans, WFPM_GP2)); + iwl_trans_read_umac_prph(trans, WFPM_GP2)); - val = iwl_read32(trans, CSR_RESET); + val = iwl_trans_pcie_read32(trans, CSR_RESET); if (val & CSR_RESET_REG_FLAG_NEVO_RESET) { IWL_INFO(trans, "Device was reset during suspend\n"); trans->state = IWL_TRANS_NO_FW; @@ -1745,17 +1759,17 @@ static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans trans) return 0; } - hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); + hpm = iwl_trans_read_umac_prph_no_grab(trans, HPM_DEBUG); if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) { - u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); + u32 wprot_val = iwl_trans_read_umac_prph_no_grab(trans, wprot); if (wprot_val & PREG_WFPM_ACCESS) { IWL_ERR(trans, "Error, can not clear persistence bit\n"); return -EPERM; } - iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, - hpm & ~PERSISTENCE_BIT); + iwl_pcie_write_umac_prph_no_grab(trans, HPM_DEBUG, + hpm & ~PERSISTENCE_BIT); } return 0; @@ -1769,15 +1783,15 @@ static int iwl_pcie_gen2_force_power_gating(struct iwl_trans trans) if (ret < 0) return ret; - iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, - HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); + iwl_trans_set_bits_prph(trans, HPM_HIPM_GEN_CFG, + HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); udelay(20); - iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, - HPM_HIPM_GEN_CFG_CR_PG_EN \| - HPM_HIPM_GEN_CFG_CR_SLP_EN); + iwl_trans_set_bits_prph(trans, HPM_HIPM_GEN_CFG, + HPM_HIPM_GEN_CFG_CR_PG_EN \| + HPM_HIPM_GEN_CFG_CR_SLP_EN); udelay(20); - iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, - HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); + iwl_trans_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, + HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); return iwl_trans_pcie_sw_reset(trans, true); } @@ -1846,6 +1860,11 @@ void iwl_trans_pcie_op_mode_leave(struct iwl_trans trans) { struct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); + if (trans->mac_cfg->gen2) { + iwl_trans_pcie_gen2_op_mode_leave(trans); + return; + } + mutex_lock(&trans_pcie->mutex); /* disable interrupts - don't enable HW RF kill interrupt / @@ -1864,17 +1883,22 @@ void iwl_trans_pcie_op_mode_leave(struct iwl_trans trans) void iwl_trans_pcie_write8(struct iwl_trans trans, u32 ofs, u8 val) { + trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val); writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); } void iwl_trans_pcie_write32(struct iwl_trans trans, u32 ofs, u32 val) { + trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val); writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); } u32 iwl_trans_pcie_read32(struct iwl_trans trans, u32 ofs) { - return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); + u32 val = readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); + + trace_iwlwifi_dev_ioread32(trans->dev, ofs, val); + return val; } static u32 iwl_trans_pcie_prph_msk(struct iwl_trans trans) @@ -1888,16 +1912,20 @@ static u32 iwl_trans_pcie_prph_msk(struct iwl_trans trans) u32 iwl_trans_pcie_read_prph(struct iwl_trans trans, u32 reg) { u32 mask = iwl_trans_pcie_prph_msk(trans); + u32 val; iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, ((reg & mask) \| (3 << 24))); - return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); + val = iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); + trace_iwlwifi_dev_ioread_prph32(trans->dev, reg, val); + return val; } -void iwl_trans_pcie_write_prph(struct iwl_trans trans, u32 addr, u32 val) +void iwl_pcie_write_prph_no_grab(struct iwl_trans trans, u32 addr, u32 val) { u32 mask = iwl_trans_pcie_prph_msk(trans); + trace_iwlwifi_dev_iowrite_prph32(trans->dev, addr, val); iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, ((addr & mask) \| (3 << 24))); iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); @@ -2265,7 +2293,7 @@ static void iwl_trans_pcie_removal_wk(struct work_struct wk) module_put(THIS_MODULE); } -void iwl_trans_pcie_reset(struct iwl_trans trans, enum iwl_reset_mode mode) +static void iwl_trans_pcie_reset(struct iwl_trans trans, enum iwl_reset_mode mode) { struct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); struct iwl_trans_pcie_removal removal; @@ -2320,7 +2348,6 @@ void iwl_trans_pcie_reset(struct iwl_trans trans, enum iwl_reset_mode mode) pci_dev_get(removal->pdev); schedule_work(&removal->work); } -EXPORT_SYMBOL(iwl_trans_pcie_reset); /* * This version doesn't disable BHs but rather assumes they're @@ -2350,7 +2377,7 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans trans, bool silent) } / this bit wakes up the NIC / - iwl_trans_set_bit(trans, CSR_GP_CNTRL, write); + iwl_pcie_set_bit(trans, CSR_GP_CNTRL, write); if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) udelay(2); @@ -2374,9 +2401,9 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans trans, bool silent) * 5000 series and later (including 1000 series) have non-volatile SRAM, * and do not save/restore SRAM when power cycling. / - ret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000); + ret = iwl_trans_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000); if (unlikely(ret)) { - u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); + u32 cntrl = iwl_trans_pcie_read32(trans, CSR_GP_CNTRL); if (silent) { spin_unlock(&trans_pcie->reg_lock); @@ -2393,8 +2420,8 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans trans, bool silent) iwl_trans_pcie_reset(trans, IWL_RESET_MODE_REMOVE_ONLY); else - iwl_write32(trans, CSR_RESET, - CSR_RESET_REG_FLAG_FORCE_NMI); + iwl_trans_pcie_write32(trans, CSR_RESET, + CSR_RESET_REG_FLAG_FORCE_NMI); spin_unlock(&trans_pcie->reg_lock); return false; @@ -2443,11 +2470,11 @@ void iwl_trans_pcie_release_nic_access(struct iwl_trans trans) if (trans_pcie->cmd_hold_nic_awake) goto out; if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) - iwl_trans_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); + iwl_pcie_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); else - iwl_trans_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + iwl_pcie_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); / * Above we read the CSR_GP_CNTRL register, which will flush * any previous writes, but we need the write that clears the @@ -2472,12 +2499,12 @@ int iwl_trans_pcie_read_mem(struct iwl_trans trans, u32 addr, bool resched = false; if (iwl_trans_grab_nic_access(trans)) { - iwl_write32(trans, HBUS_TARG_MEM_RADDR, - addr + 4 offs); + iwl_trans_pcie_write32(trans, HBUS_TARG_MEM_RADDR, + addr + 4 * offs); while (offs < dwords) { - vals[offs] = iwl_read32(trans, - HBUS_TARG_MEM_RDAT); + vals[offs] = iwl_trans_pcie_read32(trans, + HBUS_TARG_MEM_RDAT); if (iwl_trans_is_hw_error_value(vals[offs])) num_consec_hw_errors++; @@ -2524,11 +2551,11 @@ int iwl_trans_pcie_read_mem_no_grab(struct iwl_trans trans, u32 addr, unsigned long end = jiffies + HZ / 2; bool resched = false; - iwl_write32(trans, HBUS_TARG_MEM_RADDR, - addr + 4 offs); + iwl_trans_pcie_write32(trans, HBUS_TARG_MEM_RADDR, + addr + 4 * offs); while (offs < dwords) { - vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); + vals[offs] = iwl_trans_pcie_read32(trans, HBUS_TARG_MEM_RDAT); if (iwl_trans_is_hw_error_value(vals[offs])) num_consec_hw_errors++; @@ -2672,7 +2699,7 @@ void iwl_trans_pcie_set_bits_mask(struct iwl_trans trans, u32 reg, struct iwl_trans_pcie trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); spin_lock_bh(&trans_pcie->reg_lock); - _iwl_trans_set_bits_mask(trans, reg, mask, value); + iwl_pcie_set_bits_mask(trans, reg, mask, value); spin_unlock_bh(&trans_pcie->reg_lock); } @@ -2745,7 +2772,7 @@ void iwl_pcie_dump_csr(struct iwl_trans trans) for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { IWL_ERR(trans, " %25s: 0X%08x\n", get_csr_string(csr_tbl[i]), - iwl_read32(trans, csr_tbl[i])); + iwl_trans_pcie_read32(trans, csr_tbl[i])); } } @@ -3021,7 +3048,7 @@ static ssize_t iwl_dbgfs_rfkill_read(struct file file, pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", trans_pcie->debug_rfkill, - !(iwl_read32(trans, CSR_GP_CNTRL) & + !(iwl_trans_pcie_read32(trans, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); return simple_read_from_buffer(user_buf, count, ppos, buf, pos); @@ -3228,8 +3255,8 @@ static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans trans, i += sizeof(u32)) val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); else - for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); - i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); + for (i = iwl_trans_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); + i < iwl_trans_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); i += sizeof(u32)) val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, i)); @@ -3253,11 +3280,11 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans trans, if (!iwl_trans_grab_nic_access(trans)) return 0; - iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); + iwl_pcie_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); for (i = 0; i < buf_size_in_dwords; i++) - buffer[i] = iwl_read_umac_prph_no_grab(trans, - MON_DMARB_RD_DATA_ADDR); - iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); + buffer[i] = iwl_trans_read_umac_prph_no_grab(trans, + MON_DMARB_RD_DATA_ADDR); + iwl_pcie_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); iwl_trans_release_nic_access(trans); @@ -3285,14 +3312,14 @@ iwl_trans_pcie_dump_pointers(struct iwl_trans trans, wrap_cnt = MON_BUFF_CYCLE_CNT; } - write_ptr_val = iwl_read_prph(trans, write_ptr); + write_ptr_val = iwl_trans_read_prph(trans, write_ptr); fw_mon_data->fw_mon_cycle_cnt = - cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); + cpu_to_le32(iwl_trans_read_prph(trans, wrap_cnt)); fw_mon_data->fw_mon_base_ptr = - cpu_to_le32(iwl_read_prph(trans, base)); + cpu_to_le32(iwl_trans_read_prph(trans, base)); if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { fw_mon_data->fw_mon_base_high_ptr = - cpu_to_le32(iwl_read_prph(trans, base_high)); + cpu_to_le32(iwl_trans_read_prph(trans, base_high)); write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; / convert wrtPtr to DWs, to align with all HWs / write_ptr_val >>= 2; @@ -3330,13 +3357,13 @@ iwl_trans_pcie_dump_monitor(struct iwl_trans trans, * shifting / if (trans->dbg.dest_tlv->version) { - base = (iwl_read_prph(trans, base) & + base = (iwl_trans_read_prph(trans, base) & IWL_LDBG_M2S_BUF_BA_MSK) << trans->dbg.dest_tlv->base_shift; base = IWL_M2S_UNIT_SIZE; base += trans->mac_cfg->base->smem_offset; } else { - base = iwl_read_prph(trans, base) << + base = iwl_trans_read_prph(trans, base) << trans->dbg.dest_tlv->base_shift; } @@ -3371,7 +3398,7 @@ static int iwl_trans_get_fw_monitor_len(struct iwl_trans trans, u32 len) if (trans->dbg.dest_tlv->version == 1) { cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); - cfg_reg = iwl_read_prph(trans, cfg_reg); + cfg_reg = iwl_trans_read_prph(trans, cfg_reg); base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << trans->dbg.dest_tlv->base_shift; base = IWL_M2S_UNIT_SIZE; @@ -3385,9 +3412,9 @@ static int iwl_trans_get_fw_monitor_len(struct iwl_trans trans, u32 len) base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); - base = iwl_read_prph(trans, base) << + base = iwl_trans_read_prph(trans, base) << trans->dbg.dest_tlv->base_shift; - end = iwl_read_prph(trans, end) << + end = iwl_trans_read_prph(trans, end) << trans->dbg.dest_tlv->end_shift; / Make "end" point to the actual end / @@ -3445,8 +3472,8 @@ iwl_trans_pcie_dump_data(struct iwl_trans trans, u32 dump_mask, if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { if (trans->mac_cfg->gen2) len += sizeof(data) + - (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - - iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); + (iwl_trans_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - + iwl_trans_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); else len += sizeof(data) + (FH_MEM_UPPER_BOUND - @@ -3592,12 +3619,12 @@ void iwl_trans_pcie_sync_nmi(struct iwl_trans trans) iwl_trans_force_nmi(trans); while (time_after(timeout, jiffies)) { - u32 inta_hw = iwl_read32(trans, inta_addr); + u32 inta_hw = iwl_trans_pcie_read32(trans, inta_addr); / Error detected by uCode / if (inta_hw & sw_err_bit) { / Clear causes register / - iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); + iwl_trans_pcie_write32(trans, inta_addr, inta_hw & sw_err_bit); break; } @@ -3651,6 +3678,66 @@ static int iwl_trans_pcie_alloc_txcmd_pool(struct iwl_trans trans) return 0; } +const struct iwl_trans_ops iwl_trans_pcie_ops = { + .op_mode_enter = iwl_trans_pcie_op_mode_enter, + .start_hw = iwl_trans_pcie_start_hw, + .op_mode_leave = iwl_trans_pcie_op_mode_leave, + + .send_cmd = iwl_trans_pcie_send_hcmd, + .alloc_tx_cmd = iwl_pcie_alloc_tx_cmd, + .free_tx_cmd = iwl_pcie_free_tx_cmd, + + .write8 = iwl_trans_pcie_write8, + .write32 = iwl_trans_pcie_write32, + .read32 = iwl_trans_pcie_read32, + .read_prph = iwl_trans_pcie_read_prph, + .write_prph = iwl_pcie_write_prph_no_grab, + .read_mem = iwl_trans_pcie_read_mem, + .read_mem_no_grab = iwl_trans_pcie_read_mem_no_grab, + .set_bits_mask = iwl_trans_pcie_set_bits_mask, + .read_config32 = iwl_trans_pcie_read_config32, + .grab_nic_access = iwl_trans_pcie_grab_nic_access, + .release_nic_access = iwl_trans_pcie_release_nic_access, + .resched_with_nic_access = iwl_trans_pcie_resched_with_nic_access, + + .sw_reset = iwl_trans_pcie_sw_reset, + .reset = iwl_trans_pcie_reset, + .fw_reset_handshake = iwl_trans_pcie_fw_reset_handshake, + + .dump_data = iwl_trans_pcie_dump_data, + .d3_suspend = iwl_trans_pcie_d3_suspend, + .d3_resume = iwl_trans_pcie_d3_resume, + + .sync_nmi = iwl_trans_pcie_sync_nmi, + .write_imr_mem = iwl_trans_pcie_copy_imr, + + .fw_alive = iwl_trans_pcie_fw_alive, + .start_fw = iwl_trans_pcie_start_fw, + .stop_device = iwl_trans_pcie_stop_device, + + .tx = iwl_trans_pcie_tx, + .reclaim = iwl_pcie_reclaim, + .txq_disable = iwl_trans_pcie_txq_disable, + .txq_enable = iwl_trans_pcie_txq_enable, + .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, + .wait_txqs_empty = iwl_trans_pcie_wait_txqs_empty, + .freeze_txq_timer = iwl_pcie_freeze_txq_timer, + .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, + .set_q_ptrs = iwl_pcie_set_q_ptrs, + .txq_alloc = iwl_txq_dyn_alloc, + .txq_free = iwl_txq_dyn_free, + .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, + + .load_pnvm = iwl_trans_pcie_ctx_info_v2_load_pnvm, + .set_pnvm = iwl_trans_pcie_ctx_info_v2_set_pnvm, + .load_reduce_power = iwl_trans_pcie_ctx_info_v2_load_reduce_power, + .set_reduce_power = iwl_trans_pcie_ctx_info_v2_set_reduce_power, + + .is_pm_supported = iwl_pcie_gen1_is_pm_supported, + .is_ltr_enabled = iwl_pcie_is_ltr_enabled, + .activate_nic = iwl_pcie_activate_nic, +}; + static struct iwl_trans * iwl_trans_pcie_alloc(struct pci_dev pdev, const struct iwl_mac_cfg mac_cfg, @@ -3662,7 +3749,7 @@ iwl_trans_pcie_alloc(struct pci_dev pdev, int ret, addr_size; trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, - mac_cfg); + &iwl_trans_pcie_ops, mac_cfg); if (!trans) return ERR_PTR(-ENOMEM); @@ -3851,19 +3938,19 @@ iwl_trans_pcie_alloc(struct pci_dev pdev, void iwl_trans_pcie_copy_imr_fh(struct iwl_trans trans, u32 dst_addr, u64 src_addr, u32 byte_cnt) { - iwl_write_prph(trans, IMR_UREG_CHICK, - iwl_read_prph(trans, IMR_UREG_CHICK) \| - IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); - iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); - iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, - (u32)(src_addr & 0xFFFFFFFF)); - iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, - iwl_get_dma_hi_addr(src_addr)); - iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); - iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, - IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS \| - IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS \| - IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); + iwl_trans_write_prph(trans, IMR_UREG_CHICK, + iwl_trans_read_prph(trans, IMR_UREG_CHICK) \| + IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); + iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); + iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, + (u32)(src_addr & 0xFFFFFFFF)); + iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, + iwl_get_dma_hi_addr(src_addr)); + iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); + iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, + IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS \| + IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS \| + IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); } int iwl_trans_pcie_copy_imr(struct iwl_trans trans, @@ -3905,8 +3992,8 @@ static void get_crf_id(struct iwl_trans iwl_trans, / wait until the device is ready to access the prph registers / if (iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_DR \|\| iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_SC) { - u32 req = iwl_read_umac_prph_no_grab(iwl_trans, - WFPM_RSRCS_4PHS_REQ_STTS); + u32 req = iwl_trans_read_umac_prph_no_grab(iwl_trans, + WFPM_RSRCS_4PHS_REQ_STTS); int ret; if (!(req & RSRC_REQ_CNVR_TOP)) { @@ -3916,26 +4003,26 @@ static void get_crf_id(struct iwl_trans iwl_trans, return; } - ret = iwl_poll_umac_prph_bits_no_grab(iwl_trans, - WFPM_RSRCS_4PHS_ACK_STTS, - RSRC_ACK_CNVR_TOP, - RSRC_ACK_CNVR_TOP, - 50 * 1000); + ret = iwl_pcie_poll_umac_prph_bits_no_grab(iwl_trans, + WFPM_RSRCS_4PHS_ACK_STTS, + RSRC_ACK_CNVR_TOP, + RSRC_ACK_CNVR_TOP, + 50 * 1000); if (ret < 0) IWL_ERR(iwl_trans, "WFPM_RSRCS_4PHS_ACK_STTS bit 6 is clear\n"); } /* Enable access to peripheral registers / - val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG); + val = iwl_trans_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG); val \|= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK; - iwl_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val); + iwl_pcie_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val); / Read crf info / - info->hw_crf_id = iwl_read_prph_no_grab(iwl_trans, sd_reg_ver_addr); + info->hw_crf_id = iwl_trans_pcie_read_prph(iwl_trans, sd_reg_ver_addr); / Read cnv info / - info->hw_cnv_id = iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP); + info->hw_cnv_id = iwl_trans_pcie_read_prph(iwl_trans, CNVI_AUX_MISC_CHIP); / For BZ-W, take B step also when A step is indicated / if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W) @@ -3959,7 +4046,7 @@ static void get_crf_id(struct iwl_trans iwl_trans, } /* Read cdb info (also contains the jacket info if needed in the future / - hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR); + hw_wfpm_id = iwl_trans_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR); IWL_INFO(iwl_trans, "Detected crf-id 0x%x, cnv-id 0x%x wfpm id 0x%x\n", info->hw_crf_id, info->hw_cnv_id, hw_wfpm_id); @@ -3976,8 +4063,8 @@ static int map_crf_id(struct iwl_trans iwl_trans, u32 val = info->hw_crf_id; u32 step_id = REG_CRF_ID_STEP(val); u32 slave_id = REG_CRF_ID_SLAVE(val); - u32 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, - WFPM_OTP_CFG1_ADDR); + u32 hw_wfpm_id = iwl_trans_read_umac_prph_no_grab(iwl_trans, + WFPM_OTP_CFG1_ADDR); u32 cdb_id_wfpm = WFPM_OTP_CFG1_IS_CDB(hw_wfpm_id); /* Map between crf id to rf id / @@ -4043,7 +4130,7 @@ static void iwl_pcie_recheck_me_status(struct work_struct wk) me_recheck_wk.work); u32 val; - val = iwl_read32(trans_pcie->trans, CSR_HW_IF_CONFIG_REG); + val = iwl_trans_pcie_read32(trans_pcie->trans, CSR_HW_IF_CONFIG_REG); trans_pcie->me_present = !!(val & CSR_HW_IF_CONFIG_REG_IAMT_UP); } @@ -4061,14 +4148,14 @@ static void iwl_pcie_check_me_status(struct iwl_trans trans) if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ) return; - val = iwl_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1); + val = iwl_trans_pcie_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1); if (val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_KNOWN) { trans_pcie->me_present = !!(val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_PRESENT); return; } - val = iwl_read32(trans, CSR_HW_IF_CONFIG_REG); + val = iwl_trans_pcie_read32(trans, CSR_HW_IF_CONFIG_REG); if (val & (CSR_HW_IF_CONFIG_REG_ME_OWN \| CSR_HW_IF_CONFIG_REG_IAMT_UP)) { trans_pcie->me_present = 1; @@ -4126,7 +4213,7 @@ int _iwl_pci_probe(struct pci_dev pdev, const struct pci_device_id ent, } } - info.hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID); + info.hw_rf_id = iwl_trans_pcie_read32(iwl_trans, CSR_HW_RF_ID); / * The RF_ID is set to zero in blank OTP so read version to @@ -4247,13 +4334,13 @@ int iwl_pcie_activate_nic(struct iwl_trans trans) D0U* --> D0A* (powered-up active) state. / if (mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ \| - CSR_GP_CNTRL_REG_FLAG_MAC_INIT); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ \| + CSR_GP_CNTRL_REG_FLAG_MAC_INIT); poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; } else { - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_INIT_DONE); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_INIT_DONE); poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY; } @@ -4262,10 +4349,10 @@ int iwl_pcie_activate_nic(struct iwl_trans trans) /* * Wait for clock stabilization; once stabilized, access to - * device-internal resources is supported, e.g. iwl_write_prph() + * device-internal resources is supported, e.g. iwl_trans_write_prph() * and accesses to uCode SRAM. / - err = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000); + err = iwl_trans_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000); if (err < 0) { IWL_DEBUG_INFO(trans, "Failed to wake NIC\n"); diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c index 27f4973791d00..e6bebd37417f7 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / * Copyright (C) 2017 Intel Deutschland GmbH - * Copyright (C) 2018-2020, 2023-2025 Intel Corporation + * Copyright (C) 2018-2020, 2023-2026 Intel Corporation / #include <net/tso.h> #include <linux/tcp.h> #include "iwl-debug.h" #include "iwl-csr.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "internal.h" #include "fw/api/tx.h" #include "fw/api/commands.h" @@ -711,7 +711,7 @@ static void iwl_txq_inc_wr_ptr(struct iwl_trans trans, struct iwl_txq txq) if not in power-save mode, uCode will never sleep when we're * trying to tx (during RFKILL, we're not trying to tx). / - iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr \| (txq->id << 16)); + iwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr \| (txq->id << 16)); } int iwl_txq_gen2_tx(struct iwl_trans trans, struct sk_buff skb, diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c index 496435ea93ee8..0c29fb6b9ca71 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c @@ -20,7 +20,7 @@ #include "iwl-debug.h" #include "iwl-csr.h" #include "iwl-prph.h" -#include "iwl-io.h" +#include "iwl-trans.h" #include "iwl-scd.h" #include "iwl-op-mode.h" #include "internal.h" @@ -99,13 +99,13 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans trans, * uCode will wake up, and interrupt us again, so next * time we'll skip this part. / - reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); + reg = iwl_trans_pcie_read32(trans, CSR_UCODE_DRV_GP1); if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", txq_id, reg); - iwl_set_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + iwl_trans_set_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); txq->need_update = true; return; } @@ -117,8 +117,8 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans trans, / IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); if (!txq->block) - iwl_write32(trans, HBUS_TARG_WRPTR, - txq->write_ptr \| (txq_id << 8)); + iwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, + txq->write_ptr \| (txq_id << 8)); } void iwl_pcie_txq_check_wrptrs(struct iwl_trans trans) @@ -205,8 +205,8 @@ static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans trans) } trans_pcie->cmd_hold_nic_awake = false; - iwl_trans_clear_bit(trans, CSR_GP_CNTRL, - CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + iwl_pcie_clear_bit(trans, CSR_GP_CNTRL, + CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); spin_unlock(&trans_pcie->reg_lock); } @@ -493,21 +493,21 @@ void iwl_pcie_tx_start(struct iwl_trans trans) sizeof(trans_pcie->txqs.queue_used)); trans_pcie->scd_base_addr = - iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); + iwl_trans_read_prph(trans, SCD_SRAM_BASE_ADDR); /* reset context data, TX status and translation data / iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND, NULL, clear_dwords); - iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, - trans_pcie->txqs.scd_bc_tbls.dma >> 10); + iwl_trans_write_prph(trans, SCD_DRAM_BASE_ADDR, + trans_pcie->txqs.scd_bc_tbls.dma >> 10); / The chain extension of the SCD doesn't work well. This feature is * enabled by default by the HW, so we need to disable it manually. / if (trans->mac_cfg->base->scd_chain_ext_wa) - iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); + iwl_trans_write_prph(trans, SCD_CHAINEXT_EN, 0); iwl_trans_ac_txq_enable(trans, trans->conf.cmd_queue, trans->conf.cmd_fifo, @@ -518,19 +518,19 @@ void iwl_pcie_tx_start(struct iwl_trans trans) /* Enable DMA channel / for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) - iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), - FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \| - FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); + iwl_trans_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), + FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \| + FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); / Update FH chicken bits / - reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); - iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, - reg_val \| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); + reg_val = iwl_pcie_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); + iwl_trans_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, + reg_val \| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); / Enable L1-Active / if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_8000) - iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, - APMG_PCIDEV_STT_VAL_L1_ACT_DIS); + iwl_trans_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, + APMG_PCIDEV_STT_VAL_L1_ACT_DIS); } void iwl_trans_pcie_tx_reset(struct iwl_trans trans) @@ -549,21 +549,21 @@ void iwl_trans_pcie_tx_reset(struct iwl_trans trans) txq_id++) { struct iwl_txq txq = trans_pcie->txqs.txq[txq_id]; if (trans->mac_cfg->gen2) - iwl_write_direct64(trans, - FH_MEM_CBBC_QUEUE(trans, txq_id), - txq->dma_addr); + iwl_pcie_write_direct64(trans, + FH_MEM_CBBC_QUEUE(trans, txq_id), + txq->dma_addr); else - iwl_write_direct32(trans, - FH_MEM_CBBC_QUEUE(trans, txq_id), - txq->dma_addr >> 8); + iwl_trans_write_direct32(trans, + FH_MEM_CBBC_QUEUE(trans, txq_id), + txq->dma_addr >> 8); iwl_pcie_txq_unmap(trans, txq_id); txq->read_ptr = 0; txq->write_ptr = 0; } /* Tell NIC where to find the "keep warm" buffer / - iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, - trans_pcie->kw.dma >> 4); + iwl_trans_write_direct32(trans, FH_KW_MEM_ADDR_REG, + trans_pcie->kw.dma >> 4); / * Send 0 as the scd_base_addr since the device may have be reset @@ -586,16 +586,16 @@ static void iwl_pcie_tx_stop_fh(struct iwl_trans trans) / Stop each Tx DMA channel / for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { - iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); + iwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); mask \|= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); } / Wait for DMA channels to be idle / - ret = iwl_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000); + ret = iwl_trans_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000); if (ret) IWL_ERR(trans, "Failing on timeout while stopping DMA channel %d [0x%08x]\n", - ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); + ch, iwl_trans_pcie_read32(trans, FH_TSSR_TX_STATUS_REG)); iwl_trans_release_nic_access(trans); @@ -684,7 +684,7 @@ void iwl_txq_log_scd_error(struct iwl_trans trans, struct iwl_txq txq) return; } - status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); + status = iwl_trans_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); @@ -693,11 +693,11 @@ void iwl_txq_log_scd_error(struct iwl_trans trans, struct iwl_txq txq) txq_id, active ? "" : "in", fifo, jiffies_to_msecs(txq->wd_timeout), txq->read_ptr, txq->write_ptr, - iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & + iwl_trans_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & (trans->mac_cfg->base->max_tfd_queue_size - 1), - iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & + iwl_trans_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & (trans->mac_cfg->base->max_tfd_queue_size - 1), - iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); + iwl_pcie_read_direct32(trans, FH_TX_TRB_REG(fifo))); } static void iwl_txq_stuck_timer(struct timer_list t) @@ -955,8 +955,8 @@ int iwl_pcie_tx_init(struct iwl_trans trans) iwl_scd_deactivate_fifos(trans); / Tell NIC where to find the "keep warm" buffer / - iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, - trans_pcie->kw.dma >> 4); + iwl_trans_write_direct32(trans, FH_KW_MEM_ADDR_REG, + trans_pcie->kw.dma >> 4); spin_unlock_bh(&trans_pcie->irq_lock); @@ -984,14 +984,14 @@ int iwl_pcie_tx_init(struct iwl_trans trans) * queue. * Circular buffer (TFD queue in DRAM) physical base address / - iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), - trans_pcie->txqs.txq[txq_id]->dma_addr >> 8); + iwl_trans_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), + trans_pcie->txqs.txq[txq_id]->dma_addr >> 8); } - iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); + iwl_trans_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); if (trans->mac_cfg->base->num_of_queues > 20) - iwl_set_bits_prph(trans, SCD_GP_CTRL, - SCD_GP_CTRL_ENABLE_31_QUEUES); + iwl_trans_set_bits_prph(trans, SCD_GP_CTRL, + SCD_GP_CTRL_ENABLE_31_QUEUES); return 0; error: @@ -1222,13 +1222,13 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans trans, int txq_id, u16 ssn, * Assumes that ssn_idx is valid (!= 0xFFF) / txq->read_ptr = (ssn & 0xff); txq->write_ptr = (ssn & 0xff); - iwl_write_direct32(trans, HBUS_TARG_WRPTR, - (ssn & 0xff) \| (txq_id << 8)); + iwl_trans_write_direct32(trans, HBUS_TARG_WRPTR, + (ssn & 0xff) \| (txq_id << 8)); if (cfg) { u8 frame_limit = cfg->frame_limit; - iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); + iwl_trans_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); / Set up Tx window size and frame limit for this queue / iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + @@ -1240,11 +1240,11 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans trans, int txq_id, u16 ssn, SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); /* Set up status area in SRAM, map to Tx DMA/FIFO, activate / - iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), - (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) \| - (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) \| - (1 << SCD_QUEUE_STTS_REG_POS_WSL) \| - SCD_QUEUE_STTS_REG_MSK); + iwl_trans_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), + (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) \| + (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) \| + (1 << SCD_QUEUE_STTS_REG_POS_WSL) \| + SCD_QUEUE_STTS_REG_MSK); / enable the scheduler for this queue (only) / if (txq_id == trans->conf.cmd_queue && @@ -1335,8 +1335,8 @@ static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans trans, bool block) if (!block && !(WARN_ON_ONCE(!txq->block))) { txq->block--; if (!txq->block) { - iwl_write32(trans, HBUS_TARG_WRPTR, - txq->write_ptr \| (i << 8)); + iwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, + txq->write_ptr \| (i << 8)); } } else if (block) { txq->block++; @@ -2147,6 +2147,9 @@ int iwl_trans_pcie_tx(struct iwl_trans trans, struct sk_buff skb, u16 wifi_seq; bool amsdu; + if (trans->mac_cfg->gen2) + return iwl_txq_gen2_tx(trans, skb, dev_cmd, txq_id); + txq = trans_pcie->txqs.txq[txq_id]; if (WARN_ONCE(!test_bit(txq_id, trans_pcie->txqs.queue_used), diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/utils.c b/drivers/net/wireless/intel/iwlwifi/pcie/utils.c index 1bb274d8390c3..8aa43e5ac0e19 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/utils.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/utils.c @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* - * Copyright (C) 2025 Intel Corporation + * Copyright (C) 2025-2026 Intel Corporation / #include <linux/pci.h> #include <linux/gfp.h> -#include "iwl-io.h" +#include "iwl-trans.h" #include "pcie/utils.h" void iwl_trans_pcie_dump_regs(struct iwl_trans trans, struct pci_dev pdev) @@ -51,7 +51,7 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans trans, struct pci_dev pdev) IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) - ptr = iwl_read32(trans, i); + ptr = iwl_trans_pcie_read32(trans, i); print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); @@ -102,3 +102,88 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans trans, struct pci_dev pdev) pcie_dbg_dumped_once = 1; kfree(buf); } + +u32 iwl_pcie_read_direct32(struct iwl_trans trans, u32 reg) +{ + if (iwl_trans_grab_nic_access(trans)) { + u32 value = iwl_trans_pcie_read32(trans, reg); + + iwl_trans_release_nic_access(trans); + return value; + } + + /* return as if we have a HW timeout/failure / + return 0x5a5a5a5a; +} + +#define IWL_PCIE_POLL_INTERVAL 10 / microseconds / + +int iwl_pcie_poll_direct_bit(struct iwl_trans trans, + u32 addr, u32 mask, int timeout) +{ + int t = 0; + + do { + if ((iwl_pcie_read_direct32(trans, addr) & mask) == mask) + return t; + udelay(IWL_PCIE_POLL_INTERVAL); + t += IWL_PCIE_POLL_INTERVAL; + } while (t < timeout); + + return -ETIMEDOUT; +} + +int iwl_pcie_poll_prph_bit(struct iwl_trans trans, u32 addr, + u32 bits, u32 mask, int timeout) +{ + int t = 0; + + do { + if ((iwl_trans_read_prph(trans, addr) & mask) == (bits & mask)) + return 0; + udelay(IWL_PCIE_POLL_INTERVAL); + t += IWL_PCIE_POLL_INTERVAL; + } while (t < timeout); + + return -ETIMEDOUT; +} + +int iwl_pcie_poll_umac_prph_bit(struct iwl_trans trans, + u32 addr, u32 bits, u32 mask, + int timeout) +{ + return iwl_pcie_poll_prph_bit(trans, addr + + trans->mac_cfg->umac_prph_offset, + bits, mask, timeout); +} + +int iwl_pcie_poll_umac_prph_bits_no_grab(struct iwl_trans trans, u32 addr, + u32 bits, u32 mask, int timeout) +{ + int t = 0; + + do { + if ((iwl_trans_read_umac_prph_no_grab(trans, addr) & mask) == + (bits & mask)) + return 0; + udelay(IWL_PCIE_POLL_INTERVAL); + t += IWL_PCIE_POLL_INTERVAL; + } while (t < timeout); + + return -ETIMEDOUT; +} + +void iwl_pcie_write_prph64_no_grab(struct iwl_trans trans, u32 ofs, u64 val) +{ + trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val); + iwl_pcie_write_prph_no_grab(trans, ofs, val & 0xffffffff); + iwl_pcie_write_prph_no_grab(trans, ofs + 4, val >> 32); +} + +void iwl_pcie_write_direct64(struct iwl_trans trans, u64 reg, u64 value) +{ + if (iwl_trans_grab_nic_access(trans)) { + iwl_pcie_write64(trans, reg, value); + iwl_trans_release_nic_access(trans); + } +} diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/utils.h b/drivers/net/wireless/intel/iwlwifi/pcie/utils.h index 27437d5e099ba..ece1caaa49482 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/utils.h +++ b/drivers/net/wireless/intel/iwlwifi/pcie/utils.h @@ -1,17 +1,43 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / - * Copyright (C) 2025 Intel Corporation + * Copyright (C) 2025-2026 Intel Corporation / #ifndef __iwl_pcie_utils_h__ #define __iwl_pcie_utils_h__ -#include "iwl-io.h" +#include "iwl-trans.h" +#include "internal.h" void iwl_trans_pcie_dump_regs(struct iwl_trans trans, struct pci_dev pdev); -static inline void _iwl_trans_set_bits_mask(struct iwl_trans trans, - u32 reg, u32 mask, u32 value) +u32 iwl_pcie_read_direct32(struct iwl_trans trans, u32 reg); +int iwl_pcie_poll_direct_bit(struct iwl_trans trans, + u32 addr, u32 mask, int timeout); +int iwl_pcie_poll_prph_bit(struct iwl_trans trans, u32 addr, + u32 bits, u32 mask, int timeout); +int iwl_pcie_poll_umac_prph_bit(struct iwl_trans trans, u32 addr, + u32 bits, u32 mask, int timeout); +int iwl_pcie_poll_umac_prph_bits_no_grab(struct iwl_trans trans, u32 addr, + u32 bits, u32 mask, int timeout); +void iwl_pcie_write_prph64_no_grab(struct iwl_trans trans, u32 ofs, u64 val); +void iwl_pcie_write_direct64(struct iwl_trans trans, u64 reg, u64 value); + +static inline void iwl_pcie_write64(struct iwl_trans trans, u64 ofs, u64 val) +{ + iwl_trans_pcie_write32(trans, ofs, lower_32_bits(val)); + iwl_trans_pcie_write32(trans, ofs + 4, upper_32_bits(val)); +} + +static inline void iwl_pcie_write_umac_prph_no_grab(struct iwl_trans trans, + u32 ofs, u32 val) +{ + iwl_pcie_write_prph_no_grab(trans, ofs + trans->mac_cfg->umac_prph_offset, + val); +} + +static inline void iwl_pcie_set_bits_mask(struct iwl_trans trans, + u32 reg, u32 mask, u32 value) { u32 v; @@ -19,22 +45,22 @@ static inline void _iwl_trans_set_bits_mask(struct iwl_trans trans, WARN_ON_ONCE(value & ~mask); #endif - v = iwl_read32(trans, reg); + v = iwl_trans_pcie_read32(trans, reg); v &= ~mask; v \|= value; - iwl_write32(trans, reg, v); + iwl_trans_pcie_write32(trans, reg, v); } -static inline void iwl_trans_clear_bit(struct iwl_trans trans, +static inline void iwl_pcie_clear_bit(struct iwl_trans trans, u32 reg, u32 mask) { - _iwl_trans_set_bits_mask(trans, reg, mask, 0); + iwl_pcie_set_bits_mask(trans, reg, mask, 0); } -static inline void iwl_trans_set_bit(struct iwl_trans trans, +static inline void iwl_pcie_set_bit(struct iwl_trans trans, u32 reg, u32 mask) { - _iwl_trans_set_bits_mask(trans, reg, mask, mask); + iwl_pcie_set_bits_mask(trans, reg, mask, mask); } #endif / __iwl_pcie_utils_h__ */
3/2	2026/10/01 08:48	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 110348 output: 32 thoughts: 582 Thoughts: Analyzing the Potential for Fuzzing iwlwifi Patches Okay, so I see this patch is touching `drivers/net/wireless/intel/iwlwifi/`. My first instinct is to see exactly what is being modified within the `iwlwifi` driver. A quick scan reveals changes across the entire `iwlwifi` directory: Makefile, dvm, fw, mld, mvm, and pcie. It looks like `iwl-io.c` and `iwl-io.h` are gone, replaced by this new ops/trans layer stuff including `iwl-trans.h` and `pcie/utils.h`. Interesting. Within `drivers/net/wireless/intel/iwlwifi/mld/`, it's got KUnit test for `tx-gp2.c`, and other files like `tx.c`, `tx.h`, `d3.c`, `fw.c`, `mac80211.c`, `mld.c`, `mld.h`, `scan.c`, `scan.h`, `rx.c`, `sta.c`. It mentions GP2 timestamping for TX commands, so it's a sizable chunk of work. But then, my brain immediately hits the critical question: is this even fuzzable in a standard environment? The core triage instructions are screaming in my head: "REACHABILITY IS THE PRIMARY GATE!" Fuzzing is only useful if the code executes in a QEMU or GCE environment with emulated devices. I need to know if this code is reachable. The instructions clearly state that if it's structurally unreachable, don't fuzz, regardless of assertions or complex logic. The instructions specifically call out examples: vendor-specific PCIe switches, SmartNICs, or GPU drivers that require real hardware not emulated in standard QEMU. On the other hand, things like virtio, USB gadget, loopback, netlink, binder, and sockets are all fair game. So, is `iwlwifi` a physical PCIe WiFi device driver? That's the key. Does it rely on hardware? Does it have any sort of virtual bus emulation I can leverage? I know that `mac80211_hwsim` exists, but that's a separate driver (`drivers/net/wireless/virtual/mac80211_hwsim.c`), so that's not it. I need to know if `iwlwifi` itself supports any virtualized bus or standard QEMU device. I'm going to have to search the kernel tree and see if there is any emulation or if anything in virtual environments even calls iwlwifi. This is the make or break moment for this patch.
4/2	2026/10/01 08:48	tool	grepper	0m Args: { "Expression": "CONFIG_IWLWIFI", "PathPrefix": "drivers/net/wireless/" } Results: { "Output": "\nFull output is too long, showing 200 out of 918 lines.\nUse more precise expression if possible.\n\ndrivers/net/wireless/intel/Makefile=5=obj-$(CONFIG_IWLEGACY)\t+= iwlegacy/\ndrivers/net/wireless/intel/Makefile-6-\ndrivers/net/wireless/intel/Makefile:7:obj-$(CONFIG_IWLWIFI)\t+= iwlwifi/\ndrivers/net/wireless/intel/Makefile-8-obj-$(CONFIG_IWLMEI)\t+= iwlwifi/\n--\ndrivers/net/wireless/intel/iwlwifi/Makefile-2-# common\ndrivers/net/wireless/intel/iwlwifi/Makefile:3:obj-$(CONFIG_IWLWIFI)\t+= iwlwifi.o\ndrivers/net/wireless/intel/iwlwifi/Makefile-4-iwlwifi-objs\t\t+= iwl-drv.o\n--\ndrivers/net/wireless/intel/iwlwifi/Makefile=39=iwlwifi-$(CONFIG_EFI)\t+= fw/uefi.o\ndrivers/net/wireless/intel/iwlwifi/Makefile:40:iwlwifi-$(CONFIG_IWLWIFI_DEBUGFS) += fw/debugfs.o\ndrivers/net/wireless/intel/iwlwifi/Makefile-41-\ndrivers/net/wireless/intel/iwlwifi/Makefile=42=iwlwifi-objs += $(iwlwifi-m)\ndrivers/net/wireless/intel/iwlwifi/Makefile-43-\ndrivers/net/wireless/intel/iwlwifi/Makefile:44:iwlwifi-$(CONFIG_IWLWIFI_DEVICE_TRACING) += iwl-devtrace.o\ndrivers/net/wireless/intel/iwlwifi/Makefile-45-\n--\ndrivers/net/wireless/intel/iwlwifi/Makefile=51=obj-$(CONFIG_IWLMLD)\t+= mld/\ndrivers/net/wireless/intel/iwlwifi/Makefile-52-\ndrivers/net/wireless/intel/iwlwifi/Makefile:53:obj-$(CONFIG_IWLWIFI_KUNIT_TESTS) += tests/\ndrivers/net/wireless/intel/iwlwifi/Makefile-54-\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/Makefile=9=iwldvm-objs\t\t+= rxon.o devices.o\ndrivers/net/wireless/intel/iwlwifi/dvm/Makefile-10-\ndrivers/net/wireless/intel/iwlwifi/dvm/Makefile:11:iwldvm-$(CONFIG_IWLWIFI_LEDS) += led.o\ndrivers/net/wireless/intel/iwlwifi/dvm/Makefile:12:iwldvm-$(CONFIG_IWLWIFI_DEBUGFS) += debugfs.o\ndrivers/net/wireless/intel/iwlwifi/dvm/Makefile-13-\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h=225=static inline bool iwl_advanced_bt_coexist(struct iwl_priv priv)\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-230-\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h:231:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-232-const char iwl_get_tx_fail_reason(u32 status);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h=335=int iwl_alive_start(struct iwl_priv priv);\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-336-\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h:337:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-338-void iwl_print_rx_config_cmd(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h=407=int iwl_read_eeprom(struct iwl_trans trans, u8 eeprom, size_t eeprom_size);\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-408-\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h:409:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-410-void iwl_dbgfs_register(struct iwl_priv priv, struct dentry dbgfs_dir);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h=412=static inline void iwl_dbgfs_register(struct iwl_priv priv,\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-413-\t\t\t\t struct dentry dbgfs_dir) { }\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h:414:#endif /* CONFIG_IWLWIFI_DEBUGFS /\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-415-\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h:416:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-417-#define IWL_DEBUG_QUIET_RFKILL(m, fmt, args...)\t\\\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h=430=do {\t\t\t\t\t\t\t\t\t\\\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-436-} while (0)\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h:437:#endif\t\t\t\t/ CONFIG_IWLWIFI_DEBUG /\ndrivers/net/wireless/intel/iwlwifi/dvm/agn.h-438-\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c=2153=static ssize_t iwl_dbgfs_echo_test_write(struct file file,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c-2169-\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c:2170:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c-2171-static ssize_t iwl_dbgfs_log_event_read(struct file file,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c=2302=DEBUGFS_WRITE_FILE_OPS(fw_restart);\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c:2303:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c-2304-DEBUGFS_READ_WRITE_FILE_OPS(log_event);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c=2312=void iwl_dbgfs_register(struct iwl_priv priv, struct dentry dbgfs_dir)\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c-2354-\tDEBUGFS_ADD_FILE(fw_restart, dir_debug, 0200);\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c:2355:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/debugfs.c-2356-\tDEBUGFS_ADD_FILE(log_event, dir_debug, 0600);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h=627=struct iwl_priv {\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-765-\t\tstruct statistics_tx tx;\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h:766:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-767-\t\tstruct statistics_bt_activity bt_activity;\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-771-\t} statistics;\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h:772:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-773-\tstruct {\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-847-\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h:848:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-849-\t/ debugfs /\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-853-\tvoid wowlan_sram;\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h:854:#endif /* CONFIG_IWLWIFI_DEBUGFS /\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-855-\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-868-\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h:869:#ifdef CONFIG_IWLWIFI_LEDS\ndrivers/net/wireless/intel/iwlwifi/dvm/dev.h-870-\tstruct led_classdev led;\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/led.h=11=struct iwl_priv;\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/led.h-18-\ndrivers/net/wireless/intel/iwlwifi/dvm/led.h:19:#ifdef CONFIG_IWLWIFI_LEDS\ndrivers/net/wireless/intel/iwlwifi/dvm/led.h-20-void iwlagn_led_enable(struct iwl_priv priv);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/mac80211.c=417=static int iwlagn_mac_resume(struct ieee80211_hw hw)\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/mac80211.c-441-\t};\ndrivers/net/wireless/intel/iwlwifi/dvm/mac80211.c:442:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/mac80211.c-443-\tconst struct fw_img img;\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/mac80211.c-479-\ndrivers/net/wireless/intel/iwlwifi/dvm/mac80211.c:480:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/mac80211.c-481-\timg = \u0026priv-\u003efw-\u003eimg[IWL_UCODE_WOWLAN];\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c=1132=static void iwl_uninit_drv(struct iwl_priv priv)\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1137-\tiwl_calib_free_results(priv);\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1138:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1139-\tkfree(priv-\u003ewowlan_sram);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c=1157=static void iwl_option_config(struct iwl_priv priv)\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1158-{\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1159:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1160:\tIWL_INFO(priv, \"CONFIG_IWLWIFI_DEBUG enabled\\n\");\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1161-#else\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1162:\tIWL_INFO(priv, \"CONFIG_IWLWIFI_DEBUG disabled\\n\");\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1163-#endif\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1164-\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1165:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1166:\tIWL_INFO(priv, \"CONFIG_IWLWIFI_DEBUGFS enabled\\n\");\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1167-#else\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1168:\tIWL_INFO(priv, \"CONFIG_IWLWIFI_DEBUGFS disabled\\n\");\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1169-#endif\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1170-\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1171:#ifdef CONFIG_IWLWIFI_DEVICE_TRACING\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1172:\tIWL_INFO(priv, \"CONFIG_IWLWIFI_DEVICE_TRACING enabled\\n\");\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1173-#else\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1174:\tIWL_INFO(priv, \"CONFIG_IWLWIFI_DEVICE_TRACING disabled\\n\");\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1175-#endif\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c=1811=int iwl_dump_nic_event_log(struct iwl_priv priv, bool full_log,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1876-\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c:1877:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/main.c-1878-\tif (buf) {\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c=87=static void iwlagn_rx_pm_sleep_notif(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-89-{\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c:90:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-91-\tstruct iwl_rx_packet pkt = rxb_addr(rxb);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c=108=static void iwlagn_rx_beacon_notif(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-112-\tstruct iwlagn_beacon_notif beacon = (void )pkt-\u003edata;\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c:113:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-114-\tu16 status = le16_to_cpu(beacon-\u003ebeacon_notify_hdr.status.status);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c=234=static void iwlagn_rx_calc_noise(struct iwl_priv priv)\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-274-\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c:275:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-276-/\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c=341=static void iwlagn_rx_statistics(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-374-\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c:375:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-376-\t\t/ handle this exception directly /\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-415-\tmemcpy(\u0026priv-\u003estatistics.tx, tx, sizeof(tx));\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c:416:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-417-\tif (bt_activity)\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c=444=static void iwlagn_rx_reply_statistics(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-450-\tif (le32_to_cpu(stats-\u003eflag) \u0026 UCODE_STATISTICS_CLEAR_MSK) {\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c:451:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/rx.c-452-\t\tmemset(\u0026priv-\u003eaccum_stats, 0,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rxon.c=832=static int iwl_full_rxon_required(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/rxon.c-886-\ndrivers/net/wireless/intel/iwlwifi/dvm/rxon.c:887:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/rxon.c-888-void iwl_print_rx_config_cmd(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/scan.c=232=static void iwl_rx_reply_scan(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/scan.c-234-{\ndrivers/net/wireless/intel/iwlwifi/dvm/scan.c:235:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/scan.c-236-\tstruct iwl_rx_packet pkt = rxb_addr(rxb);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/scan.c=262=static void iwl_rx_scan_results_notif(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/scan.c-264-{\ndrivers/net/wireless/intel/iwlwifi/dvm/scan.c:265:#ifdef CONFIG_IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/dvm/scan.c-266-\tstruct iwl_rx_packet pkt = rxb_addr(rxb);\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/sta.c=126=bool iwl_is_ht40_tx_allowed(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/sta.c-132-\ndrivers/net/wireless/intel/iwlwifi/dvm/sta.c:133:#ifdef CONFIG_IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/dvm/sta.c-134-\tif (priv-\u003edisable_ht40)\n\n" }
5/2	2026/10/01 08:48	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 116823 output: 33 thoughts: 12 Thoughts: Okay, here's my take on those thoughts, tailored for an expert audience: Examining the iwlwifi Kconfig Alright, let's dive right in. My first thought is to immediately check the iwlwifi Kconfig. This is where the magic happens, the heart of the configuration. I want to quickly ascertain the current state of the driver, the available options, and any recent changes that might impact its behavior. I’m thinking about quickly reviewing the default build options, dependencies on other kernel modules or features, and any specific configuration flags that could potentially be causing the behavior I'm investigating. I need to get a clear picture of what’s enabled, what’s disabled, and how everything is interconnected within the broader kernel configuration. This is where it all starts, after all.
6/2	2026/10/01 08:48	tool	grepper	0m Args: { "Expression": "config IWLWIFI", "PathPrefix": "drivers/net/wireless/intel/" } Results: { "Output": "drivers/net/wireless/intel/iwlwifi/Kconfig-1-# SPDX-License-Identifier: GPL-2.0-only\ndrivers/net/wireless/intel/iwlwifi/Kconfig:2:config IWLWIFI\ndrivers/net/wireless/intel/iwlwifi/Kconfig-3-\ttristate \"Intel Wireless WiFi Next Gen AGN - Wireless-N/Advanced-N/Ultimate-N (iwlwifi) \"\n--\ndrivers/net/wireless/intel/iwlwifi/Kconfig=47=if IWLWIFI\ndrivers/net/wireless/intel/iwlwifi/Kconfig-48-\ndrivers/net/wireless/intel/iwlwifi/Kconfig:49:config IWLWIFI_KUNIT_TESTS\ndrivers/net/wireless/intel/iwlwifi/Kconfig-50-\ttristate\n--\ndrivers/net/wireless/intel/iwlwifi/Kconfig-57-\ndrivers/net/wireless/intel/iwlwifi/Kconfig:58:config IWLWIFI_LEDS\ndrivers/net/wireless/intel/iwlwifi/Kconfig-59-\tbool\n--\ndrivers/net/wireless/intel/iwlwifi/Kconfig=84=config IWLMLD\n--\ndrivers/net/wireless/intel/iwlwifi/Kconfig-94-# don't call it _MODULE -- will confuse Kconfig/fixdep/...\ndrivers/net/wireless/intel/iwlwifi/Kconfig:95:config IWLWIFI_OPMODE_MODULAR\ndrivers/net/wireless/intel/iwlwifi/Kconfig-96-\tbool\n--\ndrivers/net/wireless/intel/iwlwifi/Kconfig=105=menu \"Debugging Options\"\ndrivers/net/wireless/intel/iwlwifi/Kconfig-106-\ndrivers/net/wireless/intel/iwlwifi/Kconfig:107:config IWLWIFI_DEBUG\ndrivers/net/wireless/intel/iwlwifi/Kconfig-108-\tbool \"Enable full debugging output in the iwlwifi driver\"\n--\ndrivers/net/wireless/intel/iwlwifi/Kconfig-130-\ndrivers/net/wireless/intel/iwlwifi/Kconfig:131:config IWLWIFI_DEBUGFS\ndrivers/net/wireless/intel/iwlwifi/Kconfig-132-\tbool \"iwlwifi debugfs support\"\n--\ndrivers/net/wireless/intel/iwlwifi/Kconfig-138-\ndrivers/net/wireless/intel/iwlwifi/Kconfig:139:config IWLWIFI_DEVICE_TRACING\ndrivers/net/wireless/intel/iwlwifi/Kconfig-140-\tbool \"iwlwifi device access tracing\"\n" }
7/2	2026/10/01 08:48	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 117699 output: 40 thoughts: 32 Thoughts: Okay, let's dive into this. Here's how I'm thinking about it: Examining iwlwifi Kconfig Dependencies Alright, I need to get a clear picture of the dependencies for this `iwlwifi` wireless driver, so I’m going to focus on the `Kconfig` file in the `drivers/net/wireless/intel/iwlwifi` directory. Specifically, I'm going to look at the first 50 lines or so. That should give me a solid overview of the configuration options, any included files, and, most importantly, the relationships between the features. I'm expecting to find conditional dependencies based on architecture, kernel features, or perhaps other networking components. Understanding these dependencies is key to efficient debugging, porting, or even just general understanding of the driver's build process, especially if I'm planning to modify it or integrate it into a custom kernel configuration. I'm hoping to quickly identify the crucial variables driving the build decisions within this particular part of the code.
8/2	2026/10/01 08:48	tool	read-file	0m Args: { "File": "drivers/net/wireless/intel/iwlwifi/Kconfig", "FirstLine": 1, "LineCount": 50 } Results: { "Contents": " 1:\t# SPDX-License-Identifier: GPL-2.0-only\n 2:\tconfig IWLWIFI\n 3:\t\ttristate \"Intel Wireless WiFi Next Gen AGN - Wireless-N/Advanced-N/Ultimate-N (iwlwifi) \"\n 4:\t\tdepends on PCI \u0026\u0026 HAS_IOMEM \u0026\u0026 CFG80211\n 5:\t\tdepends on IWLMEI \|\| !IWLMEI\n 6:\t\tselect FW_LOADER\n 7:\t\thelp\n 8:\t\t Select to build the driver supporting the:\n 9:\t\n 10:\t\t Intel Wireless WiFi Link Next-Gen AGN\n 11:\t\n 12:\t\t This option enables support for use with the following hardware:\n 13:\t\t\tIntel Wireless WiFi Link 6250AGN Adapter\n 14:\t\t\tIntel 6000 Series Wi-Fi Adapters (6200AGN and 6300AGN)\n 15:\t\t\tIntel WiFi Link 1000BGN\n 16:\t\t\tIntel Wireless WiFi 5150AGN\n 17:\t\t\tIntel Wireless WiFi 5100AGN, 5300AGN, and 5350AGN\n 18:\t\t\tIntel 6005 Series Wi-Fi Adapters\n 19:\t\t\tIntel 6030 Series Wi-Fi Adapters\n 20:\t\t\tIntel Wireless WiFi Link 6150BGN 2 Adapter\n 21:\t\t\tIntel 100 Series Wi-Fi Adapters (100BGN and 130BGN)\n 22:\t\t\tIntel 2000 Series Wi-Fi Adapters\n 23:\t\t\tIntel 7260 Wi-Fi Adapter\n 24:\t\t\tIntel 3160 Wi-Fi Adapter\n 25:\t\t\tIntel 7265 Wi-Fi Adapter\n 26:\t\t\tIntel 8260 Wi-Fi Adapter\n 27:\t\t\tIntel 3165 Wi-Fi Adapter\n 28:\t\n 29:\t\n 30:\t\t This driver uses the kernel's mac80211 subsystem.\n 31:\t\n 32:\t\t In order to use this driver, you will need a firmware\n 33:\t\t image for it. You can obtain the microcode from:\n 34:\t\n 35:\t\t \u003chttps://wireless.wiki.kernel.org/en/users/Drivers/iwlwifi\u003e.\n 36:\t\n 37:\t\t The firmware is typically installed in /lib/firmware. You can\n 38:\t\t look in the hotplug script /etc/hotplug/firmware.agent to\n 39:\t\t determine which directory FIRMWARE_DIR is set to when the script\n 40:\t\t runs.\n 41:\t\n 42:\t\t If you want to compile the driver as a module ( = code which can be\n 43:\t\t inserted in and removed from the running kernel whenever you want),\n 44:\t\t say M here and read \u003cfile:Documentation/kbuild/modules.rst\u003e. The\n 45:\t\t module will be called iwlwifi.\n 46:\t\n 47:\tif IWLWIFI\n 48:\t\n 49:\tconfig IWLWIFI_KUNIT_TESTS\n 50:\t\ttristate\n" }
9/2	2026/10/01 08:48	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 118802 output: 37 thoughts: 1384 Thoughts: Analyzing the iwlwifi Commit: Reachability in a Fuzzing Context Okay, here's the deal. I'm looking at this commit and immediately see that `iwlwifi` depends on `PCI`, `HAS_IOMEM`, and `CFG80211`. All the changes are contained within the `drivers/net/wireless/intel/iwlwifi/` directory, specifically touching the `Makefile`, `dvm`, `fw`, `iwl-csr.h`, `iwl-dbg-tlv.c`, `iwl-devtrace-io.h`, `iwl-nvm-parse.c`, `iwl-scd.h`, `iwl-trans.c`, `iwl-trans.h`, `mld`, `mvm`, and `pcie` subdirectories. Wait, I see `iwl-io.c` and `iwl-io.h` are deleted. The question that immediately pops into my head is: is `iwlwifi` even reachable in a standard QEMU or GCE environment? I know from experience that standard virtualized environments, like QEMU and GCE, don't emulate Intel Wireless PCI NICs. They're more about emulating things like e1000, e1000e, rtl8139, and virtio-net. For wireless, we typically rely on `mac80211_hwsim` or `virt_wifi`. But `iwlwifi` is a vendor-specific driver for Intel WiFi hardware – the 6250, 7260, AX200, etc. That means it requires actual Intel PCIe hardware to operate. Hold on, let's confirm the rules. I recall that section of the instructions that highlights: "- Structurally unreachable hardware: Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU." Bingo. Ah, but wait! There's a `drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c` file added in this commit. KUnit tests, eh? Now, can syzkaller even fuzz KUnit tests? No. Syzkaller is focused on fuzzing through syscalls, netlink, ioctls, USB emulation, packet injection, and the like. It doesn't typically fuzz KUnit test suites, which either run at boot or through debugfs. Thinking it through, the `iwl_mld_tx_gp2_from_est` function in `tx.c` is only called by `iwl_mld_tx_gp2_timestamp()`, which itself is only called by `iwl_mld_fill_tx_cmd()` within the TX path of iwlwifi's MLD opmode, or tested by the KUnit test `test_tx_gp2`. However, without physical Intel WiFi PCIe hardware, the driver's probe function (`_iwl_pci_probe`) never executes. That means the device isn't created, mac80211 never binds the `iwlwifi` driver as an interface, and the TX path never executes. So this KUnit test is probably unreachable in a practical fuzzing sense. To recap the core triage philosophy, which I recall: Fuzzing can only find bugs in code that's reachable in standard virtualized environments. If the modified code is structurally unreachable, it MUST NOT be fuzzed, regardless of if it adds assertions. So, the next thought is: does `iwlwifi` have any virtual transport or mock transport to aid in testing? I'll need to double-check the kernel tree for any virtual bus or test harness specific to `iwlwifi`.
10/2	2026/10/01 08:48	tool	grepper	0m Args: { "Expression": "iwl_trans_alloc", "PathPrefix": "drivers/net/wireless/intel/iwlwifi" } Results: { "Output": "drivers/net/wireless/intel/iwlwifi/dvm/tx.c=259=int iwlagn_tx_skb(struct iwl_priv priv,\n--\ndrivers/net/wireless/intel/iwlwifi/dvm/tx.c-342-\ndrivers/net/wireless/intel/iwlwifi/dvm/tx.c:343:\tdev_cmd = iwl_trans_alloc_tx_cmd(priv-\u003etrans);\ndrivers/net/wireless/intel/iwlwifi/dvm/tx.c-344-\n--\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c=204=static void iwl_trans_restart_wk(struct work_struct wk)\n--\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c-268-\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c:269:struct iwl_trans iwl_trans_alloc(unsigned int priv_size,\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c-270-\t\t\t\t struct device dev,\n--\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c=336=IWL_EXPORT_SYMBOL(iwl_trans_send_cmd);\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c-337-\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c:338:struct iwl_device_tx_cmd iwl_trans_alloc_tx_cmd(struct iwl_trans trans)\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c-339-{\n--\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c-341-}\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c:342:IWL_EXPORT_SYMBOL(iwl_trans_alloc_tx_cmd);\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.c-343-\n--\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.h=842=iwl_trans_dump_data(struct iwl_trans trans, u32 dump_mask,\n--\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.h-845-\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.h:846:struct iwl_device_tx_cmd iwl_trans_alloc_tx_cmd(struct iwl_trans trans);\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.h-847-\n--\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.h=1143=static inline void iwl_trans_finish_sw_reset(struct iwl_trans trans)\n--\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.h-1150- ****************************************************/\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.h:1151:struct iwl_trans iwl_trans_alloc(unsigned int priv_size,\ndrivers/net/wireless/intel/iwlwifi/iwl-trans.h-1152-\t\t\t\t struct device dev,\n--\ndrivers/net/wireless/intel/iwlwifi/mld/tx.c=881=static int iwl_mld_tx_mpdu(struct iwl_mld mld, struct sk_buff skb,\n--\ndrivers/net/wireless/intel/iwlwifi/mld/tx.c-897-\ndrivers/net/wireless/intel/iwlwifi/mld/tx.c:898:\tdev_tx_cmd = iwl_trans_alloc_tx_cmd(mld-\u003etrans);\ndrivers/net/wireless/intel/iwlwifi/mld/tx.c-899-\tif (unlikely(!dev_tx_cmd))\n--\ndrivers/net/wireless/intel/iwlwifi/mvm/tx.c=553=iwl_mvm_set_tx_params(struct iwl_mvm mvm, struct sk_buff skb,\n--\ndrivers/net/wireless/intel/iwlwifi/mvm/tx.c-561-\ndrivers/net/wireless/intel/iwlwifi/mvm/tx.c:562:\tdev_cmd = iwl_trans_alloc_tx_cmd(mvm-\u003etrans);\ndrivers/net/wireless/intel/iwlwifi/mvm/tx.c-563-\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c=3742=iwl_trans_pcie_alloc(struct pci_dev pdev,\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-3750-\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c:3751:\ttrans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), \u0026pdev-\u003edev,\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-3752-\t\t\t\t\u0026iwl_trans_pcie_ops, mac_cfg);\n" }
11/2	2026/10/01 08:48	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 122395 output: 40 thoughts: 111 Thoughts: Verifying the Call Hierarchy of `iwl_trans_alloc` Okay, so I need to quickly confirm something about this `iwl_trans_alloc` function. My understanding is that it's called exclusively by `iwl_trans_pcie_alloc`, and looking at the code, specifically in `drivers/net/wireless/intel/iwlwifi/pcie/trans.c`, that looks correct. It's the only place I see it being called. Now, going one level up the call stack, I need to make sure that `iwl_trans_pcie_alloc` itself is only called from `_iwl_pci_probe`. And, yes, as I suspected, checking `pcie/drv.c` confirms that this is the only call site for `iwl_trans_pcie_alloc`. Excellent. That helps me maintain a clear mental model of the initialization and resource allocation within the Intel wireless driver's PCIe transport layer. I'm just verifying my existing knowledge for my own peace of mind.
12/2	2026/10/01 08:48	tool	grepper	0m Args: { "Expression": "iwl_trans_pcie_alloc", "PathPrefix": "drivers/net/wireless/intel/iwlwifi" } Results: { "Output": "drivers/net/wireless/intel/iwlwifi/pcie/trans.c=3596=void iwl_trans_pcie_sync_nmi(struct iwl_trans trans)\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-3643-\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c:3644:static int iwl_trans_pcie_alloc_txcmd_pool(struct iwl_trans trans)\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-3645-{\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c=3741=static struct iwl_trans \ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c:3742:iwl_trans_pcie_alloc(struct pci_dev pdev,\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-3743-\t\t const struct iwl_mac_cfg mac_cfg,\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-3762-\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c:3763:\tret = iwl_trans_pcie_alloc_txcmd_pool(trans);\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-3764-\tif (ret)\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c=4169=int _iwl_pci_probe(struct pci_dev pdev, const struct pci_device_id *ent,\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-4181-\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c:4182:\tiwl_trans = iwl_trans_pcie_alloc(pdev, mac_cfg, \u0026info, hw_base);\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-4183-\tif (IS_ERR(iwl_trans))\n" }
13/2	2026/10/01 08:48	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 123329 output: 39 thoughts: 50 Thoughts: Okay, here's my interpretation of that: My Deductions on iwl_trans_pcie_alloc and Probe Functions Alright, let me break this down. From what I'm seeing, `iwl_trans_pcie_alloc` only gets invoked from within `_iwl_pci_probe()`. That's a pretty critical point, as it immediately tells me something about the scope and potential dependencies of that allocation function. It's essentially private to that specific probe path. Then, taking this a step further, `_iwl_pci_probe` itself is called by `iwl_pci_probe`. This establishes the call chain, iwl_pci_probe calls _iwl_pci_probe, and this function controls the execution of `iwl_trans_pcie_alloc`. I should probably confirm that with the relevant symbol definitions, but this strongly suggests that this allocation is tightly coupled with the PCI probe sequence for these Intel wireless devices. This tells me a lot.
14/2	2026/10/01 08:48	tool	grepper	0m Args: { "Expression": "_iwl_pci_probe", "PathPrefix": "drivers/net/wireless/intel/iwlwifi" } Results: { "Output": "drivers/net/wireless/intel/iwlwifi/pcie/drv.c=1151=static int iwl_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/drv.c-1190-\ndrivers/net/wireless/intel/iwlwifi/pcie/drv.c:1191:\treturn _iwl_pci_probe(pdev, ent, mac_cfg, hw_base, hw_rev);\ndrivers/net/wireless/intel/iwlwifi/pcie/drv.c-1192-}\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/internal.h=1171=void iwl_pcie_alloc_fw_monitor(struct iwl_trans trans, u8 max_power);\ndrivers/net/wireless/intel/iwlwifi/pcie/internal.h:1172:int _iwl_pci_probe(struct pci_dev pdev, const struct pci_device_id ent,\ndrivers/net/wireless/intel/iwlwifi/pcie/internal.h-1173-\t\t const struct iwl_mac_cfg mac_cfg,\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c=4137=static void iwl_pcie_check_me_status(struct iwl_trans trans)\n--\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-4168-\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c:4169:int _iwl_pci_probe(struct pci_dev pdev, const struct pci_device_id ent,\ndrivers/net/wireless/intel/iwlwifi/pcie/trans.c-4170-\t\t const struct iwl_mac_cfg mac_cfg,\n" }
15/2	2026/10/01 08:48	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 124131 output: 98 thoughts: 1889 Thoughts: Analysis of the iwlwifi Driver for Fuzzing Suitability Okay, so my immediate thought is that `iwlwifi` is a PCI driver specifically for Intel wireless NICs. It doesn't use any virtual bus bindings, there's no USB support here (these are all PCI/PCIe devices), and there's no emulation present within QEMU. That's a key initial observation. Following the instructions, I'm going to consult Section 2, which highlights "Structurally unreachable hardware." Specifically, I see it lists vendor-specific PCIe devices as being problematic for fuzzing because they need physical hardware not emulated by standard QEMU. Intel WiFi, or `iwlwifi`, definitely falls into that category. It requires a physical Intel WiFi PCIe card, as the section clearly states. Now, let's confirm the scope of the modifications. A quick check of the provided git diff reveals that every single file touched is contained within `drivers/net/wireless/intel/iwlwifi/`. Nothing outside of that directory has been modified. This is important. Given that everything modified is strictly within the Intel iwlwifi PCIe driver and that the documentation's Section 2 explicitly states that vendor-specific PCIe devices are unreachable, and the hardware is not emulated in QEMU environments, the conclusion is clear. I am setting `WorthFuzzing` to `false`. There's no point in trying to fuzz code that requires hardware we can't emulate or access in a standard fuzzing environment. Consequently, `EnableConfigs` will be an empty list, and `FocusSymbols` will be an empty list. The reasoning is as follows: The modifications are exclusively within the Intel WiFi driver (`iwlwifi`). This driver targets vendor-specific PCIe hardware which isn't emulated in standard virtualized environments (QEMU, GCE). This makes the code structurally unreachable, so fuzzing is not worthwhile. I've verified that the set-results requirements are met. Time to call `set-results`.
16/2	2026/10/01 08:48	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The changes are strictly confined to the Intel wireless driver (iwlwifi), which drives vendor-specific Intel PCIe Wi-Fi adapters. Because standard virtualized environments (QEMU/GCE) lack emulation for this physical PCIe hardware, the modified driver code paths cannot be probed or executed during fuzzing, making them structurally unreachable.", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The changes are strictly confined to the Intel wireless driver (iwlwifi), which drives vendor-specific Intel PCIe Wi-Fi adapters. Because standard virtualized environments (QEMU/GCE) lack emulation for this physical PCIe hardware, the modified driver code paths cannot be probed or executed during fuzzing, making them structurally unreachable.", "WorthFuzzing": false }
17/1	2026/10/01 08:48	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "PatchDiff": "commit 3f251a1e32cc7686e741e402cd3ebb5513c6fd71\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Thu Oct 1 08:48:03 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/wireless/intel/iwlwifi/Makefile b/drivers/net/wireless/intel/iwlwifi/Makefile\nindex 6746281350e0e..504381b4aac7c 100644\n--- a/drivers/net/wireless/intel/iwlwifi/Makefile\n+++ b/drivers/net/wireless/intel/iwlwifi/Makefile\n@@ -1,7 +1,6 @@\n # SPDX-License-Identifier: GPL-2.0\n # common\n obj-$(CONFIG_IWLWIFI)\t+= iwlwifi.o\n-iwlwifi-objs\t\t+= iwl-io.o\n iwlwifi-objs\t\t+= iwl-drv.o\n iwlwifi-objs\t\t+= iwl-debug.o\n iwlwifi-objs\t\t+= iwl-nvm-utils.o\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c\nindex ec94c43ba28c1..799599efdd06e 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c\n@@ -2,7 +2,7 @@\n /******************************************************************************\n  *\n  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2018, 2025 Intel Corporation\n+ * Copyright (C) 2018, 2025-2026 Intel Corporation\n  *****************************************************************************/\n \n #include \u003clinux/slab.h\u003e\n@@ -14,7 +14,6 @@\n \n #include \"iwl-debug.h\"\n #include \"iwl-trans.h\"\n-#include \"iwl-io.h\"\n #include \"dev.h\"\n #include \"agn.h\"\n \n@@ -1788,7 +1787,7 @@ static ssize_t iwl_dbgfs_power_save_status_read(struct file *file,\n \tconst size_t bufsz = sizeof(buf);\n \tu32 pwrsave_status;\n \n-\tpwrsave_status = iwl_read32(priv-\u003etrans, CSR_GP_CNTRL) \u0026\n+\tpwrsave_status = iwl_trans_read32(priv-\u003etrans, CSR_GP_CNTRL) \u0026\n \t\t\tCSR_GP_REG_POWER_SAVE_STATUS_MSK;\n \n \tpos += scnprintf(buf + pos, bufsz - pos, \"Power Save Status: \");\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/devices.c b/drivers/net/wireless/intel/iwlwifi/dvm/devices.c\nindex 7f83f1bbdaad8..b7bd5e6deb5d1 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/devices.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/devices.c\n@@ -2,7 +2,7 @@\n /******************************************************************************\n  *\n  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2019, 2025 Intel Corporation\n+ * Copyright (C) 2019, 2025-2026 Intel Corporation\n  *****************************************************************************/\n \n #include \u003clinux/units.h\u003e\n@@ -10,7 +10,7 @@\n /*\n  * DVM device-specific data \u0026 functions\n  */\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-nvm-utils.h\"\n \n@@ -45,10 +45,10 @@ static void iwl1000_set_ct_threshold(struct iwl_priv *priv)\n static void iwl1000_nic_config(struct iwl_priv *priv)\n {\n \t/* Setting digital SVR for 1000 card to 1.32V */\n-\t/* locking is acquired in iwl_set_bits_mask_prph() function */\n-\tiwl_set_bits_mask_prph(priv-\u003etrans, APMG_DIGITAL_SVR_REG,\n-\t\t\t\tAPMG_SVR_DIGITAL_VOLTAGE_1_32,\n-\t\t\t\t~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);\n+\t/* locking is acquired in iwl_trans_set_bits_mask_prph() function */\n+\tiwl_trans_set_bits_mask_prph(priv-\u003etrans, APMG_DIGITAL_SVR_REG,\n+\t\t\t\t     APMG_SVR_DIGITAL_VOLTAGE_1_32,\n+\t\t\t\t     ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);\n }\n \n /**\n@@ -184,8 +184,8 @@ static void iwl2000_set_ct_threshold(struct iwl_priv *priv)\n /* NIC configuration for 2000 series */\n static void iwl2000_nic_config(struct iwl_priv *priv)\n {\n-\tiwl_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t    CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);\n+\tiwl_trans_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t  CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);\n }\n \n static const struct iwl_sensitivity_ranges iwl2000_sensitivity = {\n@@ -490,22 +490,22 @@ static void iwl6000_nic_config(struct iwl_priv *priv)\n \t\tbreak;\n \tcase IWL_DEVICE_FAMILY_6000i:\n \t\t/* 2x2 IPA phy type */\n-\t\tiwl_write32(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t\t     CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);\n+\t\tiwl_trans_write32(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t\t  CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);\n \t\tbreak;\n \tcase IWL_DEVICE_FAMILY_6050:\n \t\t/* Indicate calibration version to uCode. */\n \t\tif (priv-\u003envm_data-\u003ecalib_version \u003e= 6)\n-\t\t\tiwl_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t\t\t\tCSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);\n+\t\t\tiwl_trans_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t\t\t  CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);\n \t\tbreak;\n \tcase IWL_DEVICE_FAMILY_6150:\n \t\t/* Indicate calibration version to uCode. */\n \t\tif (priv-\u003envm_data-\u003ecalib_version \u003e= 6)\n-\t\t\tiwl_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t\t\t\tCSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);\n-\t\tiwl_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n-\t\t\t    CSR_GP_DRIVER_REG_BIT_6050_1x2);\n+\t\t\tiwl_trans_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t\t\t  CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);\n+\t\tiwl_trans_set_bit(priv-\u003etrans, CSR_GP_DRIVER_REG,\n+\t\t\t\t  CSR_GP_DRIVER_REG_BIT_6050_1x2);\n \t\tbreak;\n \tdefault:\n \t\tWARN_ON(1);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c b/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c\nindex 6de2517188f73..190e482849ac2 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c\n@@ -1,6 +1,6 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /*\n- * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2025 Intel Corporation\n+ * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2026 Intel Corporation\n  */\n #include \u003clinux/types.h\u003e\n #include \u003clinux/slab.h\u003e\n@@ -8,7 +8,7 @@\n \n #include \"iwl-drv.h\"\n #include \"iwl-debug.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"agn.h\"\n@@ -672,13 +672,13 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)\n \n \tfor (count = 0; count \u003c IWL_EEPROM_SEM_RETRY_LIMIT; count++) {\n \t\t/* Request semaphore */\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t    CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t  CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);\n \n \t\t/* See if we got it */\n-\t\tret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t\t    CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,\n-\t\t\t\t    IWL_EEPROM_SEM_TIMEOUT);\n+\t\tret = iwl_trans_poll_bits(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t\t  CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,\n+\t\t\t\t\t  IWL_EEPROM_SEM_TIMEOUT);\n \t\tif (!ret) {\n \t\t\tIWL_DEBUG_EEPROM(trans-\u003edev,\n \t\t\t\t\t \"Acquired semaphore after %d tries.\\n\",\n@@ -692,13 +692,13 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)\n \n static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)\n {\n-\tiwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t      CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);\n+\tiwl_trans_clear_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t    CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);\n }\n \n static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)\n {\n-\tu32 gp = iwl_read32(trans, CSR_EEPROM_GP) \u0026 CSR_EEPROM_GP_VALID_MSK;\n+\tu32 gp = iwl_trans_read32(trans, CSR_EEPROM_GP) \u0026 CSR_EEPROM_GP_VALID_MSK;\n \n \tIWL_DEBUG_EEPROM(trans-\u003edev, \"EEPROM signature=0x%08x\\n\", gp);\n \n@@ -734,10 +734,10 @@ static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)\n \n static void iwl_set_otp_access_absolute(struct iwl_trans *trans)\n {\n-\tiwl_read32(trans, CSR_OTP_GP_REG);\n+\tiwl_trans_read32(trans, CSR_OTP_GP_REG);\n \n-\tiwl_clear_bit(trans, CSR_OTP_GP_REG,\n-\t\t      CSR_OTP_GP_REG_OTP_ACCESS_MODE);\n+\tiwl_trans_clear_bit(trans, CSR_OTP_GP_REG,\n+\t\t\t    CSR_OTP_GP_REG_OTP_ACCESS_MODE);\n }\n \n static int iwl_nvm_is_otp(struct iwl_trans *trans)\n@@ -755,7 +755,7 @@ static int iwl_nvm_is_otp(struct iwl_trans *trans)\n \tcase CSR_HW_REV_TYPE_5150:\n \t\treturn 0;\n \tdefault:\n-\t\totpgp = iwl_read32(trans, CSR_OTP_GP_REG);\n+\t\totpgp = iwl_trans_read32(trans, CSR_OTP_GP_REG);\n \t\tif (otpgp \u0026 CSR_OTP_GP_REG_DEVICE_SELECT)\n \t\t\treturn 1;\n \t\treturn 0;\n@@ -770,19 +770,19 @@ static int iwl_init_otp_access(struct iwl_trans *trans)\n \tif (ret)\n \t\treturn ret;\n \n-\tiwl_set_bits_prph(trans, APMG_PS_CTRL_REG,\n-\t\t\t  APMG_PS_CTRL_VAL_RESET_REQ);\n+\tiwl_trans_set_bits_prph(trans, APMG_PS_CTRL_REG,\n+\t\t\t\tAPMG_PS_CTRL_VAL_RESET_REQ);\n \tudelay(5);\n-\tiwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,\n-\t\t\t    APMG_PS_CTRL_VAL_RESET_REQ);\n+\tiwl_trans_clear_bits_prph(trans, APMG_PS_CTRL_REG,\n+\t\t\t\t  APMG_PS_CTRL_VAL_RESET_REQ);\n \n \t/*\n \t * CSR auto clock gate disable bit -\n \t * this is only applicable for HW with OTP shadow RAM\n \t */\n \tif (trans-\u003emac_cfg-\u003ebase-\u003eshadow_ram_support)\n-\t\tiwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t    CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\tiwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t  CSR_RESET_LINK_PWR_MGMT_DISABLED);\n \n \treturn 0;\n }\n@@ -794,31 +794,31 @@ static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,\n \tu32 r;\n \tu32 otpgp;\n \n-\tiwl_write32(trans, CSR_EEPROM_REG,\n-\t\t    CSR_EEPROM_REG_MSK_ADDR \u0026 (addr \u003c\u003c 1));\n-\tret = iwl_poll_bits(trans, CSR_EEPROM_REG,\n-\t\t\t    CSR_EEPROM_REG_READ_VALID_MSK,\n-\t\t\t    IWL_EEPROM_ACCESS_TIMEOUT);\n+\tiwl_trans_write32(trans, CSR_EEPROM_REG,\n+\t\t\t  CSR_EEPROM_REG_MSK_ADDR \u0026 (addr \u003c\u003c 1));\n+\tret = iwl_trans_poll_bits(trans, CSR_EEPROM_REG,\n+\t\t\t\t  CSR_EEPROM_REG_READ_VALID_MSK,\n+\t\t\t\t  IWL_EEPROM_ACCESS_TIMEOUT);\n \tif (ret) {\n \t\tIWL_ERR(trans, \"Time out reading OTP[%d]\\n\", addr);\n \t\treturn ret;\n \t}\n-\tr = iwl_read32(trans, CSR_EEPROM_REG);\n+\tr = iwl_trans_read32(trans, CSR_EEPROM_REG);\n \t/* check for ECC errors: */\n-\totpgp = iwl_read32(trans, CSR_OTP_GP_REG);\n+\totpgp = iwl_trans_read32(trans, CSR_OTP_GP_REG);\n \tif (otpgp \u0026 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {\n \t\t/* stop in this case */\n \t\t/* set the uncorrectable OTP ECC bit for acknowledgment */\n-\t\tiwl_set_bit(trans, CSR_OTP_GP_REG,\n-\t\t\t    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);\n+\t\tiwl_trans_set_bit(trans, CSR_OTP_GP_REG,\n+\t\t\t\t  CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);\n \t\tIWL_ERR(trans, \"Uncorrectable OTP ECC error, abort OTP read\\n\");\n \t\treturn -EINVAL;\n \t}\n \tif (otpgp \u0026 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {\n \t\t/* continue in this case */\n \t\t/* set the correctable OTP ECC bit for acknowledgment */\n-\t\tiwl_set_bit(trans, CSR_OTP_GP_REG,\n-\t\t\t    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);\n+\t\tiwl_trans_set_bit(trans, CSR_OTP_GP_REG,\n+\t\t\t\t  CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);\n \t\tIWL_ERR(trans, \"Correctable OTP ECC error, continue read\\n\");\n \t}\n \t*eeprom_data = cpu_to_le16(r \u003e\u003e 16);\n@@ -918,7 +918,7 @@ static int iwl_find_otp_image(struct iwl_trans *trans,\n int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)\n {\n \t__le16 *e;\n-\tu32 gp = iwl_read32(trans, CSR_EEPROM_GP);\n+\tu32 gp = iwl_trans_read32(trans, CSR_EEPROM_GP);\n \tint sz;\n \tint ret;\n \tu16 addr;\n@@ -960,13 +960,13 @@ int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)\n \t\t\tgoto err_unlock;\n \t\t}\n \n-\t\tiwl_write32(trans, CSR_EEPROM_GP,\n-\t\t\t    iwl_read32(trans, CSR_EEPROM_GP) \u0026\n-\t\t\t    ~CSR_EEPROM_GP_IF_OWNER_MSK);\n+\t\tiwl_trans_write32(trans, CSR_EEPROM_GP,\n+\t\t\t\t  iwl_trans_read32(trans, CSR_EEPROM_GP) \u0026\n+\t\t\t\t  ~CSR_EEPROM_GP_IF_OWNER_MSK);\n \n-\t\tiwl_set_bit(trans, CSR_OTP_GP_REG,\n-\t\t\t    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |\n-\t\t\t    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);\n+\t\tiwl_trans_set_bit(trans, CSR_OTP_GP_REG,\n+\t\t\t\t  CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |\n+\t\t\t\t  CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);\n \t\t/* traversing the linked list if no shadow ram supported */\n \t\tif (!trans-\u003emac_cfg-\u003ebase-\u003eshadow_ram_support) {\n \t\t\tret = iwl_find_otp_image(trans, \u0026validblockaddr);\n@@ -988,18 +988,18 @@ int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)\n \t\tfor (addr = 0; addr \u003c sz; addr += sizeof(u16)) {\n \t\t\tu32 r;\n \n-\t\t\tiwl_write32(trans, CSR_EEPROM_REG,\n-\t\t\t\t    CSR_EEPROM_REG_MSK_ADDR \u0026 (addr \u003c\u003c 1));\n+\t\t\tiwl_trans_write32(trans, CSR_EEPROM_REG,\n+\t\t\t\t\t  CSR_EEPROM_REG_MSK_ADDR \u0026 (addr \u003c\u003c 1));\n \n-\t\t\tret = iwl_poll_bits(trans, CSR_EEPROM_REG,\n-\t\t\t\t\t    CSR_EEPROM_REG_READ_VALID_MSK,\n-\t\t\t\t\t    IWL_EEPROM_ACCESS_TIMEOUT);\n+\t\t\tret = iwl_trans_poll_bits(trans, CSR_EEPROM_REG,\n+\t\t\t\t\t\t  CSR_EEPROM_REG_READ_VALID_MSK,\n+\t\t\t\t\t\t  IWL_EEPROM_ACCESS_TIMEOUT);\n \t\t\tif (ret) {\n \t\t\t\tIWL_ERR(trans,\n \t\t\t\t\t\"Time out reading EEPROM[%d]\\n\", addr);\n \t\t\t\tgoto err_unlock;\n \t\t\t}\n-\t\t\tr = iwl_read32(trans, CSR_EEPROM_REG);\n+\t\t\tr = iwl_trans_read32(trans, CSR_EEPROM_REG);\n \t\t\te[addr / 2] = cpu_to_le16(r \u003e\u003e 16);\n \t\t}\n \t}\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/led.c b/drivers/net/wireless/intel/iwlwifi/dvm/led.c\nindex cec2ebdfd6519..17b045ddb910c 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/led.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/led.c\n@@ -2,7 +2,7 @@\n /******************************************************************************\n  *\n  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2019, 2025 Intel Corporation\n+ * Copyright (C) 2019, 2025-2026 Intel Corporation\n  *****************************************************************************/\n \n \n@@ -14,7 +14,6 @@\n #include \u003cnet/mac80211.h\u003e\n #include \u003clinux/etherdevice.h\u003e\n #include \u003clinux/unaligned.h\u003e\n-#include \"iwl-io.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-modparams.h\"\n #include \"dev.h\"\n@@ -49,7 +48,7 @@ static const struct ieee80211_tpt_blink iwl_blink[] = {\n /* Set led register off */\n void iwlagn_led_enable(struct iwl_priv *priv)\n {\n-\tiwl_write32(priv-\u003etrans, CSR_LED_REG, CSR_LED_REG_TURN_ON);\n+\tiwl_trans_write32(priv-\u003etrans, CSR_LED_REG, CSR_LED_REG_TURN_ON);\n }\n \n /*\n@@ -85,10 +84,10 @@ static int iwl_send_led_cmd(struct iwl_priv *priv, struct iwl_led_cmd *led_cmd)\n \t};\n \tu32 reg;\n \n-\treg = iwl_read32(priv-\u003etrans, CSR_LED_REG);\n+\treg = iwl_trans_read32(priv-\u003etrans, CSR_LED_REG);\n \tif (reg != (reg \u0026 CSR_LED_BSM_CTRL_MSK))\n-\t\tiwl_write32(priv-\u003etrans, CSR_LED_REG,\n-\t\t\t    reg \u0026 CSR_LED_BSM_CTRL_MSK);\n+\t\tiwl_trans_write32(priv-\u003etrans, CSR_LED_REG,\n+\t\t\t\t  reg \u0026 CSR_LED_BSM_CTRL_MSK);\n \n \treturn iwl_dvm_send_cmd(priv, \u0026cmd);\n }\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/lib.c b/drivers/net/wireless/intel/iwlwifi/dvm/lib.c\nindex 2e16799818e47..37d6f2cf7efb7 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/lib.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/lib.c\n@@ -2,6 +2,7 @@\n /******************************************************************************\n  *\n  * Copyright(c) 2008 - 2014, 2022 Intel Corporation. All rights reserved.\n+ * Copyright (C) 2026 Intel Corporation\n  *****************************************************************************/\n #include \u003clinux/etherdevice.h\u003e\n #include \u003clinux/kernel.h\u003e\n@@ -9,7 +10,6 @@\n #include \u003clinux/sched.h\u003e\n #include \u003cnet/mac80211.h\u003e\n \n-#include \"iwl-io.h\"\n #include \"iwl-agn-hw.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-modparams.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c\nindex a0a26ef482a5e..e83bf615c1617 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c\n@@ -2,7 +2,7 @@\n /******************************************************************************\n  *\n  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.\n- * Copyright(C) 2018 - 2019, 2022 - 2025 Intel Corporation\n+ * Copyright(C) 2018 - 2019, 2022 - 2026 Intel Corporation\n  *\n  * Portions of this file are derived from the ipw3945 project, as well\n  * as portions of the ieee80211 subsystem header files.\n@@ -23,7 +23,6 @@\n \n #include \u003casm/div64.h\u003e\n \n-#include \"iwl-io.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-op-mode.h\"\n #include \"iwl-modparams.h\"\n@@ -375,8 +374,8 @@ static int iwlagn_mac_suspend(struct ieee80211_hw *hw,\n \t\tgoto error;\n \n \t/* let the ucode operate on its own */\n-\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n-\t\t    CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);\n+\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n+\t\t\t  CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);\n \n \tiwl_trans_d3_suspend(priv-\u003etrans, true);\n \n@@ -455,8 +454,8 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)\n \t\tgoto out_unlock;\n \n \t/* uCode is no longer operating by itself */\n-\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t    CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);\n+\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t  CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);\n \n \tbase = priv-\u003edevice_pointers.error_event_table;\n \tif (!iwlagn_hw_valid_rtc_data_addr(base)) {\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/main.c b/drivers/net/wireless/intel/iwlwifi/dvm/main.c\nindex 6bd5b6d84b2a9..4bf69f7a35a64 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/main.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/main.c\n@@ -2,7 +2,7 @@\n /******************************************************************************\n  *\n  * Copyright(c) 2003 - 2014, 2018 - 2022 Intel Corporation. All rights reserved.\n- * Copyright(c) 2024-2025 Intel Corporation. All rights reserved.\n+ * Copyright(c) 2024-2026 Intel Corporation. All rights reserved.\n  * Copyright(c) 2015 Intel Deutschland GmbH\n  *\n  * Portions of this file are derived from the ipw3945 project, as well\n@@ -27,8 +27,8 @@\n #include \u003casm/div64.h\u003e\n \n #include \"iwl-nvm-utils.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-trans.h\"\n+#include \"iwl-devtrace.h\"\n #include \"iwl-op-mode.h\"\n #include \"iwl-drv.h\"\n #include \"iwl-modparams.h\"\n@@ -413,7 +413,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,\n \t\treturn;\n \n \t/* Set starting address; reads will auto-increment */\n-\tiwl_write32(priv-\u003etrans, HBUS_TARG_MEM_RADDR, ptr);\n+\tiwl_trans_write32(priv-\u003etrans, HBUS_TARG_MEM_RADDR, ptr);\n \n \t/*\n \t * Refuse to read more than would have fit into the log from\n@@ -429,13 +429,13 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,\n \t * place event id # at far right for easier visual parsing.\n \t */\n \tfor (i = 0; i \u003c num_events; i++) {\n-\t\tev = iwl_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n-\t\ttime = iwl_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n+\t\tev = iwl_trans_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n+\t\ttime = iwl_trans_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n \t\tif (mode == 0) {\n \t\t\ttrace_iwlwifi_dev_ucode_cont_event(\n \t\t\t\t\tpriv-\u003etrans-\u003edev, 0, time, ev);\n \t\t} else {\n-\t\t\tdata = iwl_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n+\t\t\tdata = iwl_trans_read32(priv-\u003etrans, HBUS_TARG_MEM_RDAT);\n \t\t\ttrace_iwlwifi_dev_ucode_cont_event(\n \t\t\t\t\tpriv-\u003etrans-\u003edev, time, data, ev);\n \t\t}\n@@ -661,8 +661,8 @@ static void iwl_rf_kill_ct_config(struct iwl_priv *priv)\n \tstruct iwl_ct_kill_throttling_config adv_cmd;\n \tint ret = 0;\n \n-\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t    CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n+\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t  CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n \n \tpriv-\u003ethermal_throttle.ct_kill_toggle = false;\n \n@@ -1731,13 +1731,13 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,\n \t\treturn pos;\n \n \t/* Set starting address; reads will auto-increment */\n-\tiwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);\n+\tiwl_trans_write32(trans, HBUS_TARG_MEM_RADDR, ptr);\n \n \t/* \"time\" is actually \"data\" for mode 0 (no timestamp).\n \t* place event id # at far right for easier visual parsing. */\n \tfor (i = 0; i \u003c num_events; i++) {\n-\t\tev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);\n-\t\ttime = iwl_read32(trans, HBUS_TARG_MEM_RDAT);\n+\t\tev = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);\n+\t\ttime = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);\n \t\tif (mode == 0) {\n \t\t\t/* data, ev */\n \t\t\tif (bufsz) {\n@@ -1751,7 +1751,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,\n \t\t\t\t\ttime, ev);\n \t\t\t}\n \t\t} else {\n-\t\t\tdata = iwl_read32(trans, HBUS_TARG_MEM_RDAT);\n+\t\t\tdata = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);\n \t\t\tif (bufsz) {\n \t\t\t\tpos += scnprintf(*buf + pos, bufsz - pos,\n \t\t\t\t\t\t\"EVT_LOGT:%010u:0x%08x:%04u\\n\",\n@@ -2028,17 +2028,17 @@ static void iwl_nic_config(struct iwl_op_mode *op_mode)\n \t}\n \n \t/* set CSR_HW_CONFIG_REG for uCode use */\n-\tiwl_set_bit(priv-\u003etrans, CSR_HW_IF_CONFIG_REG,\n-\t\t    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |\n-\t\t    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);\n+\tiwl_trans_set_bit(priv-\u003etrans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t  CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |\n+\t\t\t  CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);\n \n \t/* W/A : NIC is stuck in a reset state after Early PCIe power off\n \t * (PCIe power is lost before PERST# is asserted),\n \t * causing ME FW to lose ownership and not being able to obtain it back.\n \t */\n-\tiwl_set_bits_mask_prph(priv-\u003etrans, APMG_PS_CTRL_REG,\n-\t\t\t       APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,\n-\t\t\t       ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);\n+\tiwl_trans_set_bits_mask_prph(priv-\u003etrans, APMG_PS_CTRL_REG,\n+\t\t\t\t     APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,\n+\t\t\t\t     ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);\n \n \tif (priv-\u003elib-\u003enic_config)\n \t\tpriv-\u003elib-\u003enic_config(priv);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/power.c b/drivers/net/wireless/intel/iwlwifi/dvm/power.c\nindex e7dbba7134f72..4e19799d15d75 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/power.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/power.c\n@@ -2,7 +2,7 @@\n /******************************************************************************\n  *\n  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2019, 2025 Intel Corporation\n+ * Copyright (C) 2019, 2025-2026 Intel Corporation\n  *\n  * Portions of this file are derived from the ipw3945 project, as well\n  * as portions of the ieee80211 subsystem header files.\n@@ -13,7 +13,6 @@\n #include \u003clinux/module.h\u003e\n #include \u003clinux/slab.h\u003e\n #include \u003cnet/mac80211.h\u003e\n-#include \"iwl-io.h\"\n #include \"iwl-debug.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-modparams.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/rx.c b/drivers/net/wireless/intel/iwlwifi/dvm/rx.c\nindex 088302a238dec..fa2aff5bea6c0 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/rx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/rx.c\n@@ -3,7 +3,7 @@\n  *\n  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.\n  * Copyright(c) 2015 Intel Deutschland GmbH\n- * Copyright(c) 2018, 2020-2021, 2025 Intel Corporation\n+ * Copyright(c) 2018, 2020-2021, 2025-2026 Intel Corporation\n  *\n  * Portions of this file are derived from the ipw3945 project, as well\n  * as portionhelp of the ieee80211 subsystem header files.\n@@ -16,7 +16,6 @@\n #include \u003clinux/unaligned.h\u003e\n \n #include \"iwl-trans.h\"\n-#include \"iwl-io.h\"\n #include \"dev.h\"\n #include \"calib.h\"\n #include \"agn.h\"\n@@ -482,17 +481,17 @@ static void iwlagn_rx_card_state_notif(struct iwl_priv *priv,\n \tif (flags \u0026 (SW_CARD_DISABLED | HW_CARD_DISABLED |\n \t\t     CT_CARD_DISABLED)) {\n \n-\t\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n-\t\t\t    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n+\t\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n+\t\t\t\t  CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n \n-\t\tiwl_write_direct32(priv-\u003etrans, HBUS_TARG_MBX_C,\n-\t\t\t\t\tHBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);\n+\t\tiwl_trans_write_direct32(priv-\u003etrans, HBUS_TARG_MBX_C,\n+\t\t\t\t\t HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);\n \n \t\tif (!(flags \u0026 RXON_CARD_DISABLED)) {\n-\t\t\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t\t\t    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n-\t\t\tiwl_write_direct32(priv-\u003etrans, HBUS_TARG_MBX_C,\n-\t\t\t\t\tHBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);\n+\t\t\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t\t\t  CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n+\t\t\tiwl_trans_write_direct32(priv-\u003etrans, HBUS_TARG_MBX_C,\n+\t\t\t\t\t\t HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);\n \t\t}\n \t\tif (flags \u0026 CT_CARD_DISABLED)\n \t\t\tiwl_tt_enter_ct_kill(priv);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/tt.c b/drivers/net/wireless/intel/iwlwifi/dvm/tt.c\nindex fc9cf0531024a..a414eb7c24460 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/tt.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/tt.c\n@@ -2,7 +2,7 @@\n /******************************************************************************\n  *\n  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.\n- * Copyright (C) 2018, 2020 Intel Corporation\n+ * Copyright (C) 2018, 2020, 2026 Intel Corporation\n  *\n  * Portions of this file are derived from the ipw3945 project, as well\n  * as portions of the ieee80211 subsystem header files.\n@@ -13,7 +13,7 @@\n #include \u003clinux/module.h\u003e\n #include \u003clinux/slab.h\u003e\n #include \u003cnet/mac80211.h\u003e\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-modparams.h\"\n #include \"iwl-debug.h\"\n #include \"agn.h\"\n@@ -146,15 +146,15 @@ static void iwl_tt_check_exit_ct_kill(struct timer_list *t)\n \n \tif (tt-\u003estate == IWL_TI_CT_KILL) {\n \t\tif (priv-\u003ethermal_throttle.ct_kill_toggle) {\n-\t\t\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t\t\t    CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n+\t\t\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t\t\t  CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n \t\t\tpriv-\u003ethermal_throttle.ct_kill_toggle = false;\n \t\t} else {\n-\t\t\tiwl_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n-\t\t\t\t    CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n+\t\t\tiwl_trans_write32(priv-\u003etrans, CSR_UCODE_DRV_GP1_SET,\n+\t\t\t\t\t  CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);\n \t\t\tpriv-\u003ethermal_throttle.ct_kill_toggle = true;\n \t\t}\n-\t\tiwl_read32(priv-\u003etrans, CSR_UCODE_DRV_GP1);\n+\t\tiwl_trans_read32(priv-\u003etrans, CSR_UCODE_DRV_GP1);\n \t\tif (iwl_trans_grab_nic_access(priv-\u003etrans))\n \t\t\tiwl_trans_release_nic_access(priv-\u003etrans);\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/tx.c b/drivers/net/wireless/intel/iwlwifi/dvm/tx.c\nindex 1a0167f67c7bd..8dbc52971e7bb 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/tx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/tx.c\n@@ -3,14 +3,13 @@\n  *\n  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.\n  * Copyright (C) 2019 Intel Corporation\n- * Copyright (C) 2023, 2025 Intel Corporation\n+ * Copyright (C) 2023, 2025-2026 Intel Corporation\n  *****************************************************************************/\n \n #include \u003clinux/kernel.h\u003e\n #include \u003clinux/module.h\u003e\n #include \u003clinux/sched.h\u003e\n #include \u003clinux/ieee80211.h\u003e\n-#include \"iwl-io.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-agn-hw.h\"\n #include \"dev.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c b/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c\nindex ac90191a39735..2ab1a32d774e5 100644\n--- a/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c\n+++ b/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c\n@@ -3,12 +3,11 @@\n  *\n  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.\n  * Copyright(c) 2015 Intel Deutschland GmbH\n- * Copyright (C) 2025 Intel Corporation\n+ * Copyright (C) 2025-2026 Intel Corporation\n  *****************************************************************************/\n \n #include \u003clinux/kernel.h\u003e\n \n-#include \"iwl-io.h\"\n #include \"iwl-agn-hw.h\"\n #include \"iwl-trans.h\"\n #include \"iwl-fh.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h\nindex d3bed0216df48..9f7407c4f980c 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h\n@@ -1,6 +1,6 @@\n /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n /*\n- * Copyright (C) 2012-2014, 2018-2025 Intel Corporation\n+ * Copyright (C) 2012-2014, 2018-2026 Intel Corporation\n  * Copyright (C) 2013-2014 Intel Mobile Communications GmbH\n  * Copyright (C) 2015-2017 Intel Deutschland GmbH\n  */\n@@ -366,7 +366,6 @@ enum iwl_wowlan_flags {\n \tENABLE_L3_FILTERING\t= BIT(1),\n \tENABLE_NBNS_FILTERING\t= BIT(2),\n \tENABLE_DHCP_FILTERING\t= BIT(3),\n-\tENABLE_STORE_BEACON\t= BIT(4),\n \tHAS_BEACON_PROTECTION\t= BIT(5),\n };\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h\nindex 31d3336726b42..9d9eb320db7b0 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h\n@@ -1,6 +1,6 @@\n /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n /*\n- * Copyright (C) 2012-2014, 2018-2025 Intel Corporation\n+ * Copyright (C) 2012-2014, 2018-2026 Intel Corporation\n  * Copyright (C) 2016-2017 Intel Deutschland GmbH\n  */\n #ifndef __iwl_fw_api_tx_h__\n@@ -292,6 +292,9 @@ struct iwl_tx_cmd_v9 {\n  * @dram_info: FW internal DRAM storage\n  * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is\n  *\tcleared. Combination of RATE_MCS_*; format depends on version\n+ * @driver_timestamp: gp2 time, in microseconds, assigned before queueing the\n+ *\tMPDU. Firmware uses it to detect frames blocked for too long.\n+ *\tZero means no timestamp. Used from TX_CMD_API_S_VER_12.\n  * @reserved: reserved\n  * @hdr: 802.11 header\n  */\n@@ -301,10 +304,12 @@ struct iwl_tx_cmd {\n \t__le32 offload_assist;\n \tstruct iwl_dram_sec_info dram_info;\n \t__le32 rate_n_flags;\n-\tu8 reserved[8];\n+\t__le32 driver_timestamp;\n+\tu8 reserved[4];\n \tstruct ieee80211_hdr hdr[];\n } __packed; /* TX_CMD_API_S_VER_10,\n-\t     * TX_CMD_API_S_VER_11\n+\t     * TX_CMD_API_S_VER_11,\n+\t     * TX_CMD_API_S_VER_12\n \t     */\n \n /*\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c\nindex 19b1bfd0abee4..09c798d2eba33 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c\n@@ -9,7 +9,7 @@\n #include \"runtime.h\"\n #include \"dbg.h\"\n #include \"debugfs.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"iwl-fh.h\"\n@@ -47,8 +47,8 @@ static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,\n \t\tu32 rd_cmd = RADIO_RSP_RD_CMD;\n \n \t\trd_cmd |= i \u003c\u003c RADIO_RSP_ADDR_POS;\n-\t\tiwl_trans_write_prph(fwrt-\u003etrans, RSP_RADIO_CMD, rd_cmd);\n-\t\t*pos = (u8)iwl_trans_read_prph(fwrt-\u003etrans, RSP_RADIO_RDDAT);\n+\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RSP_RADIO_CMD, rd_cmd);\n+\t\t*pos = (u8)iwl_trans_read_prph_no_grab(fwrt-\u003etrans, RSP_RADIO_RDDAT);\n \n \t\tpos++;\n \t}\n@@ -81,35 +81,35 @@ static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,\n \n \tfifo_hdr-\u003efifo_num = cpu_to_le32(fifo_num);\n \tfifo_hdr-\u003eavailable_bytes =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_RD_D_SPACE + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_RD_D_SPACE + offset));\n \tfifo_hdr-\u003ewr_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_RD_WR_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_RD_WR_PTR + offset));\n \tfifo_hdr-\u003erd_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_RD_RD_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_RD_RD_PTR + offset));\n \tfifo_hdr-\u003efence_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_RD_FENCE_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_RD_FENCE_PTR + offset));\n \tfifo_hdr-\u003efence_mode =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tRXF_SET_FENCE_MODE + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tRXF_SET_FENCE_MODE + offset));\n \n \t/* Lock fence */\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_SET_FENCE_MODE + offset, 0x1);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_SET_FENCE_MODE + offset, 0x1);\n \t/* Set fence pointer to the same place like WR pointer */\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_LD_WR2FENCE + offset, 0x1);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_LD_WR2FENCE + offset, 0x1);\n \t/* Set fence offset */\n-\tiwl_trans_write_prph(fwrt-\u003etrans,\n-\t\t\t     RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t     RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);\n \n \t/* Read FIFO */\n \tfifo_len /= sizeof(u32); /* Size in DWORDS */\n \tfor (i = 0; i \u003c fifo_len; i++)\n-\t\tfifo_data[i] = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t RXF_FIFO_RD_FENCE_INC +\n-\t\t\t\t\t\t offset);\n+\t\tfifo_data[i] = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t   RXF_FIFO_RD_FENCE_INC +\n+\t\t\t\t\t\t\t   offset);\n \t*dump_data = iwl_fw_error_next_data(*dump_data);\n }\n \n@@ -136,33 +136,33 @@ static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,\n \n \tfifo_hdr-\u003efifo_num = cpu_to_le32(fifo_num);\n \tfifo_hdr-\u003eavailable_bytes =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_FIFO_ITEM_CNT + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_FIFO_ITEM_CNT + offset));\n \tfifo_hdr-\u003ewr_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_WR_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_WR_PTR + offset));\n \tfifo_hdr-\u003erd_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_RD_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_RD_PTR + offset));\n \tfifo_hdr-\u003efence_ptr =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_FENCE_PTR + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_FENCE_PTR + offset));\n \tfifo_hdr-\u003efence_mode =\n-\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\tTXF_LOCK_FENCE + offset));\n+\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\tTXF_LOCK_FENCE + offset));\n \n \t/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */\n-\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_READ_MODIFY_ADDR + offset,\n-\t\t\t     TXF_WR_PTR + offset);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_READ_MODIFY_ADDR + offset,\n+\t\t\t\t     TXF_WR_PTR + offset);\n \n \t/* Dummy-read to advance the read pointer to the head */\n-\tiwl_trans_read_prph(fwrt-\u003etrans, TXF_READ_MODIFY_DATA + offset);\n+\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans, TXF_READ_MODIFY_DATA + offset);\n \n \t/* Read FIFO */\n \tfor (i = 0; i \u003c fifo_len / sizeof(u32); i++)\n-\t\tfifo_data[i] = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t  TXF_READ_MODIFY_DATA +\n-\t\t\t\t\t\t  offset);\n+\t\tfifo_data[i] = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t   TXF_READ_MODIFY_DATA +\n+\t\t\t\t\t\t\t   offset);\n \n \tif (fwrt-\u003esanitize_ops \u0026\u0026 fwrt-\u003esanitize_ops-\u003efrob_txf)\n \t\tfwrt-\u003esanitize_ops-\u003efrob_txf(fwrt-\u003esanitize_ctx,\n@@ -217,7 +217,7 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,\n \t\t/* Pull TXF data from LMAC1 */\n \t\tfor (i = 0; i \u003c fwrt-\u003esmem_cfg.num_txfifo_entries; i++) {\n \t\t\t/* Mark the number of TXF we're pulling now */\n-\t\t\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_LARC_NUM, i);\n+\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_LARC_NUM, i);\n \t\t\tiwl_fwrt_dump_txf(fwrt, dump_data,\n \t\t\t\t\t  cfg-\u003elmac[0].txfifo_size[i], 0, i);\n \t\t}\n@@ -227,9 +227,9 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,\n \t\t\tfor (i = 0; i \u003c fwrt-\u003esmem_cfg.num_txfifo_entries;\n \t\t\t     i++) {\n \t\t\t\t/* Mark the number of TXF we're pulling now */\n-\t\t\t\tiwl_trans_write_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t     TXF_LARC_NUM +\n-\t\t\t\t\t\t     LMAC2_PRPH_OFFSET, i);\n+\t\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t     TXF_LARC_NUM +\n+\t\t\t\t\t\t\t     LMAC2_PRPH_OFFSET, i);\n \t\t\t\tiwl_fwrt_dump_txf(fwrt, dump_data,\n \t\t\t\t\t\t  cfg-\u003elmac[1].txfifo_size[i],\n \t\t\t\t\t\t  LMAC2_PRPH_OFFSET,\n@@ -262,40 +262,40 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,\n \t\t\tfifo_hdr-\u003efifo_num = cpu_to_le32(i);\n \n \t\t\t/* Mark the number of TXF we're pulling now */\n-\t\t\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_CPU2_NUM, i +\n-\t\t\t\tfwrt-\u003esmem_cfg.num_txfifo_entries);\n+\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_CPU2_NUM, i +\n+\t\t\t\t\t\t     fwrt-\u003esmem_cfg.num_txfifo_entries);\n \n \t\t\tfifo_hdr-\u003eavailable_bytes =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_FIFO_ITEM_CNT));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_FIFO_ITEM_CNT));\n \t\t\tfifo_hdr-\u003ewr_ptr =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_WR_PTR));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_WR_PTR));\n \t\t\tfifo_hdr-\u003erd_ptr =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_RD_PTR));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_RD_PTR));\n \t\t\tfifo_hdr-\u003efence_ptr =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_FENCE_PTR));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_FENCE_PTR));\n \t\t\tfifo_hdr-\u003efence_mode =\n-\t\t\t\tcpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\tTXF_CPU2_LOCK_FENCE));\n+\t\t\t\tcpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\tTXF_CPU2_LOCK_FENCE));\n \n \t\t\t/* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */\n-\t\t\tiwl_trans_write_prph(fwrt-\u003etrans,\n-\t\t\t\t\t     TXF_CPU2_READ_MODIFY_ADDR,\n-\t\t\t\t\t     TXF_CPU2_WR_PTR);\n+\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t     TXF_CPU2_READ_MODIFY_ADDR,\n+\t\t\t\t\t\t     TXF_CPU2_WR_PTR);\n \n \t\t\t/* Dummy-read to advance the read pointer to head */\n-\t\t\tiwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t    TXF_CPU2_READ_MODIFY_DATA);\n+\t\t\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t    TXF_CPU2_READ_MODIFY_DATA);\n \n \t\t\t/* Read FIFO */\n \t\t\tfifo_len /= sizeof(u32); /* Size in DWORDS */\n \t\t\tfor (j = 0; j \u003c fifo_len; j++)\n \t\t\t\tfifo_data[j] =\n-\t\t\t\t\tiwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t    TXF_CPU2_READ_MODIFY_DATA);\n+\t\t\t\t\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t    TXF_CPU2_READ_MODIFY_DATA);\n \t\t\t*dump_data = iwl_fw_error_next_data(*dump_data);\n \t\t}\n \t}\n@@ -514,7 +514,7 @@ static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,\n \tu32 i;\n \n \tfor (i = 0; i \u003c len_bytes; i += 4)\n-\t\t*data++ = cpu_to_le32(iwl_trans_read_prph(trans, start + i));\n+\t\t*data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(trans, start + i));\n }\n \n static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c\nindex 897538066b7de..1d34ad59bb71f 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c\n@@ -9,7 +9,7 @@\n #include \"runtime.h\"\n #include \"dbg.h\"\n #include \"debugfs.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"iwl-fh.h\"\n@@ -103,7 +103,7 @@ static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt,\n \trange-\u003einternal_base_addr = cpu_to_le32(addr);\n \trange-\u003erange_data_size = size;\n \tfor (i = 0; i \u003c le32_to_cpu(size); i += 4)\n-\t\t*val++ = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans, addr + i));\n+\t\t*val++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans, addr + i));\n \n \treturn sizeof(*range) + le32_to_cpu(range-\u003erange_data_size);\n }\n@@ -159,7 +159,7 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt,\n \tindirect_rd_addr += le32_to_cpu(offset);\n \n \tdphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;\n-\tdphy_state = iwl_read_umac_prph_no_grab(fwrt-\u003etrans, dphy_addr);\n+\tdphy_state = iwl_trans_read_umac_prph_no_grab(fwrt-\u003etrans, dphy_addr);\n \n \tfor (i = 0; i \u003c le32_to_cpu(size); i += 4) {\n \t\tif (dphy_state == HBUS_TIMEOUT ||\n@@ -169,16 +169,16 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt,\n \t\t\tcontinue;\n \t\t}\n \n-\t\tiwl_trans_write_prph(fwrt-\u003etrans, indirect_wr_addr,\n-\t\t\t\t     WMAL_INDRCT_CMD(addr + i));\n+\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, indirect_wr_addr,\n+\t\t\t\t\t     WMAL_INDRCT_CMD(addr + i));\n \n \t\tif (fwrt-\u003etrans-\u003einfo.hw_rf_id != IWL_CFG_RF_TYPE_JF1 \u0026\u0026\n \t\t    fwrt-\u003etrans-\u003einfo.hw_rf_id != IWL_CFG_RF_TYPE_JF2 \u0026\u0026\n \t\t    fwrt-\u003etrans-\u003einfo.hw_rf_id != IWL_CFG_RF_TYPE_HR1 \u0026\u0026\n \t\t    fwrt-\u003etrans-\u003einfo.hw_rf_id != IWL_CFG_RF_TYPE_HR2) {\n \t\t\tudelay(2);\n-\t\t\tprph_stts = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\tWMAL_MRSPF_STTS);\n+\t\t\tprph_stts = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\tWMAL_MRSPF_STTS);\n \n \t\t\t/* Abort dump if status is 0xA5A5A5A2 or FIFO1 empty */\n \t\t\tif (prph_stts == WMAL_TIMEOUT_VAL ||\n@@ -186,8 +186,8 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt,\n \t\t\t\tbreak;\n \t\t}\n \n-\t\tprph_val = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t       indirect_rd_addr);\n+\t\tprph_val = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t       indirect_rd_addr);\n \t\t*val++ = cpu_to_le32(prph_val);\n \t}\n \n@@ -446,7 +446,7 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,\n \trange-\u003efifo_hdr.num_of_registers = cpu_to_le32(registers_num);\n \trange-\u003erange_data_size = cpu_to_le32(iter-\u003efifo_size + registers_size);\n \n-\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_LARC_NUM + offs, iter-\u003efifo);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_LARC_NUM + offs, iter-\u003efifo);\n \n \t/*\n \t * read txf registers. for each register, write to the dump the\n@@ -456,8 +456,8 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,\n \t\taddr = le32_to_cpu(reg-\u003eaddrs[i]) + offs;\n \n \t\treg_dump-\u003eaddr = cpu_to_le32(addr);\n-\t\treg_dump-\u003edata = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\t addr));\n+\t\treg_dump-\u003edata = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\t addr));\n \n \t\treg_dump++;\n \t}\n@@ -468,17 +468,17 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,\n \t}\n \n \t/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */\n-\tiwl_trans_write_prph(fwrt-\u003etrans, TXF_READ_MODIFY_ADDR + offs,\n-\t\t\t     TXF_WR_PTR + offs);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, TXF_READ_MODIFY_ADDR + offs,\n+\t\t\t\t     TXF_WR_PTR + offs);\n \n \t/* Dummy-read to advance the read pointer to the head */\n-\tiwl_trans_read_prph(fwrt-\u003etrans, TXF_READ_MODIFY_DATA + offs);\n+\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans, TXF_READ_MODIFY_DATA + offs);\n \n \t/* Read FIFO */\n \taddr = TXF_READ_MODIFY_DATA + offs;\n \tdata = (void *)reg_dump;\n \tfor (i = 0; i \u003c iter-\u003efifo_size; i += sizeof(*data))\n-\t\t*data++ = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans, addr));\n+\t\t*data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans, addr));\n \n \tif (fwrt-\u003esanitize_ops \u0026\u0026 fwrt-\u003esanitize_ops-\u003efrob_txf)\n \t\tfwrt-\u003esanitize_ops-\u003efrob_txf(fwrt-\u003esanitize_ctx,\n@@ -508,7 +508,7 @@ iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt,\n \tindirect_rd_wr_addr += le32_to_cpu(offset);\n \n \tdphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;\n-\tdphy_state = iwl_read_umac_prph_no_grab(fwrt-\u003etrans, dphy_addr);\n+\tdphy_state = iwl_trans_read_umac_prph_no_grab(fwrt-\u003etrans, dphy_addr);\n \n \tfor (i = 0; i \u003c le32_to_cpu(reg-\u003edev_addr.size); i += 4) {\n \t\tif (dphy_state == HBUS_TIMEOUT ||\n@@ -518,12 +518,12 @@ iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt,\n \t\t\tcontinue;\n \t\t}\n \n-\t\tiwl_trans_write_prph(fwrt-\u003etrans, indirect_rd_wr_addr,\n-\t\t\t\t     addr + i);\n+\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, indirect_rd_wr_addr,\n+\t\t\t\t\t     addr + i);\n \t\t/* wait a bit for value to be ready in register */\n \t\tudelay(1);\n-\t\tprph_val = iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t       indirect_rd_wr_addr);\n+\t\tprph_val = iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t       indirect_rd_wr_addr);\n \t\t*val++ = cpu_to_le32((prph_val \u0026 DPHYIP_INDIRECT_RD_MSK) \u003e\u003e\n \t\t\t\t     DPHYIP_INDIRECT_RD_SHIFT);\n \t}\n@@ -586,13 +586,13 @@ static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,\n \t\tswitch (fifo_idx) {\n \t\tcase 0:\n \t\t\tdata-\u003esize = fwrt-\u003esmem_cfg.rxfifo2_size;\n-\t\t\tdata-\u003eoffset = iwl_umac_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t     RXF_DIFF_FROM_PREV);\n+\t\t\tdata-\u003eoffset = iwl_trans_umac_prph(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t   RXF_DIFF_FROM_PREV);\n \t\t\tbreak;\n \t\tcase 1:\n \t\t\tdata-\u003esize = fwrt-\u003esmem_cfg.rxfifo2_control_size;\n-\t\t\tdata-\u003eoffset = iwl_umac_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t     RXF2C_DIFF_FROM_PREV);\n+\t\t\tdata-\u003eoffset = iwl_trans_umac_prph(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t   RXF2C_DIFF_FROM_PREV);\n \t\t\tbreak;\n \t\t}\n \t}\n@@ -628,8 +628,8 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,\n \t\taddr = le32_to_cpu(reg-\u003eaddrs[i]) + offs;\n \n \t\treg_dump-\u003eaddr = cpu_to_le32(addr);\n-\t\treg_dump-\u003edata = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t\t\t\t addr));\n+\t\treg_dump-\u003edata = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t\t\t addr));\n \n \t\treg_dump++;\n \t}\n@@ -642,17 +642,17 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,\n \toffs = rxf_data.offset;\n \n \t/* Lock fence */\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_SET_FENCE_MODE + offs, 0x1);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_SET_FENCE_MODE + offs, 0x1);\n \t/* Set fence pointer to the same place like WR pointer */\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_LD_WR2FENCE + offs, 0x1);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_LD_WR2FENCE + offs, 0x1);\n \t/* Set fence offset */\n-\tiwl_trans_write_prph(fwrt-\u003etrans, RXF_LD_FENCE_OFFSET_ADDR + offs, 0x0);\n+\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, RXF_LD_FENCE_OFFSET_ADDR + offs, 0x0);\n \n \t/* Read FIFO */\n \taddr =  RXF_FIFO_RD_FENCE_INC + offs;\n \tdata = (void *)reg_dump;\n \tfor (i = 0; i \u003c rxf_data.size; i += sizeof(*data))\n-\t\t*data++ = cpu_to_le32(iwl_trans_read_prph(fwrt-\u003etrans, addr));\n+\t\t*data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt-\u003etrans, addr));\n \n out:\n \treturn sizeof(*range) + le32_to_cpu(range-\u003erange_data_size);\n@@ -712,10 +712,10 @@ iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,\n \trange-\u003erange_data_size = reg-\u003edev_addr.size;\n \tfor (i = 0; i \u003c (le32_to_cpu(reg-\u003edev_addr.size) / 4); i++) {\n \t\tprph_data =\n-\t\t\tiwl_trans_read_prph(fwrt-\u003etrans,\n-\t\t\t\t\t    (i % 2) ?\n-\t\t\t\t\t\tDBGI_SRAM_TARGET_ACCESS_RDATA_MSB :\n-\t\t\t\t\t\tDBGI_SRAM_TARGET_ACCESS_RDATA_LSB);\n+\t\t\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t    (i % 2) ?\n+\t\t\t\t\t\t        DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :\n+\t\t\t\t\t\t        DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);\n \t\tif (iwl_trans_is_hw_error_value(prph_data))\n \t\t\treturn -EBUSY;\n \t\t*val++ = cpu_to_le32(prph_data);\n@@ -812,7 +812,7 @@ static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id,\n \tif (!reg_info || !reg_info-\u003eaddr || !reg_info-\u003emask)\n \t\treturn 0;\n \n-\tval = iwl_trans_read_prph(fwrt-\u003etrans, reg_info-\u003eaddr + offs);\n+\tval = iwl_trans_read_prph_no_grab(fwrt-\u003etrans, reg_info-\u003eaddr + offs);\n \n \treturn cpu_to_le32(mask_apply_and_normalize(val, reg_info-\u003emask));\n }\n@@ -1820,14 +1820,14 @@ static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,\n \t\t\tcpu_to_le32(IWL_FW_INI_APPLY_POLICY_SPLIT_DUMP_RESET)) {\n \t\tsize += iwl_dump_ini_dump_entries(fwrt, list,\n \t\t\t\t\t\t  IWL_INI_DUMP_EARLY_REGIONS);\n-\t\tiwl_trans_pcie_fw_reset_handshake(fwrt-\u003etrans);\n+\t\tiwl_trans_fw_reset_handshake(fwrt-\u003etrans);\n \t\tsize += iwl_dump_ini_dump_entries(fwrt, list,\n \t\t\t\t\t\t  IWL_INI_DUMP_LATE_REGIONS);\n \t} else {\n \t\tif (fw_has_capa(\u0026fwrt-\u003efw-\u003eucode_capa,\n \t\t\t\tIWL_UCODE_TLV_CAPA_RESET_DURING_ASSERT) \u0026\u0026\n \t\t    iwl_dump_due_to_error(tp_id))\n-\t\t\tiwl_trans_pcie_fw_reset_handshake(fwrt-\u003etrans);\n+\t\t\tiwl_trans_fw_reset_handshake(fwrt-\u003etrans);\n \t\tsize += iwl_dump_ini_dump_entries(fwrt, list,\n \t\t\t\t\t\t  IWL_INI_DUMP_ALL_REGIONS);\n \t}\n@@ -2381,21 +2381,21 @@ static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans,\n \t\t\t\t      struct iwl_fw_dbg_params *params)\n {\n \tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_7000) {\n-\t\tiwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);\n+\t\tiwl_trans_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);\n \t\treturn;\n \t}\n \n \tif (params) {\n-\t\tparams-\u003ein_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);\n-\t\tparams-\u003eout_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);\n+\t\tparams-\u003ein_sample = iwl_trans_read_umac_prph(trans, DBGC_IN_SAMPLE);\n+\t\tparams-\u003eout_ctrl = iwl_trans_read_umac_prph(trans, DBGC_OUT_CTRL);\n \t}\n \n-\tiwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);\n+\tiwl_trans_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);\n \t/* wait for the DBGC to finish writing the internal buffer to DRAM to\n \t * avoid halting the HW while writing\n \t */\n \tusleep_range(700, 1000);\n-\tiwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);\n+\tiwl_trans_write_umac_prph(trans, DBGC_OUT_CTRL, 0);\n }\n \n static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,\n@@ -2405,12 +2405,12 @@ static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,\n \t\treturn -EIO;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_7000) {\n-\t\tiwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);\n-\t\tiwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);\n-\t\tiwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);\n+\t\tiwl_trans_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);\n+\t\tiwl_trans_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);\n+\t\tiwl_trans_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);\n \t} else {\n-\t\tiwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params-\u003ein_sample);\n-\t\tiwl_write_umac_prph(trans, DBGC_OUT_CTRL, params-\u003eout_ctrl);\n+\t\tiwl_trans_write_umac_prph(trans, DBGC_IN_SAMPLE, params-\u003ein_sample);\n+\t\tiwl_trans_write_umac_prph(trans, DBGC_OUT_CTRL, params-\u003eout_ctrl);\n \t}\n \n \treturn 0;\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h\nindex fc962a3205833..70134d8f03c4d 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h\n@@ -10,7 +10,7 @@\n #include \u003cnet/cfg80211.h\u003e\n #include \"runtime.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"file.h\"\n #include \"error-dump.h\"\n #include \"api/commands.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/dump.c b/drivers/net/wireless/intel/iwlwifi/fw/dump.c\nindex bbbf3669a555d..b76abc77f4959 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/dump.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/dump.c\n@@ -9,7 +9,7 @@\n #include \"runtime.h\"\n #include \"dbg.h\"\n #include \"debugfs.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"pnvm.h\"\n@@ -309,7 +309,7 @@ static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime *fwrt)\n \t\treturn;\n \t}\n \n-\terror = iwl_read_umac_prph(trans, error);\n+\terror = iwl_trans_read_umac_prph(trans, error);\n \n \tIWL_ERR(trans, \"IML/ROM dump:\\n\");\n \n@@ -318,11 +318,11 @@ static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime *fwrt)\n \n \tIWL_ERR(fwrt, \"0x%08X | IML/ROM error/state\\n\", error);\n \tIWL_ERR(fwrt, \"0x%08X | IML/ROM data1\\n\",\n-\t\tiwl_read_umac_prph(trans, data1));\n+\t\tiwl_trans_read_umac_prph(trans, data1));\n \n \tif (fwrt-\u003etrans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_22000)\n \t\tIWL_ERR(fwrt, \"0x%08X | IML/ROM WFPM_AUTH_KEY_0\\n\",\n-\t\t\tiwl_read_umac_prph(trans, SB_MODIFY_CFG_FLAG));\n+\t\t\tiwl_trans_read_umac_prph(trans, SB_MODIFY_CFG_FLAG));\n }\n \n #define FSEQ_REG(x) { .addr = (x), .str = #x, }\n@@ -360,7 +360,7 @@ static void iwl_fwrt_dump_fseq_regs(struct iwl_fw_runtime *fwrt)\n \n \tfor (i = 0; i \u003c ARRAY_SIZE(fseq_regs); i++)\n \t\tIWL_ERR(fwrt, \"0x%08X | %s\\n\",\n-\t\t\tiwl_read_prph_no_grab(trans, fseq_regs[i].addr),\n+\t\t\tiwl_trans_read_prph_no_grab(trans, fseq_regs[i].addr),\n \t\t\tfseq_regs[i].str);\n \n \tiwl_trans_release_nic_access(trans);\n@@ -398,13 +398,13 @@ void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime *fwrt)\n \t\t     count++, pc_data++)\n \t\t\tIWL_ERR(fwrt, \"%s: 0x%x\\n\",\n \t\t\t\tpc_data-\u003epc_name,\n-\t\t\t\tiwl_read_prph_no_grab(fwrt-\u003etrans,\n-\t\t\t\t\t\t      pc_data-\u003epc_address));\n+\t\t\t\tiwl_trans_read_prph_no_grab(fwrt-\u003etrans,\n+\t\t\t\t\t\t\t    pc_data-\u003epc_address));\n \t\tiwl_trans_release_nic_access(fwrt-\u003etrans);\n \t}\n \n \tif (fwrt-\u003etrans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tu32 scratch = iwl_read32(fwrt-\u003etrans, CSR_FUNC_SCRATCH);\n+\t\tu32 scratch = iwl_trans_read32(fwrt-\u003etrans, CSR_FUNC_SCRATCH);\n \n \t\tIWL_ERR(fwrt, \"Function Scratch status:\\n\");\n \t\tIWL_ERR(fwrt, \"0x%08X | Func Scratch\\n\", scratch);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c\nindex 545a213df71d2..ccd190ab8a552 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c\n@@ -6,7 +6,7 @@\n #include \"iwl-drv.h\"\n #include \"pnvm.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"fw/api/commands.h\"\n #include \"fw/api/nvm-reg.h\"\n #include \"fw/api/alive.h\"\n@@ -485,8 +485,8 @@ int iwl_pnvm_load(struct iwl_trans *trans,\n \t\t\t\t   iwl_pnvm_complete_fn, trans);\n \n \t/* kick the doorbell */\n-\tiwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n-\t\t\t    UREG_DOORBELL_TO_ISR6_PNVM);\n+\tiwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n+\t\t\t\t  UREG_DOORBELL_TO_ISR6_PNVM);\n \n \treturn iwl_wait_notification(notif_wait, \u0026pnvm_wait,\n \t\t\t\t     MVM_UCODE_PNVM_TIMEOUT);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c\nindex dffd5e68f41da..89a0f722cad94 100644\n--- a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c\n+++ b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c\n@@ -6,7 +6,7 @@\n #include \"iwl-drv.h\"\n #include \"pnvm.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n \n #include \"fw/uefi.h\"\n #include \"fw/api/alive.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h\nindex d2fa80a3dd040..11f2b31f6df7e 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h\n@@ -14,9 +14,9 @@\n  * low power states due to driver-invoked device resets\n  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.\n  *\n- * Use iwl_write32() and iwl_read32() family to access these registers;\n+ * Use iwl_trans_write32() and iwl_trans_read32() family to access these registers;\n  * these provide simple PCI bus access, without waking up the MAC.\n- * Do not use iwl_write_direct32() family for these registers;\n+ * Do not use iwl_trans_write_direct32() family for these registers;\n  * no need to \"grab nic access\" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.\n  * The MAC (uCode processor, etc.) does not need to be powered up for accessing\n  * the CSR registers.\n@@ -36,7 +36,7 @@\n #define CSR_GP_CNTRL            (CSR_BASE+0x024)\n #define CSR_FUNC_SCRATCH        (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */\n \n-/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */\n+/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_trans_write32()! */\n #define CSR_INT_PERIODIC_REG\t(CSR_BASE+0x005)\n \n /*\n@@ -474,7 +474,7 @@ enum {\n  * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and\n  * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.\n  *\n- * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW\n+ * Use iwl_trans_write32()/iwl_trans_read32() family to access these registers. The MAC HW\n  * need not be powered up so no \"grab inc access\" is required.\n  */\n \n@@ -501,12 +501,13 @@ enum {\n  * to indirectly access device's internal memory or registers that\n  * may be powered-down.\n  *\n- * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;\n+ * Use iwl_trans_write_direct32() family for writing to these registers;\n+ * A read operation doesn't exist, can be added if needed.\n  * host must \"grab nic access\" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ\n  * to make sure the MAC (uCode processor, etc.) is powered up for accessing\n  * internal resources.\n  *\n- * Do not use iwl_write32()/iwl_read32() family to access these registers;\n+ * Do not use iwl_trans_write32()/iwl_trans_read32() family to access these registers;\n  * these provide only simple PCI bus access, without waking up the MAC.\n  */\n #define HBUS_BASE\t(0x400)\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c\nindex 4372a171172b0..cc6044222b5cf 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c\n@@ -912,7 +912,7 @@ static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,\n \t\t\tfor (count = 0; count \u003c len; count++) {\n \t\t\t\taddress = le32_to_cpu(config_list-\u003eaddr_val[count].address);\n \t\t\t\tvalue = le32_to_cpu(config_list-\u003eaddr_val[count].value);\n-\t\t\t\tiwl_trans_write_prph(fwrt-\u003etrans, address + offset, value);\n+\t\t\t\tiwl_trans_write_prph_no_grab(fwrt-\u003etrans, address + offset, value);\n \t\t\t}\n \t\t\tiwl_trans_release_nic_access(fwrt-\u003etrans);\n \t\tbreak;\n@@ -931,7 +931,7 @@ static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,\n \t\t\tfor (count = 0; count \u003c len; count++) {\n \t\t\t\taddress = le32_to_cpu(config_list-\u003eaddr_val[count].address);\n \t\t\t\tvalue = le32_to_cpu(config_list-\u003eaddr_val[count].value);\n-\t\t\t\tiwl_write32(fwrt-\u003etrans, address + offset, value);\n+\t\t\t\tiwl_trans_write32(fwrt-\u003etrans, address + offset, value);\n \t\t\t\tIWL_DEBUG_FW(fwrt, \"WRT: CSR: count %u, add: %u val: %u\\n\",\n \t\t\t\t\t     count, address, value);\n \t\t\t}\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h b/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h\nindex 0af9d8362c5b8..a0cc401198908 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h\n@@ -3,6 +3,7 @@\n  *\n  * Copyright(c) 2009 - 2014 Intel Corporation. All rights reserved.\n  * Copyright(c) 2016-2017 Intel Deutschland GmbH\n+ * Copyright (C) 2026 Intel Corporation\n  *****************************************************************************/\n \n #if !defined(__IWLWIFI_DEVICE_TRACE_IO) || defined(TRACE_HEADER_MULTI_READ)\n@@ -65,23 +66,6 @@ TRACE_EVENT(iwlwifi_dev_iowrite32,\n \t\t  __get_str(dev), __entry-\u003eoffs, __entry-\u003eval)\n );\n \n-TRACE_EVENT(iwlwifi_dev_iowrite64,\n-\tTP_PROTO(const struct device *dev, u64 offs, u64 val),\n-\tTP_ARGS(dev, offs, val),\n-\tTP_STRUCT__entry(\n-\t\tDEV_ENTRY\n-\t\t__field(u64, offs)\n-\t\t__field(u64, val)\n-\t),\n-\tTP_fast_assign(\n-\t\tDEV_ASSIGN;\n-\t\t__entry-\u003eoffs = offs;\n-\t\t__entry-\u003eval = val;\n-\t),\n-\tTP_printk(\"[%s] write io[%llu] = %llu)\",\n-\t\t  __get_str(dev), __entry-\u003eoffs, __entry-\u003eval)\n-);\n-\n TRACE_EVENT(iwlwifi_dev_iowrite_prph32,\n \tTP_PROTO(const struct device *dev, u32 offs, u32 val),\n \tTP_ARGS(dev, offs, val),\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.c b/drivers/net/wireless/intel/iwlwifi/iwl-io.c\ndeleted file mode 100644\nindex cc6bf4ea5055d..0000000000000\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-io.c\n+++ /dev/null\n@@ -1,217 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n-/*\n- * Copyright (C) 2003-2014, 2018-2022, 2024-2026 Intel Corporation\n- * Copyright (C) 2015-2016 Intel Deutschland GmbH\n- */\n-#include \u003clinux/device.h\u003e\n-#include \u003clinux/export.h\u003e\n-\n-#include \"iwl-drv.h\"\n-#include \"iwl-io.h\"\n-#include \"iwl-csr.h\"\n-#include \"iwl-debug.h\"\n-\n-void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite8(trans-\u003edev, ofs, val);\n-\tiwl_trans_write8(trans, ofs, val);\n-}\n-IWL_EXPORT_SYMBOL(iwl_write8);\n-\n-void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite32(trans-\u003edev, ofs, val);\n-\tiwl_trans_write32(trans, ofs, val);\n-}\n-IWL_EXPORT_SYMBOL(iwl_write32);\n-\n-void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite64(trans-\u003edev, ofs, val);\n-\tiwl_trans_write32(trans, ofs, lower_32_bits(val));\n-\tiwl_trans_write32(trans, ofs + 4, upper_32_bits(val));\n-}\n-IWL_EXPORT_SYMBOL(iwl_write64);\n-\n-u32 iwl_read32(struct iwl_trans *trans, u32 ofs)\n-{\n-\tu32 val = iwl_trans_read32(trans, ofs);\n-\n-\ttrace_iwlwifi_dev_ioread32(trans-\u003edev, ofs, val);\n-\treturn val;\n-}\n-IWL_EXPORT_SYMBOL(iwl_read32);\n-\n-#define IWL_POLL_INTERVAL 10\t/* microseconds */\n-\n-int iwl_poll_bits_mask(struct iwl_trans *trans, u32 addr,\n-\t\t       u32 bits, u32 mask, int timeout)\n-{\n-\tint t = 0;\n-\n-\tdo {\n-\t\tif ((iwl_read32(trans, addr) \u0026 mask) == (bits \u0026 mask))\n-\t\t\treturn 0;\n-\t\tudelay(IWL_POLL_INTERVAL);\n-\t\tt += IWL_POLL_INTERVAL;\n-\t} while (t \u003c timeout);\n-\n-\treturn -ETIMEDOUT;\n-}\n-IWL_EXPORT_SYMBOL(iwl_poll_bits_mask);\n-\n-u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tu32 value = iwl_read32(trans, reg);\n-\n-\t\tiwl_trans_release_nic_access(trans);\n-\t\treturn value;\n-\t}\n-\n-\t/* return as if we have a HW timeout/failure */\n-\treturn 0x5a5a5a5a;\n-}\n-\n-void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write32(trans, reg, value);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_write_direct32);\n-\n-void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write64(trans, reg, value);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-\n-int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,\n-\t\t\tint timeout)\n-{\n-\tint t = 0;\n-\n-\tdo {\n-\t\tif ((iwl_read_direct32(trans, addr) \u0026 mask) == mask)\n-\t\t\treturn t;\n-\t\tudelay(IWL_POLL_INTERVAL);\n-\t\tt += IWL_POLL_INTERVAL;\n-\t} while (t \u003c timeout);\n-\n-\treturn -ETIMEDOUT;\n-}\n-\n-u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs)\n-{\n-\tu32 val = iwl_trans_read_prph(trans, ofs);\n-\ttrace_iwlwifi_dev_ioread_prph32(trans-\u003edev, ofs, val);\n-\treturn val;\n-}\n-\n-void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite_prph32(trans-\u003edev, ofs, val);\n-\tiwl_trans_write_prph(trans, ofs, val);\n-}\n-\n-void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val)\n-{\n-\ttrace_iwlwifi_dev_iowrite_prph64(trans-\u003edev, ofs, val);\n-\tiwl_write_prph_no_grab(trans, ofs, val \u0026 0xffffffff);\n-\tiwl_write_prph_no_grab(trans, ofs + 4, val \u003e\u003e 32);\n-}\n-\n-u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tu32 val = iwl_read_prph_no_grab(trans, ofs);\n-\n-\t\tiwl_trans_release_nic_access(trans);\n-\n-\t\treturn val;\n-\t}\n-\n-\t/* return as if we have a HW timeout/failure */\n-\treturn 0x5a5a5a5a;\n-}\n-IWL_EXPORT_SYMBOL(iwl_read_prph);\n-\n-void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val, u32 delay_ms)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tmdelay(delay_ms);\n-\t\tiwl_write_prph_no_grab(trans, ofs, val);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_write_prph_delay);\n-\n-int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,\n-\t\t      u32 bits, u32 mask, int timeout)\n-{\n-\tint t = 0;\n-\n-\tdo {\n-\t\tif ((iwl_read_prph(trans, addr) \u0026 mask) == (bits \u0026 mask))\n-\t\t\treturn 0;\n-\t\tudelay(IWL_POLL_INTERVAL);\n-\t\tt += IWL_POLL_INTERVAL;\n-\t} while (t \u003c timeout);\n-\n-\treturn -ETIMEDOUT;\n-}\n-\n-int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,\n-\t\t\t\t    u32 bits, u32 mask, int timeout)\n-{\n-\tint t = 0;\n-\n-\tdo {\n-\t\tif ((iwl_read_umac_prph_no_grab(trans, addr) \u0026 mask) ==\n-\t\t    (bits \u0026 mask))\n-\t\t\treturn 0;\n-\t\tudelay(IWL_POLL_INTERVAL);\n-\t\tt += IWL_POLL_INTERVAL;\n-\t} while (t \u003c timeout);\n-\n-\treturn -ETIMEDOUT;\n-}\n-\n-void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write_prph_no_grab(trans, ofs,\n-\t\t\t\t       iwl_read_prph_no_grab(trans, ofs) |\n-\t\t\t\t       mask);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_set_bits_prph);\n-\n-void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,\n-\t\t\t    u32 bits, u32 mask)\n-{\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write_prph_no_grab(trans, ofs,\n-\t\t\t\t       (iwl_read_prph_no_grab(trans, ofs) \u0026\n-\t\t\t\t\tmask) | bits);\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);\n-\n-void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)\n-{\n-\tu32 val;\n-\n-\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tval = iwl_read_prph_no_grab(trans, ofs);\n-\t\tiwl_write_prph_no_grab(trans, ofs, (val \u0026 ~mask));\n-\t\tiwl_trans_release_nic_access(trans);\n-\t}\n-}\n-IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.h b/drivers/net/wireless/intel/iwlwifi/iwl-io.h\ndeleted file mode 100644\nindex e4a9f2ba0de93..0000000000000\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-io.h\n+++ /dev/null\n@@ -1,103 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n-/*\n- * Copyright (C) 2018-2021, 2025-2026 Intel Corporation\n- */\n-#ifndef __iwl_io_h__\n-#define __iwl_io_h__\n-\n-#include \"iwl-devtrace.h\"\n-#include \"iwl-trans.h\"\n-\n-void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val);\n-void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val);\n-void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val);\n-u32 iwl_read32(struct iwl_trans *trans, u32 ofs);\n-\n-static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)\n-{\n-\tiwl_trans_set_bits_mask(trans, reg, mask, mask);\n-}\n-\n-static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)\n-{\n-\tiwl_trans_set_bits_mask(trans, reg, mask, 0);\n-}\n-\n-int iwl_poll_bits_mask(struct iwl_trans *trans, u32 addr,\n-\t\t       u32 bits, u32 mask, int timeout);\n-static inline int iwl_poll_bits(struct iwl_trans *trans, u32 addr, u32 bits,\n-\t\t\t\tint timeout)\n-{\n-\treturn iwl_poll_bits_mask(trans, addr, bits, bits, timeout);\n-}\n-int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,\n-\t\t\tint timeout);\n-\n-u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg);\n-void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value);\n-void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value);\n-\n-\n-u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs);\n-u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs);\n-void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val);\n-void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val);\n-void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs,\n-\t\t\t  u32 val, u32 delay_ms);\n-static inline void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)\n-{\n-\tiwl_write_prph_delay(trans, ofs, val, 0);\n-}\n-\n-int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,\n-\t\t      u32 bits, u32 mask, int timeout);\n-int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,\n-\t\t\t\t    u32 bits, u32 mask, int timeout);\n-void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);\n-void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,\n-\t\t\t    u32 bits, u32 mask);\n-void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);\n-\n-/*\n- * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from\n- * device family AX200. So peripheries used in families above and below AX200\n- * should go through iwl_..._umac_..._prph.\n- */\n-static inline u32 iwl_umac_prph(struct iwl_trans *trans, u32 ofs)\n-{\n-\treturn ofs + trans-\u003emac_cfg-\u003eumac_prph_offset;\n-}\n-\n-static inline u32 iwl_read_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs)\n-{\n-\treturn iwl_read_prph_no_grab(trans, ofs +\n-\t\t\t\t     trans-\u003emac_cfg-\u003eumac_prph_offset);\n-}\n-\n-static inline u32 iwl_read_umac_prph(struct iwl_trans *trans, u32 ofs)\n-{\n-\treturn iwl_read_prph(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset);\n-}\n-\n-static inline void iwl_write_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs,\n-\t\t\t\t\t       u32 val)\n-{\n-\tiwl_write_prph_no_grab(trans,  ofs + trans-\u003emac_cfg-\u003eumac_prph_offset,\n-\t\t\t       val);\n-}\n-\n-static inline void iwl_write_umac_prph(struct iwl_trans *trans, u32 ofs,\n-\t\t\t\t       u32 val)\n-{\n-\tiwl_write_prph(trans,  ofs + trans-\u003emac_cfg-\u003eumac_prph_offset, val);\n-}\n-\n-static inline int iwl_poll_umac_prph_bit(struct iwl_trans *trans, u32 addr,\n-\t\t\t\t\t u32 bits, u32 mask, int timeout)\n-{\n-\treturn iwl_poll_prph_bit(trans, addr +\n-\t\t\t\t trans-\u003emac_cfg-\u003eumac_prph_offset,\n-\t\t\t\t bits, mask, timeout);\n-}\n-\n-#endif\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c\nindex 413dd55115f8f..ed2b094c1ad78 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c\n@@ -16,7 +16,7 @@\n #include \"iwl-modparams.h\"\n #include \"iwl-nvm-parse.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-csr.h\"\n #include \"fw/api/nvm-reg.h\"\n #include \"fw/api/commands.h\"\n@@ -1312,10 +1312,10 @@ static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)\n static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,\n \t\t\t\t\tstruct iwl_nvm_data *data)\n {\n-\t__le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,\n-\t\t\t\t\t\t  CSR_MAC_ADDR0_STRAP(trans)));\n-\t__le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,\n-\t\t\t\t\t\t  CSR_MAC_ADDR1_STRAP(trans)));\n+\t__le32 mac_addr0 = cpu_to_le32(iwl_trans_read32(trans,\n+\t\t\t\t\t\t\tCSR_MAC_ADDR0_STRAP(trans)));\n+\t__le32 mac_addr1 = cpu_to_le32(iwl_trans_read32(trans,\n+\t\t\t\t\t\t\tCSR_MAC_ADDR1_STRAP(trans)));\n \n \tiwl_flip_hw_address(mac_addr0, mac_addr1, data-\u003ehw_addr);\n \t/*\n@@ -1325,8 +1325,8 @@ static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,\n \tif (is_valid_ether_addr(data-\u003ehw_addr))\n \t\treturn;\n \n-\tmac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));\n-\tmac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));\n+\tmac_addr0 = cpu_to_le32(iwl_trans_read32(trans, CSR_MAC_ADDR0_OTP(trans)));\n+\tmac_addr1 = cpu_to_le32(iwl_trans_read32(trans, CSR_MAC_ADDR1_OTP(trans)));\n \n \tiwl_flip_hw_address(mac_addr0, mac_addr1, data-\u003ehw_addr);\n }\n@@ -1367,10 +1367,10 @@ static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,\n \n \tif (nvm_hw) {\n \t\t/* read the mac address from WFMP registers */\n-\t\t__le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,\n-\t\t\t\t\t\tWFMP_MAC_ADDR_0));\n-\t\t__le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,\n-\t\t\t\t\t\tWFMP_MAC_ADDR_1));\n+\t\t__le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph_no_grab(trans,\n+\t\t\t\t\t\t\t\t\t   WFMP_MAC_ADDR_0));\n+\t\t__le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph_no_grab(trans,\n+\t\t\t\t\t\t\t\t\t   WFMP_MAC_ADDR_1));\n \n \t\tiwl_flip_hw_address(mac_addr0, mac_addr1, data-\u003ehw_addr);\n \n@@ -1410,7 +1410,7 @@ static int iwl_set_hw_address(struct iwl_trans *trans,\n \n \tif (!trans-\u003ecsme_own)\n \t\tIWL_INFO(trans, \"base HW address: %pM, OTP minor version: 0x%x\\n\",\n-\t\t\t data-\u003ehw_addr, iwl_read_prph(trans, REG_OTP_MINOR));\n+\t\t\t data-\u003ehw_addr, iwl_trans_read_prph(trans, REG_OTP_MINOR));\n \n \treturn 0;\n }\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-scd.h b/drivers/net/wireless/intel/iwlwifi/iwl-scd.h\nindex 1eaff898ca3ca..f13568d3094bf 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-scd.h\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-scd.h\n@@ -1,52 +1,52 @@\n /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n /*\n  * Copyright (C) 2014 Intel Mobile Communications GmbH\n+ * Copyright (C) 2026 Intel Corporation\n  */\n #ifndef __iwl_scd_h__\n #define __iwl_scd_h__\n \n #include \"iwl-trans.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-prph.h\"\n \n \n static inline void iwl_scd_txq_set_chain(struct iwl_trans *trans,\n \t\t\t\t\t u16 txq_id)\n {\n-\tiwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));\n+\tiwl_trans_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));\n }\n \n static inline void iwl_scd_txq_enable_agg(struct iwl_trans *trans,\n \t\t\t\t\t  u16 txq_id)\n {\n-\tiwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));\n+\tiwl_trans_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));\n }\n \n static inline void iwl_scd_txq_disable_agg(struct iwl_trans *trans,\n \t\t\t\t\t   u16 txq_id)\n {\n-\tiwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));\n+\tiwl_trans_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));\n }\n \n static inline void iwl_scd_disable_agg(struct iwl_trans *trans)\n {\n-\tiwl_set_bits_prph(trans, SCD_AGGR_SEL, 0);\n+\tiwl_trans_set_bits_prph(trans, SCD_AGGR_SEL, 0);\n }\n \n static inline void iwl_scd_activate_fifos(struct iwl_trans *trans)\n {\n-\tiwl_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7));\n+\tiwl_trans_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7));\n }\n \n static inline void iwl_scd_deactivate_fifos(struct iwl_trans *trans)\n {\n-\tiwl_write_prph(trans, SCD_TXFACT, 0);\n+\tiwl_trans_write_prph(trans, SCD_TXFACT, 0);\n }\n \n static inline void iwl_scd_enable_set_active(struct iwl_trans *trans,\n \t\t\t\t\t     u32 value)\n {\n-\tiwl_write_prph(trans, SCD_EN_CTRL, value);\n+\tiwl_trans_write_prph(trans, SCD_EN_CTRL, value);\n }\n \n static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)\n@@ -76,9 +76,9 @@ static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)\n static inline void iwl_scd_txq_set_inactive(struct iwl_trans *trans,\n \t\t\t\t\t    u16 txq_id)\n {\n-\tiwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),\n-\t\t       (0 \u003c\u003c SCD_QUEUE_STTS_REG_POS_ACTIVE)|\n-\t\t       (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));\n+\tiwl_trans_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),\n+\t\t\t     (0 \u003c\u003c SCD_QUEUE_STTS_REG_POS_ACTIVE)|\n+\t\t\t     (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));\n }\n \n #endif\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.c b/drivers/net/wireless/intel/iwlwifi/iwl-trans.c\nindex 0a6b7b264aa23..6e068f19af7fb 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.c\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.c\n@@ -6,6 +6,7 @@\n  */\n #include \u003clinux/kernel.h\u003e\n #include \u003clinux/bsearch.h\u003e\n+#include \u003clinux/delay.h\u003e\n #include \u003clinux/list.h\u003e\n \n #include \"iwl-trans.h\"\n@@ -260,13 +261,14 @@ static void iwl_trans_restart_wk(struct work_struct *wk)\n \t\tiwl_trans_schedule_reprobe(trans, 0);\n \t\tbreak;\n \tdefault:\n-\t\tiwl_trans_pcie_reset(trans, mode);\n+\t\tiwl_trans_reset(trans, mode);\n \t\tbreak;\n \t}\n }\n \n struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,\n \t\t\t\t  struct device *dev,\n+\t\t\t\t  const struct iwl_trans_ops *ops,\n \t\t\t\t  const struct iwl_mac_cfg *mac_cfg)\n {\n \tstruct iwl_trans *trans;\n@@ -278,6 +280,7 @@ struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,\n \tif (!trans)\n \t\treturn NULL;\n \n+\ttrans-\u003eops = ops;\n \ttrans-\u003emac_cfg = mac_cfg;\n \n #ifdef CONFIG_LOCKDEP\n@@ -428,45 +431,130 @@ void iwl_trans_op_mode_leave(struct iwl_trans *trans)\n }\n IWL_EXPORT_SYMBOL(iwl_trans_op_mode_leave);\n \n-void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)\n-{\n-\tiwl_trans_pcie_write8(trans, ofs, val);\n-}\n-\n void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)\n {\n \tiwl_trans_pcie_write32(trans, ofs, val);\n }\n+IWL_EXPORT_SYMBOL(iwl_trans_write32);\n \n u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)\n {\n \treturn iwl_trans_pcie_read32(trans, ofs);\n }\n+IWL_EXPORT_SYMBOL(iwl_trans_read32);\n \n-u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)\n+u32 iwl_trans_read_prph_no_grab(struct iwl_trans *trans, u32 ofs)\n {\n \treturn iwl_trans_pcie_read_prph(trans, ofs);\n }\n \n-void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)\n+void iwl_trans_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val)\n+{\n+\treturn iwl_pcie_write_prph_no_grab(trans, ofs, val);\n+}\n+\n+#define IWL_POLL_INTERVAL 10\t/* microseconds */\n+\n+int iwl_trans_poll_bits_mask(struct iwl_trans *trans, u32 addr,\n+\t\t\t     u32 bits, u32 mask, int timeout)\n+{\n+\tint t = 0;\n+\n+\tdo {\n+\t\tif ((iwl_trans_read32(trans, addr) \u0026 mask) == (bits \u0026 mask))\n+\t\t\treturn 0;\n+\t\tudelay(IWL_POLL_INTERVAL);\n+\t\tt += IWL_POLL_INTERVAL;\n+\t} while (t \u003c timeout);\n+\n+\treturn -ETIMEDOUT;\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_poll_bits_mask);\n+\n+void iwl_trans_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tiwl_trans_write32(trans, reg, value);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_write_direct32);\n+\n+u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tu32 val = iwl_trans_read_prph_no_grab(trans, ofs);\n+\n+\t\tiwl_trans_release_nic_access(trans);\n+\n+\t\treturn val;\n+\t}\n+\n+\t/* return as if we have a HW timeout/failure */\n+\treturn 0x5a5a5a5a;\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_read_prph);\n+\n+void iwl_trans_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val,\n+\t\t\t\tu32 delay_ms)\n {\n-\treturn iwl_trans_pcie_write_prph(trans, ofs, val);\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tmdelay(delay_ms);\n+\t\tiwl_trans_write_prph_no_grab(trans, ofs, val);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_write_prph_delay);\n+\n+void iwl_trans_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tiwl_trans_write_prph_no_grab(trans, ofs,\n+\t\t\t\t\t     iwl_trans_read_prph_no_grab(trans, ofs) |\n+\t\t\t\t\t     mask);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_set_bits_prph);\n+\n+void iwl_trans_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,\n+\t\t\t\t  u32 bits, u32 mask)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tiwl_trans_write_prph_no_grab(trans, ofs,\n+\t\t\t\t\t     (iwl_trans_read_prph_no_grab(trans, ofs) \u0026\n+\t\t\t\t\t      mask) | bits);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n }\n+IWL_EXPORT_SYMBOL(iwl_trans_set_bits_mask_prph);\n+\n+void iwl_trans_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)\n+{\n+\tu32 val;\n+\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tval = iwl_trans_read_prph_no_grab(trans, ofs);\n+\t\tiwl_trans_write_prph_no_grab(trans, ofs, (val \u0026 ~mask));\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_clear_bits_prph);\n \n void iwl_trans_force_nmi(struct iwl_trans *trans)\n {\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_9000)\n-\t\tiwl_write_prph_delay(trans, DEVICE_SET_NMI_REG,\n-\t\t\t\t     DEVICE_SET_NMI_VAL_DRV, 1);\n+\t\tiwl_trans_write_prph_delay(trans, DEVICE_SET_NMI_REG,\n+\t\t\t\t\t   DEVICE_SET_NMI_VAL_DRV, 1);\n \telse if (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_AX210)\n-\t\tiwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,\n-\t\t\t\t    UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,\n+\t\t\t\t\t  UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);\n \telse if (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n-\t\t\t\t    UREG_DOORBELL_TO_ISR6_NMI_BIT);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n+\t\t\t\t\t  UREG_DOORBELL_TO_ISR6_NMI_BIT);\n \telse\n-\t\tiwl_write32(trans, CSR_DOORBELL_VECTOR,\n-\t\t\t    UREG_DOORBELL_TO_ISR6_NMI_BIT);\n+\t\tiwl_trans_write32(trans, CSR_DOORBELL_VECTOR,\n+\t\t\t\t  UREG_DOORBELL_TO_ISR6_NMI_BIT);\n }\n IWL_EXPORT_SYMBOL(iwl_trans_force_nmi);\n \n@@ -490,10 +578,10 @@ int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,\n \tconst u32 *vals = buf;\n \n \tif (iwl_trans_grab_nic_access(trans)) {\n-\t\tiwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);\n+\t\tiwl_trans_write32(trans, HBUS_TARG_MEM_WADDR, addr);\n \t\tfor (offs = 0; offs \u003c dwords; offs++)\n-\t\t\tiwl_write32(trans, HBUS_TARG_MEM_WDAT,\n-\t\t\t\t    vals ? vals[offs] : 0);\n+\t\t\tiwl_trans_write32(trans, HBUS_TARG_MEM_WDAT,\n+\t\t\t\t\t  vals ? vals[offs] : 0);\n \t\tiwl_trans_release_nic_access(trans);\n \t} else {\n \t\tret = -EBUSY;\n@@ -843,3 +931,17 @@ int iwl_trans_activate_nic(struct iwl_trans *trans)\n }\n IWL_EXPORT_SYMBOL(iwl_trans_activate_nic);\n \n+\n+void iwl_trans_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)\n+{\n+\tif (!WARN_ON_ONCE(!trans-\u003eops-\u003ereset))\n+\t\ttrans-\u003eops-\u003ereset(trans, mode);\n+}\n+IWL_EXPORT_SYMBOL(iwl_trans_reset);\n+\n+void iwl_trans_fw_reset_handshake(struct iwl_trans *trans)\n+{\n+\tif (!WARN_ON_ONCE(!trans-\u003eops-\u003efw_reset_handshake))\n+\t\ttrans-\u003eops-\u003efw_reset_handshake(trans);\n+}\n+\ndiff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h\nindex 56c5e61b614ad..90100f16ddd52 100644\n--- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h\n+++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h\n@@ -734,12 +734,15 @@ struct iwl_trans_info {\n \tu8 num_rxqs;\n };\n \n+struct iwl_trans_ops;\n+\n /**\n  * struct iwl_trans - transport common data\n  *\n  * @csme_own: true if we couldn't get ownership on the device\n  * @op_mode: pointer to the op_mode\n  * @mac_cfg: the trans-specific configuration part\n+ * @ops: bus-specific transport operations, see \u0026struct iwl_trans_ops\n  * @cfg: pointer to the configuration\n  * @drv: pointer to iwl_drv\n  * @conf: configuration set by the opmode before enter\n@@ -773,6 +776,7 @@ struct iwl_trans {\n \tbool csme_own;\n \tstruct iwl_op_mode *op_mode;\n \tconst struct iwl_mac_cfg *mac_cfg;\n+\tconst struct iwl_trans_ops *ops;\n \tconst struct iwl_rf_cfg *cfg;\n \tstruct iwl_drv *drv;\n \tstruct iwl_trans_config conf;\n@@ -910,15 +914,13 @@ int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, u32 txqs);\n \n int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue);\n \n-void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val);\n-\n void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val);\n \n u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs);\n \n-u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs);\n+u32 iwl_trans_read_prph_no_grab(struct iwl_trans *trans, u32 ofs);\n \n-void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val);\n+void iwl_trans_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val);\n \n int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,\n \t\t       void *buf, int dwords);\n@@ -979,6 +981,66 @@ int iwl_trans_sw_reset(struct iwl_trans *trans);\n void iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg,\n \t\t\t     u32 mask, u32 value);\n \n+static inline void iwl_trans_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)\n+{\n+\tiwl_trans_set_bits_mask(trans, reg, mask, mask);\n+}\n+\n+static inline void iwl_trans_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)\n+{\n+\tiwl_trans_set_bits_mask(trans, reg, mask, 0);\n+}\n+\n+int iwl_trans_poll_bits_mask(struct iwl_trans *trans, u32 addr,\n+\t\t\t     u32 bits, u32 mask, int timeout);\n+static inline int iwl_trans_poll_bits(struct iwl_trans *trans, u32 addr, u32 bits,\n+\t\t\t\t      int timeout)\n+{\n+\treturn iwl_trans_poll_bits_mask(trans, addr, bits, bits, timeout);\n+}\n+\n+void iwl_trans_write_direct32(struct iwl_trans *trans, u32 reg, u32 value);\n+\n+u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs);\n+void iwl_trans_write_prph_delay(struct iwl_trans *trans, u32 ofs,\n+\t\t\t\tu32 val, u32 delay_ms);\n+static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)\n+{\n+\tiwl_trans_write_prph_delay(trans, ofs, val, 0);\n+}\n+\n+void iwl_trans_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);\n+void iwl_trans_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,\n+\t\t\t\t  u32 bits, u32 mask);\n+void iwl_trans_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);\n+\n+/*\n+ * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from\n+ * device family AX200. So peripheries used in families above and below AX200\n+ * should go through iwl_trans_..._umac_..._prph.\n+ */\n+static inline u32 iwl_trans_umac_prph(struct iwl_trans *trans, u32 ofs)\n+{\n+\treturn ofs + trans-\u003emac_cfg-\u003eumac_prph_offset;\n+}\n+\n+static inline u32 iwl_trans_read_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs)\n+{\n+\treturn iwl_trans_read_prph_no_grab(trans, ofs +\n+\t\t\t\t\t   trans-\u003emac_cfg-\u003eumac_prph_offset);\n+}\n+\n+static inline u32 iwl_trans_read_umac_prph(struct iwl_trans *trans, u32 ofs)\n+{\n+\treturn iwl_trans_read_prph(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset);\n+}\n+\n+static inline void iwl_trans_write_umac_prph(struct iwl_trans *trans, u32 ofs,\n+\t\t\t\t\t     u32 val)\n+{\n+\tiwl_trans_write_prph(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset, val);\n+}\n+\n bool iwl_trans_grab_nic_access(struct iwl_trans *trans);\n \n /**\n@@ -1088,6 +1150,7 @@ static inline void iwl_trans_finish_sw_reset(struct iwl_trans *trans)\n  *****************************************************/\n struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,\n \t\t\t\t  struct device *dev,\n+\t\t\t\t  const struct iwl_trans_ops *ops,\n \t\t\t\t  const struct iwl_mac_cfg *mac_cfg);\n void iwl_trans_free(struct iwl_trans *trans);\n \n@@ -1158,8 +1221,148 @@ enum iwl_reset_mode {\n \tIWL_RESET_MODE_BACKOFF,\n };\n \n-void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode);\n-void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans);\n+void iwl_trans_reset(struct iwl_trans *trans, enum iwl_reset_mode mode);\n+void iwl_trans_fw_reset_handshake(struct iwl_trans *trans);\n+\n+/**\n+ * struct iwl_trans_ops - bus-specific transport operations\n+ *\n+ * Function-pointer table filled in by the bus implementation. Unless noted\n+ * otherwise, each callback implements the identically named iwl_trans_*()\n+ * API, see its documentation.\n+ *\n+ * @op_mode_enter: the op_mode took ownership of the transport\n+ * @start_hw: start the hardware\n+ * @op_mode_leave: the op_mode released the transport\n+ * @send_cmd: send a host command to the firmware\n+ * @alloc_tx_cmd: allocate a device TX command\n+ * @free_tx_cmd: free a device TX command\n+ * @write8: write a byte to a device register\n+ * @write32: write a dword to a device register\n+ * @read32: read a dword from a device register\n+ * @read_prph: read a peripheral register\n+ * @write_prph: write a peripheral register\n+ * @read_mem: read device memory, taking NIC access\n+ * @read_mem_no_grab: read device memory, NIC access already taken\n+ * @set_bits_mask: read-modify-write a device register\n+ * @read_config32: read a dword from the bus configuration space\n+ * @grab_nic_access: keep the NIC awake for register access\n+ * @release_nic_access: release the NIC access taken by @grab_nic_access\n+ * @resched_with_nic_access: reschedule while holding NIC access\n+ * @sw_reset: perform a software reset of the device\n+ * @reset: reset the device, see \u0026enum iwl_reset_mode\n+ * @fw_reset_handshake: do a firmware reset handshake.\n+ * @dump_data: collect a firmware error dump\n+ * @d3_suspend: prepare the device for D3 (WoWLAN)\n+ * @d3_resume: resume the device from D3 (WoWLAN)\n+ * @sync_nmi: trigger an NMI and wait for it to be handled\n+ * @write_imr_mem: write to the IMR memory region\n+ * @fw_alive: Notify trans that the firmware sent the ALIVE notification\n+ * @start_fw: download firmware code to the device and and start the firmware\n+ * @stop_device: stop the device and the firmware\n+ * @tx: transmit an MPDU\n+ * @reclaim: free TX MPDUs up to the given sequence number\n+ * @txq_disable: disable a TX queue (gen1)\n+ * @txq_enable: enable a TX queue (gen1)\n+ * @wait_txq_empty: wait for a single TX queue to become empty\n+ * @wait_txqs_empty: wait for the given TX queues to become empty\n+ * @freeze_txq_timer: freeze/unfreeze the watchdog of the given TX queues\n+ * @txq_set_shared_mode: mark a TX queue as shared between TIDs\n+ * @set_q_ptrs: set the write pointer of a TX queue\n+ * @txq_alloc: allocate a TX queue (gen2)\n+ * @txq_free: free a TX queue allocated by @txq_alloc\n+ * @rxq_dma_data: get the DMA addresses of an RX queue\n+ * @load_pnvm: load the PNVM image\n+ * @set_pnvm: tell the firmware to use the loaded PNVM\n+ * @load_reduce_power: load the reduced power table\n+ * @set_reduce_power: tell the firmware to use the reduced power table\n+ * @is_pm_supported: whether bus power management is supported\n+ * @is_ltr_enabled: whether LTR is enabled on the bus\n+ * @activate_nic: bring the NIC out of low power and make it accessible\n+ */\n+struct iwl_trans_ops {\n+\tvoid (*op_mode_enter)(struct iwl_trans *trans);\n+\tint (*start_hw)(struct iwl_trans *trans);\n+\tvoid (*op_mode_leave)(struct iwl_trans *trans);\n+\n+\tint (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);\n+\tstruct iwl_device_tx_cmd *(*alloc_tx_cmd)(struct iwl_trans *trans);\n+\tvoid (*free_tx_cmd)(struct iwl_trans *trans,\n+\t\t\t    struct iwl_device_tx_cmd *dev_cmd);\n+\n+\tvoid (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);\n+\tvoid (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);\n+\tu32 (*read32)(struct iwl_trans *trans, u32 ofs);\n+\tu32 (*read_prph)(struct iwl_trans *trans, u32 ofs);\n+\tvoid (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);\n+\tint (*read_mem)(struct iwl_trans *trans, u32 addr,\n+\t\t\tvoid *buf, int dwords);\n+\tint (*read_mem_no_grab)(struct iwl_trans *trans, u32 addr,\n+\t\t\t\tvoid *buf, u32 dwords);\n+\tvoid (*set_bits_mask)(struct iwl_trans *trans, u32 reg,\n+\t\t\t      u32 mask, u32 value);\n+\tint (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val);\n+\tbool (*grab_nic_access)(struct iwl_trans *trans);\n+\tvoid (*release_nic_access)(struct iwl_trans *trans);\n+\tvoid (*resched_with_nic_access)(struct iwl_trans *trans);\n+\n+\tint (*sw_reset)(struct iwl_trans *trans, bool retake_ownership);\n+\tvoid (*reset)(struct iwl_trans *trans, enum iwl_reset_mode mode);\n+\tvoid (*fw_reset_handshake)(struct iwl_trans *trans);\n+\n+\tstruct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,\n+\t\t\t\t\t\t u32 dump_mask,\n+\t\t\t\t\t\t const struct iwl_dump_sanitize_ops *sanitize_ops,\n+\t\t\t\t\t\t void *sanitize_ctx);\n+\tint (*d3_suspend)(struct iwl_trans *trans, bool reset);\n+\tint (*d3_resume)(struct iwl_trans *trans, bool reset);\n+\n+\tvoid (*sync_nmi)(struct iwl_trans *trans);\n+\tint (*write_imr_mem)(struct iwl_trans *trans, u32 dst_addr,\n+\t\t\t     u64 src_addr, u32 byte_cnt);\n+\n+\tvoid (*fw_alive)(struct iwl_trans *trans);\n+\tint (*start_fw)(struct iwl_trans *trans, const struct iwl_fw *fw,\n+\t\t\tconst struct fw_img *img, bool run_in_rfkill);\n+\tvoid (*stop_device)(struct iwl_trans *trans);\n+\n+\tint (*tx)(struct iwl_trans *trans, struct sk_buff *skb,\n+\t\t  struct iwl_device_tx_cmd *dev_cmd, int queue);\n+\tvoid (*reclaim)(struct iwl_trans *trans, int queue, int ssn,\n+\t\t\tstruct sk_buff_head *skbs, bool is_flush);\n+\tvoid (*txq_disable)(struct iwl_trans *trans, int queue,\n+\t\t\t    bool configure_scd);\n+\tbool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,\n+\t\t\t   const struct iwl_trans_txq_scd_cfg *cfg,\n+\t\t\t   unsigned int queue_wdg_timeout);\n+\tint (*wait_txq_empty)(struct iwl_trans *trans, int queue);\n+\tint (*wait_txqs_empty)(struct iwl_trans *trans, u32 txqs);\n+\tvoid (*freeze_txq_timer)(struct iwl_trans *trans,\n+\t\t\t\t unsigned long txqs, bool freeze);\n+\tvoid (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,\n+\t\t\t\t    bool shared_mode);\n+\tvoid (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr);\n+\tint (*txq_alloc)(struct iwl_trans *trans, u32 flags, u32 sta_mask,\n+\t\t\t u8 tid, int size, unsigned int wdg_timeout);\n+\tvoid (*txq_free)(struct iwl_trans *trans, int queue);\n+\tint (*rxq_dma_data)(struct iwl_trans *trans, int queue,\n+\t\t\t    struct iwl_trans_rxq_dma_data *data);\n+\n+\tint (*load_pnvm)(struct iwl_trans *trans,\n+\t\t\t const struct iwl_pnvm_image *pnvm_data,\n+\t\t\t const struct iwl_ucode_capabilities *capa);\n+\tvoid (*set_pnvm)(struct iwl_trans *trans,\n+\t\t\t const struct iwl_ucode_capabilities *capa);\n+\tint (*load_reduce_power)(struct iwl_trans *trans,\n+\t\t\t\t const struct iwl_pnvm_image *payloads,\n+\t\t\t\t const struct iwl_ucode_capabilities *capa);\n+\tvoid (*set_reduce_power)(struct iwl_trans *trans,\n+\t\t\t\t const struct iwl_ucode_capabilities *capa);\n+\n+\tbool (*is_pm_supported)(struct iwl_trans *trans);\n+\tbool (*is_ltr_enabled)(struct iwl_trans *trans);\n+\tint (*activate_nic)(struct iwl_trans *trans);\n+};\n \n /* Internal helper */\n static inline void iwl_trans_set_info(struct iwl_trans *trans,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/constants.h b/drivers/net/wireless/intel/iwlwifi/mld/constants.h\nindex 890abcab38374..bfd5398510ee3 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/constants.h\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/constants.h\n@@ -39,6 +39,10 @@\n \n #define IWL_MLD_TPT_COUNT_WINDOW (5 * HZ)\n \n+#define IWL_MLD_TX_GP2_VALID_PERIOD\t(10 * HZ)\n+#define IWL_MLD_TX_GP2_REFRESH_MARGIN\t(5 * HZ)\n+#define IWL_MLD_TX_GP2_RETRY_PERIOD\tHZ\n+\n #define IWL_MLD_DIS_RANDOM_FW_ID                false\n #define IWL_MLD_D3_DEBUG                        false\n #define IWL_MLD_NON_TRANSMITTING_AP\t        false\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/d3.c b/drivers/net/wireless/intel/iwlwifi/mld/d3.c\nindex 6d8ede336d59b..7a7d07a7914dd 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/d3.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/d3.c\n@@ -5,6 +5,7 @@\n #include \"mld.h\"\n \n #include \"d3.h\"\n+#include \"tx.h\"\n #include \"power.h\"\n #include \"hcmd.h\"\n #include \"iface.h\"\n@@ -1610,6 +1611,8 @@ int iwl_mld_no_wowlan_suspend(struct iwl_mld *mld)\n \n \tiwl_mld_low_latency_stop(mld);\n \n+\tiwl_mld_tx_gp2_stop(mld);\n+\n \tret = iwl_mld_update_device_power(mld, true);\n \tif (ret) {\n \t\tIWL_ERR(mld,\n@@ -1663,6 +1666,8 @@ int iwl_mld_no_wowlan_resume(struct iwl_mld *mld)\n \n \tiwl_mld_low_latency_restart(mld);\n \n+\tiwl_mld_tx_gp2_start(mld);\n+\n \treturn iwl_mld_update_device_power(mld, false);\n }\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c\nindex dd4bf7cb6a791..b8793b71494d8 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c\n@@ -5,7 +5,7 @@\n \n #include \"mld.h\"\n #include \"debugfs.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"hcmd.h\"\n #include \"iface.h\"\n #include \"sta.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c\nindex a4b8037b5c765..a6a4f9672e4f9 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c\n@@ -8,7 +8,7 @@\n #include \"mld.h\"\n #include \"iface.h\"\n #include \"phy.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"constants.h\"\n #include \"fw/api/location.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/fw.c b/drivers/net/wireless/intel/iwlwifi/mld/fw.c\nindex e5866d89176d1..3b9f412cdff2b 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/fw.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/fw.c\n@@ -1,9 +1,10 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /*\n- * Copyright (C) 2024-2025 Intel Corporation\n+ * Copyright (C) 2024-2026 Intel Corporation\n  */\n \n #include \"mld.h\"\n+#include \"tx.h\"\n \n #include \"fw/api/alive.h\"\n #include \"fw/api/scan.h\"\n@@ -206,11 +207,11 @@ static void iwl_mld_print_alive_notif_timeout(struct iwl_mld *mld)\n \n \tIWL_ERR(mld,\n \t\t\"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\\n\",\n-\t\tiwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),\n-\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t   UMAG_SB_CPU_2_STATUS));\n+\t\tiwl_trans_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),\n+\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t UMAG_SB_CPU_2_STATUS));\n #define IWL_FW_PRINT_REG_INFO(reg_name) \\\n-\tIWL_ERR(mld, #reg_name \": 0x%x\\n\", iwl_read_umac_prph(trans, reg_name))\n+\tIWL_ERR(mld, #reg_name \": 0x%x\\n\", iwl_trans_read_umac_prph(trans, reg_name))\n \n \tIWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION);\n \n@@ -355,6 +356,8 @@ void iwl_mld_stop_fw(struct iwl_mld *mld)\n {\n \tlockdep_assert_wiphy(mld-\u003ewiphy);\n \n+\tiwl_mld_tx_gp2_stop(mld);\n+\n \tiwl_abort_notification_waits(\u0026mld-\u003enotif_wait);\n \n \tiwl_fw_dbg_stop_sync(\u0026mld-\u003efwrt);\n@@ -542,6 +545,8 @@ int iwl_mld_start_fw(struct iwl_mld *mld)\n \tif (ret)\n \t\tgoto error;\n \n+\tiwl_mld_tx_gp2_start(mld);\n+\n \treturn 0;\n \n error:\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c\nindex 0b121114d47ca..e05bdbd3e1a9a 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c\n@@ -2168,6 +2168,8 @@ static int iwl_mld_resume(struct ieee80211_hw *hw)\n \n \tiwl_mld_low_latency_restart(mld);\n \n+\tiwl_mld_tx_gp2_start(mld);\n+\n \treturn 0;\n }\n #endif\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/mld.c b/drivers/net/wireless/intel/iwlwifi/mld/mld.c\nindex b7b1e3686336c..71832d92024d0 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/mld.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/mld.c\n@@ -35,6 +35,17 @@ MODULE_IMPORT_NS(\"IWLWIFI\");\n \n static const struct iwl_op_mode_ops iwl_mld_ops;\n \n+int iwl_mld_get_systime(struct iwl_mld *mld, u32 *gp2)\n+{\n+\t*gp2 = iwl_trans_read_prph(mld-\u003etrans,\n+\t\t\t     mld-\u003etrans-\u003emac_cfg-\u003ebase-\u003egp2_reg_addr);\n+\n+\tif (*gp2 == 0x5a5a5a5a)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n static int __init iwl_mld_init(void)\n {\n \tint ret = iwl_opmode_register(\"iwlmld\", \u0026iwl_mld_ops);\n@@ -425,6 +436,8 @@ iwl_op_mode_mld_start(struct iwl_trans *trans, const struct iwl_rf_cfg *cfg,\n \t/* Configure transport layer with the opmode specific params */\n \tiwl_mld_configure_trans(op_mode);\n \n+\tiwl_mld_tx_gp2_init(mld);\n+\n \t/* needed for regulatory init */\n \trtnl_lock();\n \t/* Needed for sending commands */\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/mld.h b/drivers/net/wireless/intel/iwlwifi/mld/mld.h\nindex 37f41b504b54c..a9e65b216fd39 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/mld.h\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/mld.h\n@@ -29,6 +29,7 @@\n #include \"notif.h\"\n #include \"scan.h\"\n #include \"rx.h\"\n+#include \"tx.h\"\n #include \"thermal.h\"\n #include \"low_latency.h\"\n #include \"constants.h\"\n@@ -196,6 +197,7 @@\n  *\tbeing IBSS manager for that time and needing to respond to probe\n  *\trequests\n  * @ptp_data: data of the PTP clock\n+ * @tx_gp2: gp2 timestamping state for TX commands\n  * @time_sync: time sync data.\n  * @ftm_initiator: FTM initiator data\n  * @nan_device_vif: points to the NAN device vif if exists\n@@ -306,6 +308,8 @@ struct iwl_mld {\n \n \tstruct ptp_data ptp_data;\n \n+\tstruct iwl_mld_tx_gp2 tx_gp2;\n+\n \tstruct iwl_mld_time_sync_data __rcu *time_sync;\n \n \tstruct ftm_initiator_data ftm_initiator;\n@@ -572,6 +576,8 @@ iwl_mld_fw_id_to_link_conf(struct iwl_mld *mld, u8 fw_link_id)\n \n #define MSEC_TO_TU(_msec)\t((_msec) * 1000 / 1024)\n \n+int iwl_mld_get_systime(struct iwl_mld *mld, u32 *gp2);\n+\n void iwl_mld_add_vif_debugfs(struct ieee80211_hw *hw,\n \t\t\t     struct ieee80211_vif *vif);\n void iwl_mld_add_link_debugfs(struct ieee80211_hw *hw,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c\nindex 1ac85d6ce1d79..9f7d17dbdee16 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c\n@@ -1,6 +1,6 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /*\n- * Copyright (C) 2025 Intel Corporation\n+ * Copyright (C) 2025 - 2026 Intel Corporation\n  */\n \n #include \"mld.h\"\n@@ -19,16 +19,6 @@\n #define IWL_PTP_WRAP_TIME\t(3600 * HZ)\n #define IWL_PTP_WRAP_THRESHOLD_USEC\t(5000)\n \n-static int iwl_mld_get_systime(struct iwl_mld *mld, u32 *gp2)\n-{\n-\t*gp2 = iwl_read_prph(mld-\u003etrans, mld-\u003etrans-\u003emac_cfg-\u003ebase-\u003egp2_reg_addr);\n-\n-\tif (*gp2 == 0x5a5a5a5a)\n-\t\treturn -EINVAL;\n-\n-\treturn 0;\n-}\n-\n static void iwl_mld_ptp_update_new_read(struct iwl_mld *mld, u32 gp2)\n {\n \tIWL_DEBUG_PTP(mld, \"PTP: last_gp2=%u, new gp2 read=%u\\n\",\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/rx.c b/drivers/net/wireless/intel/iwlwifi/mld/rx.c\nindex 5f18aa551af52..8fa438fd78153 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/rx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/rx.c\n@@ -553,7 +553,10 @@ iwl_mld_decode_he_tb_phy_data(struct iwl_mld_rx_phy_data *phy_data,\n \n \tnsts = le32_get_bits(phy_data-\u003entfy-\u003esigs.he_tb.tb_rx1,\n \t\t\t     OFDM_UCODE_TRIG_BASE_RX_NSTS) + 1;\n-\trx_status-\u003enss = nsts \u003e\u003e !!(rate_n_flags \u0026 RATE_MCS_STBC_MSK);\n+\n+\trx_status-\u003enss = nsts;\n+\tif (rate_n_flags \u0026 RATE_MCS_STBC_MSK)\n+\t\trx_status-\u003enss = 1;\n }\n \n static void\n@@ -589,7 +592,9 @@ iwl_mld_decode_he_phy_data(struct iwl_mld_rx_phy_data *phy_data,\n \t\tbreak;\n \t}\n \n-\trx_status-\u003enss = nsts \u003e\u003e !!(rate_n_flags \u0026 RATE_MCS_STBC_MSK);\n+\trx_status-\u003enss = nsts;\n+\tif (rate_n_flags \u0026 RATE_MCS_STBC_MSK)\n+\t\trx_status-\u003enss = 1;\n \n \the-\u003edata1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |\n \t\t\t\t IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/scan.c b/drivers/net/wireless/intel/iwlwifi/mld/scan.c\nindex e44b24904c19a..b942ac1e7ccca 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/scan.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/scan.c\n@@ -2273,6 +2273,7 @@ void iwl_mld_handle_channel_survey_notif(struct iwl_mld *mld,\n \t/* Times are all in ms */\n \tinfo-\u003etime = le32_to_cpu(notif-\u003eactive_time);\n \tinfo-\u003etime_busy = le32_to_cpu(notif-\u003ebusy_time);\n+\tinfo-\u003etime_rx = le32_to_cpu(notif-\u003erx_time);\n \tinfo-\u003enoise =\n \t\tiwl_average_neg_dbm(notif-\u003enoise, ARRAY_SIZE(notif-\u003enoise));\n }\n@@ -2321,9 +2322,11 @@ int iwl_mld_mac80211_get_survey(struct ieee80211_hw *hw, int idx,\n \t\t\t/* Found (the next) channel to report */\n \t\t\tsurvey-\u003echannel = \u0026sband-\u003echannels[per_band_idx];\n \t\t\tsurvey-\u003efilled = SURVEY_INFO_TIME |\n-\t\t\t\t\t SURVEY_INFO_TIME_BUSY;\n+\t\t\t\t\t SURVEY_INFO_TIME_BUSY |\n+\t\t\t\t\t SURVEY_INFO_TIME_RX;\n \t\t\tsurvey-\u003etime = info-\u003etime;\n \t\t\tsurvey-\u003etime_busy = info-\u003etime_busy;\n+\t\t\tsurvey-\u003etime_rx = info-\u003etime_rx;\n \t\t\tsurvey-\u003enoise = info-\u003enoise;\n \t\t\tif (survey-\u003enoise \u003c 0)\n \t\t\t\tsurvey-\u003efilled |= SURVEY_INFO_NOISE_DBM;\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/scan.h b/drivers/net/wireless/intel/iwlwifi/mld/scan.h\nindex dc299fe2f999c..74ebe8296693f 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/scan.h\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/scan.h\n@@ -1,6 +1,6 @@\n /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n /*\n- * Copyright (C) 2024-2025 Intel Corporation\n+ * Copyright (C) 2024-2026 Intel Corporation\n  */\n #ifndef __iwl_mld_scan_h__\n #define __iwl_mld_scan_h__\n@@ -151,11 +151,13 @@ struct iwl_mld_scan {\n  *\n  * @time: time in ms the radio was on the channel\n  * @time_busy: time in ms the channel was sensed busy\n+ * @time_rx: time in ms the channel was sensed to carry Wi-Fi frames\n  * @noise: channel noise in dBm\n  */\n struct iwl_mld_survey_channel {\n \tu32 time;\n \tu32 time_busy;\n+\tu32 time_rx;\n \ts8 noise;\n };\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/sta.c b/drivers/net/wireless/intel/iwlwifi/mld/sta.c\nindex 7957ac11b0cd5..97f013330f068 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/sta.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/sta.c\n@@ -465,8 +465,8 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld *mld,\n \tstruct iwl_mld_sta *mld_sta = iwl_mld_sta_from_mac80211(sta);\n \tstruct iwl_sta_cfg_cmd cmd = {};\n \tint fw_id = iwl_mld_fw_sta_id_from_link_sta(mld, link_sta);\n-\tbool is_6ghz, uora_exists;\n \tu32 link_mask;\n+\tbool is_6ghz;\n \n \tlockdep_assert_wiphy(mld-\u003ewiphy);\n \n@@ -479,7 +479,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld *mld,\n \t\t\treturn -EINVAL;\n \n \t\tis_6ghz = false;\n-\t\tuora_exists = false;\n \n \t\tlink_mask = iwl_mld_get_nan_link_mask(mld);\n \t} else {\n@@ -495,7 +494,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld *mld,\n \n \t\tlink_mask = BIT(mld_link-\u003efw_id);\n \t\tis_6ghz = link-\u003echanreq.oper.chan-\u003eband == NL80211_BAND_6GHZ;\n-\t\tuora_exists = link-\u003euora_exists;\n \t}\n \n \tcmd.sta_id = cpu_to_le32(fw_id);\n@@ -554,9 +552,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld *mld,\n \t}\n \n \tif (link_sta-\u003ehe_cap.has_he) {\n-\t\tcmd.trig_rnd_alloc =\n-\t\t\tcpu_to_le32(uora_exists ? 1 : 0);\n-\n \t\t/* PPE Thresholds */\n \t\tiwl_mld_fill_pkt_ext(mld, link_sta, \u0026cmd.pkt_ext);\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile b/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile\nindex efa61638b8eeb..730185be3fa82 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile\n@@ -1,6 +1,6 @@\n # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n iwlmld-tests-y += module.o hcmd.o utils.o link.o rx.o agg.o link-selection.o\n-iwlmld-tests-y += chan_load_thresh.o\n+iwlmld-tests-y += chan_load_thresh.o tx-gp2.o\n \n ccflags-y += -I$(src)/../\n obj-$(CONFIG_IWLWIFI_KUNIT_TESTS) += iwlmld-tests.o\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c b/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c\nnew file mode 100644\nindex 0000000000000..535140eb17c47\n--- /dev/null\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c\n@@ -0,0 +1,154 @@\n+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n+/*\n+ * KUnit tests for TX gp2 timestamp handling\n+ *\n+ * Copyright (C) 2026 Intel Corporation\n+ */\n+#include \u003ckunit/test.h\u003e\n+\n+#include \"mld.h\"\n+#include \"tx.h\"\n+\n+MODULE_IMPORT_NS(\"EXPORTED_FOR_KUNIT_TESTING\");\n+\n+static const struct tx_gp2_case {\n+\tconst char *desc;\n+\tu32 est_gp2_us;\n+\tu32 est_host_us;\n+\tu32 tx_host_us;\n+\tlong valid_for;\n+\tu32 expected_gp2_us;\n+\tbool expected_refresh;\n+} tx_gp2_cases[] = {\n+\t{\n+\t\t.desc = \"zero offset is valid\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 2000,\n+\t\t.tx_host_us = 3500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 3500,\n+\t},\n+\t{\n+\t\t.desc = \"gp2 behind host\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 3500,\n+\t},\n+\t{\n+\t\t.desc = \"gp2 ahead of host\",\n+\t\t.est_gp2_us = 10000,\n+\t\t.est_host_us = 2000,\n+\t\t.tx_host_us = 3500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 11500,\n+\t},\n+\t{\n+\t\t.desc = \"gp2 wraps after the estimate\",\n+\t\t.est_gp2_us = U32_MAX - 999,\n+\t\t.est_host_us = 1000,\n+\t\t.tx_host_us = 2500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 500,\n+\t},\n+\t{\n+\t\t.desc = \"host time wraps after the estimate\",\n+\t\t.est_gp2_us = 5000,\n+\t\t.est_host_us = U32_MAX - 999,\n+\t\t.tx_host_us = 500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 6500,\n+\t},\n+\t{\n+\t\t.desc = \"gp2 landing on 0 is reported as 1\",\n+\t\t.est_gp2_us = U32_MAX - 1499,\n+\t\t.est_host_us = 1000,\n+\t\t.tx_host_us = 2500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,\n+\t\t.expected_gp2_us = 1,\n+\t},\n+\t{\n+\t\t.desc = \"within the refresh margin: still timestamped\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN - 1,\n+\t\t.expected_gp2_us = 3500,\n+\t\t.expected_refresh = true,\n+\t},\n+\t{\n+\t\t.desc = \"outside the refresh margin: no refresh\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN + 1,\n+\t\t.expected_gp2_us = 3500,\n+\t},\n+\t{\n+\t\t.desc = \"at the refresh threshold\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN,\n+\t\t.expected_gp2_us = 3500,\n+\t\t.expected_refresh = true,\n+\t},\n+\t{\n+\t\t.desc = \"last valid tick\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = 1,\n+\t\t.expected_gp2_us = 3500,\n+\t\t.expected_refresh = true,\n+\t},\n+\t{\n+\t\t.desc = \"validity reached: leave the frame unstamped\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = 0,\n+\t\t.expected_refresh = true,\n+\t},\n+\t{\n+\t\t.desc = \"validity passed: leave the frame unstamped\",\n+\t\t.est_gp2_us = 2000,\n+\t\t.est_host_us = 10000,\n+\t\t.tx_host_us = 11500,\n+\t\t.valid_for = -1,\n+\t\t.expected_refresh = true,\n+\t},\n+};\n+\n+KUNIT_ARRAY_PARAM_DESC(tx_gp2, tx_gp2_cases, desc);\n+\n+static void test_tx_gp2(struct kunit *test)\n+{\n+\t/* Pin time near wraparound to exercise wrapped validity deadlines. */\n+\tconst unsigned long now =\n+\t\tULONG_MAX - IWL_MLD_TX_GP2_REFRESH_MARGIN - 1;\n+\tconst struct tx_gp2_case *test_case = test-\u003eparam_value;\n+\tu32 delta_us = test_case-\u003eest_gp2_us - test_case-\u003eest_host_us;\n+\tunsigned long valid_until = now + test_case-\u003evalid_for;\n+\tbool refresh = !test_case-\u003eexpected_refresh;\n+\tu32 timestamp;\n+\n+\ttimestamp = iwl_mld_tx_gp2_from_est(delta_us, valid_until,\n+\t\t\t\t\t    test_case-\u003etx_host_us, now,\n+\t\t\t\t\t    \u0026refresh);\n+\tKUNIT_EXPECT_EQ(test, timestamp, test_case-\u003eexpected_gp2_us);\n+\tKUNIT_EXPECT_EQ(test, refresh, test_case-\u003eexpected_refresh);\n+}\n+\n+static struct kunit_case tx_gp2_test_cases[] = {\n+\tKUNIT_CASE_PARAM(test_tx_gp2, tx_gp2_gen_params),\n+\t{}\n+};\n+\n+static struct kunit_suite tx_gp2_test_suite = {\n+\t.name = \"iwl_mld_tx_gp2\",\n+\t.test_cases = tx_gp2_test_cases,\n+};\n+\n+kunit_test_suite(tx_gp2_test_suite);\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/tx.c b/drivers/net/wireless/intel/iwlwifi/mld/tx.c\nindex 2df6643a5aa80..fc501ac0c1f29 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/tx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/tx.c\n@@ -2,6 +2,7 @@\n /*\n  * Copyright (C) 2024 - 2026 Intel Corporation\n  */\n+#include \u003clinux/timekeeping.h\u003e\n #include \u003cnet/ip.h\u003e\n \n #include \"tx.h\"\n@@ -20,6 +21,133 @@\n \n #define MAX_ANT_NUM 2\n \n+static u32 iwl_mld_tx_gp2_host_us(void)\n+{\n+\treturn div_u64(ktime_get_boottime_ns(), NSEC_PER_USEC);\n+}\n+\n+/* Returns the gp2 for the TX command, or 0 to leave the frame unstamped.\n+ * Sets @refresh when the estimate expired or is about to.\n+ */\n+VISIBLE_IF_IWLWIFI_KUNIT u32\n+iwl_mld_tx_gp2_from_est(u32 delta_us, unsigned long valid_until, u32 host_us,\n+\t\t\tunsigned long now, bool *refresh)\n+{\n+\tu32 gp2;\n+\n+\t*refresh = time_after_eq(now, valid_until -\n+\t\t\t\t IWL_MLD_TX_GP2_REFRESH_MARGIN);\n+\n+\tif (time_after_eq(now, valid_until))\n+\t\treturn 0;\n+\n+\tgp2 = host_us + delta_us;\n+\n+\t/* 0 means no timestamp; use 1 for a valid wrapped value. */\n+\treturn gp2 ?: 1;\n+}\n+EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_mld_tx_gp2_from_est);\n+\n+static u32\n+iwl_mld_tx_gp2_timestamp(struct iwl_mld *mld)\n+{\n+\tunsigned long valid_until =\n+\t\tatomic_long_read_acquire(\u0026mld-\u003etx_gp2.valid_until);\n+\tbool refresh = false;\n+\tu32 gp2;\n+\n+\tif (!valid_until)\n+\t\treturn 0;\n+\n+\tgp2 = iwl_mld_tx_gp2_from_est(atomic_read(\u0026mld-\u003etx_gp2.delta_us),\n+\t\t\t\t      valid_until, iwl_mld_tx_gp2_host_us(),\n+\t\t\t\t      jiffies, \u0026refresh);\n+\n+\tif (refresh)\n+\t\twiphy_delayed_work_queue(mld-\u003ewiphy, \u0026mld-\u003etx_gp2.wk, 0);\n+\n+\treturn gp2;\n+}\n+\n+static void iwl_mld_tx_gp2_refresh(struct iwl_mld *mld)\n+{\n+\tunsigned long valid_until, delay;\n+\tu32 gp2, host_us;\n+\n+\tlockdep_assert_wiphy(mld-\u003ewiphy);\n+\n+\tif (!mld-\u003efw_status.running)\n+\t\treturn;\n+\n+#ifdef CONFIG_PM_SLEEP\n+\tif (mld-\u003efw_status.in_d3)\n+\t\treturn;\n+#endif\n+\n+\tif (iwl_mld_get_systime(mld, \u0026gp2))\n+\t\tgoto retry;\n+\n+\thost_us = iwl_mld_tx_gp2_host_us();\n+\tvalid_until = jiffies + IWL_MLD_TX_GP2_VALID_PERIOD;\n+\n+\t/* Keep arithmetic in u32 to match firmware wraparound semantics. */\n+\tatomic_set(\u0026mld-\u003etx_gp2.delta_us, gp2 - host_us);\n+\tatomic_long_set_release(\u0026mld-\u003etx_gp2.valid_until, valid_until ?: 1);\n+\n+\tIWL_DEBUG_TX(mld, \"gp2 sync: gp2=%u host_us=%u delta_us=%u\\n\",\n+\t\t     gp2, host_us, gp2 - host_us);\n+\treturn;\n+\n+retry:\n+\t/* Stop new TX readers from requesting immediate retries. */\n+\tatomic_long_set(\u0026mld-\u003etx_gp2.valid_until, 0);\n+\tdelay = round_jiffies_relative(IWL_MLD_TX_GP2_RETRY_PERIOD);\n+\twiphy_delayed_work_queue(mld-\u003ewiphy, \u0026mld-\u003etx_gp2.wk, delay);\n+}\n+\n+static void iwl_mld_tx_gp2_wk(struct wiphy *wiphy, struct wiphy_work *wk)\n+{\n+\tstruct iwl_mld *mld = container_of(wk, struct iwl_mld, tx_gp2.wk.work);\n+\tunsigned long valid_until = atomic_long_read(\u0026mld-\u003etx_gp2.valid_until);\n+\n+\t/* TX may have queued this work using an older estimate. */\n+\tif (valid_until \u0026\u0026\n+\t    time_before(jiffies, valid_until - IWL_MLD_TX_GP2_REFRESH_MARGIN))\n+\t\treturn;\n+\n+\tiwl_mld_tx_gp2_refresh(mld);\n+}\n+\n+void iwl_mld_tx_gp2_init(struct iwl_mld *mld)\n+{\n+\tatomic_set(\u0026mld-\u003etx_gp2.delta_us, 0);\n+\tatomic_long_set(\u0026mld-\u003etx_gp2.valid_until, 0);\n+\twiphy_delayed_work_init(\u0026mld-\u003etx_gp2.wk, iwl_mld_tx_gp2_wk);\n+}\n+\n+void iwl_mld_tx_gp2_start(struct iwl_mld *mld)\n+{\n+\tlockdep_assert_wiphy(mld-\u003ewiphy);\n+\n+\tif (iwl_fw_lookup_cmd_ver(mld-\u003efw, TX_CMD, 0) \u003c 12)\n+\t\treturn;\n+\n+\tiwl_mld_tx_gp2_refresh(mld);\n+}\n+\n+/* TX is quiesced before stopping the refresh work. */\n+void iwl_mld_tx_gp2_stop(struct iwl_mld *mld)\n+{\n+\tlockdep_assert_wiphy(mld-\u003ewiphy);\n+\n+\tif (iwl_fw_lookup_cmd_ver(mld-\u003efw, TX_CMD, 0) \u003c 12)\n+\t\treturn;\n+\n+\twiphy_delayed_work_cancel(mld-\u003ewiphy, \u0026mld-\u003etx_gp2.wk);\n+\n+\tatomic_long_set(\u0026mld-\u003etx_gp2.valid_until, 0);\n+}\n+\n /* Toggles between TX antennas. Receives the bitmask of valid TX antennas and\n  * the *index* used for the last TX, and returns the next valid *index* to use.\n  * In order to set it in the tx_cmd, must do BIT(idx).\n@@ -588,6 +716,9 @@ iwl_mld_fill_tx_cmd(struct iwl_mld *mld, struct sk_buff *skb,\n \ttx_cmd-\u003eflags = cpu_to_le16(flags);\n \n \ttx_cmd-\u003erate_n_flags = rate_n_flags;\n+\n+\ttx_cmd-\u003edriver_timestamp =\n+\t\tcpu_to_le32(iwl_mld_tx_gp2_timestamp(mld));\n }\n \n /* Caller of this need to check that info-\u003econtrol.vif is not NULL */\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mld/tx.h b/drivers/net/wireless/intel/iwlwifi/mld/tx.h\nindex 520f15f9d33ca..a376e8c9c5005 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mld/tx.h\n+++ b/drivers/net/wireless/intel/iwlwifi/mld/tx.h\n@@ -1,11 +1,15 @@\n /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n /*\n- * Copyright (C) 2024 Intel Corporation\n+ * Copyright (C) 2024, 2026 Intel Corporation\n  */\n #ifndef __iwl_mld_tx_h__\n #define __iwl_mld_tx_h__\n \n-#include \"mld.h\"\n+#include \u003clinux/atomic.h\u003e\n+#include \u003cnet/mac80211.h\u003e\n+\n+struct iwl_mld;\n+struct iwl_rx_packet;\n \n #define IWL_MLD_INVALID_QUEUE\t\t0xFFFF\n #define IWL_MLD_INVALID_DROP_TX\t\t0xFFFE\n@@ -74,4 +78,37 @@ u8 iwl_mld_get_lowest_rate(struct iwl_mld *mld,\n void iwl_mld_tx_skb(struct iwl_mld *mld, struct sk_buff *skb,\n \t\t    struct ieee80211_txq *txq);\n \n+/**\n+ * struct iwl_mld_tx_gp2 - gp2 timestamping state for TX commands\n+ *\n+ * Reading gp2 directly in the TX path is too costly. Instead, TX lazily\n+ * schedules @wk to refresh gp2 in process context and adds @delta_us to the\n+ * host clock to timestamp queued frames.\n+ *\n+ * A zero @valid_until leaves frames unstamped, including on older firmware\n+ * without TX_CMD v12. A deadline that wraps to zero is published as one.\n+ * Failed refreshes clear @valid_until, leaving @delta_us for old readers, and\n+ * schedule a retry with %IWL_MLD_TX_GP2_RETRY_PERIOD rounded for timer\n+ * coalescing, even without further TX traffic. Old readers may retry sooner.\n+ *\n+ * @delta_us: gp2 minus host time, in microseconds, modulo 2^32;\n+ *\tvalid while @valid_until is nonzero and has not expired\n+ * @valid_until: jiffies deadline for the offset, or zero when disabled\n+ * @wk: worker that refreshes the offset and retries failures\n+ */\n+struct iwl_mld_tx_gp2 {\n+\tatomic_t delta_us;\n+\tatomic_long_t valid_until;\n+\tstruct wiphy_delayed_work wk;\n+};\n+\n+void iwl_mld_tx_gp2_init(struct iwl_mld *mld);\n+void iwl_mld_tx_gp2_start(struct iwl_mld *mld);\n+void iwl_mld_tx_gp2_stop(struct iwl_mld *mld);\n+\n+#if IS_ENABLED(CONFIG_IWLWIFI_KUNIT_TESTS)\n+u32 iwl_mld_tx_gp2_from_est(u32 delta_us, unsigned long valid_until,\n+\t\t\t    u32 host_us, unsigned long now, bool *refresh);\n+#endif\n+\n #endif /* __iwl_mld_tx_h__ */\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c\nindex 06502f57e823e..90175307a7db2 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c\n@@ -13,7 +13,7 @@\n \n #include \"mvm.h\"\n #include \"sta.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"debugfs.h\"\n #include \"iwl-modparams.h\"\n #include \"iwl-drv.h\"\n@@ -1548,7 +1548,7 @@ iwl_dbgfs_prph_reg_read(struct file *file,\n \n \tpos += scnprintf(buf + pos, bufsz - pos, \"Reg 0x%x: (0x%x)\\n\",\n \t\tmvm-\u003edbgfs_prph_reg_addr,\n-\t\tiwl_read_prph(mvm-\u003etrans, mvm-\u003edbgfs_prph_reg_addr));\n+\t\tiwl_trans_read_prph(mvm-\u003etrans, mvm-\u003edbgfs_prph_reg_addr));\n \n \treturn simple_read_from_buffer(user_buf, count, ppos, buf, pos);\n }\n@@ -1569,7 +1569,7 @@ iwl_dbgfs_prph_reg_write(struct iwl_mvm *mvm, char *buf,\n \tif (args != 2)\n \t\treturn -EINVAL;\n \n-\tiwl_write_prph(mvm-\u003etrans, mvm-\u003edbgfs_prph_reg_addr, value);\n+\tiwl_trans_write_prph(mvm-\u003etrans, mvm-\u003edbgfs_prph_reg_addr, value);\n \n out:\n \treturn count;\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c\nindex 8d7f60dcd0270..4c39a452564da 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c\n@@ -7,7 +7,7 @@\n #include \u003clinux/math64.h\u003e\n #include \u003cnet/cfg80211.h\u003e\n #include \"mvm.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"constants.h\"\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c\nindex c3402f5e47a03..ae109e3ea141c 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c\n@@ -263,7 +263,7 @@ static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,\n static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm)\n {\n #define IWL_FW_PRINT_REG_INFO(reg_name) \\\n-\tIWL_ERR(mvm, #reg_name \": 0x%x\\n\", iwl_read_umac_prph(trans, reg_name))\n+\tIWL_ERR(mvm, #reg_name \": 0x%x\\n\", iwl_trans_read_umac_prph(trans, reg_name))\n \n \tstruct iwl_trans *trans = mvm-\u003etrans;\n \tenum iwl_device_family device_family = trans-\u003emac_cfg-\u003edevice_family;\n@@ -332,13 +332,13 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,\n \t    IWL_DEVICE_FAMILY_AX210) {\n \t\t/* print these registers regardless of alive fail/success */\n \t\tIWL_INFO(mvm, \"WFPM_UMAC_PD_NOTIFICATION: 0x%x\\n\",\n-\t\t\t iwl_read_umac_prph(mvm-\u003etrans, WFPM_ARC1_PD_NOTIFICATION));\n+\t\t\t iwl_trans_read_umac_prph(mvm-\u003etrans, WFPM_ARC1_PD_NOTIFICATION));\n \t\tIWL_INFO(mvm, \"WFPM_LMAC2_PD_NOTIFICATION: 0x%x\\n\",\n-\t\t\t iwl_read_umac_prph(mvm-\u003etrans, WFPM_LMAC2_PD_NOTIFICATION));\n+\t\t\t iwl_trans_read_umac_prph(mvm-\u003etrans, WFPM_LMAC2_PD_NOTIFICATION));\n \t\tIWL_INFO(mvm, \"WFPM_AUTH_KEY_0: 0x%x\\n\",\n-\t\t\t iwl_read_umac_prph(mvm-\u003etrans, SB_MODIFY_CFG_FLAG));\n+\t\t\t iwl_trans_read_umac_prph(mvm-\u003etrans, SB_MODIFY_CFG_FLAG));\n \t\tIWL_INFO(mvm, \"CNVI_SCU_SEQ_DATA_DW9: 0x%x\\n\",\n-\t\t\t iwl_read_prph(mvm-\u003etrans, CNVI_SCU_SEQ_DATA_DW9));\n+\t\t\t iwl_trans_read_prph(mvm-\u003etrans, CNVI_SCU_SEQ_DATA_DW9));\n \t}\n \n \tif (ret) {\n@@ -349,15 +349,15 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,\n \t\t\t\t\tIWL_DEVICE_FAMILY_22000) {\n \t\t\tIWL_ERR(mvm,\n \t\t\t\t\"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\\n\",\n-\t\t\t\tiwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),\n-\t\t\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t\t\t   UMAG_SB_CPU_2_STATUS));\n+\t\t\t\tiwl_trans_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),\n+\t\t\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t\t\t UMAG_SB_CPU_2_STATUS));\n \t\t} else if (trans-\u003emac_cfg-\u003edevice_family \u003e=\n \t\t\t   IWL_DEVICE_FAMILY_8000) {\n \t\t\tIWL_ERR(mvm,\n \t\t\t\t\"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\\n\",\n-\t\t\t\tiwl_read_prph(trans, SB_CPU_1_STATUS),\n-\t\t\t\tiwl_read_prph(trans, SB_CPU_2_STATUS));\n+\t\t\t\tiwl_trans_read_prph(trans, SB_CPU_1_STATUS),\n+\t\t\t\tiwl_trans_read_prph(trans, SB_CPU_2_STATUS));\n \t\t}\n \n \t\tiwl_mvm_print_pd_notification(mvm);\n@@ -374,15 +374,15 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,\n \t\t} else if (trans-\u003emac_cfg-\u003edevice_family \u003e=\n \t\t\t\t\tIWL_DEVICE_FAMILY_9000) {\n \t\t\tIWL_ERR(mvm, \"UMAC PC: 0x%x\\n\",\n-\t\t\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t\t\t   UREG_UMAC_CURRENT_PC));\n+\t\t\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t\t\t UREG_UMAC_CURRENT_PC));\n \t\t\tIWL_ERR(mvm, \"LMAC PC: 0x%x\\n\",\n-\t\t\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t\t\t   UREG_LMAC1_CURRENT_PC));\n+\t\t\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t\t\t UREG_LMAC1_CURRENT_PC));\n \t\t\tif (iwl_mvm_is_cdb_supported(mvm))\n \t\t\t\tIWL_ERR(mvm, \"LMAC2 PC: 0x%x\\n\",\n-\t\t\t\t\tiwl_read_umac_prph(trans,\n-\t\t\t\t\t\tUREG_LMAC2_CURRENT_PC));\n+\t\t\t\t\tiwl_trans_read_umac_prph(trans,\n+\t\t\t\t\t\t\t\t UREG_LMAC2_CURRENT_PC));\n \t\t}\n \n \t\tif (ret == -ETIMEDOUT \u0026\u0026 !mvm-\u003efw_product_reset)\n@@ -616,7 +616,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)\n \tmvm-\u003erfkill_safe_init_done = false;\n \n \tif (mvm-\u003etrans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210) {\n-\t\tsb_cfg = iwl_read_umac_prph(mvm-\u003etrans, SB_MODIFY_CFG_FLAG);\n+\t\tsb_cfg = iwl_trans_read_umac_prph(mvm-\u003etrans, SB_MODIFY_CFG_FLAG);\n \t\t/* if needed, we'll reset this on our way out later */\n \t\tmvm-\u003efw_product_reset = sb_cfg == SB_CFG_RESIDES_IN_ROM;\n \t\tif (mvm-\u003efw_product_reset \u0026\u0026 iwl_mei_pldr_req())\n@@ -640,8 +640,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)\n \t\t/* if we needed reset then fail here, but notify and remove */\n \t\tif (mvm-\u003efw_product_reset) {\n \t\t\tiwl_mei_alive_notif(false);\n-\t\t\tiwl_trans_pcie_reset(mvm-\u003etrans,\n-\t\t\t\t\t     IWL_RESET_MODE_RESCAN);\n+\t\t\tiwl_trans_reset(mvm-\u003etrans, IWL_RESET_MODE_RESCAN);\n \t\t}\n \n \t\tgoto error;\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/led.c b/drivers/net/wireless/intel/iwlwifi/mvm/led.c\nindex c3cc1ea3ccc93..ac238c9638559 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/led.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/led.c\n@@ -1,10 +1,10 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /*\n- * Copyright (C) 2012-2014, 2018-2019, 2025 Intel Corporation\n+ * Copyright (C) 2012-2014, 2018-2019, 2025-2026 Intel Corporation\n  * Copyright (C) 2017 Intel Deutschland GmbH\n  */\n #include \u003clinux/leds.h\u003e\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-csr.h\"\n #include \"mvm.h\"\n \n@@ -38,8 +38,8 @@ static void iwl_mvm_led_set(struct iwl_mvm *mvm, bool on)\n \t\treturn;\n \t}\n \n-\tiwl_write32(mvm-\u003etrans, CSR_LED_REG,\n-\t\t    on ? CSR_LED_REG_TURN_ON : CSR_LED_REG_TURN_OFF);\n+\tiwl_trans_write32(mvm-\u003etrans, CSR_LED_REG,\n+\t\t\t  on ? CSR_LED_REG_TURN_ON : CSR_LED_REG_TURN_OFF);\n }\n \n static void iwl_led_brightness_set(struct led_classdev *led_cdev,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c\nindex b2c5be22c293c..509e80fa0df5e 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c\n@@ -7,7 +7,7 @@\n #include \u003clinux/etherdevice.h\u003e\n #include \u003clinux/crc32.h\u003e\n #include \u003cnet/mac80211.h\u003e\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"fw-api.h\"\n #include \"mvm.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c\nindex a4f3d3c2bd350..daa05339e3fbf 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c\n@@ -19,7 +19,7 @@\n \n #include \"iwl-drv.h\"\n #include \"iwl-op-mode.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"mvm.h\"\n #include \"sta.h\"\n #include \"time-event.h\"\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c\nindex 93d5cab87f645..1832514573612 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c\n@@ -20,7 +20,6 @@\n #include \"iwl-phy-db.h\"\n #include \"iwl-nvm-utils.h\"\n #include \"iwl-csr.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-prph.h\"\n #include \"rs.h\"\n #include \"fw/api/scan.h\"\n@@ -138,9 +137,9 @@ static void iwl_mvm_nic_config(struct iwl_op_mode *op_mode)\n \t * to lose ownership and not being able to obtain it back.\n \t */\n \tif (!mvm-\u003etrans-\u003emac_cfg-\u003ebase-\u003eapmg_not_supported)\n-\t\tiwl_set_bits_mask_prph(mvm-\u003etrans, APMG_PS_CTRL_REG,\n-\t\t\t\t       APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,\n-\t\t\t\t       ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);\n+\t\tiwl_trans_set_bits_mask_prph(mvm-\u003etrans, APMG_PS_CTRL_REG,\n+\t\t\t\t\t     APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,\n+\t\t\t\t\t     ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);\n }\n \n static void iwl_mvm_rx_monitor_notif(struct iwl_mvm *mvm,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c\nindex a94eaca0b3ed5..c12eda75317d1 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c\n@@ -10,7 +10,7 @@\n \n #include \"mvm.h\"\n #include \"fw/api/scan.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-utils.h\"\n \n #define IWL_DENSE_EBS_SCAN_RATIO 5\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c b/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c\nindex a7cd2e4ba1ae9..6aac71cfccb3e 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c\n@@ -2,12 +2,12 @@\n /*\n  * Copyright (C) 2014 Intel Mobile Communications GmbH\n  * Copyright (C) 2017 Intel Deutschland GmbH\n- * Copyright (C) 2018-2020, 2022-2025 Intel Corporation\n+ * Copyright (C) 2018-2020, 2022-2026 Intel Corporation\n  */\n #include \u003clinux/etherdevice.h\u003e\n #include \"mvm.h\"\n #include \"time-event.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n \n #define TU_TO_US(x) (x * 1024)\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c\nindex 93b46c9e2333d..5a800d3f2a98f 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c\n@@ -12,7 +12,6 @@\n #include \"fw-api.h\"\n #include \"time-event.h\"\n #include \"mvm.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-prph.h\"\n \n /*\ndiff --git a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c\nindex 2fd4a99611450..e97ab2c9e5ba7 100644\n--- a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c\n+++ b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c\n@@ -7,7 +7,7 @@\n #include \u003cnet/mac80211.h\u003e\n \n #include \"iwl-debug.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-prph.h\"\n #include \"iwl-csr.h\"\n #include \"mvm.h\"\n@@ -1159,7 +1159,7 @@ u32 iwl_mvm_get_systime(struct iwl_mvm *mvm)\n \t    mvm-\u003etrans-\u003emac_cfg-\u003ebase-\u003egp2_reg_addr)\n \t\treg_addr = mvm-\u003etrans-\u003emac_cfg-\u003ebase-\u003egp2_reg_addr;\n \n-\treturn iwl_read_prph(mvm-\u003etrans, reg_addr);\n+\treturn iwl_trans_read_prph(mvm-\u003etrans, reg_addr);\n }\n \n void iwl_mvm_get_sync_time(struct iwl_mvm *mvm, int clock_type,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c\nindex c75210829ec94..0009a05511af1 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c\n@@ -7,6 +7,7 @@\n #include \"iwl-fh.h\"\n #include \"iwl-context-info-v2.h\"\n #include \"internal.h\"\n+#include \"pcie/utils.h\"\n #include \"iwl-prph.h\"\n \n static const struct dmi_system_id dmi_force_scu_active_approved_list[] = {\n@@ -314,12 +315,12 @@ void iwl_pcie_ctxt_info_v2_kick(struct iwl_trans *trans)\n \tiwl_enable_fw_load_int_ctx_info(trans, trans-\u003edo_top_reset);\n \n \t/* kick FW self load */\n-\tiwl_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie-\u003ectxt_info_dma_addr);\n-\tiwl_write64(trans, CSR_IML_DATA_ADDR, trans_pcie-\u003eiml_dma_addr);\n-\tiwl_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie-\u003eiml_len);\n+\tiwl_pcie_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie-\u003ectxt_info_dma_addr);\n+\tiwl_pcie_write64(trans, CSR_IML_DATA_ADDR, trans_pcie-\u003eiml_dma_addr);\n+\tiwl_trans_pcie_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie-\u003eiml_len);\n \n-\tiwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,\n-\t\t    CSR_AUTO_FUNC_BOOT_ENA);\n+\tiwl_trans_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,\n+\t\t\t  CSR_AUTO_FUNC_BOOT_ENA);\n }\n \n void iwl_pcie_ctxt_info_v2_free(struct iwl_trans *trans, bool alive)\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c\nindex 23ec968577bd9..bc90a2714251a 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c\n@@ -7,6 +7,7 @@\n #include \"iwl-fh.h\"\n #include \"iwl-context-info.h\"\n #include \"internal.h\"\n+#include \"utils.h\"\n #include \"iwl-prph.h\"\n \n static void *_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,\n@@ -245,7 +246,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,\n \t\tiwl_pcie_apply_destination(trans);\n \n \t/* kick FW self load */\n-\tiwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie-\u003ectxt_info_dma_addr);\n+\tiwl_pcie_write64(trans, CSR_CTXT_INFO_BA, trans_pcie-\u003ectxt_info_dma_addr);\n \n \t/* Context info will be released upon alive or failure to get one */\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c\nindex 905482419a9af..24012005ccb87 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c\n@@ -1252,7 +1252,7 @@ static int _iwl_pci_resume(struct device *device, bool restore)\n \t\t * For older devices, just try silently to grab the NIC.\n \t\t */\n \t\tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\t\tu32 scratch = iwl_read32(trans, CSR_FUNC_SCRATCH);\n+\t\t\tu32 scratch = iwl_trans_pcie_read32(trans, CSR_FUNC_SCRATCH);\n \n \t\t\tif (!(scratch \u0026 CSR_FUNC_SCRATCH_POWER_OFF_MASK) ||\n \t\t\t    scratch == ~0U) {\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h\nindex e6b1cb559a0a6..01bfc1492c848 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h\n@@ -18,12 +18,22 @@\n #include \"iwl-fh.h\"\n #include \"iwl-csr.h\"\n #include \"iwl-trans.h\"\n+#include \"iwl-devtrace.h\"\n #include \"iwl-debug.h\"\n-#include \"iwl-io.h\"\n #include \"iwl-op-mode.h\"\n #include \"iwl-drv.h\"\n #include \"iwl-context-info.h\"\n \n+/* transport-specific register accessors (bus implementation) */\n+void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val);\n+void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val);\n+u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs);\n+u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg);\n+void iwl_pcie_write_prph_no_grab(struct iwl_trans *trans, u32 addr, u32 val);\n+\n+/* bus-specific transport operations table */\n+extern const struct iwl_trans_ops iwl_trans_pcie_ops;\n+\n /*\n  * RX related structures and functions\n  */\n@@ -593,7 +603,7 @@ static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)\n \t * write 1 clear (W1C) register, meaning that it's being clear\n \t * by writing 1 to the bit.\n \t */\n-\tiwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));\n }\n \n static inline struct iwl_trans *\n@@ -889,18 +899,18 @@ static inline void _iwl_disable_interrupts(struct iwl_trans *trans)\n \tclear_bit(STATUS_INT_ENABLED, \u0026trans-\u003estatus);\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\t/* disable interrupts from uCode/NIC to host */\n-\t\tiwl_write32(trans, CSR_INT_MASK, 0x00000000);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, 0x00000000);\n \n \t\t/* acknowledge/clear/reset any interrupts still pending\n \t\t * from uCode or flow handler (Rx/Tx DMA) */\n-\t\tiwl_write32(trans, CSR_INT, 0xffffffff);\n-\t\tiwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT, 0xffffffff);\n+\t\tiwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);\n \t} else {\n \t\t/* disable all the interrupt we might use */\n-\t\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n-\t\t\t    trans_pcie-\u003efh_init_mask);\n-\t\tiwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n-\t\t\t    trans_pcie-\u003ehw_init_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n+\t\t\t\t       trans_pcie-\u003efh_init_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n+\t\t\t\t       trans_pcie-\u003ehw_init_mask);\n \t\ttrans_pcie-\u003efh_mask = 0;\n \t\ttrans_pcie-\u003ehw_mask = 0;\n \t}\n@@ -958,7 +968,7 @@ static inline void _iwl_enable_interrupts(struct iwl_trans *trans)\n \tset_bit(STATUS_INT_ENABLED, \u0026trans-\u003estatus);\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\ttrans_pcie-\u003einta_mask = CSR_INI_SET_MASK;\n-\t\tiwl_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n \t} else {\n \t\t/*\n \t\t * fh/hw_mask keeps all the unmasked causes.\n@@ -966,10 +976,10 @@ static inline void _iwl_enable_interrupts(struct iwl_trans *trans)\n \t\t */\n \t\ttrans_pcie-\u003ehw_mask = trans_pcie-\u003ehw_init_mask;\n \t\ttrans_pcie-\u003efh_mask = trans_pcie-\u003efh_init_mask;\n-\t\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n-\t\t\t    ~trans_pcie-\u003efh_mask);\n-\t\tiwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n-\t\t\t    ~trans_pcie-\u003ehw_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n+\t\t\t\t       ~trans_pcie-\u003efh_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n+\t\t\t\t       ~trans_pcie-\u003ehw_mask);\n \t}\n }\n \n@@ -985,7 +995,7 @@ static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)\n {\n \tstruct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \n-\tiwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);\n \ttrans_pcie-\u003ehw_mask = msk;\n }\n \n@@ -993,7 +1003,7 @@ static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)\n {\n \tstruct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \n-\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);\n \ttrans_pcie-\u003efh_mask = msk;\n }\n \n@@ -1004,10 +1014,10 @@ static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)\n \tIWL_DEBUG_ISR(trans, \"Enabling FW load interrupt\\n\");\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\ttrans_pcie-\u003einta_mask = CSR_INT_BIT_FH_TX;\n-\t\tiwl_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n \t} else {\n-\t\tiwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n-\t\t\t    trans_pcie-\u003ehw_init_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,\n+\t\t\t\t       trans_pcie-\u003ehw_init_mask);\n \t\tiwl_enable_fh_int_msk_msix(trans,\n \t\t\t\t\t   MSIX_FH_INT_CAUSES_D2S_CH0_NUM);\n \t}\n@@ -1034,7 +1044,7 @@ static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans,\n \t\telse\n \t\t\ttrans_pcie-\u003einta_mask =  CSR_INT_BIT_ALIVE |\n \t\t\t\t\t\t CSR_INT_BIT_FH_RX;\n-\t\tiwl_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n \t} else {\n \t\tu32 val = top_reset ? MSIX_HW_INT_CAUSES_REG_RESET_DONE\n \t\t\t\t    : MSIX_HW_INT_CAUSES_REG_ALIVE;\n@@ -1081,10 +1091,10 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)\n \tIWL_DEBUG_ISR(trans, \"Enabling rfkill interrupt\\n\");\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\ttrans_pcie-\u003einta_mask = CSR_INT_BIT_RF_KILL;\n-\t\tiwl_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie-\u003einta_mask);\n \t} else {\n-\t\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n-\t\t\t    trans_pcie-\u003efh_init_mask);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,\n+\t\t\t\t       trans_pcie-\u003efh_init_mask);\n \t\ttrans_pcie-\u003efh_mask = 0;\n \t\tiwl_enable_hw_int_msk_msix(trans,\n \t\t\t\t\t   MSIX_HW_INT_CAUSES_REG_RF_KILL);\n@@ -1096,8 +1106,8 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)\n \t\t * when we power down the device we need set the bit to allow it\n \t\t * to wake up the PCI-E bus for RF-kill interrupts.\n \t\t */\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);\n \t}\n }\n \n@@ -1112,7 +1122,7 @@ static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)\n \tif (trans_pcie-\u003edebug_rfkill == 1)\n \t\treturn true;\n \n-\treturn !(iwl_read32(trans, CSR_GP_CNTRL) \u0026\n+\treturn !(iwl_trans_pcie_read32(trans, CSR_GP_CNTRL) \u0026\n \t\tCSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);\n }\n \n@@ -1136,16 +1146,12 @@ void iwl_trans_pcie_op_mode_enter(struct iwl_trans *trans);\n int _iwl_trans_pcie_start_hw(struct iwl_trans *trans);\n int iwl_trans_pcie_start_hw(struct iwl_trans *trans);\n void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans);\n-void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val);\n-void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val);\n-u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs);\n-u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg);\n-void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val);\n int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,\n \t\t\t    void *buf, int dwords);\n int iwl_trans_pcie_read_mem_no_grab(struct iwl_trans *trans, u32 addr,\n \t\t\t\t    void *buf, u32 dwords);\n int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership);\n+void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans);\n struct iwl_trans_dump_data *\n iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,\n \t\t\t const struct iwl_dump_sanitize_ops *sanitize_ops,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c\nindex db3933b0d1979..f033bb51dcca3 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c\n@@ -9,8 +9,9 @@\n #include \u003clinux/gfp.h\u003e\n \n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"internal.h\"\n+#include \"pcie/utils.h\"\n #include \"iwl-op-mode.h\"\n #include \"iwl-context-info-v2.h\"\n #include \"fw/dbg.h\"\n@@ -146,18 +147,18 @@ int iwl_pcie_rx_stop(struct iwl_trans *trans)\n {\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_AX210) {\n \t\t/* TODO: remove this once fw does it */\n-\t\tiwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0);\n-\t\treturn iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210,\n-\t\t\t\t\t      RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);\n+\t\tiwl_trans_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0);\n+\t\treturn iwl_pcie_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210,\n+\t\t\t\t\t\t   RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);\n \t} else if (trans-\u003emac_cfg-\u003emq_rx_supported) {\n-\t\tiwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);\n-\t\treturn iwl_poll_prph_bit(trans, RFH_GEN_STATUS,\n-\t\t\t\t\t   RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);\n+\t\tiwl_trans_write_prph(trans, RFH_RXF_DMA_CFG, 0);\n+\t\treturn iwl_pcie_poll_prph_bit(trans, RFH_GEN_STATUS,\n+\t\t\t\t\t      RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);\n \t} else {\n-\t\tiwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);\n-\t\treturn iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,\n-\t\t\t\t\t   FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,\n-\t\t\t\t\t   1000);\n+\t\tiwl_trans_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);\n+\t\treturn iwl_pcie_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,\n+\t\t\t\t\t\tFH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,\n+\t\t\t\t\t\t1000);\n \t}\n }\n \n@@ -178,13 +179,13 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,\n \t */\n \tif (!trans-\u003emac_cfg-\u003ebase-\u003eshadow_reg_enable \u0026\u0026\n \t    test_bit(STATUS_TPOWER_PMI, \u0026trans-\u003estatus)) {\n-\t\treg = iwl_read32(trans, CSR_UCODE_DRV_GP1);\n+\t\treg = iwl_trans_pcie_read32(trans, CSR_UCODE_DRV_GP1);\n \n \t\tif (reg \u0026 CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {\n \t\t\tIWL_DEBUG_INFO(trans, \"Rx queue requesting wakeup, GP1 = 0x%x\\n\",\n \t\t\t\t       reg);\n-\t\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \t\t\trxq-\u003eneed_update = true;\n \t\t\treturn;\n \t\t}\n@@ -192,13 +193,13 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,\n \n \trxq-\u003ewrite_actual = round_down(rxq-\u003ewrite, 8);\n \tif (!trans-\u003emac_cfg-\u003emq_rx_supported)\n-\t\tiwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq-\u003ewrite_actual);\n+\t\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq-\u003ewrite_actual);\n \telse if (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_write32(trans, HBUS_TARG_WRPTR, rxq-\u003ewrite_actual |\n-\t\t\t    HBUS_TARG_WRPTR_RX_Q(rxq-\u003eid));\n+\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, rxq-\u003ewrite_actual |\n+\t\t\t\t       HBUS_TARG_WRPTR_RX_Q(rxq-\u003eid));\n \telse\n-\t\tiwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq-\u003eid),\n-\t\t\t    rxq-\u003ewrite_actual);\n+\t\tiwl_trans_pcie_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq-\u003eid),\n+\t\t\t\t       rxq-\u003ewrite_actual);\n }\n \n static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)\n@@ -854,22 +855,22 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)\n \t\treturn;\n \n \t/* Stop Rx DMA */\n-\tiwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);\n+\tiwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);\n \t/* reset and flush pointers */\n-\tiwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);\n-\tiwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);\n-\tiwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);\n+\tiwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);\n+\tiwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);\n+\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);\n \n \t/* Reset driver's Rx queue write index */\n-\tiwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);\n+\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);\n \n \t/* Tell device where to find RBD circular buffer in DRAM */\n-\tiwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,\n-\t\t    (u32)(rxq-\u003ebd_dma \u003e\u003e 8));\n+\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,\n+\t\t\t       (u32)(rxq-\u003ebd_dma \u003e\u003e 8));\n \n \t/* Tell device where in DRAM to update its Rx status */\n-\tiwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,\n-\t\t    rxq-\u003erb_stts_dma \u003e\u003e 4);\n+\tiwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,\n+\t\t\t       rxq-\u003erb_stts_dma \u003e\u003e 4);\n \n \t/* Enable Rx DMA\n \t * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in\n@@ -879,22 +880,22 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)\n \t * RB timeout 0x10\n \t * 256 RBDs\n \t */\n-\tiwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,\n-\t\t    FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |\n-\t\t    FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |\n-\t\t    FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |\n-\t\t    rb_size |\n-\t\t    (RX_RB_TIMEOUT \u003c\u003c FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |\n-\t\t    (rfdnlog \u003c\u003c FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));\n+\tiwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,\n+\t\t\t       FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |\n+\t\t\t       FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |\n+\t\t\t       FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |\n+\t\t\t       rb_size |\n+\t\t\t       (RX_RB_TIMEOUT \u003c\u003c FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |\n+\t\t\t       (rfdnlog \u003c\u003c FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));\n \n \tiwl_trans_release_nic_access(trans);\n \n \t/* Set interrupt coalescing timer to default (2048 usecs) */\n-\tiwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n+\tiwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n \n \t/* W/A for interrupt coalescing bug in 7260 and 3160 */\n \tif (trans-\u003ecfg-\u003ehost_interrupt_operation_mode)\n-\t\tiwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);\n+\t\tiwl_trans_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);\n }\n \n static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)\n@@ -925,27 +926,27 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)\n \t\treturn;\n \n \t/* Stop Rx DMA */\n-\tiwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);\n \t/* disable free amd used rx queue operation */\n-\tiwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);\n \n \tfor (i = 0; i \u003c trans-\u003einfo.num_rxqs; i++) {\n \t\t/* Tell device where to find RBD free table in DRAM */\n-\t\tiwl_write_prph64_no_grab(trans,\n-\t\t\t\t\t RFH_Q_FRBDCB_BA_LSB(i),\n-\t\t\t\t\t trans_pcie-\u003erxq[i].bd_dma);\n+\t\tiwl_pcie_write_prph64_no_grab(trans,\n+\t\t\t\t\t      RFH_Q_FRBDCB_BA_LSB(i),\n+\t\t\t\t\t      trans_pcie-\u003erxq[i].bd_dma);\n \t\t/* Tell device where to find RBD used table in DRAM */\n-\t\tiwl_write_prph64_no_grab(trans,\n-\t\t\t\t\t RFH_Q_URBDCB_BA_LSB(i),\n-\t\t\t\t\t trans_pcie-\u003erxq[i].used_bd_dma);\n+\t\tiwl_pcie_write_prph64_no_grab(trans,\n+\t\t\t\t\t      RFH_Q_URBDCB_BA_LSB(i),\n+\t\t\t\t\t      trans_pcie-\u003erxq[i].used_bd_dma);\n \t\t/* Tell device where in DRAM to update its Rx status */\n-\t\tiwl_write_prph64_no_grab(trans,\n-\t\t\t\t\t RFH_Q_URBD_STTS_WPTR_LSB(i),\n-\t\t\t\t\t trans_pcie-\u003erxq[i].rb_stts_dma);\n+\t\tiwl_pcie_write_prph64_no_grab(trans,\n+\t\t\t\t\t      RFH_Q_URBD_STTS_WPTR_LSB(i),\n+\t\t\t\t\t      trans_pcie-\u003erxq[i].rb_stts_dma);\n \t\t/* Reset device indice tables */\n-\t\tiwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);\n-\t\tiwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);\n-\t\tiwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);\n+\t\tiwl_pcie_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);\n+\t\tiwl_pcie_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);\n+\t\tiwl_pcie_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);\n \n \t\tenabled |= BIT(i) | BIT(i + 16);\n \t}\n@@ -957,32 +958,32 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)\n \t * Drop frames that exceed RB size\n \t * 512 RBDs\n \t */\n-\tiwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,\n-\t\t\t       RFH_DMA_EN_ENABLE_VAL | rb_size |\n-\t\t\t       RFH_RXF_DMA_MIN_RB_4_8 |\n-\t\t\t       RFH_RXF_DMA_DROP_TOO_LARGE_MASK |\n-\t\t\t       RFH_RXF_DMA_RBDCB_SIZE_512);\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,\n+\t\t\t\t    RFH_DMA_EN_ENABLE_VAL | rb_size |\n+\t\t\t\t    RFH_RXF_DMA_MIN_RB_4_8 |\n+\t\t\t\t    RFH_RXF_DMA_DROP_TOO_LARGE_MASK |\n+\t\t\t\t    RFH_RXF_DMA_RBDCB_SIZE_512);\n \n \t/*\n \t * Activate DMA snooping.\n \t * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe\n \t * Default queue is 0\n \t */\n-\tiwl_write_prph_no_grab(trans, RFH_GEN_CFG,\n-\t\t\t       RFH_GEN_CFG_RFH_DMA_SNOOP |\n-\t\t\t       RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |\n-\t\t\t       RFH_GEN_CFG_SERVICE_DMA_SNOOP |\n-\t\t\t       RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,\n-\t\t\t\t\t       trans-\u003emac_cfg-\u003eintegrated ?\n-\t\t\t\t\t       RFH_GEN_CFG_RB_CHUNK_SIZE_64 :\n-\t\t\t\t\t       RFH_GEN_CFG_RB_CHUNK_SIZE_128));\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_GEN_CFG,\n+\t\t\t\t    RFH_GEN_CFG_RFH_DMA_SNOOP |\n+\t\t\t\t    RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |\n+\t\t\t\t    RFH_GEN_CFG_SERVICE_DMA_SNOOP |\n+\t\t\t\t    RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,\n+\t\t\t\t\t\t    trans-\u003emac_cfg-\u003eintegrated ?\n+\t\t\t\t\t\t    RFH_GEN_CFG_RB_CHUNK_SIZE_64 :\n+\t\t\t\t\t\t    RFH_GEN_CFG_RB_CHUNK_SIZE_128));\n \t/* Enable the relevant rx queues */\n-\tiwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);\n+\tiwl_pcie_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);\n \n \tiwl_trans_release_nic_access(trans);\n \n \t/* Set interrupt coalescing timer to default (2048 usecs) */\n-\tiwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n+\tiwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n }\n \n void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)\n@@ -1189,7 +1190,7 @@ int iwl_pcie_rx_init(struct iwl_trans *trans)\n int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)\n {\n \t/* Set interrupt coalescing timer to default (2048 usecs) */\n-\tiwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n+\tiwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);\n \n \t/*\n \t * We don't configure the RFH.\n@@ -1691,9 +1692,9 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)\n \t/* W/A for WiFi/WiMAX coex and WiMAX own the RF */\n \tif (trans-\u003ecfg-\u003einternal_wimax_coex \u0026\u0026\n \t    !trans-\u003emac_cfg-\u003ebase-\u003eapmg_not_supported \u0026\u0026\n-\t    (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) \u0026\n+\t    (!(iwl_trans_read_prph(trans, APMG_CLK_CTRL_REG) \u0026\n \t\t\t     APMS_CLK_VAL_MRB_FUNC_MODE) ||\n-\t     (iwl_read_prph(trans, APMG_PS_CTRL_REG) \u0026\n+\t     (iwl_trans_read_prph(trans, APMG_PS_CTRL_REG) \u0026\n \t\t\t    APMG_PS_CTRL_VAL_RESET_REQ))) {\n \t\tclear_bit(STATUS_SYNC_HCMD_ACTIVE, \u0026trans-\u003estatus);\n \t\tiwl_op_mode_wimax_active(trans-\u003eop_mode);\n@@ -1708,7 +1709,7 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)\n \t}\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_SC) {\n-\t\tu32 val = iwl_read32(trans, CSR_IPC_STATE);\n+\t\tu32 val = iwl_trans_pcie_read32(trans, CSR_IPC_STATE);\n \n \t\tif (val \u0026 CSR_IPC_STATE_TOP_RESET_REQ) {\n \t\t\tIWL_ERR(trans, \"FW requested TOP reset for FSEQ\\n\");\n@@ -1733,7 +1734,7 @@ static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)\n \ttrace_iwlwifi_dev_irq(trans-\u003edev);\n \n \t/* Discover which interrupts are active/pending */\n-\tinta = iwl_read32(trans, CSR_INT);\n+\tinta = iwl_trans_pcie_read32(trans, CSR_INT);\n \n \t/* the thread will service interrupts and re-enable them */\n \treturn inta;\n@@ -1850,7 +1851,7 @@ static void iwl_trans_pcie_handle_reset_interrupt(struct iwl_trans *trans)\n \tu32 state;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_SC) {\n-\t\tu32 val = iwl_read32(trans, CSR_IPC_STATE);\n+\t\tu32 val = iwl_trans_pcie_read32(trans, CSR_IPC_STATE);\n \n \t\tstate = u32_get_bits(val, CSR_IPC_STATE_RESET);\n \t\tIWL_DEBUG_ISR(trans, \"IPC state = 0x%x/%d\\n\", val, state);\n@@ -1922,8 +1923,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)\n \t\tIWL_DEBUG_ISR(trans,\n \t\t\t      \"ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\\n\",\n \t\t\t      inta, trans_pcie-\u003einta_mask,\n-\t\t\t      iwl_read32(trans, CSR_INT_MASK),\n-\t\t\t      iwl_read32(trans, CSR_FH_INT_STATUS));\n+\t\t\t      iwl_trans_pcie_read32(trans, CSR_INT_MASK),\n+\t\t\t      iwl_trans_pcie_read32(trans, CSR_FH_INT_STATUS));\n \t\tif (inta \u0026 (~trans_pcie-\u003einta_mask))\n \t\t\tIWL_DEBUG_ISR(trans,\n \t\t\t\t      \"We got a masked interrupt (0x%08x)\\n\",\n@@ -1971,11 +1972,11 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)\n \t * hardware bugs here by ACKing all the possible interrupts so that\n \t * interrupt coalescing can still be achieved.\n \t */\n-\tiwl_write32(trans, CSR_INT, inta | ~trans_pcie-\u003einta_mask);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, inta | ~trans_pcie-\u003einta_mask);\n \n \tif (iwl_have_debug_level(IWL_DL_ISR))\n \t\tIWL_DEBUG_ISR(trans, \"inta 0x%08x, enabled 0x%08x\\n\",\n-\t\t\t      inta, iwl_read32(trans, CSR_INT_MASK));\n+\t\t\t      inta, iwl_trans_pcie_read32(trans, CSR_INT_MASK));\n \n \tspin_unlock_bh(\u0026trans_pcie-\u003eirq_lock);\n \n@@ -2070,13 +2071,13 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)\n \t\tIWL_DEBUG_ISR(trans, \"Rx interrupt\\n\");\n \t\tif (inta \u0026 (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {\n \t\t\thandled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);\n-\t\t\tiwl_write32(trans, CSR_FH_INT_STATUS,\n-\t\t\t\t\tCSR_FH_INT_RX_MASK);\n+\t\t\tiwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS,\n+\t\t\t\t\t       CSR_FH_INT_RX_MASK);\n \t\t}\n \t\tif (inta \u0026 CSR_INT_BIT_RX_PERIODIC) {\n \t\t\thandled |= CSR_INT_BIT_RX_PERIODIC;\n-\t\t\tiwl_write32(trans,\n-\t\t\t\tCSR_INT, CSR_INT_BIT_RX_PERIODIC);\n+\t\t\tiwl_trans_pcie_write32(trans,\n+\t\t\t\t\t       CSR_INT, CSR_INT_BIT_RX_PERIODIC);\n \t\t}\n \t\t/* Sending RX interrupt require many steps to be done in the\n \t\t * device:\n@@ -2090,8 +2091,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)\n \t\t */\n \n \t\t/* Disable periodic interrupt; we use it as just a one-shot. */\n-\t\tiwl_write8(trans, CSR_INT_PERIODIC_REG,\n-\t\t\t    CSR_INT_PERIODIC_DIS);\n+\t\tiwl_trans_pcie_write8(trans, CSR_INT_PERIODIC_REG,\n+\t\t\t\t      CSR_INT_PERIODIC_DIS);\n \n \t\t/*\n \t\t * Enable periodic interrupt in 8 msec only if we received\n@@ -2101,8 +2102,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)\n \t\t * to extend the periodic interrupt; one-shot is enough.\n \t\t */\n \t\tif (inta \u0026 (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))\n-\t\t\tiwl_write8(trans, CSR_INT_PERIODIC_REG,\n-\t\t\t\t   CSR_INT_PERIODIC_ENA);\n+\t\t\tiwl_trans_pcie_write8(trans, CSR_INT_PERIODIC_REG,\n+\t\t\t\t\t      CSR_INT_PERIODIC_ENA);\n \n \t\tisr_stats-\u003erx++;\n \n@@ -2116,7 +2117,7 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)\n \n \t/* This \"Tx\" DMA channel is used only for loading uCode */\n \tif (inta \u0026 CSR_INT_BIT_FH_TX) {\n-\t\tiwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);\n+\t\tiwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);\n \t\tIWL_DEBUG_ISR(trans, \"uCode load interrupt\\n\");\n \t\tisr_stats-\u003etx++;\n \t\thandled |= CSR_INT_BIT_FH_TX;\n@@ -2230,10 +2231,10 @@ void iwl_pcie_reset_ict(struct iwl_trans *trans)\n \n \tIWL_DEBUG_ISR(trans, \"CSR_DRAM_INT_TBL_REG =0x%x\\n\", val);\n \n-\tiwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);\n+\tiwl_trans_pcie_write32(trans, CSR_DRAM_INT_TBL_REG, val);\n \ttrans_pcie-\u003euse_ict = true;\n \ttrans_pcie-\u003eict_index = 0;\n-\tiwl_write32(trans, CSR_INT, trans_pcie-\u003einta_mask);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, trans_pcie-\u003einta_mask);\n \t_iwl_enable_interrupts(trans);\n \tspin_unlock_bh(\u0026trans_pcie-\u003eirq_lock);\n }\n@@ -2260,7 +2261,7 @@ irqreturn_t iwl_pcie_isr(int irq, void *data)\n \t * If we have something to service, the tasklet will re-enable ints.\n \t * If we *don't* have something, we'll re-enable before leaving here.\n \t */\n-\tiwl_write32(trans, CSR_INT_MASK, 0x00000000);\n+\tiwl_trans_pcie_write32(trans, CSR_INT_MASK, 0x00000000);\n \n \treturn IRQ_WAKE_THREAD;\n }\n@@ -2290,13 +2291,13 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)\n \tlock_map_acquire(\u0026trans-\u003esync_cmd_lockdep_map);\n \n \tspin_lock_bh(\u0026trans_pcie-\u003eirq_lock);\n-\tinta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);\n-\tinta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);\n+\tinta_fh = iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);\n+\tinta_hw = iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);\n \t/*\n \t * Clear causes registers to avoid being handling the same cause.\n \t */\n-\tiwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh \u0026 inta_fh_msk);\n-\tiwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh \u0026 inta_fh_msk);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);\n \tspin_unlock_bh(\u0026trans_pcie-\u003eirq_lock);\n \n \ttrace_iwlwifi_dev_irq_msix(trans-\u003edev, entry, true, inta_fh, inta_hw);\n@@ -2311,7 +2312,7 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)\n \t\tIWL_DEBUG_ISR(trans,\n \t\t\t      \"ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\\n\",\n \t\t\t      entry-\u003eentry, inta_fh, trans_pcie-\u003efh_mask,\n-\t\t\t      iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));\n+\t\t\t      iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_MASK_AD));\n \t\tif (inta_fh \u0026 ~trans_pcie-\u003efh_mask)\n \t\t\tIWL_DEBUG_ISR(trans,\n \t\t\t\t      \"We got a masked interrupt (0x%08x)\\n\",\n@@ -2413,7 +2414,7 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)\n \t\tIWL_DEBUG_ISR(trans,\n \t\t\t      \"ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\\n\",\n \t\t\t      entry-\u003eentry, inta_hw, trans_pcie-\u003ehw_mask,\n-\t\t\t      iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));\n+\t\t\t      iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_MASK_AD));\n \t\tif (inta_hw \u0026 ~trans_pcie-\u003ehw_mask)\n \t\t\tIWL_DEBUG_ISR(trans,\n \t\t\t\t      \"We got a masked interrupt 0x%08x\\n\",\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c\nindex 39dd963920b31..dce6043fe9627 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c\n@@ -32,18 +32,18 @@ int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)\n \t * Disable L0s without affecting L1;\n \t * don't wait for ICH L0s (ICH bug W/A)\n \t */\n-\tiwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n-\t\t    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);\n+\tiwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n+\t\t\t  CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);\n \n \t/* Set FH wait threshold to maximum (HW error during stress W/A) */\n-\tiwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);\n+\tiwl_trans_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);\n \n \t/*\n \t * Enable HAP INTA (interrupt from management bus) to\n \t * wake device's PCI Express link L1a -\u003e L0s\n \t */\n-\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t    CSR_HW_IF_CONFIG_REG_HAP_WAKE);\n+\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t  CSR_HW_IF_CONFIG_REG_HAP_WAKE);\n \n \tiwl_pcie_apm_config(trans);\n \n@@ -65,14 +65,14 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)\n \t\t\tiwl_pcie_gen2_apm_init(trans);\n \n \t\t/* inform ME that we are leaving */\n-\t\tiwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t    CSR_RESET_LINK_PWR_MGMT_DISABLED);\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t    CSR_HW_IF_CONFIG_REG_WAKE_ME |\n-\t\t\t    CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);\n+\t\tiwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t  CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t  CSR_HW_IF_CONFIG_REG_WAKE_ME |\n+\t\t\t\t  CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);\n \t\tmdelay(1);\n-\t\tiwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t      CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\tiwl_trans_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t    CSR_RESET_LINK_PWR_MGMT_DISABLED);\n \t\tmdelay(5);\n \t}\n \n@@ -88,11 +88,11 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)\n \t * D0A* (powered-up Active) --\u003e D0U* (Uninitialized) state.\n \t */\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n \telse\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n }\n \n static void\n@@ -105,14 +105,14 @@ _iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans,\n \ttrans_pcie-\u003efw_reset_state = FW_RESET_REQUESTED;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_AX210)\n-\t\tiwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,\n-\t\t\t\t    UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,\n+\t\t\t\t\t  UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);\n \telse if (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210)\n-\t\tiwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n-\t\t\t\t    UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n+\t\t\t\t\t  UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);\n \telse\n-\t\tiwl_write32(trans, CSR_DOORBELL_VECTOR,\n-\t\t\t    UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);\n+\t\tiwl_trans_pcie_write32(trans, CSR_DOORBELL_VECTOR,\n+\t\t\t\t       UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);\n \n \t/* wait 200ms */\n \tret = wait_event_timeout(trans_pcie-\u003efw_reset_waitq,\n@@ -123,11 +123,11 @@ _iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans,\n \t\tu32 inta_hw;\n \n \t\tif (trans_pcie-\u003emsix_enabled) {\n-\t\t\tinta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);\n+\t\t\tinta_hw = iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);\n \t\t\treset_done =\n \t\t\t\tinta_hw \u0026 MSIX_HW_INT_CAUSES_REG_RESET_DONE;\n \t\t} else {\n-\t\t\tinta_hw = iwl_read32(trans, CSR_INT);\n+\t\t\tinta_hw = iwl_trans_pcie_read32(trans, CSR_INT);\n \t\t\treset_done = inta_hw \u0026 CSR_INT_BIT_RESET_DONE;\n \t\t}\n \n@@ -281,7 +281,7 @@ static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)\n \t\treturn -ENOMEM;\n \n \t/* enable shadow regs in HW */\n-\tiwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);\n+\tiwl_trans_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);\n \tIWL_DEBUG_INFO(trans, \"Enabling shadow registers in device\\n\");\n \n \treturn 0;\n@@ -342,7 +342,7 @@ static void iwl_pcie_get_rf_name(struct iwl_trans *trans)\n \tcase CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):\n \tcase CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):\n \tcase CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):\n-\t\tversion = iwl_read_prph(trans, CNVI_MBOX_C);\n+\t\tversion = iwl_trans_read_prph(trans, CNVI_MBOX_C);\n \t\tswitch (version) {\n \t\tcase 0x20000:\n \t\t\tpos += scnprintf(buf + pos, buflen - pos, \" B3\");\n@@ -410,7 +410,7 @@ void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans)\n \n \tstep_reg = trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_SC ?\n \t\t   CNVI_PMU_STEP_FLOW_SC : CNVI_PMU_STEP_FLOW_BZ;\n-\ttrans-\u003estep_urm = !!(iwl_read_prph(trans, step_reg) \u0026\n+\ttrans-\u003estep_urm = !!(iwl_trans_read_prph(trans, step_reg) \u0026\n \t\t\t     CNVI_PMU_STEP_FLOW_FORCE_URM);\n }\n \n@@ -434,21 +434,21 @@ static bool iwl_pcie_set_ltr(struct iwl_trans *trans)\n \tif ((trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210 ||\n \t     trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_22000) \u0026\u0026\n \t    !trans-\u003emac_cfg-\u003eintegrated) {\n-\t\tiwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);\n+\t\tiwl_trans_pcie_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);\n \t\treturn true;\n \t}\n \n \tif (trans-\u003emac_cfg-\u003eintegrated \u0026\u0026\n \t    trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_22000) {\n-\t\tiwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);\n-\t\tiwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);\n+\t\tiwl_trans_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);\n+\t\tiwl_trans_write_prph(trans, HPM_UMAC_LTR, ltr_val);\n \t\treturn true;\n \t}\n \n \tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210) {\n \t\t/* First clear the interrupt, just in case */\n-\t\tiwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,\n-\t\t\t    MSIX_HW_INT_CAUSES_REG_IML);\n+\t\tiwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,\n+\t\t\t\t       MSIX_HW_INT_CAUSES_REG_IML);\n \t\t/* In this case, unfortunately the same ROM bug exists in the\n \t\t * device (not setting LTR correctly), but we don't have control\n \t\t * over the settings from the host due to some hardware security\n@@ -475,18 +475,18 @@ static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)\n \tif (WARN_ON(!trans_pcie-\u003eiml))\n \t\treturn;\n \n-\tvalue = iwl_read32(trans, CSR_LTR_LAST_MSG);\n+\tvalue = iwl_trans_pcie_read32(trans, CSR_LTR_LAST_MSG);\n \tIWL_DEBUG_INFO(trans, \"Polling for IML load - CSR_LTR_LAST_MSG=0x%x\\n\",\n \t\t       value);\n \n \twhile (time_before(jiffies, end_time)) {\n-\t\tif (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) \u0026\n+\t\tif (iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) \u0026\n \t\t\t\tMSIX_HW_INT_CAUSES_REG_IML) {\n \t\t\tirq = true;\n \t\t\tbreak;\n \t\t}\n \t\t/* Keep the CPU and device busy. */\n-\t\tvalue = iwl_read32(trans, CSR_LTR_LAST_MSG);\n+\t\tvalue = iwl_trans_pcie_read32(trans, CSR_LTR_LAST_MSG);\n \t\tloops++;\n \t}\n \n@@ -522,7 +522,7 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,\n \n \tiwl_enable_rfkill_int(trans);\n \n-\tiwl_write32(trans, CSR_INT, 0xFFFFFFFF);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);\n \n \t/*\n \t * We enabled the RF-Kill interrupt and the handler may very\n@@ -550,12 +550,12 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,\n \t}\n \n \t/* make sure rfkill handshake bits are cleared */\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t       CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n \n \t/* clear (again), then enable host interrupts */\n-\tiwl_write32(trans, CSR_INT, 0xFFFFFFFF);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);\n \n \tret = iwl_pcie_gen2_nic_init(trans);\n \tif (ret) {\n@@ -591,14 +591,14 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n \t\tIWL_DEBUG_POWER(trans, \"function scratch register value is 0x%08x\\n\",\n-\t\t\t\tiwl_read32(trans, CSR_FUNC_SCRATCH));\n-\t\tiwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_ROM_START);\n+\t\t\t\tiwl_trans_pcie_read32(trans, CSR_FUNC_SCRATCH));\n+\t\tiwl_trans_pcie_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_ROM_START);\n \t} else if (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_AX210) {\n-\t\tiwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);\n \t} else {\n-\t\tiwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);\n+\t\tiwl_trans_write_prph(trans, UREG_CPU_INIT_RUN, 1);\n \t}\n \n \tif (keep_ram_busy)\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c\nindex bda069a6f7ebf..eda88940dd074 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c\n@@ -44,10 +44,10 @@ static void iwl_dump_host_monitor_block(struct iwl_trans *trans,\n \tint i;\n \n \tIWL_ERR(trans, \"Host monitor block 0x%x vector 0x%x\\n\", block, vec);\n-\tiwl_write32(trans, CSR_MONITOR_CFG_REG, (block \u003c\u003c 8) | vec);\n+\tiwl_trans_pcie_write32(trans, CSR_MONITOR_CFG_REG, (block \u003c\u003c 8) | vec);\n \tfor (i = 0; i \u003c iter; i++)\n \t\tIWL_ERR(trans, \"    value [iter %d]: 0x%08x\\n\",\n-\t\t\ti, iwl_read32(trans, CSR_MONITOR_STATUS_REG));\n+\t\t\ti, iwl_trans_pcie_read32(trans, CSR_MONITOR_STATUS_REG));\n }\n \n static void iwl_pcie_dump_host_monitor(struct iwl_trans *trans)\n@@ -56,7 +56,7 @@ static void iwl_pcie_dump_host_monitor(struct iwl_trans *trans)\n \tcase IWL_DEVICE_FAMILY_22000:\n \tcase IWL_DEVICE_FAMILY_AX210:\n \t\tIWL_ERR(trans, \"CSR_RESET = 0x%x\\n\",\n-\t\t\tiwl_read32(trans, CSR_RESET));\n+\t\t\tiwl_trans_pcie_read32(trans, CSR_RESET));\n \t\tiwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,\n \t\t\t\t\t    IWL_HOST_MON_BLOCK_PEMON_VEC0, 15);\n \t\tiwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,\n@@ -79,12 +79,12 @@ int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership)\n {\n \t/* Reset entire device - do controller reset (results in SHRD_HW_RST) */\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_SW_RESET);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_SW_RESET);\n \t\tusleep_range(10000, 20000);\n \t} else {\n-\t\tiwl_set_bit(trans, CSR_RESET,\n-\t\t\t    CSR_RESET_REG_FLAG_SW_RESET);\n+\t\tiwl_trans_set_bit(trans, CSR_RESET,\n+\t\t\t\t  CSR_RESET_REG_FLAG_SW_RESET);\n \t\tusleep_range(5000, 6000);\n \t}\n \n@@ -170,16 +170,16 @@ void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)\n \n static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)\n {\n-\tiwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,\n-\t\t    ((reg \u0026 0x0000ffff) | (2 \u003c\u003c 28)));\n-\treturn iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);\n+\tiwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,\n+\t\t\t       ((reg \u0026 0x0000ffff) | (2 \u003c\u003c 28)));\n+\treturn iwl_trans_pcie_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);\n }\n \n static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)\n {\n-\tiwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);\n-\tiwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,\n-\t\t    ((reg \u0026 0x0000ffff) | (3 \u003c\u003c 28)));\n+\tiwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);\n+\tiwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,\n+\t\t\t       ((reg \u0026 0x0000ffff) | (3 \u003c\u003c 28)));\n }\n \n static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)\n@@ -188,13 +188,13 @@ static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)\n \t\treturn;\n \n \tif (vaux \u0026\u0026 pci_pme_capable(to_pci_dev(trans-\u003edev), PCI_D3cold))\n-\t\tiwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,\n-\t\t\t\t       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,\n-\t\t\t\t       ~APMG_PS_CTRL_MSK_PWR_SRC);\n+\t\tiwl_trans_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,\n+\t\t\t\t\t     APMG_PS_CTRL_VAL_PWR_SRC_VAUX,\n+\t\t\t\t\t     ~APMG_PS_CTRL_MSK_PWR_SRC);\n \telse\n-\t\tiwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,\n-\t\t\t\t       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,\n-\t\t\t\t       ~APMG_PS_CTRL_MSK_PWR_SRC);\n+\t\tiwl_trans_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,\n+\t\t\t\t\t     APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,\n+\t\t\t\t\t     ~APMG_PS_CTRL_MSK_PWR_SRC);\n }\n \n /* PCI registers */\n@@ -211,7 +211,7 @@ void iwl_pcie_apm_config(struct iwl_trans *trans)\n \t * and in newer hardware they are not officially supported at\n \t * all, so we must always set the L0S_DISABLED bit.\n \t */\n-\tiwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);\n+\tiwl_trans_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);\n \n \tpcie_capability_read_word(trans_pcie-\u003epci_dev, PCI_EXP_LNKCTL, \u0026lctl);\n \ttrans_pcie-\u003epm_support = !(lctl \u0026 PCI_EXP_LNKCTL_ASPM_L0S);\n@@ -241,31 +241,31 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)\n \n \t/* Disable L0S exit timer (platform NMI Work/Around) */\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_8000)\n-\t\tiwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n-\t\t\t    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);\n+\t\tiwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n+\t\t\t\t  CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);\n \n \t/*\n \t * Disable L0s without affecting L1;\n \t *  don't wait for ICH L0s (ICH bug W/A)\n \t */\n-\tiwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n-\t\t    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);\n+\tiwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,\n+\t\t\t  CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);\n \n \t/* Set FH wait threshold to maximum (HW error during stress W/A) */\n-\tiwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);\n+\tiwl_trans_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);\n \n \t/*\n \t * Enable HAP INTA (interrupt from management bus) to\n \t * wake device's PCI Express link L1a -\u003e L0s\n \t */\n-\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t    CSR_HW_IF_CONFIG_REG_HAP_WAKE);\n+\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t  CSR_HW_IF_CONFIG_REG_HAP_WAKE);\n \n \tiwl_pcie_apm_config(trans);\n \n \t/* Configure analog phase-lock-loop before activating to D0A */\n \tif (trans-\u003emac_cfg-\u003ebase-\u003epll_cfg)\n-\t\tiwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);\n+\t\tiwl_trans_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);\n \n \tret = iwl_trans_activate_nic(trans);\n \tif (ret)\n@@ -286,11 +286,11 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)\n \t\t * just to discard the value. But that's the way the hardware\n \t\t * seems to like it.\n \t\t */\n-\t\tiwl_read_prph(trans, OSC_CLK);\n-\t\tiwl_read_prph(trans, OSC_CLK);\n-\t\tiwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);\n-\t\tiwl_read_prph(trans, OSC_CLK);\n-\t\tiwl_read_prph(trans, OSC_CLK);\n+\t\tiwl_trans_read_prph(trans, OSC_CLK);\n+\t\tiwl_trans_read_prph(trans, OSC_CLK);\n+\t\tiwl_trans_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);\n+\t\tiwl_trans_read_prph(trans, OSC_CLK);\n+\t\tiwl_trans_read_prph(trans, OSC_CLK);\n \t}\n \n \t/*\n@@ -301,17 +301,17 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)\n \t * bits already set by default in \"CLK_CTRL_REG\" after reset.\n \t */\n \tif (!trans-\u003emac_cfg-\u003ebase-\u003eapmg_not_supported) {\n-\t\tiwl_write_prph(trans, APMG_CLK_EN_REG,\n-\t\t\t       APMG_CLK_VAL_DMA_CLK_RQT);\n+\t\tiwl_trans_write_prph(trans, APMG_CLK_EN_REG,\n+\t\t\t\t     APMG_CLK_VAL_DMA_CLK_RQT);\n \t\tudelay(20);\n \n \t\t/* Disable L1-Active */\n-\t\tiwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,\n-\t\t\t\t  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);\n+\t\tiwl_trans_set_bits_prph(trans, APMG_PCIDEV_STT_REG,\n+\t\t\t\t\tAPMG_PCIDEV_STT_VAL_L1_ACT_DIS);\n \n \t\t/* Clear the interrupt in APMG if the NIC is in RFKILL */\n-\t\tiwl_write_prph(trans, APMG_RTC_INT_STT_REG,\n-\t\t\t       APMG_RTC_INT_STT_RFKILL);\n+\t\tiwl_trans_write_prph(trans, APMG_RTC_INT_STT_REG,\n+\t\t\t\t     APMG_RTC_INT_STT_RFKILL);\n \t}\n \n \tset_bit(STATUS_DEVICE_ENABLED, \u0026trans-\u003estatus);\n@@ -334,8 +334,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)\n \tu32 dl_cfg_reg;\n \n \t/* Force XTAL ON */\n-\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n+\tiwl_pcie_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n \n \tret = iwl_trans_pcie_sw_reset(trans, true);\n \n@@ -344,8 +344,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)\n \n \tif (WARN_ON(ret)) {\n \t\t/* Release XTAL ON request */\n-\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n+\t\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n \t\treturn;\n \t}\n \n@@ -353,8 +353,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)\n \t * Clear \"disable persistence\" to avoid LP XTAL resetting when\n \t * SHRD_HW_RST is applied in S3.\n \t */\n-\tiwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,\n-\t\t\t\t    APMG_PCIDEV_STT_VAL_PERSIST_DIS);\n+\tiwl_trans_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,\n+\t\t\t\t  APMG_PCIDEV_STT_VAL_PERSIST_DIS);\n \n \t/*\n \t * Force APMG XTAL to be active to prevent its disabling by HW\n@@ -386,22 +386,22 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)\n \t * Enable persistence mode to avoid LP XTAL resetting when\n \t * SHRD_HW_RST is applied in S3.\n \t */\n-\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t    CSR_HW_IF_CONFIG_REG_PERSISTENCE);\n+\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t  CSR_HW_IF_CONFIG_REG_PERSISTENCE);\n \n \t/*\n \t * Clear \"initialization complete\" bit to move adapter from\n \t * D0A* (powered-up Active) --\u003e D0U* (Uninitialized) state.\n \t */\n-\tiwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n \n \t/* Activates XTAL resources monitor */\n-\tiwl_trans_set_bit(trans, CSR_MONITOR_CFG_REG,\n-\t\t\t  CSR_MONITOR_XTAL_RESOURCES);\n+\tiwl_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,\n+\t\t\t CSR_MONITOR_XTAL_RESOURCES);\n \n \t/* Release XTAL ON request */\n-\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n+\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);\n \tudelay(10);\n \n \t/* Release APMG XTAL */\n@@ -417,18 +417,18 @@ void iwl_pcie_apm_stop_master(struct iwl_trans *trans)\n \t/* stop device's busmaster DMA activity */\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);\n \n-\t\tret = iwl_poll_bits(trans, CSR_GP_CNTRL,\n-\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,\n-\t\t\t\t    100);\n+\t\tret = iwl_trans_poll_bits(trans, CSR_GP_CNTRL,\n+\t\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,\n+\t\t\t\t\t  100);\n \t\tusleep_range(10000, 20000);\n \t} else {\n-\t\tiwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);\n+\t\tiwl_trans_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);\n \n-\t\tret = iwl_poll_bits(trans, CSR_RESET,\n-\t\t\t\t    CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);\n+\t\tret = iwl_trans_poll_bits(trans, CSR_RESET,\n+\t\t\t\t\t  CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);\n \t}\n \n \tif (ret)\n@@ -447,18 +447,18 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)\n \n \t\t/* inform ME that we are leaving */\n \t\tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_7000)\n-\t\t\tiwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,\n-\t\t\t\t\t  APMG_PCIDEV_STT_VAL_WAKE_ME);\n+\t\t\tiwl_trans_set_bits_prph(trans, APMG_PCIDEV_STT_REG,\n+\t\t\t\t\t\tAPMG_PCIDEV_STT_VAL_WAKE_ME);\n \t\telse if (trans-\u003emac_cfg-\u003edevice_family \u003e=\n \t\t\t IWL_DEVICE_FAMILY_8000) {\n-\t\t\tiwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t\t    CSR_RESET_LINK_PWR_MGMT_DISABLED);\n-\t\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t\t    CSR_HW_IF_CONFIG_REG_WAKE_ME |\n-\t\t\t\t    CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);\n+\t\t\tiwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t\t  CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t\t  CSR_HW_IF_CONFIG_REG_WAKE_ME |\n+\t\t\t\t\t  CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);\n \t\t\tmdelay(1);\n-\t\t\tiwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t\t\t      CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\t\t\tiwl_trans_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t\t\t    CSR_RESET_LINK_PWR_MGMT_DISABLED);\n \t\t}\n \t\tmdelay(5);\n \t}\n@@ -479,7 +479,7 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)\n \t * Clear \"initialization complete\" bit to move adapter from\n \t * D0A* (powered-up Active) --\u003e D0U* (Uninitialized) state.\n \t */\n-\tiwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n }\n \n static int iwl_pcie_nic_init(struct iwl_trans *trans)\n@@ -512,7 +512,7 @@ static int iwl_pcie_nic_init(struct iwl_trans *trans)\n \n \tif (trans-\u003emac_cfg-\u003ebase-\u003eshadow_reg_enable) {\n \t\t/* enable shadow regs in HW */\n-\t\tiwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);\n+\t\tiwl_trans_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);\n \t\tIWL_DEBUG_INFO(trans, \"Enabling shadow registers in device\\n\");\n \t}\n \n@@ -525,16 +525,16 @@ static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)\n {\n \tint ret;\n \n-\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t    CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);\n+\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t  CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);\n \n \t/* See if we got it */\n-\tret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t    CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,\n-\t\t\t    HW_READY_TIMEOUT);\n+\tret = iwl_trans_poll_bits(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t  CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,\n+\t\t\t\t  HW_READY_TIMEOUT);\n \n \tif (!ret)\n-\t\tiwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);\n+\t\tiwl_trans_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);\n \n \tIWL_DEBUG_INFO(trans, \"hardware%s ready\\n\", ret ? \" not\" : \"\");\n \treturn ret;\n@@ -555,16 +555,16 @@ int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)\n \t\treturn 0;\n \t}\n \n-\tiwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n-\t\t    CSR_RESET_LINK_PWR_MGMT_DISABLED);\n+\tiwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,\n+\t\t\t  CSR_RESET_LINK_PWR_MGMT_DISABLED);\n \tusleep_range(1000, 2000);\n \n \tfor (iter = 0; iter \u003c 10; iter++) {\n \t\tint t = 0;\n \n \t\t/* If HW is not ready, prepare the conditions to check again */\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t    CSR_HW_IF_CONFIG_REG_WAKE_ME);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t  CSR_HW_IF_CONFIG_REG_WAKE_ME);\n \n \t\tdo {\n \t\t\tret = iwl_pcie_set_hw_ready(trans);\n@@ -603,28 +603,28 @@ static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,\n \t\t\t\t\t    u32 dst_addr, dma_addr_t phy_addr,\n \t\t\t\t\t    u32 byte_cnt)\n {\n-\tiwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),\n-\t\t    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);\n+\tiwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),\n+\t\t\t       FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);\n \n-\tiwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),\n-\t\t    dst_addr);\n+\tiwl_trans_pcie_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),\n+\t\t\t       dst_addr);\n \n-\tiwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),\n-\t\t    phy_addr \u0026 FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);\n+\tiwl_trans_pcie_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),\n+\t\t\t       phy_addr \u0026 FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);\n \n-\tiwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),\n-\t\t    (iwl_get_dma_hi_addr(phy_addr)\n-\t\t\t\u003c\u003c FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);\n+\tiwl_trans_pcie_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),\n+\t\t\t       (iwl_get_dma_hi_addr(phy_addr)\n+\t\t\t\t\u003c\u003c FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);\n \n-\tiwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),\n-\t\t    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |\n-\t\t    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |\n-\t\t    FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);\n+\tiwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),\n+\t\t\t       BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |\n+\t\t\t       BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |\n+\t\t\t       FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);\n \n-\tiwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),\n-\t\t    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |\n-\t\t    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |\n-\t\t    FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);\n+\tiwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),\n+\t\t\t       FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |\n+\t\t\t       FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |\n+\t\t\t       FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);\n }\n \n static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,\n@@ -688,16 +688,16 @@ static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,\n \t\t\textended_addr = true;\n \n \t\tif (extended_addr)\n-\t\t\tiwl_set_bits_prph(trans, LMPM_CHICK,\n-\t\t\t\t\t  LMPM_CHICK_EXTENDED_ADDR_SPACE);\n+\t\t\tiwl_trans_set_bits_prph(trans, LMPM_CHICK,\n+\t\t\t\t\t\tLMPM_CHICK_EXTENDED_ADDR_SPACE);\n \n \t\tmemcpy(v_addr, (const u8 *)section-\u003edata + offset, copy_size);\n \t\tret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,\n \t\t\t\t\t\t   copy_size);\n \n \t\tif (extended_addr)\n-\t\t\tiwl_clear_bits_prph(trans, LMPM_CHICK,\n-\t\t\t\t\t    LMPM_CHICK_EXTENDED_ADDR_SPACE);\n+\t\t\tiwl_trans_clear_bits_prph(trans, LMPM_CHICK,\n+\t\t\t\t\t\t  LMPM_CHICK_EXTENDED_ADDR_SPACE);\n \n \t\tif (ret) {\n \t\t\tIWL_ERR(trans,\n@@ -751,9 +751,9 @@ static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,\n \t\t\treturn ret;\n \n \t\t/* Notify ucode of loaded section number and status */\n-\t\tval = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);\n+\t\tval = iwl_pcie_read_direct32(trans, FH_UCODE_LOAD_STATUS);\n \t\tval = val | (sec_num \u003c\u003c shift_param);\n-\t\tiwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);\n+\t\tiwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);\n \n \t\tsec_num = (sec_num \u003c\u003c 1) | 0x1;\n \t}\n@@ -764,18 +764,18 @@ static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,\n \n \tif (trans-\u003emac_cfg-\u003egen2) {\n \t\tif (cpu == 1)\n-\t\t\tiwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,\n-\t\t\t\t       0xFFFF);\n+\t\t\tiwl_trans_write_prph(trans, UREG_UCODE_LOAD_STATUS,\n+\t\t\t\t\t     0xFFFF);\n \t\telse\n-\t\t\tiwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,\n-\t\t\t\t       0xFFFFFFFF);\n+\t\t\tiwl_trans_write_prph(trans, UREG_UCODE_LOAD_STATUS,\n+\t\t\t\t\t     0xFFFFFFFF);\n \t} else {\n \t\tif (cpu == 1)\n-\t\t\tiwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,\n-\t\t\t\t\t   0xFFFF);\n+\t\t\tiwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS,\n+\t\t\t\t\t\t 0xFFFF);\n \t\telse\n-\t\t\tiwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,\n-\t\t\t\t\t   0xFFFFFFFF);\n+\t\t\tiwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS,\n+\t\t\t\t\t\t 0xFFFFFFFF);\n \t}\n \n \treturn 0;\n@@ -836,8 +836,8 @@ static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)\n \t    IWL_FW_INI_LOCATION_SRAM_PATH) {\n \t\tIWL_DEBUG_FW(trans, \"WRT: Applying SMEM buffer destination\\n\");\n \t\t/* set sram monitor by enabling bit 7 */\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t    CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t  CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);\n \n \t\treturn;\n \t}\n@@ -852,11 +852,11 @@ static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)\n \tIWL_DEBUG_FW(trans, \"WRT: Applying DRAM destination (alloc_id=%u)\\n\",\n \t\t     alloc_id);\n \n-\tiwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,\n-\t\t\t    frag-\u003ephysical \u003e\u003e MON_BUFF_SHIFT_VER2);\n-\tiwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,\n-\t\t\t    (frag-\u003ephysical + frag-\u003esize - 256) \u003e\u003e\n-\t\t\t    MON_BUFF_SHIFT_VER2);\n+\tiwl_trans_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,\n+\t\t\t\t  frag-\u003ephysical \u003e\u003e MON_BUFF_SHIFT_VER2);\n+\tiwl_trans_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,\n+\t\t\t\t  (frag-\u003ephysical + frag-\u003esize - 256) \u003e\u003e\n+\t\t\t\t  MON_BUFF_SHIFT_VER2);\n }\n \n void iwl_pcie_apply_destination(struct iwl_trans *trans)\n@@ -884,25 +884,25 @@ void iwl_pcie_apply_destination(struct iwl_trans *trans)\n \n \t\tswitch (dest-\u003ereg_ops[i].op) {\n \t\tcase CSR_ASSIGN:\n-\t\t\tiwl_write32(trans, addr, val);\n+\t\t\tiwl_trans_pcie_write32(trans, addr, val);\n \t\t\tbreak;\n \t\tcase CSR_SETBIT:\n-\t\t\tiwl_set_bit(trans, addr, BIT(val));\n+\t\t\tiwl_trans_set_bit(trans, addr, BIT(val));\n \t\t\tbreak;\n \t\tcase CSR_CLEARBIT:\n-\t\t\tiwl_clear_bit(trans, addr, BIT(val));\n+\t\t\tiwl_trans_clear_bit(trans, addr, BIT(val));\n \t\t\tbreak;\n \t\tcase PRPH_ASSIGN:\n-\t\t\tiwl_write_prph(trans, addr, val);\n+\t\t\tiwl_trans_write_prph(trans, addr, val);\n \t\t\tbreak;\n \t\tcase PRPH_SETBIT:\n-\t\t\tiwl_set_bits_prph(trans, addr, BIT(val));\n+\t\t\tiwl_trans_set_bits_prph(trans, addr, BIT(val));\n \t\t\tbreak;\n \t\tcase PRPH_CLEARBIT:\n-\t\t\tiwl_clear_bits_prph(trans, addr, BIT(val));\n+\t\t\tiwl_trans_clear_bits_prph(trans, addr, BIT(val));\n \t\t\tbreak;\n \t\tcase PRPH_BLOCKBIT:\n-\t\t\tif (iwl_read_prph(trans, addr) \u0026 BIT(val)) {\n+\t\t\tif (iwl_trans_read_prph(trans, addr) \u0026 BIT(val)) {\n \t\t\t\tIWL_ERR(trans,\n \t\t\t\t\t\"BIT(%u) in address 0x%x is 1, stopping FW configuration\\n\",\n \t\t\t\t\tval, addr);\n@@ -918,16 +918,16 @@ void iwl_pcie_apply_destination(struct iwl_trans *trans)\n \n monitor:\n \tif (dest-\u003emonitor_mode == EXTERNAL_MODE \u0026\u0026 fw_mon-\u003esize) {\n-\t\tiwl_write_prph(trans, le32_to_cpu(dest-\u003ebase_reg),\n-\t\t\t       fw_mon-\u003ephysical \u003e\u003e dest-\u003ebase_shift);\n+\t\tiwl_trans_write_prph(trans, le32_to_cpu(dest-\u003ebase_reg),\n+\t\t\t\t     fw_mon-\u003ephysical \u003e\u003e dest-\u003ebase_shift);\n \t\tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_8000)\n-\t\t\tiwl_write_prph(trans, le32_to_cpu(dest-\u003eend_reg),\n-\t\t\t\t       (fw_mon-\u003ephysical + fw_mon-\u003esize -\n-\t\t\t\t\t256) \u003e\u003e dest-\u003eend_shift);\n+\t\t\tiwl_trans_write_prph(trans, le32_to_cpu(dest-\u003eend_reg),\n+\t\t\t\t\t     (fw_mon-\u003ephysical + fw_mon-\u003esize -\n+\t\t\t\t\t      256) \u003e\u003e dest-\u003eend_shift);\n \t\telse\n-\t\t\tiwl_write_prph(trans, le32_to_cpu(dest-\u003eend_reg),\n-\t\t\t\t       (fw_mon-\u003ephysical + fw_mon-\u003esize) \u003e\u003e\n-\t\t\t\t       dest-\u003eend_shift);\n+\t\t\tiwl_trans_write_prph(trans, le32_to_cpu(dest-\u003eend_reg),\n+\t\t\t\t\t     (fw_mon-\u003ephysical + fw_mon-\u003esize) \u003e\u003e\n+\t\t\t\t\t     dest-\u003eend_shift);\n \t}\n }\n \n@@ -947,9 +947,9 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,\n \n \tif (image-\u003eis_dual_cpus) {\n \t\t/* set CPU2 header address */\n-\t\tiwl_write_prph(trans,\n-\t\t\t       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,\n-\t\t\t       LMPM_SECURE_CPU2_HDR_MEM_SPACE);\n+\t\tiwl_trans_write_prph(trans,\n+\t\t\t\t     LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,\n+\t\t\t\t     LMPM_SECURE_CPU2_HDR_MEM_SPACE);\n \n \t\t/* load to FW the binary sections of CPU2 */\n \t\tret = iwl_pcie_load_cpu_sections(trans, image, 2,\n@@ -964,7 +964,7 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,\n \tiwl_enable_interrupts(trans);\n \n \t/* release CPU reset */\n-\tiwl_write32(trans, CSR_RESET, 0);\n+\tiwl_trans_pcie_write32(trans, CSR_RESET, 0);\n \n \treturn 0;\n }\n@@ -982,18 +982,18 @@ static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,\n \t\tiwl_pcie_apply_destination(trans);\n \n \tIWL_DEBUG_POWER(trans, \"Original WFPM value = 0x%08X\\n\",\n-\t\t\tiwl_read_prph(trans, WFPM_GP2));\n+\t\t\tiwl_trans_read_prph(trans, WFPM_GP2));\n \n \t/*\n \t * Set default value. On resume reading the values that were\n \t * zeored can provide debug data on the resume flow.\n \t * This is for debugging only and has no functional impact.\n \t */\n-\tiwl_write_prph(trans, WFPM_GP2, 0x01010101);\n+\tiwl_trans_write_prph(trans, WFPM_GP2, 0x01010101);\n \n \t/* configure the ucode to be ready to get the secured image */\n \t/* release CPU reset */\n-\tiwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);\n+\tiwl_trans_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);\n \n \t/* load to FW the binary Secured sections of CPU1 */\n \tret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,\n@@ -1079,9 +1079,9 @@ static void iwl_pcie_map_list(struct iwl_trans *trans,\n \tint i;\n \n \tfor (i = 0; i \u003c arr_size; i++) {\n-\t\tiwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);\n-\t\tiwl_clear_bit(trans, causes[i].mask_reg,\n-\t\t\t      BIT(causes[i].bit));\n+\t\tiwl_trans_pcie_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);\n+\t\tiwl_trans_clear_bit(trans, causes[i].mask_reg,\n+\t\t\t\t    BIT(causes[i].bit));\n \t}\n }\n \n@@ -1119,19 +1119,19 @@ static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)\n \t */\n \tval = BIT(MSIX_FH_INT_CAUSES_Q(0));\n \tfor (idx = 1; idx \u003c trans-\u003einfo.num_rxqs; idx++) {\n-\t\tiwl_write8(trans, CSR_MSIX_RX_IVAR(idx),\n-\t\t\t   MSIX_FH_INT_CAUSES_Q(idx - offset));\n+\t\tiwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(idx),\n+\t\t\t\t      MSIX_FH_INT_CAUSES_Q(idx - offset));\n \t\tval |= BIT(MSIX_FH_INT_CAUSES_Q(idx));\n \t}\n-\tiwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);\n+\tiwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);\n \n \tval = MSIX_FH_INT_CAUSES_Q(0);\n \tif (trans_pcie-\u003eshared_vec_mask \u0026 IWL_SHARED_IRQ_NON_RX)\n \t\tval |= MSIX_NON_AUTO_CLEAR_CAUSE;\n-\tiwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);\n+\tiwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(0), val);\n \n \tif (trans_pcie-\u003eshared_vec_mask \u0026 IWL_SHARED_IRQ_FIRST_RSS)\n-\t\tiwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);\n+\t\tiwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(1), val);\n }\n \n void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)\n@@ -1141,8 +1141,8 @@ void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)\n \tif (!trans_pcie-\u003emsix_enabled) {\n \t\tif (trans-\u003emac_cfg-\u003emq_rx_supported \u0026\u0026\n \t\t    test_bit(STATUS_DEVICE_ENABLED, \u0026trans-\u003estatus))\n-\t\t\tiwl_write_umac_prph(trans, UREG_CHICK,\n-\t\t\t\t\t    UREG_CHICK_MSI_ENABLE);\n+\t\t\tiwl_trans_write_umac_prph(trans, UREG_CHICK,\n+\t\t\t\t\t\t  UREG_CHICK_MSI_ENABLE);\n \t\treturn;\n \t}\n \t/*\n@@ -1151,7 +1151,7 @@ void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)\n \t * prph.\n \t */\n \tif (test_bit(STATUS_DEVICE_ENABLED, \u0026trans-\u003estatus))\n-\t\tiwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);\n \n \t/*\n \t * Each cause from the causes list above and the RX causes is\n@@ -1174,9 +1174,9 @@ static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)\n \tif (!trans_pcie-\u003emsix_enabled)\n \t\treturn;\n \n-\ttrans_pcie-\u003efh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);\n+\ttrans_pcie-\u003efh_init_mask = ~iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_MASK_AD);\n \ttrans_pcie-\u003efh_mask = trans_pcie-\u003efh_init_mask;\n-\ttrans_pcie-\u003ehw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);\n+\ttrans_pcie-\u003ehw_init_mask = ~iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_MASK_AD);\n \ttrans_pcie-\u003ehw_mask = trans_pcie-\u003ehw_init_mask;\n }\n \n@@ -1215,19 +1215,19 @@ static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq)\n \n \t\t/* Power-down device's busmaster DMA clocks */\n \t\tif (!trans-\u003emac_cfg-\u003ebase-\u003eapmg_not_supported) {\n-\t\t\tiwl_write_prph(trans, APMG_CLK_DIS_REG,\n-\t\t\t\t       APMG_CLK_VAL_DMA_CLK_RQT);\n+\t\t\tiwl_trans_write_prph(trans, APMG_CLK_DIS_REG,\n+\t\t\t\t\t     APMG_CLK_VAL_DMA_CLK_RQT);\n \t\t\tudelay(5);\n \t\t}\n \t}\n \n \t/* Make sure (redundant) we've released our request to stay awake */\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n \telse\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \n \t/* Stop the device, and put it in low power state */\n \tiwl_pcie_apm_stop(trans, false);\n@@ -1288,6 +1288,10 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,\n \tbool hw_rfkill;\n \tint ret;\n \n+\tif (trans-\u003emac_cfg-\u003egen2)\n+\t\treturn iwl_trans_pcie_gen2_start_fw(trans, fw, img,\n+\t\t\t\t\t\t    run_in_rfkill);\n+\n \t/* This may fail if AMT took ownership of the device */\n \tif (iwl_pcie_prepare_card_hw(trans)) {\n \t\tIWL_WARN(trans, \"Exit HW not ready\\n\");\n@@ -1296,7 +1300,7 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,\n \n \tiwl_enable_rfkill_int(trans);\n \n-\tiwl_write32(trans, CSR_INT, 0xFFFFFFFF);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);\n \n \t/*\n \t * We enabled the RF-Kill interrupt and the handler may very\n@@ -1326,12 +1330,12 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,\n \t}\n \n \t/* make sure rfkill handshake bits are cleared */\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,\n-\t\t    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR,\n+\t\t\t       CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);\n \n \t/* clear (again), then enable host interrupts */\n-\tiwl_write32(trans, CSR_INT, 0xFFFFFFFF);\n+\tiwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);\n \n \tret = iwl_pcie_nic_init(trans);\n \tif (ret) {\n@@ -1349,8 +1353,8 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,\n \tiwl_enable_fw_load_int(trans);\n \n \t/* really make sure rfkill handshake bits are cleared */\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n-\tiwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n+\tiwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);\n \n \t/* Load the given image to the HW */\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_8000)\n@@ -1370,6 +1374,11 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,\n \n void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)\n {\n+\tif (trans-\u003emac_cfg-\u003egen2) {\n+\t\tiwl_trans_pcie_gen2_fw_alive(trans);\n+\t\treturn;\n+\t}\n+\n \tiwl_pcie_reset_ict(trans);\n \tiwl_pcie_tx_start(trans);\n }\n@@ -1408,6 +1417,11 @@ void iwl_trans_pcie_stop_device(struct iwl_trans *trans)\n \tstruct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \tbool was_in_rfkill;\n \n+\tif (trans-\u003emac_cfg-\u003egen2) {\n+\t\tiwl_trans_pcie_gen2_stop_device(trans);\n+\t\treturn;\n+\t}\n+\n \tiwl_op_mode_time_point(trans-\u003eop_mode,\n \t\t\t       IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,\n \t\t\t       NULL);\n@@ -1444,15 +1458,15 @@ static void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,\n \tiwl_pcie_synchronize_irqs(trans);\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n \t} else {\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n \t}\n \n \tif (reset) {\n@@ -1478,13 +1492,13 @@ static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)\n \ttrans_pcie-\u003esx_state = IWL_SX_WAITING;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_AX210)\n-\t\tiwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n-\t\t\t\t    suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :\n-\t\t\t\t\t      UREG_DOORBELL_TO_ISR6_RESUME);\n+\t\tiwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,\n+\t\t\t\t\t  suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :\n+\t\t\t\t\t  UREG_DOORBELL_TO_ISR6_RESUME);\n \telse\n-\t\tiwl_write32(trans, CSR_IPC_SLEEP_CONTROL,\n-\t\t\t    suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :\n-\t\t\t\t      CSR_IPC_SLEEP_CONTROL_RESUME);\n+\t\tiwl_trans_pcie_write32(trans, CSR_IPC_SLEEP_CONTROL,\n+\t\t\t\t       suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :\n+\t\t\t\t\t\t CSR_IPC_SLEEP_CONTROL_RESUME);\n \n \tret = wait_event_timeout(trans_pcie-\u003esx_waitq,\n \t\t\t\t trans_pcie-\u003esx_state != IWL_SX_WAITING,\n@@ -1515,8 +1529,8 @@ int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool reset)\n \n \tif (!reset)\n \t\t/* Enable persistence mode to avoid reset */\n-\t\tiwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n-\t\t\t    CSR_HW_IF_CONFIG_REG_PERSISTENCE);\n+\t\tiwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,\n+\t\t\t\t  CSR_HW_IF_CONFIG_REG_PERSISTENCE);\n \n \tret = iwl_pcie_d3_handshake(trans, true);\n \tif (ret)\n@@ -1535,11 +1549,11 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,\n \tint ret;\n \n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n \telse\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \n \tret = iwl_trans_activate_nic(trans);\n \tif (ret) {\n@@ -1563,8 +1577,8 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,\n \tiwl_pcie_set_pwr(trans, false);\n \n \tif (!reset) {\n-\t\tiwl_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \t} else {\n \t\tiwl_trans_pcie_tx_reset(trans);\n \n@@ -1577,9 +1591,9 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,\n \t}\n \n \tIWL_DEBUG_POWER(trans, \"WFPM value upon resume = 0x%08X\\n\",\n-\t\t\tiwl_read_umac_prph(trans, WFPM_GP2));\n+\t\t\tiwl_trans_read_umac_prph(trans, WFPM_GP2));\n \n-\tval = iwl_read32(trans, CSR_RESET);\n+\tval = iwl_trans_pcie_read32(trans, CSR_RESET);\n \tif (val \u0026 CSR_RESET_REG_FLAG_NEVO_RESET) {\n \t\tIWL_INFO(trans, \"Device was reset during suspend\\n\");\n \t\ttrans-\u003estate = IWL_TRANS_NO_FW;\n@@ -1745,17 +1759,17 @@ static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)\n \t\treturn 0;\n \t}\n \n-\thpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);\n+\thpm = iwl_trans_read_umac_prph_no_grab(trans, HPM_DEBUG);\n \tif (!iwl_trans_is_hw_error_value(hpm) \u0026\u0026 (hpm \u0026 PERSISTENCE_BIT)) {\n-\t\tu32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);\n+\t\tu32 wprot_val = iwl_trans_read_umac_prph_no_grab(trans, wprot);\n \n \t\tif (wprot_val \u0026 PREG_WFPM_ACCESS) {\n \t\t\tIWL_ERR(trans,\n \t\t\t\t\"Error, can not clear persistence bit\\n\");\n \t\t\treturn -EPERM;\n \t\t}\n-\t\tiwl_write_umac_prph_no_grab(trans, HPM_DEBUG,\n-\t\t\t\t\t    hpm \u0026 ~PERSISTENCE_BIT);\n+\t\tiwl_pcie_write_umac_prph_no_grab(trans, HPM_DEBUG,\n+\t\t\t\t\t\t hpm \u0026 ~PERSISTENCE_BIT);\n \t}\n \n \treturn 0;\n@@ -1769,15 +1783,15 @@ static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)\n \tif (ret \u003c 0)\n \t\treturn ret;\n \n-\tiwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,\n-\t\t\t  HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);\n+\tiwl_trans_set_bits_prph(trans, HPM_HIPM_GEN_CFG,\n+\t\t\t\tHPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);\n \tudelay(20);\n-\tiwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,\n-\t\t\t  HPM_HIPM_GEN_CFG_CR_PG_EN |\n-\t\t\t  HPM_HIPM_GEN_CFG_CR_SLP_EN);\n+\tiwl_trans_set_bits_prph(trans, HPM_HIPM_GEN_CFG,\n+\t\t\t\tHPM_HIPM_GEN_CFG_CR_PG_EN |\n+\t\t\t\tHPM_HIPM_GEN_CFG_CR_SLP_EN);\n \tudelay(20);\n-\tiwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,\n-\t\t\t    HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);\n+\tiwl_trans_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,\n+\t\t\t\t  HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);\n \n \treturn iwl_trans_pcie_sw_reset(trans, true);\n }\n@@ -1846,6 +1860,11 @@ void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)\n {\n \tstruct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \n+\tif (trans-\u003emac_cfg-\u003egen2) {\n+\t\tiwl_trans_pcie_gen2_op_mode_leave(trans);\n+\t\treturn;\n+\t}\n+\n \tmutex_lock(\u0026trans_pcie-\u003emutex);\n \n \t/* disable interrupts - don't enable HW RF kill interrupt */\n@@ -1864,17 +1883,22 @@ void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)\n \n void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)\n {\n+\ttrace_iwlwifi_dev_iowrite8(trans-\u003edev, ofs, val);\n \twriteb(val, IWL_TRANS_GET_PCIE_TRANS(trans)-\u003ehw_base + ofs);\n }\n \n void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)\n {\n+\ttrace_iwlwifi_dev_iowrite32(trans-\u003edev, ofs, val);\n \twritel(val, IWL_TRANS_GET_PCIE_TRANS(trans)-\u003ehw_base + ofs);\n }\n \n u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)\n {\n-\treturn readl(IWL_TRANS_GET_PCIE_TRANS(trans)-\u003ehw_base + ofs);\n+\tu32 val = readl(IWL_TRANS_GET_PCIE_TRANS(trans)-\u003ehw_base + ofs);\n+\n+\ttrace_iwlwifi_dev_ioread32(trans-\u003edev, ofs, val);\n+\treturn val;\n }\n \n static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)\n@@ -1888,16 +1912,20 @@ static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)\n u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)\n {\n \tu32 mask = iwl_trans_pcie_prph_msk(trans);\n+\tu32 val;\n \n \tiwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,\n \t\t\t       ((reg \u0026 mask) | (3 \u003c\u003c 24)));\n-\treturn iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);\n+\tval = iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);\n+\ttrace_iwlwifi_dev_ioread_prph32(trans-\u003edev, reg, val);\n+\treturn val;\n }\n \n-void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val)\n+void iwl_pcie_write_prph_no_grab(struct iwl_trans *trans, u32 addr, u32 val)\n {\n \tu32 mask = iwl_trans_pcie_prph_msk(trans);\n \n+\ttrace_iwlwifi_dev_iowrite_prph32(trans-\u003edev, addr, val);\n \tiwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,\n \t\t\t       ((addr \u0026 mask) | (3 \u003c\u003c 24)));\n \tiwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);\n@@ -2265,7 +2293,7 @@ static void iwl_trans_pcie_removal_wk(struct work_struct *wk)\n \tmodule_put(THIS_MODULE);\n }\n \n-void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)\n+static void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)\n {\n \tstruct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \tstruct iwl_trans_pcie_removal *removal;\n@@ -2320,7 +2348,6 @@ void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)\n \tpci_dev_get(removal-\u003epdev);\n \tschedule_work(\u0026removal-\u003ework);\n }\n-EXPORT_SYMBOL(iwl_trans_pcie_reset);\n \n /*\n  * This version doesn't disable BHs but rather assumes they're\n@@ -2350,7 +2377,7 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)\n \t}\n \n \t/* this bit wakes up the NIC */\n-\tiwl_trans_set_bit(trans, CSR_GP_CNTRL, write);\n+\tiwl_pcie_set_bit(trans, CSR_GP_CNTRL, write);\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_8000)\n \t\tudelay(2);\n \n@@ -2374,9 +2401,9 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)\n \t * 5000 series and later (including 1000 series) have non-volatile SRAM,\n \t * and do not save/restore SRAM when power cycling.\n \t */\n-\tret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);\n+\tret = iwl_trans_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);\n \tif (unlikely(ret)) {\n-\t\tu32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);\n+\t\tu32 cntrl = iwl_trans_pcie_read32(trans, CSR_GP_CNTRL);\n \n \t\tif (silent) {\n \t\t\tspin_unlock(\u0026trans_pcie-\u003ereg_lock);\n@@ -2393,8 +2420,8 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)\n \t\t\tiwl_trans_pcie_reset(trans,\n \t\t\t\t\t     IWL_RESET_MODE_REMOVE_ONLY);\n \t\telse\n-\t\t\tiwl_write32(trans, CSR_RESET,\n-\t\t\t\t    CSR_RESET_REG_FLAG_FORCE_NMI);\n+\t\t\tiwl_trans_pcie_write32(trans, CSR_RESET,\n+\t\t\t\t\t       CSR_RESET_REG_FLAG_FORCE_NMI);\n \n \t\tspin_unlock(\u0026trans_pcie-\u003ereg_lock);\n \t\treturn false;\n@@ -2443,11 +2470,11 @@ void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)\n \tif (trans_pcie-\u003ecmd_hold_nic_awake)\n \t\tgoto out;\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ)\n-\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n+\t\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t   CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);\n \telse\n-\t\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \t/*\n \t * Above we read the CSR_GP_CNTRL register, which will flush\n \t * any previous writes, but we need the write that clears the\n@@ -2472,12 +2499,12 @@ int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,\n \t\tbool resched = false;\n \n \t\tif (iwl_trans_grab_nic_access(trans)) {\n-\t\t\tiwl_write32(trans, HBUS_TARG_MEM_RADDR,\n-\t\t\t\t    addr + 4 * offs);\n+\t\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_MEM_RADDR,\n+\t\t\t\t\t       addr + 4 * offs);\n \n \t\t\twhile (offs \u003c dwords) {\n-\t\t\t\tvals[offs] = iwl_read32(trans,\n-\t\t\t\t\t\t\tHBUS_TARG_MEM_RDAT);\n+\t\t\t\tvals[offs] = iwl_trans_pcie_read32(trans,\n+\t\t\t\t\t\t\t\t   HBUS_TARG_MEM_RDAT);\n \n \t\t\t\tif (iwl_trans_is_hw_error_value(vals[offs]))\n \t\t\t\t\tnum_consec_hw_errors++;\n@@ -2524,11 +2551,11 @@ int iwl_trans_pcie_read_mem_no_grab(struct iwl_trans *trans, u32 addr,\n \t\tunsigned long end = jiffies + HZ / 2;\n \t\tbool resched = false;\n \n-\t\tiwl_write32(trans, HBUS_TARG_MEM_RADDR,\n-\t\t\t    addr + 4 * offs);\n+\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_MEM_RADDR,\n+\t\t\t\t       addr + 4 * offs);\n \n \t\twhile (offs \u003c dwords) {\n-\t\t\tvals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);\n+\t\t\tvals[offs] = iwl_trans_pcie_read32(trans, HBUS_TARG_MEM_RDAT);\n \n \t\t\tif (iwl_trans_is_hw_error_value(vals[offs]))\n \t\t\t\tnum_consec_hw_errors++;\n@@ -2672,7 +2699,7 @@ void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,\n \tstruct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);\n \n \tspin_lock_bh(\u0026trans_pcie-\u003ereg_lock);\n-\t_iwl_trans_set_bits_mask(trans, reg, mask, value);\n+\tiwl_pcie_set_bits_mask(trans, reg, mask, value);\n \tspin_unlock_bh(\u0026trans_pcie-\u003ereg_lock);\n }\n \n@@ -2745,7 +2772,7 @@ void iwl_pcie_dump_csr(struct iwl_trans *trans)\n \tfor (i = 0; i \u003c  ARRAY_SIZE(csr_tbl); i++) {\n \t\tIWL_ERR(trans, \"  %25s: 0X%08x\\n\",\n \t\t\tget_csr_string(csr_tbl[i]),\n-\t\t\tiwl_read32(trans, csr_tbl[i]));\n+\t\t\tiwl_trans_pcie_read32(trans, csr_tbl[i]));\n \t}\n }\n \n@@ -3021,7 +3048,7 @@ static ssize_t iwl_dbgfs_rfkill_read(struct file *file,\n \n \tpos = scnprintf(buf, sizeof(buf), \"debug: %d\\nhw: %d\\n\",\n \t\t\ttrans_pcie-\u003edebug_rfkill,\n-\t\t\t!(iwl_read32(trans, CSR_GP_CNTRL) \u0026\n+\t\t\t!(iwl_trans_pcie_read32(trans, CSR_GP_CNTRL) \u0026\n \t\t\t\tCSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));\n \n \treturn simple_read_from_buffer(user_buf, count, ppos, buf, pos);\n@@ -3228,8 +3255,8 @@ static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,\n \t\t     i += sizeof(u32))\n \t\t\t*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));\n \telse\n-\t\tfor (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);\n-\t\t     i \u003c iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);\n+\t\tfor (i = iwl_trans_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);\n+\t\t     i \u003c iwl_trans_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);\n \t\t     i += sizeof(u32))\n \t\t\t*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,\n \t\t\t\t\t\t\t\t      i));\n@@ -3253,11 +3280,11 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,\n \tif (!iwl_trans_grab_nic_access(trans))\n \t\treturn 0;\n \n-\tiwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);\n+\tiwl_pcie_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);\n \tfor (i = 0; i \u003c buf_size_in_dwords; i++)\n-\t\tbuffer[i] = iwl_read_umac_prph_no_grab(trans,\n-\t\t\t\t\t\t       MON_DMARB_RD_DATA_ADDR);\n-\tiwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);\n+\t\tbuffer[i] = iwl_trans_read_umac_prph_no_grab(trans,\n+\t\t\t\t\t\t\t     MON_DMARB_RD_DATA_ADDR);\n+\tiwl_pcie_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);\n \n \tiwl_trans_release_nic_access(trans);\n \n@@ -3285,14 +3312,14 @@ iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,\n \t\twrap_cnt = MON_BUFF_CYCLE_CNT;\n \t}\n \n-\twrite_ptr_val = iwl_read_prph(trans, write_ptr);\n+\twrite_ptr_val = iwl_trans_read_prph(trans, write_ptr);\n \tfw_mon_data-\u003efw_mon_cycle_cnt =\n-\t\tcpu_to_le32(iwl_read_prph(trans, wrap_cnt));\n+\t\tcpu_to_le32(iwl_trans_read_prph(trans, wrap_cnt));\n \tfw_mon_data-\u003efw_mon_base_ptr =\n-\t\tcpu_to_le32(iwl_read_prph(trans, base));\n+\t\tcpu_to_le32(iwl_trans_read_prph(trans, base));\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_AX210) {\n \t\tfw_mon_data-\u003efw_mon_base_high_ptr =\n-\t\t\tcpu_to_le32(iwl_read_prph(trans, base_high));\n+\t\t\tcpu_to_le32(iwl_trans_read_prph(trans, base_high));\n \t\twrite_ptr_val \u0026= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;\n \t\t/* convert wrtPtr to DWs, to align with all HWs */\n \t\twrite_ptr_val \u003e\u003e= 2;\n@@ -3330,13 +3357,13 @@ iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,\n \t\t\t * shifting\n \t\t\t */\n \t\t\tif (trans-\u003edbg.dest_tlv-\u003eversion) {\n-\t\t\t\tbase = (iwl_read_prph(trans, base) \u0026\n+\t\t\t\tbase = (iwl_trans_read_prph(trans, base) \u0026\n \t\t\t\t\tIWL_LDBG_M2S_BUF_BA_MSK) \u003c\u003c\n \t\t\t\t       trans-\u003edbg.dest_tlv-\u003ebase_shift;\n \t\t\t\tbase *= IWL_M2S_UNIT_SIZE;\n \t\t\t\tbase += trans-\u003emac_cfg-\u003ebase-\u003esmem_offset;\n \t\t\t} else {\n-\t\t\t\tbase = iwl_read_prph(trans, base) \u003c\u003c\n+\t\t\t\tbase = iwl_trans_read_prph(trans, base) \u003c\u003c\n \t\t\t\t       trans-\u003edbg.dest_tlv-\u003ebase_shift;\n \t\t\t}\n \n@@ -3371,7 +3398,7 @@ static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)\n \n \t\tif (trans-\u003edbg.dest_tlv-\u003eversion == 1) {\n \t\t\tcfg_reg = le32_to_cpu(trans-\u003edbg.dest_tlv-\u003ebase_reg);\n-\t\t\tcfg_reg = iwl_read_prph(trans, cfg_reg);\n+\t\t\tcfg_reg = iwl_trans_read_prph(trans, cfg_reg);\n \t\t\tbase = (cfg_reg \u0026 IWL_LDBG_M2S_BUF_BA_MSK) \u003c\u003c\n \t\t\t\ttrans-\u003edbg.dest_tlv-\u003ebase_shift;\n \t\t\tbase *= IWL_M2S_UNIT_SIZE;\n@@ -3385,9 +3412,9 @@ static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)\n \t\t\tbase = le32_to_cpu(trans-\u003edbg.dest_tlv-\u003ebase_reg);\n \t\t\tend = le32_to_cpu(trans-\u003edbg.dest_tlv-\u003eend_reg);\n \n-\t\t\tbase = iwl_read_prph(trans, base) \u003c\u003c\n+\t\t\tbase = iwl_trans_read_prph(trans, base) \u003c\u003c\n \t\t\t       trans-\u003edbg.dest_tlv-\u003ebase_shift;\n-\t\t\tend = iwl_read_prph(trans, end) \u003c\u003c\n+\t\t\tend = iwl_trans_read_prph(trans, end) \u003c\u003c\n \t\t\t      trans-\u003edbg.dest_tlv-\u003eend_shift;\n \n \t\t\t/* Make \"end\" point to the actual end */\n@@ -3445,8 +3472,8 @@ iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,\n \tif (dump_mask \u0026 BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {\n \t\tif (trans-\u003emac_cfg-\u003egen2)\n \t\t\tlen += sizeof(*data) +\n-\t\t\t       (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -\n-\t\t\t\tiwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));\n+\t\t\t       (iwl_trans_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -\n+\t\t\t\tiwl_trans_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));\n \t\telse\n \t\t\tlen += sizeof(*data) +\n \t\t\t       (FH_MEM_UPPER_BOUND -\n@@ -3592,12 +3619,12 @@ void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)\n \n \tiwl_trans_force_nmi(trans);\n \twhile (time_after(timeout, jiffies)) {\n-\t\tu32 inta_hw = iwl_read32(trans, inta_addr);\n+\t\tu32 inta_hw = iwl_trans_pcie_read32(trans, inta_addr);\n \n \t\t/* Error detected by uCode */\n \t\tif (inta_hw \u0026 sw_err_bit) {\n \t\t\t/* Clear causes register */\n-\t\t\tiwl_write32(trans, inta_addr, inta_hw \u0026 sw_err_bit);\n+\t\t\tiwl_trans_pcie_write32(trans, inta_addr, inta_hw \u0026 sw_err_bit);\n \t\t\tbreak;\n \t\t}\n \n@@ -3651,6 +3678,66 @@ static int iwl_trans_pcie_alloc_txcmd_pool(struct iwl_trans *trans)\n \treturn 0;\n }\n \n+const struct iwl_trans_ops iwl_trans_pcie_ops = {\n+\t.op_mode_enter = iwl_trans_pcie_op_mode_enter,\n+\t.start_hw = iwl_trans_pcie_start_hw,\n+\t.op_mode_leave = iwl_trans_pcie_op_mode_leave,\n+\n+\t.send_cmd = iwl_trans_pcie_send_hcmd,\n+\t.alloc_tx_cmd = iwl_pcie_alloc_tx_cmd,\n+\t.free_tx_cmd = iwl_pcie_free_tx_cmd,\n+\n+\t.write8 = iwl_trans_pcie_write8,\n+\t.write32 = iwl_trans_pcie_write32,\n+\t.read32 = iwl_trans_pcie_read32,\n+\t.read_prph = iwl_trans_pcie_read_prph,\n+\t.write_prph = iwl_pcie_write_prph_no_grab,\n+\t.read_mem = iwl_trans_pcie_read_mem,\n+\t.read_mem_no_grab = iwl_trans_pcie_read_mem_no_grab,\n+\t.set_bits_mask = iwl_trans_pcie_set_bits_mask,\n+\t.read_config32 = iwl_trans_pcie_read_config32,\n+\t.grab_nic_access = iwl_trans_pcie_grab_nic_access,\n+\t.release_nic_access = iwl_trans_pcie_release_nic_access,\n+\t.resched_with_nic_access = iwl_trans_pcie_resched_with_nic_access,\n+\n+\t.sw_reset = iwl_trans_pcie_sw_reset,\n+\t.reset = iwl_trans_pcie_reset,\n+\t.fw_reset_handshake = iwl_trans_pcie_fw_reset_handshake,\n+\n+\t.dump_data = iwl_trans_pcie_dump_data,\n+\t.d3_suspend = iwl_trans_pcie_d3_suspend,\n+\t.d3_resume = iwl_trans_pcie_d3_resume,\n+\n+\t.sync_nmi = iwl_trans_pcie_sync_nmi,\n+\t.write_imr_mem = iwl_trans_pcie_copy_imr,\n+\n+\t.fw_alive = iwl_trans_pcie_fw_alive,\n+\t.start_fw = iwl_trans_pcie_start_fw,\n+\t.stop_device = iwl_trans_pcie_stop_device,\n+\n+\t.tx = iwl_trans_pcie_tx,\n+\t.reclaim = iwl_pcie_reclaim,\n+\t.txq_disable = iwl_trans_pcie_txq_disable,\n+\t.txq_enable = iwl_trans_pcie_txq_enable,\n+\t.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,\n+\t.wait_txqs_empty = iwl_trans_pcie_wait_txqs_empty,\n+\t.freeze_txq_timer = iwl_pcie_freeze_txq_timer,\n+\t.txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,\n+\t.set_q_ptrs = iwl_pcie_set_q_ptrs,\n+\t.txq_alloc = iwl_txq_dyn_alloc,\n+\t.txq_free = iwl_txq_dyn_free,\n+\t.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,\n+\n+\t.load_pnvm = iwl_trans_pcie_ctx_info_v2_load_pnvm,\n+\t.set_pnvm = iwl_trans_pcie_ctx_info_v2_set_pnvm,\n+\t.load_reduce_power = iwl_trans_pcie_ctx_info_v2_load_reduce_power,\n+\t.set_reduce_power = iwl_trans_pcie_ctx_info_v2_set_reduce_power,\n+\n+\t.is_pm_supported = iwl_pcie_gen1_is_pm_supported,\n+\t.is_ltr_enabled = iwl_pcie_is_ltr_enabled,\n+\t.activate_nic = iwl_pcie_activate_nic,\n+};\n+\n static struct iwl_trans *\n iwl_trans_pcie_alloc(struct pci_dev *pdev,\n \t\t     const struct iwl_mac_cfg *mac_cfg,\n@@ -3662,7 +3749,7 @@ iwl_trans_pcie_alloc(struct pci_dev *pdev,\n \tint ret, addr_size;\n \n \ttrans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), \u0026pdev-\u003edev,\n-\t\t\t\tmac_cfg);\n+\t\t\t\t\u0026iwl_trans_pcie_ops, mac_cfg);\n \tif (!trans)\n \t\treturn ERR_PTR(-ENOMEM);\n \n@@ -3851,19 +3938,19 @@ iwl_trans_pcie_alloc(struct pci_dev *pdev,\n void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,\n \t\t\t\tu32 dst_addr, u64 src_addr, u32 byte_cnt)\n {\n-\tiwl_write_prph(trans, IMR_UREG_CHICK,\n-\t\t       iwl_read_prph(trans, IMR_UREG_CHICK) |\n-\t\t       IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,\n-\t\t       (u32)(src_addr \u0026 0xFFFFFFFF));\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,\n-\t\t       iwl_get_dma_hi_addr(src_addr));\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);\n-\tiwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,\n-\t\t       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |\n-\t\t       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |\n-\t\t       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);\n+\tiwl_trans_write_prph(trans, IMR_UREG_CHICK,\n+\t\t\t     iwl_trans_read_prph(trans, IMR_UREG_CHICK) |\n+\t\t\t     IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,\n+\t\t\t     (u32)(src_addr \u0026 0xFFFFFFFF));\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,\n+\t\t\t     iwl_get_dma_hi_addr(src_addr));\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);\n+\tiwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,\n+\t\t\t     IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |\n+\t\t\t     IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |\n+\t\t\t     IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);\n }\n \n int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,\n@@ -3905,8 +3992,8 @@ static void get_crf_id(struct iwl_trans *iwl_trans,\n \t/* wait until the device is ready to access the prph registers */\n \tif (iwl_trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_DR ||\n \t    iwl_trans-\u003emac_cfg-\u003edevice_family == IWL_DEVICE_FAMILY_SC) {\n-\t\tu32 req = iwl_read_umac_prph_no_grab(iwl_trans,\n-\t\t\t\t\t\t     WFPM_RSRCS_4PHS_REQ_STTS);\n+\t\tu32 req = iwl_trans_read_umac_prph_no_grab(iwl_trans,\n+\t\t\t\t\t\t\t   WFPM_RSRCS_4PHS_REQ_STTS);\n \t\tint ret;\n \n \t\tif (!(req \u0026 RSRC_REQ_CNVR_TOP)) {\n@@ -3916,26 +4003,26 @@ static void get_crf_id(struct iwl_trans *iwl_trans,\n \t\t\treturn;\n \t\t}\n \n-\t\tret = iwl_poll_umac_prph_bits_no_grab(iwl_trans,\n-\t\t\t\t\t\t      WFPM_RSRCS_4PHS_ACK_STTS,\n-\t\t\t\t\t\t      RSRC_ACK_CNVR_TOP,\n-\t\t\t\t\t\t      RSRC_ACK_CNVR_TOP,\n-\t\t\t\t\t\t      50 * 1000);\n+\t\tret = iwl_pcie_poll_umac_prph_bits_no_grab(iwl_trans,\n+\t\t\t\t\t\t\t   WFPM_RSRCS_4PHS_ACK_STTS,\n+\t\t\t\t\t\t\t   RSRC_ACK_CNVR_TOP,\n+\t\t\t\t\t\t\t   RSRC_ACK_CNVR_TOP,\n+\t\t\t\t\t\t\t   50 * 1000);\n \t\tif (ret \u003c 0)\n \t\t\tIWL_ERR(iwl_trans,\n \t\t\t\t\"WFPM_RSRCS_4PHS_ACK_STTS bit 6 is clear\\n\");\n \t}\n \n \t/* Enable access to peripheral registers */\n-\tval = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);\n+\tval = iwl_trans_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);\n \tval |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;\n-\tiwl_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val);\n+\tiwl_pcie_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val);\n \n \t/* Read crf info */\n-\tinfo-\u003ehw_crf_id = iwl_read_prph_no_grab(iwl_trans, sd_reg_ver_addr);\n+\tinfo-\u003ehw_crf_id = iwl_trans_pcie_read_prph(iwl_trans, sd_reg_ver_addr);\n \n \t/* Read cnv info */\n-\tinfo-\u003ehw_cnv_id = iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP);\n+\tinfo-\u003ehw_cnv_id = iwl_trans_pcie_read_prph(iwl_trans, CNVI_AUX_MISC_CHIP);\n \n \t/* For BZ-W, take B step also when A step is indicated */\n \tif (CSR_HW_REV_TYPE(info-\u003ehw_rev) == IWL_CFG_MAC_TYPE_BZ_W)\n@@ -3959,7 +4046,7 @@ static void get_crf_id(struct iwl_trans *iwl_trans,\n \t}\n \n \t/* Read cdb info (also contains the jacket info if needed in the future */\n-\thw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);\n+\thw_wfpm_id = iwl_trans_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);\n \n \tIWL_INFO(iwl_trans, \"Detected crf-id 0x%x, cnv-id 0x%x wfpm id 0x%x\\n\",\n \t\t info-\u003ehw_crf_id, info-\u003ehw_cnv_id, hw_wfpm_id);\n@@ -3976,8 +4063,8 @@ static int map_crf_id(struct iwl_trans *iwl_trans,\n \tu32 val = info-\u003ehw_crf_id;\n \tu32 step_id = REG_CRF_ID_STEP(val);\n \tu32 slave_id = REG_CRF_ID_SLAVE(val);\n-\tu32 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans,\n-\t\t\t\t\t\t    WFPM_OTP_CFG1_ADDR);\n+\tu32 hw_wfpm_id = iwl_trans_read_umac_prph_no_grab(iwl_trans,\n+\t\t\t\t\t\t\t  WFPM_OTP_CFG1_ADDR);\n \tu32 cdb_id_wfpm = WFPM_OTP_CFG1_IS_CDB(hw_wfpm_id);\n \n \t/* Map between crf id to rf id */\n@@ -4043,7 +4130,7 @@ static void iwl_pcie_recheck_me_status(struct work_struct *wk)\n \t\t\t\t\t\t\t me_recheck_wk.work);\n \tu32 val;\n \n-\tval = iwl_read32(trans_pcie-\u003etrans, CSR_HW_IF_CONFIG_REG);\n+\tval = iwl_trans_pcie_read32(trans_pcie-\u003etrans, CSR_HW_IF_CONFIG_REG);\n \ttrans_pcie-\u003eme_present = !!(val \u0026 CSR_HW_IF_CONFIG_REG_IAMT_UP);\n }\n \n@@ -4061,14 +4148,14 @@ static void iwl_pcie_check_me_status(struct iwl_trans *trans)\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_BZ)\n \t\treturn;\n \n-\tval = iwl_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1);\n+\tval = iwl_trans_pcie_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1);\n \tif (val \u0026 CNVI_SCU_REG_FOR_ECO_1_WIAMT_KNOWN) {\n \t\ttrans_pcie-\u003eme_present =\n \t\t\t!!(val \u0026 CNVI_SCU_REG_FOR_ECO_1_WIAMT_PRESENT);\n \t\treturn;\n \t}\n \n-\tval = iwl_read32(trans, CSR_HW_IF_CONFIG_REG);\n+\tval = iwl_trans_pcie_read32(trans, CSR_HW_IF_CONFIG_REG);\n \tif (val \u0026 (CSR_HW_IF_CONFIG_REG_ME_OWN |\n \t\t   CSR_HW_IF_CONFIG_REG_IAMT_UP)) {\n \t\ttrans_pcie-\u003eme_present = 1;\n@@ -4126,7 +4213,7 @@ int _iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent,\n \t\t}\n \t}\n \n-\tinfo.hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID);\n+\tinfo.hw_rf_id = iwl_trans_pcie_read32(iwl_trans, CSR_HW_RF_ID);\n \n \t/*\n \t * The RF_ID is set to zero in blank OTP so read version to\n@@ -4247,13 +4334,13 @@ int iwl_pcie_activate_nic(struct iwl_trans *trans)\n \t * D0U* --\u003e D0A* (powered-up active) state.\n \t */\n \tif (mac_cfg-\u003edevice_family \u003e= IWL_DEVICE_FAMILY_BZ) {\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ |\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ |\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_MAC_INIT);\n \t\tpoll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;\n \t} else {\n-\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n+\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_INIT_DONE);\n \t\tpoll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY;\n \t}\n \n@@ -4262,10 +4349,10 @@ int iwl_pcie_activate_nic(struct iwl_trans *trans)\n \n \t/*\n \t * Wait for clock stabilization; once stabilized, access to\n-\t * device-internal resources is supported, e.g. iwl_write_prph()\n+\t * device-internal resources is supported, e.g. iwl_trans_write_prph()\n \t * and accesses to uCode SRAM.\n \t */\n-\terr = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);\n+\terr = iwl_trans_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);\n \tif (err \u003c 0) {\n \t\tIWL_DEBUG_INFO(trans, \"Failed to wake NIC\\n\");\n \ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c\nindex 27f4973791d00..e6bebd37417f7 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c\n@@ -1,14 +1,14 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /*\n  * Copyright (C) 2017 Intel Deutschland GmbH\n- * Copyright (C) 2018-2020, 2023-2025 Intel Corporation\n+ * Copyright (C) 2018-2020, 2023-2026 Intel Corporation\n  */\n #include \u003cnet/tso.h\u003e\n #include \u003clinux/tcp.h\u003e\n \n #include \"iwl-debug.h\"\n #include \"iwl-csr.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"internal.h\"\n #include \"fw/api/tx.h\"\n #include \"fw/api/commands.h\"\n@@ -711,7 +711,7 @@ static void iwl_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)\n \t * if not in power-save mode, uCode will never sleep when we're\n \t * trying to tx (during RFKILL, we're not trying to tx).\n \t */\n-\tiwl_write32(trans, HBUS_TARG_WRPTR, txq-\u003ewrite_ptr | (txq-\u003eid \u003c\u003c 16));\n+\tiwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, txq-\u003ewrite_ptr | (txq-\u003eid \u003c\u003c 16));\n }\n \n int iwl_txq_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c\nindex 496435ea93ee8..0c29fb6b9ca71 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c\n@@ -20,7 +20,7 @@\n #include \"iwl-debug.h\"\n #include \"iwl-csr.h\"\n #include \"iwl-prph.h\"\n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"iwl-scd.h\"\n #include \"iwl-op-mode.h\"\n #include \"internal.h\"\n@@ -99,13 +99,13 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,\n \t\t * uCode will wake up, and interrupt us again, so next\n \t\t * time we'll skip this part.\n \t\t */\n-\t\treg = iwl_read32(trans, CSR_UCODE_DRV_GP1);\n+\t\treg = iwl_trans_pcie_read32(trans, CSR_UCODE_DRV_GP1);\n \n \t\tif (reg \u0026 CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {\n \t\t\tIWL_DEBUG_INFO(trans, \"Tx queue %d requesting wakeup, GP1 = 0x%x\\n\",\n \t\t\t\t       txq_id, reg);\n-\t\t\tiwl_set_bit(trans, CSR_GP_CNTRL,\n-\t\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\t\t\tiwl_trans_set_bit(trans, CSR_GP_CNTRL,\n+\t\t\t\t\t  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \t\t\ttxq-\u003eneed_update = true;\n \t\t\treturn;\n \t\t}\n@@ -117,8 +117,8 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,\n \t */\n \tIWL_DEBUG_TX(trans, \"Q:%d WR: 0x%x\\n\", txq_id, txq-\u003ewrite_ptr);\n \tif (!txq-\u003eblock)\n-\t\tiwl_write32(trans, HBUS_TARG_WRPTR,\n-\t\t\t    txq-\u003ewrite_ptr | (txq_id \u003c\u003c 8));\n+\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR,\n+\t\t\t\t       txq-\u003ewrite_ptr | (txq_id \u003c\u003c 8));\n }\n \n void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)\n@@ -205,8 +205,8 @@ static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)\n \t}\n \n \ttrans_pcie-\u003ecmd_hold_nic_awake = false;\n-\tiwl_trans_clear_bit(trans, CSR_GP_CNTRL,\n-\t\t\t    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n+\tiwl_pcie_clear_bit(trans, CSR_GP_CNTRL,\n+\t\t\t   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);\n \tspin_unlock(\u0026trans_pcie-\u003ereg_lock);\n }\n \n@@ -493,21 +493,21 @@ void iwl_pcie_tx_start(struct iwl_trans *trans)\n \t       sizeof(trans_pcie-\u003etxqs.queue_used));\n \n \ttrans_pcie-\u003escd_base_addr =\n-\t\tiwl_read_prph(trans, SCD_SRAM_BASE_ADDR);\n+\t\tiwl_trans_read_prph(trans, SCD_SRAM_BASE_ADDR);\n \n \t/* reset context data, TX status and translation data */\n \tiwl_trans_write_mem(trans, trans_pcie-\u003escd_base_addr +\n \t\t\t\t   SCD_CONTEXT_MEM_LOWER_BOUND,\n \t\t\t    NULL, clear_dwords);\n \n-\tiwl_write_prph(trans, SCD_DRAM_BASE_ADDR,\n-\t\t       trans_pcie-\u003etxqs.scd_bc_tbls.dma \u003e\u003e 10);\n+\tiwl_trans_write_prph(trans, SCD_DRAM_BASE_ADDR,\n+\t\t\t     trans_pcie-\u003etxqs.scd_bc_tbls.dma \u003e\u003e 10);\n \n \t/* The chain extension of the SCD doesn't work well. This feature is\n \t * enabled by default by the HW, so we need to disable it manually.\n \t */\n \tif (trans-\u003emac_cfg-\u003ebase-\u003escd_chain_ext_wa)\n-\t\tiwl_write_prph(trans, SCD_CHAINEXT_EN, 0);\n+\t\tiwl_trans_write_prph(trans, SCD_CHAINEXT_EN, 0);\n \n \tiwl_trans_ac_txq_enable(trans, trans-\u003econf.cmd_queue,\n \t\t\t\ttrans-\u003econf.cmd_fifo,\n@@ -518,19 +518,19 @@ void iwl_pcie_tx_start(struct iwl_trans *trans)\n \n \t/* Enable DMA channel */\n \tfor (chan = 0; chan \u003c FH_TCSR_CHNL_NUM; chan++)\n-\t\tiwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),\n-\t\t\t\t   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |\n-\t\t\t\t   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);\n+\t\tiwl_trans_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),\n+\t\t\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |\n+\t\t\t\t\t FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);\n \n \t/* Update FH chicken bits */\n-\treg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);\n-\tiwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,\n-\t\t\t   reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);\n+\treg_val = iwl_pcie_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);\n+\tiwl_trans_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,\n+\t\t\t\t reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);\n \n \t/* Enable L1-Active */\n \tif (trans-\u003emac_cfg-\u003edevice_family \u003c IWL_DEVICE_FAMILY_8000)\n-\t\tiwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,\n-\t\t\t\t    APMG_PCIDEV_STT_VAL_L1_ACT_DIS);\n+\t\tiwl_trans_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,\n+\t\t\t\t\t  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);\n }\n \n void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)\n@@ -549,21 +549,21 @@ void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)\n \t     txq_id++) {\n \t\tstruct iwl_txq *txq = trans_pcie-\u003etxqs.txq[txq_id];\n \t\tif (trans-\u003emac_cfg-\u003egen2)\n-\t\t\tiwl_write_direct64(trans,\n-\t\t\t\t\t   FH_MEM_CBBC_QUEUE(trans, txq_id),\n-\t\t\t\t\t   txq-\u003edma_addr);\n+\t\t\tiwl_pcie_write_direct64(trans,\n+\t\t\t\t\t\tFH_MEM_CBBC_QUEUE(trans, txq_id),\n+\t\t\t\t\t\ttxq-\u003edma_addr);\n \t\telse\n-\t\t\tiwl_write_direct32(trans,\n-\t\t\t\t\t   FH_MEM_CBBC_QUEUE(trans, txq_id),\n-\t\t\t\t\t   txq-\u003edma_addr \u003e\u003e 8);\n+\t\t\tiwl_trans_write_direct32(trans,\n+\t\t\t\t\t\t FH_MEM_CBBC_QUEUE(trans, txq_id),\n+\t\t\t\t\t\t txq-\u003edma_addr \u003e\u003e 8);\n \t\tiwl_pcie_txq_unmap(trans, txq_id);\n \t\ttxq-\u003eread_ptr = 0;\n \t\ttxq-\u003ewrite_ptr = 0;\n \t}\n \n \t/* Tell NIC where to find the \"keep warm\" buffer */\n-\tiwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,\n-\t\t\t   trans_pcie-\u003ekw.dma \u003e\u003e 4);\n+\tiwl_trans_write_direct32(trans, FH_KW_MEM_ADDR_REG,\n+\t\t\t\t trans_pcie-\u003ekw.dma \u003e\u003e 4);\n \n \t/*\n \t * Send 0 as the scd_base_addr since the device may have be reset\n@@ -586,16 +586,16 @@ static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)\n \n \t/* Stop each Tx DMA channel */\n \tfor (ch = 0; ch \u003c FH_TCSR_CHNL_NUM; ch++) {\n-\t\tiwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);\n+\t\tiwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);\n \t\tmask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);\n \t}\n \n \t/* Wait for DMA channels to be idle */\n-\tret = iwl_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);\n+\tret = iwl_trans_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);\n \tif (ret)\n \t\tIWL_ERR(trans,\n \t\t\t\"Failing on timeout while stopping DMA channel %d [0x%08x]\\n\",\n-\t\t\tch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));\n+\t\t\tch, iwl_trans_pcie_read32(trans, FH_TSSR_TX_STATUS_REG));\n \n \tiwl_trans_release_nic_access(trans);\n \n@@ -684,7 +684,7 @@ void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)\n \t\treturn;\n \t}\n \n-\tstatus = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));\n+\tstatus = iwl_trans_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));\n \tfifo = (status \u003e\u003e SCD_QUEUE_STTS_REG_POS_TXF) \u0026 0x7;\n \tactive = !!(status \u0026 BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));\n \n@@ -693,11 +693,11 @@ void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)\n \t\ttxq_id, active ? \"\" : \"in\", fifo,\n \t\tjiffies_to_msecs(txq-\u003ewd_timeout),\n \t\ttxq-\u003eread_ptr, txq-\u003ewrite_ptr,\n-\t\tiwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) \u0026\n+\t\tiwl_trans_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) \u0026\n \t\t\t(trans-\u003emac_cfg-\u003ebase-\u003emax_tfd_queue_size - 1),\n-\t\t\tiwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) \u0026\n+\t\t\tiwl_trans_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) \u0026\n \t\t\t(trans-\u003emac_cfg-\u003ebase-\u003emax_tfd_queue_size - 1),\n-\t\t\tiwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));\n+\t\t\tiwl_pcie_read_direct32(trans, FH_TX_TRB_REG(fifo)));\n }\n \n static void iwl_txq_stuck_timer(struct timer_list *t)\n@@ -955,8 +955,8 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)\n \tiwl_scd_deactivate_fifos(trans);\n \n \t/* Tell NIC where to find the \"keep warm\" buffer */\n-\tiwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,\n-\t\t\t   trans_pcie-\u003ekw.dma \u003e\u003e 4);\n+\tiwl_trans_write_direct32(trans, FH_KW_MEM_ADDR_REG,\n+\t\t\t\t trans_pcie-\u003ekw.dma \u003e\u003e 4);\n \n \tspin_unlock_bh(\u0026trans_pcie-\u003eirq_lock);\n \n@@ -984,14 +984,14 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)\n \t\t * queue.\n \t\t * Circular buffer (TFD queue in DRAM) physical base address\n \t\t */\n-\t\tiwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),\n-\t\t\t\t   trans_pcie-\u003etxqs.txq[txq_id]-\u003edma_addr \u003e\u003e 8);\n+\t\tiwl_trans_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),\n+\t\t\t\t\t trans_pcie-\u003etxqs.txq[txq_id]-\u003edma_addr \u003e\u003e 8);\n \t}\n \n-\tiwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);\n+\tiwl_trans_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);\n \tif (trans-\u003emac_cfg-\u003ebase-\u003enum_of_queues \u003e 20)\n-\t\tiwl_set_bits_prph(trans, SCD_GP_CTRL,\n-\t\t\t\t  SCD_GP_CTRL_ENABLE_31_QUEUES);\n+\t\tiwl_trans_set_bits_prph(trans, SCD_GP_CTRL,\n+\t\t\t\t\tSCD_GP_CTRL_ENABLE_31_QUEUES);\n \n \treturn 0;\n error:\n@@ -1222,13 +1222,13 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,\n \t * Assumes that ssn_idx is valid (!= 0xFFF) */\n \ttxq-\u003eread_ptr = (ssn \u0026 0xff);\n \ttxq-\u003ewrite_ptr = (ssn \u0026 0xff);\n-\tiwl_write_direct32(trans, HBUS_TARG_WRPTR,\n-\t\t\t   (ssn \u0026 0xff) | (txq_id \u003c\u003c 8));\n+\tiwl_trans_write_direct32(trans, HBUS_TARG_WRPTR,\n+\t\t\t\t (ssn \u0026 0xff) | (txq_id \u003c\u003c 8));\n \n \tif (cfg) {\n \t\tu8 frame_limit = cfg-\u003eframe_limit;\n \n-\t\tiwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);\n+\t\tiwl_trans_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);\n \n \t\t/* Set up Tx window size and frame limit for this queue */\n \t\tiwl_trans_write_mem32(trans, trans_pcie-\u003escd_base_addr +\n@@ -1240,11 +1240,11 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,\n \t\t\tSCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));\n \n \t\t/* Set up status area in SRAM, map to Tx DMA/FIFO, activate */\n-\t\tiwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),\n-\t\t\t       (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_ACTIVE) |\n-\t\t\t       (cfg-\u003efifo \u003c\u003c SCD_QUEUE_STTS_REG_POS_TXF) |\n-\t\t\t       (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_WSL) |\n-\t\t\t       SCD_QUEUE_STTS_REG_MSK);\n+\t\tiwl_trans_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),\n+\t\t\t\t     (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_ACTIVE) |\n+\t\t\t\t     (cfg-\u003efifo \u003c\u003c SCD_QUEUE_STTS_REG_POS_TXF) |\n+\t\t\t\t     (1 \u003c\u003c SCD_QUEUE_STTS_REG_POS_WSL) |\n+\t\t\t\t     SCD_QUEUE_STTS_REG_MSK);\n \n \t\t/* enable the scheduler for this queue (only) */\n \t\tif (txq_id == trans-\u003econf.cmd_queue \u0026\u0026\n@@ -1335,8 +1335,8 @@ static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)\n \t\tif (!block \u0026\u0026 !(WARN_ON_ONCE(!txq-\u003eblock))) {\n \t\t\ttxq-\u003eblock--;\n \t\t\tif (!txq-\u003eblock) {\n-\t\t\t\tiwl_write32(trans, HBUS_TARG_WRPTR,\n-\t\t\t\t\t    txq-\u003ewrite_ptr | (i \u003c\u003c 8));\n+\t\t\t\tiwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR,\n+\t\t\t\t\t\t       txq-\u003ewrite_ptr | (i \u003c\u003c 8));\n \t\t\t}\n \t\t} else if (block) {\n \t\t\ttxq-\u003eblock++;\n@@ -2147,6 +2147,9 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,\n \tu16 wifi_seq;\n \tbool amsdu;\n \n+\tif (trans-\u003emac_cfg-\u003egen2)\n+\t\treturn iwl_txq_gen2_tx(trans, skb, dev_cmd, txq_id);\n+\n \ttxq = trans_pcie-\u003etxqs.txq[txq_id];\n \n \tif (WARN_ONCE(!test_bit(txq_id, trans_pcie-\u003etxqs.queue_used),\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/utils.c b/drivers/net/wireless/intel/iwlwifi/pcie/utils.c\nindex 1bb274d8390c3..8aa43e5ac0e19 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/utils.c\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/utils.c\n@@ -1,12 +1,12 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /*\n- * Copyright (C) 2025 Intel Corporation\n+ * Copyright (C) 2025-2026 Intel Corporation\n  */\n \n #include \u003clinux/pci.h\u003e\n #include \u003clinux/gfp.h\u003e\n \n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n #include \"pcie/utils.h\"\n \n void iwl_trans_pcie_dump_regs(struct iwl_trans *trans, struct pci_dev *pdev)\n@@ -51,7 +51,7 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans *trans, struct pci_dev *pdev)\n \n \tIWL_ERR(trans, \"iwlwifi device memory mapped registers:\\n\");\n \tfor (i = 0, ptr = buf; i \u003c PCI_MEM_DUMP_SIZE; i += 4, ptr++)\n-\t\t*ptr = iwl_read32(trans, i);\n+\t\t*ptr = iwl_trans_pcie_read32(trans, i);\n \tprint_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);\n \n \tpos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);\n@@ -102,3 +102,88 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans *trans, struct pci_dev *pdev)\n \tpcie_dbg_dumped_once = 1;\n \tkfree(buf);\n }\n+\n+u32 iwl_pcie_read_direct32(struct iwl_trans *trans, u32 reg)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tu32 value = iwl_trans_pcie_read32(trans, reg);\n+\n+\t\tiwl_trans_release_nic_access(trans);\n+\t\treturn value;\n+\t}\n+\n+\t/* return as if we have a HW timeout/failure */\n+\treturn 0x5a5a5a5a;\n+}\n+\n+#define IWL_PCIE_POLL_INTERVAL 10\t/* microseconds */\n+\n+int iwl_pcie_poll_direct_bit(struct iwl_trans *trans,\n+\t\t\t     u32 addr, u32 mask, int timeout)\n+{\n+\tint t = 0;\n+\n+\tdo {\n+\t\tif ((iwl_pcie_read_direct32(trans, addr) \u0026 mask) == mask)\n+\t\t\treturn t;\n+\t\tudelay(IWL_PCIE_POLL_INTERVAL);\n+\t\tt += IWL_PCIE_POLL_INTERVAL;\n+\t} while (t \u003c timeout);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+int iwl_pcie_poll_prph_bit(struct iwl_trans *trans, u32 addr,\n+\t\t\t   u32 bits, u32 mask, int timeout)\n+{\n+\tint t = 0;\n+\n+\tdo {\n+\t\tif ((iwl_trans_read_prph(trans, addr) \u0026 mask) == (bits \u0026 mask))\n+\t\t\treturn 0;\n+\t\tudelay(IWL_PCIE_POLL_INTERVAL);\n+\t\tt += IWL_PCIE_POLL_INTERVAL;\n+\t} while (t \u003c timeout);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+int iwl_pcie_poll_umac_prph_bit(struct iwl_trans *trans,\n+\t\t\t\tu32 addr, u32 bits, u32 mask,\n+\t\t\t\tint timeout)\n+{\n+\treturn iwl_pcie_poll_prph_bit(trans, addr +\n+\t\t\t\t      trans-\u003emac_cfg-\u003eumac_prph_offset,\n+\t\t\t\t      bits, mask, timeout);\n+}\n+\n+int iwl_pcie_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,\n+\t\t\t\t\t u32 bits, u32 mask, int timeout)\n+{\n+\tint t = 0;\n+\n+\tdo {\n+\t\tif ((iwl_trans_read_umac_prph_no_grab(trans, addr) \u0026 mask) ==\n+\t\t    (bits \u0026 mask))\n+\t\t\treturn 0;\n+\t\tudelay(IWL_PCIE_POLL_INTERVAL);\n+\t\tt += IWL_PCIE_POLL_INTERVAL;\n+\t} while (t \u003c timeout);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+void iwl_pcie_write_prph64_no_grab(struct iwl_trans *trans, u32 ofs, u64 val)\n+{\n+\ttrace_iwlwifi_dev_iowrite_prph64(trans-\u003edev, ofs, val);\n+\tiwl_pcie_write_prph_no_grab(trans, ofs, val \u0026 0xffffffff);\n+\tiwl_pcie_write_prph_no_grab(trans, ofs + 4, val \u003e\u003e 32);\n+}\n+\n+void iwl_pcie_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)\n+{\n+\tif (iwl_trans_grab_nic_access(trans)) {\n+\t\tiwl_pcie_write64(trans, reg, value);\n+\t\tiwl_trans_release_nic_access(trans);\n+\t}\n+}\ndiff --git a/drivers/net/wireless/intel/iwlwifi/pcie/utils.h b/drivers/net/wireless/intel/iwlwifi/pcie/utils.h\nindex 27437d5e099ba..ece1caaa49482 100644\n--- a/drivers/net/wireless/intel/iwlwifi/pcie/utils.h\n+++ b/drivers/net/wireless/intel/iwlwifi/pcie/utils.h\n@@ -1,17 +1,43 @@\n // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n /*\n- * Copyright (C) 2025 Intel Corporation\n+ * Copyright (C) 2025-2026 Intel Corporation\n  */\n \n #ifndef __iwl_pcie_utils_h__\n #define __iwl_pcie_utils_h__\n \n-#include \"iwl-io.h\"\n+#include \"iwl-trans.h\"\n+#include \"internal.h\"\n \n void iwl_trans_pcie_dump_regs(struct iwl_trans *trans, struct pci_dev *pdev);\n \n-static inline void _iwl_trans_set_bits_mask(struct iwl_trans *trans,\n-\t\t\t\t\t    u32 reg, u32 mask, u32 value)\n+u32 iwl_pcie_read_direct32(struct iwl_trans *trans, u32 reg);\n+int iwl_pcie_poll_direct_bit(struct iwl_trans *trans,\n+\t\t\t     u32 addr, u32 mask, int timeout);\n+int iwl_pcie_poll_prph_bit(struct iwl_trans *trans, u32 addr,\n+\t\t\t   u32 bits, u32 mask, int timeout);\n+int iwl_pcie_poll_umac_prph_bit(struct iwl_trans *trans, u32 addr,\n+\t\t\t\tu32 bits, u32 mask, int timeout);\n+int iwl_pcie_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,\n+\t\t\t\t\t u32 bits, u32 mask, int timeout);\n+void iwl_pcie_write_prph64_no_grab(struct iwl_trans *trans, u32 ofs, u64 val);\n+void iwl_pcie_write_direct64(struct iwl_trans *trans, u64 reg, u64 value);\n+\n+static inline void iwl_pcie_write64(struct iwl_trans *trans, u64 ofs, u64 val)\n+{\n+\tiwl_trans_pcie_write32(trans, ofs, lower_32_bits(val));\n+\tiwl_trans_pcie_write32(trans, ofs + 4, upper_32_bits(val));\n+}\n+\n+static inline void iwl_pcie_write_umac_prph_no_grab(struct iwl_trans *trans,\n+\t\t\t\t\t\t    u32 ofs, u32 val)\n+{\n+\tiwl_pcie_write_prph_no_grab(trans, ofs + trans-\u003emac_cfg-\u003eumac_prph_offset,\n+\t\t\t\t    val);\n+}\n+\n+static inline void iwl_pcie_set_bits_mask(struct iwl_trans *trans,\n+\t\t\t\t\t  u32 reg, u32 mask, u32 value)\n {\n \tu32 v;\n \n@@ -19,22 +45,22 @@ static inline void _iwl_trans_set_bits_mask(struct iwl_trans *trans,\n \tWARN_ON_ONCE(value \u0026 ~mask);\n #endif\n \n-\tv = iwl_read32(trans, reg);\n+\tv = iwl_trans_pcie_read32(trans, reg);\n \tv \u0026= ~mask;\n \tv |= value;\n-\tiwl_write32(trans, reg, v);\n+\tiwl_trans_pcie_write32(trans, reg, v);\n }\n \n-static inline void iwl_trans_clear_bit(struct iwl_trans *trans,\n+static inline void iwl_pcie_clear_bit(struct iwl_trans *trans,\n \t\t\t\t       u32 reg, u32 mask)\n {\n-\t_iwl_trans_set_bits_mask(trans, reg, mask, 0);\n+\tiwl_pcie_set_bits_mask(trans, reg, mask, 0);\n }\n \n-static inline void iwl_trans_set_bit(struct iwl_trans *trans,\n+static inline void iwl_pcie_set_bit(struct iwl_trans *trans,\n \t\t\t\t     u32 reg, u32 mask)\n {\n-\t_iwl_trans_set_bits_mask(trans, reg, mask, mask);\n+\tiwl_pcie_set_bits_mask(trans, reg, mask, mask);\n }\n \n #endif /* __iwl_pcie_utils_h__ */\n"
}

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit 3f251a1e32cc7686e741e402cd3ebb5513c6fd71
Author: syz-cluster <triage@syzkaller.com>
Date:   Thu Oct 1 08:48:03 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/wireless/intel/iwlwifi/Makefile b/drivers/net/wireless/intel/iwlwifi/Makefile
index 6746281350e0e..504381b4aac7c 100644
--- a/drivers/net/wireless/intel/iwlwifi/Makefile
+++ b/drivers/net/wireless/intel/iwlwifi/Makefile
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 # common
 obj-$(CONFIG_IWLWIFI)	+= iwlwifi.o
-iwlwifi-objs		+= iwl-io.o
 iwlwifi-objs		+= iwl-drv.o
 iwlwifi-objs		+= iwl-debug.o
 iwlwifi-objs		+= iwl-nvm-utils.o
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c
index ec94c43ba28c1..799599efdd06e 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/debugfs.c
@@ -2,7 +2,7 @@
 /******************************************************************************
  *
  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
- * Copyright (C) 2018, 2025 Intel Corporation
+ * Copyright (C) 2018, 2025-2026 Intel Corporation
  *****************************************************************************/
 
 #include <linux/slab.h>
@@ -14,7 +14,6 @@
 
 #include "iwl-debug.h"
 #include "iwl-trans.h"
-#include "iwl-io.h"
 #include "dev.h"
 #include "agn.h"
 
@@ -1788,7 +1787,7 @@ static ssize_t iwl_dbgfs_power_save_status_read(struct file *file,
 	const size_t bufsz = sizeof(buf);
 	u32 pwrsave_status;
 
-	pwrsave_status = iwl_read32(priv->trans, CSR_GP_CNTRL) &
+	pwrsave_status = iwl_trans_read32(priv->trans, CSR_GP_CNTRL) &
 			CSR_GP_REG_POWER_SAVE_STATUS_MSK;
 
 	pos += scnprintf(buf + pos, bufsz - pos, "Power Save Status: ");
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/devices.c b/drivers/net/wireless/intel/iwlwifi/dvm/devices.c
index 7f83f1bbdaad8..b7bd5e6deb5d1 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/devices.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/devices.c
@@ -2,7 +2,7 @@
 /******************************************************************************
  *
  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
- * Copyright (C) 2019, 2025 Intel Corporation
+ * Copyright (C) 2019, 2025-2026 Intel Corporation
  *****************************************************************************/
 
 #include <linux/units.h>
@@ -10,7 +10,7 @@
 /*
  * DVM device-specific data & functions
  */
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "iwl-nvm-utils.h"
 
@@ -45,10 +45,10 @@ static void iwl1000_set_ct_threshold(struct iwl_priv *priv)
 static void iwl1000_nic_config(struct iwl_priv *priv)
 {
 	/* Setting digital SVR for 1000 card to 1.32V */
-	/* locking is acquired in iwl_set_bits_mask_prph() function */
-	iwl_set_bits_mask_prph(priv->trans, APMG_DIGITAL_SVR_REG,
-				APMG_SVR_DIGITAL_VOLTAGE_1_32,
-				~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
+	/* locking is acquired in iwl_trans_set_bits_mask_prph() function */
+	iwl_trans_set_bits_mask_prph(priv->trans, APMG_DIGITAL_SVR_REG,
+				     APMG_SVR_DIGITAL_VOLTAGE_1_32,
+				     ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
 }
 
 /**
@@ -184,8 +184,8 @@ static void iwl2000_set_ct_threshold(struct iwl_priv *priv)
 /* NIC configuration for 2000 series */
 static void iwl2000_nic_config(struct iwl_priv *priv)
 {
-	iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
-		    CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);
+	iwl_trans_set_bit(priv->trans, CSR_GP_DRIVER_REG,
+			  CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);
 }
 
 static const struct iwl_sensitivity_ranges iwl2000_sensitivity = {
@@ -490,22 +490,22 @@ static void iwl6000_nic_config(struct iwl_priv *priv)
 		break;
 	case IWL_DEVICE_FAMILY_6000i:
 		/* 2x2 IPA phy type */
-		iwl_write32(priv->trans, CSR_GP_DRIVER_REG,
-			     CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);
+		iwl_trans_write32(priv->trans, CSR_GP_DRIVER_REG,
+				  CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);
 		break;
 	case IWL_DEVICE_FAMILY_6050:
 		/* Indicate calibration version to uCode. */
 		if (priv->nvm_data->calib_version >= 6)
-			iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
-					CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
+			iwl_trans_set_bit(priv->trans, CSR_GP_DRIVER_REG,
+					  CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
 		break;
 	case IWL_DEVICE_FAMILY_6150:
 		/* Indicate calibration version to uCode. */
 		if (priv->nvm_data->calib_version >= 6)
-			iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
-					CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
-		iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
-			    CSR_GP_DRIVER_REG_BIT_6050_1x2);
+			iwl_trans_set_bit(priv->trans, CSR_GP_DRIVER_REG,
+					  CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
+		iwl_trans_set_bit(priv->trans, CSR_GP_DRIVER_REG,
+				  CSR_GP_DRIVER_REG_BIT_6050_1x2);
 		break;
 	default:
 		WARN_ON(1);
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c b/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c
index 6de2517188f73..190e482849ac2 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2025 Intel Corporation
+ * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2026 Intel Corporation
  */
 #include <linux/types.h>
 #include <linux/slab.h>
@@ -8,7 +8,7 @@
 
 #include "iwl-drv.h"
 #include "iwl-debug.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "iwl-csr.h"
 #include "agn.h"
@@ -672,13 +672,13 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
 
 	for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) {
 		/* Request semaphore */
-		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-			    CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);
+		iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+				  CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);
 
 		/* See if we got it */
-		ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
-				    CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
-				    IWL_EEPROM_SEM_TIMEOUT);
+		ret = iwl_trans_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
+					  CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
+					  IWL_EEPROM_SEM_TIMEOUT);
 		if (!ret) {
 			IWL_DEBUG_EEPROM(trans->dev,
 					 "Acquired semaphore after %d tries.\n",
@@ -692,13 +692,13 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
 
 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
 {
-	iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
-		      CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);
+	iwl_trans_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
+			    CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);
 }
 
 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
 {
-	u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
+	u32 gp = iwl_trans_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
 
 	IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
 
@@ -734,10 +734,10 @@ static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
 
 static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
 {
-	iwl_read32(trans, CSR_OTP_GP_REG);
+	iwl_trans_read32(trans, CSR_OTP_GP_REG);
 
-	iwl_clear_bit(trans, CSR_OTP_GP_REG,
-		      CSR_OTP_GP_REG_OTP_ACCESS_MODE);
+	iwl_trans_clear_bit(trans, CSR_OTP_GP_REG,
+			    CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 }
 
 static int iwl_nvm_is_otp(struct iwl_trans *trans)
@@ -755,7 +755,7 @@ static int iwl_nvm_is_otp(struct iwl_trans *trans)
 	case CSR_HW_REV_TYPE_5150:
 		return 0;
 	default:
-		otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
+		otpgp = iwl_trans_read32(trans, CSR_OTP_GP_REG);
 		if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
 			return 1;
 		return 0;
@@ -770,19 +770,19 @@ static int iwl_init_otp_access(struct iwl_trans *trans)
 	if (ret)
 		return ret;
 
-	iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
-			  APMG_PS_CTRL_VAL_RESET_REQ);
+	iwl_trans_set_bits_prph(trans, APMG_PS_CTRL_REG,
+				APMG_PS_CTRL_VAL_RESET_REQ);
 	udelay(5);
-	iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
-			    APMG_PS_CTRL_VAL_RESET_REQ);
+	iwl_trans_clear_bits_prph(trans, APMG_PS_CTRL_REG,
+				  APMG_PS_CTRL_VAL_RESET_REQ);
 
 	/*
 	 * CSR auto clock gate disable bit -
 	 * this is only applicable for HW with OTP shadow RAM
 	 */
 	if (trans->mac_cfg->base->shadow_ram_support)
-		iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
-			    CSR_RESET_LINK_PWR_MGMT_DISABLED);
+		iwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+				  CSR_RESET_LINK_PWR_MGMT_DISABLED);
 
 	return 0;
 }
@@ -794,31 +794,31 @@ static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
 	u32 r;
 	u32 otpgp;
 
-	iwl_write32(trans, CSR_EEPROM_REG,
-		    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
-	ret = iwl_poll_bits(trans, CSR_EEPROM_REG,
-			    CSR_EEPROM_REG_READ_VALID_MSK,
-			    IWL_EEPROM_ACCESS_TIMEOUT);
+	iwl_trans_write32(trans, CSR_EEPROM_REG,
+			  CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
+	ret = iwl_trans_poll_bits(trans, CSR_EEPROM_REG,
+				  CSR_EEPROM_REG_READ_VALID_MSK,
+				  IWL_EEPROM_ACCESS_TIMEOUT);
 	if (ret) {
 		IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
 		return ret;
 	}
-	r = iwl_read32(trans, CSR_EEPROM_REG);
+	r = iwl_trans_read32(trans, CSR_EEPROM_REG);
 	/* check for ECC errors: */
-	otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
+	otpgp = iwl_trans_read32(trans, CSR_OTP_GP_REG);
 	if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
 		/* stop in this case */
 		/* set the uncorrectable OTP ECC bit for acknowledgment */
-		iwl_set_bit(trans, CSR_OTP_GP_REG,
-			    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
+		iwl_trans_set_bit(trans, CSR_OTP_GP_REG,
+				  CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 		IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
 		return -EINVAL;
 	}
 	if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
 		/* continue in this case */
 		/* set the correctable OTP ECC bit for acknowledgment */
-		iwl_set_bit(trans, CSR_OTP_GP_REG,
-			    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
+		iwl_trans_set_bit(trans, CSR_OTP_GP_REG,
+				  CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
 		IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
 	}
 	*eeprom_data = cpu_to_le16(r >> 16);
@@ -918,7 +918,7 @@ static int iwl_find_otp_image(struct iwl_trans *trans,
 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
 {
 	__le16 *e;
-	u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
+	u32 gp = iwl_trans_read32(trans, CSR_EEPROM_GP);
 	int sz;
 	int ret;
 	u16 addr;
@@ -960,13 +960,13 @@ int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
 			goto err_unlock;
 		}
 
-		iwl_write32(trans, CSR_EEPROM_GP,
-			    iwl_read32(trans, CSR_EEPROM_GP) &
-			    ~CSR_EEPROM_GP_IF_OWNER_MSK);
+		iwl_trans_write32(trans, CSR_EEPROM_GP,
+				  iwl_trans_read32(trans, CSR_EEPROM_GP) &
+				  ~CSR_EEPROM_GP_IF_OWNER_MSK);
 
-		iwl_set_bit(trans, CSR_OTP_GP_REG,
-			    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
-			    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
+		iwl_trans_set_bit(trans, CSR_OTP_GP_REG,
+				  CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
+				  CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 		/* traversing the linked list if no shadow ram supported */
 		if (!trans->mac_cfg->base->shadow_ram_support) {
 			ret = iwl_find_otp_image(trans, &validblockaddr);
@@ -988,18 +988,18 @@ int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
 		for (addr = 0; addr < sz; addr += sizeof(u16)) {
 			u32 r;
 
-			iwl_write32(trans, CSR_EEPROM_REG,
-				    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
+			iwl_trans_write32(trans, CSR_EEPROM_REG,
+					  CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 
-			ret = iwl_poll_bits(trans, CSR_EEPROM_REG,
-					    CSR_EEPROM_REG_READ_VALID_MSK,
-					    IWL_EEPROM_ACCESS_TIMEOUT);
+			ret = iwl_trans_poll_bits(trans, CSR_EEPROM_REG,
+						  CSR_EEPROM_REG_READ_VALID_MSK,
+						  IWL_EEPROM_ACCESS_TIMEOUT);
 			if (ret) {
 				IWL_ERR(trans,
 					"Time out reading EEPROM[%d]\n", addr);
 				goto err_unlock;
 			}
-			r = iwl_read32(trans, CSR_EEPROM_REG);
+			r = iwl_trans_read32(trans, CSR_EEPROM_REG);
 			e[addr / 2] = cpu_to_le16(r >> 16);
 		}
 	}
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/led.c b/drivers/net/wireless/intel/iwlwifi/dvm/led.c
index cec2ebdfd6519..17b045ddb910c 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/led.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/led.c
@@ -2,7 +2,7 @@
 /******************************************************************************
  *
  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
- * Copyright (C) 2019, 2025 Intel Corporation
+ * Copyright (C) 2019, 2025-2026 Intel Corporation
  *****************************************************************************/
 
 
@@ -14,7 +14,6 @@
 #include <net/mac80211.h>
 #include <linux/etherdevice.h>
 #include <linux/unaligned.h>
-#include "iwl-io.h"
 #include "iwl-trans.h"
 #include "iwl-modparams.h"
 #include "dev.h"
@@ -49,7 +48,7 @@ static const struct ieee80211_tpt_blink iwl_blink[] = {
 /* Set led register off */
 void iwlagn_led_enable(struct iwl_priv *priv)
 {
-	iwl_write32(priv->trans, CSR_LED_REG, CSR_LED_REG_TURN_ON);
+	iwl_trans_write32(priv->trans, CSR_LED_REG, CSR_LED_REG_TURN_ON);
 }
 
 /*
@@ -85,10 +84,10 @@ static int iwl_send_led_cmd(struct iwl_priv *priv, struct iwl_led_cmd *led_cmd)
 	};
 	u32 reg;
 
-	reg = iwl_read32(priv->trans, CSR_LED_REG);
+	reg = iwl_trans_read32(priv->trans, CSR_LED_REG);
 	if (reg != (reg & CSR_LED_BSM_CTRL_MSK))
-		iwl_write32(priv->trans, CSR_LED_REG,
-			    reg & CSR_LED_BSM_CTRL_MSK);
+		iwl_trans_write32(priv->trans, CSR_LED_REG,
+				  reg & CSR_LED_BSM_CTRL_MSK);
 
 	return iwl_dvm_send_cmd(priv, &cmd);
 }
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/lib.c b/drivers/net/wireless/intel/iwlwifi/dvm/lib.c
index 2e16799818e47..37d6f2cf7efb7 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/lib.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/lib.c
@@ -2,6 +2,7 @@
 /******************************************************************************
  *
  * Copyright(c) 2008 - 2014, 2022 Intel Corporation. All rights reserved.
+ * Copyright (C) 2026 Intel Corporation
  *****************************************************************************/
 #include <linux/etherdevice.h>
 #include <linux/kernel.h>
@@ -9,7 +10,6 @@
 #include <linux/sched.h>
 #include <net/mac80211.h>
 
-#include "iwl-io.h"
 #include "iwl-agn-hw.h"
 #include "iwl-trans.h"
 #include "iwl-modparams.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c
index a0a26ef482a5e..e83bf615c1617 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c
@@ -2,7 +2,7 @@
 /******************************************************************************
  *
  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
- * Copyright(C) 2018 - 2019, 2022 - 2025 Intel Corporation
+ * Copyright(C) 2018 - 2019, 2022 - 2026 Intel Corporation
  *
  * Portions of this file are derived from the ipw3945 project, as well
  * as portions of the ieee80211 subsystem header files.
@@ -23,7 +23,6 @@
 
 #include <asm/div64.h>
 
-#include "iwl-io.h"
 #include "iwl-trans.h"
 #include "iwl-op-mode.h"
 #include "iwl-modparams.h"
@@ -375,8 +374,8 @@ static int iwlagn_mac_suspend(struct ieee80211_hw *hw,
 		goto error;
 
 	/* let the ucode operate on its own */
-	iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
-		    CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
+	iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
+			  CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
 
 	iwl_trans_d3_suspend(priv->trans, true);
 
@@ -455,8 +454,8 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
 		goto out_unlock;
 
 	/* uCode is no longer operating by itself */
-	iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
-		    CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
+	iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
+			  CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
 
 	base = priv->device_pointers.error_event_table;
 	if (!iwlagn_hw_valid_rtc_data_addr(base)) {
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/main.c b/drivers/net/wireless/intel/iwlwifi/dvm/main.c
index 6bd5b6d84b2a9..4bf69f7a35a64 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/main.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/main.c
@@ -2,7 +2,7 @@
 /******************************************************************************
  *
  * Copyright(c) 2003 - 2014, 2018 - 2022 Intel Corporation. All rights reserved.
- * Copyright(c) 2024-2025 Intel Corporation. All rights reserved.
+ * Copyright(c) 2024-2026 Intel Corporation. All rights reserved.
  * Copyright(c) 2015 Intel Deutschland GmbH
  *
  * Portions of this file are derived from the ipw3945 project, as well
@@ -27,8 +27,8 @@
 #include <asm/div64.h>
 
 #include "iwl-nvm-utils.h"
-#include "iwl-io.h"
 #include "iwl-trans.h"
+#include "iwl-devtrace.h"
 #include "iwl-op-mode.h"
 #include "iwl-drv.h"
 #include "iwl-modparams.h"
@@ -413,7 +413,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 		return;
 
 	/* Set starting address; reads will auto-increment */
-	iwl_write32(priv->trans, HBUS_TARG_MEM_RADDR, ptr);
+	iwl_trans_write32(priv->trans, HBUS_TARG_MEM_RADDR, ptr);
 
 	/*
 	 * Refuse to read more than would have fit into the log from
@@ -429,13 +429,13 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 	 * place event id # at far right for easier visual parsing.
 	 */
 	for (i = 0; i < num_events; i++) {
-		ev = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT);
-		time = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT);
+		ev = iwl_trans_read32(priv->trans, HBUS_TARG_MEM_RDAT);
+		time = iwl_trans_read32(priv->trans, HBUS_TARG_MEM_RDAT);
 		if (mode == 0) {
 			trace_iwlwifi_dev_ucode_cont_event(
 					priv->trans->dev, 0, time, ev);
 		} else {
-			data = iwl_read32(priv->trans, HBUS_TARG_MEM_RDAT);
+			data = iwl_trans_read32(priv->trans, HBUS_TARG_MEM_RDAT);
 			trace_iwlwifi_dev_ucode_cont_event(
 					priv->trans->dev, time, data, ev);
 		}
@@ -661,8 +661,8 @@ static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
 	struct iwl_ct_kill_throttling_config adv_cmd;
 	int ret = 0;
 
-	iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
-		    CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
+	iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
+			  CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
 
 	priv->thermal_throttle.ct_kill_toggle = false;
 
@@ -1731,13 +1731,13 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
 		return pos;
 
 	/* Set starting address; reads will auto-increment */
-	iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
+	iwl_trans_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
 
 	/* "time" is actually "data" for mode 0 (no timestamp).
 	* place event id # at far right for easier visual parsing. */
 	for (i = 0; i < num_events; i++) {
-		ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
-		time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
+		ev = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);
+		time = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);
 		if (mode == 0) {
 			/* data, ev */
 			if (bufsz) {
@@ -1751,7 +1751,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
 					time, ev);
 			}
 		} else {
-			data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
+			data = iwl_trans_read32(trans, HBUS_TARG_MEM_RDAT);
 			if (bufsz) {
 				pos += scnprintf(*buf + pos, bufsz - pos,
 						"EVT_LOGT:%010u:0x%08x:%04u\n",
@@ -2028,17 +2028,17 @@ static void iwl_nic_config(struct iwl_op_mode *op_mode)
 	}
 
 	/* set CSR_HW_CONFIG_REG for uCode use */
-	iwl_set_bit(priv->trans, CSR_HW_IF_CONFIG_REG,
-		    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
-		    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
+	iwl_trans_set_bit(priv->trans, CSR_HW_IF_CONFIG_REG,
+			  CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
+			  CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 
 	/* W/A : NIC is stuck in a reset state after Early PCIe power off
 	 * (PCIe power is lost before PERST# is asserted),
 	 * causing ME FW to lose ownership and not being able to obtain it back.
 	 */
-	iwl_set_bits_mask_prph(priv->trans, APMG_PS_CTRL_REG,
-			       APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
-			       ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
+	iwl_trans_set_bits_mask_prph(priv->trans, APMG_PS_CTRL_REG,
+				     APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
+				     ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 
 	if (priv->lib->nic_config)
 		priv->lib->nic_config(priv);
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/power.c b/drivers/net/wireless/intel/iwlwifi/dvm/power.c
index e7dbba7134f72..4e19799d15d75 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/power.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/power.c
@@ -2,7 +2,7 @@
 /******************************************************************************
  *
  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
- * Copyright (C) 2019, 2025 Intel Corporation
+ * Copyright (C) 2019, 2025-2026 Intel Corporation
  *
  * Portions of this file are derived from the ipw3945 project, as well
  * as portions of the ieee80211 subsystem header files.
@@ -13,7 +13,6 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <net/mac80211.h>
-#include "iwl-io.h"
 #include "iwl-debug.h"
 #include "iwl-trans.h"
 #include "iwl-modparams.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/rx.c b/drivers/net/wireless/intel/iwlwifi/dvm/rx.c
index 088302a238dec..fa2aff5bea6c0 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/rx.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/rx.c
@@ -3,7 +3,7 @@
  *
  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
  * Copyright(c) 2015 Intel Deutschland GmbH
- * Copyright(c) 2018, 2020-2021, 2025 Intel Corporation
+ * Copyright(c) 2018, 2020-2021, 2025-2026 Intel Corporation
  *
  * Portions of this file are derived from the ipw3945 project, as well
  * as portionhelp of the ieee80211 subsystem header files.
@@ -16,7 +16,6 @@
 #include <linux/unaligned.h>
 
 #include "iwl-trans.h"
-#include "iwl-io.h"
 #include "dev.h"
 #include "calib.h"
 #include "agn.h"
@@ -482,17 +481,17 @@ static void iwlagn_rx_card_state_notif(struct iwl_priv *priv,
 	if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 		     CT_CARD_DISABLED)) {
 
-		iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
-			    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
+		iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
+				  CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 
-		iwl_write_direct32(priv->trans, HBUS_TARG_MBX_C,
-					HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
+		iwl_trans_write_direct32(priv->trans, HBUS_TARG_MBX_C,
+					 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 
 		if (!(flags & RXON_CARD_DISABLED)) {
-			iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
-				    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
-			iwl_write_direct32(priv->trans, HBUS_TARG_MBX_C,
-					HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
+			iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
+					  CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
+			iwl_trans_write_direct32(priv->trans, HBUS_TARG_MBX_C,
+						 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 		}
 		if (flags & CT_CARD_DISABLED)
 			iwl_tt_enter_ct_kill(priv);
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/tt.c b/drivers/net/wireless/intel/iwlwifi/dvm/tt.c
index fc9cf0531024a..a414eb7c24460 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/tt.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/tt.c
@@ -2,7 +2,7 @@
 /******************************************************************************
  *
  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
- * Copyright (C) 2018, 2020 Intel Corporation
+ * Copyright (C) 2018, 2020, 2026 Intel Corporation
  *
  * Portions of this file are derived from the ipw3945 project, as well
  * as portions of the ieee80211 subsystem header files.
@@ -13,7 +13,7 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <net/mac80211.h>
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-modparams.h"
 #include "iwl-debug.h"
 #include "agn.h"
@@ -146,15 +146,15 @@ static void iwl_tt_check_exit_ct_kill(struct timer_list *t)
 
 	if (tt->state == IWL_TI_CT_KILL) {
 		if (priv->thermal_throttle.ct_kill_toggle) {
-			iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
-				    CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
+			iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
+					  CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
 			priv->thermal_throttle.ct_kill_toggle = false;
 		} else {
-			iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
-				    CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
+			iwl_trans_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
+					  CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
 			priv->thermal_throttle.ct_kill_toggle = true;
 		}
-		iwl_read32(priv->trans, CSR_UCODE_DRV_GP1);
+		iwl_trans_read32(priv->trans, CSR_UCODE_DRV_GP1);
 		if (iwl_trans_grab_nic_access(priv->trans))
 			iwl_trans_release_nic_access(priv->trans);
 
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/tx.c b/drivers/net/wireless/intel/iwlwifi/dvm/tx.c
index 1a0167f67c7bd..8dbc52971e7bb 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/tx.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/tx.c
@@ -3,14 +3,13 @@
  *
  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
  * Copyright (C) 2019 Intel Corporation
- * Copyright (C) 2023, 2025 Intel Corporation
+ * Copyright (C) 2023, 2025-2026 Intel Corporation
  *****************************************************************************/
 
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/ieee80211.h>
-#include "iwl-io.h"
 #include "iwl-trans.h"
 #include "iwl-agn-hw.h"
 #include "dev.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c b/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c
index ac90191a39735..2ab1a32d774e5 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/ucode.c
@@ -3,12 +3,11 @@
  *
  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
  * Copyright(c) 2015 Intel Deutschland GmbH
- * Copyright (C) 2025 Intel Corporation
+ * Copyright (C) 2025-2026 Intel Corporation
  *****************************************************************************/
 
 #include <linux/kernel.h>
 
-#include "iwl-io.h"
 #include "iwl-agn-hw.h"
 #include "iwl-trans.h"
 #include "iwl-fh.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h
index d3bed0216df48..9f7407c4f980c 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2026 Intel Corporation
  * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
  * Copyright (C) 2015-2017 Intel Deutschland GmbH
  */
@@ -366,7 +366,6 @@ enum iwl_wowlan_flags {
 	ENABLE_L3_FILTERING	= BIT(1),
 	ENABLE_NBNS_FILTERING	= BIT(2),
 	ENABLE_DHCP_FILTERING	= BIT(3),
-	ENABLE_STORE_BEACON	= BIT(4),
 	HAS_BEACON_PROTECTION	= BIT(5),
 };
 
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h
index 31d3336726b42..9d9eb320db7b0 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2026 Intel Corporation
  * Copyright (C) 2016-2017 Intel Deutschland GmbH
  */
 #ifndef __iwl_fw_api_tx_h__
@@ -292,6 +292,9 @@ struct iwl_tx_cmd_v9 {
  * @dram_info: FW internal DRAM storage
  * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
  *	cleared. Combination of RATE_MCS_*; format depends on version
+ * @driver_timestamp: gp2 time, in microseconds, assigned before queueing the
+ *	MPDU. Firmware uses it to detect frames blocked for too long.
+ *	Zero means no timestamp. Used from TX_CMD_API_S_VER_12.
  * @reserved: reserved
  * @hdr: 802.11 header
  */
@@ -301,10 +304,12 @@ struct iwl_tx_cmd {
 	__le32 offload_assist;
 	struct iwl_dram_sec_info dram_info;
 	__le32 rate_n_flags;
-	u8 reserved[8];
+	__le32 driver_timestamp;
+	u8 reserved[4];
 	struct ieee80211_hdr hdr[];
 } __packed; /* TX_CMD_API_S_VER_10,
-	     * TX_CMD_API_S_VER_11
+	     * TX_CMD_API_S_VER_11,
+	     * TX_CMD_API_S_VER_12
 	     */
 
 /*
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c
index 19b1bfd0abee4..09c798d2eba33 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg-old.c
@@ -9,7 +9,7 @@
 #include "runtime.h"
 #include "dbg.h"
 #include "debugfs.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "iwl-csr.h"
 #include "iwl-fh.h"
@@ -47,8 +47,8 @@ static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
 		u32 rd_cmd = RADIO_RSP_RD_CMD;
 
 		rd_cmd |= i << RADIO_RSP_ADDR_POS;
-		iwl_trans_write_prph(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
-		*pos = (u8)iwl_trans_read_prph(fwrt->trans, RSP_RADIO_RDDAT);
+		iwl_trans_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
+		*pos = (u8)iwl_trans_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
 
 		pos++;
 	}
@@ -81,35 +81,35 @@ static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
 
 	fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
 	fifo_hdr->available_bytes =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						RXF_RD_D_SPACE + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							RXF_RD_D_SPACE + offset));
 	fifo_hdr->wr_ptr =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						RXF_RD_WR_PTR + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							RXF_RD_WR_PTR + offset));
 	fifo_hdr->rd_ptr =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						RXF_RD_RD_PTR + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							RXF_RD_RD_PTR + offset));
 	fifo_hdr->fence_ptr =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						RXF_RD_FENCE_PTR + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							RXF_RD_FENCE_PTR + offset));
 	fifo_hdr->fence_mode =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						RXF_SET_FENCE_MODE + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							RXF_SET_FENCE_MODE + offset));
 
 	/* Lock fence */
-	iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
+	iwl_trans_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
 	/* Set fence pointer to the same place like WR pointer */
-	iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
+	iwl_trans_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
 	/* Set fence offset */
-	iwl_trans_write_prph(fwrt->trans,
-			     RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
+	iwl_trans_write_prph_no_grab(fwrt->trans,
+				     RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
 
 	/* Read FIFO */
 	fifo_len /= sizeof(u32); /* Size in DWORDS */
 	for (i = 0; i < fifo_len; i++)
-		fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
-						 RXF_FIFO_RD_FENCE_INC +
-						 offset);
+		fifo_data[i] = iwl_trans_read_prph_no_grab(fwrt->trans,
+							   RXF_FIFO_RD_FENCE_INC +
+							   offset);
 	*dump_data = iwl_fw_error_next_data(*dump_data);
 }
 
@@ -136,33 +136,33 @@ static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
 
 	fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
 	fifo_hdr->available_bytes =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						TXF_FIFO_ITEM_CNT + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							TXF_FIFO_ITEM_CNT + offset));
 	fifo_hdr->wr_ptr =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						TXF_WR_PTR + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							TXF_WR_PTR + offset));
 	fifo_hdr->rd_ptr =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						TXF_RD_PTR + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							TXF_RD_PTR + offset));
 	fifo_hdr->fence_ptr =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						TXF_FENCE_PTR + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							TXF_FENCE_PTR + offset));
 	fifo_hdr->fence_mode =
-		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-						TXF_LOCK_FENCE + offset));
+		cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+							TXF_LOCK_FENCE + offset));
 
 	/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
-	iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
-			     TXF_WR_PTR + offset);
+	iwl_trans_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
+				     TXF_WR_PTR + offset);
 
 	/* Dummy-read to advance the read pointer to the head */
-	iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
+	iwl_trans_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
 
 	/* Read FIFO */
 	for (i = 0; i < fifo_len / sizeof(u32); i++)
-		fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
-						  TXF_READ_MODIFY_DATA +
-						  offset);
+		fifo_data[i] = iwl_trans_read_prph_no_grab(fwrt->trans,
+							   TXF_READ_MODIFY_DATA +
+							   offset);
 
 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
 		fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
@@ -217,7 +217,7 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
 		/* Pull TXF data from LMAC1 */
 		for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
 			/* Mark the number of TXF we're pulling now */
-			iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
+			iwl_trans_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM, i);
 			iwl_fwrt_dump_txf(fwrt, dump_data,
 					  cfg->lmac[0].txfifo_size[i], 0, i);
 		}
@@ -227,9 +227,9 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
 			for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
 			     i++) {
 				/* Mark the number of TXF we're pulling now */
-				iwl_trans_write_prph(fwrt->trans,
-						     TXF_LARC_NUM +
-						     LMAC2_PRPH_OFFSET, i);
+				iwl_trans_write_prph_no_grab(fwrt->trans,
+							     TXF_LARC_NUM +
+							     LMAC2_PRPH_OFFSET, i);
 				iwl_fwrt_dump_txf(fwrt, dump_data,
 						  cfg->lmac[1].txfifo_size[i],
 						  LMAC2_PRPH_OFFSET,
@@ -262,40 +262,40 @@ static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
 			fifo_hdr->fifo_num = cpu_to_le32(i);
 
 			/* Mark the number of TXF we're pulling now */
-			iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
-				fwrt->smem_cfg.num_txfifo_entries);
+			iwl_trans_write_prph_no_grab(fwrt->trans, TXF_CPU2_NUM, i +
+						     fwrt->smem_cfg.num_txfifo_entries);
 
 			fifo_hdr->available_bytes =
-				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-								TXF_CPU2_FIFO_ITEM_CNT));
+				cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+									TXF_CPU2_FIFO_ITEM_CNT));
 			fifo_hdr->wr_ptr =
-				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-								TXF_CPU2_WR_PTR));
+				cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+									TXF_CPU2_WR_PTR));
 			fifo_hdr->rd_ptr =
-				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-								TXF_CPU2_RD_PTR));
+				cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+									TXF_CPU2_RD_PTR));
 			fifo_hdr->fence_ptr =
-				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-								TXF_CPU2_FENCE_PTR));
+				cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+									TXF_CPU2_FENCE_PTR));
 			fifo_hdr->fence_mode =
-				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-								TXF_CPU2_LOCK_FENCE));
+				cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+									TXF_CPU2_LOCK_FENCE));
 
 			/* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
-			iwl_trans_write_prph(fwrt->trans,
-					     TXF_CPU2_READ_MODIFY_ADDR,
-					     TXF_CPU2_WR_PTR);
+			iwl_trans_write_prph_no_grab(fwrt->trans,
+						     TXF_CPU2_READ_MODIFY_ADDR,
+						     TXF_CPU2_WR_PTR);
 
 			/* Dummy-read to advance the read pointer to head */
-			iwl_trans_read_prph(fwrt->trans,
-					    TXF_CPU2_READ_MODIFY_DATA);
+			iwl_trans_read_prph_no_grab(fwrt->trans,
+						    TXF_CPU2_READ_MODIFY_DATA);
 
 			/* Read FIFO */
 			fifo_len /= sizeof(u32); /* Size in DWORDS */
 			for (j = 0; j < fifo_len; j++)
 				fifo_data[j] =
-					iwl_trans_read_prph(fwrt->trans,
-							    TXF_CPU2_READ_MODIFY_DATA);
+					iwl_trans_read_prph_no_grab(fwrt->trans,
+								    TXF_CPU2_READ_MODIFY_DATA);
 			*dump_data = iwl_fw_error_next_data(*dump_data);
 		}
 	}
@@ -514,7 +514,7 @@ static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
 	u32 i;
 
 	for (i = 0; i < len_bytes; i += 4)
-		*data++ = cpu_to_le32(iwl_trans_read_prph(trans, start + i));
+		*data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(trans, start + i));
 }
 
 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
index 897538066b7de..1d34ad59bb71f 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
@@ -9,7 +9,7 @@
 #include "runtime.h"
 #include "dbg.h"
 #include "debugfs.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "iwl-csr.h"
 #include "iwl-fh.h"
@@ -103,7 +103,7 @@ static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt,
 	range->internal_base_addr = cpu_to_le32(addr);
 	range->range_data_size = size;
 	for (i = 0; i < le32_to_cpu(size); i += 4)
-		*val++ = cpu_to_le32(iwl_trans_read_prph(fwrt->trans, addr + i));
+		*val++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, addr + i));
 
 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
 }
@@ -159,7 +159,7 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt,
 	indirect_rd_addr += le32_to_cpu(offset);
 
 	dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;
-	dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
+	dphy_state = iwl_trans_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
 
 	for (i = 0; i < le32_to_cpu(size); i += 4) {
 		if (dphy_state == HBUS_TIMEOUT ||
@@ -169,16 +169,16 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt,
 			continue;
 		}
 
-		iwl_trans_write_prph(fwrt->trans, indirect_wr_addr,
-				     WMAL_INDRCT_CMD(addr + i));
+		iwl_trans_write_prph_no_grab(fwrt->trans, indirect_wr_addr,
+					     WMAL_INDRCT_CMD(addr + i));
 
 		if (fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_JF1 &&
 		    fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_JF2 &&
 		    fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_HR1 &&
 		    fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_HR2) {
 			udelay(2);
-			prph_stts = iwl_trans_read_prph(fwrt->trans,
-							WMAL_MRSPF_STTS);
+			prph_stts = iwl_trans_read_prph_no_grab(fwrt->trans,
+								WMAL_MRSPF_STTS);
 
 			/* Abort dump if status is 0xA5A5A5A2 or FIFO1 empty */
 			if (prph_stts == WMAL_TIMEOUT_VAL ||
@@ -186,8 +186,8 @@ static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt,
 				break;
 		}
 
-		prph_val = iwl_trans_read_prph(fwrt->trans,
-					       indirect_rd_addr);
+		prph_val = iwl_trans_read_prph_no_grab(fwrt->trans,
+						       indirect_rd_addr);
 		*val++ = cpu_to_le32(prph_val);
 	}
 
@@ -446,7 +446,7 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
 	range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
 	range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size);
 
-	iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
+	iwl_trans_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
 
 	/*
 	 * read txf registers. for each register, write to the dump the
@@ -456,8 +456,8 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
 		addr = le32_to_cpu(reg->addrs[i]) + offs;
 
 		reg_dump->addr = cpu_to_le32(addr);
-		reg_dump->data = cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-								 addr));
+		reg_dump->data = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+									 addr));
 
 		reg_dump++;
 	}
@@ -468,17 +468,17 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
 	}
 
 	/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
-	iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
-			     TXF_WR_PTR + offs);
+	iwl_trans_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
+				     TXF_WR_PTR + offs);
 
 	/* Dummy-read to advance the read pointer to the head */
-	iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
+	iwl_trans_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
 
 	/* Read FIFO */
 	addr = TXF_READ_MODIFY_DATA + offs;
 	data = (void *)reg_dump;
 	for (i = 0; i < iter->fifo_size; i += sizeof(*data))
-		*data++ = cpu_to_le32(iwl_trans_read_prph(fwrt->trans, addr));
+		*data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, addr));
 
 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
 		fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
@@ -508,7 +508,7 @@ iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt,
 	indirect_rd_wr_addr += le32_to_cpu(offset);
 
 	dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;
-	dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
+	dphy_state = iwl_trans_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
 
 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
 		if (dphy_state == HBUS_TIMEOUT ||
@@ -518,12 +518,12 @@ iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt,
 			continue;
 		}
 
-		iwl_trans_write_prph(fwrt->trans, indirect_rd_wr_addr,
-				     addr + i);
+		iwl_trans_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr,
+					     addr + i);
 		/* wait a bit for value to be ready in register */
 		udelay(1);
-		prph_val = iwl_trans_read_prph(fwrt->trans,
-					       indirect_rd_wr_addr);
+		prph_val = iwl_trans_read_prph_no_grab(fwrt->trans,
+						       indirect_rd_wr_addr);
 		*val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >>
 				     DPHYIP_INDIRECT_RD_SHIFT);
 	}
@@ -586,13 +586,13 @@ static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,
 		switch (fifo_idx) {
 		case 0:
 			data->size = fwrt->smem_cfg.rxfifo2_size;
-			data->offset = iwl_umac_prph(fwrt->trans,
-						     RXF_DIFF_FROM_PREV);
+			data->offset = iwl_trans_umac_prph(fwrt->trans,
+							   RXF_DIFF_FROM_PREV);
 			break;
 		case 1:
 			data->size = fwrt->smem_cfg.rxfifo2_control_size;
-			data->offset = iwl_umac_prph(fwrt->trans,
-						     RXF2C_DIFF_FROM_PREV);
+			data->offset = iwl_trans_umac_prph(fwrt->trans,
+							   RXF2C_DIFF_FROM_PREV);
 			break;
 		}
 	}
@@ -628,8 +628,8 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
 		addr = le32_to_cpu(reg->addrs[i]) + offs;
 
 		reg_dump->addr = cpu_to_le32(addr);
-		reg_dump->data = cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
-								 addr));
+		reg_dump->data = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans,
+									 addr));
 
 		reg_dump++;
 	}
@@ -642,17 +642,17 @@ static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
 	offs = rxf_data.offset;
 
 	/* Lock fence */
-	iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
+	iwl_trans_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
 	/* Set fence pointer to the same place like WR pointer */
-	iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
+	iwl_trans_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
 	/* Set fence offset */
-	iwl_trans_write_prph(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 0x0);
+	iwl_trans_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 0x0);
 
 	/* Read FIFO */
 	addr =  RXF_FIFO_RD_FENCE_INC + offs;
 	data = (void *)reg_dump;
 	for (i = 0; i < rxf_data.size; i += sizeof(*data))
-		*data++ = cpu_to_le32(iwl_trans_read_prph(fwrt->trans, addr));
+		*data++ = cpu_to_le32(iwl_trans_read_prph_no_grab(fwrt->trans, addr));
 
 out:
 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
@@ -712,10 +712,10 @@ iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,
 	range->range_data_size = reg->dev_addr.size;
 	for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {
 		prph_data =
-			iwl_trans_read_prph(fwrt->trans,
-					    (i % 2) ?
-						DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
-						DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
+			iwl_trans_read_prph_no_grab(fwrt->trans,
+						    (i % 2) ?
+						        DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
+						        DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
 		if (iwl_trans_is_hw_error_value(prph_data))
 			return -EBUSY;
 		*val++ = cpu_to_le32(prph_data);
@@ -812,7 +812,7 @@ static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id,
 	if (!reg_info || !reg_info->addr || !reg_info->mask)
 		return 0;
 
-	val = iwl_trans_read_prph(fwrt->trans, reg_info->addr + offs);
+	val = iwl_trans_read_prph_no_grab(fwrt->trans, reg_info->addr + offs);
 
 	return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask));
 }
@@ -1820,14 +1820,14 @@ static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
 			cpu_to_le32(IWL_FW_INI_APPLY_POLICY_SPLIT_DUMP_RESET)) {
 		size += iwl_dump_ini_dump_entries(fwrt, list,
 						  IWL_INI_DUMP_EARLY_REGIONS);
-		iwl_trans_pcie_fw_reset_handshake(fwrt->trans);
+		iwl_trans_fw_reset_handshake(fwrt->trans);
 		size += iwl_dump_ini_dump_entries(fwrt, list,
 						  IWL_INI_DUMP_LATE_REGIONS);
 	} else {
 		if (fw_has_capa(&fwrt->fw->ucode_capa,
 				IWL_UCODE_TLV_CAPA_RESET_DURING_ASSERT) &&
 		    iwl_dump_due_to_error(tp_id))
-			iwl_trans_pcie_fw_reset_handshake(fwrt->trans);
+			iwl_trans_fw_reset_handshake(fwrt->trans);
 		size += iwl_dump_ini_dump_entries(fwrt, list,
 						  IWL_INI_DUMP_ALL_REGIONS);
 	}
@@ -2381,21 +2381,21 @@ static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
 				      struct iwl_fw_dbg_params *params)
 {
 	if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
-		iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
+		iwl_trans_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
 		return;
 	}
 
 	if (params) {
-		params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);
-		params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);
+		params->in_sample = iwl_trans_read_umac_prph(trans, DBGC_IN_SAMPLE);
+		params->out_ctrl = iwl_trans_read_umac_prph(trans, DBGC_OUT_CTRL);
 	}
 
-	iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
+	iwl_trans_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
 	/* wait for the DBGC to finish writing the internal buffer to DRAM to
 	 * avoid halting the HW while writing
 	 */
 	usleep_range(700, 1000);
-	iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
+	iwl_trans_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
 }
 
 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
@@ -2405,12 +2405,12 @@ static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
 		return -EIO;
 
 	if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
-		iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
-		iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
-		iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
+		iwl_trans_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
+		iwl_trans_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
+		iwl_trans_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
 	} else {
-		iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
-		iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
+		iwl_trans_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
+		iwl_trans_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
 	}
 
 	return 0;
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h
index fc962a3205833..70134d8f03c4d 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h
@@ -10,7 +10,7 @@
 #include <net/cfg80211.h>
 #include "runtime.h"
 #include "iwl-prph.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "file.h"
 #include "error-dump.h"
 #include "api/commands.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dump.c b/drivers/net/wireless/intel/iwlwifi/fw/dump.c
index bbbf3669a555d..b76abc77f4959 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/dump.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/dump.c
@@ -9,7 +9,7 @@
 #include "runtime.h"
 #include "dbg.h"
 #include "debugfs.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "iwl-csr.h"
 #include "pnvm.h"
@@ -309,7 +309,7 @@ static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime *fwrt)
 		return;
 	}
 
-	error = iwl_read_umac_prph(trans, error);
+	error = iwl_trans_read_umac_prph(trans, error);
 
 	IWL_ERR(trans, "IML/ROM dump:\n");
 
@@ -318,11 +318,11 @@ static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime *fwrt)
 
 	IWL_ERR(fwrt, "0x%08X | IML/ROM error/state\n", error);
 	IWL_ERR(fwrt, "0x%08X | IML/ROM data1\n",
-		iwl_read_umac_prph(trans, data1));
+		iwl_trans_read_umac_prph(trans, data1));
 
 	if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_22000)
 		IWL_ERR(fwrt, "0x%08X | IML/ROM WFPM_AUTH_KEY_0\n",
-			iwl_read_umac_prph(trans, SB_MODIFY_CFG_FLAG));
+			iwl_trans_read_umac_prph(trans, SB_MODIFY_CFG_FLAG));
 }
 
 #define FSEQ_REG(x) { .addr = (x), .str = #x, }
@@ -360,7 +360,7 @@ static void iwl_fwrt_dump_fseq_regs(struct iwl_fw_runtime *fwrt)
 
 	for (i = 0; i < ARRAY_SIZE(fseq_regs); i++)
 		IWL_ERR(fwrt, "0x%08X | %s\n",
-			iwl_read_prph_no_grab(trans, fseq_regs[i].addr),
+			iwl_trans_read_prph_no_grab(trans, fseq_regs[i].addr),
 			fseq_regs[i].str);
 
 	iwl_trans_release_nic_access(trans);
@@ -398,13 +398,13 @@ void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime *fwrt)
 		     count++, pc_data++)
 			IWL_ERR(fwrt, "%s: 0x%x\n",
 				pc_data->pc_name,
-				iwl_read_prph_no_grab(fwrt->trans,
-						      pc_data->pc_address));
+				iwl_trans_read_prph_no_grab(fwrt->trans,
+							    pc_data->pc_address));
 		iwl_trans_release_nic_access(fwrt->trans);
 	}
 
 	if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
-		u32 scratch = iwl_read32(fwrt->trans, CSR_FUNC_SCRATCH);
+		u32 scratch = iwl_trans_read32(fwrt->trans, CSR_FUNC_SCRATCH);
 
 		IWL_ERR(fwrt, "Function Scratch status:\n");
 		IWL_ERR(fwrt, "0x%08X | Func Scratch\n", scratch);
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c
index 545a213df71d2..ccd190ab8a552 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c
@@ -6,7 +6,7 @@
 #include "iwl-drv.h"
 #include "pnvm.h"
 #include "iwl-prph.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "fw/api/commands.h"
 #include "fw/api/nvm-reg.h"
 #include "fw/api/alive.h"
@@ -485,8 +485,8 @@ int iwl_pnvm_load(struct iwl_trans *trans,
 				   iwl_pnvm_complete_fn, trans);
 
 	/* kick the doorbell */
-	iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
-			    UREG_DOORBELL_TO_ISR6_PNVM);
+	iwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
+				  UREG_DOORBELL_TO_ISR6_PNVM);
 
 	return iwl_wait_notification(notif_wait, &pnvm_wait,
 				     MVM_UCODE_PNVM_TIMEOUT);
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c
index dffd5e68f41da..89a0f722cad94 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c
@@ -6,7 +6,7 @@
 #include "iwl-drv.h"
 #include "pnvm.h"
 #include "iwl-prph.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 
 #include "fw/uefi.h"
 #include "fw/api/alive.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h
index d2fa80a3dd040..11f2b31f6df7e 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h
@@ -14,9 +14,9 @@
  * low power states due to driver-invoked device resets
  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
  *
- * Use iwl_write32() and iwl_read32() family to access these registers;
+ * Use iwl_trans_write32() and iwl_trans_read32() family to access these registers;
  * these provide simple PCI bus access, without waking up the MAC.
- * Do not use iwl_write_direct32() family for these registers;
+ * Do not use iwl_trans_write_direct32() family for these registers;
  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
  * the CSR registers.
@@ -36,7 +36,7 @@
 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
 #define CSR_FUNC_SCRATCH        (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
 
-/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
+/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_trans_write32()! */
 #define CSR_INT_PERIODIC_REG	(CSR_BASE+0x005)
 
 /*
@@ -474,7 +474,7 @@ enum {
  * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
  * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
  *
- * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
+ * Use iwl_trans_write32()/iwl_trans_read32() family to access these registers. The MAC HW
  * need not be powered up so no "grab inc access" is required.
  */
 
@@ -501,12 +501,13 @@ enum {
  * to indirectly access device's internal memory or registers that
  * may be powered-down.
  *
- * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
+ * Use iwl_trans_write_direct32() family for writing to these registers;
+ * A read operation doesn't exist, can be added if needed.
  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
  * internal resources.
  *
- * Do not use iwl_write32()/iwl_read32() family to access these registers;
+ * Do not use iwl_trans_write32()/iwl_trans_read32() family to access these registers;
  * these provide only simple PCI bus access, without waking up the MAC.
  */
 #define HBUS_BASE	(0x400)
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
index 4372a171172b0..cc6044222b5cf 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
@@ -912,7 +912,7 @@ static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,
 			for (count = 0; count < len; count++) {
 				address = le32_to_cpu(config_list->addr_val[count].address);
 				value = le32_to_cpu(config_list->addr_val[count].value);
-				iwl_trans_write_prph(fwrt->trans, address + offset, value);
+				iwl_trans_write_prph_no_grab(fwrt->trans, address + offset, value);
 			}
 			iwl_trans_release_nic_access(fwrt->trans);
 		break;
@@ -931,7 +931,7 @@ static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,
 			for (count = 0; count < len; count++) {
 				address = le32_to_cpu(config_list->addr_val[count].address);
 				value = le32_to_cpu(config_list->addr_val[count].value);
-				iwl_write32(fwrt->trans, address + offset, value);
+				iwl_trans_write32(fwrt->trans, address + offset, value);
 				IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n",
 					     count, address, value);
 			}
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h b/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h
index 0af9d8362c5b8..a0cc401198908 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-io.h
@@ -3,6 +3,7 @@
  *
  * Copyright(c) 2009 - 2014 Intel Corporation. All rights reserved.
  * Copyright(c) 2016-2017 Intel Deutschland GmbH
+ * Copyright (C) 2026 Intel Corporation
  *****************************************************************************/
 
 #if !defined(__IWLWIFI_DEVICE_TRACE_IO) || defined(TRACE_HEADER_MULTI_READ)
@@ -65,23 +66,6 @@ TRACE_EVENT(iwlwifi_dev_iowrite32,
 		  __get_str(dev), __entry->offs, __entry->val)
 );
 
-TRACE_EVENT(iwlwifi_dev_iowrite64,
-	TP_PROTO(const struct device *dev, u64 offs, u64 val),
-	TP_ARGS(dev, offs, val),
-	TP_STRUCT__entry(
-		DEV_ENTRY
-		__field(u64, offs)
-		__field(u64, val)
-	),
-	TP_fast_assign(
-		DEV_ASSIGN;
-		__entry->offs = offs;
-		__entry->val = val;
-	),
-	TP_printk("[%s] write io[%llu] = %llu)",
-		  __get_str(dev), __entry->offs, __entry->val)
-);
-
 TRACE_EVENT(iwlwifi_dev_iowrite_prph32,
 	TP_PROTO(const struct device *dev, u32 offs, u32 val),
 	TP_ARGS(dev, offs, val),
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.c b/drivers/net/wireless/intel/iwlwifi/iwl-io.c
deleted file mode 100644
index cc6bf4ea5055d..0000000000000
--- a/drivers/net/wireless/intel/iwlwifi/iwl-io.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
-/*
- * Copyright (C) 2003-2014, 2018-2022, 2024-2026 Intel Corporation
- * Copyright (C) 2015-2016 Intel Deutschland GmbH
- */
-#include <linux/device.h>
-#include <linux/export.h>
-
-#include "iwl-drv.h"
-#include "iwl-io.h"
-#include "iwl-csr.h"
-#include "iwl-debug.h"
-
-void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val)
-{
-	trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val);
-	iwl_trans_write8(trans, ofs, val);
-}
-IWL_EXPORT_SYMBOL(iwl_write8);
-
-void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val)
-{
-	trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val);
-	iwl_trans_write32(trans, ofs, val);
-}
-IWL_EXPORT_SYMBOL(iwl_write32);
-
-void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val)
-{
-	trace_iwlwifi_dev_iowrite64(trans->dev, ofs, val);
-	iwl_trans_write32(trans, ofs, lower_32_bits(val));
-	iwl_trans_write32(trans, ofs + 4, upper_32_bits(val));
-}
-IWL_EXPORT_SYMBOL(iwl_write64);
-
-u32 iwl_read32(struct iwl_trans *trans, u32 ofs)
-{
-	u32 val = iwl_trans_read32(trans, ofs);
-
-	trace_iwlwifi_dev_ioread32(trans->dev, ofs, val);
-	return val;
-}
-IWL_EXPORT_SYMBOL(iwl_read32);
-
-#define IWL_POLL_INTERVAL 10	/* microseconds */
-
-int iwl_poll_bits_mask(struct iwl_trans *trans, u32 addr,
-		       u32 bits, u32 mask, int timeout)
-{
-	int t = 0;
-
-	do {
-		if ((iwl_read32(trans, addr) & mask) == (bits & mask))
-			return 0;
-		udelay(IWL_POLL_INTERVAL);
-		t += IWL_POLL_INTERVAL;
-	} while (t < timeout);
-
-	return -ETIMEDOUT;
-}
-IWL_EXPORT_SYMBOL(iwl_poll_bits_mask);
-
-u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
-{
-	if (iwl_trans_grab_nic_access(trans)) {
-		u32 value = iwl_read32(trans, reg);
-
-		iwl_trans_release_nic_access(trans);
-		return value;
-	}
-
-	/* return as if we have a HW timeout/failure */
-	return 0x5a5a5a5a;
-}
-
-void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
-{
-	if (iwl_trans_grab_nic_access(trans)) {
-		iwl_write32(trans, reg, value);
-		iwl_trans_release_nic_access(trans);
-	}
-}
-IWL_EXPORT_SYMBOL(iwl_write_direct32);
-
-void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)
-{
-	if (iwl_trans_grab_nic_access(trans)) {
-		iwl_write64(trans, reg, value);
-		iwl_trans_release_nic_access(trans);
-	}
-}
-
-int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
-			int timeout)
-{
-	int t = 0;
-
-	do {
-		if ((iwl_read_direct32(trans, addr) & mask) == mask)
-			return t;
-		udelay(IWL_POLL_INTERVAL);
-		t += IWL_POLL_INTERVAL;
-	} while (t < timeout);
-
-	return -ETIMEDOUT;
-}
-
-u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs)
-{
-	u32 val = iwl_trans_read_prph(trans, ofs);
-	trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val);
-	return val;
-}
-
-void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val)
-{
-	trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val);
-	iwl_trans_write_prph(trans, ofs, val);
-}
-
-void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val)
-{
-	trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val);
-	iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff);
-	iwl_write_prph_no_grab(trans, ofs + 4, val >> 32);
-}
-
-u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
-{
-	if (iwl_trans_grab_nic_access(trans)) {
-		u32 val = iwl_read_prph_no_grab(trans, ofs);
-
-		iwl_trans_release_nic_access(trans);
-
-		return val;
-	}
-
-	/* return as if we have a HW timeout/failure */
-	return 0x5a5a5a5a;
-}
-IWL_EXPORT_SYMBOL(iwl_read_prph);
-
-void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val, u32 delay_ms)
-{
-	if (iwl_trans_grab_nic_access(trans)) {
-		mdelay(delay_ms);
-		iwl_write_prph_no_grab(trans, ofs, val);
-		iwl_trans_release_nic_access(trans);
-	}
-}
-IWL_EXPORT_SYMBOL(iwl_write_prph_delay);
-
-int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
-		      u32 bits, u32 mask, int timeout)
-{
-	int t = 0;
-
-	do {
-		if ((iwl_read_prph(trans, addr) & mask) == (bits & mask))
-			return 0;
-		udelay(IWL_POLL_INTERVAL);
-		t += IWL_POLL_INTERVAL;
-	} while (t < timeout);
-
-	return -ETIMEDOUT;
-}
-
-int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
-				    u32 bits, u32 mask, int timeout)
-{
-	int t = 0;
-
-	do {
-		if ((iwl_read_umac_prph_no_grab(trans, addr) & mask) ==
-		    (bits & mask))
-			return 0;
-		udelay(IWL_POLL_INTERVAL);
-		t += IWL_POLL_INTERVAL;
-	} while (t < timeout);
-
-	return -ETIMEDOUT;
-}
-
-void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
-{
-	if (iwl_trans_grab_nic_access(trans)) {
-		iwl_write_prph_no_grab(trans, ofs,
-				       iwl_read_prph_no_grab(trans, ofs) |
-				       mask);
-		iwl_trans_release_nic_access(trans);
-	}
-}
-IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
-
-void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
-			    u32 bits, u32 mask)
-{
-	if (iwl_trans_grab_nic_access(trans)) {
-		iwl_write_prph_no_grab(trans, ofs,
-				       (iwl_read_prph_no_grab(trans, ofs) &
-					mask) | bits);
-		iwl_trans_release_nic_access(trans);
-	}
-}
-IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);
-
-void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
-{
-	u32 val;
-
-	if (iwl_trans_grab_nic_access(trans)) {
-		val = iwl_read_prph_no_grab(trans, ofs);
-		iwl_write_prph_no_grab(trans, ofs, (val & ~mask));
-		iwl_trans_release_nic_access(trans);
-	}
-}
-IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.h b/drivers/net/wireless/intel/iwlwifi/iwl-io.h
deleted file mode 100644
index e4a9f2ba0de93..0000000000000
--- a/drivers/net/wireless/intel/iwlwifi/iwl-io.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
-/*
- * Copyright (C) 2018-2021, 2025-2026 Intel Corporation
- */
-#ifndef __iwl_io_h__
-#define __iwl_io_h__
-
-#include "iwl-devtrace.h"
-#include "iwl-trans.h"
-
-void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val);
-void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val);
-void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val);
-u32 iwl_read32(struct iwl_trans *trans, u32 ofs);
-
-static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
-{
-	iwl_trans_set_bits_mask(trans, reg, mask, mask);
-}
-
-static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
-{
-	iwl_trans_set_bits_mask(trans, reg, mask, 0);
-}
-
-int iwl_poll_bits_mask(struct iwl_trans *trans, u32 addr,
-		       u32 bits, u32 mask, int timeout);
-static inline int iwl_poll_bits(struct iwl_trans *trans, u32 addr, u32 bits,
-				int timeout)
-{
-	return iwl_poll_bits_mask(trans, addr, bits, bits, timeout);
-}
-int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
-			int timeout);
-
-u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg);
-void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value);
-void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value);
-
-
-u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs);
-u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs);
-void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val);
-void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val);
-void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs,
-			  u32 val, u32 delay_ms);
-static inline void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
-{
-	iwl_write_prph_delay(trans, ofs, val, 0);
-}
-
-int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
-		      u32 bits, u32 mask, int timeout);
-int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
-				    u32 bits, u32 mask, int timeout);
-void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
-void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
-			    u32 bits, u32 mask);
-void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
-
-/*
- * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from
- * device family AX200. So peripheries used in families above and below AX200
- * should go through iwl_..._umac_..._prph.
- */
-static inline u32 iwl_umac_prph(struct iwl_trans *trans, u32 ofs)
-{
-	return ofs + trans->mac_cfg->umac_prph_offset;
-}
-
-static inline u32 iwl_read_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs)
-{
-	return iwl_read_prph_no_grab(trans, ofs +
-				     trans->mac_cfg->umac_prph_offset);
-}
-
-static inline u32 iwl_read_umac_prph(struct iwl_trans *trans, u32 ofs)
-{
-	return iwl_read_prph(trans, ofs + trans->mac_cfg->umac_prph_offset);
-}
-
-static inline void iwl_write_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs,
-					       u32 val)
-{
-	iwl_write_prph_no_grab(trans,  ofs + trans->mac_cfg->umac_prph_offset,
-			       val);
-}
-
-static inline void iwl_write_umac_prph(struct iwl_trans *trans, u32 ofs,
-				       u32 val)
-{
-	iwl_write_prph(trans,  ofs + trans->mac_cfg->umac_prph_offset, val);
-}
-
-static inline int iwl_poll_umac_prph_bit(struct iwl_trans *trans, u32 addr,
-					 u32 bits, u32 mask, int timeout)
-{
-	return iwl_poll_prph_bit(trans, addr +
-				 trans->mac_cfg->umac_prph_offset,
-				 bits, mask, timeout);
-}
-
-#endif
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
index 413dd55115f8f..ed2b094c1ad78 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
@@ -16,7 +16,7 @@
 #include "iwl-modparams.h"
 #include "iwl-nvm-parse.h"
 #include "iwl-prph.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-csr.h"
 #include "fw/api/nvm-reg.h"
 #include "fw/api/commands.h"
@@ -1312,10 +1312,10 @@ static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
 					struct iwl_nvm_data *data)
 {
-	__le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,
-						  CSR_MAC_ADDR0_STRAP(trans)));
-	__le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,
-						  CSR_MAC_ADDR1_STRAP(trans)));
+	__le32 mac_addr0 = cpu_to_le32(iwl_trans_read32(trans,
+							CSR_MAC_ADDR0_STRAP(trans)));
+	__le32 mac_addr1 = cpu_to_le32(iwl_trans_read32(trans,
+							CSR_MAC_ADDR1_STRAP(trans)));
 
 	iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 	/*
@@ -1325,8 +1325,8 @@ static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
 	if (is_valid_ether_addr(data->hw_addr))
 		return;
 
-	mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));
-	mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));
+	mac_addr0 = cpu_to_le32(iwl_trans_read32(trans, CSR_MAC_ADDR0_OTP(trans)));
+	mac_addr1 = cpu_to_le32(iwl_trans_read32(trans, CSR_MAC_ADDR1_OTP(trans)));
 
 	iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 }
@@ -1367,10 +1367,10 @@ static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
 
 	if (nvm_hw) {
 		/* read the mac address from WFMP registers */
-		__le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
-						WFMP_MAC_ADDR_0));
-		__le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
-						WFMP_MAC_ADDR_1));
+		__le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph_no_grab(trans,
+									   WFMP_MAC_ADDR_0));
+		__le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph_no_grab(trans,
+									   WFMP_MAC_ADDR_1));
 
 		iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
 
@@ -1410,7 +1410,7 @@ static int iwl_set_hw_address(struct iwl_trans *trans,
 
 	if (!trans->csme_own)
 		IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n",
-			 data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR));
+			 data->hw_addr, iwl_trans_read_prph(trans, REG_OTP_MINOR));
 
 	return 0;
 }
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-scd.h b/drivers/net/wireless/intel/iwlwifi/iwl-scd.h
index 1eaff898ca3ca..f13568d3094bf 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-scd.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-scd.h
@@ -1,52 +1,52 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
  * Copyright (C) 2014 Intel Mobile Communications GmbH
+ * Copyright (C) 2026 Intel Corporation
  */
 #ifndef __iwl_scd_h__
 #define __iwl_scd_h__
 
 #include "iwl-trans.h"
-#include "iwl-io.h"
 #include "iwl-prph.h"
 
 
 static inline void iwl_scd_txq_set_chain(struct iwl_trans *trans,
 					 u16 txq_id)
 {
-	iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
+	iwl_trans_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
 }
 
 static inline void iwl_scd_txq_enable_agg(struct iwl_trans *trans,
 					  u16 txq_id)
 {
-	iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
+	iwl_trans_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
 }
 
 static inline void iwl_scd_txq_disable_agg(struct iwl_trans *trans,
 					   u16 txq_id)
 {
-	iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
+	iwl_trans_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
 }
 
 static inline void iwl_scd_disable_agg(struct iwl_trans *trans)
 {
-	iwl_set_bits_prph(trans, SCD_AGGR_SEL, 0);
+	iwl_trans_set_bits_prph(trans, SCD_AGGR_SEL, 0);
 }
 
 static inline void iwl_scd_activate_fifos(struct iwl_trans *trans)
 {
-	iwl_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7));
+	iwl_trans_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7));
 }
 
 static inline void iwl_scd_deactivate_fifos(struct iwl_trans *trans)
 {
-	iwl_write_prph(trans, SCD_TXFACT, 0);
+	iwl_trans_write_prph(trans, SCD_TXFACT, 0);
 }
 
 static inline void iwl_scd_enable_set_active(struct iwl_trans *trans,
 					     u32 value)
 {
-	iwl_write_prph(trans, SCD_EN_CTRL, value);
+	iwl_trans_write_prph(trans, SCD_EN_CTRL, value);
 }
 
 static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
@@ -76,9 +76,9 @@ static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
 static inline void iwl_scd_txq_set_inactive(struct iwl_trans *trans,
 					    u16 txq_id)
 {
-	iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
-		       (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
-		       (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
+	iwl_trans_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
+			     (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
+			     (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 }
 
 #endif
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.c b/drivers/net/wireless/intel/iwlwifi/iwl-trans.c
index 0a6b7b264aa23..6e068f19af7fb 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.c
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.c
@@ -6,6 +6,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/bsearch.h>
+#include <linux/delay.h>
 #include <linux/list.h>
 
 #include "iwl-trans.h"
@@ -260,13 +261,14 @@ static void iwl_trans_restart_wk(struct work_struct *wk)
 		iwl_trans_schedule_reprobe(trans, 0);
 		break;
 	default:
-		iwl_trans_pcie_reset(trans, mode);
+		iwl_trans_reset(trans, mode);
 		break;
 	}
 }
 
 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
 				  struct device *dev,
+				  const struct iwl_trans_ops *ops,
 				  const struct iwl_mac_cfg *mac_cfg)
 {
 	struct iwl_trans *trans;
@@ -278,6 +280,7 @@ struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
 	if (!trans)
 		return NULL;
 
+	trans->ops = ops;
 	trans->mac_cfg = mac_cfg;
 
 #ifdef CONFIG_LOCKDEP
@@ -428,45 +431,130 @@ void iwl_trans_op_mode_leave(struct iwl_trans *trans)
 }
 IWL_EXPORT_SYMBOL(iwl_trans_op_mode_leave);
 
-void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
-{
-	iwl_trans_pcie_write8(trans, ofs, val);
-}
-
 void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 {
 	iwl_trans_pcie_write32(trans, ofs, val);
 }
+IWL_EXPORT_SYMBOL(iwl_trans_write32);
 
 u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
 {
 	return iwl_trans_pcie_read32(trans, ofs);
 }
+IWL_EXPORT_SYMBOL(iwl_trans_read32);
 
-u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
+u32 iwl_trans_read_prph_no_grab(struct iwl_trans *trans, u32 ofs)
 {
 	return iwl_trans_pcie_read_prph(trans, ofs);
 }
 
-void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
+void iwl_trans_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val)
+{
+	return iwl_pcie_write_prph_no_grab(trans, ofs, val);
+}
+
+#define IWL_POLL_INTERVAL 10	/* microseconds */
+
+int iwl_trans_poll_bits_mask(struct iwl_trans *trans, u32 addr,
+			     u32 bits, u32 mask, int timeout)
+{
+	int t = 0;
+
+	do {
+		if ((iwl_trans_read32(trans, addr) & mask) == (bits & mask))
+			return 0;
+		udelay(IWL_POLL_INTERVAL);
+		t += IWL_POLL_INTERVAL;
+	} while (t < timeout);
+
+	return -ETIMEDOUT;
+}
+IWL_EXPORT_SYMBOL(iwl_trans_poll_bits_mask);
+
+void iwl_trans_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
+{
+	if (iwl_trans_grab_nic_access(trans)) {
+		iwl_trans_write32(trans, reg, value);
+		iwl_trans_release_nic_access(trans);
+	}
+}
+IWL_EXPORT_SYMBOL(iwl_trans_write_direct32);
+
+u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
+{
+	if (iwl_trans_grab_nic_access(trans)) {
+		u32 val = iwl_trans_read_prph_no_grab(trans, ofs);
+
+		iwl_trans_release_nic_access(trans);
+
+		return val;
+	}
+
+	/* return as if we have a HW timeout/failure */
+	return 0x5a5a5a5a;
+}
+IWL_EXPORT_SYMBOL(iwl_trans_read_prph);
+
+void iwl_trans_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val,
+				u32 delay_ms)
 {
-	return iwl_trans_pcie_write_prph(trans, ofs, val);
+	if (iwl_trans_grab_nic_access(trans)) {
+		mdelay(delay_ms);
+		iwl_trans_write_prph_no_grab(trans, ofs, val);
+		iwl_trans_release_nic_access(trans);
+	}
+}
+IWL_EXPORT_SYMBOL(iwl_trans_write_prph_delay);
+
+void iwl_trans_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
+{
+	if (iwl_trans_grab_nic_access(trans)) {
+		iwl_trans_write_prph_no_grab(trans, ofs,
+					     iwl_trans_read_prph_no_grab(trans, ofs) |
+					     mask);
+		iwl_trans_release_nic_access(trans);
+	}
+}
+IWL_EXPORT_SYMBOL(iwl_trans_set_bits_prph);
+
+void iwl_trans_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
+				  u32 bits, u32 mask)
+{
+	if (iwl_trans_grab_nic_access(trans)) {
+		iwl_trans_write_prph_no_grab(trans, ofs,
+					     (iwl_trans_read_prph_no_grab(trans, ofs) &
+					      mask) | bits);
+		iwl_trans_release_nic_access(trans);
+	}
 }
+IWL_EXPORT_SYMBOL(iwl_trans_set_bits_mask_prph);
+
+void iwl_trans_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
+{
+	u32 val;
+
+	if (iwl_trans_grab_nic_access(trans)) {
+		val = iwl_trans_read_prph_no_grab(trans, ofs);
+		iwl_trans_write_prph_no_grab(trans, ofs, (val & ~mask));
+		iwl_trans_release_nic_access(trans);
+	}
+}
+IWL_EXPORT_SYMBOL(iwl_trans_clear_bits_prph);
 
 void iwl_trans_force_nmi(struct iwl_trans *trans)
 {
 	if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_9000)
-		iwl_write_prph_delay(trans, DEVICE_SET_NMI_REG,
-				     DEVICE_SET_NMI_VAL_DRV, 1);
+		iwl_trans_write_prph_delay(trans, DEVICE_SET_NMI_REG,
+					   DEVICE_SET_NMI_VAL_DRV, 1);
 	else if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
-		iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
-				    UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);
+		iwl_trans_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
+					  UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);
 	else if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ)
-		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
-				    UREG_DOORBELL_TO_ISR6_NMI_BIT);
+		iwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
+					  UREG_DOORBELL_TO_ISR6_NMI_BIT);
 	else
-		iwl_write32(trans, CSR_DOORBELL_VECTOR,
-			    UREG_DOORBELL_TO_ISR6_NMI_BIT);
+		iwl_trans_write32(trans, CSR_DOORBELL_VECTOR,
+				  UREG_DOORBELL_TO_ISR6_NMI_BIT);
 }
 IWL_EXPORT_SYMBOL(iwl_trans_force_nmi);
 
@@ -490,10 +578,10 @@ int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
 	const u32 *vals = buf;
 
 	if (iwl_trans_grab_nic_access(trans)) {
-		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
+		iwl_trans_write32(trans, HBUS_TARG_MEM_WADDR, addr);
 		for (offs = 0; offs < dwords; offs++)
-			iwl_write32(trans, HBUS_TARG_MEM_WDAT,
-				    vals ? vals[offs] : 0);
+			iwl_trans_write32(trans, HBUS_TARG_MEM_WDAT,
+					  vals ? vals[offs] : 0);
 		iwl_trans_release_nic_access(trans);
 	} else {
 		ret = -EBUSY;
@@ -843,3 +931,17 @@ int iwl_trans_activate_nic(struct iwl_trans *trans)
 }
 IWL_EXPORT_SYMBOL(iwl_trans_activate_nic);
 
+
+void iwl_trans_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)
+{
+	if (!WARN_ON_ONCE(!trans->ops->reset))
+		trans->ops->reset(trans, mode);
+}
+IWL_EXPORT_SYMBOL(iwl_trans_reset);
+
+void iwl_trans_fw_reset_handshake(struct iwl_trans *trans)
+{
+	if (!WARN_ON_ONCE(!trans->ops->fw_reset_handshake))
+		trans->ops->fw_reset_handshake(trans);
+}
+
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h
index 56c5e61b614ad..90100f16ddd52 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h
@@ -734,12 +734,15 @@ struct iwl_trans_info {
 	u8 num_rxqs;
 };
 
+struct iwl_trans_ops;
+
 /**
  * struct iwl_trans - transport common data
  *
  * @csme_own: true if we couldn't get ownership on the device
  * @op_mode: pointer to the op_mode
  * @mac_cfg: the trans-specific configuration part
+ * @ops: bus-specific transport operations, see &struct iwl_trans_ops
  * @cfg: pointer to the configuration
  * @drv: pointer to iwl_drv
  * @conf: configuration set by the opmode before enter
@@ -773,6 +776,7 @@ struct iwl_trans {
 	bool csme_own;
 	struct iwl_op_mode *op_mode;
 	const struct iwl_mac_cfg *mac_cfg;
+	const struct iwl_trans_ops *ops;
 	const struct iwl_rf_cfg *cfg;
 	struct iwl_drv *drv;
 	struct iwl_trans_config conf;
@@ -910,15 +914,13 @@ int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, u32 txqs);
 
 int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue);
 
-void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val);
-
 void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val);
 
 u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs);
 
-u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs);
+u32 iwl_trans_read_prph_no_grab(struct iwl_trans *trans, u32 ofs);
 
-void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val);
+void iwl_trans_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val);
 
 int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
 		       void *buf, int dwords);
@@ -979,6 +981,66 @@ int iwl_trans_sw_reset(struct iwl_trans *trans);
 void iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg,
 			     u32 mask, u32 value);
 
+static inline void iwl_trans_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
+{
+	iwl_trans_set_bits_mask(trans, reg, mask, mask);
+}
+
+static inline void iwl_trans_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
+{
+	iwl_trans_set_bits_mask(trans, reg, mask, 0);
+}
+
+int iwl_trans_poll_bits_mask(struct iwl_trans *trans, u32 addr,
+			     u32 bits, u32 mask, int timeout);
+static inline int iwl_trans_poll_bits(struct iwl_trans *trans, u32 addr, u32 bits,
+				      int timeout)
+{
+	return iwl_trans_poll_bits_mask(trans, addr, bits, bits, timeout);
+}
+
+void iwl_trans_write_direct32(struct iwl_trans *trans, u32 reg, u32 value);
+
+u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs);
+void iwl_trans_write_prph_delay(struct iwl_trans *trans, u32 ofs,
+				u32 val, u32 delay_ms);
+static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
+{
+	iwl_trans_write_prph_delay(trans, ofs, val, 0);
+}
+
+void iwl_trans_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
+void iwl_trans_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
+				  u32 bits, u32 mask);
+void iwl_trans_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
+
+/*
+ * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from
+ * device family AX200. So peripheries used in families above and below AX200
+ * should go through iwl_trans_..._umac_..._prph.
+ */
+static inline u32 iwl_trans_umac_prph(struct iwl_trans *trans, u32 ofs)
+{
+	return ofs + trans->mac_cfg->umac_prph_offset;
+}
+
+static inline u32 iwl_trans_read_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs)
+{
+	return iwl_trans_read_prph_no_grab(trans, ofs +
+					   trans->mac_cfg->umac_prph_offset);
+}
+
+static inline u32 iwl_trans_read_umac_prph(struct iwl_trans *trans, u32 ofs)
+{
+	return iwl_trans_read_prph(trans, ofs + trans->mac_cfg->umac_prph_offset);
+}
+
+static inline void iwl_trans_write_umac_prph(struct iwl_trans *trans, u32 ofs,
+					     u32 val)
+{
+	iwl_trans_write_prph(trans, ofs + trans->mac_cfg->umac_prph_offset, val);
+}
+
 bool iwl_trans_grab_nic_access(struct iwl_trans *trans);
 
 /**
@@ -1088,6 +1150,7 @@ static inline void iwl_trans_finish_sw_reset(struct iwl_trans *trans)
  *****************************************************/
 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
 				  struct device *dev,
+				  const struct iwl_trans_ops *ops,
 				  const struct iwl_mac_cfg *mac_cfg);
 void iwl_trans_free(struct iwl_trans *trans);
 
@@ -1158,8 +1221,148 @@ enum iwl_reset_mode {
 	IWL_RESET_MODE_BACKOFF,
 };
 
-void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode);
-void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans);
+void iwl_trans_reset(struct iwl_trans *trans, enum iwl_reset_mode mode);
+void iwl_trans_fw_reset_handshake(struct iwl_trans *trans);
+
+/**
+ * struct iwl_trans_ops - bus-specific transport operations
+ *
+ * Function-pointer table filled in by the bus implementation. Unless noted
+ * otherwise, each callback implements the identically named iwl_trans_*()
+ * API, see its documentation.
+ *
+ * @op_mode_enter: the op_mode took ownership of the transport
+ * @start_hw: start the hardware
+ * @op_mode_leave: the op_mode released the transport
+ * @send_cmd: send a host command to the firmware
+ * @alloc_tx_cmd: allocate a device TX command
+ * @free_tx_cmd: free a device TX command
+ * @write8: write a byte to a device register
+ * @write32: write a dword to a device register
+ * @read32: read a dword from a device register
+ * @read_prph: read a peripheral register
+ * @write_prph: write a peripheral register
+ * @read_mem: read device memory, taking NIC access
+ * @read_mem_no_grab: read device memory, NIC access already taken
+ * @set_bits_mask: read-modify-write a device register
+ * @read_config32: read a dword from the bus configuration space
+ * @grab_nic_access: keep the NIC awake for register access
+ * @release_nic_access: release the NIC access taken by @grab_nic_access
+ * @resched_with_nic_access: reschedule while holding NIC access
+ * @sw_reset: perform a software reset of the device
+ * @reset: reset the device, see &enum iwl_reset_mode
+ * @fw_reset_handshake: do a firmware reset handshake.
+ * @dump_data: collect a firmware error dump
+ * @d3_suspend: prepare the device for D3 (WoWLAN)
+ * @d3_resume: resume the device from D3 (WoWLAN)
+ * @sync_nmi: trigger an NMI and wait for it to be handled
+ * @write_imr_mem: write to the IMR memory region
+ * @fw_alive: Notify trans that the firmware sent the ALIVE notification
+ * @start_fw: download firmware code to the device and and start the firmware
+ * @stop_device: stop the device and the firmware
+ * @tx: transmit an MPDU
+ * @reclaim: free TX MPDUs up to the given sequence number
+ * @txq_disable: disable a TX queue (gen1)
+ * @txq_enable: enable a TX queue (gen1)
+ * @wait_txq_empty: wait for a single TX queue to become empty
+ * @wait_txqs_empty: wait for the given TX queues to become empty
+ * @freeze_txq_timer: freeze/unfreeze the watchdog of the given TX queues
+ * @txq_set_shared_mode: mark a TX queue as shared between TIDs
+ * @set_q_ptrs: set the write pointer of a TX queue
+ * @txq_alloc: allocate a TX queue (gen2)
+ * @txq_free: free a TX queue allocated by @txq_alloc
+ * @rxq_dma_data: get the DMA addresses of an RX queue
+ * @load_pnvm: load the PNVM image
+ * @set_pnvm: tell the firmware to use the loaded PNVM
+ * @load_reduce_power: load the reduced power table
+ * @set_reduce_power: tell the firmware to use the reduced power table
+ * @is_pm_supported: whether bus power management is supported
+ * @is_ltr_enabled: whether LTR is enabled on the bus
+ * @activate_nic: bring the NIC out of low power and make it accessible
+ */
+struct iwl_trans_ops {
+	void (*op_mode_enter)(struct iwl_trans *trans);
+	int (*start_hw)(struct iwl_trans *trans);
+	void (*op_mode_leave)(struct iwl_trans *trans);
+
+	int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
+	struct iwl_device_tx_cmd *(*alloc_tx_cmd)(struct iwl_trans *trans);
+	void (*free_tx_cmd)(struct iwl_trans *trans,
+			    struct iwl_device_tx_cmd *dev_cmd);
+
+	void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
+	void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
+	u32 (*read32)(struct iwl_trans *trans, u32 ofs);
+	u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
+	void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
+	int (*read_mem)(struct iwl_trans *trans, u32 addr,
+			void *buf, int dwords);
+	int (*read_mem_no_grab)(struct iwl_trans *trans, u32 addr,
+				void *buf, u32 dwords);
+	void (*set_bits_mask)(struct iwl_trans *trans, u32 reg,
+			      u32 mask, u32 value);
+	int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val);
+	bool (*grab_nic_access)(struct iwl_trans *trans);
+	void (*release_nic_access)(struct iwl_trans *trans);
+	void (*resched_with_nic_access)(struct iwl_trans *trans);
+
+	int (*sw_reset)(struct iwl_trans *trans, bool retake_ownership);
+	void (*reset)(struct iwl_trans *trans, enum iwl_reset_mode mode);
+	void (*fw_reset_handshake)(struct iwl_trans *trans);
+
+	struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
+						 u32 dump_mask,
+						 const struct iwl_dump_sanitize_ops *sanitize_ops,
+						 void *sanitize_ctx);
+	int (*d3_suspend)(struct iwl_trans *trans, bool reset);
+	int (*d3_resume)(struct iwl_trans *trans, bool reset);
+
+	void (*sync_nmi)(struct iwl_trans *trans);
+	int (*write_imr_mem)(struct iwl_trans *trans, u32 dst_addr,
+			     u64 src_addr, u32 byte_cnt);
+
+	void (*fw_alive)(struct iwl_trans *trans);
+	int (*start_fw)(struct iwl_trans *trans, const struct iwl_fw *fw,
+			const struct fw_img *img, bool run_in_rfkill);
+	void (*stop_device)(struct iwl_trans *trans);
+
+	int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
+		  struct iwl_device_tx_cmd *dev_cmd, int queue);
+	void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
+			struct sk_buff_head *skbs, bool is_flush);
+	void (*txq_disable)(struct iwl_trans *trans, int queue,
+			    bool configure_scd);
+	bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
+			   const struct iwl_trans_txq_scd_cfg *cfg,
+			   unsigned int queue_wdg_timeout);
+	int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
+	int (*wait_txqs_empty)(struct iwl_trans *trans, u32 txqs);
+	void (*freeze_txq_timer)(struct iwl_trans *trans,
+				 unsigned long txqs, bool freeze);
+	void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
+				    bool shared_mode);
+	void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr);
+	int (*txq_alloc)(struct iwl_trans *trans, u32 flags, u32 sta_mask,
+			 u8 tid, int size, unsigned int wdg_timeout);
+	void (*txq_free)(struct iwl_trans *trans, int queue);
+	int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
+			    struct iwl_trans_rxq_dma_data *data);
+
+	int (*load_pnvm)(struct iwl_trans *trans,
+			 const struct iwl_pnvm_image *pnvm_data,
+			 const struct iwl_ucode_capabilities *capa);
+	void (*set_pnvm)(struct iwl_trans *trans,
+			 const struct iwl_ucode_capabilities *capa);
+	int (*load_reduce_power)(struct iwl_trans *trans,
+				 const struct iwl_pnvm_image *payloads,
+				 const struct iwl_ucode_capabilities *capa);
+	void (*set_reduce_power)(struct iwl_trans *trans,
+				 const struct iwl_ucode_capabilities *capa);
+
+	bool (*is_pm_supported)(struct iwl_trans *trans);
+	bool (*is_ltr_enabled)(struct iwl_trans *trans);
+	int (*activate_nic)(struct iwl_trans *trans);
+};
 
 /* Internal helper */
 static inline void iwl_trans_set_info(struct iwl_trans *trans,
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/constants.h b/drivers/net/wireless/intel/iwlwifi/mld/constants.h
index 890abcab38374..bfd5398510ee3 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/constants.h
+++ b/drivers/net/wireless/intel/iwlwifi/mld/constants.h
@@ -39,6 +39,10 @@
 
 #define IWL_MLD_TPT_COUNT_WINDOW (5 * HZ)
 
+#define IWL_MLD_TX_GP2_VALID_PERIOD	(10 * HZ)
+#define IWL_MLD_TX_GP2_REFRESH_MARGIN	(5 * HZ)
+#define IWL_MLD_TX_GP2_RETRY_PERIOD	HZ
+
 #define IWL_MLD_DIS_RANDOM_FW_ID                false
 #define IWL_MLD_D3_DEBUG                        false
 #define IWL_MLD_NON_TRANSMITTING_AP	        false
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/d3.c b/drivers/net/wireless/intel/iwlwifi/mld/d3.c
index 6d8ede336d59b..7a7d07a7914dd 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/d3.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/d3.c
@@ -5,6 +5,7 @@
 #include "mld.h"
 
 #include "d3.h"
+#include "tx.h"
 #include "power.h"
 #include "hcmd.h"
 #include "iface.h"
@@ -1610,6 +1611,8 @@ int iwl_mld_no_wowlan_suspend(struct iwl_mld *mld)
 
 	iwl_mld_low_latency_stop(mld);
 
+	iwl_mld_tx_gp2_stop(mld);
+
 	ret = iwl_mld_update_device_power(mld, true);
 	if (ret) {
 		IWL_ERR(mld,
@@ -1663,6 +1666,8 @@ int iwl_mld_no_wowlan_resume(struct iwl_mld *mld)
 
 	iwl_mld_low_latency_restart(mld);
 
+	iwl_mld_tx_gp2_start(mld);
+
 	return iwl_mld_update_device_power(mld, false);
 }
 
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c
index dd4bf7cb6a791..b8793b71494d8 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/debugfs.c
@@ -5,7 +5,7 @@
 
 #include "mld.h"
 #include "debugfs.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "hcmd.h"
 #include "iface.h"
 #include "sta.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c
index a4b8037b5c765..a6a4f9672e4f9 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/ftm-initiator.c
@@ -8,7 +8,7 @@
 #include "mld.h"
 #include "iface.h"
 #include "phy.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "constants.h"
 #include "fw/api/location.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/fw.c b/drivers/net/wireless/intel/iwlwifi/mld/fw.c
index e5866d89176d1..3b9f412cdff2b 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/fw.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/fw.c
@@ -1,9 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2024-2025 Intel Corporation
+ * Copyright (C) 2024-2026 Intel Corporation
  */
 
 #include "mld.h"
+#include "tx.h"
 
 #include "fw/api/alive.h"
 #include "fw/api/scan.h"
@@ -206,11 +207,11 @@ static void iwl_mld_print_alive_notif_timeout(struct iwl_mld *mld)
 
 	IWL_ERR(mld,
 		"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
-		iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
-		iwl_read_umac_prph(trans,
-				   UMAG_SB_CPU_2_STATUS));
+		iwl_trans_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
+		iwl_trans_read_umac_prph(trans,
+					 UMAG_SB_CPU_2_STATUS));
 #define IWL_FW_PRINT_REG_INFO(reg_name) \
-	IWL_ERR(mld, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))
+	IWL_ERR(mld, #reg_name ": 0x%x\n", iwl_trans_read_umac_prph(trans, reg_name))
 
 	IWL_FW_PRINT_REG_INFO(WFPM_LMAC1_PD_NOTIFICATION);
 
@@ -355,6 +356,8 @@ void iwl_mld_stop_fw(struct iwl_mld *mld)
 {
 	lockdep_assert_wiphy(mld->wiphy);
 
+	iwl_mld_tx_gp2_stop(mld);
+
 	iwl_abort_notification_waits(&mld->notif_wait);
 
 	iwl_fw_dbg_stop_sync(&mld->fwrt);
@@ -542,6 +545,8 @@ int iwl_mld_start_fw(struct iwl_mld *mld)
 	if (ret)
 		goto error;
 
+	iwl_mld_tx_gp2_start(mld);
+
 	return 0;
 
 error:
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c
index 0b121114d47ca..e05bdbd3e1a9a 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/mac80211.c
@@ -2168,6 +2168,8 @@ static int iwl_mld_resume(struct ieee80211_hw *hw)
 
 	iwl_mld_low_latency_restart(mld);
 
+	iwl_mld_tx_gp2_start(mld);
+
 	return 0;
 }
 #endif
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/mld.c b/drivers/net/wireless/intel/iwlwifi/mld/mld.c
index b7b1e3686336c..71832d92024d0 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/mld.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/mld.c
@@ -35,6 +35,17 @@ MODULE_IMPORT_NS("IWLWIFI");
 
 static const struct iwl_op_mode_ops iwl_mld_ops;
 
+int iwl_mld_get_systime(struct iwl_mld *mld, u32 *gp2)
+{
+	*gp2 = iwl_trans_read_prph(mld->trans,
+			     mld->trans->mac_cfg->base->gp2_reg_addr);
+
+	if (*gp2 == 0x5a5a5a5a)
+		return -EINVAL;
+
+	return 0;
+}
+
 static int __init iwl_mld_init(void)
 {
 	int ret = iwl_opmode_register("iwlmld", &iwl_mld_ops);
@@ -425,6 +436,8 @@ iwl_op_mode_mld_start(struct iwl_trans *trans, const struct iwl_rf_cfg *cfg,
 	/* Configure transport layer with the opmode specific params */
 	iwl_mld_configure_trans(op_mode);
 
+	iwl_mld_tx_gp2_init(mld);
+
 	/* needed for regulatory init */
 	rtnl_lock();
 	/* Needed for sending commands */
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/mld.h b/drivers/net/wireless/intel/iwlwifi/mld/mld.h
index 37f41b504b54c..a9e65b216fd39 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/mld.h
+++ b/drivers/net/wireless/intel/iwlwifi/mld/mld.h
@@ -29,6 +29,7 @@
 #include "notif.h"
 #include "scan.h"
 #include "rx.h"
+#include "tx.h"
 #include "thermal.h"
 #include "low_latency.h"
 #include "constants.h"
@@ -196,6 +197,7 @@
  *	being IBSS manager for that time and needing to respond to probe
  *	requests
  * @ptp_data: data of the PTP clock
+ * @tx_gp2: gp2 timestamping state for TX commands
  * @time_sync: time sync data.
  * @ftm_initiator: FTM initiator data
  * @nan_device_vif: points to the NAN device vif if exists
@@ -306,6 +308,8 @@ struct iwl_mld {
 
 	struct ptp_data ptp_data;
 
+	struct iwl_mld_tx_gp2 tx_gp2;
+
 	struct iwl_mld_time_sync_data __rcu *time_sync;
 
 	struct ftm_initiator_data ftm_initiator;
@@ -572,6 +576,8 @@ iwl_mld_fw_id_to_link_conf(struct iwl_mld *mld, u8 fw_link_id)
 
 #define MSEC_TO_TU(_msec)	((_msec) * 1000 / 1024)
 
+int iwl_mld_get_systime(struct iwl_mld *mld, u32 *gp2);
+
 void iwl_mld_add_vif_debugfs(struct ieee80211_hw *hw,
 			     struct ieee80211_vif *vif);
 void iwl_mld_add_link_debugfs(struct ieee80211_hw *hw,
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c
index 1ac85d6ce1d79..9f7d17dbdee16 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2025 Intel Corporation
+ * Copyright (C) 2025 - 2026 Intel Corporation
  */
 
 #include "mld.h"
@@ -19,16 +19,6 @@
 #define IWL_PTP_WRAP_TIME	(3600 * HZ)
 #define IWL_PTP_WRAP_THRESHOLD_USEC	(5000)
 
-static int iwl_mld_get_systime(struct iwl_mld *mld, u32 *gp2)
-{
-	*gp2 = iwl_read_prph(mld->trans, mld->trans->mac_cfg->base->gp2_reg_addr);
-
-	if (*gp2 == 0x5a5a5a5a)
-		return -EINVAL;
-
-	return 0;
-}
-
 static void iwl_mld_ptp_update_new_read(struct iwl_mld *mld, u32 gp2)
 {
 	IWL_DEBUG_PTP(mld, "PTP: last_gp2=%u, new gp2 read=%u\n",
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/rx.c b/drivers/net/wireless/intel/iwlwifi/mld/rx.c
index 5f18aa551af52..8fa438fd78153 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/rx.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/rx.c
@@ -553,7 +553,10 @@ iwl_mld_decode_he_tb_phy_data(struct iwl_mld_rx_phy_data *phy_data,
 
 	nsts = le32_get_bits(phy_data->ntfy->sigs.he_tb.tb_rx1,
 			     OFDM_UCODE_TRIG_BASE_RX_NSTS) + 1;
-	rx_status->nss = nsts >> !!(rate_n_flags & RATE_MCS_STBC_MSK);
+
+	rx_status->nss = nsts;
+	if (rate_n_flags & RATE_MCS_STBC_MSK)
+		rx_status->nss = 1;
 }
 
 static void
@@ -589,7 +592,9 @@ iwl_mld_decode_he_phy_data(struct iwl_mld_rx_phy_data *phy_data,
 		break;
 	}
 
-	rx_status->nss = nsts >> !!(rate_n_flags & RATE_MCS_STBC_MSK);
+	rx_status->nss = nsts;
+	if (rate_n_flags & RATE_MCS_STBC_MSK)
+		rx_status->nss = 1;
 
 	he->data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |
 				 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN);
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/scan.c b/drivers/net/wireless/intel/iwlwifi/mld/scan.c
index e44b24904c19a..b942ac1e7ccca 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/scan.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/scan.c
@@ -2273,6 +2273,7 @@ void iwl_mld_handle_channel_survey_notif(struct iwl_mld *mld,
 	/* Times are all in ms */
 	info->time = le32_to_cpu(notif->active_time);
 	info->time_busy = le32_to_cpu(notif->busy_time);
+	info->time_rx = le32_to_cpu(notif->rx_time);
 	info->noise =
 		iwl_average_neg_dbm(notif->noise, ARRAY_SIZE(notif->noise));
 }
@@ -2321,9 +2322,11 @@ int iwl_mld_mac80211_get_survey(struct ieee80211_hw *hw, int idx,
 			/* Found (the next) channel to report */
 			survey->channel = &sband->channels[per_band_idx];
 			survey->filled = SURVEY_INFO_TIME |
-					 SURVEY_INFO_TIME_BUSY;
+					 SURVEY_INFO_TIME_BUSY |
+					 SURVEY_INFO_TIME_RX;
 			survey->time = info->time;
 			survey->time_busy = info->time_busy;
+			survey->time_rx = info->time_rx;
 			survey->noise = info->noise;
 			if (survey->noise < 0)
 				survey->filled |= SURVEY_INFO_NOISE_DBM;
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/scan.h b/drivers/net/wireless/intel/iwlwifi/mld/scan.h
index dc299fe2f999c..74ebe8296693f 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/scan.h
+++ b/drivers/net/wireless/intel/iwlwifi/mld/scan.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2024-2025 Intel Corporation
+ * Copyright (C) 2024-2026 Intel Corporation
  */
 #ifndef __iwl_mld_scan_h__
 #define __iwl_mld_scan_h__
@@ -151,11 +151,13 @@ struct iwl_mld_scan {
  *
  * @time: time in ms the radio was on the channel
  * @time_busy: time in ms the channel was sensed busy
+ * @time_rx: time in ms the channel was sensed to carry Wi-Fi frames
  * @noise: channel noise in dBm
  */
 struct iwl_mld_survey_channel {
 	u32 time;
 	u32 time_busy;
+	u32 time_rx;
 	s8 noise;
 };
 
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/sta.c b/drivers/net/wireless/intel/iwlwifi/mld/sta.c
index 7957ac11b0cd5..97f013330f068 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/sta.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/sta.c
@@ -465,8 +465,8 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld *mld,
 	struct iwl_mld_sta *mld_sta = iwl_mld_sta_from_mac80211(sta);
 	struct iwl_sta_cfg_cmd cmd = {};
 	int fw_id = iwl_mld_fw_sta_id_from_link_sta(mld, link_sta);
-	bool is_6ghz, uora_exists;
 	u32 link_mask;
+	bool is_6ghz;
 
 	lockdep_assert_wiphy(mld->wiphy);
 
@@ -479,7 +479,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld *mld,
 			return -EINVAL;
 
 		is_6ghz = false;
-		uora_exists = false;
 
 		link_mask = iwl_mld_get_nan_link_mask(mld);
 	} else {
@@ -495,7 +494,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld *mld,
 
 		link_mask = BIT(mld_link->fw_id);
 		is_6ghz = link->chanreq.oper.chan->band == NL80211_BAND_6GHZ;
-		uora_exists = link->uora_exists;
 	}
 
 	cmd.sta_id = cpu_to_le32(fw_id);
@@ -554,9 +552,6 @@ int iwl_mld_add_modify_sta_cmd(struct iwl_mld *mld,
 	}
 
 	if (link_sta->he_cap.has_he) {
-		cmd.trig_rnd_alloc =
-			cpu_to_le32(uora_exists ? 1 : 0);
-
 		/* PPE Thresholds */
 		iwl_mld_fill_pkt_ext(mld, link_sta, &cmd.pkt_ext);
 
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile b/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile
index efa61638b8eeb..730185be3fa82 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile
+++ b/drivers/net/wireless/intel/iwlwifi/mld/tests/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 iwlmld-tests-y += module.o hcmd.o utils.o link.o rx.o agg.o link-selection.o
-iwlmld-tests-y += chan_load_thresh.o
+iwlmld-tests-y += chan_load_thresh.o tx-gp2.o
 
 ccflags-y += -I$(src)/../
 obj-$(CONFIG_IWLWIFI_KUNIT_TESTS) += iwlmld-tests.o
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c b/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c
new file mode 100644
index 0000000000000..535140eb17c47
--- /dev/null
+++ b/drivers/net/wireless/intel/iwlwifi/mld/tests/tx-gp2.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * KUnit tests for TX gp2 timestamp handling
+ *
+ * Copyright (C) 2026 Intel Corporation
+ */
+#include <kunit/test.h>
+
+#include "mld.h"
+#include "tx.h"
+
+MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING");
+
+static const struct tx_gp2_case {
+	const char *desc;
+	u32 est_gp2_us;
+	u32 est_host_us;
+	u32 tx_host_us;
+	long valid_for;
+	u32 expected_gp2_us;
+	bool expected_refresh;
+} tx_gp2_cases[] = {
+	{
+		.desc = "zero offset is valid",
+		.est_gp2_us = 2000,
+		.est_host_us = 2000,
+		.tx_host_us = 3500,
+		.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,
+		.expected_gp2_us = 3500,
+	},
+	{
+		.desc = "gp2 behind host",
+		.est_gp2_us = 2000,
+		.est_host_us = 10000,
+		.tx_host_us = 11500,
+		.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,
+		.expected_gp2_us = 3500,
+	},
+	{
+		.desc = "gp2 ahead of host",
+		.est_gp2_us = 10000,
+		.est_host_us = 2000,
+		.tx_host_us = 3500,
+		.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,
+		.expected_gp2_us = 11500,
+	},
+	{
+		.desc = "gp2 wraps after the estimate",
+		.est_gp2_us = U32_MAX - 999,
+		.est_host_us = 1000,
+		.tx_host_us = 2500,
+		.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,
+		.expected_gp2_us = 500,
+	},
+	{
+		.desc = "host time wraps after the estimate",
+		.est_gp2_us = 5000,
+		.est_host_us = U32_MAX - 999,
+		.tx_host_us = 500,
+		.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,
+		.expected_gp2_us = 6500,
+	},
+	{
+		.desc = "gp2 landing on 0 is reported as 1",
+		.est_gp2_us = U32_MAX - 1499,
+		.est_host_us = 1000,
+		.tx_host_us = 2500,
+		.valid_for = IWL_MLD_TX_GP2_VALID_PERIOD,
+		.expected_gp2_us = 1,
+	},
+	{
+		.desc = "within the refresh margin: still timestamped",
+		.est_gp2_us = 2000,
+		.est_host_us = 10000,
+		.tx_host_us = 11500,
+		.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN - 1,
+		.expected_gp2_us = 3500,
+		.expected_refresh = true,
+	},
+	{
+		.desc = "outside the refresh margin: no refresh",
+		.est_gp2_us = 2000,
+		.est_host_us = 10000,
+		.tx_host_us = 11500,
+		.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN + 1,
+		.expected_gp2_us = 3500,
+	},
+	{
+		.desc = "at the refresh threshold",
+		.est_gp2_us = 2000,
+		.est_host_us = 10000,
+		.tx_host_us = 11500,
+		.valid_for = IWL_MLD_TX_GP2_REFRESH_MARGIN,
+		.expected_gp2_us = 3500,
+		.expected_refresh = true,
+	},
+	{
+		.desc = "last valid tick",
+		.est_gp2_us = 2000,
+		.est_host_us = 10000,
+		.tx_host_us = 11500,
+		.valid_for = 1,
+		.expected_gp2_us = 3500,
+		.expected_refresh = true,
+	},
+	{
+		.desc = "validity reached: leave the frame unstamped",
+		.est_gp2_us = 2000,
+		.est_host_us = 10000,
+		.tx_host_us = 11500,
+		.valid_for = 0,
+		.expected_refresh = true,
+	},
+	{
+		.desc = "validity passed: leave the frame unstamped",
+		.est_gp2_us = 2000,
+		.est_host_us = 10000,
+		.tx_host_us = 11500,
+		.valid_for = -1,
+		.expected_refresh = true,
+	},
+};
+
+KUNIT_ARRAY_PARAM_DESC(tx_gp2, tx_gp2_cases, desc);
+
+static void test_tx_gp2(struct kunit *test)
+{
+	/* Pin time near wraparound to exercise wrapped validity deadlines. */
+	const unsigned long now =
+		ULONG_MAX - IWL_MLD_TX_GP2_REFRESH_MARGIN - 1;
+	const struct tx_gp2_case *test_case = test->param_value;
+	u32 delta_us = test_case->est_gp2_us - test_case->est_host_us;
+	unsigned long valid_until = now + test_case->valid_for;
+	bool refresh = !test_case->expected_refresh;
+	u32 timestamp;
+
+	timestamp = iwl_mld_tx_gp2_from_est(delta_us, valid_until,
+					    test_case->tx_host_us, now,
+					    &refresh);
+	KUNIT_EXPECT_EQ(test, timestamp, test_case->expected_gp2_us);
+	KUNIT_EXPECT_EQ(test, refresh, test_case->expected_refresh);
+}
+
+static struct kunit_case tx_gp2_test_cases[] = {
+	KUNIT_CASE_PARAM(test_tx_gp2, tx_gp2_gen_params),
+	{}
+};
+
+static struct kunit_suite tx_gp2_test_suite = {
+	.name = "iwl_mld_tx_gp2",
+	.test_cases = tx_gp2_test_cases,
+};
+
+kunit_test_suite(tx_gp2_test_suite);
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/tx.c b/drivers/net/wireless/intel/iwlwifi/mld/tx.c
index 2df6643a5aa80..fc501ac0c1f29 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/tx.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/tx.c
@@ -2,6 +2,7 @@
 /*
  * Copyright (C) 2024 - 2026 Intel Corporation
  */
+#include <linux/timekeeping.h>
 #include <net/ip.h>
 
 #include "tx.h"
@@ -20,6 +21,133 @@
 
 #define MAX_ANT_NUM 2
 
+static u32 iwl_mld_tx_gp2_host_us(void)
+{
+	return div_u64(ktime_get_boottime_ns(), NSEC_PER_USEC);
+}
+
+/* Returns the gp2 for the TX command, or 0 to leave the frame unstamped.
+ * Sets @refresh when the estimate expired or is about to.
+ */
+VISIBLE_IF_IWLWIFI_KUNIT u32
+iwl_mld_tx_gp2_from_est(u32 delta_us, unsigned long valid_until, u32 host_us,
+			unsigned long now, bool *refresh)
+{
+	u32 gp2;
+
+	*refresh = time_after_eq(now, valid_until -
+				 IWL_MLD_TX_GP2_REFRESH_MARGIN);
+
+	if (time_after_eq(now, valid_until))
+		return 0;
+
+	gp2 = host_us + delta_us;
+
+	/* 0 means no timestamp; use 1 for a valid wrapped value. */
+	return gp2 ?: 1;
+}
+EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_mld_tx_gp2_from_est);
+
+static u32
+iwl_mld_tx_gp2_timestamp(struct iwl_mld *mld)
+{
+	unsigned long valid_until =
+		atomic_long_read_acquire(&mld->tx_gp2.valid_until);
+	bool refresh = false;
+	u32 gp2;
+
+	if (!valid_until)
+		return 0;
+
+	gp2 = iwl_mld_tx_gp2_from_est(atomic_read(&mld->tx_gp2.delta_us),
+				      valid_until, iwl_mld_tx_gp2_host_us(),
+				      jiffies, &refresh);
+
+	if (refresh)
+		wiphy_delayed_work_queue(mld->wiphy, &mld->tx_gp2.wk, 0);
+
+	return gp2;
+}
+
+static void iwl_mld_tx_gp2_refresh(struct iwl_mld *mld)
+{
+	unsigned long valid_until, delay;
+	u32 gp2, host_us;
+
+	lockdep_assert_wiphy(mld->wiphy);
+
+	if (!mld->fw_status.running)
+		return;
+
+#ifdef CONFIG_PM_SLEEP
+	if (mld->fw_status.in_d3)
+		return;
+#endif
+
+	if (iwl_mld_get_systime(mld, &gp2))
+		goto retry;
+
+	host_us = iwl_mld_tx_gp2_host_us();
+	valid_until = jiffies + IWL_MLD_TX_GP2_VALID_PERIOD;
+
+	/* Keep arithmetic in u32 to match firmware wraparound semantics. */
+	atomic_set(&mld->tx_gp2.delta_us, gp2 - host_us);
+	atomic_long_set_release(&mld->tx_gp2.valid_until, valid_until ?: 1);
+
+	IWL_DEBUG_TX(mld, "gp2 sync: gp2=%u host_us=%u delta_us=%u\n",
+		     gp2, host_us, gp2 - host_us);
+	return;
+
+retry:
+	/* Stop new TX readers from requesting immediate retries. */
+	atomic_long_set(&mld->tx_gp2.valid_until, 0);
+	delay = round_jiffies_relative(IWL_MLD_TX_GP2_RETRY_PERIOD);
+	wiphy_delayed_work_queue(mld->wiphy, &mld->tx_gp2.wk, delay);
+}
+
+static void iwl_mld_tx_gp2_wk(struct wiphy *wiphy, struct wiphy_work *wk)
+{
+	struct iwl_mld *mld = container_of(wk, struct iwl_mld, tx_gp2.wk.work);
+	unsigned long valid_until = atomic_long_read(&mld->tx_gp2.valid_until);
+
+	/* TX may have queued this work using an older estimate. */
+	if (valid_until &&
+	    time_before(jiffies, valid_until - IWL_MLD_TX_GP2_REFRESH_MARGIN))
+		return;
+
+	iwl_mld_tx_gp2_refresh(mld);
+}
+
+void iwl_mld_tx_gp2_init(struct iwl_mld *mld)
+{
+	atomic_set(&mld->tx_gp2.delta_us, 0);
+	atomic_long_set(&mld->tx_gp2.valid_until, 0);
+	wiphy_delayed_work_init(&mld->tx_gp2.wk, iwl_mld_tx_gp2_wk);
+}
+
+void iwl_mld_tx_gp2_start(struct iwl_mld *mld)
+{
+	lockdep_assert_wiphy(mld->wiphy);
+
+	if (iwl_fw_lookup_cmd_ver(mld->fw, TX_CMD, 0) < 12)
+		return;
+
+	iwl_mld_tx_gp2_refresh(mld);
+}
+
+/* TX is quiesced before stopping the refresh work. */
+void iwl_mld_tx_gp2_stop(struct iwl_mld *mld)
+{
+	lockdep_assert_wiphy(mld->wiphy);
+
+	if (iwl_fw_lookup_cmd_ver(mld->fw, TX_CMD, 0) < 12)
+		return;
+
+	wiphy_delayed_work_cancel(mld->wiphy, &mld->tx_gp2.wk);
+
+	atomic_long_set(&mld->tx_gp2.valid_until, 0);
+}
+
 /* Toggles between TX antennas. Receives the bitmask of valid TX antennas and
  * the *index* used for the last TX, and returns the next valid *index* to use.
  * In order to set it in the tx_cmd, must do BIT(idx).
@@ -588,6 +716,9 @@ iwl_mld_fill_tx_cmd(struct iwl_mld *mld, struct sk_buff *skb,
 	tx_cmd->flags = cpu_to_le16(flags);
 
 	tx_cmd->rate_n_flags = rate_n_flags;
+
+	tx_cmd->driver_timestamp =
+		cpu_to_le32(iwl_mld_tx_gp2_timestamp(mld));
 }
 
 /* Caller of this need to check that info->control.vif is not NULL */
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/tx.h b/drivers/net/wireless/intel/iwlwifi/mld/tx.h
index 520f15f9d33ca..a376e8c9c5005 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/tx.h
+++ b/drivers/net/wireless/intel/iwlwifi/mld/tx.h
@@ -1,11 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2024 Intel Corporation
+ * Copyright (C) 2024, 2026 Intel Corporation
  */
 #ifndef __iwl_mld_tx_h__
 #define __iwl_mld_tx_h__
 
-#include "mld.h"
+#include <linux/atomic.h>
+#include <net/mac80211.h>
+
+struct iwl_mld;
+struct iwl_rx_packet;
 
 #define IWL_MLD_INVALID_QUEUE		0xFFFF
 #define IWL_MLD_INVALID_DROP_TX		0xFFFE
@@ -74,4 +78,37 @@ u8 iwl_mld_get_lowest_rate(struct iwl_mld *mld,
 void iwl_mld_tx_skb(struct iwl_mld *mld, struct sk_buff *skb,
 		    struct ieee80211_txq *txq);
 
+/**
+ * struct iwl_mld_tx_gp2 - gp2 timestamping state for TX commands
+ *
+ * Reading gp2 directly in the TX path is too costly. Instead, TX lazily
+ * schedules @wk to refresh gp2 in process context and adds @delta_us to the
+ * host clock to timestamp queued frames.
+ *
+ * A zero @valid_until leaves frames unstamped, including on older firmware
+ * without TX_CMD v12. A deadline that wraps to zero is published as one.
+ * Failed refreshes clear @valid_until, leaving @delta_us for old readers, and
+ * schedule a retry with %IWL_MLD_TX_GP2_RETRY_PERIOD rounded for timer
+ * coalescing, even without further TX traffic. Old readers may retry sooner.
+ *
+ * @delta_us: gp2 minus host time, in microseconds, modulo 2^32;
+ *	valid while @valid_until is nonzero and has not expired
+ * @valid_until: jiffies deadline for the offset, or zero when disabled
+ * @wk: worker that refreshes the offset and retries failures
+ */
+struct iwl_mld_tx_gp2 {
+	atomic_t delta_us;
+	atomic_long_t valid_until;
+	struct wiphy_delayed_work wk;
+};
+
+void iwl_mld_tx_gp2_init(struct iwl_mld *mld);
+void iwl_mld_tx_gp2_start(struct iwl_mld *mld);
+void iwl_mld_tx_gp2_stop(struct iwl_mld *mld);
+
+#if IS_ENABLED(CONFIG_IWLWIFI_KUNIT_TESTS)
+u32 iwl_mld_tx_gp2_from_est(u32 delta_us, unsigned long valid_until,
+			    u32 host_us, unsigned long now, bool *refresh);
+#endif
+
 #endif /* __iwl_mld_tx_h__ */
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
index 06502f57e823e..90175307a7db2 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
@@ -13,7 +13,7 @@
 
 #include "mvm.h"
 #include "sta.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "debugfs.h"
 #include "iwl-modparams.h"
 #include "iwl-drv.h"
@@ -1548,7 +1548,7 @@ iwl_dbgfs_prph_reg_read(struct file *file,
 
 	pos += scnprintf(buf + pos, bufsz - pos, "Reg 0x%x: (0x%x)\n",
 		mvm->dbgfs_prph_reg_addr,
-		iwl_read_prph(mvm->trans, mvm->dbgfs_prph_reg_addr));
+		iwl_trans_read_prph(mvm->trans, mvm->dbgfs_prph_reg_addr));
 
 	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
 }
@@ -1569,7 +1569,7 @@ iwl_dbgfs_prph_reg_write(struct iwl_mvm *mvm, char *buf,
 	if (args != 2)
 		return -EINVAL;
 
-	iwl_write_prph(mvm->trans, mvm->dbgfs_prph_reg_addr, value);
+	iwl_trans_write_prph(mvm->trans, mvm->dbgfs_prph_reg_addr, value);
 
 out:
 	return count;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c
index 8d7f60dcd0270..4c39a452564da 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c
@@ -7,7 +7,7 @@
 #include <linux/math64.h>
 #include <net/cfg80211.h>
 #include "mvm.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "constants.h"
 
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c
index c3402f5e47a03..ae109e3ea141c 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c
@@ -263,7 +263,7 @@ static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
 static void iwl_mvm_print_pd_notification(struct iwl_mvm *mvm)
 {
 #define IWL_FW_PRINT_REG_INFO(reg_name) \
-	IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_read_umac_prph(trans, reg_name))
+	IWL_ERR(mvm, #reg_name ": 0x%x\n", iwl_trans_read_umac_prph(trans, reg_name))
 
 	struct iwl_trans *trans = mvm->trans;
 	enum iwl_device_family device_family = trans->mac_cfg->device_family;
@@ -332,13 +332,13 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
 	    IWL_DEVICE_FAMILY_AX210) {
 		/* print these registers regardless of alive fail/success */
 		IWL_INFO(mvm, "WFPM_UMAC_PD_NOTIFICATION: 0x%x\n",
-			 iwl_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION));
+			 iwl_trans_read_umac_prph(mvm->trans, WFPM_ARC1_PD_NOTIFICATION));
 		IWL_INFO(mvm, "WFPM_LMAC2_PD_NOTIFICATION: 0x%x\n",
-			 iwl_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION));
+			 iwl_trans_read_umac_prph(mvm->trans, WFPM_LMAC2_PD_NOTIFICATION));
 		IWL_INFO(mvm, "WFPM_AUTH_KEY_0: 0x%x\n",
-			 iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG));
+			 iwl_trans_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG));
 		IWL_INFO(mvm, "CNVI_SCU_SEQ_DATA_DW9: 0x%x\n",
-			 iwl_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9));
+			 iwl_trans_read_prph(mvm->trans, CNVI_SCU_SEQ_DATA_DW9));
 	}
 
 	if (ret) {
@@ -349,15 +349,15 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
 					IWL_DEVICE_FAMILY_22000) {
 			IWL_ERR(mvm,
 				"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
-				iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
-				iwl_read_umac_prph(trans,
-						   UMAG_SB_CPU_2_STATUS));
+				iwl_trans_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
+				iwl_trans_read_umac_prph(trans,
+							 UMAG_SB_CPU_2_STATUS));
 		} else if (trans->mac_cfg->device_family >=
 			   IWL_DEVICE_FAMILY_8000) {
 			IWL_ERR(mvm,
 				"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
-				iwl_read_prph(trans, SB_CPU_1_STATUS),
-				iwl_read_prph(trans, SB_CPU_2_STATUS));
+				iwl_trans_read_prph(trans, SB_CPU_1_STATUS),
+				iwl_trans_read_prph(trans, SB_CPU_2_STATUS));
 		}
 
 		iwl_mvm_print_pd_notification(mvm);
@@ -374,15 +374,15 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
 		} else if (trans->mac_cfg->device_family >=
 					IWL_DEVICE_FAMILY_9000) {
 			IWL_ERR(mvm, "UMAC PC: 0x%x\n",
-				iwl_read_umac_prph(trans,
-						   UREG_UMAC_CURRENT_PC));
+				iwl_trans_read_umac_prph(trans,
+							 UREG_UMAC_CURRENT_PC));
 			IWL_ERR(mvm, "LMAC PC: 0x%x\n",
-				iwl_read_umac_prph(trans,
-						   UREG_LMAC1_CURRENT_PC));
+				iwl_trans_read_umac_prph(trans,
+							 UREG_LMAC1_CURRENT_PC));
 			if (iwl_mvm_is_cdb_supported(mvm))
 				IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
-					iwl_read_umac_prph(trans,
-						UREG_LMAC2_CURRENT_PC));
+					iwl_trans_read_umac_prph(trans,
+								 UREG_LMAC2_CURRENT_PC));
 		}
 
 		if (ret == -ETIMEDOUT && !mvm->fw_product_reset)
@@ -616,7 +616,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
 	mvm->rfkill_safe_init_done = false;
 
 	if (mvm->trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
-		sb_cfg = iwl_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG);
+		sb_cfg = iwl_trans_read_umac_prph(mvm->trans, SB_MODIFY_CFG_FLAG);
 		/* if needed, we'll reset this on our way out later */
 		mvm->fw_product_reset = sb_cfg == SB_CFG_RESIDES_IN_ROM;
 		if (mvm->fw_product_reset && iwl_mei_pldr_req())
@@ -640,8 +640,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
 		/* if we needed reset then fail here, but notify and remove */
 		if (mvm->fw_product_reset) {
 			iwl_mei_alive_notif(false);
-			iwl_trans_pcie_reset(mvm->trans,
-					     IWL_RESET_MODE_RESCAN);
+			iwl_trans_reset(mvm->trans, IWL_RESET_MODE_RESCAN);
 		}
 
 		goto error;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/led.c b/drivers/net/wireless/intel/iwlwifi/mvm/led.c
index c3cc1ea3ccc93..ac238c9638559 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/led.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/led.c
@@ -1,10 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2012-2014, 2018-2019, 2025 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2019, 2025-2026 Intel Corporation
  * Copyright (C) 2017 Intel Deutschland GmbH
  */
 #include <linux/leds.h>
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-csr.h"
 #include "mvm.h"
 
@@ -38,8 +38,8 @@ static void iwl_mvm_led_set(struct iwl_mvm *mvm, bool on)
 		return;
 	}
 
-	iwl_write32(mvm->trans, CSR_LED_REG,
-		    on ? CSR_LED_REG_TURN_ON : CSR_LED_REG_TURN_OFF);
+	iwl_trans_write32(mvm->trans, CSR_LED_REG,
+			  on ? CSR_LED_REG_TURN_ON : CSR_LED_REG_TURN_OFF);
 }
 
 static void iwl_led_brightness_set(struct led_classdev *led_cdev,
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c
index b2c5be22c293c..509e80fa0df5e 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c
@@ -7,7 +7,7 @@
 #include <linux/etherdevice.h>
 #include <linux/crc32.h>
 #include <net/mac80211.h>
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "fw-api.h"
 #include "mvm.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
index a4f3d3c2bd350..daa05339e3fbf 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
@@ -19,7 +19,7 @@
 
 #include "iwl-drv.h"
 #include "iwl-op-mode.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "mvm.h"
 #include "sta.h"
 #include "time-event.h"
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c
index 93d5cab87f645..1832514573612 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c
@@ -20,7 +20,6 @@
 #include "iwl-phy-db.h"
 #include "iwl-nvm-utils.h"
 #include "iwl-csr.h"
-#include "iwl-io.h"
 #include "iwl-prph.h"
 #include "rs.h"
 #include "fw/api/scan.h"
@@ -138,9 +137,9 @@ static void iwl_mvm_nic_config(struct iwl_op_mode *op_mode)
 	 * to lose ownership and not being able to obtain it back.
 	 */
 	if (!mvm->trans->mac_cfg->base->apmg_not_supported)
-		iwl_set_bits_mask_prph(mvm->trans, APMG_PS_CTRL_REG,
-				       APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
-				       ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
+		iwl_trans_set_bits_mask_prph(mvm->trans, APMG_PS_CTRL_REG,
+					     APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
+					     ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 }
 
 static void iwl_mvm_rx_monitor_notif(struct iwl_mvm *mvm,
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c
index a94eaca0b3ed5..c12eda75317d1 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c
@@ -10,7 +10,7 @@
 
 #include "mvm.h"
 #include "fw/api/scan.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-utils.h"
 
 #define IWL_DENSE_EBS_SCAN_RATIO 5
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c b/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c
index a7cd2e4ba1ae9..6aac71cfccb3e 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/tdls.c
@@ -2,12 +2,12 @@
 /*
  * Copyright (C) 2014 Intel Mobile Communications GmbH
  * Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2020, 2022-2025 Intel Corporation
+ * Copyright (C) 2018-2020, 2022-2026 Intel Corporation
  */
 #include <linux/etherdevice.h>
 #include "mvm.h"
 #include "time-event.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 
 #define TU_TO_US(x) (x * 1024)
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c
index 93b46c9e2333d..5a800d3f2a98f 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c
@@ -12,7 +12,6 @@
 #include "fw-api.h"
 #include "time-event.h"
 #include "mvm.h"
-#include "iwl-io.h"
 #include "iwl-prph.h"
 
 /*
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c
index 2fd4a99611450..e97ab2c9e5ba7 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c
@@ -7,7 +7,7 @@
 #include <net/mac80211.h>
 
 #include "iwl-debug.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-prph.h"
 #include "iwl-csr.h"
 #include "mvm.h"
@@ -1159,7 +1159,7 @@ u32 iwl_mvm_get_systime(struct iwl_mvm *mvm)
 	    mvm->trans->mac_cfg->base->gp2_reg_addr)
 		reg_addr = mvm->trans->mac_cfg->base->gp2_reg_addr;
 
-	return iwl_read_prph(mvm->trans, reg_addr);
+	return iwl_trans_read_prph(mvm->trans, reg_addr);
 }
 
 void iwl_mvm_get_sync_time(struct iwl_mvm *mvm, int clock_type,
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c
index c75210829ec94..0009a05511af1 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c
@@ -7,6 +7,7 @@
 #include "iwl-fh.h"
 #include "iwl-context-info-v2.h"
 #include "internal.h"
+#include "pcie/utils.h"
 #include "iwl-prph.h"
 
 static const struct dmi_system_id dmi_force_scu_active_approved_list[] = {
@@ -314,12 +315,12 @@ void iwl_pcie_ctxt_info_v2_kick(struct iwl_trans *trans)
 	iwl_enable_fw_load_int_ctx_info(trans, trans->do_top_reset);
 
 	/* kick FW self load */
-	iwl_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie->ctxt_info_dma_addr);
-	iwl_write64(trans, CSR_IML_DATA_ADDR, trans_pcie->iml_dma_addr);
-	iwl_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie->iml_len);
+	iwl_pcie_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie->ctxt_info_dma_addr);
+	iwl_pcie_write64(trans, CSR_IML_DATA_ADDR, trans_pcie->iml_dma_addr);
+	iwl_trans_pcie_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie->iml_len);
 
-	iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
-		    CSR_AUTO_FUNC_BOOT_ENA);
+	iwl_trans_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
+			  CSR_AUTO_FUNC_BOOT_ENA);
 }
 
 void iwl_pcie_ctxt_info_v2_free(struct iwl_trans *trans, bool alive)
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c
index 23ec968577bd9..bc90a2714251a 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c
@@ -7,6 +7,7 @@
 #include "iwl-fh.h"
 #include "iwl-context-info.h"
 #include "internal.h"
+#include "utils.h"
 #include "iwl-prph.h"
 
 static void *_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
@@ -245,7 +246,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
 		iwl_pcie_apply_destination(trans);
 
 	/* kick FW self load */
-	iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
+	iwl_pcie_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
 
 	/* Context info will be released upon alive or failure to get one */
 
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c
index 905482419a9af..24012005ccb87 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c
@@ -1252,7 +1252,7 @@ static int _iwl_pci_resume(struct device *device, bool restore)
 		 * For older devices, just try silently to grab the NIC.
 		 */
 		if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
-			u32 scratch = iwl_read32(trans, CSR_FUNC_SCRATCH);
+			u32 scratch = iwl_trans_pcie_read32(trans, CSR_FUNC_SCRATCH);
 
 			if (!(scratch & CSR_FUNC_SCRATCH_POWER_OFF_MASK) ||
 			    scratch == ~0U) {
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h
index e6b1cb559a0a6..01bfc1492c848 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h
@@ -18,12 +18,22 @@
 #include "iwl-fh.h"
 #include "iwl-csr.h"
 #include "iwl-trans.h"
+#include "iwl-devtrace.h"
 #include "iwl-debug.h"
-#include "iwl-io.h"
 #include "iwl-op-mode.h"
 #include "iwl-drv.h"
 #include "iwl-context-info.h"
 
+/* transport-specific register accessors (bus implementation) */
+void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val);
+void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val);
+u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs);
+u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg);
+void iwl_pcie_write_prph_no_grab(struct iwl_trans *trans, u32 addr, u32 val);
+
+/* bus-specific transport operations table */
+extern const struct iwl_trans_ops iwl_trans_pcie_ops;
+
 /*
  * RX related structures and functions
  */
@@ -593,7 +603,7 @@ static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
 	 * write 1 clear (W1C) register, meaning that it's being clear
 	 * by writing 1 to the bit.
 	 */
-	iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
+	iwl_trans_pcie_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
 }
 
 static inline struct iwl_trans *
@@ -889,18 +899,18 @@ static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
 	clear_bit(STATUS_INT_ENABLED, &trans->status);
 	if (!trans_pcie->msix_enabled) {
 		/* disable interrupts from uCode/NIC to host */
-		iwl_write32(trans, CSR_INT_MASK, 0x00000000);
+		iwl_trans_pcie_write32(trans, CSR_INT_MASK, 0x00000000);
 
 		/* acknowledge/clear/reset any interrupts still pending
 		 * from uCode or flow handler (Rx/Tx DMA) */
-		iwl_write32(trans, CSR_INT, 0xffffffff);
-		iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
+		iwl_trans_pcie_write32(trans, CSR_INT, 0xffffffff);
+		iwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
 	} else {
 		/* disable all the interrupt we might use */
-		iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
-			    trans_pcie->fh_init_mask);
-		iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
-			    trans_pcie->hw_init_mask);
+		iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
+				       trans_pcie->fh_init_mask);
+		iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
+				       trans_pcie->hw_init_mask);
 		trans_pcie->fh_mask = 0;
 		trans_pcie->hw_mask = 0;
 	}
@@ -958,7 +968,7 @@ static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
 	set_bit(STATUS_INT_ENABLED, &trans->status);
 	if (!trans_pcie->msix_enabled) {
 		trans_pcie->inta_mask = CSR_INI_SET_MASK;
-		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
+		iwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 	} else {
 		/*
 		 * fh/hw_mask keeps all the unmasked causes.
@@ -966,10 +976,10 @@ static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
 		 */
 		trans_pcie->hw_mask = trans_pcie->hw_init_mask;
 		trans_pcie->fh_mask = trans_pcie->fh_init_mask;
-		iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
-			    ~trans_pcie->fh_mask);
-		iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
-			    ~trans_pcie->hw_mask);
+		iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
+				       ~trans_pcie->fh_mask);
+		iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
+				       ~trans_pcie->hw_mask);
 	}
 }
 
@@ -985,7 +995,7 @@ static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
 {
 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 
-	iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
+	iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
 	trans_pcie->hw_mask = msk;
 }
 
@@ -993,7 +1003,7 @@ static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
 {
 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 
-	iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
+	iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
 	trans_pcie->fh_mask = msk;
 }
 
@@ -1004,10 +1014,10 @@ static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
 	IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
 	if (!trans_pcie->msix_enabled) {
 		trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
-		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
+		iwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 	} else {
-		iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
-			    trans_pcie->hw_init_mask);
+		iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
+				       trans_pcie->hw_init_mask);
 		iwl_enable_fh_int_msk_msix(trans,
 					   MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
 	}
@@ -1034,7 +1044,7 @@ static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans,
 		else
 			trans_pcie->inta_mask =  CSR_INT_BIT_ALIVE |
 						 CSR_INT_BIT_FH_RX;
-		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
+		iwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 	} else {
 		u32 val = top_reset ? MSIX_HW_INT_CAUSES_REG_RESET_DONE
 				    : MSIX_HW_INT_CAUSES_REG_ALIVE;
@@ -1081,10 +1091,10 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
 	IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
 	if (!trans_pcie->msix_enabled) {
 		trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
-		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
+		iwl_trans_pcie_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 	} else {
-		iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
-			    trans_pcie->fh_init_mask);
+		iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
+				       trans_pcie->fh_init_mask);
 		trans_pcie->fh_mask = 0;
 		iwl_enable_hw_int_msk_msix(trans,
 					   MSIX_HW_INT_CAUSES_REG_RF_KILL);
@@ -1096,8 +1106,8 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
 		 * when we power down the device we need set the bit to allow it
 		 * to wake up the PCI-E bus for RF-kill interrupts.
 		 */
-		iwl_set_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
+		iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+				  CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
 	}
 }
 
@@ -1112,7 +1122,7 @@ static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
 	if (trans_pcie->debug_rfkill == 1)
 		return true;
 
-	return !(iwl_read32(trans, CSR_GP_CNTRL) &
+	return !(iwl_trans_pcie_read32(trans, CSR_GP_CNTRL) &
 		CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
 }
 
@@ -1136,16 +1146,12 @@ void iwl_trans_pcie_op_mode_enter(struct iwl_trans *trans);
 int _iwl_trans_pcie_start_hw(struct iwl_trans *trans);
 int iwl_trans_pcie_start_hw(struct iwl_trans *trans);
 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans);
-void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val);
-void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val);
-u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs);
-u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg);
-void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val);
 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
 			    void *buf, int dwords);
 int iwl_trans_pcie_read_mem_no_grab(struct iwl_trans *trans, u32 addr,
 				    void *buf, u32 dwords);
 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership);
+void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans);
 struct iwl_trans_dump_data *
 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,
 			 const struct iwl_dump_sanitize_ops *sanitize_ops,
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
index db3933b0d1979..f033bb51dcca3 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
@@ -9,8 +9,9 @@
 #include <linux/gfp.h>
 
 #include "iwl-prph.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "internal.h"
+#include "pcie/utils.h"
 #include "iwl-op-mode.h"
 #include "iwl-context-info-v2.h"
 #include "fw/dbg.h"
@@ -146,18 +147,18 @@ int iwl_pcie_rx_stop(struct iwl_trans *trans)
 {
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
 		/* TODO: remove this once fw does it */
-		iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0);
-		return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210,
-					      RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
+		iwl_trans_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0);
+		return iwl_pcie_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210,
+						   RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 	} else if (trans->mac_cfg->mq_rx_supported) {
-		iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
-		return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
-					   RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
+		iwl_trans_write_prph(trans, RFH_RXF_DMA_CFG, 0);
+		return iwl_pcie_poll_prph_bit(trans, RFH_GEN_STATUS,
+					      RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 	} else {
-		iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
-		return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
-					   FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
-					   1000);
+		iwl_trans_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
+		return iwl_pcie_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
+						FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
+						1000);
 	}
 }
 
@@ -178,13 +179,13 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 	 */
 	if (!trans->mac_cfg->base->shadow_reg_enable &&
 	    test_bit(STATUS_TPOWER_PMI, &trans->status)) {
-		reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
+		reg = iwl_trans_pcie_read32(trans, CSR_UCODE_DRV_GP1);
 
 		if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 			IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
 				       reg);
-			iwl_set_bit(trans, CSR_GP_CNTRL,
-				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+			iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+					  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 			rxq->need_update = true;
 			return;
 		}
@@ -192,13 +193,13 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 
 	rxq->write_actual = round_down(rxq->write, 8);
 	if (!trans->mac_cfg->mq_rx_supported)
-		iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
+		iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 	else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
-		iwl_write32(trans, HBUS_TARG_WRPTR, rxq->write_actual |
-			    HBUS_TARG_WRPTR_RX_Q(rxq->id));
+		iwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, rxq->write_actual |
+				       HBUS_TARG_WRPTR_RX_Q(rxq->id));
 	else
-		iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
-			    rxq->write_actual);
+		iwl_trans_pcie_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
+				       rxq->write_actual);
 }
 
 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
@@ -854,22 +855,22 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 		return;
 
 	/* Stop Rx DMA */
-	iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
+	iwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 	/* reset and flush pointers */
-	iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
-	iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
-	iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
+	iwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
+	iwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
+	iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 
 	/* Reset driver's Rx queue write index */
-	iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
+	iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 
 	/* Tell device where to find RBD circular buffer in DRAM */
-	iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
-		    (u32)(rxq->bd_dma >> 8));
+	iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
+			       (u32)(rxq->bd_dma >> 8));
 
 	/* Tell device where in DRAM to update its Rx status */
-	iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
-		    rxq->rb_stts_dma >> 4);
+	iwl_trans_pcie_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
+			       rxq->rb_stts_dma >> 4);
 
 	/* Enable Rx DMA
 	 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
@@ -879,22 +880,22 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 	 * RB timeout 0x10
 	 * 256 RBDs
 	 */
-	iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
-		    FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
-		    FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
-		    FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
-		    rb_size |
-		    (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
-		    (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
+	iwl_trans_pcie_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
+			       FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
+			       FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
+			       FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
+			       rb_size |
+			       (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
+			       (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 
 	iwl_trans_release_nic_access(trans);
 
 	/* Set interrupt coalescing timer to default (2048 usecs) */
-	iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
+	iwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 
 	/* W/A for interrupt coalescing bug in 7260 and 3160 */
 	if (trans->cfg->host_interrupt_operation_mode)
-		iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
+		iwl_trans_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 }
 
 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
@@ -925,27 +926,27 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
 		return;
 
 	/* Stop Rx DMA */
-	iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
+	iwl_pcie_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
 	/* disable free amd used rx queue operation */
-	iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
+	iwl_pcie_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
 
 	for (i = 0; i < trans->info.num_rxqs; i++) {
 		/* Tell device where to find RBD free table in DRAM */
-		iwl_write_prph64_no_grab(trans,
-					 RFH_Q_FRBDCB_BA_LSB(i),
-					 trans_pcie->rxq[i].bd_dma);
+		iwl_pcie_write_prph64_no_grab(trans,
+					      RFH_Q_FRBDCB_BA_LSB(i),
+					      trans_pcie->rxq[i].bd_dma);
 		/* Tell device where to find RBD used table in DRAM */
-		iwl_write_prph64_no_grab(trans,
-					 RFH_Q_URBDCB_BA_LSB(i),
-					 trans_pcie->rxq[i].used_bd_dma);
+		iwl_pcie_write_prph64_no_grab(trans,
+					      RFH_Q_URBDCB_BA_LSB(i),
+					      trans_pcie->rxq[i].used_bd_dma);
 		/* Tell device where in DRAM to update its Rx status */
-		iwl_write_prph64_no_grab(trans,
-					 RFH_Q_URBD_STTS_WPTR_LSB(i),
-					 trans_pcie->rxq[i].rb_stts_dma);
+		iwl_pcie_write_prph64_no_grab(trans,
+					      RFH_Q_URBD_STTS_WPTR_LSB(i),
+					      trans_pcie->rxq[i].rb_stts_dma);
 		/* Reset device indice tables */
-		iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
-		iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
-		iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
+		iwl_pcie_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
+		iwl_pcie_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
+		iwl_pcie_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
 
 		enabled |= BIT(i) | BIT(i + 16);
 	}
@@ -957,32 +958,32 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
 	 * Drop frames that exceed RB size
 	 * 512 RBDs
 	 */
-	iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
-			       RFH_DMA_EN_ENABLE_VAL | rb_size |
-			       RFH_RXF_DMA_MIN_RB_4_8 |
-			       RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
-			       RFH_RXF_DMA_RBDCB_SIZE_512);
+	iwl_pcie_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
+				    RFH_DMA_EN_ENABLE_VAL | rb_size |
+				    RFH_RXF_DMA_MIN_RB_4_8 |
+				    RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
+				    RFH_RXF_DMA_RBDCB_SIZE_512);
 
 	/*
 	 * Activate DMA snooping.
 	 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
 	 * Default queue is 0
 	 */
-	iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
-			       RFH_GEN_CFG_RFH_DMA_SNOOP |
-			       RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
-			       RFH_GEN_CFG_SERVICE_DMA_SNOOP |
-			       RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
-					       trans->mac_cfg->integrated ?
-					       RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
-					       RFH_GEN_CFG_RB_CHUNK_SIZE_128));
+	iwl_pcie_write_prph_no_grab(trans, RFH_GEN_CFG,
+				    RFH_GEN_CFG_RFH_DMA_SNOOP |
+				    RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
+				    RFH_GEN_CFG_SERVICE_DMA_SNOOP |
+				    RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
+						    trans->mac_cfg->integrated ?
+						    RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
+						    RFH_GEN_CFG_RB_CHUNK_SIZE_128));
 	/* Enable the relevant rx queues */
-	iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
+	iwl_pcie_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
 
 	iwl_trans_release_nic_access(trans);
 
 	/* Set interrupt coalescing timer to default (2048 usecs) */
-	iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
+	iwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 }
 
 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
@@ -1189,7 +1190,7 @@ int iwl_pcie_rx_init(struct iwl_trans *trans)
 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
 {
 	/* Set interrupt coalescing timer to default (2048 usecs) */
-	iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
+	iwl_trans_pcie_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 
 	/*
 	 * We don't configure the RFH.
@@ -1691,9 +1692,9 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
 	/* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 	if (trans->cfg->internal_wimax_coex &&
 	    !trans->mac_cfg->base->apmg_not_supported &&
-	    (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
+	    (!(iwl_trans_read_prph(trans, APMG_CLK_CTRL_REG) &
 			     APMS_CLK_VAL_MRB_FUNC_MODE) ||
-	     (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
+	     (iwl_trans_read_prph(trans, APMG_PS_CTRL_REG) &
 			    APMG_PS_CTRL_VAL_RESET_REQ))) {
 		clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 		iwl_op_mode_wimax_active(trans->op_mode);
@@ -1708,7 +1709,7 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
 	}
 
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_SC) {
-		u32 val = iwl_read32(trans, CSR_IPC_STATE);
+		u32 val = iwl_trans_pcie_read32(trans, CSR_IPC_STATE);
 
 		if (val & CSR_IPC_STATE_TOP_RESET_REQ) {
 			IWL_ERR(trans, "FW requested TOP reset for FSEQ\n");
@@ -1733,7 +1734,7 @@ static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
 	trace_iwlwifi_dev_irq(trans->dev);
 
 	/* Discover which interrupts are active/pending */
-	inta = iwl_read32(trans, CSR_INT);
+	inta = iwl_trans_pcie_read32(trans, CSR_INT);
 
 	/* the thread will service interrupts and re-enable them */
 	return inta;
@@ -1850,7 +1851,7 @@ static void iwl_trans_pcie_handle_reset_interrupt(struct iwl_trans *trans)
 	u32 state;
 
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_SC) {
-		u32 val = iwl_read32(trans, CSR_IPC_STATE);
+		u32 val = iwl_trans_pcie_read32(trans, CSR_IPC_STATE);
 
 		state = u32_get_bits(val, CSR_IPC_STATE_RESET);
 		IWL_DEBUG_ISR(trans, "IPC state = 0x%x/%d\n", val, state);
@@ -1922,8 +1923,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 		IWL_DEBUG_ISR(trans,
 			      "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
 			      inta, trans_pcie->inta_mask,
-			      iwl_read32(trans, CSR_INT_MASK),
-			      iwl_read32(trans, CSR_FH_INT_STATUS));
+			      iwl_trans_pcie_read32(trans, CSR_INT_MASK),
+			      iwl_trans_pcie_read32(trans, CSR_FH_INT_STATUS));
 		if (inta & (~trans_pcie->inta_mask))
 			IWL_DEBUG_ISR(trans,
 				      "We got a masked interrupt (0x%08x)\n",
@@ -1971,11 +1972,11 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 	 * hardware bugs here by ACKing all the possible interrupts so that
 	 * interrupt coalescing can still be achieved.
 	 */
-	iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
+	iwl_trans_pcie_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
 
 	if (iwl_have_debug_level(IWL_DL_ISR))
 		IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
-			      inta, iwl_read32(trans, CSR_INT_MASK));
+			      inta, iwl_trans_pcie_read32(trans, CSR_INT_MASK));
 
 	spin_unlock_bh(&trans_pcie->irq_lock);
 
@@ -2070,13 +2071,13 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 		IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 		if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 			handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
-			iwl_write32(trans, CSR_FH_INT_STATUS,
-					CSR_FH_INT_RX_MASK);
+			iwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS,
+					       CSR_FH_INT_RX_MASK);
 		}
 		if (inta & CSR_INT_BIT_RX_PERIODIC) {
 			handled |= CSR_INT_BIT_RX_PERIODIC;
-			iwl_write32(trans,
-				CSR_INT, CSR_INT_BIT_RX_PERIODIC);
+			iwl_trans_pcie_write32(trans,
+					       CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 		}
 		/* Sending RX interrupt require many steps to be done in the
 		 * device:
@@ -2090,8 +2091,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 		 */
 
 		/* Disable periodic interrupt; we use it as just a one-shot. */
-		iwl_write8(trans, CSR_INT_PERIODIC_REG,
-			    CSR_INT_PERIODIC_DIS);
+		iwl_trans_pcie_write8(trans, CSR_INT_PERIODIC_REG,
+				      CSR_INT_PERIODIC_DIS);
 
 		/*
 		 * Enable periodic interrupt in 8 msec only if we received
@@ -2101,8 +2102,8 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 		 * to extend the periodic interrupt; one-shot is enough.
 		 */
 		if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
-			iwl_write8(trans, CSR_INT_PERIODIC_REG,
-				   CSR_INT_PERIODIC_ENA);
+			iwl_trans_pcie_write8(trans, CSR_INT_PERIODIC_REG,
+					      CSR_INT_PERIODIC_ENA);
 
 		isr_stats->rx++;
 
@@ -2116,7 +2117,7 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 
 	/* This "Tx" DMA channel is used only for loading uCode */
 	if (inta & CSR_INT_BIT_FH_TX) {
-		iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
+		iwl_trans_pcie_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 		IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 		isr_stats->tx++;
 		handled |= CSR_INT_BIT_FH_TX;
@@ -2230,10 +2231,10 @@ void iwl_pcie_reset_ict(struct iwl_trans *trans)
 
 	IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
 
-	iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
+	iwl_trans_pcie_write32(trans, CSR_DRAM_INT_TBL_REG, val);
 	trans_pcie->use_ict = true;
 	trans_pcie->ict_index = 0;
-	iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
+	iwl_trans_pcie_write32(trans, CSR_INT, trans_pcie->inta_mask);
 	_iwl_enable_interrupts(trans);
 	spin_unlock_bh(&trans_pcie->irq_lock);
 }
@@ -2260,7 +2261,7 @@ irqreturn_t iwl_pcie_isr(int irq, void *data)
 	 * If we have something to service, the tasklet will re-enable ints.
 	 * If we *don't* have something, we'll re-enable before leaving here.
 	 */
-	iwl_write32(trans, CSR_INT_MASK, 0x00000000);
+	iwl_trans_pcie_write32(trans, CSR_INT_MASK, 0x00000000);
 
 	return IRQ_WAKE_THREAD;
 }
@@ -2290,13 +2291,13 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
 	lock_map_acquire(&trans->sync_cmd_lockdep_map);
 
 	spin_lock_bh(&trans_pcie->irq_lock);
-	inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
-	inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
+	inta_fh = iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
+	inta_hw = iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
 	/*
 	 * Clear causes registers to avoid being handling the same cause.
 	 */
-	iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk);
-	iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
+	iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk);
+	iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
 	spin_unlock_bh(&trans_pcie->irq_lock);
 
 	trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
@@ -2311,7 +2312,7 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
 		IWL_DEBUG_ISR(trans,
 			      "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
 			      entry->entry, inta_fh, trans_pcie->fh_mask,
-			      iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
+			      iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
 		if (inta_fh & ~trans_pcie->fh_mask)
 			IWL_DEBUG_ISR(trans,
 				      "We got a masked interrupt (0x%08x)\n",
@@ -2413,7 +2414,7 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
 		IWL_DEBUG_ISR(trans,
 			      "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
 			      entry->entry, inta_hw, trans_pcie->hw_mask,
-			      iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
+			      iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
 		if (inta_hw & ~trans_pcie->hw_mask)
 			IWL_DEBUG_ISR(trans,
 				      "We got a masked interrupt 0x%08x\n",
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c
index 39dd963920b31..dce6043fe9627 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c
@@ -32,18 +32,18 @@ int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
 	 * Disable L0s without affecting L1;
 	 * don't wait for ICH L0s (ICH bug W/A)
 	 */
-	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
-		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
+	iwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,
+			  CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 
 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
-	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
+	iwl_trans_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 
 	/*
 	 * Enable HAP INTA (interrupt from management bus) to
 	 * wake device's PCI Express link L1a -> L0s
 	 */
-	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-		    CSR_HW_IF_CONFIG_REG_HAP_WAKE);
+	iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+			  CSR_HW_IF_CONFIG_REG_HAP_WAKE);
 
 	iwl_pcie_apm_config(trans);
 
@@ -65,14 +65,14 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 			iwl_pcie_gen2_apm_init(trans);
 
 		/* inform ME that we are leaving */
-		iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
-			    CSR_RESET_LINK_PWR_MGMT_DISABLED);
-		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-			    CSR_HW_IF_CONFIG_REG_WAKE_ME |
-			    CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
+		iwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+				  CSR_RESET_LINK_PWR_MGMT_DISABLED);
+		iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+				  CSR_HW_IF_CONFIG_REG_WAKE_ME |
+				  CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
 		mdelay(1);
-		iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
-			      CSR_RESET_LINK_PWR_MGMT_DISABLED);
+		iwl_trans_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
 		mdelay(5);
 	}
 
@@ -88,11 +88,11 @@ static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 	 */
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
 	else
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 }
 
 static void
@@ -105,14 +105,14 @@ _iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans,
 	trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
 
 	if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
-		iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
-				    UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
+		iwl_trans_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
+					  UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
 	else if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
-		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
-				    UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
+		iwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
+					  UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
 	else
-		iwl_write32(trans, CSR_DOORBELL_VECTOR,
-			    UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
+		iwl_trans_pcie_write32(trans, CSR_DOORBELL_VECTOR,
+				       UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
 
 	/* wait 200ms */
 	ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
@@ -123,11 +123,11 @@ _iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans,
 		u32 inta_hw;
 
 		if (trans_pcie->msix_enabled) {
-			inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
+			inta_hw = iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
 			reset_done =
 				inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE;
 		} else {
-			inta_hw = iwl_read32(trans, CSR_INT);
+			inta_hw = iwl_trans_pcie_read32(trans, CSR_INT);
 			reset_done = inta_hw & CSR_INT_BIT_RESET_DONE;
 		}
 
@@ -281,7 +281,7 @@ static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
 		return -ENOMEM;
 
 	/* enable shadow regs in HW */
-	iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
+	iwl_trans_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 	IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 
 	return 0;
@@ -342,7 +342,7 @@ static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
-		version = iwl_read_prph(trans, CNVI_MBOX_C);
+		version = iwl_trans_read_prph(trans, CNVI_MBOX_C);
 		switch (version) {
 		case 0x20000:
 			pos += scnprintf(buf + pos, buflen - pos, " B3");
@@ -410,7 +410,7 @@ void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans)
 
 	step_reg = trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_SC ?
 		   CNVI_PMU_STEP_FLOW_SC : CNVI_PMU_STEP_FLOW_BZ;
-	trans->step_urm = !!(iwl_read_prph(trans, step_reg) &
+	trans->step_urm = !!(iwl_trans_read_prph(trans, step_reg) &
 			     CNVI_PMU_STEP_FLOW_FORCE_URM);
 }
 
@@ -434,21 +434,21 @@ static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
 	if ((trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
 	     trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
 	    !trans->mac_cfg->integrated) {
-		iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
+		iwl_trans_pcie_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
 		return true;
 	}
 
 	if (trans->mac_cfg->integrated &&
 	    trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
-		iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
-		iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
+		iwl_trans_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
+		iwl_trans_write_prph(trans, HPM_UMAC_LTR, ltr_val);
 		return true;
 	}
 
 	if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
 		/* First clear the interrupt, just in case */
-		iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
-			    MSIX_HW_INT_CAUSES_REG_IML);
+		iwl_trans_pcie_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
+				       MSIX_HW_INT_CAUSES_REG_IML);
 		/* In this case, unfortunately the same ROM bug exists in the
 		 * device (not setting LTR correctly), but we don't have control
 		 * over the settings from the host due to some hardware security
@@ -475,18 +475,18 @@ static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
 	if (WARN_ON(!trans_pcie->iml))
 		return;
 
-	value = iwl_read32(trans, CSR_LTR_LAST_MSG);
+	value = iwl_trans_pcie_read32(trans, CSR_LTR_LAST_MSG);
 	IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
 		       value);
 
 	while (time_before(jiffies, end_time)) {
-		if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
+		if (iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
 				MSIX_HW_INT_CAUSES_REG_IML) {
 			irq = true;
 			break;
 		}
 		/* Keep the CPU and device busy. */
-		value = iwl_read32(trans, CSR_LTR_LAST_MSG);
+		value = iwl_trans_pcie_read32(trans, CSR_LTR_LAST_MSG);
 		loops++;
 	}
 
@@ -522,7 +522,7 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
 
 	iwl_enable_rfkill_int(trans);
 
-	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
+	iwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);
 
 	/*
 	 * We enabled the RF-Kill interrupt and the handler may very
@@ -550,12 +550,12 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
 	}
 
 	/* make sure rfkill handshake bits are cleared */
-	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
-	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
-		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
+	iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
+	iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR,
+			       CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 
 	/* clear (again), then enable host interrupts */
-	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
+	iwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);
 
 	ret = iwl_pcie_gen2_nic_init(trans);
 	if (ret) {
@@ -591,14 +591,14 @@ int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
 
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
 		IWL_DEBUG_POWER(trans, "function scratch register value is 0x%08x\n",
-				iwl_read32(trans, CSR_FUNC_SCRATCH));
-		iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
-		iwl_set_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_ROM_START);
+				iwl_trans_pcie_read32(trans, CSR_FUNC_SCRATCH));
+		iwl_trans_pcie_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
+		iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+				  CSR_GP_CNTRL_REG_FLAG_ROM_START);
 	} else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
-		iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
+		iwl_trans_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
 	} else {
-		iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
+		iwl_trans_write_prph(trans, UREG_CPU_INIT_RUN, 1);
 	}
 
 	if (keep_ram_busy)
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
index bda069a6f7ebf..eda88940dd074 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
@@ -44,10 +44,10 @@ static void iwl_dump_host_monitor_block(struct iwl_trans *trans,
 	int i;
 
 	IWL_ERR(trans, "Host monitor block 0x%x vector 0x%x\n", block, vec);
-	iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec);
+	iwl_trans_pcie_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec);
 	for (i = 0; i < iter; i++)
 		IWL_ERR(trans, "    value [iter %d]: 0x%08x\n",
-			i, iwl_read32(trans, CSR_MONITOR_STATUS_REG));
+			i, iwl_trans_pcie_read32(trans, CSR_MONITOR_STATUS_REG));
 }
 
 static void iwl_pcie_dump_host_monitor(struct iwl_trans *trans)
@@ -56,7 +56,7 @@ static void iwl_pcie_dump_host_monitor(struct iwl_trans *trans)
 	case IWL_DEVICE_FAMILY_22000:
 	case IWL_DEVICE_FAMILY_AX210:
 		IWL_ERR(trans, "CSR_RESET = 0x%x\n",
-			iwl_read32(trans, CSR_RESET));
+			iwl_trans_pcie_read32(trans, CSR_RESET));
 		iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
 					    IWL_HOST_MON_BLOCK_PEMON_VEC0, 15);
 		iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
@@ -79,12 +79,12 @@ int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership)
 {
 	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
-		iwl_set_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_SW_RESET);
+		iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+				  CSR_GP_CNTRL_REG_FLAG_SW_RESET);
 		usleep_range(10000, 20000);
 	} else {
-		iwl_set_bit(trans, CSR_RESET,
-			    CSR_RESET_REG_FLAG_SW_RESET);
+		iwl_trans_set_bit(trans, CSR_RESET,
+				  CSR_RESET_REG_FLAG_SW_RESET);
 		usleep_range(5000, 6000);
 	}
 
@@ -170,16 +170,16 @@ void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 
 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 {
-	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
-		    ((reg & 0x0000ffff) | (2 << 28)));
-	return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
+	iwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
+			       ((reg & 0x0000ffff) | (2 << 28)));
+	return iwl_trans_pcie_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 }
 
 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 {
-	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
-	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
-		    ((reg & 0x0000ffff) | (3 << 28)));
+	iwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
+	iwl_trans_pcie_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
+			       ((reg & 0x0000ffff) | (3 << 28)));
 }
 
 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
@@ -188,13 +188,13 @@ static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 		return;
 
 	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
-		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
-				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
-				       ~APMG_PS_CTRL_MSK_PWR_SRC);
+		iwl_trans_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
+					     APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
+					     ~APMG_PS_CTRL_MSK_PWR_SRC);
 	else
-		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
-				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
-				       ~APMG_PS_CTRL_MSK_PWR_SRC);
+		iwl_trans_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
+					     APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
+					     ~APMG_PS_CTRL_MSK_PWR_SRC);
 }
 
 /* PCI registers */
@@ -211,7 +211,7 @@ void iwl_pcie_apm_config(struct iwl_trans *trans)
 	 * and in newer hardware they are not officially supported at
 	 * all, so we must always set the L0S_DISABLED bit.
 	 */
-	iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
+	iwl_trans_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
 
 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 	trans_pcie->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
@@ -241,31 +241,31 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
 
 	/* Disable L0S exit timer (platform NMI Work/Around) */
 	if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_8000)
-		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
-			    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
+		iwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,
+				  CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 
 	/*
 	 * Disable L0s without affecting L1;
 	 *  don't wait for ICH L0s (ICH bug W/A)
 	 */
-	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
-		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
+	iwl_trans_set_bit(trans, CSR_GIO_CHICKEN_BITS,
+			  CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 
 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
-	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
+	iwl_trans_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 
 	/*
 	 * Enable HAP INTA (interrupt from management bus) to
 	 * wake device's PCI Express link L1a -> L0s
 	 */
-	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-		    CSR_HW_IF_CONFIG_REG_HAP_WAKE);
+	iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+			  CSR_HW_IF_CONFIG_REG_HAP_WAKE);
 
 	iwl_pcie_apm_config(trans);
 
 	/* Configure analog phase-lock-loop before activating to D0A */
 	if (trans->mac_cfg->base->pll_cfg)
-		iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
+		iwl_trans_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 
 	ret = iwl_trans_activate_nic(trans);
 	if (ret)
@@ -286,11 +286,11 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
 		 * just to discard the value. But that's the way the hardware
 		 * seems to like it.
 		 */
-		iwl_read_prph(trans, OSC_CLK);
-		iwl_read_prph(trans, OSC_CLK);
-		iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
-		iwl_read_prph(trans, OSC_CLK);
-		iwl_read_prph(trans, OSC_CLK);
+		iwl_trans_read_prph(trans, OSC_CLK);
+		iwl_trans_read_prph(trans, OSC_CLK);
+		iwl_trans_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
+		iwl_trans_read_prph(trans, OSC_CLK);
+		iwl_trans_read_prph(trans, OSC_CLK);
 	}
 
 	/*
@@ -301,17 +301,17 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
 	 * bits already set by default in "CLK_CTRL_REG" after reset.
 	 */
 	if (!trans->mac_cfg->base->apmg_not_supported) {
-		iwl_write_prph(trans, APMG_CLK_EN_REG,
-			       APMG_CLK_VAL_DMA_CLK_RQT);
+		iwl_trans_write_prph(trans, APMG_CLK_EN_REG,
+				     APMG_CLK_VAL_DMA_CLK_RQT);
 		udelay(20);
 
 		/* Disable L1-Active */
-		iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
-				  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
+		iwl_trans_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
+					APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 
 		/* Clear the interrupt in APMG if the NIC is in RFKILL */
-		iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
-			       APMG_RTC_INT_STT_RFKILL);
+		iwl_trans_write_prph(trans, APMG_RTC_INT_STT_REG,
+				     APMG_RTC_INT_STT_RFKILL);
 	}
 
 	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
@@ -334,8 +334,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 	u32 dl_cfg_reg;
 
 	/* Force XTAL ON */
-	iwl_trans_set_bit(trans, CSR_GP_CNTRL,
-			  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
+	iwl_pcie_set_bit(trans, CSR_GP_CNTRL,
+			 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 
 	ret = iwl_trans_pcie_sw_reset(trans, true);
 
@@ -344,8 +344,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 
 	if (WARN_ON(ret)) {
 		/* Release XTAL ON request */
-		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
-				    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
+		iwl_pcie_clear_bit(trans, CSR_GP_CNTRL,
+				   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 		return;
 	}
 
@@ -353,8 +353,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 	 * Clear "disable persistence" to avoid LP XTAL resetting when
 	 * SHRD_HW_RST is applied in S3.
 	 */
-	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
-				    APMG_PCIDEV_STT_VAL_PERSIST_DIS);
+	iwl_trans_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
+				  APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 
 	/*
 	 * Force APMG XTAL to be active to prevent its disabling by HW
@@ -386,22 +386,22 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 	 * Enable persistence mode to avoid LP XTAL resetting when
 	 * SHRD_HW_RST is applied in S3.
 	 */
-	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-		    CSR_HW_IF_CONFIG_REG_PERSISTENCE);
+	iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+			  CSR_HW_IF_CONFIG_REG_PERSISTENCE);
 
 	/*
 	 * Clear "initialization complete" bit to move adapter from
 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 	 */
-	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+	iwl_trans_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 
 	/* Activates XTAL resources monitor */
-	iwl_trans_set_bit(trans, CSR_MONITOR_CFG_REG,
-			  CSR_MONITOR_XTAL_RESOURCES);
+	iwl_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
+			 CSR_MONITOR_XTAL_RESOURCES);
 
 	/* Release XTAL ON request */
-	iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
+	iwl_pcie_clear_bit(trans, CSR_GP_CNTRL,
+			   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 	udelay(10);
 
 	/* Release APMG XTAL */
@@ -417,18 +417,18 @@ void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 	/* stop device's busmaster DMA activity */
 
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
-		iwl_set_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
+		iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+				  CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
 
-		ret = iwl_poll_bits(trans, CSR_GP_CNTRL,
-				    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
-				    100);
+		ret = iwl_trans_poll_bits(trans, CSR_GP_CNTRL,
+					  CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
+					  100);
 		usleep_range(10000, 20000);
 	} else {
-		iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
+		iwl_trans_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 
-		ret = iwl_poll_bits(trans, CSR_RESET,
-				    CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
+		ret = iwl_trans_poll_bits(trans, CSR_RESET,
+					  CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 	}
 
 	if (ret)
@@ -447,18 +447,18 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 
 		/* inform ME that we are leaving */
 		if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000)
-			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
-					  APMG_PCIDEV_STT_VAL_WAKE_ME);
+			iwl_trans_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
+						APMG_PCIDEV_STT_VAL_WAKE_ME);
 		else if (trans->mac_cfg->device_family >=
 			 IWL_DEVICE_FAMILY_8000) {
-			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
-				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
-			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-				    CSR_HW_IF_CONFIG_REG_WAKE_ME |
-				    CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
+			iwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+					  CSR_RESET_LINK_PWR_MGMT_DISABLED);
+			iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+					  CSR_HW_IF_CONFIG_REG_WAKE_ME |
+					  CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
 			mdelay(1);
-			iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
-				      CSR_RESET_LINK_PWR_MGMT_DISABLED);
+			iwl_trans_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+					    CSR_RESET_LINK_PWR_MGMT_DISABLED);
 		}
 		mdelay(5);
 	}
@@ -479,7 +479,7 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 	 * Clear "initialization complete" bit to move adapter from
 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 	 */
-	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+	iwl_trans_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 }
 
 static int iwl_pcie_nic_init(struct iwl_trans *trans)
@@ -512,7 +512,7 @@ static int iwl_pcie_nic_init(struct iwl_trans *trans)
 
 	if (trans->mac_cfg->base->shadow_reg_enable) {
 		/* enable shadow regs in HW */
-		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
+		iwl_trans_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 	}
 
@@ -525,16 +525,16 @@ static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 {
 	int ret;
 
-	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-		    CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);
+	iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+			  CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);
 
 	/* See if we got it */
-	ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
-			    CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
-			    HW_READY_TIMEOUT);
+	ret = iwl_trans_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
+				  CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
+				  HW_READY_TIMEOUT);
 
 	if (!ret)
-		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
+		iwl_trans_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 
 	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret ? " not" : "");
 	return ret;
@@ -555,16 +555,16 @@ int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 		return 0;
 	}
 
-	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
-		    CSR_RESET_LINK_PWR_MGMT_DISABLED);
+	iwl_trans_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
+			  CSR_RESET_LINK_PWR_MGMT_DISABLED);
 	usleep_range(1000, 2000);
 
 	for (iter = 0; iter < 10; iter++) {
 		int t = 0;
 
 		/* If HW is not ready, prepare the conditions to check again */
-		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-			    CSR_HW_IF_CONFIG_REG_WAKE_ME);
+		iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+				  CSR_HW_IF_CONFIG_REG_WAKE_ME);
 
 		do {
 			ret = iwl_pcie_set_hw_ready(trans);
@@ -603,28 +603,28 @@ static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 					    u32 dst_addr, dma_addr_t phy_addr,
 					    u32 byte_cnt)
 {
-	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
-		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
+	iwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
+			       FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 
-	iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
-		    dst_addr);
+	iwl_trans_pcie_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
+			       dst_addr);
 
-	iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
-		    phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
+	iwl_trans_pcie_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
+			       phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 
-	iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
-		    (iwl_get_dma_hi_addr(phy_addr)
-			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
+	iwl_trans_pcie_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
+			       (iwl_get_dma_hi_addr(phy_addr)
+				<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 
-	iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
-		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
-		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
-		    FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
+	iwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
+			       BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
+			       BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
+			       FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 
-	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
-		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
-		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
-		    FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
+	iwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
+			       FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
+			       FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
+			       FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 }
 
 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
@@ -688,16 +688,16 @@ static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 			extended_addr = true;
 
 		if (extended_addr)
-			iwl_set_bits_prph(trans, LMPM_CHICK,
-					  LMPM_CHICK_EXTENDED_ADDR_SPACE);
+			iwl_trans_set_bits_prph(trans, LMPM_CHICK,
+						LMPM_CHICK_EXTENDED_ADDR_SPACE);
 
 		memcpy(v_addr, (const u8 *)section->data + offset, copy_size);
 		ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 						   copy_size);
 
 		if (extended_addr)
-			iwl_clear_bits_prph(trans, LMPM_CHICK,
-					    LMPM_CHICK_EXTENDED_ADDR_SPACE);
+			iwl_trans_clear_bits_prph(trans, LMPM_CHICK,
+						  LMPM_CHICK_EXTENDED_ADDR_SPACE);
 
 		if (ret) {
 			IWL_ERR(trans,
@@ -751,9 +751,9 @@ static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 			return ret;
 
 		/* Notify ucode of loaded section number and status */
-		val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
+		val = iwl_pcie_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 		val = val | (sec_num << shift_param);
-		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
+		iwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 
 		sec_num = (sec_num << 1) | 0x1;
 	}
@@ -764,18 +764,18 @@ static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 
 	if (trans->mac_cfg->gen2) {
 		if (cpu == 1)
-			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
-				       0xFFFF);
+			iwl_trans_write_prph(trans, UREG_UCODE_LOAD_STATUS,
+					     0xFFFF);
 		else
-			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
-				       0xFFFFFFFF);
+			iwl_trans_write_prph(trans, UREG_UCODE_LOAD_STATUS,
+					     0xFFFFFFFF);
 	} else {
 		if (cpu == 1)
-			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
-					   0xFFFF);
+			iwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS,
+						 0xFFFF);
 		else
-			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
-					   0xFFFFFFFF);
+			iwl_trans_write_direct32(trans, FH_UCODE_LOAD_STATUS,
+						 0xFFFFFFFF);
 	}
 
 	return 0;
@@ -836,8 +836,8 @@ static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
 	    IWL_FW_INI_LOCATION_SRAM_PATH) {
 		IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
 		/* set sram monitor by enabling bit 7 */
-		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-			    CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
+		iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+				  CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
 
 		return;
 	}
@@ -852,11 +852,11 @@ static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
 	IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
 		     alloc_id);
 
-	iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
-			    frag->physical >> MON_BUFF_SHIFT_VER2);
-	iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
-			    (frag->physical + frag->size - 256) >>
-			    MON_BUFF_SHIFT_VER2);
+	iwl_trans_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
+				  frag->physical >> MON_BUFF_SHIFT_VER2);
+	iwl_trans_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
+				  (frag->physical + frag->size - 256) >>
+				  MON_BUFF_SHIFT_VER2);
 }
 
 void iwl_pcie_apply_destination(struct iwl_trans *trans)
@@ -884,25 +884,25 @@ void iwl_pcie_apply_destination(struct iwl_trans *trans)
 
 		switch (dest->reg_ops[i].op) {
 		case CSR_ASSIGN:
-			iwl_write32(trans, addr, val);
+			iwl_trans_pcie_write32(trans, addr, val);
 			break;
 		case CSR_SETBIT:
-			iwl_set_bit(trans, addr, BIT(val));
+			iwl_trans_set_bit(trans, addr, BIT(val));
 			break;
 		case CSR_CLEARBIT:
-			iwl_clear_bit(trans, addr, BIT(val));
+			iwl_trans_clear_bit(trans, addr, BIT(val));
 			break;
 		case PRPH_ASSIGN:
-			iwl_write_prph(trans, addr, val);
+			iwl_trans_write_prph(trans, addr, val);
 			break;
 		case PRPH_SETBIT:
-			iwl_set_bits_prph(trans, addr, BIT(val));
+			iwl_trans_set_bits_prph(trans, addr, BIT(val));
 			break;
 		case PRPH_CLEARBIT:
-			iwl_clear_bits_prph(trans, addr, BIT(val));
+			iwl_trans_clear_bits_prph(trans, addr, BIT(val));
 			break;
 		case PRPH_BLOCKBIT:
-			if (iwl_read_prph(trans, addr) & BIT(val)) {
+			if (iwl_trans_read_prph(trans, addr) & BIT(val)) {
 				IWL_ERR(trans,
 					"BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 					val, addr);
@@ -918,16 +918,16 @@ void iwl_pcie_apply_destination(struct iwl_trans *trans)
 
 monitor:
 	if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
-		iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
-			       fw_mon->physical >> dest->base_shift);
+		iwl_trans_write_prph(trans, le32_to_cpu(dest->base_reg),
+				     fw_mon->physical >> dest->base_shift);
 		if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
-			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
-				       (fw_mon->physical + fw_mon->size -
-					256) >> dest->end_shift);
+			iwl_trans_write_prph(trans, le32_to_cpu(dest->end_reg),
+					     (fw_mon->physical + fw_mon->size -
+					      256) >> dest->end_shift);
 		else
-			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
-				       (fw_mon->physical + fw_mon->size) >>
-				       dest->end_shift);
+			iwl_trans_write_prph(trans, le32_to_cpu(dest->end_reg),
+					     (fw_mon->physical + fw_mon->size) >>
+					     dest->end_shift);
 	}
 }
 
@@ -947,9 +947,9 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 
 	if (image->is_dual_cpus) {
 		/* set CPU2 header address */
-		iwl_write_prph(trans,
-			       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
-			       LMPM_SECURE_CPU2_HDR_MEM_SPACE);
+		iwl_trans_write_prph(trans,
+				     LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
+				     LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 
 		/* load to FW the binary sections of CPU2 */
 		ret = iwl_pcie_load_cpu_sections(trans, image, 2,
@@ -964,7 +964,7 @@ static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 	iwl_enable_interrupts(trans);
 
 	/* release CPU reset */
-	iwl_write32(trans, CSR_RESET, 0);
+	iwl_trans_pcie_write32(trans, CSR_RESET, 0);
 
 	return 0;
 }
@@ -982,18 +982,18 @@ static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 		iwl_pcie_apply_destination(trans);
 
 	IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
-			iwl_read_prph(trans, WFPM_GP2));
+			iwl_trans_read_prph(trans, WFPM_GP2));
 
 	/*
 	 * Set default value. On resume reading the values that were
 	 * zeored can provide debug data on the resume flow.
 	 * This is for debugging only and has no functional impact.
 	 */
-	iwl_write_prph(trans, WFPM_GP2, 0x01010101);
+	iwl_trans_write_prph(trans, WFPM_GP2, 0x01010101);
 
 	/* configure the ucode to be ready to get the secured image */
 	/* release CPU reset */
-	iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
+	iwl_trans_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 
 	/* load to FW the binary Secured sections of CPU1 */
 	ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
@@ -1079,9 +1079,9 @@ static void iwl_pcie_map_list(struct iwl_trans *trans,
 	int i;
 
 	for (i = 0; i < arr_size; i++) {
-		iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
-		iwl_clear_bit(trans, causes[i].mask_reg,
-			      BIT(causes[i].bit));
+		iwl_trans_pcie_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
+		iwl_trans_clear_bit(trans, causes[i].mask_reg,
+				    BIT(causes[i].bit));
 	}
 }
 
@@ -1119,19 +1119,19 @@ static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
 	 */
 	val = BIT(MSIX_FH_INT_CAUSES_Q(0));
 	for (idx = 1; idx < trans->info.num_rxqs; idx++) {
-		iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
-			   MSIX_FH_INT_CAUSES_Q(idx - offset));
+		iwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(idx),
+				      MSIX_FH_INT_CAUSES_Q(idx - offset));
 		val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
 	}
-	iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
+	iwl_trans_pcie_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
 
 	val = MSIX_FH_INT_CAUSES_Q(0);
 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
 		val |= MSIX_NON_AUTO_CLEAR_CAUSE;
-	iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
+	iwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(0), val);
 
 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
-		iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
+		iwl_trans_pcie_write8(trans, CSR_MSIX_RX_IVAR(1), val);
 }
 
 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
@@ -1141,8 +1141,8 @@ void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
 	if (!trans_pcie->msix_enabled) {
 		if (trans->mac_cfg->mq_rx_supported &&
 		    test_bit(STATUS_DEVICE_ENABLED, &trans->status))
-			iwl_write_umac_prph(trans, UREG_CHICK,
-					    UREG_CHICK_MSI_ENABLE);
+			iwl_trans_write_umac_prph(trans, UREG_CHICK,
+						  UREG_CHICK_MSI_ENABLE);
 		return;
 	}
 	/*
@@ -1151,7 +1151,7 @@ void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
 	 * prph.
 	 */
 	if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
-		iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
+		iwl_trans_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
 
 	/*
 	 * Each cause from the causes list above and the RX causes is
@@ -1174,9 +1174,9 @@ static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
 	if (!trans_pcie->msix_enabled)
 		return;
 
-	trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
+	trans_pcie->fh_init_mask = ~iwl_trans_pcie_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
 	trans_pcie->fh_mask = trans_pcie->fh_init_mask;
-	trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
+	trans_pcie->hw_init_mask = ~iwl_trans_pcie_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
 	trans_pcie->hw_mask = trans_pcie->hw_init_mask;
 }
 
@@ -1215,19 +1215,19 @@ static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq)
 
 		/* Power-down device's busmaster DMA clocks */
 		if (!trans->mac_cfg->base->apmg_not_supported) {
-			iwl_write_prph(trans, APMG_CLK_DIS_REG,
-				       APMG_CLK_VAL_DMA_CLK_RQT);
+			iwl_trans_write_prph(trans, APMG_CLK_DIS_REG,
+					     APMG_CLK_VAL_DMA_CLK_RQT);
 			udelay(5);
 		}
 	}
 
 	/* Make sure (redundant) we've released our request to stay awake */
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
 	else
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 
 	/* Stop the device, and put it in low power state */
 	iwl_pcie_apm_stop(trans, false);
@@ -1288,6 +1288,10 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 	bool hw_rfkill;
 	int ret;
 
+	if (trans->mac_cfg->gen2)
+		return iwl_trans_pcie_gen2_start_fw(trans, fw, img,
+						    run_in_rfkill);
+
 	/* This may fail if AMT took ownership of the device */
 	if (iwl_pcie_prepare_card_hw(trans)) {
 		IWL_WARN(trans, "Exit HW not ready\n");
@@ -1296,7 +1300,7 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 
 	iwl_enable_rfkill_int(trans);
 
-	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
+	iwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);
 
 	/*
 	 * We enabled the RF-Kill interrupt and the handler may very
@@ -1326,12 +1330,12 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 	}
 
 	/* make sure rfkill handshake bits are cleared */
-	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
-	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
-		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
+	iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
+	iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR,
+			       CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 
 	/* clear (again), then enable host interrupts */
-	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
+	iwl_trans_pcie_write32(trans, CSR_INT, 0xFFFFFFFF);
 
 	ret = iwl_pcie_nic_init(trans);
 	if (ret) {
@@ -1349,8 +1353,8 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 	iwl_enable_fw_load_int(trans);
 
 	/* really make sure rfkill handshake bits are cleared */
-	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
-	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
+	iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
+	iwl_trans_pcie_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 
 	/* Load the given image to the HW */
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
@@ -1370,6 +1374,11 @@ int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 
 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
 {
+	if (trans->mac_cfg->gen2) {
+		iwl_trans_pcie_gen2_fw_alive(trans);
+		return;
+	}
+
 	iwl_pcie_reset_ict(trans);
 	iwl_pcie_tx_start(trans);
 }
@@ -1408,6 +1417,11 @@ void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 	bool was_in_rfkill;
 
+	if (trans->mac_cfg->gen2) {
+		iwl_trans_pcie_gen2_stop_device(trans);
+		return;
+	}
+
 	iwl_op_mode_time_point(trans->op_mode,
 			       IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
 			       NULL);
@@ -1444,15 +1458,15 @@ static void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
 	iwl_pcie_synchronize_irqs(trans);
 
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
 	} else {
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 	}
 
 	if (reset) {
@@ -1478,13 +1492,13 @@ static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)
 	trans_pcie->sx_state = IWL_SX_WAITING;
 
 	if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
-		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
-				    suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :
-					      UREG_DOORBELL_TO_ISR6_RESUME);
+		iwl_trans_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
+					  suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :
+					  UREG_DOORBELL_TO_ISR6_RESUME);
 	else
-		iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,
-			    suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :
-				      CSR_IPC_SLEEP_CONTROL_RESUME);
+		iwl_trans_pcie_write32(trans, CSR_IPC_SLEEP_CONTROL,
+				       suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :
+						 CSR_IPC_SLEEP_CONTROL_RESUME);
 
 	ret = wait_event_timeout(trans_pcie->sx_waitq,
 				 trans_pcie->sx_state != IWL_SX_WAITING,
@@ -1515,8 +1529,8 @@ int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool reset)
 
 	if (!reset)
 		/* Enable persistence mode to avoid reset */
-		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
-			    CSR_HW_IF_CONFIG_REG_PERSISTENCE);
+		iwl_trans_set_bit(trans, CSR_HW_IF_CONFIG_REG,
+				  CSR_HW_IF_CONFIG_REG_PERSISTENCE);
 
 	ret = iwl_pcie_d3_handshake(trans, true);
 	if (ret)
@@ -1535,11 +1549,11 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 	int ret;
 
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
-		iwl_set_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
+		iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+				  CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
 	else
-		iwl_set_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+		iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+				  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 
 	ret = iwl_trans_activate_nic(trans);
 	if (ret) {
@@ -1563,8 +1577,8 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 	iwl_pcie_set_pwr(trans, false);
 
 	if (!reset) {
-		iwl_clear_bit(trans, CSR_GP_CNTRL,
-			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
+				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 	} else {
 		iwl_trans_pcie_tx_reset(trans);
 
@@ -1577,9 +1591,9 @@ int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 	}
 
 	IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
-			iwl_read_umac_prph(trans, WFPM_GP2));
+			iwl_trans_read_umac_prph(trans, WFPM_GP2));
 
-	val = iwl_read32(trans, CSR_RESET);
+	val = iwl_trans_pcie_read32(trans, CSR_RESET);
 	if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 		IWL_INFO(trans, "Device was reset during suspend\n");
 		trans->state = IWL_TRANS_NO_FW;
@@ -1745,17 +1759,17 @@ static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
 		return 0;
 	}
 
-	hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
+	hpm = iwl_trans_read_umac_prph_no_grab(trans, HPM_DEBUG);
 	if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) {
-		u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
+		u32 wprot_val = iwl_trans_read_umac_prph_no_grab(trans, wprot);
 
 		if (wprot_val & PREG_WFPM_ACCESS) {
 			IWL_ERR(trans,
 				"Error, can not clear persistence bit\n");
 			return -EPERM;
 		}
-		iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
-					    hpm & ~PERSISTENCE_BIT);
+		iwl_pcie_write_umac_prph_no_grab(trans, HPM_DEBUG,
+						 hpm & ~PERSISTENCE_BIT);
 	}
 
 	return 0;
@@ -1769,15 +1783,15 @@ static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
 	if (ret < 0)
 		return ret;
 
-	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
-			  HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
+	iwl_trans_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
+				HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
 	udelay(20);
-	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
-			  HPM_HIPM_GEN_CFG_CR_PG_EN |
-			  HPM_HIPM_GEN_CFG_CR_SLP_EN);
+	iwl_trans_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
+				HPM_HIPM_GEN_CFG_CR_PG_EN |
+				HPM_HIPM_GEN_CFG_CR_SLP_EN);
 	udelay(20);
-	iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
-			    HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
+	iwl_trans_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
+				  HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
 
 	return iwl_trans_pcie_sw_reset(trans, true);
 }
@@ -1846,6 +1860,11 @@ void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
 {
 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 
+	if (trans->mac_cfg->gen2) {
+		iwl_trans_pcie_gen2_op_mode_leave(trans);
+		return;
+	}
+
 	mutex_lock(&trans_pcie->mutex);
 
 	/* disable interrupts - don't enable HW RF kill interrupt */
@@ -1864,17 +1883,22 @@ void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
 
 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 {
+	trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val);
 	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 }
 
 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 {
+	trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val);
 	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 }
 
 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 {
-	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
+	u32 val = readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
+
+	trace_iwlwifi_dev_ioread32(trans->dev, ofs, val);
+	return val;
 }
 
 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
@@ -1888,16 +1912,20 @@ static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 {
 	u32 mask = iwl_trans_pcie_prph_msk(trans);
+	u32 val;
 
 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 			       ((reg & mask) | (3 << 24)));
-	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
+	val = iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
+	trace_iwlwifi_dev_ioread_prph32(trans->dev, reg, val);
+	return val;
 }
 
-void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
+void iwl_pcie_write_prph_no_grab(struct iwl_trans *trans, u32 addr, u32 val)
 {
 	u32 mask = iwl_trans_pcie_prph_msk(trans);
 
+	trace_iwlwifi_dev_iowrite_prph32(trans->dev, addr, val);
 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 			       ((addr & mask) | (3 << 24)));
 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
@@ -2265,7 +2293,7 @@ static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
 	module_put(THIS_MODULE);
 }
 
-void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)
+static void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)
 {
 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 	struct iwl_trans_pcie_removal *removal;
@@ -2320,7 +2348,6 @@ void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode)
 	pci_dev_get(removal->pdev);
 	schedule_work(&removal->work);
 }
-EXPORT_SYMBOL(iwl_trans_pcie_reset);
 
 /*
  * This version doesn't disable BHs but rather assumes they're
@@ -2350,7 +2377,7 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
 	}
 
 	/* this bit wakes up the NIC */
-	iwl_trans_set_bit(trans, CSR_GP_CNTRL, write);
+	iwl_pcie_set_bit(trans, CSR_GP_CNTRL, write);
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 		udelay(2);
 
@@ -2374,9 +2401,9 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
 	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
 	 * and do not save/restore SRAM when power cycling.
 	 */
-	ret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);
+	ret = iwl_trans_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);
 	if (unlikely(ret)) {
-		u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
+		u32 cntrl = iwl_trans_pcie_read32(trans, CSR_GP_CNTRL);
 
 		if (silent) {
 			spin_unlock(&trans_pcie->reg_lock);
@@ -2393,8 +2420,8 @@ bool _iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
 			iwl_trans_pcie_reset(trans,
 					     IWL_RESET_MODE_REMOVE_ONLY);
 		else
-			iwl_write32(trans, CSR_RESET,
-				    CSR_RESET_REG_FLAG_FORCE_NMI);
+			iwl_trans_pcie_write32(trans, CSR_RESET,
+					       CSR_RESET_REG_FLAG_FORCE_NMI);
 
 		spin_unlock(&trans_pcie->reg_lock);
 		return false;
@@ -2443,11 +2470,11 @@ void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
 	if (trans_pcie->cmd_hold_nic_awake)
 		goto out;
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
-		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
-				    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
+		iwl_pcie_clear_bit(trans, CSR_GP_CNTRL,
+				   CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
 	else
-		iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
-				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+		iwl_pcie_clear_bit(trans, CSR_GP_CNTRL,
+				   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 	/*
 	 * Above we read the CSR_GP_CNTRL register, which will flush
 	 * any previous writes, but we need the write that clears the
@@ -2472,12 +2499,12 @@ int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
 		bool resched = false;
 
 		if (iwl_trans_grab_nic_access(trans)) {
-			iwl_write32(trans, HBUS_TARG_MEM_RADDR,
-				    addr + 4 * offs);
+			iwl_trans_pcie_write32(trans, HBUS_TARG_MEM_RADDR,
+					       addr + 4 * offs);
 
 			while (offs < dwords) {
-				vals[offs] = iwl_read32(trans,
-							HBUS_TARG_MEM_RDAT);
+				vals[offs] = iwl_trans_pcie_read32(trans,
+								   HBUS_TARG_MEM_RDAT);
 
 				if (iwl_trans_is_hw_error_value(vals[offs]))
 					num_consec_hw_errors++;
@@ -2524,11 +2551,11 @@ int iwl_trans_pcie_read_mem_no_grab(struct iwl_trans *trans, u32 addr,
 		unsigned long end = jiffies + HZ / 2;
 		bool resched = false;
 
-		iwl_write32(trans, HBUS_TARG_MEM_RADDR,
-			    addr + 4 * offs);
+		iwl_trans_pcie_write32(trans, HBUS_TARG_MEM_RADDR,
+				       addr + 4 * offs);
 
 		while (offs < dwords) {
-			vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
+			vals[offs] = iwl_trans_pcie_read32(trans, HBUS_TARG_MEM_RDAT);
 
 			if (iwl_trans_is_hw_error_value(vals[offs]))
 				num_consec_hw_errors++;
@@ -2672,7 +2699,7 @@ void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 
 	spin_lock_bh(&trans_pcie->reg_lock);
-	_iwl_trans_set_bits_mask(trans, reg, mask, value);
+	iwl_pcie_set_bits_mask(trans, reg, mask, value);
 	spin_unlock_bh(&trans_pcie->reg_lock);
 }
 
@@ -2745,7 +2772,7 @@ void iwl_pcie_dump_csr(struct iwl_trans *trans)
 	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
 		IWL_ERR(trans, "  %25s: 0X%08x\n",
 			get_csr_string(csr_tbl[i]),
-			iwl_read32(trans, csr_tbl[i]));
+			iwl_trans_pcie_read32(trans, csr_tbl[i]));
 	}
 }
 
@@ -3021,7 +3048,7 @@ static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
 
 	pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
 			trans_pcie->debug_rfkill,
-			!(iwl_read32(trans, CSR_GP_CNTRL) &
+			!(iwl_trans_pcie_read32(trans, CSR_GP_CNTRL) &
 				CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
 
 	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
@@ -3228,8 +3255,8 @@ static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
 		     i += sizeof(u32))
 			*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
 	else
-		for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
-		     i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
+		for (i = iwl_trans_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
+		     i < iwl_trans_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
 		     i += sizeof(u32))
 			*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
 								      i));
@@ -3253,11 +3280,11 @@ iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
 	if (!iwl_trans_grab_nic_access(trans))
 		return 0;
 
-	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
+	iwl_pcie_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
 	for (i = 0; i < buf_size_in_dwords; i++)
-		buffer[i] = iwl_read_umac_prph_no_grab(trans,
-						       MON_DMARB_RD_DATA_ADDR);
-	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
+		buffer[i] = iwl_trans_read_umac_prph_no_grab(trans,
+							     MON_DMARB_RD_DATA_ADDR);
+	iwl_pcie_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
 
 	iwl_trans_release_nic_access(trans);
 
@@ -3285,14 +3312,14 @@ iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
 		wrap_cnt = MON_BUFF_CYCLE_CNT;
 	}
 
-	write_ptr_val = iwl_read_prph(trans, write_ptr);
+	write_ptr_val = iwl_trans_read_prph(trans, write_ptr);
 	fw_mon_data->fw_mon_cycle_cnt =
-		cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
+		cpu_to_le32(iwl_trans_read_prph(trans, wrap_cnt));
 	fw_mon_data->fw_mon_base_ptr =
-		cpu_to_le32(iwl_read_prph(trans, base));
+		cpu_to_le32(iwl_trans_read_prph(trans, base));
 	if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
 		fw_mon_data->fw_mon_base_high_ptr =
-			cpu_to_le32(iwl_read_prph(trans, base_high));
+			cpu_to_le32(iwl_trans_read_prph(trans, base_high));
 		write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
 		/* convert wrtPtr to DWs, to align with all HWs */
 		write_ptr_val >>= 2;
@@ -3330,13 +3357,13 @@ iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
 			 * shifting
 			 */
 			if (trans->dbg.dest_tlv->version) {
-				base = (iwl_read_prph(trans, base) &
+				base = (iwl_trans_read_prph(trans, base) &
 					IWL_LDBG_M2S_BUF_BA_MSK) <<
 				       trans->dbg.dest_tlv->base_shift;
 				base *= IWL_M2S_UNIT_SIZE;
 				base += trans->mac_cfg->base->smem_offset;
 			} else {
-				base = iwl_read_prph(trans, base) <<
+				base = iwl_trans_read_prph(trans, base) <<
 				       trans->dbg.dest_tlv->base_shift;
 			}
 
@@ -3371,7 +3398,7 @@ static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
 
 		if (trans->dbg.dest_tlv->version == 1) {
 			cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
-			cfg_reg = iwl_read_prph(trans, cfg_reg);
+			cfg_reg = iwl_trans_read_prph(trans, cfg_reg);
 			base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
 				trans->dbg.dest_tlv->base_shift;
 			base *= IWL_M2S_UNIT_SIZE;
@@ -3385,9 +3412,9 @@ static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
 			base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
 			end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
 
-			base = iwl_read_prph(trans, base) <<
+			base = iwl_trans_read_prph(trans, base) <<
 			       trans->dbg.dest_tlv->base_shift;
-			end = iwl_read_prph(trans, end) <<
+			end = iwl_trans_read_prph(trans, end) <<
 			      trans->dbg.dest_tlv->end_shift;
 
 			/* Make "end" point to the actual end */
@@ -3445,8 +3472,8 @@ iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,
 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
 		if (trans->mac_cfg->gen2)
 			len += sizeof(*data) +
-			       (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
-				iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
+			       (iwl_trans_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
+				iwl_trans_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
 		else
 			len += sizeof(*data) +
 			       (FH_MEM_UPPER_BOUND -
@@ -3592,12 +3619,12 @@ void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
 
 	iwl_trans_force_nmi(trans);
 	while (time_after(timeout, jiffies)) {
-		u32 inta_hw = iwl_read32(trans, inta_addr);
+		u32 inta_hw = iwl_trans_pcie_read32(trans, inta_addr);
 
 		/* Error detected by uCode */
 		if (inta_hw & sw_err_bit) {
 			/* Clear causes register */
-			iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
+			iwl_trans_pcie_write32(trans, inta_addr, inta_hw & sw_err_bit);
 			break;
 		}
 
@@ -3651,6 +3678,66 @@ static int iwl_trans_pcie_alloc_txcmd_pool(struct iwl_trans *trans)
 	return 0;
 }
 
+const struct iwl_trans_ops iwl_trans_pcie_ops = {
+	.op_mode_enter = iwl_trans_pcie_op_mode_enter,
+	.start_hw = iwl_trans_pcie_start_hw,
+	.op_mode_leave = iwl_trans_pcie_op_mode_leave,
+
+	.send_cmd = iwl_trans_pcie_send_hcmd,
+	.alloc_tx_cmd = iwl_pcie_alloc_tx_cmd,
+	.free_tx_cmd = iwl_pcie_free_tx_cmd,
+
+	.write8 = iwl_trans_pcie_write8,
+	.write32 = iwl_trans_pcie_write32,
+	.read32 = iwl_trans_pcie_read32,
+	.read_prph = iwl_trans_pcie_read_prph,
+	.write_prph = iwl_pcie_write_prph_no_grab,
+	.read_mem = iwl_trans_pcie_read_mem,
+	.read_mem_no_grab = iwl_trans_pcie_read_mem_no_grab,
+	.set_bits_mask = iwl_trans_pcie_set_bits_mask,
+	.read_config32 = iwl_trans_pcie_read_config32,
+	.grab_nic_access = iwl_trans_pcie_grab_nic_access,
+	.release_nic_access = iwl_trans_pcie_release_nic_access,
+	.resched_with_nic_access = iwl_trans_pcie_resched_with_nic_access,
+
+	.sw_reset = iwl_trans_pcie_sw_reset,
+	.reset = iwl_trans_pcie_reset,
+	.fw_reset_handshake = iwl_trans_pcie_fw_reset_handshake,
+
+	.dump_data = iwl_trans_pcie_dump_data,
+	.d3_suspend = iwl_trans_pcie_d3_suspend,
+	.d3_resume = iwl_trans_pcie_d3_resume,
+
+	.sync_nmi = iwl_trans_pcie_sync_nmi,
+	.write_imr_mem = iwl_trans_pcie_copy_imr,
+
+	.fw_alive = iwl_trans_pcie_fw_alive,
+	.start_fw = iwl_trans_pcie_start_fw,
+	.stop_device = iwl_trans_pcie_stop_device,
+
+	.tx = iwl_trans_pcie_tx,
+	.reclaim = iwl_pcie_reclaim,
+	.txq_disable = iwl_trans_pcie_txq_disable,
+	.txq_enable = iwl_trans_pcie_txq_enable,
+	.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
+	.wait_txqs_empty = iwl_trans_pcie_wait_txqs_empty,
+	.freeze_txq_timer = iwl_pcie_freeze_txq_timer,
+	.txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
+	.set_q_ptrs = iwl_pcie_set_q_ptrs,
+	.txq_alloc = iwl_txq_dyn_alloc,
+	.txq_free = iwl_txq_dyn_free,
+	.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
+
+	.load_pnvm = iwl_trans_pcie_ctx_info_v2_load_pnvm,
+	.set_pnvm = iwl_trans_pcie_ctx_info_v2_set_pnvm,
+	.load_reduce_power = iwl_trans_pcie_ctx_info_v2_load_reduce_power,
+	.set_reduce_power = iwl_trans_pcie_ctx_info_v2_set_reduce_power,
+
+	.is_pm_supported = iwl_pcie_gen1_is_pm_supported,
+	.is_ltr_enabled = iwl_pcie_is_ltr_enabled,
+	.activate_nic = iwl_pcie_activate_nic,
+};
+
 static struct iwl_trans *
 iwl_trans_pcie_alloc(struct pci_dev *pdev,
 		     const struct iwl_mac_cfg *mac_cfg,
@@ -3662,7 +3749,7 @@ iwl_trans_pcie_alloc(struct pci_dev *pdev,
 	int ret, addr_size;
 
 	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev,
-				mac_cfg);
+				&iwl_trans_pcie_ops, mac_cfg);
 	if (!trans)
 		return ERR_PTR(-ENOMEM);
 
@@ -3851,19 +3938,19 @@ iwl_trans_pcie_alloc(struct pci_dev *pdev,
 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
 				u32 dst_addr, u64 src_addr, u32 byte_cnt)
 {
-	iwl_write_prph(trans, IMR_UREG_CHICK,
-		       iwl_read_prph(trans, IMR_UREG_CHICK) |
-		       IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);
-	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
-	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
-		       (u32)(src_addr & 0xFFFFFFFF));
-	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
-		       iwl_get_dma_hi_addr(src_addr));
-	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
-	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
-		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |
-		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |
-		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);
+	iwl_trans_write_prph(trans, IMR_UREG_CHICK,
+			     iwl_trans_read_prph(trans, IMR_UREG_CHICK) |
+			     IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);
+	iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
+	iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
+			     (u32)(src_addr & 0xFFFFFFFF));
+	iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
+			     iwl_get_dma_hi_addr(src_addr));
+	iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
+	iwl_trans_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
+			     IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |
+			     IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |
+			     IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);
 }
 
 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
@@ -3905,8 +3992,8 @@ static void get_crf_id(struct iwl_trans *iwl_trans,
 	/* wait until the device is ready to access the prph registers */
 	if (iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_DR ||
 	    iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_SC) {
-		u32 req = iwl_read_umac_prph_no_grab(iwl_trans,
-						     WFPM_RSRCS_4PHS_REQ_STTS);
+		u32 req = iwl_trans_read_umac_prph_no_grab(iwl_trans,
+							   WFPM_RSRCS_4PHS_REQ_STTS);
 		int ret;
 
 		if (!(req & RSRC_REQ_CNVR_TOP)) {
@@ -3916,26 +4003,26 @@ static void get_crf_id(struct iwl_trans *iwl_trans,
 			return;
 		}
 
-		ret = iwl_poll_umac_prph_bits_no_grab(iwl_trans,
-						      WFPM_RSRCS_4PHS_ACK_STTS,
-						      RSRC_ACK_CNVR_TOP,
-						      RSRC_ACK_CNVR_TOP,
-						      50 * 1000);
+		ret = iwl_pcie_poll_umac_prph_bits_no_grab(iwl_trans,
+							   WFPM_RSRCS_4PHS_ACK_STTS,
+							   RSRC_ACK_CNVR_TOP,
+							   RSRC_ACK_CNVR_TOP,
+							   50 * 1000);
 		if (ret < 0)
 			IWL_ERR(iwl_trans,
 				"WFPM_RSRCS_4PHS_ACK_STTS bit 6 is clear\n");
 	}
 
 	/* Enable access to peripheral registers */
-	val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);
+	val = iwl_trans_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);
 	val |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;
-	iwl_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val);
+	iwl_pcie_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val);
 
 	/* Read crf info */
-	info->hw_crf_id = iwl_read_prph_no_grab(iwl_trans, sd_reg_ver_addr);
+	info->hw_crf_id = iwl_trans_pcie_read_prph(iwl_trans, sd_reg_ver_addr);
 
 	/* Read cnv info */
-	info->hw_cnv_id = iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP);
+	info->hw_cnv_id = iwl_trans_pcie_read_prph(iwl_trans, CNVI_AUX_MISC_CHIP);
 
 	/* For BZ-W, take B step also when A step is indicated */
 	if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W)
@@ -3959,7 +4046,7 @@ static void get_crf_id(struct iwl_trans *iwl_trans,
 	}
 
 	/* Read cdb info (also contains the jacket info if needed in the future */
-	hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);
+	hw_wfpm_id = iwl_trans_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);
 
 	IWL_INFO(iwl_trans, "Detected crf-id 0x%x, cnv-id 0x%x wfpm id 0x%x\n",
 		 info->hw_crf_id, info->hw_cnv_id, hw_wfpm_id);
@@ -3976,8 +4063,8 @@ static int map_crf_id(struct iwl_trans *iwl_trans,
 	u32 val = info->hw_crf_id;
 	u32 step_id = REG_CRF_ID_STEP(val);
 	u32 slave_id = REG_CRF_ID_SLAVE(val);
-	u32 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans,
-						    WFPM_OTP_CFG1_ADDR);
+	u32 hw_wfpm_id = iwl_trans_read_umac_prph_no_grab(iwl_trans,
+							  WFPM_OTP_CFG1_ADDR);
 	u32 cdb_id_wfpm = WFPM_OTP_CFG1_IS_CDB(hw_wfpm_id);
 
 	/* Map between crf id to rf id */
@@ -4043,7 +4130,7 @@ static void iwl_pcie_recheck_me_status(struct work_struct *wk)
 							 me_recheck_wk.work);
 	u32 val;
 
-	val = iwl_read32(trans_pcie->trans, CSR_HW_IF_CONFIG_REG);
+	val = iwl_trans_pcie_read32(trans_pcie->trans, CSR_HW_IF_CONFIG_REG);
 	trans_pcie->me_present = !!(val & CSR_HW_IF_CONFIG_REG_IAMT_UP);
 }
 
@@ -4061,14 +4148,14 @@ static void iwl_pcie_check_me_status(struct iwl_trans *trans)
 	if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ)
 		return;
 
-	val = iwl_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1);
+	val = iwl_trans_pcie_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1);
 	if (val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_KNOWN) {
 		trans_pcie->me_present =
 			!!(val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_PRESENT);
 		return;
 	}
 
-	val = iwl_read32(trans, CSR_HW_IF_CONFIG_REG);
+	val = iwl_trans_pcie_read32(trans, CSR_HW_IF_CONFIG_REG);
 	if (val & (CSR_HW_IF_CONFIG_REG_ME_OWN |
 		   CSR_HW_IF_CONFIG_REG_IAMT_UP)) {
 		trans_pcie->me_present = 1;
@@ -4126,7 +4213,7 @@ int _iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent,
 		}
 	}
 
-	info.hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID);
+	info.hw_rf_id = iwl_trans_pcie_read32(iwl_trans, CSR_HW_RF_ID);
 
 	/*
 	 * The RF_ID is set to zero in blank OTP so read version to
@@ -4247,13 +4334,13 @@ int iwl_pcie_activate_nic(struct iwl_trans *trans)
 	 * D0U* --> D0A* (powered-up active) state.
 	 */
 	if (mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
-		iwl_set_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ |
-			    CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
+		iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+				  CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ |
+				  CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
 		poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
 	} else {
-		iwl_set_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+		iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+				  CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 		poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY;
 	}
 
@@ -4262,10 +4349,10 @@ int iwl_pcie_activate_nic(struct iwl_trans *trans)
 
 	/*
 	 * Wait for clock stabilization; once stabilized, access to
-	 * device-internal resources is supported, e.g. iwl_write_prph()
+	 * device-internal resources is supported, e.g. iwl_trans_write_prph()
 	 * and accesses to uCode SRAM.
 	 */
-	err = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);
+	err = iwl_trans_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);
 	if (err < 0) {
 		IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
 
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c
index 27f4973791d00..e6bebd37417f7 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c
@@ -1,14 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
  * Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2020, 2023-2025 Intel Corporation
+ * Copyright (C) 2018-2020, 2023-2026 Intel Corporation
  */
 #include <net/tso.h>
 #include <linux/tcp.h>
 
 #include "iwl-debug.h"
 #include "iwl-csr.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "internal.h"
 #include "fw/api/tx.h"
 #include "fw/api/commands.h"
@@ -711,7 +711,7 @@ static void iwl_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
 	 * if not in power-save mode, uCode will never sleep when we're
 	 * trying to tx (during RFKILL, we're not trying to tx).
 	 */
-	iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16));
+	iwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16));
 }
 
 int iwl_txq_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c
index 496435ea93ee8..0c29fb6b9ca71 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c
@@ -20,7 +20,7 @@
 #include "iwl-debug.h"
 #include "iwl-csr.h"
 #include "iwl-prph.h"
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "iwl-scd.h"
 #include "iwl-op-mode.h"
 #include "internal.h"
@@ -99,13 +99,13 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 		 * uCode will wake up, and interrupt us again, so next
 		 * time we'll skip this part.
 		 */
-		reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
+		reg = iwl_trans_pcie_read32(trans, CSR_UCODE_DRV_GP1);
 
 		if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 			IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 				       txq_id, reg);
-			iwl_set_bit(trans, CSR_GP_CNTRL,
-				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+			iwl_trans_set_bit(trans, CSR_GP_CNTRL,
+					  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 			txq->need_update = true;
 			return;
 		}
@@ -117,8 +117,8 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 	 */
 	IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
 	if (!txq->block)
-		iwl_write32(trans, HBUS_TARG_WRPTR,
-			    txq->write_ptr | (txq_id << 8));
+		iwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR,
+				       txq->write_ptr | (txq_id << 8));
 }
 
 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
@@ -205,8 +205,8 @@ static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
 	}
 
 	trans_pcie->cmd_hold_nic_awake = false;
-	iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
-			    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+	iwl_pcie_clear_bit(trans, CSR_GP_CNTRL,
+			   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 	spin_unlock(&trans_pcie->reg_lock);
 }
 
@@ -493,21 +493,21 @@ void iwl_pcie_tx_start(struct iwl_trans *trans)
 	       sizeof(trans_pcie->txqs.queue_used));
 
 	trans_pcie->scd_base_addr =
-		iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
+		iwl_trans_read_prph(trans, SCD_SRAM_BASE_ADDR);
 
 	/* reset context data, TX status and translation data */
 	iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 				   SCD_CONTEXT_MEM_LOWER_BOUND,
 			    NULL, clear_dwords);
 
-	iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
-		       trans_pcie->txqs.scd_bc_tbls.dma >> 10);
+	iwl_trans_write_prph(trans, SCD_DRAM_BASE_ADDR,
+			     trans_pcie->txqs.scd_bc_tbls.dma >> 10);
 
 	/* The chain extension of the SCD doesn't work well. This feature is
 	 * enabled by default by the HW, so we need to disable it manually.
 	 */
 	if (trans->mac_cfg->base->scd_chain_ext_wa)
-		iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
+		iwl_trans_write_prph(trans, SCD_CHAINEXT_EN, 0);
 
 	iwl_trans_ac_txq_enable(trans, trans->conf.cmd_queue,
 				trans->conf.cmd_fifo,
@@ -518,19 +518,19 @@ void iwl_pcie_tx_start(struct iwl_trans *trans)
 
 	/* Enable DMA channel */
 	for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
-		iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
-				   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
-				   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
+		iwl_trans_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
+					 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
+					 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 
 	/* Update FH chicken bits */
-	reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
-	iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
-			   reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
+	reg_val = iwl_pcie_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
+	iwl_trans_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
+				 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 
 	/* Enable L1-Active */
 	if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_8000)
-		iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
-				    APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
+		iwl_trans_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
+					  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 }
 
 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
@@ -549,21 +549,21 @@ void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 	     txq_id++) {
 		struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
 		if (trans->mac_cfg->gen2)
-			iwl_write_direct64(trans,
-					   FH_MEM_CBBC_QUEUE(trans, txq_id),
-					   txq->dma_addr);
+			iwl_pcie_write_direct64(trans,
+						FH_MEM_CBBC_QUEUE(trans, txq_id),
+						txq->dma_addr);
 		else
-			iwl_write_direct32(trans,
-					   FH_MEM_CBBC_QUEUE(trans, txq_id),
-					   txq->dma_addr >> 8);
+			iwl_trans_write_direct32(trans,
+						 FH_MEM_CBBC_QUEUE(trans, txq_id),
+						 txq->dma_addr >> 8);
 		iwl_pcie_txq_unmap(trans, txq_id);
 		txq->read_ptr = 0;
 		txq->write_ptr = 0;
 	}
 
 	/* Tell NIC where to find the "keep warm" buffer */
-	iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
-			   trans_pcie->kw.dma >> 4);
+	iwl_trans_write_direct32(trans, FH_KW_MEM_ADDR_REG,
+				 trans_pcie->kw.dma >> 4);
 
 	/*
 	 * Send 0 as the scd_base_addr since the device may have be reset
@@ -586,16 +586,16 @@ static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 
 	/* Stop each Tx DMA channel */
 	for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
-		iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
+		iwl_trans_pcie_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 		mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 	}
 
 	/* Wait for DMA channels to be idle */
-	ret = iwl_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);
+	ret = iwl_trans_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);
 	if (ret)
 		IWL_ERR(trans,
 			"Failing on timeout while stopping DMA channel %d [0x%08x]\n",
-			ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
+			ch, iwl_trans_pcie_read32(trans, FH_TSSR_TX_STATUS_REG));
 
 	iwl_trans_release_nic_access(trans);
 
@@ -684,7 +684,7 @@ void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
 		return;
 	}
 
-	status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
+	status = iwl_trans_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
 	fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 	active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 
@@ -693,11 +693,11 @@ void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
 		txq_id, active ? "" : "in", fifo,
 		jiffies_to_msecs(txq->wd_timeout),
 		txq->read_ptr, txq->write_ptr,
-		iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
+		iwl_trans_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
 			(trans->mac_cfg->base->max_tfd_queue_size - 1),
-			iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
+			iwl_trans_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
 			(trans->mac_cfg->base->max_tfd_queue_size - 1),
-			iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
+			iwl_pcie_read_direct32(trans, FH_TX_TRB_REG(fifo)));
 }
 
 static void iwl_txq_stuck_timer(struct timer_list *t)
@@ -955,8 +955,8 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
 	iwl_scd_deactivate_fifos(trans);
 
 	/* Tell NIC where to find the "keep warm" buffer */
-	iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
-			   trans_pcie->kw.dma >> 4);
+	iwl_trans_write_direct32(trans, FH_KW_MEM_ADDR_REG,
+				 trans_pcie->kw.dma >> 4);
 
 	spin_unlock_bh(&trans_pcie->irq_lock);
 
@@ -984,14 +984,14 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
 		 * queue.
 		 * Circular buffer (TFD queue in DRAM) physical base address
 		 */
-		iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
-				   trans_pcie->txqs.txq[txq_id]->dma_addr >> 8);
+		iwl_trans_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
+					 trans_pcie->txqs.txq[txq_id]->dma_addr >> 8);
 	}
 
-	iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
+	iwl_trans_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
 	if (trans->mac_cfg->base->num_of_queues > 20)
-		iwl_set_bits_prph(trans, SCD_GP_CTRL,
-				  SCD_GP_CTRL_ENABLE_31_QUEUES);
+		iwl_trans_set_bits_prph(trans, SCD_GP_CTRL,
+					SCD_GP_CTRL_ENABLE_31_QUEUES);
 
 	return 0;
 error:
@@ -1222,13 +1222,13 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
 	 * Assumes that ssn_idx is valid (!= 0xFFF) */
 	txq->read_ptr = (ssn & 0xff);
 	txq->write_ptr = (ssn & 0xff);
-	iwl_write_direct32(trans, HBUS_TARG_WRPTR,
-			   (ssn & 0xff) | (txq_id << 8));
+	iwl_trans_write_direct32(trans, HBUS_TARG_WRPTR,
+				 (ssn & 0xff) | (txq_id << 8));
 
 	if (cfg) {
 		u8 frame_limit = cfg->frame_limit;
 
-		iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
+		iwl_trans_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
 
 		/* Set up Tx window size and frame limit for this queue */
 		iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
@@ -1240,11 +1240,11 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
 			SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
 
 		/* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
-		iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
-			       (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
-			       (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
-			       (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
-			       SCD_QUEUE_STTS_REG_MSK);
+		iwl_trans_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
+				     (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
+				     (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
+				     (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
+				     SCD_QUEUE_STTS_REG_MSK);
 
 		/* enable the scheduler for this queue (only) */
 		if (txq_id == trans->conf.cmd_queue &&
@@ -1335,8 +1335,8 @@ static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
 		if (!block && !(WARN_ON_ONCE(!txq->block))) {
 			txq->block--;
 			if (!txq->block) {
-				iwl_write32(trans, HBUS_TARG_WRPTR,
-					    txq->write_ptr | (i << 8));
+				iwl_trans_pcie_write32(trans, HBUS_TARG_WRPTR,
+						       txq->write_ptr | (i << 8));
 			}
 		} else if (block) {
 			txq->block++;
@@ -2147,6 +2147,9 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
 	u16 wifi_seq;
 	bool amsdu;
 
+	if (trans->mac_cfg->gen2)
+		return iwl_txq_gen2_tx(trans, skb, dev_cmd, txq_id);
+
 	txq = trans_pcie->txqs.txq[txq_id];
 
 	if (WARN_ONCE(!test_bit(txq_id, trans_pcie->txqs.queue_used),
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/utils.c b/drivers/net/wireless/intel/iwlwifi/pcie/utils.c
index 1bb274d8390c3..8aa43e5ac0e19 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/utils.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/utils.c
@@ -1,12 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2025 Intel Corporation
+ * Copyright (C) 2025-2026 Intel Corporation
  */
 
 #include <linux/pci.h>
 #include <linux/gfp.h>
 
-#include "iwl-io.h"
+#include "iwl-trans.h"
 #include "pcie/utils.h"
 
 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans, struct pci_dev *pdev)
@@ -51,7 +51,7 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans *trans, struct pci_dev *pdev)
 
 	IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
 	for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
-		*ptr = iwl_read32(trans, i);
+		*ptr = iwl_trans_pcie_read32(trans, i);
 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 
 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
@@ -102,3 +102,88 @@ void iwl_trans_pcie_dump_regs(struct iwl_trans *trans, struct pci_dev *pdev)
 	pcie_dbg_dumped_once = 1;
 	kfree(buf);
 }
+
+u32 iwl_pcie_read_direct32(struct iwl_trans *trans, u32 reg)
+{
+	if (iwl_trans_grab_nic_access(trans)) {
+		u32 value = iwl_trans_pcie_read32(trans, reg);
+
+		iwl_trans_release_nic_access(trans);
+		return value;
+	}
+
+	/* return as if we have a HW timeout/failure */
+	return 0x5a5a5a5a;
+}
+
+#define IWL_PCIE_POLL_INTERVAL 10	/* microseconds */
+
+int iwl_pcie_poll_direct_bit(struct iwl_trans *trans,
+			     u32 addr, u32 mask, int timeout)
+{
+	int t = 0;
+
+	do {
+		if ((iwl_pcie_read_direct32(trans, addr) & mask) == mask)
+			return t;
+		udelay(IWL_PCIE_POLL_INTERVAL);
+		t += IWL_PCIE_POLL_INTERVAL;
+	} while (t < timeout);
+
+	return -ETIMEDOUT;
+}
+
+int iwl_pcie_poll_prph_bit(struct iwl_trans *trans, u32 addr,
+			   u32 bits, u32 mask, int timeout)
+{
+	int t = 0;
+
+	do {
+		if ((iwl_trans_read_prph(trans, addr) & mask) == (bits & mask))
+			return 0;
+		udelay(IWL_PCIE_POLL_INTERVAL);
+		t += IWL_PCIE_POLL_INTERVAL;
+	} while (t < timeout);
+
+	return -ETIMEDOUT;
+}
+
+int iwl_pcie_poll_umac_prph_bit(struct iwl_trans *trans,
+				u32 addr, u32 bits, u32 mask,
+				int timeout)
+{
+	return iwl_pcie_poll_prph_bit(trans, addr +
+				      trans->mac_cfg->umac_prph_offset,
+				      bits, mask, timeout);
+}
+
+int iwl_pcie_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
+					 u32 bits, u32 mask, int timeout)
+{
+	int t = 0;
+
+	do {
+		if ((iwl_trans_read_umac_prph_no_grab(trans, addr) & mask) ==
+		    (bits & mask))
+			return 0;
+		udelay(IWL_PCIE_POLL_INTERVAL);
+		t += IWL_PCIE_POLL_INTERVAL;
+	} while (t < timeout);
+
+	return -ETIMEDOUT;
+}
+
+void iwl_pcie_write_prph64_no_grab(struct iwl_trans *trans, u32 ofs, u64 val)
+{
+	trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val);
+	iwl_pcie_write_prph_no_grab(trans, ofs, val & 0xffffffff);
+	iwl_pcie_write_prph_no_grab(trans, ofs + 4, val >> 32);
+}
+
+void iwl_pcie_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)
+{
+	if (iwl_trans_grab_nic_access(trans)) {
+		iwl_pcie_write64(trans, reg, value);
+		iwl_trans_release_nic_access(trans);
+	}
+}
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/utils.h b/drivers/net/wireless/intel/iwlwifi/pcie/utils.h
index 27437d5e099ba..ece1caaa49482 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/utils.h
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/utils.h
@@ -1,17 +1,43 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2025 Intel Corporation
+ * Copyright (C) 2025-2026 Intel Corporation
  */
 
 #ifndef __iwl_pcie_utils_h__
 #define __iwl_pcie_utils_h__
 
-#include "iwl-io.h"
+#include "iwl-trans.h"
+#include "internal.h"
 
 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans, struct pci_dev *pdev);
 
-static inline void _iwl_trans_set_bits_mask(struct iwl_trans *trans,
-					    u32 reg, u32 mask, u32 value)
+u32 iwl_pcie_read_direct32(struct iwl_trans *trans, u32 reg);
+int iwl_pcie_poll_direct_bit(struct iwl_trans *trans,
+			     u32 addr, u32 mask, int timeout);
+int iwl_pcie_poll_prph_bit(struct iwl_trans *trans, u32 addr,
+			   u32 bits, u32 mask, int timeout);
+int iwl_pcie_poll_umac_prph_bit(struct iwl_trans *trans, u32 addr,
+				u32 bits, u32 mask, int timeout);
+int iwl_pcie_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
+					 u32 bits, u32 mask, int timeout);
+void iwl_pcie_write_prph64_no_grab(struct iwl_trans *trans, u32 ofs, u64 val);
+void iwl_pcie_write_direct64(struct iwl_trans *trans, u64 reg, u64 value);
+
+static inline void iwl_pcie_write64(struct iwl_trans *trans, u64 ofs, u64 val)
+{
+	iwl_trans_pcie_write32(trans, ofs, lower_32_bits(val));
+	iwl_trans_pcie_write32(trans, ofs + 4, upper_32_bits(val));
+}
+
+static inline void iwl_pcie_write_umac_prph_no_grab(struct iwl_trans *trans,
+						    u32 ofs, u32 val)
+{
+	iwl_pcie_write_prph_no_grab(trans, ofs + trans->mac_cfg->umac_prph_offset,
+				    val);
+}
+
+static inline void iwl_pcie_set_bits_mask(struct iwl_trans *trans,
+					  u32 reg, u32 mask, u32 value)
 {
 	u32 v;
 
@@ -19,22 +45,22 @@ static inline void _iwl_trans_set_bits_mask(struct iwl_trans *trans,
 	WARN_ON_ONCE(value & ~mask);
 #endif
 
-	v = iwl_read32(trans, reg);
+	v = iwl_trans_pcie_read32(trans, reg);
 	v &= ~mask;
 	v |= value;
-	iwl_write32(trans, reg, v);
+	iwl_trans_pcie_write32(trans, reg, v);
 }
 
-static inline void iwl_trans_clear_bit(struct iwl_trans *trans,
+static inline void iwl_pcie_clear_bit(struct iwl_trans *trans,
 				       u32 reg, u32 mask)
 {
-	_iwl_trans_set_bits_mask(trans, reg, mask, 0);
+	iwl_pcie_set_bits_mask(trans, reg, mask, 0);
 }
 
-static inline void iwl_trans_set_bit(struct iwl_trans *trans,
+static inline void iwl_pcie_set_bit(struct iwl_trans *trans,
 				     u32 reg, u32 mask)
 {
-	_iwl_trans_set_bits_mask(trans, reg, mask, mask);
+	iwl_pcie_set_bits_mask(trans, reg, mask, mask);
 }
 
 #endif /* __iwl_pcie_utils_h__ */