| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/07/11 07:45 | flow | patch-triage |
2mArgs:null Results: {
"EnableConfigs": [
"NET_DSA_MT7530",
"NET_DSA_MT7530_MMIO"
],
"FocusSymbols": [
"en7528_mac_port_get_caps",
"mt7988_setup",
"mt753x_conduit_state_change"
],
"Reasoning": "The patch adds support for the EcoNet EN7528 SoC built-in switch to the Mediatek MT7530 DSA driver. This includes a new function for getting MAC port capabilities and modifications to switch setup and conduit state change logic. The driver can be probed via device tree and the switch operations are reachable via the DSA core in a virtualized environment.",
"WorthFuzzing": true
} |
| 1/1 | 2026/07/11 07:45 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit 5cf18ec0b94be1c01ff594520cd15c4b23b4c5f6\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Sat Jul 11 07:45:53 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml\nindex 815a9080890104..90b3582b761909 100644\n--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml\n+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml\n@@ -100,6 +100,10 @@ properties:\n Built-in switch of the Airoha AN7583 SoC\n const: airoha,an7583-switch\n \n+ - description:\n+ Built-in switch of the EcoNet EN7528 SoC\n+ const: econet,en7528-switch\n+\n reg:\n maxItems: 1\n \n@@ -318,6 +322,7 @@ allOf:\n - mediatek,mt7988-switch\n - airoha,en7581-switch\n - airoha,an7583-switch\n+ - econet,en7528-switch\n then:\n $ref: \"#/$defs/builtin-dsa-port\"\n properties:\ndiff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mt7530-mmio.c\nindex 1dc8b93fb51a13..1065671bcdd132 100644\n--- a/drivers/net/dsa/mt7530-mmio.c\n+++ b/drivers/net/dsa/mt7530-mmio.c\n@@ -13,6 +13,7 @@\n static const struct of_device_id mt7988_of_match[] = {\n \t{ .compatible = \"airoha,an7583-switch\", .data = \u0026mt753x_table[ID_AN7583], },\n \t{ .compatible = \"airoha,en7581-switch\", .data = \u0026mt753x_table[ID_EN7581], },\n+\t{ .compatible = \"econet,en7528-switch\", .data = \u0026mt753x_table[ID_EN7528], },\n \t{ .compatible = \"mediatek,mt7988-switch\", .data = \u0026mt753x_table[ID_MT7988], },\n \t{ /* sentinel */ },\n };\ndiff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c\nindex 3c2a3029b10cfb..2aecad77af9ad6 100644\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -2912,6 +2912,30 @@ static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port,\n \t}\n }\n \n+static void en7528_mac_port_get_caps(struct dsa_switch *ds, int port,\n+\t\t\t\t struct phylink_config *config)\n+{\n+\tswitch (port) {\n+\t/* Ports which are connected to switch PHYs. There is no MII pinout. */\n+\tcase 1 ... 4:\n+\t\t__set_bit(PHY_INTERFACE_MODE_INTERNAL,\n+\t\t\t config-\u003esupported_interfaces);\n+\n+\t\tconfig-\u003emac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;\n+\t\tbreak;\n+\n+\t/* Port 6 is connected to SoC's GMAC at 1000 Mbps full duplex. There\n+\t * is no MII pinout.\n+\t */\n+\tcase 6:\n+\t\t__set_bit(PHY_INTERFACE_MODE_INTERNAL,\n+\t\t\t config-\u003esupported_interfaces);\n+\n+\t\tconfig-\u003emac_capabilities |= MAC_1000FD;\n+\t\tbreak;\n+\t}\n+}\n+\n static void\n mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,\n \t\t phy_interface_t interface)\n@@ -3254,7 +3278,8 @@ mt753x_conduit_state_change(struct dsa_switch *ds,\n \t * forwarded to the numerically smallest CPU port whose conduit\n \t * interface is up.\n \t */\n-\tif (priv-\u003eid != ID_MT7530 \u0026\u0026 priv-\u003eid != ID_MT7621)\n+\tif (priv-\u003eid != ID_MT7530 \u0026\u0026 priv-\u003eid != ID_MT7621 \u0026\u0026\n+\t priv-\u003eid != ID_EN7528)\n \t\treturn;\n \n \tmask = BIT(cpu_dp-\u003eindex);\n@@ -3319,9 +3344,17 @@ static int mt753x_setup_tc(struct dsa_switch *ds, int port,\n \t}\n }\n \n+/* The EN7528 LAN ports are integrated GPHYs at MDIO addresses 9..12 (switch\n+ * ports 1..4) on the switch internal MDIO bus, reachable only through the PHY\n+ * indirect access registers. There is no mdiodev to derive the addresses from.\n+ */\n+#define EN7528_GPHY_BASE\t\t9\n+#define EN7528_NUM_GPHYS\t\t4\n+\n static int mt7988_setup(struct dsa_switch *ds)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n+\tint i;\n \n \t/* Reset the switch */\n \treset_control_assert(priv-\u003erstc);\n@@ -3342,6 +3375,17 @@ static int mt7988_setup(struct dsa_switch *ds)\n \t/* Reset the switch PHYs */\n \tmt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);\n \n+\t/* The EN7528 LAN GPHYs advertise EEE by default, but negotiating EEE\n+\t * with common link partners (e.g. Realtek GbE NICs) results in an\n+\t * unstable link with dropped frames. Disable EEE advertisement on\n+\t * them.\n+\t */\n+\tif (priv-\u003eid == ID_EN7528)\n+\t\tfor (i = EN7528_GPHY_BASE;\n+\t\t i \u003c EN7528_GPHY_BASE + EN7528_NUM_GPHYS; i++)\n+\t\t\tmt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN,\n+\t\t\t\t\t\t MDIO_AN_EEE_ADV, 0);\n+\n \treturn mt7531_setup_common(ds);\n }\n \n@@ -3459,6 +3503,16 @@ const struct mt753x_info mt753x_table[] = {\n \t\t.phy_write_c45 = mt7531_ind_c45_phy_write,\n \t\t.mac_port_get_caps = en7581_mac_port_get_caps,\n \t},\n+\t[ID_EN7528] = {\n+\t\t.id = ID_EN7528,\n+\t\t.pcs_ops = \u0026mt7530_pcs_ops,\n+\t\t.sw_setup = mt7988_setup,\n+\t\t.phy_read_c22 = mt7531_ind_c22_phy_read,\n+\t\t.phy_write_c22 = mt7531_ind_c22_phy_write,\n+\t\t.phy_read_c45 = mt7531_ind_c45_phy_read,\n+\t\t.phy_write_c45 = mt7531_ind_c45_phy_write,\n+\t\t.mac_port_get_caps = en7528_mac_port_get_caps,\n+\t},\n };\n EXPORT_SYMBOL_GPL(mt753x_table);\n \ndiff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h\nindex dd33b0df3419e3..5f1e841f42c0ed 100644\n--- a/drivers/net/dsa/mt7530.h\n+++ b/drivers/net/dsa/mt7530.h\n@@ -21,6 +21,7 @@ enum mt753x_id {\n \tID_MT7988 = 3,\n \tID_EN7581 = 4,\n \tID_AN7583 = 5,\n+\tID_EN7528 = 6,\n };\n \n #define\tNUM_TRGMII_CTRL\t\t\t5\n"
} |
| 2/1 | 2026/07/11 07:45 | agent | patch-evaluator |
2mModel:gemini-3.1-pro-preview Args: null Results: {
"EnableConfigs": [
"NET_DSA_MT7530",
"NET_DSA_MT7530_MMIO"
],
"FocusSymbols": [
"en7528_mac_port_get_caps",
"mt7988_setup",
"mt753x_conduit_state_change"
],
"Reasoning": "The patch adds support for the EcoNet EN7528 SoC built-in switch to the Mediatek MT7530 DSA driver. This includes a new function for getting MAC port capabilities and modifications to switch setup and conduit state change logic. The driver can be probed via device tree and the switch operations are reachable via the DSA core in a virtualized environment.",
"WorthFuzzing": true
}Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Do not list too generic configs (we already have them enabled). Only list those that specifically cover the modified code. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes:
commit 5cf18ec0b94be1c01ff594520cd15c4b23b4c5f6
Author: syz-cluster <triage@syzkaller.com>
Date: Sat Jul 11 07:45:53 2026 +0000
syz-cluster: applied patch under review
diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
index 815a9080890104..90b3582b761909 100644
--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -100,6 +100,10 @@ properties:
Built-in switch of the Airoha AN7583 SoC
const: airoha,an7583-switch
+ - description:
+ Built-in switch of the EcoNet EN7528 SoC
+ const: econet,en7528-switch
+
reg:
maxItems: 1
@@ -318,6 +322,7 @@ allOf:
- mediatek,mt7988-switch
- airoha,en7581-switch
- airoha,an7583-switch
+ - econet,en7528-switch
then:
$ref: "#/$defs/builtin-dsa-port"
properties:
diff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mt7530-mmio.c
index 1dc8b93fb51a13..1065671bcdd132 100644
--- a/drivers/net/dsa/mt7530-mmio.c
+++ b/drivers/net/dsa/mt7530-mmio.c
@@ -13,6 +13,7 @@
static const struct of_device_id mt7988_of_match[] = {
{ .compatible = "airoha,an7583-switch", .data = &mt753x_table[ID_AN7583], },
{ .compatible = "airoha,en7581-switch", .data = &mt753x_table[ID_EN7581], },
+ { .compatible = "econet,en7528-switch", .data = &mt753x_table[ID_EN7528], },
{ .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
{ /* sentinel */ },
};
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 3c2a3029b10cfb..2aecad77af9ad6 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -2912,6 +2912,30 @@ static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port,
}
}
+static void en7528_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+{
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 1 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+
+ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
+ break;
+
+ /* Port 6 is connected to SoC's GMAC at 1000 Mbps full duplex. There
+ * is no MII pinout.
+ */
+ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+
+ config->mac_capabilities |= MAC_1000FD;
+ break;
+ }
+}
+
static void
mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
@@ -3254,7 +3278,8 @@ mt753x_conduit_state_change(struct dsa_switch *ds,
* forwarded to the numerically smallest CPU port whose conduit
* interface is up.
*/
- if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621 &&
+ priv->id != ID_EN7528)
return;
mask = BIT(cpu_dp->index);
@@ -3319,9 +3344,17 @@ static int mt753x_setup_tc(struct dsa_switch *ds, int port,
}
}
+/* The EN7528 LAN ports are integrated GPHYs at MDIO addresses 9..12 (switch
+ * ports 1..4) on the switch internal MDIO bus, reachable only through the PHY
+ * indirect access registers. There is no mdiodev to derive the addresses from.
+ */
+#define EN7528_GPHY_BASE 9
+#define EN7528_NUM_GPHYS 4
+
static int mt7988_setup(struct dsa_switch *ds)
{
struct mt7530_priv *priv = ds->priv;
+ int i;
/* Reset the switch */
reset_control_assert(priv->rstc);
@@ -3342,6 +3375,17 @@ static int mt7988_setup(struct dsa_switch *ds)
/* Reset the switch PHYs */
mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
+ /* The EN7528 LAN GPHYs advertise EEE by default, but negotiating EEE
+ * with common link partners (e.g. Realtek GbE NICs) results in an
+ * unstable link with dropped frames. Disable EEE advertisement on
+ * them.
+ */
+ if (priv->id == ID_EN7528)
+ for (i = EN7528_GPHY_BASE;
+ i < EN7528_GPHY_BASE + EN7528_NUM_GPHYS; i++)
+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN,
+ MDIO_AN_EEE_ADV, 0);
+
return mt7531_setup_common(ds);
}
@@ -3459,6 +3503,16 @@ const struct mt753x_info mt753x_table[] = {
.phy_write_c45 = mt7531_ind_c45_phy_write,
.mac_port_get_caps = en7581_mac_port_get_caps,
},
+ [ID_EN7528] = {
+ .id = ID_EN7528,
+ .pcs_ops = &mt7530_pcs_ops,
+ .sw_setup = mt7988_setup,
+ .phy_read_c22 = mt7531_ind_c22_phy_read,
+ .phy_write_c22 = mt7531_ind_c22_phy_write,
+ .phy_read_c45 = mt7531_ind_c45_phy_read,
+ .phy_write_c45 = mt7531_ind_c45_phy_write,
+ .mac_port_get_caps = en7528_mac_port_get_caps,
+ },
};
EXPORT_SYMBOL_GPL(mt753x_table);
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index dd33b0df3419e3..5f1e841f42c0ed 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -21,6 +21,7 @@ enum mt753x_id {
ID_MT7988 = 3,
ID_EN7581 = 4,
ID_AN7583 = 5,
+ ID_EN7528 = 6,
};
#define NUM_TRGMII_CTRL 5
|
| 3/2 | 2026/07/11 07:45 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 3936 output: 32 thoughts: 810 Thoughts: **Assessing the Fuzzability of a Network Switch Driver Patch** Okay, so I've got a patch here that adds support for the EcoNet EN7528 SoC's built-in switch to the Mediatek MT7530 DSA driver. The changes are spread across several files: the Device Tree bindings, the MMIO and core driver files, and the header file. Looking at the changes, it seems to be adding device-specific matching, capabilities, and workarounds for this particular switch. Specifically, I see `econet,en7528-switch` being added, along with functions and identifiers that relate to this new hardware. The patch also includes a workaround to disable EEE advertisement on its GPHYs. Now, as an expert, my primary thought is, "Can I even *reach* this in a virtualized environment?" This is a DSA switch driver, so it's likely probed through the Device Tree. I immediately think of QEMU. Can I emulate the EN7528 or the MT7530/MT7988 in QEMU? Almost certainly not – I've never heard of such specific emulation being available. These are typically low-level hardware drivers. However, a glimmer of hope arises: syzkaller. I recall that syzkaller can generate arbitrary Device Trees. Theoretically, if the driver is compiled in, it *could* be probed by syzkaller if the DT node matches. The catch? It's an MMIO driver. Without the *actual* hardware, MMIO accesses are going to be problematic. They'll either fault if unmapped or just return meaningless data if mapped to dummy memory. Although syzkaller *does* map some dummy memory for MMIO, it doesn't give me much hope that the driver will behave in a meaningful way. But, syzkaller *does* fuzz device trees and *can* probe drivers. So let's check if it's worth fuzzing! My experience tells me that hardware-specific drivers that just do MMIO without software emulation or virtual interfaces are usually *not* worth fuzzing. They tend to just crash or fail early during the probe due to the hardware not responding, and they rarely expose interesting, software-reachable attack surfaces. These types of drivers are like USB gadget, mac80211_hwsim or vhci, that offer an entry point to the system and have great potential to be fuzzed. Wait, looking closer at the prompt for the task. It specifically says to return `WorthFuzzing=false` if the patch contains code paths that are impossible to reach in virtualized environments like GCE or QEMU, *even* with software-emulated hardware. It seems pretty clear. My instincts are right. So, the `mt7530` switch driver...is it reachable in QEMU? I doubt it, but just to be certain. I don't need to look at QEMU source code. I know it's a hardware driver. Therefore, given the nature of the driver being tightly coupled with specific hardware and inaccessible in typical virtualized environments, I'm going to determine that this is *not* worth fuzzing. |
| 4/2 | 2026/07/11 07:46 | tool | grepper |
0mArgs:{
"Expression": "mt7530",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "\nFull output is too long, showing 500 out of 2017 lines.\nUse more precise expression if possible.\n\ndrivers/net/dsa/Makefile=5=obj-$(CONFIG_NET_DSA_KS8995) \t+= ks8995.o\ndrivers/net/dsa/Makefile:6:obj-$(CONFIG_NET_DSA_MT7530)\t+= mt7530.o\ndrivers/net/dsa/Makefile:7:obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o\ndrivers/net/dsa/Makefile:8:obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o\ndrivers/net/dsa/Makefile-9-obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o\n--\ndrivers/net/dsa/mt7530-mdio.c-15-\ndrivers/net/dsa/mt7530-mdio.c:16:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530-mdio.c-17-\ndrivers/net/dsa/mt7530-mdio.c=18=static int\ndrivers/net/dsa/mt7530-mdio.c:19:mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)\ndrivers/net/dsa/mt7530-mdio.c-20-{\ndrivers/net/dsa/mt7530-mdio.c:21:\tstruct mt7530_priv *priv = context;\ndrivers/net/dsa/mt7530-mdio.c-22-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/net/dsa/mt7530-mdio.c=43=static int\ndrivers/net/dsa/mt7530-mdio.c:44:mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)\ndrivers/net/dsa/mt7530-mdio.c-45-{\ndrivers/net/dsa/mt7530-mdio.c:46:\tstruct mt7530_priv *priv = context;\ndrivers/net/dsa/mt7530-mdio.c-47-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/net/dsa/mt7530-mdio.c=66=static void\ndrivers/net/dsa/mt7530-mdio.c:67:mt7530_mdio_regmap_lock(void *mdio_lock)\ndrivers/net/dsa/mt7530-mdio.c-68-{\n--\ndrivers/net/dsa/mt7530-mdio.c=72=static void\ndrivers/net/dsa/mt7530-mdio.c:73:mt7530_mdio_regmap_unlock(void *mdio_lock)\ndrivers/net/dsa/mt7530-mdio.c-74-{\n--\ndrivers/net/dsa/mt7530-mdio.c-77-\ndrivers/net/dsa/mt7530-mdio.c:78:static const struct regmap_bus mt7530_regmap_bus = {\ndrivers/net/dsa/mt7530-mdio.c:79:\t.reg_write = mt7530_regmap_write,\ndrivers/net/dsa/mt7530-mdio.c:80:\t.reg_read = mt7530_regmap_read,\ndrivers/net/dsa/mt7530-mdio.c-81-};\n--\ndrivers/net/dsa/mt7530-mdio.c=83=static int\ndrivers/net/dsa/mt7530-mdio.c:84:mt7531_create_sgmii(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530-mdio.c-85-{\n--\ndrivers/net/dsa/mt7530-mdio.c-105-\t\tmt7531_pcs_config[i]-\u003emax_register = 0x17c;\ndrivers/net/dsa/mt7530-mdio.c:106:\t\tmt7531_pcs_config[i]-\u003elock = mt7530_mdio_regmap_lock;\ndrivers/net/dsa/mt7530-mdio.c:107:\t\tmt7531_pcs_config[i]-\u003eunlock = mt7530_mdio_regmap_unlock;\ndrivers/net/dsa/mt7530-mdio.c-108-\t\tmt7531_pcs_config[i]-\u003elock_arg = \u0026priv-\u003ebus-\u003emdio_lock;\ndrivers/net/dsa/mt7530-mdio.c-109-\ndrivers/net/dsa/mt7530-mdio.c:110:\t\tregmap = devm_regmap_init(priv-\u003edev, \u0026mt7530_regmap_bus, priv,\ndrivers/net/dsa/mt7530-mdio.c-111-\t\t\t\t\t mt7531_pcs_config[i]);\n--\ndrivers/net/dsa/mt7530-mdio.c-130-\ndrivers/net/dsa/mt7530-mdio.c:131:static const struct of_device_id mt7530_of_match[] = {\ndrivers/net/dsa/mt7530-mdio.c-132-\t{ .compatible = \"mediatek,mt7621\", .data = \u0026mt753x_table[ID_MT7621], },\ndrivers/net/dsa/mt7530-mdio.c:133:\t{ .compatible = \"mediatek,mt7530\", .data = \u0026mt753x_table[ID_MT7530], },\ndrivers/net/dsa/mt7530-mdio.c-134-\t{ .compatible = \"mediatek,mt7531\", .data = \u0026mt753x_table[ID_MT7531], },\n--\ndrivers/net/dsa/mt7530-mdio.c-136-};\ndrivers/net/dsa/mt7530-mdio.c:137:MODULE_DEVICE_TABLE(of, mt7530_of_match);\ndrivers/net/dsa/mt7530-mdio.c-138-\n--\ndrivers/net/dsa/mt7530-mdio.c=147=static int\ndrivers/net/dsa/mt7530-mdio.c:148:mt7530_probe(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-149-{\ndrivers/net/dsa/mt7530-mdio.c:150:\tstruct mt7530_priv *priv;\ndrivers/net/dsa/mt7530-mdio.c-151-\tstruct device_node *dn;\n--\ndrivers/net/dsa/mt7530-mdio.c-163-\ndrivers/net/dsa/mt7530-mdio.c:164:\tret = mt7530_probe_common(priv);\ndrivers/net/dsa/mt7530-mdio.c-165-\tif (ret)\n--\ndrivers/net/dsa/mt7530-mdio.c-202-\ndrivers/net/dsa/mt7530-mdio.c:203:\tpriv-\u003eregmap = devm_regmap_init(priv-\u003edev, \u0026mt7530_regmap_bus, priv,\ndrivers/net/dsa/mt7530-mdio.c-204-\t\t\t\t\t\u0026regmap_config);\n--\ndrivers/net/dsa/mt7530-mdio.c=214=static void\ndrivers/net/dsa/mt7530-mdio.c:215:mt7530_remove(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-216-{\ndrivers/net/dsa/mt7530-mdio.c:217:\tstruct mt7530_priv *priv = dev_get_drvdata(\u0026mdiodev-\u003edev);\ndrivers/net/dsa/mt7530-mdio.c-218-\tint ret = 0, i;\n--\ndrivers/net/dsa/mt7530-mdio.c-232-\ndrivers/net/dsa/mt7530-mdio.c:233:\tmt7530_remove_common(priv);\ndrivers/net/dsa/mt7530-mdio.c-234-\n--\ndrivers/net/dsa/mt7530-mdio.c-238-\ndrivers/net/dsa/mt7530-mdio.c:239:static void mt7530_shutdown(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-240-{\ndrivers/net/dsa/mt7530-mdio.c:241:\tstruct mt7530_priv *priv = dev_get_drvdata(\u0026mdiodev-\u003edev);\ndrivers/net/dsa/mt7530-mdio.c-242-\n--\ndrivers/net/dsa/mt7530-mdio.c-250-\ndrivers/net/dsa/mt7530-mdio.c:251:static struct mdio_driver mt7530_mdio_driver = {\ndrivers/net/dsa/mt7530-mdio.c:252:\t.probe = mt7530_probe,\ndrivers/net/dsa/mt7530-mdio.c:253:\t.remove = mt7530_remove,\ndrivers/net/dsa/mt7530-mdio.c:254:\t.shutdown = mt7530_shutdown,\ndrivers/net/dsa/mt7530-mdio.c-255-\t.mdiodrv.driver = {\ndrivers/net/dsa/mt7530-mdio.c:256:\t\t.name = \"mt7530-mdio\",\ndrivers/net/dsa/mt7530-mdio.c:257:\t\t.of_match_table = mt7530_of_match,\ndrivers/net/dsa/mt7530-mdio.c-258-\t},\n--\ndrivers/net/dsa/mt7530-mdio.c-260-\ndrivers/net/dsa/mt7530-mdio.c:261:mdio_module_driver(mt7530_mdio_driver);\ndrivers/net/dsa/mt7530-mdio.c-262-\n--\ndrivers/net/dsa/mt7530-mmio.c-10-\ndrivers/net/dsa/mt7530-mmio.c:11:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530-mmio.c-12-\n--\ndrivers/net/dsa/mt7530-mmio.c=31=mt7988_probe(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-32-{\ndrivers/net/dsa/mt7530-mmio.c:33:\tstruct mt7530_priv *priv;\ndrivers/net/dsa/mt7530-mmio.c-34-\tvoid __iomem *base_addr;\n--\ndrivers/net/dsa/mt7530-mmio.c-43-\ndrivers/net/dsa/mt7530-mmio.c:44:\tret = mt7530_probe_common(priv);\ndrivers/net/dsa/mt7530-mmio.c-45-\tif (ret)\n--\ndrivers/net/dsa/mt7530-mmio.c=68=static void mt7988_remove(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-69-{\ndrivers/net/dsa/mt7530-mmio.c:70:\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\ndrivers/net/dsa/mt7530-mmio.c-71-\ndrivers/net/dsa/mt7530-mmio.c-72-\tif (priv)\ndrivers/net/dsa/mt7530-mmio.c:73:\t\tmt7530_remove_common(priv);\ndrivers/net/dsa/mt7530-mmio.c-74-}\n--\ndrivers/net/dsa/mt7530-mmio.c=76=static void mt7988_shutdown(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-77-{\ndrivers/net/dsa/mt7530-mmio.c:78:\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\ndrivers/net/dsa/mt7530-mmio.c-79-\n--\ndrivers/net/dsa/mt7530-mmio.c=88=static struct platform_driver mt7988_platform_driver = {\n--\ndrivers/net/dsa/mt7530-mmio.c-92-\t.driver = {\ndrivers/net/dsa/mt7530-mmio.c:93:\t\t.name = \"mt7530-mmio\",\ndrivers/net/dsa/mt7530-mmio.c-94-\t\t.of_match_table = mt7988_of_match,\n--\ndrivers/net/dsa/mt7530.c-25-\ndrivers/net/dsa/mt7530.c:26:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530.c-27-\n--\ndrivers/net/dsa/mt7530.c=31=static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)\n--\ndrivers/net/dsa/mt7530.c-36-/* String, offset, and register size in bytes if different from 4 bytes */\ndrivers/net/dsa/mt7530.c:37:static const struct mt7530_mib_desc mt7530_mib[] = {\ndrivers/net/dsa/mt7530.c-38-\tMIB_DESC(1, MT7530_PORT_MIB_TX_DROP, \"TxDrop\"),\n--\ndrivers/net/dsa/mt7530.c=49=static void\ndrivers/net/dsa/mt7530.c:50:mt7530_mutex_lock(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-51-{\n--\ndrivers/net/dsa/mt7530.c=56=static void\ndrivers/net/dsa/mt7530.c:57:mt7530_mutex_unlock(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-58-{\n--\ndrivers/net/dsa/mt7530.c=63=static void\ndrivers/net/dsa/mt7530.c:64:core_write(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-65-{\n--\ndrivers/net/dsa/mt7530.c-68-\ndrivers/net/dsa/mt7530.c:69:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-70-\n--\ndrivers/net/dsa/mt7530.c-95-\ndrivers/net/dsa/mt7530.c:96:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-97-}\n--\ndrivers/net/dsa/mt7530.c=99=static void\ndrivers/net/dsa/mt7530.c:100:core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)\ndrivers/net/dsa/mt7530.c-101-{\n--\ndrivers/net/dsa/mt7530.c-105-\ndrivers/net/dsa/mt7530.c:106:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-107-\n--\ndrivers/net/dsa/mt7530.c-137-\ndrivers/net/dsa/mt7530.c:138:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-139-}\n--\ndrivers/net/dsa/mt7530.c=141=static void\ndrivers/net/dsa/mt7530.c:142:core_set(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-143-{\n--\ndrivers/net/dsa/mt7530.c=147=static void\ndrivers/net/dsa/mt7530.c:148:core_clear(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-149-{\n--\ndrivers/net/dsa/mt7530.c=153=static int\ndrivers/net/dsa/mt7530.c:154:mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-155-{\n--\ndrivers/net/dsa/mt7530.c-161-\t\tdev_err(priv-\u003edev,\ndrivers/net/dsa/mt7530.c:162:\t\t\t\"failed to write mt7530 register\\n\");\ndrivers/net/dsa/mt7530.c-163-\n--\ndrivers/net/dsa/mt7530.c=167=static u32\ndrivers/net/dsa/mt7530.c:168:mt7530_mii_read(struct mt7530_priv *priv, u32 reg)\ndrivers/net/dsa/mt7530.c-169-{\n--\ndrivers/net/dsa/mt7530.c-176-\t\tdev_err(priv-\u003edev,\ndrivers/net/dsa/mt7530.c:177:\t\t\t\"failed to read mt7530 register\\n\");\ndrivers/net/dsa/mt7530.c-178-\t\treturn 0;\n--\ndrivers/net/dsa/mt7530.c=184=static void\ndrivers/net/dsa/mt7530.c:185:mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-186-{\ndrivers/net/dsa/mt7530.c:187:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-188-\ndrivers/net/dsa/mt7530.c:189:\tmt7530_mii_write(priv, reg, val);\ndrivers/net/dsa/mt7530.c-190-\ndrivers/net/dsa/mt7530.c:191:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-192-}\n--\ndrivers/net/dsa/mt7530.c=194=static u32\ndrivers/net/dsa/mt7530.c:195:_mt7530_unlocked_read(struct mt7530_dummy_poll *p)\ndrivers/net/dsa/mt7530.c-196-{\ndrivers/net/dsa/mt7530.c:197:\treturn mt7530_mii_read(p-\u003epriv, p-\u003ereg);\ndrivers/net/dsa/mt7530.c-198-}\n--\ndrivers/net/dsa/mt7530.c=200=static u32\ndrivers/net/dsa/mt7530.c:201:_mt7530_read(struct mt7530_dummy_poll *p)\ndrivers/net/dsa/mt7530.c-202-{\n--\ndrivers/net/dsa/mt7530.c-204-\ndrivers/net/dsa/mt7530.c:205:\tmt7530_mutex_lock(p-\u003epriv);\ndrivers/net/dsa/mt7530.c-206-\ndrivers/net/dsa/mt7530.c:207:\tval = mt7530_mii_read(p-\u003epriv, p-\u003ereg);\ndrivers/net/dsa/mt7530.c-208-\ndrivers/net/dsa/mt7530.c:209:\tmt7530_mutex_unlock(p-\u003epriv);\ndrivers/net/dsa/mt7530.c-210-\n--\ndrivers/net/dsa/mt7530.c=214=static u32\ndrivers/net/dsa/mt7530.c:215:mt7530_read(struct mt7530_priv *priv, u32 reg)\ndrivers/net/dsa/mt7530.c-216-{\ndrivers/net/dsa/mt7530.c:217:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-218-\ndrivers/net/dsa/mt7530.c-219-\tINIT_MT7530_DUMMY_POLL(\u0026p, priv, reg);\ndrivers/net/dsa/mt7530.c:220:\treturn _mt7530_read(\u0026p);\ndrivers/net/dsa/mt7530.c-221-}\n--\ndrivers/net/dsa/mt7530.c=223=static void\ndrivers/net/dsa/mt7530.c:224:mt7530_rmw(struct mt7530_priv *priv, u32 reg,\ndrivers/net/dsa/mt7530.c-225-\t u32 mask, u32 set)\ndrivers/net/dsa/mt7530.c-226-{\ndrivers/net/dsa/mt7530.c:227:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-228-\n--\ndrivers/net/dsa/mt7530.c-230-\ndrivers/net/dsa/mt7530.c:231:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-232-}\n--\ndrivers/net/dsa/mt7530.c=234=static void\ndrivers/net/dsa/mt7530.c:235:mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-236-{\ndrivers/net/dsa/mt7530.c:237:\tmt7530_rmw(priv, reg, val, val);\ndrivers/net/dsa/mt7530.c-238-}\n--\ndrivers/net/dsa/mt7530.c=240=static void\ndrivers/net/dsa/mt7530.c:241:mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-242-{\ndrivers/net/dsa/mt7530.c:243:\tmt7530_rmw(priv, reg, val, 0);\ndrivers/net/dsa/mt7530.c-244-}\n--\ndrivers/net/dsa/mt7530.c=246=static int\ndrivers/net/dsa/mt7530.c:247:mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)\ndrivers/net/dsa/mt7530.c-248-{\n--\ndrivers/net/dsa/mt7530.c-250-\tint ret;\ndrivers/net/dsa/mt7530.c:251:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-252-\n--\ndrivers/net/dsa/mt7530.c-254-\tval = ATC_BUSY | ATC_MAT(0) | cmd;\ndrivers/net/dsa/mt7530.c:255:\tmt7530_write(priv, MT7530_ATC, val);\ndrivers/net/dsa/mt7530.c-256-\ndrivers/net/dsa/mt7530.c-257-\tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7530_ATC);\ndrivers/net/dsa/mt7530.c:258:\tret = readx_poll_timeout(_mt7530_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-259-\t\t\t\t !(val \u0026 ATC_BUSY), 20, 20000);\n--\ndrivers/net/dsa/mt7530.c-267-\t */\ndrivers/net/dsa/mt7530.c:268:\tval = mt7530_read(priv, MT7530_ATC);\ndrivers/net/dsa/mt7530.c-269-\tif ((cmd == MT7530_FDB_READ) \u0026\u0026 (val \u0026 ATC_INVALID))\n--\ndrivers/net/dsa/mt7530.c=278=static void\ndrivers/net/dsa/mt7530.c:279:mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)\ndrivers/net/dsa/mt7530.c-280-{\n--\ndrivers/net/dsa/mt7530.c-285-\tfor (i = 0; i \u003c 3; i++) {\ndrivers/net/dsa/mt7530.c:286:\t\treg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));\ndrivers/net/dsa/mt7530.c-287-\n--\ndrivers/net/dsa/mt7530.c=304=static void\ndrivers/net/dsa/mt7530.c:305:mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,\ndrivers/net/dsa/mt7530.c-306-\t\t u8 port_mask, const u8 *mac,\n--\ndrivers/net/dsa/mt7530.c-330-\tfor (i = 0; i \u003c 3; i++)\ndrivers/net/dsa/mt7530.c:331:\t\tmt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);\ndrivers/net/dsa/mt7530.c-332-}\n--\ndrivers/net/dsa/mt7530.c-334-/* Set up switch core clock for MT7530 */\ndrivers/net/dsa/mt7530.c:335:static void mt7530_pll_setup(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-336-{\n--\ndrivers/net/dsa/mt7530.c=375=static void\ndrivers/net/dsa/mt7530.c:376:mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)\ndrivers/net/dsa/mt7530.c-377-{\ndrivers/net/dsa/mt7530.c:378:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c-379-\tu32 ncpo1, ssc_delta, xtal;\n--\ndrivers/net/dsa/mt7530.c-384-\tif (interface == PHY_INTERFACE_MODE_RGMII) {\ndrivers/net/dsa/mt7530.c:385:\t\tmt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,\ndrivers/net/dsa/mt7530.c-386-\t\t\t P6_INTF_MODE(0));\n--\ndrivers/net/dsa/mt7530.c-389-\ndrivers/net/dsa/mt7530.c:390:\tmt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));\ndrivers/net/dsa/mt7530.c-391-\ndrivers/net/dsa/mt7530.c:392:\txtal = mt7530_read(priv, MT753X_MTRAP) \u0026 MT7530_XTAL_MASK;\ndrivers/net/dsa/mt7530.c-393-\n--\ndrivers/net/dsa/mt7530.c=428=static void\ndrivers/net/dsa/mt7530.c:429:mt7531_pll_setup(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-430-{\n--\ndrivers/net/dsa/mt7530.c-435-\ndrivers/net/dsa/mt7530.c:436:\tval = mt7530_read(priv, MT7531_CREV);\ndrivers/net/dsa/mt7530.c:437:\ttop_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);\ndrivers/net/dsa/mt7530.c:438:\thwstrap = mt7530_read(priv, MT753X_TRAP);\ndrivers/net/dsa/mt7530.c-439-\tif ((val \u0026 CHIP_REV_M) \u003e 0)\n--\ndrivers/net/dsa/mt7530.c-446-\t/* Step 1 : Disable MT7531 COREPLL */\ndrivers/net/dsa/mt7530.c:447:\tval = mt7530_read(priv, MT7531_PLLGP_EN);\ndrivers/net/dsa/mt7530.c-448-\tval \u0026= ~EN_COREPLL;\ndrivers/net/dsa/mt7530.c:449:\tmt7530_write(priv, MT7531_PLLGP_EN, val);\ndrivers/net/dsa/mt7530.c-450-\ndrivers/net/dsa/mt7530.c-451-\t/* Step 2: switch to XTAL output */\ndrivers/net/dsa/mt7530.c:452:\tval = mt7530_read(priv, MT7531_PLLGP_EN);\ndrivers/net/dsa/mt7530.c-453-\tval |= SW_CLKSW;\ndrivers/net/dsa/mt7530.c:454:\tmt7530_write(priv, MT7531_PLLGP_EN, val);\ndrivers/net/dsa/mt7530.c-455-\ndrivers/net/dsa/mt7530.c:456:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-457-\tval \u0026= ~RG_COREPLL_EN;\ndrivers/net/dsa/mt7530.c:458:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-459-\ndrivers/net/dsa/mt7530.c-460-\t/* Step 3: disable PLLGP and enable program PLLGP */\ndrivers/net/dsa/mt7530.c:461:\tval = mt7530_read(priv, MT7531_PLLGP_EN);\ndrivers/net/dsa/mt7530.c-462-\tval |= SW_PLLGP;\ndrivers/net/dsa/mt7530.c:463:\tmt7530_write(priv, MT7531_PLLGP_EN, val);\ndrivers/net/dsa/mt7530.c-464-\ndrivers/net/dsa/mt7530.c-465-\t/* Step 4: program COREPLL output frequency to 500MHz */\ndrivers/net/dsa/mt7530.c:466:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-467-\tval \u0026= ~RG_COREPLL_POSDIV_M;\ndrivers/net/dsa/mt7530.c-468-\tval |= 2 \u003c\u003c RG_COREPLL_POSDIV_S;\ndrivers/net/dsa/mt7530.c:469:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-470-\tusleep_range(25, 35);\n--\ndrivers/net/dsa/mt7530.c-473-\tcase MT7531_XTAL_FSEL_25MHZ:\ndrivers/net/dsa/mt7530.c:474:\t\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-475-\t\tval \u0026= ~RG_COREPLL_SDM_PCW_M;\ndrivers/net/dsa/mt7530.c-476-\t\tval |= 0x140000 \u003c\u003c RG_COREPLL_SDM_PCW_S;\ndrivers/net/dsa/mt7530.c:477:\t\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-478-\t\tbreak;\ndrivers/net/dsa/mt7530.c-479-\tcase MT7531_XTAL_FSEL_40MHZ:\ndrivers/net/dsa/mt7530.c:480:\t\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-481-\t\tval \u0026= ~RG_COREPLL_SDM_PCW_M;\ndrivers/net/dsa/mt7530.c-482-\t\tval |= 0x190000 \u003c\u003c RG_COREPLL_SDM_PCW_S;\ndrivers/net/dsa/mt7530.c:483:\t\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-484-\t\tbreak;\n--\ndrivers/net/dsa/mt7530.c-487-\t/* Set feedback divide ratio update signal to high */\ndrivers/net/dsa/mt7530.c:488:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-489-\tval |= RG_COREPLL_SDM_PCW_CHG;\ndrivers/net/dsa/mt7530.c:490:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-491-\t/* Wait for at least 16 XTAL clocks */\n--\ndrivers/net/dsa/mt7530.c-494-\t/* Step 5: set feedback divide ratio update signal to low */\ndrivers/net/dsa/mt7530.c:495:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-496-\tval \u0026= ~RG_COREPLL_SDM_PCW_CHG;\ndrivers/net/dsa/mt7530.c:497:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-498-\ndrivers/net/dsa/mt7530.c-499-\t/* Enable 325M clock for SGMII */\ndrivers/net/dsa/mt7530.c:500:\tmt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);\ndrivers/net/dsa/mt7530.c-501-\ndrivers/net/dsa/mt7530.c-502-\t/* Enable 250SSC clock for RGMII */\ndrivers/net/dsa/mt7530.c:503:\tmt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);\ndrivers/net/dsa/mt7530.c-504-\ndrivers/net/dsa/mt7530.c-505-\t/* Step 6: Enable MT7531 PLL */\ndrivers/net/dsa/mt7530.c:506:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-507-\tval |= RG_COREPLL_EN;\ndrivers/net/dsa/mt7530.c:508:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-509-\ndrivers/net/dsa/mt7530.c:510:\tval = mt7530_read(priv, MT7531_PLLGP_EN);\ndrivers/net/dsa/mt7530.c-511-\tval |= EN_COREPLL;\ndrivers/net/dsa/mt7530.c:512:\tmt7530_write(priv, MT7531_PLLGP_EN, val);\ndrivers/net/dsa/mt7530.c-513-\tusleep_range(25, 35);\n--\ndrivers/net/dsa/mt7530.c=516=static void\ndrivers/net/dsa/mt7530.c:517:mt7530_mib_reset(struct dsa_switch *ds)\ndrivers/net/dsa/mt7530.c-518-{\ndrivers/net/dsa/mt7530.c:519:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c-520-\ndrivers/net/dsa/mt7530.c:521:\tmt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);\ndrivers/net/dsa/mt7530.c:522:\tmt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);\ndrivers/net/dsa/mt7530.c-523-}\ndrivers/net/dsa/mt7530.c-524-\ndrivers/net/dsa/mt7530.c:525:static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)\ndrivers/net/dsa/mt7530.c-526-{\n--\ndrivers/net/dsa/mt7530.c-529-\ndrivers/net/dsa/mt7530.c:530:static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum,\ndrivers/net/dsa/mt7530.c-531-\t\t\t\tu16 val)\n--\ndrivers/net/dsa/mt7530.c-535-\ndrivers/net/dsa/mt7530.c:536:static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port,\ndrivers/net/dsa/mt7530.c-537-\t\t\t int devad, int regnum)\n--\ndrivers/net/dsa/mt7530.c-541-\ndrivers/net/dsa/mt7530.c:542:static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-543-\t\t\t\tint regnum, u16 val)\n--\ndrivers/net/dsa/mt7530.c=548=static int\ndrivers/net/dsa/mt7530.c:549:mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-550-\t\t\tint regnum)\ndrivers/net/dsa/mt7530.c-551-{\ndrivers/net/dsa/mt7530.c:552:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-553-\tu32 reg, val;\n--\ndrivers/net/dsa/mt7530.c-557-\ndrivers/net/dsa/mt7530.c:558:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-559-\ndrivers/net/dsa/mt7530.c:560:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-561-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-568-\t MT7531_MDIO_DEV_ADDR(devad) | regnum;\ndrivers/net/dsa/mt7530.c:569:\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-570-\ndrivers/net/dsa/mt7530.c:571:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-572-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-579-\t MT7531_MDIO_DEV_ADDR(devad);\ndrivers/net/dsa/mt7530.c:580:\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-581-\ndrivers/net/dsa/mt7530.c:582:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-583-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-590-out:\ndrivers/net/dsa/mt7530.c:591:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-592-\n--\ndrivers/net/dsa/mt7530.c=596=static int\ndrivers/net/dsa/mt7530.c:597:mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-598-\t\t\t int regnum, u16 data)\ndrivers/net/dsa/mt7530.c-599-{\ndrivers/net/dsa/mt7530.c:600:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-601-\tu32 val, reg;\n--\ndrivers/net/dsa/mt7530.c-605-\ndrivers/net/dsa/mt7530.c:606:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-607-\ndrivers/net/dsa/mt7530.c:608:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-609-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-616-\t MT7531_MDIO_DEV_ADDR(devad) | regnum;\ndrivers/net/dsa/mt7530.c:617:\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-618-\ndrivers/net/dsa/mt7530.c:619:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-620-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-627-\t MT7531_MDIO_DEV_ADDR(devad) | data;\ndrivers/net/dsa/mt7530.c:628:\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-629-\ndrivers/net/dsa/mt7530.c:630:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-631-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-637-out:\ndrivers/net/dsa/mt7530.c:638:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-639-\n--\ndrivers/net/dsa/mt7530.c=643=static int\ndrivers/net/dsa/mt7530.c:644:mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)\ndrivers/net/dsa/mt7530.c-645-{\ndrivers/net/dsa/mt7530.c:646:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-647-\tint ret;\n--\ndrivers/net/dsa/mt7530.c-651-\ndrivers/net/dsa/mt7530.c:652:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-653-\ndrivers/net/dsa/mt7530.c:654:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-655-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-663-\ndrivers/net/dsa/mt7530.c:664:\tmt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-665-\ndrivers/net/dsa/mt7530.c:666:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-667-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-674-out:\ndrivers/net/dsa/mt7530.c:675:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-676-\n--\ndrivers/net/dsa/mt7530.c=680=static int\ndrivers/net/dsa/mt7530.c:681:mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,\ndrivers/net/dsa/mt7530.c-682-\t\t\t u16 data)\ndrivers/net/dsa/mt7530.c-683-{\ndrivers/net/dsa/mt7530.c:684:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-685-\tint ret;\n\n"
} |
| 5/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 19259 output: 36 thoughts: 169 Thoughts: **Analyzing the Path to Initialization** Okay, so I'm trying to figure out how this `mt7530_probe_common` function gets executed, particularly in a QEMU environment. It looks like the driver interacts with the hardware through either MDIO or MMIO. My initial thought is that `mt7530-mmio.c` registers a platform driver called `mt7988_platform_driver`. The crucial step appears to be that the `mt7988_probe` function *eventually* calls `mt7530_probe_common`. The key question now is, can I trigger this within QEMU? It seems plausible. If syzkaller crafts a device tree that includes the node property `econet,en7528-switch`, the platform driver should probe. During this probe, the code is going to map the MMIO region and, crucially, call `mt7530_probe_common`. Then, this function is supposed to do the initialization, and register a DSA switch. Now, the real question is: what does `mt7530_probe_common` actually *do*? I need to dig into that function to see if it's reachable and if it's doing what I expect. |
| 6/2 | 2026/07/11 07:46 | tool | grepper |
0mArgs:{
"Expression": "mt7530_probe_common",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "drivers/net/dsa/mt7530-mdio.c=148=mt7530_probe(struct mdio_device *mdiodev)\n--\ndrivers/net/dsa/mt7530-mdio.c-163-\ndrivers/net/dsa/mt7530-mdio.c:164:\tret = mt7530_probe_common(priv);\ndrivers/net/dsa/mt7530-mdio.c-165-\tif (ret)\n--\ndrivers/net/dsa/mt7530-mmio.c=31=mt7988_probe(struct platform_device *pdev)\n--\ndrivers/net/dsa/mt7530-mmio.c-43-\ndrivers/net/dsa/mt7530-mmio.c:44:\tret = mt7530_probe_common(priv);\ndrivers/net/dsa/mt7530-mmio.c-45-\tif (ret)\n--\ndrivers/net/dsa/mt7530.c=3519=int\ndrivers/net/dsa/mt7530.c:3520:mt7530_probe_common(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-3521-{\n--\ndrivers/net/dsa/mt7530.c-3550-}\ndrivers/net/dsa/mt7530.c:3551:EXPORT_SYMBOL_GPL(mt7530_probe_common);\ndrivers/net/dsa/mt7530.c-3552-\n--\ndrivers/net/dsa/mt7530.h=941=static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,\n--\ndrivers/net/dsa/mt7530.h-947-\ndrivers/net/dsa/mt7530.h:948:int mt7530_probe_common(struct mt7530_priv *priv);\ndrivers/net/dsa/mt7530.h-949-void mt7530_remove_common(struct mt7530_priv *priv);\n"
} |
| 7/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 20340 output: 44 thoughts: 32 Thoughts: Here's my attempt at summarizing the thought process, tailored for an expert audience: **Diving into the MT7530 Probe Function** Okay, time to dig into this MT7530 driver code. I'm going to start by taking a look at `mt7530_probe_common` within `drivers/net/dsa/mt7530.c`. This is usually the first place I start when debugging or understanding a driver's initialization sequence. I'm assuming this function is the core of the device probing process, and thus where the initial device setup and resource allocation is handled. I need to refresh my memory on the likely steps performed there: determining the device's hardware, requesting the correct clocks, maybe setting up the interrupt lines and I/O memory regions. I also need to see how the dsa driver is working within the scope of this device. I anticipate a fair amount of resource allocation, register access initialization, and probably some early PHY configuration calls to get this chip up and running. Let's see how they handle error checking and what the overall structure of this probe looks like. Hopefully, it's well-documented! |
| 8/2 | 2026/07/11 07:46 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530.c",
"FirstLine": 3519,
"LineCount": 100
}Results: {
"Contents": "3519:\tint\n3520:\tmt7530_probe_common(struct mt7530_priv *priv)\n3521:\t{\n3522:\t\tstruct device *dev = priv-\u003edev;\n3523:\t\n3524:\t\tpriv-\u003eds = devm_kzalloc(dev, sizeof(*priv-\u003eds), GFP_KERNEL);\n3525:\t\tif (!priv-\u003eds)\n3526:\t\t\treturn -ENOMEM;\n3527:\t\n3528:\t\tpriv-\u003eds-\u003edev = dev;\n3529:\t\tpriv-\u003eds-\u003enum_ports = MT7530_NUM_PORTS;\n3530:\t\n3531:\t\t/* Get the hardware identifier from the devicetree node.\n3532:\t\t * We will need it for some of the clock and regulator setup.\n3533:\t\t */\n3534:\t\tpriv-\u003einfo = of_device_get_match_data(dev);\n3535:\t\tif (!priv-\u003einfo)\n3536:\t\t\treturn -EINVAL;\n3537:\t\n3538:\t\tpriv-\u003eid = priv-\u003einfo-\u003eid;\n3539:\t\tpriv-\u003edev = dev;\n3540:\t\tpriv-\u003eds-\u003epriv = priv;\n3541:\t\tpriv-\u003eds-\u003eops = \u0026mt7530_switch_ops;\n3542:\t\tpriv-\u003eds-\u003ephylink_mac_ops = \u0026mt753x_phylink_mac_ops;\n3543:\t\tmutex_init(\u0026priv-\u003ereg_mutex);\n3544:\t\tspin_lock_init(\u0026priv-\u003estats_lock);\n3545:\t\tINIT_DELAYED_WORK(\u0026priv-\u003estats_work, mt7530_stats_poll);\n3546:\t\n3547:\t\tdev_set_drvdata(dev, priv);\n3548:\t\n3549:\t\treturn 0;\n3550:\t}\n3551:\tEXPORT_SYMBOL_GPL(mt7530_probe_common);\n3552:\t\n3553:\tvoid\n3554:\tmt7530_remove_common(struct mt7530_priv *priv)\n3555:\t{\n3556:\t\tif (priv-\u003eirq_domain)\n3557:\t\t\tmt7530_free_mdio_irq(priv);\n3558:\t\n3559:\t\tdsa_unregister_switch(priv-\u003eds);\n3560:\t\n3561:\t\tmutex_destroy(\u0026priv-\u003ereg_mutex);\n3562:\t}\n3563:\tEXPORT_SYMBOL_GPL(mt7530_remove_common);\n3564:\t\n3565:\tMODULE_AUTHOR(\"Sean Wang \u003csean.wang@mediatek.com\u003e\");\n3566:\tMODULE_DESCRIPTION(\"Driver for Mediatek MT7530 Switch\");\n3567:\tMODULE_LICENSE(\"GPL\");\n"
} |
| 9/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 21437 output: 44 thoughts: 71 Thoughts: **My Initial Assessment of the Code** Okay, so looking at `mt7530_probe_common`, it seems pretty straightforward. All it's doing is allocating some memory and setting up some data structures. It's not actually the bit where the switch gets registered with the DSA subsystem, which is good to know. The question is, where is that vital `dsa_register_switch` function called? Time to go hunting... Let's see, the probe function for this hardware is located in `mt7988_probe` within the `mt7530-mmio.c` file. That's the logical place to look for the switch registration to occur. |
| 10/2 | 2026/07/11 07:46 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530-mmio.c",
"FirstLine": 31,
"LineCount": 50
}Results: {
"Contents": " 31:\tmt7988_probe(struct platform_device *pdev)\n 32:\t{\n 33:\t\tstruct mt7530_priv *priv;\n 34:\t\tvoid __iomem *base_addr;\n 35:\t\tint ret;\n 36:\t\n 37:\t\tpriv = devm_kzalloc(\u0026pdev-\u003edev, sizeof(*priv), GFP_KERNEL);\n 38:\t\tif (!priv)\n 39:\t\t\treturn -ENOMEM;\n 40:\t\n 41:\t\tpriv-\u003ebus = NULL;\n 42:\t\tpriv-\u003edev = \u0026pdev-\u003edev;\n 43:\t\n 44:\t\tret = mt7530_probe_common(priv);\n 45:\t\tif (ret)\n 46:\t\t\treturn ret;\n 47:\t\n 48:\t\tpriv-\u003erstc = devm_reset_control_get(\u0026pdev-\u003edev, NULL);\n 49:\t\tif (IS_ERR(priv-\u003erstc)) {\n 50:\t\t\tdev_err(\u0026pdev-\u003edev, \"Couldn't get our reset line\\n\");\n 51:\t\t\treturn PTR_ERR(priv-\u003erstc);\n 52:\t\t}\n 53:\t\n 54:\t\tbase_addr = devm_platform_ioremap_resource(pdev, 0);\n 55:\t\tif (IS_ERR(base_addr)) {\n 56:\t\t\tdev_err(\u0026pdev-\u003edev, \"cannot request I/O memory space\\n\");\n 57:\t\t\treturn -ENXIO;\n 58:\t\t}\n 59:\t\n 60:\t\tpriv-\u003eregmap = devm_regmap_init_mmio(\u0026pdev-\u003edev, base_addr,\n 61:\t\t\t\t\t\t \u0026sw_regmap_config);\n 62:\t\tif (IS_ERR(priv-\u003eregmap))\n 63:\t\t\treturn PTR_ERR(priv-\u003eregmap);\n 64:\t\n 65:\t\treturn dsa_register_switch(priv-\u003eds);\n 66:\t}\n 67:\t\n 68:\tstatic void mt7988_remove(struct platform_device *pdev)\n 69:\t{\n 70:\t\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\n 71:\t\n 72:\t\tif (priv)\n 73:\t\t\tmt7530_remove_common(priv);\n 74:\t}\n 75:\t\n 76:\tstatic void mt7988_shutdown(struct platform_device *pdev)\n 77:\t{\n 78:\t\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\n 79:\t\n 80:\t\tif (!priv)\n"
} |
| 11/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 22414 output: 43 thoughts: 120 Thoughts: **Analyzing the MT7988 Switch Probe** Okay, so `mt7988_probe` calls `dsa_register_switch` – that's the standard entry point. Right, and `dsa_register_switch` then takes over, initiating the switch's setup functions. This is where things get interesting, because those setup functions are inevitably going to involve hardware accesses, poking at the MMIO regions. Now, the big question is, what happens if there's *no* actual hardware present? Specifically, in the context of fuzzing like we do, with no actual switch present? Syzkaller, in its brilliance, provides these fake MMIO regions, usually filled with either zeroes or ones. Will the probe succeed in this scenario? I need to look at `mt7988_setup` – that's the setup function specific to `ID_EN7528`, that will give me the answer. Time to dig in and see what's being read and written and if the error handling is robust enough. This will tell me if the probing will fail or whether we will have a false positive. |
| 12/2 | 2026/07/11 07:46 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530.c",
"FirstLine": 3347,
"LineCount": 50
}Results: {
"Contents": "3347:\t/* The EN7528 LAN ports are integrated GPHYs at MDIO addresses 9..12 (switch\n3348:\t * ports 1..4) on the switch internal MDIO bus, reachable only through the PHY\n3349:\t * indirect access registers. There is no mdiodev to derive the addresses from.\n3350:\t */\n3351:\t#define EN7528_GPHY_BASE\t\t9\n3352:\t#define EN7528_NUM_GPHYS\t\t4\n3353:\t\n3354:\tstatic int mt7988_setup(struct dsa_switch *ds)\n3355:\t{\n3356:\t\tstruct mt7530_priv *priv = ds-\u003epriv;\n3357:\t\tint i;\n3358:\t\n3359:\t\t/* Reset the switch */\n3360:\t\treset_control_assert(priv-\u003erstc);\n3361:\t\tusleep_range(20, 50);\n3362:\t\treset_control_deassert(priv-\u003erstc);\n3363:\t\tusleep_range(20, 50);\n3364:\t\n3365:\t\t/* AN7583 require additional tweak to CONN_CFG */\n3366:\t\tif (priv-\u003eid == ID_AN7583)\n3367:\t\t\tmt7530_rmw(priv, AN7583_GEPHY_CONN_CFG,\n3368:\t\t\t\t AN7583_CSR_DPHY_CKIN_SEL |\n3369:\t\t\t\t AN7583_CSR_PHY_CORE_REG_CLK_SEL |\n3370:\t\t\t\t AN7583_CSR_ETHER_AFE_PWD,\n3371:\t\t\t\t AN7583_CSR_DPHY_CKIN_SEL |\n3372:\t\t\t\t AN7583_CSR_PHY_CORE_REG_CLK_SEL |\n3373:\t\t\t\t FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0));\n3374:\t\n3375:\t\t/* Reset the switch PHYs */\n3376:\t\tmt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);\n3377:\t\n3378:\t\t/* The EN7528 LAN GPHYs advertise EEE by default, but negotiating EEE\n3379:\t\t * with common link partners (e.g. Realtek GbE NICs) results in an\n3380:\t\t * unstable link with dropped frames. Disable EEE advertisement on\n3381:\t\t * them.\n3382:\t\t */\n3383:\t\tif (priv-\u003eid == ID_EN7528)\n3384:\t\t\tfor (i = EN7528_GPHY_BASE;\n3385:\t\t\t i \u003c EN7528_GPHY_BASE + EN7528_NUM_GPHYS; i++)\n3386:\t\t\t\tmt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN,\n3387:\t\t\t\t\t\t\t MDIO_AN_EEE_ADV, 0);\n3388:\t\n3389:\t\treturn mt7531_setup_common(ds);\n3390:\t}\n3391:\t\n3392:\tstatic const struct dsa_switch_ops mt7530_switch_ops = {\n3393:\t\t.get_tag_protocol\t= mtk_get_tag_protocol,\n3394:\t\t.setup\t\t\t= mt753x_setup,\n3395:\t\t.teardown\t\t= mt753x_teardown,\n3396:\t\t.preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port,\n"
} |
| 13/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 23823 output: 36 thoughts: 40 Thoughts: Here's my thought process, as an expert in this embedded systems networking context: **Analyzing the MT7988 and MT7531 Initialization Sequence** Okay, so I'm looking at the `mt7988_setup` function, and it immediately calls `mt7531_setup_common(ds)`. The 'ds' likely refers to a device-specific data structure. Alright, this is a common pattern – we have a specific setup function for the MT7988, but it leverages a more generic initialization routine for the MT7531, which is probably the underlying switch chip. It makes sense to share code like this. Now, to truly understand what's happening, I need to dive into `mt7531_setup_common`. I need to understand what it's doing with this device structure (ds). Is it configuring the PHYs? Setting up registers? Initializing the MAC addresses? I'm betting it's doing the low-level register setup and bringing the switch up into a known state. So, let's go check that routine. I'll be looking for things like clock configuration, PHY initialization, and possibly some basic port configuration as a starting point. |
| 14/2 | 2026/07/11 07:46 | tool | grepper |
0mArgs:{
"Expression": "mt7531_setup_common",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "drivers/net/dsa/mt7530.c=2635=static int\ndrivers/net/dsa/mt7530.c:2636:mt7531_setup_common(struct dsa_switch *ds)\ndrivers/net/dsa/mt7530.c-2637-{\n--\ndrivers/net/dsa/mt7530.c=2707=mt7531_setup(struct dsa_switch *ds)\n--\ndrivers/net/dsa/mt7530.c-2794-\ndrivers/net/dsa/mt7530.c:2795:\tret = mt7531_setup_common(ds);\ndrivers/net/dsa/mt7530.c-2796-\tif (ret)\n--\ndrivers/net/dsa/mt7530.c=3354=static int mt7988_setup(struct dsa_switch *ds)\n--\ndrivers/net/dsa/mt7530.c-3388-\ndrivers/net/dsa/mt7530.c:3389:\treturn mt7531_setup_common(ds);\ndrivers/net/dsa/mt7530.c-3390-}\n"
} |
| 15/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 24500 output: 43 thoughts: 15 Thoughts: Okay, let's dive into this. Here's my take on those thoughts, as if they're my own: **Analyzing the `mt7531_setup_common` Function** Alright, I'm going to take a look at the `mt7531_setup_common` function. Given the naming convention, I'm expecting this is going to be a common setup routine specifically for the MT7531 chip. I need to understand how this function initializes and configures the core aspects of this particular switch. I'm going to be paying close attention to the order in which things happen, any register writes, and what kind of assumptions or dependencies this function has on the underlying hardware and the overall driver context. This likely sets up the basic clocking, reset sequences, and default configurations necessary for the switch to function correctly before more specific features or port settings are applied. I'll need to look for any potential areas of concern, like race conditions, incorrect register values, or lack of error handling. Ultimately, I'm assessing this for overall code quality, best practices, and whether I can trust this function to be a solid foundation for the driver. |
| 16/2 | 2026/07/11 07:46 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530.c",
"FirstLine": 2635,
"LineCount": 50
}Results: {
"Contents": "2635:\tstatic int\n2636:\tmt7531_setup_common(struct dsa_switch *ds)\n2637:\t{\n2638:\t\tstruct mt7530_priv *priv = ds-\u003epriv;\n2639:\t\tint ret, i;\n2640:\t\n2641:\t\tds-\u003eassisted_learning_on_cpu_port = true;\n2642:\t\tds-\u003euntag_vlan_aware_bridge_pvid = true;\n2643:\t\tds-\u003emtu_enforcement_ingress = true;\n2644:\t\tds-\u003eageing_time_min = 2 * 1000;\n2645:\t\tds-\u003eageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000;\n2646:\t\n2647:\t\tmt753x_trap_frames(priv);\n2648:\t\n2649:\t\t/* Enable and reset MIB counters */\n2650:\t\tmt7530_mib_reset(ds);\n2651:\t\n2652:\t\t/* Disable flooding on all ports */\n2653:\t\tmt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |\n2654:\t\t\t UNU_FFP_MASK);\n2655:\t\n2656:\t\tfor (i = 0; i \u003c priv-\u003eds-\u003enum_ports; i++) {\n2657:\t\t\t/* Clear link settings and enable force mode to force link down\n2658:\t\t\t * on all ports until they're enabled later.\n2659:\t\t\t */\n2660:\t\t\tmt7530_rmw(priv, MT753X_PMCR_P(i),\n2661:\t\t\t\t PMCR_LINK_SETTINGS_MASK |\n2662:\t\t\t\t MT753X_FORCE_MODE(priv-\u003eid),\n2663:\t\t\t\t MT753X_FORCE_MODE(priv-\u003eid));\n2664:\t\n2665:\t\t\t/* Disable forwarding by default on all ports */\n2666:\t\t\tmt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,\n2667:\t\t\t\t PCR_MATRIX_CLR);\n2668:\t\n2669:\t\t\t/* Disable learning by default on all ports */\n2670:\t\t\tmt7530_set(priv, MT7530_PSC_P(i), SA_DIS);\n2671:\t\n2672:\t\t\tmt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);\n2673:\t\n2674:\t\t\tif (dsa_is_cpu_port(ds, i)) {\n2675:\t\t\t\tmt753x_cpu_port_enable(ds, i);\n2676:\t\t\t} else {\n2677:\t\t\t\tmt7530_port_disable(ds, i);\n2678:\t\n2679:\t\t\t\t/* Set default PVID to 0 on all user ports */\n2680:\t\t\t\tmt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,\n2681:\t\t\t\t\t G0_PORT_VID_DEF);\n2682:\t\t\t}\n2683:\t\n2684:\t\t\t/* Enable consistent egress tag */\n"
} |
| 17/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 25722 output: 43 thoughts: 794 Thoughts: **Analyzing the Fuzzing Potential of This MMIO Driver** Okay, so I'm looking at this code and trying to figure out if it's fuzzable with syzkaller. The code is interacting with MMIO registers, which is interesting. If syzkaller maps dummy memory, these reads and writes will likely succeed, albeit with dummy values. That's a good starting point. Now, there's a polling loop in `mt7531_ind_c45_phy_write`. It's reading a register and waiting for a specific bit to clear. If the read returns 0 (due to the dummy memory), the polling loop might succeed immediately. If it returns `0xffffffff`, which is another dummy value that could arise, the loop might time out after 100ms. In either of these cases, it won't crash the system, and it will keep going. Even if there's an error, `mt7988_setup` doesn't seem to check the return value of `mt7531_ind_c45_phy_write`. So, it just continues to the next step. Then, `mt7531_setup_common(ds)` would be called. The key thing here is that `mt7531_setup_common` either succeeds or fails gracefully, too. Therefore, the switch *will* get registered! Syzkaller can then use netlink to interact with the DSA switch, configuring things like bridges, and so on. The bigger question is this: is this driver *actually* reachable in a virtualized environment? The prompt says to return "WorthFuzzing=false" if it's impossible. Now, what's interesting is this is a pure MMIO driver that only works with hardware. Syzkaller can generate a device tree that matches `econet,en7528-switch`. The driver will probe, map the dummy memory, and register a DSA switch. Then syzkaller can start fuzzing. Typically, hardware drivers that rely on specific register values or behavior will fail to probe. However, in this case, `mt7988_setup` doesn't seem to have strict checks that would cause a failure if the hardware isn't present. I need to double-check `mt7530_probe_common` and `mt7988_probe` again to make absolutely sure they don't contain any hardware ID checks that would kill the probing process. But at this point, it looks promising. |
| 18/2 | 2026/07/11 07:46 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530.c",
"FirstLine": 3519,
"LineCount": 50
}Results: {
"Contents": "3519:\tint\n3520:\tmt7530_probe_common(struct mt7530_priv *priv)\n3521:\t{\n3522:\t\tstruct device *dev = priv-\u003edev;\n3523:\t\n3524:\t\tpriv-\u003eds = devm_kzalloc(dev, sizeof(*priv-\u003eds), GFP_KERNEL);\n3525:\t\tif (!priv-\u003eds)\n3526:\t\t\treturn -ENOMEM;\n3527:\t\n3528:\t\tpriv-\u003eds-\u003edev = dev;\n3529:\t\tpriv-\u003eds-\u003enum_ports = MT7530_NUM_PORTS;\n3530:\t\n3531:\t\t/* Get the hardware identifier from the devicetree node.\n3532:\t\t * We will need it for some of the clock and regulator setup.\n3533:\t\t */\n3534:\t\tpriv-\u003einfo = of_device_get_match_data(dev);\n3535:\t\tif (!priv-\u003einfo)\n3536:\t\t\treturn -EINVAL;\n3537:\t\n3538:\t\tpriv-\u003eid = priv-\u003einfo-\u003eid;\n3539:\t\tpriv-\u003edev = dev;\n3540:\t\tpriv-\u003eds-\u003epriv = priv;\n3541:\t\tpriv-\u003eds-\u003eops = \u0026mt7530_switch_ops;\n3542:\t\tpriv-\u003eds-\u003ephylink_mac_ops = \u0026mt753x_phylink_mac_ops;\n3543:\t\tmutex_init(\u0026priv-\u003ereg_mutex);\n3544:\t\tspin_lock_init(\u0026priv-\u003estats_lock);\n3545:\t\tINIT_DELAYED_WORK(\u0026priv-\u003estats_work, mt7530_stats_poll);\n3546:\t\n3547:\t\tdev_set_drvdata(dev, priv);\n3548:\t\n3549:\t\treturn 0;\n3550:\t}\n3551:\tEXPORT_SYMBOL_GPL(mt7530_probe_common);\n3552:\t\n3553:\tvoid\n3554:\tmt7530_remove_common(struct mt7530_priv *priv)\n3555:\t{\n3556:\t\tif (priv-\u003eirq_domain)\n3557:\t\t\tmt7530_free_mdio_irq(priv);\n3558:\t\n3559:\t\tdsa_unregister_switch(priv-\u003eds);\n3560:\t\n3561:\t\tmutex_destroy(\u0026priv-\u003ereg_mutex);\n3562:\t}\n3563:\tEXPORT_SYMBOL_GPL(mt7530_remove_common);\n3564:\t\n3565:\tMODULE_AUTHOR(\"Sean Wang \u003csean.wang@mediatek.com\u003e\");\n3566:\tMODULE_DESCRIPTION(\"Driver for Mediatek MT7530 Switch\");\n3567:\tMODULE_LICENSE(\"GPL\");\n"
} |
| 19/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 27877 output: 43 thoughts: 70 Thoughts: Okay, let me think this through. **Analyzing the MT7530 Driver Probe Function** Hmm, so the `mt7530_probe_common` function… right, it doesn't seem to be checking any hardware ID registers, which is a bit unusual. Okay, that's noted. Now, where are those IDs being validated or verified? Let me see… what about `dsa_register_switch`? Does *that* function trigger any setup routines? Ah, yes. Got it. `dsa_register_switch` calls `ds->ops->setup`. And looking at the MT753x driver, the `setup` operation is defined as `mt753x_setup`. Good. So the initialization likely occurs there, or possibly further down the call chain within that setup function. I'll need to dig into `mt753x_setup` to see how that function proceeds, and whether hardware ID checks are performed there. That's where I should focus next. |
| 20/2 | 2026/07/11 07:46 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530.c",
"FirstLine": 3286,
"LineCount": 50
}Results: {
"Contents": "3286:\t\n3287:\t\tif (operational)\n3288:\t\t\tpriv-\u003eactive_cpu_ports |= mask;\n3289:\t\telse\n3290:\t\t\tpriv-\u003eactive_cpu_ports \u0026= ~mask;\n3291:\t\n3292:\t\tif (priv-\u003eactive_cpu_ports) {\n3293:\t\t\tval = MT7530_CPU_EN |\n3294:\t\t\t MT7530_CPU_PORT(__ffs(priv-\u003eactive_cpu_ports));\n3295:\t\t}\n3296:\t\n3297:\t\tmt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);\n3298:\t}\n3299:\t\n3300:\tstatic int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port,\n3301:\t\t\t\t\t struct tc_tbf_qopt_offload *qopt)\n3302:\t{\n3303:\t\tstruct tc_tbf_qopt_offload_replace_params *p = \u0026qopt-\u003ereplace_params;\n3304:\t\tstruct mt7530_priv *priv = ds-\u003epriv;\n3305:\t\tu32 rate = 0;\n3306:\t\n3307:\t\tswitch (qopt-\u003ecommand) {\n3308:\t\tcase TC_TBF_REPLACE:\n3309:\t\t\trate = div_u64(p-\u003erate.rate_bytes_ps, 1000) \u003c\u003c 3; /* kbps */\n3310:\t\t\tfallthrough;\n3311:\t\tcase TC_TBF_DESTROY: {\n3312:\t\t\tu32 val, tick;\n3313:\t\n3314:\t\t\tmt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK,\n3315:\t\t\t\t EGR_BC_CRC_IPG_PREAMBLE);\n3316:\t\n3317:\t\t\t/* if rate is greater than 10Mbps tick is 1/32 ms,\n3318:\t\t\t * 1ms otherwise\n3319:\t\t\t */\n3320:\t\t\ttick = rate \u003e 10000 ? 2 : 7;\n3321:\t\t\tval = FIELD_PREP(ERLCR_CIR_MASK, (rate \u003e\u003e 5)) |\n3322:\t\t\t FIELD_PREP(ERLCR_EN_MASK, !!rate) |\n3323:\t\t\t FIELD_PREP(ERLCR_EXP_MASK, tick) |\n3324:\t\t\t ERLCR_TBF_MODE_MASK |\n3325:\t\t\t FIELD_PREP(ERLCR_MANT_MASK, 0xf);\n3326:\t\t\tmt7530_write(priv, MT753X_ERLCR_P(port), val);\n3327:\t\t\tbreak;\n3328:\t\t}\n3329:\t\tdefault:\n3330:\t\t\treturn -EOPNOTSUPP;\n3331:\t\t}\n3332:\t\n3333:\t\treturn 0;\n3334:\t}\n3335:\t\n"
} |
| 21/2 | 2026/07/11 07:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 29067 output: 34 thoughts: 15 Thoughts: Okay, here's my interpretation of that thought process, tailored for an expert audience, and written in the first person: **Quick Check: mt753x_setup** Alright, I'm diving in here, but before I get too deep into this specific area, I need to make a mental note – *mt753x_setup*. It's a key function in this subsystem, and experience has taught me that overlooking its initial configuration can lead to some really nasty debugging sessions down the road. I've been burned by that before. I know it's probably been checked recently, but it never hurts to double-check a configuration function, especially one that's fundamental to device initialization. I need to make sure I haven't missed any potential subtle interactions with newer features or upstream changes, any of which might alter expected register settings or required timing. That setup function could also be responsible for ensuring any hardware pre-requisites are met. A quick review of its logic will save a ton of time. Better safe than sorry, I'll refresh my understanding of how it's setting up the PHY and the relevant clocks. Back to the plan after that. |
| 22/2 | 2026/07/11 07:47 | tool | grepper |
0mArgs:{
"Expression": "mt753x_setup",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "drivers/net/dsa/mt7530.c=3209=static int\ndrivers/net/dsa/mt7530.c:3210:mt753x_setup(struct dsa_switch *ds)\ndrivers/net/dsa/mt7530.c-3211-{\n--\ndrivers/net/dsa/mt7530.c=3300=static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/mt7530.c-3335-\ndrivers/net/dsa/mt7530.c:3336:static int mt753x_setup_tc(struct dsa_switch *ds, int port,\ndrivers/net/dsa/mt7530.c-3337-\t\t\t enum tc_setup_type type, void *type_data)\n--\ndrivers/net/dsa/mt7530.c=3392=static const struct dsa_switch_ops mt7530_switch_ops = {\ndrivers/net/dsa/mt7530.c-3393-\t.get_tag_protocol\t= mtk_get_tag_protocol,\ndrivers/net/dsa/mt7530.c:3394:\t.setup\t\t\t= mt753x_setup,\ndrivers/net/dsa/mt7530.c-3395-\t.teardown\t\t= mt753x_teardown,\n--\ndrivers/net/dsa/mt7530.c-3427-\t.conduit_state_change\t= mt753x_conduit_state_change,\ndrivers/net/dsa/mt7530.c:3428:\t.port_setup_tc\t\t= mt753x_setup_tc,\ndrivers/net/dsa/mt7530.c-3429-\t.port_hsr_join\t\t= dsa_port_simple_hsr_join,\n"
} |
| 23/2 | 2026/07/11 07:47 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 29894 output: 43 thoughts: 13 Thoughts: Okay, here's my interpretation of that thought process, tailored for an expert audience, and written in the first person: **Analyzing the `mt753x_setup` Function** Alright, let's dive into the `mt753x_setup` function. The first thing I'm doing is a mental inventory of what I already know about this driver or the chipset it pertains to. I'm recalling any past experiences with MTK switch configurations or similar setups. Are there any known quirks? Common pitfalls? Does this align with the typical initialization sequence? As I read, I'm mentally checking each line of code against my understanding of switch hardware, register maps, and likely initialization procedures. Are they addressing things in the correct order? Are the clock settings plausible? I'm looking for any obvious red flags, potential race conditions, or anything that seems out of the ordinary, and I am cross checking this new data with the knowledge I already possess. I am quickly looking for the core components that are being set up: PHYs, internal switch fabric configuration, VLAN settings, QoS parameters... I'll start with the most critical paths and data structures. Are there any hardware-specific dependencies I need to be aware of? Are there any potential issues related to DMA transfers, interrupt handling, or memory management? I'm keeping a constant internal log of where I can find more context or information on specific operations. I'm looking for function calls to related APIs or driver-specific structures that I may want to examine in depth. The overall goal is to understand how the `mt753x_setup` function is integrating the hardware configuration with any higher-level abstractions that might be used by the OS. |
| 24/2 | 2026/07/11 07:47 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530.c",
"FirstLine": 3209,
"LineCount": 50
}Results: {
"Contents": "3209:\tstatic int\n3210:\tmt753x_setup(struct dsa_switch *ds)\n3211:\t{\n3212:\t\tstruct mt7530_priv *priv = ds-\u003epriv;\n3213:\t\tint ret = priv-\u003einfo-\u003esw_setup(ds);\n3214:\t\tint i;\n3215:\t\n3216:\t\tif (ret)\n3217:\t\t\treturn ret;\n3218:\t\n3219:\t\tret = mt7530_setup_irq(priv);\n3220:\t\tif (ret)\n3221:\t\t\treturn ret;\n3222:\t\n3223:\t\tret = mt7530_setup_mdio(priv);\n3224:\t\tif (ret)\n3225:\t\t\treturn ret;\n3226:\t\n3227:\t\t/* Initialise the PCS devices */\n3228:\t\tfor (i = 0; i \u003c priv-\u003eds-\u003enum_ports; i++) {\n3229:\t\t\tpriv-\u003epcs[i].pcs.ops = priv-\u003einfo-\u003epcs_ops;\n3230:\t\t\tpriv-\u003epcs[i].priv = priv;\n3231:\t\t\tpriv-\u003epcs[i].port = i;\n3232:\t\t}\n3233:\t\n3234:\t\tif (priv-\u003ecreate_sgmii)\n3235:\t\t\tret = priv-\u003ecreate_sgmii(priv);\n3236:\t\n3237:\t\tif (ret \u0026\u0026 priv-\u003eirq_domain)\n3238:\t\t\tmt7530_free_mdio_irq(priv);\n3239:\t\n3240:\t\tif (!ret \u0026\u0026 priv-\u003ebus) {\n3241:\t\t\tmt7530_stats_refresh(priv);\n3242:\t\t\tschedule_delayed_work(\u0026priv-\u003estats_work,\n3243:\t\t\t\t\t MT7530_STATS_POLL_INTERVAL);\n3244:\t\t}\n3245:\t\n3246:\t\treturn ret;\n3247:\t}\n3248:\t\n3249:\tstatic void\n3250:\tmt753x_teardown(struct dsa_switch *ds)\n3251:\t{\n3252:\t\tstruct mt7530_priv *priv = ds-\u003epriv;\n3253:\t\n3254:\t\tif (priv-\u003ebus)\n3255:\t\t\tcancel_delayed_work_sync(\u0026priv-\u003estats_work);\n3256:\t}\n3257:\t\n3258:\tstatic int mt753x_set_mac_eee(struct dsa_switch *ds, int port,\n"
} |
| 25/2 | 2026/07/11 07:47 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 31020 output: 37 thoughts: 115 Thoughts: **Analyzing the Network Switch Initialization** Okay, so I'm digging into this network switch initialization, specifically for the `ID_EN7528` configuration. I see that `priv->info->sw_setup(ds)` is set to `mt7988_setup`, which is expected. We know that `mt7988_setup` is a key function in this process. Now, as I recall from previous debugging, `mt7988_setup` then calls `mt7531_setup_common`. The function calls `mt7531_setup_common` which, if I remember correctly, involves a good amount of MMIO register access which, at this point, all seemed to have succeeded. The next steps after that initial setup are `mt7530_setup_irq` and `mt7530_setup_mdio`. Given where we are now, let's turn our attention to `mt7530_setup_mdio` and see what it's doing. |
| 26/2 | 2026/07/11 07:47 | tool | grepper |
0mArgs:{
"Expression": "mt7530_setup_mdio",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "drivers/net/dsa/mt7530.c=2269=static void\ndrivers/net/dsa/mt7530.c:2270:mt7530_setup_mdio_irq(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-2271-{\n--\ndrivers/net/dsa/mt7530.c=2370=static int\ndrivers/net/dsa/mt7530.c:2371:mt7530_setup_mdio(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-2372-{\n--\ndrivers/net/dsa/mt7530.c-2404-\tif (priv-\u003eirq_domain \u0026\u0026 !mnp)\ndrivers/net/dsa/mt7530.c:2405:\t\tmt7530_setup_mdio_irq(priv);\ndrivers/net/dsa/mt7530.c-2406-\n--\ndrivers/net/dsa/mt7530.c=3210=mt753x_setup(struct dsa_switch *ds)\n--\ndrivers/net/dsa/mt7530.c-3222-\ndrivers/net/dsa/mt7530.c:3223:\tret = mt7530_setup_mdio(priv);\ndrivers/net/dsa/mt7530.c-3224-\tif (ret)\n"
} |
| 27/2 | 2026/07/11 07:47 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 31812 output: 43 thoughts: 16 Thoughts: Okay, let's dive into this `mt7530_setup_mdio` function. I see it's probably part of a driver or some low-level network interface code, judging by the name. My initial thought is to quickly establish the context. What's the overall goal of this function? From the name, I'm guessing it's setting up the MDIO interface, which is a common serial interface for accessing PHY (physical layer) registers. Knowing this, I want to quickly understand the sequence of operations. Is it initializing the MDIO controller? Configuring the clock? Mapping the registers? It's all about efficient PHY communication. I anticipate the code will involve writing to specific registers to control the MDIO clock frequency, the MDIO mode (e.g., bit-banging vs. hardware acceleration), and potentially enabling the MDIO controller. I’ll be looking for any potential error handling or timeouts, especially when waiting for MDIO transactions to complete. Are they using any hardware-specific MDIO commands? Any bit-shifting or masking operations to isolate and manipulate specific register bits? I'll probably scrutinize any loops or delays very closely, because these are classic areas for potential timing issues or lockups. I’m also interested in how they're handling different MDIO address spaces if they're supporting multiple PHYs. Is there a clear separation of concerns in the code, or is everything tightly coupled? And, of course, I'll be keeping an eye out for any undocumented or unusual register accesses that might represent a vendor-specific hack or optimization. Let's see what gems are in there! |
| 28/2 | 2026/07/11 07:47 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530.c",
"FirstLine": 2370,
"LineCount": 50
}Results: {
"Contents": "2370:\tstatic int\n2371:\tmt7530_setup_mdio(struct mt7530_priv *priv)\n2372:\t{\n2373:\t\tstruct device_node *mnp, *np = priv-\u003edev-\u003eof_node;\n2374:\t\tstruct dsa_switch *ds = priv-\u003eds;\n2375:\t\tstruct device *dev = priv-\u003edev;\n2376:\t\tstruct mii_bus *bus;\n2377:\t\tstatic int idx;\n2378:\t\tint ret = 0;\n2379:\t\n2380:\t\tmnp = of_get_child_by_name(np, \"mdio\");\n2381:\t\n2382:\t\tif (mnp \u0026\u0026 !of_device_is_available(mnp))\n2383:\t\t\tgoto out;\n2384:\t\n2385:\t\tbus = devm_mdiobus_alloc(dev);\n2386:\t\tif (!bus) {\n2387:\t\t\tret = -ENOMEM;\n2388:\t\t\tgoto out;\n2389:\t\t}\n2390:\t\n2391:\t\tif (!mnp)\n2392:\t\t\tds-\u003euser_mii_bus = bus;\n2393:\t\n2394:\t\tbus-\u003epriv = priv;\n2395:\t\tbus-\u003ename = KBUILD_MODNAME \"-mii\";\n2396:\t\tsnprintf(bus-\u003eid, MII_BUS_ID_SIZE, KBUILD_MODNAME \"-%d\", idx++);\n2397:\t\tbus-\u003eread = mt753x_phy_read_c22;\n2398:\t\tbus-\u003ewrite = mt753x_phy_write_c22;\n2399:\t\tbus-\u003eread_c45 = mt753x_phy_read_c45;\n2400:\t\tbus-\u003ewrite_c45 = mt753x_phy_write_c45;\n2401:\t\tbus-\u003eparent = dev;\n2402:\t\tbus-\u003ephy_mask = ~ds-\u003ephys_mii_mask;\n2403:\t\n2404:\t\tif (priv-\u003eirq_domain \u0026\u0026 !mnp)\n2405:\t\t\tmt7530_setup_mdio_irq(priv);\n2406:\t\n2407:\t\tret = devm_of_mdiobus_register(dev, bus, mnp);\n2408:\t\tif (ret) {\n2409:\t\t\tdev_err(dev, \"failed to register MDIO bus: %d\\n\", ret);\n2410:\t\t\tif (priv-\u003eirq_domain \u0026\u0026 !mnp)\n2411:\t\t\t\tmt7530_free_mdio_irq(priv);\n2412:\t\t}\n2413:\t\n2414:\tout:\n2415:\t\tof_node_put(mnp);\n2416:\t\treturn ret;\n2417:\t}\n2418:\t\n2419:\tstatic int\n"
} |
| 29/2 | 2026/07/11 07:47 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 33010 output: 32 thoughts: 493 Thoughts: **Worth Fuzzing Assessment** Okay, let's break this down. My initial thought is, `mt7530_setup_mdio` successfully registering the MDIO bus and the switch is a good starting point. This means the DSA core will expose switch ports as network interfaces, and that's precisely where Syzkaller can go to town fuzzing. The introduction of `en7528_mac_port_get_caps` called by phylink, modifications to `mt753x_conduit_state_change` for `ID_EN7528`, and the EEE disable in `mt7988_setup` – that all sounds like new hardware ID and new switch logic accessible through DSA. Definitely worth a closer look, right? But then I remember the prompt: "Code paths that are impossible to reach in virtualized environments...". Can I reach this in GCE or QEMU? Hmm... No, not impossible. Syzkaller can generate a device tree with `econet,en7528-switch`, the driver will probe, map dummy memory, register the DSA switch, DSA core will call the switch operations. So it *is* reachable. Now, let's make sure it meets the other criteria. "If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true." Yup, that's what's happening here. The patch is modifying driver code, and core logic, so I'm concluding WorthFuzzing=true. Now, because WorthFuzzing=true, I need to identify specific kernel functions that should be heavily fuzzed (FocusSymbols) and any relevant CONFIG options. Let's see... The relevant driver files are `drivers/net/dsa/mt7530.c` and `drivers/net/dsa/mt7530-mmio.c`. Time to dig into the `Makefile` and `Kconfig` files in `drivers/net/dsa/` and see what CONFIG options are in play. |
| 30/2 | 2026/07/11 07:47 | tool | grepper |
0mArgs:{
"Expression": "mt7530",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "\nFull output is too long, showing 500 out of 2017 lines.\nUse more precise expression if possible.\n\ndrivers/net/dsa/Makefile=5=obj-$(CONFIG_NET_DSA_KS8995) \t+= ks8995.o\ndrivers/net/dsa/Makefile:6:obj-$(CONFIG_NET_DSA_MT7530)\t+= mt7530.o\ndrivers/net/dsa/Makefile:7:obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o\ndrivers/net/dsa/Makefile:8:obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o\ndrivers/net/dsa/Makefile-9-obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o\n--\ndrivers/net/dsa/mt7530-mdio.c-15-\ndrivers/net/dsa/mt7530-mdio.c:16:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530-mdio.c-17-\ndrivers/net/dsa/mt7530-mdio.c=18=static int\ndrivers/net/dsa/mt7530-mdio.c:19:mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)\ndrivers/net/dsa/mt7530-mdio.c-20-{\ndrivers/net/dsa/mt7530-mdio.c:21:\tstruct mt7530_priv *priv = context;\ndrivers/net/dsa/mt7530-mdio.c-22-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/net/dsa/mt7530-mdio.c=43=static int\ndrivers/net/dsa/mt7530-mdio.c:44:mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)\ndrivers/net/dsa/mt7530-mdio.c-45-{\ndrivers/net/dsa/mt7530-mdio.c:46:\tstruct mt7530_priv *priv = context;\ndrivers/net/dsa/mt7530-mdio.c-47-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/net/dsa/mt7530-mdio.c=66=static void\ndrivers/net/dsa/mt7530-mdio.c:67:mt7530_mdio_regmap_lock(void *mdio_lock)\ndrivers/net/dsa/mt7530-mdio.c-68-{\n--\ndrivers/net/dsa/mt7530-mdio.c=72=static void\ndrivers/net/dsa/mt7530-mdio.c:73:mt7530_mdio_regmap_unlock(void *mdio_lock)\ndrivers/net/dsa/mt7530-mdio.c-74-{\n--\ndrivers/net/dsa/mt7530-mdio.c-77-\ndrivers/net/dsa/mt7530-mdio.c:78:static const struct regmap_bus mt7530_regmap_bus = {\ndrivers/net/dsa/mt7530-mdio.c:79:\t.reg_write = mt7530_regmap_write,\ndrivers/net/dsa/mt7530-mdio.c:80:\t.reg_read = mt7530_regmap_read,\ndrivers/net/dsa/mt7530-mdio.c-81-};\n--\ndrivers/net/dsa/mt7530-mdio.c=83=static int\ndrivers/net/dsa/mt7530-mdio.c:84:mt7531_create_sgmii(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530-mdio.c-85-{\n--\ndrivers/net/dsa/mt7530-mdio.c-105-\t\tmt7531_pcs_config[i]-\u003emax_register = 0x17c;\ndrivers/net/dsa/mt7530-mdio.c:106:\t\tmt7531_pcs_config[i]-\u003elock = mt7530_mdio_regmap_lock;\ndrivers/net/dsa/mt7530-mdio.c:107:\t\tmt7531_pcs_config[i]-\u003eunlock = mt7530_mdio_regmap_unlock;\ndrivers/net/dsa/mt7530-mdio.c-108-\t\tmt7531_pcs_config[i]-\u003elock_arg = \u0026priv-\u003ebus-\u003emdio_lock;\ndrivers/net/dsa/mt7530-mdio.c-109-\ndrivers/net/dsa/mt7530-mdio.c:110:\t\tregmap = devm_regmap_init(priv-\u003edev, \u0026mt7530_regmap_bus, priv,\ndrivers/net/dsa/mt7530-mdio.c-111-\t\t\t\t\t mt7531_pcs_config[i]);\n--\ndrivers/net/dsa/mt7530-mdio.c-130-\ndrivers/net/dsa/mt7530-mdio.c:131:static const struct of_device_id mt7530_of_match[] = {\ndrivers/net/dsa/mt7530-mdio.c-132-\t{ .compatible = \"mediatek,mt7621\", .data = \u0026mt753x_table[ID_MT7621], },\ndrivers/net/dsa/mt7530-mdio.c:133:\t{ .compatible = \"mediatek,mt7530\", .data = \u0026mt753x_table[ID_MT7530], },\ndrivers/net/dsa/mt7530-mdio.c-134-\t{ .compatible = \"mediatek,mt7531\", .data = \u0026mt753x_table[ID_MT7531], },\n--\ndrivers/net/dsa/mt7530-mdio.c-136-};\ndrivers/net/dsa/mt7530-mdio.c:137:MODULE_DEVICE_TABLE(of, mt7530_of_match);\ndrivers/net/dsa/mt7530-mdio.c-138-\n--\ndrivers/net/dsa/mt7530-mdio.c=147=static int\ndrivers/net/dsa/mt7530-mdio.c:148:mt7530_probe(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-149-{\ndrivers/net/dsa/mt7530-mdio.c:150:\tstruct mt7530_priv *priv;\ndrivers/net/dsa/mt7530-mdio.c-151-\tstruct device_node *dn;\n--\ndrivers/net/dsa/mt7530-mdio.c-163-\ndrivers/net/dsa/mt7530-mdio.c:164:\tret = mt7530_probe_common(priv);\ndrivers/net/dsa/mt7530-mdio.c-165-\tif (ret)\n--\ndrivers/net/dsa/mt7530-mdio.c-202-\ndrivers/net/dsa/mt7530-mdio.c:203:\tpriv-\u003eregmap = devm_regmap_init(priv-\u003edev, \u0026mt7530_regmap_bus, priv,\ndrivers/net/dsa/mt7530-mdio.c-204-\t\t\t\t\t\u0026regmap_config);\n--\ndrivers/net/dsa/mt7530-mdio.c=214=static void\ndrivers/net/dsa/mt7530-mdio.c:215:mt7530_remove(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-216-{\ndrivers/net/dsa/mt7530-mdio.c:217:\tstruct mt7530_priv *priv = dev_get_drvdata(\u0026mdiodev-\u003edev);\ndrivers/net/dsa/mt7530-mdio.c-218-\tint ret = 0, i;\n--\ndrivers/net/dsa/mt7530-mdio.c-232-\ndrivers/net/dsa/mt7530-mdio.c:233:\tmt7530_remove_common(priv);\ndrivers/net/dsa/mt7530-mdio.c-234-\n--\ndrivers/net/dsa/mt7530-mdio.c-238-\ndrivers/net/dsa/mt7530-mdio.c:239:static void mt7530_shutdown(struct mdio_device *mdiodev)\ndrivers/net/dsa/mt7530-mdio.c-240-{\ndrivers/net/dsa/mt7530-mdio.c:241:\tstruct mt7530_priv *priv = dev_get_drvdata(\u0026mdiodev-\u003edev);\ndrivers/net/dsa/mt7530-mdio.c-242-\n--\ndrivers/net/dsa/mt7530-mdio.c-250-\ndrivers/net/dsa/mt7530-mdio.c:251:static struct mdio_driver mt7530_mdio_driver = {\ndrivers/net/dsa/mt7530-mdio.c:252:\t.probe = mt7530_probe,\ndrivers/net/dsa/mt7530-mdio.c:253:\t.remove = mt7530_remove,\ndrivers/net/dsa/mt7530-mdio.c:254:\t.shutdown = mt7530_shutdown,\ndrivers/net/dsa/mt7530-mdio.c-255-\t.mdiodrv.driver = {\ndrivers/net/dsa/mt7530-mdio.c:256:\t\t.name = \"mt7530-mdio\",\ndrivers/net/dsa/mt7530-mdio.c:257:\t\t.of_match_table = mt7530_of_match,\ndrivers/net/dsa/mt7530-mdio.c-258-\t},\n--\ndrivers/net/dsa/mt7530-mdio.c-260-\ndrivers/net/dsa/mt7530-mdio.c:261:mdio_module_driver(mt7530_mdio_driver);\ndrivers/net/dsa/mt7530-mdio.c-262-\n--\ndrivers/net/dsa/mt7530-mmio.c-10-\ndrivers/net/dsa/mt7530-mmio.c:11:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530-mmio.c-12-\n--\ndrivers/net/dsa/mt7530-mmio.c=31=mt7988_probe(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-32-{\ndrivers/net/dsa/mt7530-mmio.c:33:\tstruct mt7530_priv *priv;\ndrivers/net/dsa/mt7530-mmio.c-34-\tvoid __iomem *base_addr;\n--\ndrivers/net/dsa/mt7530-mmio.c-43-\ndrivers/net/dsa/mt7530-mmio.c:44:\tret = mt7530_probe_common(priv);\ndrivers/net/dsa/mt7530-mmio.c-45-\tif (ret)\n--\ndrivers/net/dsa/mt7530-mmio.c=68=static void mt7988_remove(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-69-{\ndrivers/net/dsa/mt7530-mmio.c:70:\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\ndrivers/net/dsa/mt7530-mmio.c-71-\ndrivers/net/dsa/mt7530-mmio.c-72-\tif (priv)\ndrivers/net/dsa/mt7530-mmio.c:73:\t\tmt7530_remove_common(priv);\ndrivers/net/dsa/mt7530-mmio.c-74-}\n--\ndrivers/net/dsa/mt7530-mmio.c=76=static void mt7988_shutdown(struct platform_device *pdev)\ndrivers/net/dsa/mt7530-mmio.c-77-{\ndrivers/net/dsa/mt7530-mmio.c:78:\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\ndrivers/net/dsa/mt7530-mmio.c-79-\n--\ndrivers/net/dsa/mt7530-mmio.c=88=static struct platform_driver mt7988_platform_driver = {\n--\ndrivers/net/dsa/mt7530-mmio.c-92-\t.driver = {\ndrivers/net/dsa/mt7530-mmio.c:93:\t\t.name = \"mt7530-mmio\",\ndrivers/net/dsa/mt7530-mmio.c-94-\t\t.of_match_table = mt7988_of_match,\n--\ndrivers/net/dsa/mt7530.c-25-\ndrivers/net/dsa/mt7530.c:26:#include \"mt7530.h\"\ndrivers/net/dsa/mt7530.c-27-\n--\ndrivers/net/dsa/mt7530.c=31=static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)\n--\ndrivers/net/dsa/mt7530.c-36-/* String, offset, and register size in bytes if different from 4 bytes */\ndrivers/net/dsa/mt7530.c:37:static const struct mt7530_mib_desc mt7530_mib[] = {\ndrivers/net/dsa/mt7530.c-38-\tMIB_DESC(1, MT7530_PORT_MIB_TX_DROP, \"TxDrop\"),\n--\ndrivers/net/dsa/mt7530.c=49=static void\ndrivers/net/dsa/mt7530.c:50:mt7530_mutex_lock(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-51-{\n--\ndrivers/net/dsa/mt7530.c=56=static void\ndrivers/net/dsa/mt7530.c:57:mt7530_mutex_unlock(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-58-{\n--\ndrivers/net/dsa/mt7530.c=63=static void\ndrivers/net/dsa/mt7530.c:64:core_write(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-65-{\n--\ndrivers/net/dsa/mt7530.c-68-\ndrivers/net/dsa/mt7530.c:69:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-70-\n--\ndrivers/net/dsa/mt7530.c-95-\ndrivers/net/dsa/mt7530.c:96:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-97-}\n--\ndrivers/net/dsa/mt7530.c=99=static void\ndrivers/net/dsa/mt7530.c:100:core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)\ndrivers/net/dsa/mt7530.c-101-{\n--\ndrivers/net/dsa/mt7530.c-105-\ndrivers/net/dsa/mt7530.c:106:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-107-\n--\ndrivers/net/dsa/mt7530.c-137-\ndrivers/net/dsa/mt7530.c:138:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-139-}\n--\ndrivers/net/dsa/mt7530.c=141=static void\ndrivers/net/dsa/mt7530.c:142:core_set(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-143-{\n--\ndrivers/net/dsa/mt7530.c=147=static void\ndrivers/net/dsa/mt7530.c:148:core_clear(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-149-{\n--\ndrivers/net/dsa/mt7530.c=153=static int\ndrivers/net/dsa/mt7530.c:154:mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-155-{\n--\ndrivers/net/dsa/mt7530.c-161-\t\tdev_err(priv-\u003edev,\ndrivers/net/dsa/mt7530.c:162:\t\t\t\"failed to write mt7530 register\\n\");\ndrivers/net/dsa/mt7530.c-163-\n--\ndrivers/net/dsa/mt7530.c=167=static u32\ndrivers/net/dsa/mt7530.c:168:mt7530_mii_read(struct mt7530_priv *priv, u32 reg)\ndrivers/net/dsa/mt7530.c-169-{\n--\ndrivers/net/dsa/mt7530.c-176-\t\tdev_err(priv-\u003edev,\ndrivers/net/dsa/mt7530.c:177:\t\t\t\"failed to read mt7530 register\\n\");\ndrivers/net/dsa/mt7530.c-178-\t\treturn 0;\n--\ndrivers/net/dsa/mt7530.c=184=static void\ndrivers/net/dsa/mt7530.c:185:mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-186-{\ndrivers/net/dsa/mt7530.c:187:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-188-\ndrivers/net/dsa/mt7530.c:189:\tmt7530_mii_write(priv, reg, val);\ndrivers/net/dsa/mt7530.c-190-\ndrivers/net/dsa/mt7530.c:191:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-192-}\n--\ndrivers/net/dsa/mt7530.c=194=static u32\ndrivers/net/dsa/mt7530.c:195:_mt7530_unlocked_read(struct mt7530_dummy_poll *p)\ndrivers/net/dsa/mt7530.c-196-{\ndrivers/net/dsa/mt7530.c:197:\treturn mt7530_mii_read(p-\u003epriv, p-\u003ereg);\ndrivers/net/dsa/mt7530.c-198-}\n--\ndrivers/net/dsa/mt7530.c=200=static u32\ndrivers/net/dsa/mt7530.c:201:_mt7530_read(struct mt7530_dummy_poll *p)\ndrivers/net/dsa/mt7530.c-202-{\n--\ndrivers/net/dsa/mt7530.c-204-\ndrivers/net/dsa/mt7530.c:205:\tmt7530_mutex_lock(p-\u003epriv);\ndrivers/net/dsa/mt7530.c-206-\ndrivers/net/dsa/mt7530.c:207:\tval = mt7530_mii_read(p-\u003epriv, p-\u003ereg);\ndrivers/net/dsa/mt7530.c-208-\ndrivers/net/dsa/mt7530.c:209:\tmt7530_mutex_unlock(p-\u003epriv);\ndrivers/net/dsa/mt7530.c-210-\n--\ndrivers/net/dsa/mt7530.c=214=static u32\ndrivers/net/dsa/mt7530.c:215:mt7530_read(struct mt7530_priv *priv, u32 reg)\ndrivers/net/dsa/mt7530.c-216-{\ndrivers/net/dsa/mt7530.c:217:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-218-\ndrivers/net/dsa/mt7530.c-219-\tINIT_MT7530_DUMMY_POLL(\u0026p, priv, reg);\ndrivers/net/dsa/mt7530.c:220:\treturn _mt7530_read(\u0026p);\ndrivers/net/dsa/mt7530.c-221-}\n--\ndrivers/net/dsa/mt7530.c=223=static void\ndrivers/net/dsa/mt7530.c:224:mt7530_rmw(struct mt7530_priv *priv, u32 reg,\ndrivers/net/dsa/mt7530.c-225-\t u32 mask, u32 set)\ndrivers/net/dsa/mt7530.c-226-{\ndrivers/net/dsa/mt7530.c:227:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-228-\n--\ndrivers/net/dsa/mt7530.c-230-\ndrivers/net/dsa/mt7530.c:231:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-232-}\n--\ndrivers/net/dsa/mt7530.c=234=static void\ndrivers/net/dsa/mt7530.c:235:mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-236-{\ndrivers/net/dsa/mt7530.c:237:\tmt7530_rmw(priv, reg, val, val);\ndrivers/net/dsa/mt7530.c-238-}\n--\ndrivers/net/dsa/mt7530.c=240=static void\ndrivers/net/dsa/mt7530.c:241:mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)\ndrivers/net/dsa/mt7530.c-242-{\ndrivers/net/dsa/mt7530.c:243:\tmt7530_rmw(priv, reg, val, 0);\ndrivers/net/dsa/mt7530.c-244-}\n--\ndrivers/net/dsa/mt7530.c=246=static int\ndrivers/net/dsa/mt7530.c:247:mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)\ndrivers/net/dsa/mt7530.c-248-{\n--\ndrivers/net/dsa/mt7530.c-250-\tint ret;\ndrivers/net/dsa/mt7530.c:251:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-252-\n--\ndrivers/net/dsa/mt7530.c-254-\tval = ATC_BUSY | ATC_MAT(0) | cmd;\ndrivers/net/dsa/mt7530.c:255:\tmt7530_write(priv, MT7530_ATC, val);\ndrivers/net/dsa/mt7530.c-256-\ndrivers/net/dsa/mt7530.c-257-\tINIT_MT7530_DUMMY_POLL(\u0026p, priv, MT7530_ATC);\ndrivers/net/dsa/mt7530.c:258:\tret = readx_poll_timeout(_mt7530_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-259-\t\t\t\t !(val \u0026 ATC_BUSY), 20, 20000);\n--\ndrivers/net/dsa/mt7530.c-267-\t */\ndrivers/net/dsa/mt7530.c:268:\tval = mt7530_read(priv, MT7530_ATC);\ndrivers/net/dsa/mt7530.c-269-\tif ((cmd == MT7530_FDB_READ) \u0026\u0026 (val \u0026 ATC_INVALID))\n--\ndrivers/net/dsa/mt7530.c=278=static void\ndrivers/net/dsa/mt7530.c:279:mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)\ndrivers/net/dsa/mt7530.c-280-{\n--\ndrivers/net/dsa/mt7530.c-285-\tfor (i = 0; i \u003c 3; i++) {\ndrivers/net/dsa/mt7530.c:286:\t\treg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));\ndrivers/net/dsa/mt7530.c-287-\n--\ndrivers/net/dsa/mt7530.c=304=static void\ndrivers/net/dsa/mt7530.c:305:mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,\ndrivers/net/dsa/mt7530.c-306-\t\t u8 port_mask, const u8 *mac,\n--\ndrivers/net/dsa/mt7530.c-330-\tfor (i = 0; i \u003c 3; i++)\ndrivers/net/dsa/mt7530.c:331:\t\tmt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);\ndrivers/net/dsa/mt7530.c-332-}\n--\ndrivers/net/dsa/mt7530.c-334-/* Set up switch core clock for MT7530 */\ndrivers/net/dsa/mt7530.c:335:static void mt7530_pll_setup(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-336-{\n--\ndrivers/net/dsa/mt7530.c=375=static void\ndrivers/net/dsa/mt7530.c:376:mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)\ndrivers/net/dsa/mt7530.c-377-{\ndrivers/net/dsa/mt7530.c:378:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c-379-\tu32 ncpo1, ssc_delta, xtal;\n--\ndrivers/net/dsa/mt7530.c-384-\tif (interface == PHY_INTERFACE_MODE_RGMII) {\ndrivers/net/dsa/mt7530.c:385:\t\tmt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,\ndrivers/net/dsa/mt7530.c-386-\t\t\t P6_INTF_MODE(0));\n--\ndrivers/net/dsa/mt7530.c-389-\ndrivers/net/dsa/mt7530.c:390:\tmt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));\ndrivers/net/dsa/mt7530.c-391-\ndrivers/net/dsa/mt7530.c:392:\txtal = mt7530_read(priv, MT753X_MTRAP) \u0026 MT7530_XTAL_MASK;\ndrivers/net/dsa/mt7530.c-393-\n--\ndrivers/net/dsa/mt7530.c=428=static void\ndrivers/net/dsa/mt7530.c:429:mt7531_pll_setup(struct mt7530_priv *priv)\ndrivers/net/dsa/mt7530.c-430-{\n--\ndrivers/net/dsa/mt7530.c-435-\ndrivers/net/dsa/mt7530.c:436:\tval = mt7530_read(priv, MT7531_CREV);\ndrivers/net/dsa/mt7530.c:437:\ttop_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);\ndrivers/net/dsa/mt7530.c:438:\thwstrap = mt7530_read(priv, MT753X_TRAP);\ndrivers/net/dsa/mt7530.c-439-\tif ((val \u0026 CHIP_REV_M) \u003e 0)\n--\ndrivers/net/dsa/mt7530.c-446-\t/* Step 1 : Disable MT7531 COREPLL */\ndrivers/net/dsa/mt7530.c:447:\tval = mt7530_read(priv, MT7531_PLLGP_EN);\ndrivers/net/dsa/mt7530.c-448-\tval \u0026= ~EN_COREPLL;\ndrivers/net/dsa/mt7530.c:449:\tmt7530_write(priv, MT7531_PLLGP_EN, val);\ndrivers/net/dsa/mt7530.c-450-\ndrivers/net/dsa/mt7530.c-451-\t/* Step 2: switch to XTAL output */\ndrivers/net/dsa/mt7530.c:452:\tval = mt7530_read(priv, MT7531_PLLGP_EN);\ndrivers/net/dsa/mt7530.c-453-\tval |= SW_CLKSW;\ndrivers/net/dsa/mt7530.c:454:\tmt7530_write(priv, MT7531_PLLGP_EN, val);\ndrivers/net/dsa/mt7530.c-455-\ndrivers/net/dsa/mt7530.c:456:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-457-\tval \u0026= ~RG_COREPLL_EN;\ndrivers/net/dsa/mt7530.c:458:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-459-\ndrivers/net/dsa/mt7530.c-460-\t/* Step 3: disable PLLGP and enable program PLLGP */\ndrivers/net/dsa/mt7530.c:461:\tval = mt7530_read(priv, MT7531_PLLGP_EN);\ndrivers/net/dsa/mt7530.c-462-\tval |= SW_PLLGP;\ndrivers/net/dsa/mt7530.c:463:\tmt7530_write(priv, MT7531_PLLGP_EN, val);\ndrivers/net/dsa/mt7530.c-464-\ndrivers/net/dsa/mt7530.c-465-\t/* Step 4: program COREPLL output frequency to 500MHz */\ndrivers/net/dsa/mt7530.c:466:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-467-\tval \u0026= ~RG_COREPLL_POSDIV_M;\ndrivers/net/dsa/mt7530.c-468-\tval |= 2 \u003c\u003c RG_COREPLL_POSDIV_S;\ndrivers/net/dsa/mt7530.c:469:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-470-\tusleep_range(25, 35);\n--\ndrivers/net/dsa/mt7530.c-473-\tcase MT7531_XTAL_FSEL_25MHZ:\ndrivers/net/dsa/mt7530.c:474:\t\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-475-\t\tval \u0026= ~RG_COREPLL_SDM_PCW_M;\ndrivers/net/dsa/mt7530.c-476-\t\tval |= 0x140000 \u003c\u003c RG_COREPLL_SDM_PCW_S;\ndrivers/net/dsa/mt7530.c:477:\t\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-478-\t\tbreak;\ndrivers/net/dsa/mt7530.c-479-\tcase MT7531_XTAL_FSEL_40MHZ:\ndrivers/net/dsa/mt7530.c:480:\t\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-481-\t\tval \u0026= ~RG_COREPLL_SDM_PCW_M;\ndrivers/net/dsa/mt7530.c-482-\t\tval |= 0x190000 \u003c\u003c RG_COREPLL_SDM_PCW_S;\ndrivers/net/dsa/mt7530.c:483:\t\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-484-\t\tbreak;\n--\ndrivers/net/dsa/mt7530.c-487-\t/* Set feedback divide ratio update signal to high */\ndrivers/net/dsa/mt7530.c:488:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-489-\tval |= RG_COREPLL_SDM_PCW_CHG;\ndrivers/net/dsa/mt7530.c:490:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-491-\t/* Wait for at least 16 XTAL clocks */\n--\ndrivers/net/dsa/mt7530.c-494-\t/* Step 5: set feedback divide ratio update signal to low */\ndrivers/net/dsa/mt7530.c:495:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-496-\tval \u0026= ~RG_COREPLL_SDM_PCW_CHG;\ndrivers/net/dsa/mt7530.c:497:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-498-\ndrivers/net/dsa/mt7530.c-499-\t/* Enable 325M clock for SGMII */\ndrivers/net/dsa/mt7530.c:500:\tmt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);\ndrivers/net/dsa/mt7530.c-501-\ndrivers/net/dsa/mt7530.c-502-\t/* Enable 250SSC clock for RGMII */\ndrivers/net/dsa/mt7530.c:503:\tmt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);\ndrivers/net/dsa/mt7530.c-504-\ndrivers/net/dsa/mt7530.c-505-\t/* Step 6: Enable MT7531 PLL */\ndrivers/net/dsa/mt7530.c:506:\tval = mt7530_read(priv, MT7531_PLLGP_CR0);\ndrivers/net/dsa/mt7530.c-507-\tval |= RG_COREPLL_EN;\ndrivers/net/dsa/mt7530.c:508:\tmt7530_write(priv, MT7531_PLLGP_CR0, val);\ndrivers/net/dsa/mt7530.c-509-\ndrivers/net/dsa/mt7530.c:510:\tval = mt7530_read(priv, MT7531_PLLGP_EN);\ndrivers/net/dsa/mt7530.c-511-\tval |= EN_COREPLL;\ndrivers/net/dsa/mt7530.c:512:\tmt7530_write(priv, MT7531_PLLGP_EN, val);\ndrivers/net/dsa/mt7530.c-513-\tusleep_range(25, 35);\n--\ndrivers/net/dsa/mt7530.c=516=static void\ndrivers/net/dsa/mt7530.c:517:mt7530_mib_reset(struct dsa_switch *ds)\ndrivers/net/dsa/mt7530.c-518-{\ndrivers/net/dsa/mt7530.c:519:\tstruct mt7530_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/mt7530.c-520-\ndrivers/net/dsa/mt7530.c:521:\tmt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);\ndrivers/net/dsa/mt7530.c:522:\tmt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);\ndrivers/net/dsa/mt7530.c-523-}\ndrivers/net/dsa/mt7530.c-524-\ndrivers/net/dsa/mt7530.c:525:static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)\ndrivers/net/dsa/mt7530.c-526-{\n--\ndrivers/net/dsa/mt7530.c-529-\ndrivers/net/dsa/mt7530.c:530:static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum,\ndrivers/net/dsa/mt7530.c-531-\t\t\t\tu16 val)\n--\ndrivers/net/dsa/mt7530.c-535-\ndrivers/net/dsa/mt7530.c:536:static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port,\ndrivers/net/dsa/mt7530.c-537-\t\t\t int devad, int regnum)\n--\ndrivers/net/dsa/mt7530.c-541-\ndrivers/net/dsa/mt7530.c:542:static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-543-\t\t\t\tint regnum, u16 val)\n--\ndrivers/net/dsa/mt7530.c=548=static int\ndrivers/net/dsa/mt7530.c:549:mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-550-\t\t\tint regnum)\ndrivers/net/dsa/mt7530.c-551-{\ndrivers/net/dsa/mt7530.c:552:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-553-\tu32 reg, val;\n--\ndrivers/net/dsa/mt7530.c-557-\ndrivers/net/dsa/mt7530.c:558:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-559-\ndrivers/net/dsa/mt7530.c:560:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-561-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-568-\t MT7531_MDIO_DEV_ADDR(devad) | regnum;\ndrivers/net/dsa/mt7530.c:569:\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-570-\ndrivers/net/dsa/mt7530.c:571:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-572-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-579-\t MT7531_MDIO_DEV_ADDR(devad);\ndrivers/net/dsa/mt7530.c:580:\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-581-\ndrivers/net/dsa/mt7530.c:582:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-583-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-590-out:\ndrivers/net/dsa/mt7530.c:591:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-592-\n--\ndrivers/net/dsa/mt7530.c=596=static int\ndrivers/net/dsa/mt7530.c:597:mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,\ndrivers/net/dsa/mt7530.c-598-\t\t\t int regnum, u16 data)\ndrivers/net/dsa/mt7530.c-599-{\ndrivers/net/dsa/mt7530.c:600:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-601-\tu32 val, reg;\n--\ndrivers/net/dsa/mt7530.c-605-\ndrivers/net/dsa/mt7530.c:606:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-607-\ndrivers/net/dsa/mt7530.c:608:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-609-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-616-\t MT7531_MDIO_DEV_ADDR(devad) | regnum;\ndrivers/net/dsa/mt7530.c:617:\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-618-\ndrivers/net/dsa/mt7530.c:619:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-620-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-627-\t MT7531_MDIO_DEV_ADDR(devad) | data;\ndrivers/net/dsa/mt7530.c:628:\tmt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-629-\ndrivers/net/dsa/mt7530.c:630:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-631-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-637-out:\ndrivers/net/dsa/mt7530.c:638:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-639-\n--\ndrivers/net/dsa/mt7530.c=643=static int\ndrivers/net/dsa/mt7530.c:644:mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)\ndrivers/net/dsa/mt7530.c-645-{\ndrivers/net/dsa/mt7530.c:646:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-647-\tint ret;\n--\ndrivers/net/dsa/mt7530.c-651-\ndrivers/net/dsa/mt7530.c:652:\tmt7530_mutex_lock(priv);\ndrivers/net/dsa/mt7530.c-653-\ndrivers/net/dsa/mt7530.c:654:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-655-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-663-\ndrivers/net/dsa/mt7530.c:664:\tmt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);\ndrivers/net/dsa/mt7530.c-665-\ndrivers/net/dsa/mt7530.c:666:\tret = readx_poll_timeout(_mt7530_unlocked_read, \u0026p, val,\ndrivers/net/dsa/mt7530.c-667-\t\t\t\t !(val \u0026 MT7531_PHY_ACS_ST), 20, 100000);\n--\ndrivers/net/dsa/mt7530.c-674-out:\ndrivers/net/dsa/mt7530.c:675:\tmt7530_mutex_unlock(priv);\ndrivers/net/dsa/mt7530.c-676-\n--\ndrivers/net/dsa/mt7530.c=680=static int\ndrivers/net/dsa/mt7530.c:681:mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,\ndrivers/net/dsa/mt7530.c-682-\t\t\t u16 data)\ndrivers/net/dsa/mt7530.c-683-{\ndrivers/net/dsa/mt7530.c:684:\tstruct mt7530_dummy_poll p;\ndrivers/net/dsa/mt7530.c-685-\tint ret;\n\n"
} |
| 31/2 | 2026/07/11 07:47 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 47788 output: 38 thoughts: 116 Thoughts: **Analyzing the MT7530 Configuration Options** Okay, so I'm looking at this patch and immediately, my mind jumps to the configuration options related to the MT7530 switch. It's listing `NET_DSA_MT7530`, `NET_DSA_MT7530_MDIO`, and `NET_DSA_MT7530_MMIO`. Knowing the architecture of these drivers, the fact that the patch is touching `mt7530-mmio.c` and `mt7530.c` tells me right away that `NET_DSA_MT7530` *and* `NET_DSA_MT7530_MMIO` are going to be essential for the changes to take effect. No surprises there. To be absolutely certain about the dependencies and how these options are related, I'll need to double-check the Kconfig file for the DSA drivers. Specifically, I'll need to navigate to `drivers/net/dsa/Kconfig` to refresh my memory on any conditional dependencies and ensure there are no subtle interactions with other parts of the network stack. This is just a quick sanity check to avoid any unexpected issues downstream. |
| 32/2 | 2026/07/11 07:47 | tool | grepper |
0mArgs:{
"Expression": "NET_DSA_MT7530",
"PathPrefix": "drivers/net/dsa/Kconfig"
}Results: {
"Output": "drivers/net/dsa/Kconfig=29=source \"drivers/net/dsa/lantiq/Kconfig\"\ndrivers/net/dsa/Kconfig-30-\ndrivers/net/dsa/Kconfig:31:config NET_DSA_MT7530\ndrivers/net/dsa/Kconfig-32-\ttristate \"MediaTek MT7530 and MT7531 Ethernet switch support\"\n--\ndrivers/net/dsa/Kconfig-34-\tselect REGMAP_IRQ\ndrivers/net/dsa/Kconfig:35:\timply NET_DSA_MT7530_MDIO\ndrivers/net/dsa/Kconfig:36:\timply NET_DSA_MT7530_MMIO\ndrivers/net/dsa/Kconfig-37-\thelp\n--\ndrivers/net/dsa/Kconfig-42-\ndrivers/net/dsa/Kconfig:43:config NET_DSA_MT7530_MDIO\ndrivers/net/dsa/Kconfig-44-\ttristate \"MediaTek MT7530 MDIO interface driver\"\ndrivers/net/dsa/Kconfig:45:\tdepends on NET_DSA_MT7530\ndrivers/net/dsa/Kconfig-46-\tselect MEDIATEK_GE_PHY\n--\ndrivers/net/dsa/Kconfig-53-\ndrivers/net/dsa/Kconfig:54:config NET_DSA_MT7530_MMIO\ndrivers/net/dsa/Kconfig-55-\ttristate \"MediaTek MT7530 MMIO interface driver\"\ndrivers/net/dsa/Kconfig:56:\tdepends on NET_DSA_MT7530\ndrivers/net/dsa/Kconfig-57-\tdepends on HAS_IOMEM\n"
} |
| 33/2 | 2026/07/11 07:47 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 48662 output: 173 thoughts: 2461 Thoughts: **Analysis of MT7530 Switch Chip Support** Okay, let's break this down. It looks like we're adding support for a new switch chip, the EN7528, within the MT7530 DSA driver. The essential configs needed are `NET_DSA_MT7530` and `NET_DSA_MT7530_MMIO`. This is a pretty focused change, so it's good. My immediate focus shifts to the newly introduced and modified functions: `en7528_mac_port_get_caps`, `mt7988_setup` (with its new `ID_EN7528` block), and `mt753x_conduit_state_change` (also modified to include `ID_EN7528`). `en7528_mac_port_get_caps` is brand new, which means it will probably need thorough attention when fuzzing. After a quick assessment, these aren't hot-path functions, so potential performance regressions are less of a concern. `mt7988_setup` is a probe-time function, `en7528_mac_port_get_caps` is called during port setup, and `mt753x_conduit_state_change` is triggered by conduit state changes. Looking closer at the patch, the main modifications are in `mt7530-mmio.c` where we see the addition of the EN7528 compatible string and an entry in the `mt753x_table`. `mt7530.c` gets the bulk of the changes. The switch's PHYs are integrated GPHYs at MDIO addresses 9..12 (switch ports 1..4), so they're reached through the PHY's internal indirect access registers. The key addition is `en7528_mac_port_get_caps`, which defines the capabilities for the EN7528 ports. Ports 1-4 are internal and support 10/100/1000 Mbps, while port 6 also supports internal mode and 1000FD. Then there's the modification to `mt7988_setup` which disables EEE (Energy Efficient Ethernet) on the EN7528 LAN GPHYs. It's disabling the advertisement of EEE because it causes issues with link stability. Finally, `mt753x_conduit_state_change` is modified to include ID_EN7528. Given the scope and reachability through the DSA core, I'm confident in marking this as "WorthFuzzing=true." The focus symbols are clear: `en7528_mac_port_get_caps`, `mt7988_setup`, and `mt753x_conduit_state_change`. I will set the results. |
| 34/2 | 2026/07/11 07:48 | tool | set-results |
0mArgs:{
"EnableConfigs": [
"NET_DSA_MT7530",
"NET_DSA_MT7530_MMIO"
],
"FocusSymbols": [
"en7528_mac_port_get_caps",
"mt7988_setup",
"mt753x_conduit_state_change"
],
"Reasoning": "The patch adds support for the EcoNet EN7528 SoC built-in switch to the Mediatek MT7530 DSA driver. This includes a new function for getting MAC port capabilities and modifications to switch setup and conduit state change logic. The driver can be probed via device tree and the switch operations are reachable via the DSA core in a virtualized environment.",
"WorthFuzzing": true
}Results: {
"EnableConfigs": [
"NET_DSA_MT7530",
"NET_DSA_MT7530_MMIO"
],
"FocusSymbols": [
"en7528_mac_port_get_caps",
"mt7988_setup",
"mt753x_conduit_state_change"
],
"Reasoning": "The patch adds support for the EcoNet EN7528 SoC built-in switch to the Mediatek MT7530 DSA driver. This includes a new function for getting MAC port capabilities and modifications to switch setup and conduit state change logic. The driver can be probed via device tree and the switch operations are reachable via the DSA core in a virtualized environment.",
"WorthFuzzing": true
} |
| Total Calls | Total Tokens | Avg Tokens | Total Duration (Seconds) | Avg Duration (Seconds) |
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| Total Calls | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|