| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/07/07 15:45 | flow | patch-triage |
0mArgs:null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch adds support for a new MediaTek SoC (MT8189) to the dwmac-mediatek platform driver. This is hardware-specific code that relies on physical MMIO registers and specific device tree configurations, which cannot be meaningfully executed or reached in generic virtualized environments like QEMU or GCE.",
"WorthFuzzing": false
} |
| 1/1 | 2026/07/07 15:45 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit 9d94f05e132fc176484540f1a16a16090af27cb6\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Tue Jul 7 15:45:31 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml\nindex 3aab21b8e8de5b..000abec023b314 100644\n--- a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml\n+++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml\n@@ -20,13 +20,11 @@ select:\n enum:\n - mediatek,mt2712-gmac\n - mediatek,mt8188-gmac\n+ - mediatek,mt8189-gmac\n - mediatek,mt8195-gmac\n required:\n - compatible\n \n-allOf:\n- - $ref: snps,dwmac.yaml#\n-\n properties:\n compatible:\n oneOf:\n@@ -36,6 +34,7 @@ properties:\n - const: snps,dwmac-4.20a\n - items:\n - enum:\n+ - mediatek,mt8189-gmac\n - mediatek,mt8195-gmac\n - const: snps,dwmac-5.10a\n - items:\n@@ -44,26 +43,6 @@ properties:\n - const: mediatek,mt8195-gmac\n - const: snps,dwmac-5.10a\n \n- clocks:\n- minItems: 5\n- items:\n- - description: AXI clock\n- - description: APB clock\n- - description: MAC Main clock\n- - description: PTP clock\n- - description: RMII reference clock provided by MAC\n- - description: MAC clock gate\n-\n- clock-names:\n- minItems: 5\n- items:\n- - const: axi\n- - const: apb\n- - const: mac_main\n- - const: ptp_ref\n- - const: rmii_internal\n- - const: mac_cg\n-\n interrupts:\n maxItems: 1\n \n@@ -147,6 +126,58 @@ required:\n - phy-mode\n - mediatek,pericfg\n \n+allOf:\n+ - $ref: snps,dwmac.yaml#\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - mediatek,mt2712-gmac\n+ - mediatek,mt8188-gmac\n+ - mediatek,mt8195-gmac\n+ then:\n+ properties:\n+ clocks:\n+ minItems: 5\n+ items:\n+ - description: AXI clock\n+ - description: APB clock\n+ - description: MAC Main clock\n+ - description: PTP clock\n+ - description: RMII reference clock provided by MAC\n+ - description: MAC clock gate\n+\n+ clock-names:\n+ minItems: 5\n+ items:\n+ - const: axi\n+ - const: apb\n+ - const: mac_main\n+ - const: ptp_ref\n+ - const: rmii_internal\n+ - const: mac_cg\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - mediatek,mt8189-gmac\n+ then:\n+ properties:\n+ clocks:\n+ items:\n+ - description: MAC Main clock\n+ - description: PTP clock\n+ - description: RMII reference clock provided by MAC\n+\n+ clock-names:\n+ items:\n+ - const: mac_main\n+ - const: ptp_ref\n+ - const: rmii_internal\n+\n unevaluatedProperties: false\n \n examples:\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c\nindex 30ae0dba7fffdb..e7e336b1f114c4 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c\n@@ -36,8 +36,16 @@\n #define ETH_FINE_DLY_GTXC\tBIT(1)\n #define ETH_FINE_DLY_RXC\tBIT(0)\n \n+/* Peri Configuration register for mt8189 */\n+#define MT8189_PERI_ETH_CTRL_BASE\t\t0x270\n+\n+#define MT8189_CTRL0_TXC_OUT_OP\t\t\tBIT(20)\n+#define MT8189_CTRL0_DLY_GTXC_STAGE_FINE\tGENMASK(11, 6)\n+\n /* Peri Configuration register for mt8195 */\n-#define MT8195_PERI_ETH_CTRL0\t\t0xFD0\n+#define MT8195_PERI_ETH_CTRL_BASE\t0xFD0\n+\n+#define MT8195_PERI_ETH_CTRL0\t\t0x0\n #define MT8195_RMII_CLK_SRC_INTERNAL\tBIT(28)\n #define MT8195_RMII_CLK_SRC_RXC\t\tBIT(27)\n #define MT8195_ETH_INTF_SEL\t\tGENMASK(26, 24)\n@@ -47,7 +55,7 @@\n #define MT8195_DLY_GTXC_ENABLE\t\tBIT(5)\n #define MT8195_DLY_GTXC_STAGES\t\tGENMASK(4, 0)\n \n-#define MT8195_PERI_ETH_CTRL1\t\t0xFD4\n+#define MT8195_PERI_ETH_CTRL1\t\t0x4\n #define MT8195_DLY_RXC_INV\t\tBIT(25)\n #define MT8195_DLY_RXC_ENABLE\t\tBIT(18)\n #define MT8195_DLY_RXC_STAGES\t\tGENMASK(17, 13)\n@@ -55,7 +63,7 @@\n #define MT8195_DLY_TXC_ENABLE\t\tBIT(5)\n #define MT8195_DLY_TXC_STAGES\t\tGENMASK(4, 0)\n \n-#define MT8195_PERI_ETH_CTRL2\t\t0xFD8\n+#define MT8195_PERI_ETH_CTRL2\t\t0x8\n #define MT8195_DLY_RMII_RXC_INV\t\tBIT(25)\n #define MT8195_DLY_RMII_RXC_ENABLE\tBIT(18)\n #define MT8195_DLY_RMII_RXC_STAGES\tGENMASK(17, 13)\n@@ -95,7 +103,10 @@ struct mediatek_dwmac_variant {\n \n \tu32 rx_delay_max;\n \tu32 tx_delay_max;\n+\tu32 peri_eth_ctrl_offset;\n \tu8 dma_bit_mask;\n+\tbool use_out_op;\n+\tbool use_stage_fine;\n };\n \n /* list of clocks required for mac */\n@@ -107,7 +118,11 @@ static const char * const mt8195_dwmac_clk_l[] = {\n \t\"axi\", \"apb\", \"mac_cg\", \"mac_main\", \"ptp_ref\"\n };\n \n-static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,\n+static const char * const mt8189_dwmac_clk_l[] = {\n+\t\"mac_main\", \"ptp_ref\"\n+};\n+\n+static int set_phy_interface_v1(struct mediatek_dwmac_plat_data *plat,\n \t\t\t\tu8 phy_intf_sel)\n {\n \tu32 intf_val = phy_intf_sel;\n@@ -124,7 +139,7 @@ static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,\n \treturn 0;\n }\n \n-static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)\n+static void delay_ps2stage_v1(struct mediatek_dwmac_plat_data *plat)\n {\n \tstruct mac_delay_struct *mac_delay = \u0026plat-\u003emac_delay;\n \n@@ -149,7 +164,7 @@ static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)\n \t}\n }\n \n-static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)\n+static void delay_stage2ps_v1(struct mediatek_dwmac_plat_data *plat)\n {\n \tstruct mac_delay_struct *mac_delay = \u0026plat-\u003emac_delay;\n \n@@ -174,12 +189,12 @@ static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)\n \t}\n }\n \n-static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)\n+static int set_delay_v1(struct mediatek_dwmac_plat_data *plat)\n {\n \tstruct mac_delay_struct *mac_delay = \u0026plat-\u003emac_delay;\n \tu32 delay_val = 0, fine_val = 0;\n \n-\tmt2712_delay_ps2stage(plat);\n+\tdelay_ps2stage_v1(plat);\n \n \tswitch (plat-\u003ephy_mode) {\n \tcase PHY_INTERFACE_MODE_MII:\n@@ -258,14 +273,14 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)\n \tregmap_write(plat-\u003eperi_regmap, PERI_ETH_DLY, delay_val);\n \tregmap_write(plat-\u003eperi_regmap, PERI_ETH_DLY_FINE, fine_val);\n \n-\tmt2712_delay_stage2ps(plat);\n+\tdelay_stage2ps_v1(plat);\n \n \treturn 0;\n }\n \n static const struct mediatek_dwmac_variant mt2712_gmac_variant = {\n-\t\t.dwmac_set_phy_interface = mt2712_set_interface,\n-\t\t.dwmac_set_delay = mt2712_set_delay,\n+\t\t.dwmac_set_phy_interface = set_phy_interface_v1,\n+\t\t.dwmac_set_delay = set_delay_v1,\n \t\t.clk_list = mt2712_dwmac_clk_l,\n \t\t.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),\n \t\t.rx_delay_max = 17600,\n@@ -273,10 +288,11 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {\n \t\t.dma_bit_mask = 33,\n };\n \n-static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,\n+static int set_phy_interface_v2(struct mediatek_dwmac_plat_data *plat,\n \t\t\t\tu8 phy_intf_sel)\n {\n \tu32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel);\n+\tu32 reg_offset = plat-\u003evariant-\u003eperi_eth_ctrl_offset;\n \n \tif (phy_intf_sel == PHY_INTF_SEL_RMII) {\n \t\tif (plat-\u003ermii_clk_from_mac)\n@@ -288,12 +304,17 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,\n \t/* MT8195 only support external PHY */\n \tintf_val |= MT8195_EXT_PHY_MODE;\n \n-\tregmap_write(plat-\u003eperi_regmap, MT8195_PERI_ETH_CTRL0, intf_val);\n+\tif (plat-\u003evariant-\u003euse_out_op)\n+\t\tintf_val |= MT8189_CTRL0_TXC_OUT_OP;\n+\n+\tregmap_write(plat-\u003eperi_regmap,\n+\t\t reg_offset + MT8195_PERI_ETH_CTRL0,\n+\t\t intf_val);\n \n \treturn 0;\n }\n \n-static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)\n+static void delay_ps2stage_v2(struct mediatek_dwmac_plat_data *plat)\n {\n \tstruct mac_delay_struct *mac_delay = \u0026plat-\u003emac_delay;\n \n@@ -302,7 +323,7 @@ static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)\n \tmac_delay-\u003erx_delay /= 290;\n }\n \n-static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)\n+static void delay_stage2ps_v2(struct mediatek_dwmac_plat_data *plat)\n {\n \tstruct mac_delay_struct *mac_delay = \u0026plat-\u003emac_delay;\n \n@@ -311,12 +332,16 @@ static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)\n \tmac_delay-\u003erx_delay *= 290;\n }\n \n-static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)\n+static int set_delay_v2(struct mediatek_dwmac_plat_data *plat)\n {\n \tstruct mac_delay_struct *mac_delay = \u0026plat-\u003emac_delay;\n-\tu32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0;\n+\tu32 reg_offset = plat-\u003evariant-\u003eperi_eth_ctrl_offset;\n+\tu32 gtxc_delay_mask = 0;\n+\tu32 gtxc_delay_val = 0;\n+\tu32 rmii_delay_val = 0;\n+\tu32 delay_val = 0;\n \n-\tmt8195_delay_ps2stage(plat);\n+\tdelay_ps2stage_v2(plat);\n \n \tswitch (plat-\u003ephy_mode) {\n \tcase PHY_INTERFACE_MODE_MII:\n@@ -388,6 +413,9 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)\n \t\tgtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay-\u003etx_delay);\n \t\tgtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay-\u003etx_inv);\n \n+\t\tif (plat-\u003evariant-\u003euse_stage_fine)\n+\t\t\tgtxc_delay_val |= MT8189_CTRL0_DLY_GTXC_STAGE_FINE;\n+\n \t\tdelay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay-\u003erx_delay);\n \t\tdelay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay-\u003erx_delay);\n \t\tdelay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay-\u003erx_inv);\n@@ -398,29 +426,52 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)\n \t\treturn -EINVAL;\n \t}\n \n+\tgtxc_delay_mask = MT8195_RGMII_TXC_PHASE_CTRL |\n+\t\t\t MT8195_DLY_GTXC_INV |\n+\t\t\t MT8195_DLY_GTXC_ENABLE |\n+\t\t\t MT8195_DLY_GTXC_STAGES;\n+\n+\tif (plat-\u003evariant-\u003euse_stage_fine)\n+\t\tgtxc_delay_mask |= MT8189_CTRL0_DLY_GTXC_STAGE_FINE;\n+\n \tregmap_update_bits(plat-\u003eperi_regmap,\n-\t\t\t MT8195_PERI_ETH_CTRL0,\n-\t\t\t MT8195_RGMII_TXC_PHASE_CTRL |\n-\t\t\t MT8195_DLY_GTXC_INV |\n-\t\t\t MT8195_DLY_GTXC_ENABLE |\n-\t\t\t MT8195_DLY_GTXC_STAGES,\n+\t\t\t reg_offset + MT8195_PERI_ETH_CTRL0,\n+\t\t\t gtxc_delay_mask,\n \t\t\t gtxc_delay_val);\n-\tregmap_write(plat-\u003eperi_regmap, MT8195_PERI_ETH_CTRL1, delay_val);\n-\tregmap_write(plat-\u003eperi_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val);\n+\tregmap_write(plat-\u003eperi_regmap,\n+\t\t reg_offset + MT8195_PERI_ETH_CTRL1,\n+\t\t delay_val);\n+\tregmap_write(plat-\u003eperi_regmap,\n+\t\t reg_offset + MT8195_PERI_ETH_CTRL2,\n+\t\t rmii_delay_val);\n \n-\tmt8195_delay_stage2ps(plat);\n+\tdelay_stage2ps_v2(plat);\n \n \treturn 0;\n }\n \n+static const struct mediatek_dwmac_variant mt8189_gmac_variant = {\n+\t.dwmac_set_phy_interface = set_phy_interface_v2,\n+\t.dwmac_set_delay = set_delay_v2,\n+\t.clk_list = mt8189_dwmac_clk_l,\n+\t.num_clks = ARRAY_SIZE(mt8189_dwmac_clk_l),\n+\t.dma_bit_mask = 35,\n+\t.rx_delay_max = 9280,\n+\t.tx_delay_max = 9280,\n+\t.peri_eth_ctrl_offset = MT8189_PERI_ETH_CTRL_BASE,\n+\t.use_out_op = true,\n+\t.use_stage_fine = true,\n+};\n+\n static const struct mediatek_dwmac_variant mt8195_gmac_variant = {\n-\t.dwmac_set_phy_interface = mt8195_set_interface,\n-\t.dwmac_set_delay = mt8195_set_delay,\n+\t.dwmac_set_phy_interface = set_phy_interface_v2,\n+\t.dwmac_set_delay = set_delay_v2,\n \t.clk_list = mt8195_dwmac_clk_l,\n \t.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),\n \t.rx_delay_max = 9280,\n \t.tx_delay_max = 9280,\n \t.dma_bit_mask = 35,\n+\t.peri_eth_ctrl_offset = MT8195_PERI_ETH_CTRL_BASE,\n };\n \n static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)\n@@ -662,6 +713,8 @@ static void mediatek_dwmac_remove(struct platform_device *pdev)\n static const struct of_device_id mediatek_dwmac_match[] = {\n \t{ .compatible = \"mediatek,mt2712-gmac\",\n \t .data = \u0026mt2712_gmac_variant },\n+\t{ .compatible = \"mediatek,mt8189-gmac\",\n+\t .data = \u0026mt8189_gmac_variant },\n \t{ .compatible = \"mediatek,mt8195-gmac\",\n \t .data = \u0026mt8195_gmac_variant },\n \t{ }\n"
} |
| 2/1 | 2026/07/07 15:45 | agent | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch adds support for a new MediaTek SoC (MT8189) to the dwmac-mediatek platform driver. This is hardware-specific code that relies on physical MMIO registers and specific device tree configurations, which cannot be meaningfully executed or reached in generic virtualized environments like QEMU or GCE.",
"WorthFuzzing": false
}Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Do not list too generic configs (we already have them enabled). Only list those that specifically cover the modified code. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes:
commit 9d94f05e132fc176484540f1a16a16090af27cb6
Author: syz-cluster <triage@syzkaller.com>
Date: Tue Jul 7 15:45:31 2026 +0000
syz-cluster: applied patch under review
diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml
index 3aab21b8e8de5b..000abec023b314 100644
--- a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml
@@ -20,13 +20,11 @@ select:
enum:
- mediatek,mt2712-gmac
- mediatek,mt8188-gmac
+ - mediatek,mt8189-gmac
- mediatek,mt8195-gmac
required:
- compatible
-allOf:
- - $ref: snps,dwmac.yaml#
-
properties:
compatible:
oneOf:
@@ -36,6 +34,7 @@ properties:
- const: snps,dwmac-4.20a
- items:
- enum:
+ - mediatek,mt8189-gmac
- mediatek,mt8195-gmac
- const: snps,dwmac-5.10a
- items:
@@ -44,26 +43,6 @@ properties:
- const: mediatek,mt8195-gmac
- const: snps,dwmac-5.10a
- clocks:
- minItems: 5
- items:
- - description: AXI clock
- - description: APB clock
- - description: MAC Main clock
- - description: PTP clock
- - description: RMII reference clock provided by MAC
- - description: MAC clock gate
-
- clock-names:
- minItems: 5
- items:
- - const: axi
- - const: apb
- - const: mac_main
- - const: ptp_ref
- - const: rmii_internal
- - const: mac_cg
-
interrupts:
maxItems: 1
@@ -147,6 +126,58 @@ required:
- phy-mode
- mediatek,pericfg
+allOf:
+ - $ref: snps,dwmac.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt2712-gmac
+ - mediatek,mt8188-gmac
+ - mediatek,mt8195-gmac
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ items:
+ - description: AXI clock
+ - description: APB clock
+ - description: MAC Main clock
+ - description: PTP clock
+ - description: RMII reference clock provided by MAC
+ - description: MAC clock gate
+
+ clock-names:
+ minItems: 5
+ items:
+ - const: axi
+ - const: apb
+ - const: mac_main
+ - const: ptp_ref
+ - const: rmii_internal
+ - const: mac_cg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8189-gmac
+ then:
+ properties:
+ clocks:
+ items:
+ - description: MAC Main clock
+ - description: PTP clock
+ - description: RMII reference clock provided by MAC
+
+ clock-names:
+ items:
+ - const: mac_main
+ - const: ptp_ref
+ - const: rmii_internal
+
unevaluatedProperties: false
examples:
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
index 30ae0dba7fffdb..e7e336b1f114c4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
@@ -36,8 +36,16 @@
#define ETH_FINE_DLY_GTXC BIT(1)
#define ETH_FINE_DLY_RXC BIT(0)
+/* Peri Configuration register for mt8189 */
+#define MT8189_PERI_ETH_CTRL_BASE 0x270
+
+#define MT8189_CTRL0_TXC_OUT_OP BIT(20)
+#define MT8189_CTRL0_DLY_GTXC_STAGE_FINE GENMASK(11, 6)
+
/* Peri Configuration register for mt8195 */
-#define MT8195_PERI_ETH_CTRL0 0xFD0
+#define MT8195_PERI_ETH_CTRL_BASE 0xFD0
+
+#define MT8195_PERI_ETH_CTRL0 0x0
#define MT8195_RMII_CLK_SRC_INTERNAL BIT(28)
#define MT8195_RMII_CLK_SRC_RXC BIT(27)
#define MT8195_ETH_INTF_SEL GENMASK(26, 24)
@@ -47,7 +55,7 @@
#define MT8195_DLY_GTXC_ENABLE BIT(5)
#define MT8195_DLY_GTXC_STAGES GENMASK(4, 0)
-#define MT8195_PERI_ETH_CTRL1 0xFD4
+#define MT8195_PERI_ETH_CTRL1 0x4
#define MT8195_DLY_RXC_INV BIT(25)
#define MT8195_DLY_RXC_ENABLE BIT(18)
#define MT8195_DLY_RXC_STAGES GENMASK(17, 13)
@@ -55,7 +63,7 @@
#define MT8195_DLY_TXC_ENABLE BIT(5)
#define MT8195_DLY_TXC_STAGES GENMASK(4, 0)
-#define MT8195_PERI_ETH_CTRL2 0xFD8
+#define MT8195_PERI_ETH_CTRL2 0x8
#define MT8195_DLY_RMII_RXC_INV BIT(25)
#define MT8195_DLY_RMII_RXC_ENABLE BIT(18)
#define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13)
@@ -95,7 +103,10 @@ struct mediatek_dwmac_variant {
u32 rx_delay_max;
u32 tx_delay_max;
+ u32 peri_eth_ctrl_offset;
u8 dma_bit_mask;
+ bool use_out_op;
+ bool use_stage_fine;
};
/* list of clocks required for mac */
@@ -107,7 +118,11 @@ static const char * const mt8195_dwmac_clk_l[] = {
"axi", "apb", "mac_cg", "mac_main", "ptp_ref"
};
-static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,
+static const char * const mt8189_dwmac_clk_l[] = {
+ "mac_main", "ptp_ref"
+};
+
+static int set_phy_interface_v1(struct mediatek_dwmac_plat_data *plat,
u8 phy_intf_sel)
{
u32 intf_val = phy_intf_sel;
@@ -124,7 +139,7 @@ static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,
return 0;
}
-static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
+static void delay_ps2stage_v1(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -149,7 +164,7 @@ static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
}
}
-static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
+static void delay_stage2ps_v1(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -174,12 +189,12 @@ static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
}
}
-static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
+static int set_delay_v1(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
u32 delay_val = 0, fine_val = 0;
- mt2712_delay_ps2stage(plat);
+ delay_ps2stage_v1(plat);
switch (plat->phy_mode) {
case PHY_INTERFACE_MODE_MII:
@@ -258,14 +273,14 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
- mt2712_delay_stage2ps(plat);
+ delay_stage2ps_v1(plat);
return 0;
}
static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
- .dwmac_set_phy_interface = mt2712_set_interface,
- .dwmac_set_delay = mt2712_set_delay,
+ .dwmac_set_phy_interface = set_phy_interface_v1,
+ .dwmac_set_delay = set_delay_v1,
.clk_list = mt2712_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
.rx_delay_max = 17600,
@@ -273,10 +288,11 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
.dma_bit_mask = 33,
};
-static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
+static int set_phy_interface_v2(struct mediatek_dwmac_plat_data *plat,
u8 phy_intf_sel)
{
u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel);
+ u32 reg_offset = plat->variant->peri_eth_ctrl_offset;
if (phy_intf_sel == PHY_INTF_SEL_RMII) {
if (plat->rmii_clk_from_mac)
@@ -288,12 +304,17 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
/* MT8195 only support external PHY */
intf_val |= MT8195_EXT_PHY_MODE;
- regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val);
+ if (plat->variant->use_out_op)
+ intf_val |= MT8189_CTRL0_TXC_OUT_OP;
+
+ regmap_write(plat->peri_regmap,
+ reg_offset + MT8195_PERI_ETH_CTRL0,
+ intf_val);
return 0;
}
-static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
+static void delay_ps2stage_v2(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -302,7 +323,7 @@ static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
mac_delay->rx_delay /= 290;
}
-static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
+static void delay_stage2ps_v2(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -311,12 +332,16 @@ static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
mac_delay->rx_delay *= 290;
}
-static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
+static int set_delay_v2(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
- u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0;
+ u32 reg_offset = plat->variant->peri_eth_ctrl_offset;
+ u32 gtxc_delay_mask = 0;
+ u32 gtxc_delay_val = 0;
+ u32 rmii_delay_val = 0;
+ u32 delay_val = 0;
- mt8195_delay_ps2stage(plat);
+ delay_ps2stage_v2(plat);
switch (plat->phy_mode) {
case PHY_INTERFACE_MODE_MII:
@@ -388,6 +413,9 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay);
gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv);
+ if (plat->variant->use_stage_fine)
+ gtxc_delay_val |= MT8189_CTRL0_DLY_GTXC_STAGE_FINE;
+
delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
@@ -398,29 +426,52 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
return -EINVAL;
}
+ gtxc_delay_mask = MT8195_RGMII_TXC_PHASE_CTRL |
+ MT8195_DLY_GTXC_INV |
+ MT8195_DLY_GTXC_ENABLE |
+ MT8195_DLY_GTXC_STAGES;
+
+ if (plat->variant->use_stage_fine)
+ gtxc_delay_mask |= MT8189_CTRL0_DLY_GTXC_STAGE_FINE;
+
regmap_update_bits(plat->peri_regmap,
- MT8195_PERI_ETH_CTRL0,
- MT8195_RGMII_TXC_PHASE_CTRL |
- MT8195_DLY_GTXC_INV |
- MT8195_DLY_GTXC_ENABLE |
- MT8195_DLY_GTXC_STAGES,
+ reg_offset + MT8195_PERI_ETH_CTRL0,
+ gtxc_delay_mask,
gtxc_delay_val);
- regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val);
- regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val);
+ regmap_write(plat->peri_regmap,
+ reg_offset + MT8195_PERI_ETH_CTRL1,
+ delay_val);
+ regmap_write(plat->peri_regmap,
+ reg_offset + MT8195_PERI_ETH_CTRL2,
+ rmii_delay_val);
- mt8195_delay_stage2ps(plat);
+ delay_stage2ps_v2(plat);
return 0;
}
+static const struct mediatek_dwmac_variant mt8189_gmac_variant = {
+ .dwmac_set_phy_interface = set_phy_interface_v2,
+ .dwmac_set_delay = set_delay_v2,
+ .clk_list = mt8189_dwmac_clk_l,
+ .num_clks = ARRAY_SIZE(mt8189_dwmac_clk_l),
+ .dma_bit_mask = 35,
+ .rx_delay_max = 9280,
+ .tx_delay_max = 9280,
+ .peri_eth_ctrl_offset = MT8189_PERI_ETH_CTRL_BASE,
+ .use_out_op = true,
+ .use_stage_fine = true,
+};
+
static const struct mediatek_dwmac_variant mt8195_gmac_variant = {
- .dwmac_set_phy_interface = mt8195_set_interface,
- .dwmac_set_delay = mt8195_set_delay,
+ .dwmac_set_phy_interface = set_phy_interface_v2,
+ .dwmac_set_delay = set_delay_v2,
.clk_list = mt8195_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
.rx_delay_max = 9280,
.tx_delay_max = 9280,
.dma_bit_mask = 35,
+ .peri_eth_ctrl_offset = MT8195_PERI_ETH_CTRL_BASE,
};
static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
@@ -662,6 +713,8 @@ static void mediatek_dwmac_remove(struct platform_device *pdev)
static const struct of_device_id mediatek_dwmac_match[] = {
{ .compatible = "mediatek,mt2712-gmac",
.data = &mt2712_gmac_variant },
+ { .compatible = "mediatek,mt8189-gmac",
+ .data = &mt8189_gmac_variant },
{ .compatible = "mediatek,mt8195-gmac",
.data = &mt8195_gmac_variant },
{ }
|
| 3/2 | 2026/07/07 15:45 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 6925 output: 22 thoughts: 760 Thoughts: **Analyzing the New GMAC Variant Patch** Okay, so I'm looking at this patch. It's touching `dwmac-mediatek.c` and the device tree bindings. The goal is to add support for a new MediaTek GMAC variant: `mt8189-gmac`. It looks like there's some function refactoring happening too, which is always something to pay close attention to, making sure the changes are clean and don't introduce regressions. They're renaming a bunch of `mt2712_` and `mt8195_` functions to a `v1` and `v2` scheme, and then using the `v2` versions for this new `mt8189_gmac_variant`. My immediate thought is, can I even *test* this in a virtual environment? This is a hardware-specific driver, `dwmac-mediatek.c`, and those are often a pain. Platform drivers for specific SoCs like the MediaTek ones are typically not testable in generic QEMU, unless there's dedicated machine emulation for the target hardware. So, I need to check if this driver can even be probed in QEMU or if it's strictly tied to the physical hardware device tree. The driver matches on the usual MediaTek GMAC IDs like `mediatek,mt8189-gmac`, and so on. Unless I can inject a device tree node into the environment, or QEMU has *specific* emulation for this MediaTek board (which is unlikely), it's probably unreachable. Now, wait, could I use something like syzkaller? Syzkaller *can* inject platform devices using `syz_dev_platform_add` or by manipulating the device tree, but most platform drivers like this that MMIO to specific physical addresses would crash or just fail to probe without the actual hardware present unless, of course, the registers are mocked. And I've found in the past that while syzkaller has pseudo-devices for *some* things, random SoC ethernet MACs are usually just a no-go for probing. So, is it fuzzable? Probably not, at least not in any sensible way. Unless it's a USB or PCI device that can be emulated (with a dummy HCD or PCI emulation), or is a *virtual* driver, I'm going to consider it unreachable for the time being. Generally, these SoC-specific Ethernet MAC drivers are not fuzzable in x86 VMs. I should just double-check that `dwmac-mediatek.c` is tied to `CONFIG_DWMAC_MEDIATEK`. It's worth verifying. |
| 4/2 | 2026/07/07 15:45 | tool | grepper |
0mArgs:{
"Expression": "config DWMAC_MEDIATEK"
}Results: {
"Output": "drivers/net/ethernet/stmicro/stmmac/Kconfig=106=config DWMAC_LPC18XX\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-113-\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:114:config DWMAC_MEDIATEK\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-115-\ttristate \"MediaTek MT27xx GMAC support\"\n"
} |
| 5/2 | 2026/07/07 15:45 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 8413 output: 44 thoughts: 16 Thoughts: Here's a summary of my thought process, as requested: **Assessing Dependencies for `DWMAC_MEDIATEK`** Okay, first things first, let's dive into the `DWMAC_MEDIATEK` module and map out its landscape. I need a clear understanding of its dependencies. This is critical for everything from troubleshooting integration issues to predicting the impact of potential modifications down the line. We can't afford to have a cascade of unexpected behavior. So, I'm thinking, where do we start? I need to know: what other modules or libraries does `DWMAC_MEDIATEK` rely on? Are these internal components, specific to the MediaTek platform, or are we dealing with external libraries? What version control is in place for these dependencies? Are they locked to specific versions, or do we have a range we can work with? Are there known compatibility issues between the module and any of its dependencies? Have there been reports of instability in certain dependency versions? I need to understand the interfaces. How does `DWMAC_MEDIATEK` interact with these components? Is it through direct function calls, message passing, or some other mechanism? Are there any shared resources, like memory regions, that might require careful synchronization? What kind of testing and validation is in place to ensure these dependencies are properly managed? Alright, let's get down to specifics. We need to gather this information to build a solid foundation. |
| 6/2 | 2026/07/07 15:45 | tool | grepper |
0mArgs:{
"Expression": "depends on.*ARCH_MEDIATEK",
"PathPrefix": "drivers/net/ethernet/stmicro/stmmac/Kconfig"
}Results: {
"Output": "drivers/net/ethernet/stmicro/stmmac/Kconfig=114=config DWMAC_MEDIATEK\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-115-\ttristate \"MediaTek MT27xx GMAC support\"\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:116:\tdepends on OF \u0026\u0026 (ARCH_MEDIATEK || COMPILE_TEST)\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-117-\thelp\n"
} |
| 7/2 | 2026/07/07 15:45 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 8920 output: 97 thoughts: 264 Thoughts: **My Assessment of the Patch's Fuzzing Potential** Okay, let's break this down. My initial instinct is that this patch isn't going to be fruitful for fuzzing in a standard setup. The conditional compilation (`ARCH_MEDIATEK || COMPILE_TEST`) is a dead giveaway. Since this is a platform driver specifically for MediaTek SoCs, it's virtually impossible to reach in your average x86 QEMU VM. It hinges on having the correct device tree nodes defined and the correct physical MMIO registers mapped, things that just aren't going to happen in a generic virtual environment. Even if you tried to fake it by injecting a device tree node, either `devm_regmap_init` or `syscon_regmap_lookup_by_phandle` is going to fail, or any attempted MMIO access will fault, do nothing, or simply not be reachable because the hardware doesn't exist. Let's quickly confirm there's no generic logic that *could* be exercised. Ah, nope. Looks like the patch's changes consist of adding a new variant structure, some function renaming, and a handful of bitwise operations for the new variant. It's pure hardware enablement, essentially tailoring the driver for a specific SoC. It's not exposing generic functionality. Therefore, I'm setting `WorthFuzzing=false`. The rationale is straightforward: This patch introduces support for a new MediaTek SoC, the MT8189, within the dwmac-mediatek platform driver. It's entirely hardware-specific code that depends on physical MMIO registers and particular device tree configurations. This means that executing or reaching it in generic virtualized environments like QEMU or GCE is essentially meaningless. Any fuzzing attempts would be fruitless because the underlying hardware dependencies are simply not present. |
| 8/2 | 2026/07/07 15:46 | tool | set-results |
0mArgs:{
"EnableConfigs": [],
"FocusSymbols": [],
"Reasoning": "The patch adds support for a new MediaTek SoC (MT8189) to the dwmac-mediatek platform driver. This is hardware-specific code that relies on physical MMIO registers and specific device tree configurations, which cannot be meaningfully executed or reached in generic virtualized environments like QEMU or GCE.",
"WorthFuzzing": false
}Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch adds support for a new MediaTek SoC (MT8189) to the dwmac-mediatek platform driver. This is hardware-specific code that relies on physical MMIO registers and specific device tree configurations, which cannot be meaningfully executed or reached in generic virtualized environments like QEMU or GCE.",
"WorthFuzzing": false
} |
| Total Calls | Total Tokens | Avg Tokens | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|
| Total Calls | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|