| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/07/17 08:41 | flow | patch-triage |
5mArgs:null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch introduces a new PCS subsystem and an Airoha AN7581 PCS driver, and modifies the Airoha ethernet driver to use it. The new PCS subsystem and the modifications to phylink are only used by the Airoha driver. The Airoha driver is a hardware-specific platform driver that requires a specific device tree structure (child nodes, reset lines, syscon) and hardware registers to probe successfully. Therefore, the new code paths are impossible to reach in virtualized environments like GCE or QEMU.",
"WorthFuzzing": false
} |
| 1/1 | 2026/07/17 08:41 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit 4da378eff5f142d2ebbe83411747eb176ed016cd\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Fri Jul 17 08:41:20 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml\nnew file mode 100644\nindex 00000000000000..9c1d116c1b016d\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml\n@@ -0,0 +1,261 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Airoha Ethernet PCS and Serdes\n+\n+maintainers:\n+ - Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+\n+description:\n+ Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for\n+ the various Serdes port supporting different Media Independent Interface\n+ (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).\n+\n+properties:\n+ compatible:\n+ enum:\n+ - airoha,an7581-pcs-eth\n+ - airoha,an7581-pcs-pon\n+ - airoha,an7581-pcs-pcie\n+ - airoha,an7581-pcs-usb\n+\n+ reg:\n+ minItems: 6\n+ maxItems: 15\n+\n+ reg-names:\n+ minItems: 6\n+ maxItems: 15\n+\n+ airoha,scu:\n+ $ref: /schemas/types.yaml#/definitions/phandle\n+ description: phandle to the SCU node required to configure\n+ the serdes line to the correct interface mode.\n+\n+ phys:\n+ maxItems: 1\n+\n+ \"#pcs-cells\": true\n+\n+required:\n+ - compatible\n+ - reg\n+ - reg-names\n+ - \"#pcs-cells\"\n+\n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - airoha,an7581-pcs-eth\n+ - airoha,an7581-pcs-pon\n+\n+ then:\n+ properties:\n+ reg:\n+ items:\n+ - description: PCS MAC reg\n+ - description: HSGMII AN reg\n+ - description: HSGMII PCS reg\n+ - description: MULTI SGMII reg\n+ - description: USXGMII reg\n+ - description: HSGMII rate adaption reg\n+ - description: PCS Analog register\n+ - description: PCS PMA (Physical Medium Attachment) register\n+\n+ reg-names:\n+ items:\n+ - const: pcs_mac\n+ - const: hsgmii_an\n+ - const: hsgmii_pcs\n+ - const: multi_sgmii\n+ - const: usxgmii\n+ - const: hsgmii_rate_adp\n+ - const: pcs_ana\n+ - const: pcs_pma\n+\n+ phys: false\n+\n+ \"#pcs-cells\":\n+ const: 0\n+\n+ required:\n+ - airoha,scu\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ const: airoha,an7581-pcs-pcie\n+\n+ then:\n+ properties:\n+ reg:\n+ items:\n+ - description: PCS MAC 0 reg\n+ - description: HSGMII AN 0 reg\n+ - description: HSGMII PCS 0 reg\n+ - description: MULTI SGMII 0 reg\n+ - description: USXGMII 0 reg\n+ - description: HSGMII rate adaption 0 reg\n+ - description: PCS MAC 1 reg\n+ - description: HSGMII AN 1 reg\n+ - description: HSGMII PCS 1 reg\n+ - description: MULTI SGMII 1 reg\n+ - description: USXGMII 1 reg\n+ - description: HSGMII rate adaption 1 reg\n+ - description: PCS Analog register\n+ - description: PCS PMA (Physical Medium Attachment) 0 register\n+ - description: PCS PMA (Physical Medium Attachment) 1 register\n+\n+ reg-names:\n+ items:\n+ - const: pcs_mac0\n+ - const: hsgmii_an0\n+ - const: hsgmii_pcs0\n+ - const: multi_sgmii0\n+ - const: usxgmii0\n+ - const: hsgmii_rate_adp0\n+ - const: pcs_mac1\n+ - const: hsgmii_an1\n+ - const: hsgmii_pcs1\n+ - const: multi_sgmii1\n+ - const: usxgmii1\n+ - const: hsgmii_rate_adp1\n+ - const: pcs_ana\n+ - const: pcs_pma0\n+ - const: pcs_pma1\n+\n+ phys: false\n+\n+ \"#pcs-cells\":\n+ const: 1\n+\n+ required:\n+ - airoha,scu\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ const: airoha,an7581-pcs-usb\n+\n+ then:\n+ properties:\n+ reg:\n+ items:\n+ - description: PCS MAC reg\n+ - description: HSGMII AN reg\n+ - description: HSGMII PCS reg\n+ - description: MULTI SGMII reg\n+ - description: HSGMII rate adaption reg\n+ - description: PCS Analog register\n+\n+ reg-names:\n+ items:\n+ - const: pcs_mac\n+ - const: hsgmii_an\n+ - const: hsgmii_pcs\n+ - const: multi_sgmii\n+ - const: hsgmii_rate_adp\n+ - const: pcs_ana\n+\n+ airoha,scu: false\n+\n+ \"#pcs-cells\":\n+ const: 0\n+\n+ required:\n+ - phys\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include \u003cdt-bindings/phy/phy.h\u003e\n+\n+ pcs@1fa08000 {\n+ compatible = \"airoha,an7581-pcs-pon\";\n+ reg = \u003c0x1fa08000 0x1000\u003e,\n+ \u003c0x1fa80000 0x60\u003e,\n+ \u003c0x1fa80a00 0x164\u003e,\n+ \u003c0x1fa84000 0x450\u003e,\n+ \u003c0x1fa85900 0x338\u003e,\n+ \u003c0x1fa86000 0x300\u003e,\n+ \u003c0x1fa8a000 0x1000\u003e,\n+ \u003c0x1fa8b000 0x1000\u003e;\n+ reg-names = \"pcs_mac\", \"hsgmii_an\", \"hsgmii_pcs\",\n+ \"multi_sgmii\", \"usxgmii\",\n+ \"hsgmii_rate_adp\", \"pcs_ana\", \"pcs_pma\";\n+\n+ airoha,scu = \u003c\u0026scuclk\u003e;\n+ #pcs-cells = \u003c0\u003e;\n+ };\n+\n+ pcs@1fa09000 {\n+ compatible = \"airoha,an7581-pcs-eth\";\n+ reg = \u003c0x1fa09000 0x1000\u003e,\n+ \u003c0x1fa70000 0x60\u003e,\n+ \u003c0x1fa70a00 0x164\u003e,\n+ \u003c0x1fa74000 0x450\u003e,\n+ \u003c0x1fa75900 0x338\u003e,\n+ \u003c0x1fa76000 0x300\u003e,\n+ \u003c0x1fa7a000 0x1000\u003e,\n+ \u003c0x1fa7b000 0x1000\u003e;\n+ reg-names = \"pcs_mac\", \"hsgmii_an\", \"hsgmii_pcs\",\n+ \"multi_sgmii\", \"usxgmii\",\n+ \"hsgmii_rate_adp\", \"pcs_ana\", \"pcs_pma\";\n+\n+ airoha,scu = \u003c\u0026scuclk\u003e;\n+ #pcs-cells = \u003c0\u003e;\n+ };\n+\n+ pcs@1fa04000 {\n+ compatible = \"airoha,an7581-pcs-pcie\";\n+ reg = \u003c0x1fa04000 0x1000\u003e,\n+ \u003c0x1fa50000 0x60\u003e,\n+ \u003c0x1fa50a00 0x164\u003e,\n+ \u003c0x1fa54000 0x450\u003e,\n+ \u003c0x1fa55900 0x338\u003e,\n+ \u003c0x1fa56000 0x300\u003e,\n+ \u003c0x1fa05000 0x1000\u003e,\n+ \u003c0x1fa60000 0x60\u003e,\n+ \u003c0x1fa60a00 0x164\u003e,\n+ \u003c0x1fa64000 0x450\u003e,\n+ \u003c0x1fa65900 0x338\u003e,\n+ \u003c0x1fa66000 0x300\u003e,\n+ \u003c0x1fa5a000 0x1000\u003e,\n+ \u003c0x1fa5b000 0x1000\u003e,\n+ \u003c0x1fa5c000 0x1000\u003e;\n+ reg-names = \"pcs_mac0\", \"hsgmii_an0\", \"hsgmii_pcs0\",\n+ \"multi_sgmii0\", \"usxgmii0\",\n+ \"hsgmii_rate_adp0\",\n+ \"pcs_mac1\", \"hsgmii_an1\", \"hsgmii_pcs1\",\n+ \"multi_sgmii1\", \"usxgmii1\",\n+ \"hsgmii_rate_adp1\",\n+ \"pcs_ana\", \"pcs_pma0\", \"pcs_pma1\";\n+\n+ airoha,scu = \u003c\u0026scuclk\u003e;\n+ #pcs-cells = \u003c1\u003e;\n+ };\n+\n+ pcs@1fa07000 {\n+ compatible = \"airoha,an7581-pcs-usb\";\n+ reg = \u003c0x1fa07000 0x1000\u003e,\n+ \u003c0x1fa90000 0x60\u003e,\n+ \u003c0x1fa90a00 0x164\u003e,\n+ \u003c0x1fa94000 0x450\u003e,\n+ \u003c0x1fa96000 0x300\u003e,\n+ \u003c0x1fa9a000 0x600\u003e;\n+ reg-names = \"pcs_mac\", \"hsgmii_an\", \"hsgmii_pcs\",\n+ \"multi_sgmii\", \"hsgmii_rate_adp\",\"pcs_ana\";\n+\n+ phys = \u003c\u0026usb0_phy PHY_TYPE_USB3\u003e;\n+\n+ #pcs-cells = \u003c0\u003e;\n+ };\ndiff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst\nindex 44a422ad3b0553..3fce8f6ac089ee 100644\n--- a/Documentation/networking/index.rst\n+++ b/Documentation/networking/index.rst\n@@ -28,6 +28,7 @@ Contents:\n net_failover\n page_pool\n phy\n+ pcs\n sfp-phylink\n alias\n bridge\ndiff --git a/Documentation/networking/pcs.rst b/Documentation/networking/pcs.rst\nnew file mode 100644\nindex 00000000000000..98592cdee3ef20\n--- /dev/null\n+++ b/Documentation/networking/pcs.rst\n@@ -0,0 +1,229 @@\n+.. SPDX-License-Identifier: GPL-2.0\n+\n+=============\n+PCS Subsystem\n+=============\n+\n+The PCS (Physical Coding Sublayer) subsystem handles the registration and lookup\n+of PCS devices. These devices contain the upper sublayers of the Ethernet\n+physical layer, generally handling framing, scrambling, and encoding tasks. PCS\n+devices may also include PMA (Physical Medium Attachment) components. PCS\n+devices transfer data between the Link-layer MAC device, and the rest of the\n+physical layer, typically via a serdes. The output of the serdes may be\n+connected more-or-less directly to the medium when using fiber-optic or\n+backplane connections (1000BASE-SX, 1000BASE-KX, etc). It may also communicate\n+with a separate PHY (such as over SGMII) which handles the connection to the\n+medium (such as 1000BASE-T).\n+\n+Remark on usage of .mac_select_pcs and fw_node PCS\n+--------------------------------------------------\n+\n+There are generally two ways to look up a PCS device.\n+\n+1. MAC OP struct .mac_select_pcs (considered legacy)\n+2. firmware node (fwnode) PCS entirely handled by phylink\n+\n+Implementation 1 leaves the entire handling of the PCS to the MAC\n+driver with the selection of the PCS driven by .mac_select_pcs.\n+Custom implementations are required if the PCS is external to the MAC\n+and needs to be handled by a separate driver.\n+\n+This implementation is considered legacy and it's suggested to\n+switch to the new fwnode PCS.\n+\n+Looking up PCS Devices (fwnode implementation)\n+-----------------------------------------------\n+\n+The lookup of a PCS device follows the common producer/consumer implementation\n+used by similar subsystems with a ``#pcs-cells`` on the producer and a\n+``pcs-handle`` property on the consumer::\n+\n+ pcs: pcs {\n+ // ...\n+ #pcs-cells = \u003c0\u003e;\n+ };\n+\n+ ethernet-controller {\n+ // ...\n+ pcs-handle = \u003c\u0026pcs\u003e;\n+ };\n+\n+On :c:func:`phylink_create`, phylink will use the ``num_possible_pcs``\n+value and ``fill_available_pcs`` helper function in\n+:c:struct:`phylink_config` to compose the list of available PCS that can be\n+used for the phylink instance.\n+\n+Phylink will then internally handle the selection of the correct PCS for\n+the requested interface mode based on the interface modes configured in\n+``pcs_interfaces`` in :c:struct:`phylink_config` struct and\n+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.\n+\n+A PCS is considered eligible when the requested interface mode is present\n+in both ``pcs_interfaces`` in :c:struct:`phylink_config` struct and\n+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.\n+\n+``supported_interfaces`` describes all interface modes supported by the MAC,\n+whereas ``pcs_interfaces`` identifies the subset that require PCS selection.\n+\n+For the special implementation where the PCS is internal or part of the MAC\n+and a dedicated driver is not needed, it's possible to leave the implementation\n+of the PCS to the MAC driver and just implement the ``num_possible_pcs``\n+value and ``fill_available_pcs`` helper function in\n+:c:struct:`phylink_config` referencing the local :c:struct:`phylink_pcs`\n+struct allocated from the MAC driver.\n+\n+Using PCS Devices\n+-----------------\n+\n+It's mandatory to either implement the ``mac_select_pcs`` callback\n+of :c:struct:`phylink_mac_ops` or ``num_possible_pcs`` and ``fill_available_pcs``\n+of :c:struct:`phylink_config` to use a PCS for a MAC.\n+\n+The fwnode implementation exposes simple helpers to parse the PCS from\n+the fwnode :c:func:`fwnode_phylink_pcs_count` and\n+:c:func:`fwnode_phylink_pcs_parse`. The :c:func:`fwnode_phylink_pcs_count` helper\n+takes the fwnode where the ``pcs-handle`` should be parsed and return the\n+number of PCS entries described in the fwnode.\n+The :c:func:`fwnode_phylink_pcs_parse` helper takes three arguments,\n+the fwnode where the ``pcs-handle`` should be parsed, an allocated array\n+of :c:struct:`phylink_pcs` pointer where to put the parsed PCS from the fwnode\n+and the maximum number of PCS to parse.\n+Contrary to :c:func:`fwnode_phylink_pcs_count`, :c:func:`fwnode_phylink_pcs_parse`\n+helper fills the allocated array with ONLY the available PCS and return the\n+number of available PCS found. PCS that returns -ENODEV will be skipped and\n+won't be inserted in the allocated array.\n+\n+A phylink instance may use multiple PCS devices. The maximum number is reported\n+through ``num_possible_pcs``.\n+\n+It's mandatory to specify for what interface a PCS is needed. This can be done\n+by filling the ``pcs_interfaces`` in :c:struct:`phylink_config` struct.\n+If the requested interface mode is not present in this bitmask, phylink does\n+not search for a PCS for that specific mode. (example MAC doesn't need a PCS\n+for SGMII but require one for USXGMII)\n+\n+With the use of the :c:func:`fwnode_phylink_pcs_parse` a common implementation\n+is the following::\n+\n+ static int mac_fill_available_pcs(struct phylink_config *config,\n+ \t\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t\t\t unsigned int num_possible_pcs)\n+ {\n+ \tstruct device *dev = config-\u003edev;\n+\n+ \treturn fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,\n+\t\t\t\t\t\t num_possible_pcs);\n+ }\n+\n+ static int mac_setup_phylink(struct net_device *netdev)\n+ {\n+ struct phylink_config *config;\n+\n+ // ...\n+\n+ config-\u003edev = \u0026netdev-\u003edev;\n+\n+ // ...\n+\n+ // Parse possible PCS and fill num_possible_pcs.\n+ config-\u003enum_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(\u0026netdev-\u003edev));\n+ config-\u003efill_available_pcs = mac_fill_available_pcs;\n+\n+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config-\u003esupported_interfaces);\n+ __set_bit(PHY_INTERFACE_MODE_SGMII, config-\u003esupported_interfaces);\n+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, config-\u003esupported_interfaces);\n+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config-\u003esupported_interfaces);\n+\n+ // PCS required only for USXGMII\n+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config-\u003epcs_interfaces);\n+\n+ phylink = phylink_create(config, //...\n+\n+It's worth to mention that it's phylink code that takes care of allocating\n+the array of :c:struct:`phylink_pcs` pointer for ``fill_available_pcs``\n+callback based on the value set in ``num_possible_pcs`` for\n+:c:struct:`phylink_config` struct.\n+\n+The ``fill_available_pcs`` callback must not write more than\n+``num_possible_pcs`` entries. The third argument may be used to validate\n+that there is enough space to fill all the available PCS in the passed array\n+of :c:struct:`phylink_pcs` pointer.\n+\n+The ``fill_available_pcs`` callback is called only on :c:func:`phylink_create`\n+and is used only to compose the initial available PCS list. Ownership of PCS\n+is held by phylink and :c:func:`phylink_release_pcs` should be used to release\n+them.\n+\n+Writing PCS Drivers\n+-------------------\n+\n+To write a PCS driver, first implement :c:struct:`phylink_pcs_ops`. Then,\n+register your PCS in your probe function using :c:func:`fwnode_pcs_add_provider`.\n+The :c:func:`fwnode_pcs_add_provider` takes three arguments, the fwnode where\n+the PCS provider should be registered to, a get function to return the requested\n+PCS based on ``#pcs-cells`` and a pointer to reference private data for the get\n+function.\n+\n+The PCS will then be registered to a global list of PCS provider that the\n+PCS fwnode implementation will use to parse it.\n+\n+For the simple case where the PCS driver expose a single PCS,\n+:c:func:`fwnode_pcs_simple_get` can be used as the get function.\n+\n+You must call :c:func:`fwnode_pcs_del_provider` from your remove function and\n+release the PCS from any phylink instance under RTNL lock with\n+:c:func:`phylink_release_pcs`::\n+\n+ fwnode_pcs_del_provider(dev_fwnode(\u0026pdev-\u003edev));\n+\n+\trtnl_lock();\n+\n+\tfor (i = 0; i \u003c data-\u003enum_port; i++) {\n+\t\tstruct pcs_port *port = \u0026priv-\u003eports[i];\n+\n+\t\tphylink_release_pcs(\u0026port-\u003epcs);\n+\t}\n+\n+\trtnl_unlock();\n+\n+Late PCS registration handling\n+------------------------------\n+\n+It's possible that a PCS becomes available after the MAC finished probing.\n+Contrary to the usual producer/consumer implementation, when a PCS is not\n+registered and can't be found, the fwnode parser helper returns ``-ENODEV``\n+instead of ``-EPROBE_DEFER``.\n+\n+This is to prevent race condition with particular devices that register\n+MAC and PCS with USB or PCIe and require the MAC to be registered before\n+the PCS.\n+\n+The phylink logic correctly handle this special case and keep the phylink\n+instance in a fail condition.\n+\n+The PCS fwnode implementation provides a notifier to which each phylink\n+instance with a non-empty ``pcs_interfaces`` in :c:type:`phylink_config`\n+registers. When a new PCS provider is registered, the notifier is called\n+triggering the :c:func:`pcs_provider_notify` function.\n+\n+Function :c:func:`pcs_provider_notify` will check if the just added PCS\n+should be used by the phylink instance. If it should be used then,\n+it's added to the internal list of available PCS and a phylink major\n+config is forced.\n+\n+If a phylink instance was in a failure state, with the just added PCS\n+now part of the available PCS internal phylink list, provided all other\n+conditions are satisfied, the configuration is retried and the failure\n+condition is cleared.\n+\n+API Reference\n+-------------\n+\n+.. kernel-doc:: include/linux/phylink.h\n+ :identifiers: phylink_pcs\n+\n+.. kernel-doc:: include/linux/pcs/pcs.h\n+ :internal:\n+\n+.. kernel-doc:: include/linux/pcs/pcs-provider.h\n+ :internal:\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex f3218abefd0c6b..51704a90ca4683 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -9682,6 +9682,15 @@ F:\tinclude/uapi/linux/if_bridge.h\n F:\tinclude/linux/netfilter_bridge/\n F:\tnet/bridge/\n \n+ETHERNET PCS SUBSYSTEM\n+M:\tChristian Marangi \u003cansuelsmth@gmail.com\u003e\n+L:\tnetdev@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/networking/pcs.rst\n+F:\tdrivers/net/pcs/pcs.c\n+F:\tinclude/linux/pcs/pcs-provider.h\n+F:\tinclude/linux/pcs/pcs.h\n+\n ETHERNET PHY LIBRARY\n M:\tAndrew Lunn \u003candrew@lunn.ch\u003e\n M:\tHeiner Kallweit \u003chkallweit1@gmail.com\u003e\ndiff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig\nindex 1f6640a15fc947..789906516bf8fb 100644\n--- a/drivers/net/ethernet/airoha/Kconfig\n+++ b/drivers/net/ethernet/airoha/Kconfig\n@@ -20,6 +20,7 @@ config NET_AIROHA\n \tdepends on NET_DSA || !NET_DSA\n \tselect NET_AIROHA_NPU\n \tselect PAGE_POOL\n+\tselect PHYLINK\n \thelp\n \t This driver supports the gigabit ethernet MACs in the\n \t Airoha SoC family.\ndiff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c\nindex 59001fd4b6f740..ed1ac032f33747 100644\n--- a/drivers/net/ethernet/airoha/airoha_eth.c\n+++ b/drivers/net/ethernet/airoha/airoha_eth.c\n@@ -8,6 +8,7 @@\n #include \u003clinux/of_reserved_mem.h\u003e\n #include \u003clinux/platform_device.h\u003e\n #include \u003clinux/tcp.h\u003e\n+#include \u003clinux/pcs/pcs.h\u003e\n #include \u003clinux/u64_stats_sync.h\u003e\n #include \u003cnet/dst_metadata.h\u003e\n #include \u003cnet/page_pool/helpers.h\u003e\n@@ -1837,7 +1838,7 @@ static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)\n \tstruct airoha_gdm_port *port = dev-\u003eport;\n \tint i;\n \n-\tspin_lock(\u0026port-\u003estats_lock);\n+\tspin_lock(\u0026port-\u003elock);\n \n \tfor (i = 0; i \u003c ARRAY_SIZE(port-\u003edevs); i++) {\n \t\tif (port-\u003edevs[i])\n@@ -1848,7 +1849,7 @@ static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)\n \tairoha_fe_set(dev-\u003eeth, REG_FE_GDM_MIB_CLEAR(port-\u003eid),\n \t\t FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK);\n \n-\tspin_unlock(\u0026port-\u003estats_lock);\n+\tspin_unlock(\u0026port-\u003elock);\n }\n \n static void airoha_dev_set_xmit_frame_size(struct net_device *netdev)\n@@ -1870,6 +1871,14 @@ static int airoha_dev_open(struct net_device *netdev)\n \tu32 pse_port = FE_PSE_PORT_PPE1;\n \tint err;\n \n+\terr = phylink_of_phy_connect(dev-\u003ephylink, netdev-\u003edev.of_node, 0);\n+\tif (err) {\n+\t\tnetdev_err(netdev, \"could not attach PHY: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\tphylink_start(dev-\u003ephylink);\n+\n \tnetif_tx_start_all_queues(netdev);\n \terr = airoha_set_vip_for_gdm_port(dev, true);\n \tif (err)\n@@ -1909,6 +1918,10 @@ static int airoha_dev_stop(struct net_device *netdev)\n \t\tairoha_set_gdm_port_fwd_cfg(qdma-\u003eeth,\n \t\t\t\t\t REG_GDM_FWD_CFG(port-\u003eid),\n \t\t\t\t\t FE_PSE_PORT_DROP);\n+\n+\tphylink_stop(dev-\u003ephylink);\n+\tphylink_disconnect_phy(dev-\u003ephylink);\n+\n \treturn 0;\n }\n \n@@ -2389,6 +2402,24 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,\n \t} while (u64_stats_fetch_retry(\u0026dev-\u003estats.syncp, start));\n }\n \n+static int\n+airoha_ethtool_get_link_ksettings(struct net_device *netdev,\n+\t\t\t\t struct ethtool_link_ksettings *cmd)\n+{\n+\tstruct airoha_gdm_dev *dev = netdev_priv(netdev);\n+\n+\treturn phylink_ethtool_ksettings_get(dev-\u003ephylink, cmd);\n+}\n+\n+static int\n+airoha_ethtool_set_link_ksettings(struct net_device *netdev,\n+\t\t\t\t const struct ethtool_link_ksettings *cmd)\n+{\n+\tstruct airoha_gdm_dev *dev = netdev_priv(netdev);\n+\n+\treturn phylink_ethtool_ksettings_set(dev-\u003ephylink, cmd);\n+}\n+\n static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev,\n \t\t\t\t\t int channel, enum tx_sched_mode mode,\n \t\t\t\t\t const u16 *weights, u8 n_weights)\n@@ -3120,7 +3151,8 @@ static const struct ethtool_ops airoha_ethtool_ops = {\n \t.get_drvinfo\t\t= airoha_ethtool_get_drvinfo,\n \t.get_eth_mac_stats = airoha_ethtool_get_mac_stats,\n \t.get_rmon_stats\t\t= airoha_ethtool_get_rmon_stats,\n-\t.get_link_ksettings\t= phy_ethtool_get_link_ksettings,\n+\t.get_link_ksettings\t= airoha_ethtool_get_link_ksettings,\n+\t.set_link_ksettings\t= airoha_ethtool_set_link_ksettings,\n \t.get_link\t\t= ethtool_op_get_link,\n };\n \n@@ -3176,6 +3208,155 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,\n \treturn false;\n }\n \n+/* Nothing to do in MAC, everything is handled in PCS */\n+static void airoha_mac_config(struct phylink_config *config, unsigned int mode,\n+\t\t\t const struct phylink_link_state *state)\n+{\n+}\n+\n+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,\n+\t\t\t unsigned int mode, phy_interface_t interface,\n+\t\t\t int speed, int duplex, bool tx_pause, bool rx_pause)\n+{\n+\tstruct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev,\n+\t\t\t\t\t\t phylink_config);\n+\tstruct airoha_gdm_port *port = dev-\u003eport;\n+\tstruct airoha_eth *eth = dev-\u003eeth;\n+\tu32 frag_size_tx, frag_size_rx;\n+\tu32 mask, val;\n+\n+\t/* TX/RX frag is configured only for GDM4 */\n+\tif (port-\u003eid != AIROHA_GDM4_IDX)\n+\t\treturn;\n+\n+\tswitch (speed) {\n+\tcase SPEED_10000:\n+\tcase SPEED_5000:\n+\t\tfrag_size_tx = 8;\n+\t\tfrag_size_rx = 8;\n+\t\tbreak;\n+\tcase SPEED_2500:\n+\t\tfrag_size_tx = 2;\n+\t\tfrag_size_rx = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tfrag_size_tx = 1;\n+\t\tfrag_size_rx = 0;\n+\t}\n+\n+\tspin_lock(\u0026port-\u003elock);\n+\n+\t/* Configure TX/RX frag based on speed */\n+\tif (dev-\u003enbq == 1) {\n+\t\tmask = GDM4_SGMII1_TX_FRAG_SIZE_MASK;\n+\t\tval = FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK,\n+\t\t\t\t frag_size_tx);\n+\t} else {\n+\t\tmask = GDM4_SGMII0_TX_FRAG_SIZE_MASK;\n+\t\tval = FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK,\n+\t\t\t\t frag_size_tx);\n+\t}\n+\tairoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG, mask, val);\n+\n+\tif (dev-\u003enbq == 1) {\n+\t\tmask = GDM4_SGMII1_RX_FRAG_SIZE_MASK;\n+\t\tval = FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK,\n+\t\t\t\t frag_size_rx);\n+\t} else {\n+\t\tmask = GDM4_SGMII0_RX_FRAG_SIZE_MASK;\n+\t\tval = FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK,\n+\t\t\t\t frag_size_rx);\n+\t}\n+\tairoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG, mask, val);\n+\n+\tspin_unlock(\u0026port-\u003elock);\n+}\n+\n+/* Nothing to do in MAC, everything is handled in PCS */\n+static void airoha_mac_link_down(struct phylink_config *config, unsigned int mode,\n+\t\t\t\t phy_interface_t interface)\n+{\n+}\n+\n+static const struct phylink_mac_ops airoha_phylink_ops = {\n+\t.mac_config = airoha_mac_config,\n+\t.mac_link_up = airoha_mac_link_up,\n+\t.mac_link_down = airoha_mac_link_down,\n+};\n+\n+static int airoha_fill_available_pcs(struct phylink_config *config,\n+\t\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t\t unsigned int num_possible_pcs)\n+{\n+\tstruct device *dev = config-\u003edev;\n+\n+\treturn fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,\n+\t\t\t\t\tnum_possible_pcs);\n+}\n+\n+static int airoha_setup_phylink(struct net_device *netdev)\n+{\n+\tstruct airoha_gdm_dev *dev = netdev_priv(netdev);\n+\tstruct device_node *np = netdev-\u003edev.of_node;\n+\tstruct airoha_gdm_port *port = dev-\u003eport;\n+\tstruct phylink_config *config;\n+\tphy_interface_t phy_mode;\n+\tstruct phylink *phylink;\n+\tint err;\n+\n+\terr = of_get_phy_mode(np, \u0026phy_mode);\n+\tif (err) {\n+\t\tdev_err(\u0026netdev-\u003edev, \"incorrect phy-mode\\n\");\n+\t\treturn err;\n+\t}\n+\n+\tconfig = \u0026dev-\u003ephylink_config;\n+\tconfig-\u003edev = \u0026netdev-\u003edev;\n+\tconfig-\u003etype = PHYLINK_NETDEV;\n+\n+\t/*\n+\t * GDM1 only supports internal for Embedded Switch\n+\t * and doesn't require a PCS.\n+\t */\n+\tif (port-\u003eid == AIROHA_GDM1_IDX) {\n+\t\tconfig-\u003emac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |\n+\t\t\t\t\t MAC_10000FD;\n+\n+\t\t__set_bit(PHY_INTERFACE_MODE_INTERNAL,\n+\t\t\t config-\u003esupported_interfaces);\n+\t} else {\n+\t\tconfig-\u003emac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |\n+\t\t\t\t\t MAC_10 | MAC_100 | MAC_1000 |\n+\t\t\t\t\t MAC_2500FD | MAC_5000FD | MAC_10000FD;\n+\n+\t\tconfig-\u003enum_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config-\u003edev));\n+\t\tconfig-\u003efill_available_pcs = airoha_fill_available_pcs;\n+\n+\t\t__set_bit(PHY_INTERFACE_MODE_SGMII,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_1000BASEX,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_2500BASEX,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_10GBASER,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_USXGMII,\n+\t\t\t config-\u003esupported_interfaces);\n+\n+\t\tphy_interface_copy(config-\u003epcs_interfaces,\n+\t\t\t\t config-\u003esupported_interfaces);\n+\t}\n+\n+\tphylink = phylink_create(config, of_fwnode_handle(np),\n+\t\t\t\t phy_mode, \u0026airoha_phylink_ops);\n+\tif (IS_ERR(phylink))\n+\t\treturn PTR_ERR(phylink);\n+\n+\tdev-\u003ephylink = phylink;\n+\n+\treturn 0;\n+}\n+\n static int airoha_alloc_gdm_device(struct airoha_eth *eth,\n \t\t\t\t struct airoha_gdm_port *port,\n \t\t\t\t int nbq, struct device_node *np)\n@@ -3239,7 +3420,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,\n \tdev-\u003enbq = nbq;\n \tport-\u003edevs[index] = dev;\n \n-\treturn 0;\n+\treturn airoha_setup_phylink(netdev);\n }\n \n static int airoha_alloc_gdm_port(struct airoha_eth *eth,\n@@ -3274,7 +3455,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,\n \t\treturn -ENOMEM;\n \n \tport-\u003eid = id;\n-\tspin_lock_init(\u0026port-\u003estats_lock);\n+\tspin_lock_init(\u0026port-\u003elock);\n \teth-\u003eports[p] = port;\n \n \terr = airoha_metadata_dst_alloc(port);\n@@ -3471,6 +3652,8 @@ static int airoha_probe(struct platform_device *pdev)\n \t\t\tnetdev = netdev_from_priv(dev);\n \t\t\tif (netdev-\u003ereg_state == NETREG_REGISTERED)\n \t\t\t\tunregister_netdev(netdev);\n+\t\t\tif (dev-\u003ephylink)\n+\t\t\t\tphylink_destroy(dev-\u003ephylink);\n \t\t\tof_node_put(netdev-\u003edev.of_node);\n \t\t}\n \t\tairoha_metadata_dst_free(port);\n@@ -3509,6 +3692,7 @@ static void airoha_remove(struct platform_device *pdev)\n \n \t\t\tnetdev = netdev_from_priv(dev);\n \t\t\tunregister_netdev(netdev);\n+\t\t\tphylink_destroy(dev-\u003ephylink);\n \t\t\tof_node_put(netdev-\u003edev.of_node);\n \t\t}\n \t\tairoha_metadata_dst_free(port);\ndiff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h\nindex f6d01a8e8da139..b49fc5304b3aaf 100644\n--- a/drivers/net/ethernet/airoha/airoha_eth.h\n+++ b/drivers/net/ethernet/airoha/airoha_eth.h\n@@ -561,6 +561,9 @@ struct airoha_gdm_dev {\n \tint nbq;\n \n \tstruct airoha_hw_stats stats;\n+\n+\tstruct phylink *phylink;\n+\tstruct phylink_config phylink_config;\n };\n \n struct airoha_gdm_port {\n@@ -568,8 +571,8 @@ struct airoha_gdm_port {\n \tint id;\n \tint users;\n \n-\t/* protect concurrent hw_stats accesses */\n-\tspinlock_t stats_lock;\n+\t/* protect concurrent hw_stats and frag register accesses */\n+\tspinlock_t lock;\n \n \tstruct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];\n };\ndiff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h\nindex 6fed63d013b412..8df02f51211c48 100644\n--- a/drivers/net/ethernet/airoha/airoha_regs.h\n+++ b/drivers/net/ethernet/airoha/airoha_regs.h\n@@ -357,6 +357,18 @@\n #define IP_FRAGMENT_PORT_MASK\t\tGENMASK(8, 5)\n #define IP_FRAGMENT_NBQ_MASK\t\tGENMASK(4, 0)\n \n+#define REG_FE_GDM4_TMBI_FRAG\t\t0x2028\n+#define GDM4_SGMII1_TX_WEIGHT_MASK\tGENMASK(31, 26)\n+#define GDM4_SGMII1_TX_FRAG_SIZE_MASK\tGENMASK(25, 16)\n+#define GDM4_SGMII0_TX_WEIGHT_MASK\tGENMASK(15, 10)\n+#define GDM4_SGMII0_TX_FRAG_SIZE_MASK\tGENMASK(9, 0)\n+\n+#define REG_FE_GDM4_RMBI_FRAG\t\t0x202c\n+#define GDM4_SGMII1_RX_WEIGHT_MASK\tGENMASK(31, 26)\n+#define GDM4_SGMII1_RX_FRAG_SIZE_MASK\tGENMASK(25, 16)\n+#define GDM4_SGMII0_RX_WEIGHT_MASK\tGENMASK(15, 10)\n+#define GDM4_SGMII0_RX_FRAG_SIZE_MASK\tGENMASK(9, 0)\n+\n #define REG_MC_VLAN_EN\t\t\t0x2100\n #define MC_VLAN_EN_MASK\t\t\tBIT(0)\n \ndiff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig\nindex e417fd66f660ad..10ac9af045940a 100644\n--- a/drivers/net/pcs/Kconfig\n+++ b/drivers/net/pcs/Kconfig\n@@ -5,6 +5,12 @@\n \n menu \"PCS device drivers\"\n \n+config FWNODE_PCS\n+\tbool \"PCS Firmware Node\"\n+\tdepends on (ACPI || OF)\n+\thelp\n+\t\tFirmware node PCS accessors\n+\n config PCS_XPCS\n \ttristate \"Synopsys DesignWare Ethernet XPCS\"\n \tselect PHYLINK\n@@ -35,4 +41,6 @@ config PCS_RZN1_MIIC\n \t Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to\n \t RMII/RGMII, or can be set in pass-through mode for MII.\n \n+source \"drivers/net/pcs/airoha/Kconfig\"\n+\n endmenu\ndiff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile\nindex 4f7920618b9005..91593aa8d92664 100644\n--- a/drivers/net/pcs/Makefile\n+++ b/drivers/net/pcs/Makefile\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0\n # Makefile for Linux PCS drivers\n \n+obj-$(CONFIG_FWNODE_PCS)\t+= pcs.o\n pcs_xpcs-$(CONFIG_PCS_XPCS)\t:= pcs-xpcs.o pcs-xpcs-plat.o \\\n \t\t\t\t pcs-xpcs-nxp.o pcs-xpcs-wx.o\n \n@@ -8,3 +9,5 @@ obj-$(CONFIG_PCS_XPCS)\t\t+= pcs_xpcs.o\n obj-$(CONFIG_PCS_LYNX)\t\t+= pcs-lynx.o\n obj-$(CONFIG_PCS_MTK_LYNXI)\t+= pcs-mtk-lynxi.o\n obj-$(CONFIG_PCS_RZN1_MIIC)\t+= pcs-rzn1-miic.o\n+\n+obj-$(CONFIG_PCS_AIROHA)\t+= airoha/\ndiff --git a/drivers/net/pcs/airoha/Kconfig b/drivers/net/pcs/airoha/Kconfig\nnew file mode 100644\nindex 00000000000000..4ddd527b365fd7\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/Kconfig\n@@ -0,0 +1,12 @@\n+# SPDX-License-Identifier: GPL-2.0-only\n+\n+config PCS_AIROHA\n+\ttristate\n+\tselect FWNODE_PCS\n+\n+config PCS_AIROHA_AN7581\n+\ttristate \"Airoha AN7581 PCS driver\"\n+\tselect PCS_AIROHA\n+\thelp\n+\t This module provides helper to phylink for managing the Airoha\n+\t AN7581 PCS for SoC Ethernet and PON SERDES.\ndiff --git a/drivers/net/pcs/airoha/Makefile b/drivers/net/pcs/airoha/Makefile\nnew file mode 100644\nindex 00000000000000..c5201d5cc3569e\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/Makefile\n@@ -0,0 +1,7 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+obj-$(CONFIG_PCS_AIROHA)\t:= pcs-airoha.o\n+pcs-airoha-objs\t\t\t:= pcs-airoha-common.o\n+ifdef CONFIG_PCS_AIROHA_AN7581\n+pcs-airoha-objs\t\t\t+= pcs-an7581.o\n+endif\ndiff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c\nnew file mode 100644\nindex 00000000000000..781f89adf3abfa\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c\n@@ -0,0 +1,1324 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+\n+#include \u003clinux/device.h\u003e\n+#include \u003clinux/mfd/syscon.h\u003e\n+#include \u003clinux/of.h\u003e\n+#include \u003clinux/of_platform.h\u003e\n+#include \u003clinux/pcs/pcs-provider.h\u003e\n+#include \u003clinux/phy/phy.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/platform_device.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+#include \u003clinux/reset.h\u003e\n+#include \u003clinux/rtnetlink.h\u003e\n+\n+#include \"pcs-airoha.h\"\n+\n+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,\n+\t\t\t\t phy_interface_t interface)\n+{\n+\tu32 xsi_sel;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\txsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\tdefault:\n+\t\txsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;\n+\t}\n+\n+\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_SSR3,\n+\t\t\t AIROHA_SCU_ETH_XSI_SEL,\n+\t\t\t xsi_sel);\n+}\n+\n+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,\n+\t\t\t\t phy_interface_t interface)\n+{\n+\tu32 xsi_sel, wan_sel;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_SGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_HSGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\tdefault:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_USXGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_USXGMII;\n+\t}\n+\n+\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_SSTR,\n+\t\t\t AIROHA_SCU_PON_XSI_SEL,\n+\t\t\t xsi_sel);\n+\n+\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_WAN_CONF,\n+\t\t\t AIROHA_SCU_WAN_SEL,\n+\t\t\t wan_sel);\n+}\n+\n+static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tu32 xsi_sel;\n+\n+\tif (index == 0) {\n+\t\tswitch (interface) {\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\t\txsi_sel = AIROHA_SCU_PCIE_XSI0_HSGMII;\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tdefault:\n+\t\t\txsi_sel = AIROHA_SCU_PCIE_XSI0_USXGMII;\n+\t\t}\n+\n+\t\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_SSTR,\n+\t\t\t\t AIROHA_SCU_PCIE_XSI0_SEL,\n+\t\t\t\t xsi_sel);\n+\t} else {\n+\t\tswitch (interface) {\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\t\txsi_sel = AIROHA_SCU_PCIE_XSI1_HSGMII;\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tdefault:\n+\t\t\txsi_sel = AIROHA_SCU_PCIE_XSI1_USXGMII;\n+\t\t}\n+\n+\t\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_SSTR,\n+\t\t\t\t AIROHA_SCU_PCIE_XSI1_SEL,\n+\t\t\t\t xsi_sel);\n+\t}\n+}\n+\n+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,\n+\t\t\t\tint index, phy_interface_t interface)\n+{\n+\tconst struct airoha_pcs_match_data *data = priv-\u003edata;\n+\tint ret;\n+\n+\tswitch (data-\u003eport_type) {\n+\tcase AIROHA_PCS_ETH:\n+\t\tairoha_pcs_setup_scu_eth(priv, interface);\n+\t\tbreak;\n+\tcase AIROHA_PCS_PON:\n+\t\tairoha_pcs_setup_scu_pon(priv, interface);\n+\t\tbreak;\n+\tcase AIROHA_PCS_PCIE:\n+\t\tairoha_pcs_setup_scu_pcie(priv, index, interface);\n+\t\tbreak;\n+\tcase AIROHA_PCS_USB:\n+\t\tbreak;\n+\t}\n+\n+\t/* TODO better handle reset from MAC */\n+\tret = reset_control_bulk_assert(ARRAY_SIZE(priv-\u003ersts),\n+\t\t\t\t\tpriv-\u003ersts);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = reset_control_bulk_deassert(ARRAY_SIZE(priv-\u003ersts),\n+\t\t\t\t\t priv-\u003ersts);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\tregmap_set_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\tAIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\t/* Disable Hibernation */\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,\n+\t\t\t AIROHA_PCS_USXGMII_SPEED_SEL_H);\n+\n+\t/* FIXME: wait Airoha */\n+\t/* Avoid PCS sending garbage to MAC in some HW revision (E0) */\n+\tregmap_write(maps-\u003eusxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);\n+}\n+\n+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\tregmap_clear_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\t AIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\tregmap_update_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\t AIROHA_PCS_TBI_10B_MODE,\n+\t\t\t priv-\u003ephy ? 0 : AIROHA_PCS_TBI_10B_MODE);\n+}\n+\n+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\tregmap_clear_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\t AIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\tAIROHA_PCS_TBI_10B_MODE);\n+\n+\tregmap_update_bits(maps-\u003ehsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,\n+\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));\n+\n+\tregmap_update_bits(maps-\u003ehsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,\n+\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));\n+}\n+\n+static void airoha_pcs_init(struct airoha_pcs_priv *priv,\n+\t\t\t int index, phy_interface_t interface)\n+{\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tairoha_pcs_init_sgmii(priv, index);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tairoha_pcs_init_hsgmii(priv, index);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tairoha_pcs_init_usxgmii(priv, index);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\t/* Disable every interrupt */\n+\tregmap_clear_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);\n+\n+\t/* Clear interrupt */\n+\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);\n+\n+\tregmap_clear_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);\n+}\n+\n+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\t/* Disable every Interrupt */\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);\n+\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);\n+\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,\n+\t\t\t AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);\n+\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,\n+\t\t\t AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);\n+\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,\n+\t\t\t AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);\n+\n+\t/* Clear any pending interrupt */\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,\n+\t\t\tAIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_E_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_T_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_D_INT);\n+\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,\n+\t\t\tAIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_LINK_UP_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_HI_BER_ST_INT);\n+\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,\n+\t\t\tAIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);\n+\n+\t/* Interrupt saddly seems to be not weel supported for Link Down.\n+\t * PCS Poll is a must to correctly read and react on Cable Deatch\n+\t * as only cable attach interrupt are fired and Link Down interrupt\n+\t * are fired only in special case like AN restart.\n+\t */\n+}\n+\n+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\treturn airoha_pcs_interrupt_init_sgmii(priv, index);\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\treturn airoha_pcs_interrupt_init_usxgmii(priv, index);\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,\n+\t\t\t\t unsigned int neg_mode, int index,\n+\t\t\t\t struct phylink_link_state *state)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 bmsr, lpa;\n+\n+\tregmap_read(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,\n+\t\t \u0026bmsr);\n+\tregmap_read(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,\n+\t\t \u0026lpa);\n+\n+\tbmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) \u0026 bmsr;\n+\tlpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY \u0026 lpa;\n+\n+\tphylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);\n+}\n+\n+static void airoha_pcs_get_state_hsgmii(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\tstruct phylink_link_state *state)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 bmsr;\n+\n+\tregmap_read(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,\n+\t\t \u0026bmsr);\n+\n+\tbmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) \u0026 bmsr;\n+\n+\tstate-\u003elink = !!(bmsr \u0026 BMSR_LSTATUS);\n+\tstate-\u003ean_complete = !!(bmsr \u0026 BMSR_ANEGCOMPLETE);\n+\tstate-\u003espeed = SPEED_2500;\n+\tstate-\u003eduplex = DUPLEX_FULL;\n+}\n+\n+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\t struct phylink_link_state *state)\n+{\n+\tconst struct airoha_pcs_match_data *data = priv-\u003edata;\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 an_done, lpa;\n+\n+\t/* Trigger HW workaround if needed. If an error is reported,\n+\t * consider link down and test again later.\n+\t */\n+\tif (data-\u003erxlock_workaround \u0026\u0026 data-\u003erxlock_workaround(priv, index)) {\n+\t\tstate-\u003elink = false;\n+\t\treturn;\n+\t}\n+\n+\t/* Toggle AN Status */\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,\n+\t\t\tAIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,\n+\t\t\t AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);\n+\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, \u0026lpa);\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_2, \u0026an_done);\n+\n+\tstate-\u003elink = !!(lpa \u0026 MDIO_USXGMII_LINK);\n+\tstate-\u003ean_complete = !!(an_done \u0026 AIROHA_PCS_USXGMII_PCS_AN_COMPLETE);\n+\n+\tphylink_decode_usxgmii_word(state, lpa);\n+}\n+\n+static void airoha_pcs_get_state_10gbaser(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\t struct phylink_link_state *state)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 status, curr_mode;\n+\n+\t/* Toggle AN Status */\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,\n+\t\t\tAIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,\n+\t\t\t AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);\n+\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1,\n+\t\t \u0026status);\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, \u0026curr_mode);\n+\n+\tstate-\u003elink = !!(status \u0026 AIROHA_PCS_USXGMII_RX_LINK_STUS);\n+\n+\tswitch (curr_mode \u0026 AIROHA_PCS_USXGMII_CUR_USXGMII_MODE) {\n+\tcase AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G:\n+\t\tstate-\u003espeed = SPEED_10000;\n+\t\tbreak;\n+\tcase AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G:\n+\t\tstate-\u003espeed = SPEED_5000;\n+\t\tbreak;\n+\tcase AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G:\n+\t\tstate-\u003espeed = SPEED_2500;\n+\t\tbreak;\n+\tdefault:\n+\t\tstate-\u003espeed = SPEED_UNKNOWN;\n+\t\treturn;\n+\t}\n+\n+\tstate-\u003eduplex = DUPLEX_FULL;\n+}\n+\n+static void airoha_pcs_get_state(struct phylink_pcs *pcs,\n+\t\t\t\t unsigned int neg_mode,\n+\t\t\t\t struct phylink_link_state *state)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\n+\tswitch (state-\u003einterface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tairoha_pcs_get_state_sgmii(priv, neg_mode, port-\u003eindex, state);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tairoha_pcs_get_state_hsgmii(priv, port-\u003eindex, state);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\tairoha_pcs_get_state_usxgmii(priv, port-\u003eindex, state);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tairoha_pcs_get_state_10gbaser(priv, port-\u003eindex, state);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,\n+\t\t\t phy_interface_t interface,\n+\t\t\t const unsigned long *advertising,\n+\t\t\t bool permit_pause_to_mac)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tconst struct airoha_pcs_match_data *data;\n+\tstruct airoha_pcs_maps *maps;\n+\tint index = port-\u003eindex;\n+\tu32 rate_adapt;\n+\tint ret;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\tport-\u003einterface = interface;\n+\tdata = priv-\u003edata;\n+\n+\t/* Apply Analog and Digital configuration for PCS */\n+\tif (data-\u003ebringup) {\n+\t\tret = data-\u003ebringup(priv, index, interface);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Set final configuration for various modes */\n+\tairoha_pcs_init(priv, index, interface);\n+\n+\t/* Configure Interrupt for various modes */\n+\tairoha_pcs_interrupt_init(priv, index, interface);\n+\n+\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |\n+\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;\n+\n+\tif (interface == PHY_INTERFACE_MODE_SGMII)\n+\t\trate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS;\n+\n+\t/* AN Auto Settings (Rate Adaptation) */\n+\tregmap_update_bits(maps-\u003ehsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);\n+\n+\tif (interface == PHY_INTERFACE_MODE_USXGMII ||\n+\t interface == PHY_INTERFACE_MODE_10GBASER) {\n+\t\tif (interface == PHY_INTERFACE_MODE_USXGMII) {\n+\t\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)\n+\t\t\t\tregmap_set_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\t\tAIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t\t\tAIROHA_PCS_USXGMII_AN_ENABLE);\n+\t\t\telse\n+\t\t\t\tregmap_clear_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\t\t AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t\t\t AIROHA_PCS_USXGMII_AN_ENABLE);\n+\n+\t\t\tregmap_clear_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);\n+\t\t} else {\n+\t\t\tregmap_clear_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_AN_ENABLE);\n+\n+\t\t\tregmap_set_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\tAIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,\n+\t\t\t\t\tAIROHA_PCS_USXGMII_RATE_UPDATE_MODE);\n+\t\t}\n+\t}\n+\n+\t/* Clear any force bit that my be set by bootloader */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t interface == PHY_INTERFACE_MODE_1000BASEX ||\n+\t interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_clear_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,\n+\t\t\t\t AIROHA_PCS_LINK_MODE_P0 |\n+\t\t\t\t AIROHA_PCS_FORCE_SPD_MODE_P0 |\n+\t\t\t\t AIROHA_PCS_FORCE_LINKDOWN_P0 |\n+\t\t\t\t AIROHA_PCS_FORCE_LINKUP_P0);\n+\t}\n+\n+\t/* Toggle Rate Adaption for SGMII/HSGMII mode */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t interface == PHY_INTERFACE_MODE_1000BASEX ||\n+\t interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)\n+\t\t\tregmap_clear_bits(maps-\u003ehsgmii_rate_adp,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);\n+\t\telse\n+\t\t\tregmap_set_bits(maps-\u003ehsgmii_rate_adp,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_P0_DIS_MII_MODE);\n+\t}\n+\n+\t/* Setup AN Link Timer */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t interface == PHY_INTERFACE_MODE_1000BASEX) {\n+\t\tu32 an_timer;\n+\n+\t\tan_timer = phylink_get_link_timer_ns(interface);\n+\n+\t\t/* Value needs to be shifted by 4, seems value is internally * 16 */\n+\t\tregmap_update_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,\n+\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,\n+\t\t\t\t\t an_timer \u003e\u003e 4));\n+\n+\t\tregmap_update_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,\n+\t\t\t\t AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,\n+\t\t\t\t\t an_timer \u003e\u003e 4));\n+\t}\n+\n+\t/* Setup SGMII AN and advertisement in DEV_ABILITY */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\t\tint advertise = phylink_mii_c22_pcs_encode_advertisement(interface,\n+\t\t\t\t\t\t\t\t\t\t advertising);\n+\t\t\tif (advertise \u003c 0)\n+\t\t\t\treturn advertise;\n+\n+\t\t\tregmap_update_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,\n+\t\t\t\t\t\t advertise));\n+\n+\t\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\t\t} else {\n+\t\t\tregmap_clear_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\t\t}\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_clear_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\n+\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_TX_ENABLE);\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t interface == PHY_INTERFACE_MODE_1000BASEX) {\n+\t\tu32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;\n+\n+\t\t/* Toggle SGMII or 1000base-x mode */\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII)\n+\t\t\tif_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN;\n+\n+\t\tif (neg_mode \u0026 PHYLINK_PCS_NEG_INBAND)\n+\t\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);\n+\t\telse\n+\t\t\tregmap_clear_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);\n+\n+\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\t\t/* Clear force speed bits and MAC mode */\n+\t\t\tregmap_clear_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_MAC_MODE |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);\n+\t\t} else {\n+\t\t\t/* Enable compatibility with MAC PCS Layer */\n+\t\t\tif_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;\n+\n+\t\t\t/* AN off force rate adaption, speed is set later in Link Up */\n+\t\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_PCS_MAC_MODE |\n+\t\t\t\t\tAIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);\n+\t\t}\n+\n+\t\tregmap_update_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);\n+\n+\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_TX_ENABLE |\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_MODE2_EN);\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_1000BASEX \u0026\u0026\n+\t neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\t\tAIROHA_PCS_SGMII_SEND_AN_ERR_EN);\n+\n+\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,\n+\t\t\t\tAIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY);\n+\t}\n+\n+\t/* Configure Flow Control on XFI */\n+\tregmap_update_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,\n+\t\t\t permit_pause_to_mac ?\n+\t\t\t\tAIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :\n+\t\t\t\t0);\n+\n+\treturn 0;\n+}\n+\n+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\n+\tswitch (port-\u003einterface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);\n+\t\tudelay(3);\n+\t\tregmap_clear_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\tAIROHA_PCS_USXGMII_AN_RESTART);\n+\t\tudelay(3);\n+\t\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t AIROHA_PCS_USXGMII_AN_RESTART);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,\n+\t\t\t phy_interface_t interface, int speed, int duplex)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tconst struct airoha_pcs_match_data *data;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\tdata = priv-\u003edata;\n+\n+\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\t\tregmap_update_bits(maps-\u003ehsgmii_rate_adp,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));\n+\t\t\tudelay(1);\n+\t\t\tregmap_update_bits(maps-\u003ehsgmii_rate_adp,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));\n+\t\t}\n+\t} else {\n+\t\tif (interface == PHY_INTERFACE_MODE_USXGMII ||\n+\t\t interface == PHY_INTERFACE_MODE_10GBASER) {\n+\t\t\tu32 mode;\n+\t\t\tu32 rate_adapt;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_10000:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_10000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_5000:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_5000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_2500:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_2500;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_1000:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_100;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\t/* Not supported */\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\t/* Force USXGMII to selected speed */\n+\t\t\tregmap_update_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_MODE, mode);\n+\n+\t\t\tif (interface == PHY_INTERFACE_MODE_10GBASER)\n+\t\t\t\tregmap_update_bits(maps-\u003ehsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |\n+\t\t\t\t\t\t rate_adapt);\n+\t\t}\n+\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t\t interface == PHY_INTERFACE_MODE_1000BASEX) {\n+\t\t\tu32 force_speed;\n+\t\t\tu32 rate_adapt;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_1000:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_10:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\t/* Not supported */\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tregmap_update_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,\n+\t\t\t\t\t force_speed | rate_adapt);\n+\t\t}\n+\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t\t interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\t\tu32 ck_gen_mode;\n+\t\t\tu32 speed_reg;\n+\t\t\tu32 if_mode;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_2500:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_1000:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_1G;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_100M;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_10:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_100M;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\t\t\tregmap_update_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,\n+\t\t\t\t\t\t if_mode);\n+\n+\t\t\t\tregmap_update_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,\n+\t\t\t\t\t\t ck_gen_mode |\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);\n+\t\t\t}\n+\n+\t\t\tregmap_update_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,\n+\t\t\t\t\t AIROHA_PCS_LINK_MODE_P0 |\n+\t\t\t\t\t AIROHA_PCS_FORCE_SPD_MODE_P0,\n+\t\t\t\t\t speed_reg |\n+\t\t\t\t\t AIROHA_PCS_FORCE_SPD_MODE_P0);\n+\t\t}\n+\t}\n+\n+\tif (data-\u003elink_up)\n+\t\tdata-\u003elink_up(priv, port-\u003eindex);\n+\n+\t/* BPI BMI enable */\n+\tregmap_clear_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\t AIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\t AIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\t AIROHA_PCS_XFI_TXMBI_STOP);\n+}\n+\n+static void airoha_pcs_link_down(struct phylink_pcs *pcs)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\n+\t/* MPI MBI disable */\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMBI_STOP);\n+}\n+\n+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,\n+\t\t\t\t phy_interface_t interface)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\n+\t/* Select HSGMII or USXGMII in SCU regs */\n+\tairoha_pcs_setup_scu(priv, port-\u003eindex, interface);\n+\n+\t/* MPI MBI disable */\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMBI_STOP);\n+\n+\t/* Write 1 to trigger reset and clear */\n+\tregmap_clear_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,\n+\t\t\t AIROHA_PCS_XFI_MAC_LOGIC_RST);\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,\n+\t\t\tAIROHA_PCS_XFI_MAC_LOGIC_RST);\n+\n+\tusleep_range(1000, 2000);\n+\n+\t/* Clear XFI MAC counter */\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,\n+\t\t\tAIROHA_PCS_XFI_GLB_CNT_CLR);\n+}\n+\n+static int airoha_pcs_post_config(struct phylink_pcs *pcs,\n+\t\t\t\t phy_interface_t interface)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\n+\t/* Frag disable */\n+\tregmap_update_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_RX_FRAG_LEN,\n+\t\t\t FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31));\n+\tregmap_update_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_TX_FRAG_LEN,\n+\t\t\t FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31));\n+\n+\t/* IPG NUM */\n+\tregmap_update_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_IPG_NUM,\n+\t\t\t FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10));\n+\n+\t/* Enable TX/RX flow control */\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_TX_FC_EN);\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_RX_FC_EN);\n+\n+\treturn 0;\n+}\n+\n+static unsigned int airoha_pcs_inband_caps(struct phylink_pcs *pcs,\n+\t\t\t\t\t phy_interface_t interface)\n+{\n+\treturn LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;\n+}\n+\n+static const struct phylink_pcs_ops airoha_pcs_ops = {\n+\t.pcs_inband_caps = airoha_pcs_inband_caps,\n+\t.pcs_pre_config = airoha_pcs_pre_config,\n+\t.pcs_post_config = airoha_pcs_post_config,\n+\t.pcs_get_state = airoha_pcs_get_state,\n+\t.pcs_config = airoha_pcs_config,\n+\t.pcs_an_restart = airoha_pcs_an_restart,\n+\t.pcs_link_up = airoha_pcs_link_up,\n+\t.pcs_link_down = airoha_pcs_link_down,\n+};\n+\n+static int airoha_pcs_init_named_regmap(struct platform_device *pdev,\n+\t\t\t\t\tconst char *name, struct regmap **regmap)\n+{\n+\tstruct regmap_config config = {\n+\t\t.reg_bits = 32,\n+\t\t.val_bits = 32,\n+\t\t.reg_stride = 4,\n+\t};\n+\tvoid *base;\n+\n+\tbase = devm_platform_ioremap_resource_byname(pdev, name);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tconfig.name = name;\n+\t*regmap = devm_regmap_init_mmio(\u0026pdev-\u003edev, base, \u0026config);\n+\n+\treturn PTR_ERR_OR_ZERO(*regmap);\n+}\n+\n+static int airoha_pcs_alloc_maps(struct platform_device *pdev,\n+\t\t\t\t struct airoha_pcs_priv *priv)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[0];\n+\tint ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_mac\", \u0026maps-\u003epcs_mac);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_an\", \u0026maps-\u003ehsgmii_an);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_pcs\", \u0026maps-\u003ehsgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_rate_adp\", \u0026maps-\u003ehsgmii_rate_adp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"multi_sgmii\", \u0026maps-\u003emulti_sgmii);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"usxgmii\", \u0026maps-\u003eusxgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_pma\", \u0026priv-\u003epcs_pma[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn airoha_pcs_init_named_regmap(pdev, \"pcs_ana\", \u0026priv-\u003epcs_ana);\n+}\n+\n+static int airoha_pcs_usb_alloc_maps(struct platform_device *pdev,\n+\t\t\t\t struct airoha_pcs_priv *priv)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[0];\n+\tint ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_mac\", \u0026maps-\u003epcs_mac);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_an\", \u0026maps-\u003ehsgmii_an);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_pcs\", \u0026maps-\u003ehsgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_rate_adp\", \u0026maps-\u003ehsgmii_rate_adp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"multi_sgmii\", \u0026maps-\u003emulti_sgmii);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn airoha_pcs_init_named_regmap(pdev, \"pcs_ana\", \u0026priv-\u003epcs_ana);\n+}\n+\n+static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev,\n+\t\t\t\t struct airoha_pcs_priv *priv)\n+{\n+\tstruct airoha_pcs_maps *maps = priv-\u003emaps;\n+\tint ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_mac0\", \u0026maps[0].pcs_mac);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_an0\", \u0026maps[0].hsgmii_an);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_pcs0\", \u0026maps[0].hsgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_rate_adp0\", \u0026maps[0].hsgmii_rate_adp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"multi_sgmii0\", \u0026maps[0].multi_sgmii);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"usxgmii0\", \u0026maps[0].usxgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_mac1\", \u0026maps[1].pcs_mac);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_an1\", \u0026maps[1].hsgmii_an);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_pcs1\", \u0026maps[1].hsgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_rate_adp1\", \u0026maps[1].hsgmii_rate_adp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"multi_sgmii1\", \u0026maps[1].multi_sgmii);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"usxgmii1\", \u0026maps[1].usxgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_pma0\", \u0026priv-\u003epcs_pma[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_pma1\", \u0026priv-\u003epcs_pma[1]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn airoha_pcs_init_named_regmap(pdev, \"pcs_ana\", \u0026priv-\u003epcs_ana);\n+}\n+\n+static struct phylink_pcs *airoha_pcs_get(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t void *data)\n+{\n+\tstruct airoha_pcs_priv *priv = data;\n+\tstruct device *dev = priv-\u003edev;\n+\tu64 index = 0;\n+\n+\tswitch (priv-\u003edata-\u003eport_type) {\n+\tcase AIROHA_PCS_ETH:\n+\tcase AIROHA_PCS_PON:\n+\tcase AIROHA_PCS_USB:\n+\t\tif (pcsspec-\u003enargs) {\n+\t\t\tdev_err(dev, \"invalid number of cells in 'pcs-handle' property\\n\");\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\n+\t\tbreak;\n+\tcase AIROHA_PCS_PCIE:\n+\t\tif (pcsspec-\u003enargs != 1) {\n+\t\t\tdev_err(dev, \"invalid number of cells in 'pcs-handle' property\\n\");\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\n+\t\tbreak;\n+\t}\n+\n+\tif (pcsspec-\u003enargs)\n+\t\tindex = pcsspec-\u003eargs[0];\n+\n+\tif (index \u003e= priv-\u003edata-\u003enum_port) {\n+\t\tdev_err(dev, \"invalid index cell in 'pcs-handle' property\\n\");\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\n+\treturn \u0026priv-\u003eports[index].pcs;\n+}\n+\n+static int airoha_pcs_probe(struct platform_device *pdev)\n+{\n+\tconst struct airoha_pcs_match_data *data;\n+\tstruct device *dev = \u0026pdev-\u003edev;\n+\tstruct airoha_pcs_priv *priv;\n+\tint index, ret;\n+\n+\tdata = of_device_get_match_data(dev);\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv-\u003eports = devm_kcalloc(dev, data-\u003enum_port,\n+\t\t\t\t sizeof(*priv-\u003eports), GFP_KERNEL);\n+\tif (!priv-\u003eports)\n+\t\treturn -ENOMEM;\n+\n+\tpriv-\u003edev = dev;\n+\tpriv-\u003edata = data;\n+\n+\tif (data-\u003eport_type == AIROHA_PCS_USB) {\n+\t\tstruct phy *phy;\n+\n+\t\tphy = devm_phy_get(dev, NULL);\n+\t\tif (IS_ERR(phy))\n+\t\t\treturn dev_err_probe(dev, PTR_ERR(phy), \"failed to get phy\\n\");\n+\n+\t\tpriv-\u003ephy = phy;\n+\t}\n+\n+\tswitch (data-\u003eport_type) {\n+\tcase AIROHA_PCS_ETH:\n+\tcase AIROHA_PCS_PON:\n+\t\tret = airoha_pcs_alloc_maps(pdev, priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tbreak;\n+\tcase AIROHA_PCS_PCIE:\n+\t\tret = airoha_pcs_pcie_alloc_maps(pdev, priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tbreak;\n+\tcase AIROHA_PCS_USB:\n+\t\tret = airoha_pcs_usb_alloc_maps(pdev, priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tbreak;\n+\t}\n+\n+\tif (data-\u003ealloc_regmap_fields) {\n+\t\tret = data-\u003ealloc_regmap_fields(priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* SCU is used to toggle XFI or HSGMII in global SoC registers */\n+\tif (!priv-\u003ephy) {\n+\t\tpriv-\u003escu = syscon_regmap_lookup_by_phandle(dev-\u003eof_node, \"airoha,scu\");\n+\t\tif (IS_ERR(priv-\u003escu))\n+\t\t\treturn PTR_ERR(priv-\u003escu);\n+\t}\n+\n+\tpriv-\u003ersts[0].id = \"mac\";\n+\tpriv-\u003ersts[1].id = \"phy\";\n+\tret = devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(priv-\u003ersts),\n+\t\t\t\t\t\t\t priv-\u003ersts);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"failed to get bulk reset lines\\n\");\n+\n+\t/* For Ethernet PCS, read the AN7581 SoC revision to check if\n+\t * manual rx calibration is needed. This is only limited to\n+\t * any SoC revision before E2.\n+\t */\n+\tif (device_is_compatible(dev, \"airoha,an7581-pcs-eth\")) {\n+\t\tu32 val;\n+\n+\t\tret = regmap_read(priv-\u003escu, AIROHA_SCU_PDIDR, \u0026val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tif (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) \u003c 0x2)\n+\t\t\tpriv-\u003emanual_rx_calib = true;\n+\t}\n+\n+\tfor (index = 0; index \u003c data-\u003enum_port; index++) {\n+\t\tstruct airoha_pcs_port *port = \u0026priv-\u003eports[index];\n+\n+\t\tport-\u003epriv = priv;\n+\t\tport-\u003eindex = index;\n+\t\tport-\u003epcs.poll = true;\n+\t\tport-\u003epcs.ops = \u0026airoha_pcs_ops;\n+\n+\t\tswitch (data-\u003eport_type) {\n+\t\tcase AIROHA_PCS_ETH:\n+\t\tcase AIROHA_PCS_PON:\n+\t\tcase AIROHA_PCS_PCIE:\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_10GBASER,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_USXGMII,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\tfallthrough;\n+\t\tcase AIROHA_PCS_USB:\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_SGMII,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_1000BASEX,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_2500BASEX,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\treturn fwnode_pcs_add_provider(dev_fwnode(dev), airoha_pcs_get, priv);\n+}\n+\n+static void airoha_pcs_remove(struct platform_device *pdev)\n+{\n+\tstruct airoha_pcs_priv *priv = platform_get_drvdata(pdev);\n+\tconst struct airoha_pcs_match_data *data = priv-\u003edata;\n+\tint i;\n+\n+\tfwnode_pcs_del_provider(dev_fwnode(\u0026pdev-\u003edev));\n+\n+\trtnl_lock();\n+\n+\tfor (i = 0; i \u003c data-\u003enum_port; i++) {\n+\t\tstruct airoha_pcs_port *port = \u0026priv-\u003eports[i];\n+\n+\t\tphylink_release_pcs(\u0026port-\u003epcs);\n+\t}\n+\n+\trtnl_unlock();\n+}\n+\n+static const struct airoha_pcs_match_data an7581_pcs_eth = {\n+\t.num_port = 1,\n+\t.port_type = AIROHA_PCS_ETH,\n+\t.alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,\n+\t.bringup = an7581_pcs_bringup,\n+\t.link_up = an7581_pcs_phya_link_up,\n+\t.rxlock_workaround = an7581_pcs_rxlock_workaround,\n+};\n+\n+static const struct airoha_pcs_match_data an7581_pcs_pon = {\n+\t.num_port = 1,\n+\t.port_type = AIROHA_PCS_PON,\n+\t.alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,\n+\t.bringup = an7581_pcs_bringup,\n+\t.link_up = an7581_pcs_phya_link_up,\n+};\n+\n+static const struct airoha_pcs_match_data an7581_pcs_pcie = {\n+\t.num_port = 2,\n+\t.port_type = AIROHA_PCS_PCIE,\n+\t.alloc_regmap_fields = an7581_pcs_pcie_alloc_regmap_fields,\n+\t.bringup = an7581_pcs_bringup,\n+\t.link_up = an7581_pcs_phya_link_up,\n+};\n+\n+static const struct airoha_pcs_match_data an7581_pcs_usb = {\n+\t.num_port = 1,\n+\t.port_type = AIROHA_PCS_USB,\n+\t.bringup = an7581_pcs_usb_bringup,\n+};\n+\n+static const struct of_device_id airoha_pcs_of_table[] = {\n+\t{ .compatible = \"airoha,an7581-pcs-eth\", .data = \u0026an7581_pcs_eth },\n+\t{ .compatible = \"airoha,an7581-pcs-pon\", .data = \u0026an7581_pcs_pon },\n+\t{ .compatible = \"airoha,an7581-pcs-pcie\", .data = \u0026an7581_pcs_pcie },\n+\t{ .compatible = \"airoha,an7581-pcs-usb\", .data = \u0026an7581_pcs_usb },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);\n+\n+static struct platform_driver airoha_pcs_driver = {\n+\t.driver = {\n+\t\t.name\t = \"airoha-pcs\",\n+\t\t.of_match_table = airoha_pcs_of_table,\n+\t},\n+\t.probe = airoha_pcs_probe,\n+\t.remove = airoha_pcs_remove,\n+};\n+module_platform_driver(airoha_pcs_driver);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"Airoha PCS driver\");\n+MODULE_AUTHOR(\"Christian Marangi \u003cansuelsmth@gmail.com\u003e\");\ndiff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h\nnew file mode 100644\nindex 00000000000000..8a76d51b5d2c8e\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/pcs-airoha.h\n@@ -0,0 +1,1311 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+\n+#include \u003clinux/bitfield.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/platform_device.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+#include \u003clinux/reset.h\u003e\n+\n+/* SCU*/\n+#define AIROHA_SCU_PDIDR\t\t\t0x5c\n+#define AIROHA_SCU_PRODUCT_ID\t\t\tGENMASK(15, 0)\n+#define AIROHA_SCU_WAN_CONF\t\t\t0x70\n+#define AIROHA_SCU_WAN_SEL\t\t\tGENMASK(7, 0)\n+#define AIROHA_SCU_WAN_SEL_SGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)\n+#define AIROHA_SCU_WAN_SEL_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)\n+#define AIROHA_SCU_WAN_SEL_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)\n+#define AIROHA_SCU_SSR3\t\t\t\t0x94\n+#define AIROHA_SCU_ETH_XSI_SEL\t\tGENMASK(14, 13)\n+#define AIROHA_SCU_ETH_XSI_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)\n+#define AIROHA_SCU_ETH_XSI_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)\n+#define AIROHA_SCU_SSTR\t\t\t\t0x9c\n+#define AIROHA_SCU_PCIE_XSI0_SEL\t\tGENMASK(14, 13)\n+#define AIROHA_SCU_PCIE_XSI0_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x1)\n+#define AIROHA_SCU_PCIE_XSI0_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x2)\n+#define AIROHA_SCU_PCIE_XSI1_SEL\t\tGENMASK(12, 11)\n+#define AIROHA_SCU_PCIE_XSI1_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x1)\n+#define AIROHA_SCU_PCIE_XSI1_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x2)\n+#define AIROHA_SCU_PON_XSI_SEL\t\tGENMASK(10, 9)\n+#define AIROHA_SCU_PON_XSI_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)\n+#define AIROHA_SCU_PON_XSI_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)\n+\n+/* XFI_MAC */\n+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG\t\t0x0\n+#define AIROHA_PCS_XFI_RX_FRAG_LEN\t\tGENMASK(26, 22)\n+#define AIROHA_PCS_XFI_TX_FRAG_LEN\t\tGENMASK(21, 17)\n+#define AIROHA_PCS_XFI_IPG_NUM\t\tGENMASK(15, 10)\n+#define AIROHA_PCS_XFI_TX_FC_EN\t\tBIT(5)\n+#define AIROHA_PCS_XFI_RX_FC_EN\t\tBIT(4)\n+#define AIROHA_PCS_XFI_RXMPI_STOP\t\tBIT(3)\n+#define AIROHA_PCS_XFI_RXMBI_STOP\t\tBIT(2)\n+#define AIROHA_PCS_XFI_TXMPI_STOP\t\tBIT(1)\n+#define AIROHA_PCS_XFI_TXMBI_STOP\t\tBIT(0)\n+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST\t0x10\n+#define AIROHA_PCS_XFI_MAC_LOGIC_RST\t\tBIT(0)\n+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH\t\t0x60\n+#define AIROHA_PCS_XFI_MAC_MACADDRH\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL\t\t0x64\n+#define AIROHA_PCS_XFI_MAC_MACADDRL\t\tGENMASK(31, 0)\n+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR\t\t0x100\n+#define AIROHA_PCS_XFI_GLB_CNT_CLR\t\tBIT(0)\n+\n+/* HSGMII_AN */\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0\t0x0\n+#define AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY\tBIT(15)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE\tBIT(12)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART\tBIT(9)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1\t0x4 /* BMSR */\n+#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4\t0x10\n+#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5\t0x14 /* LPA */\n+#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11\t0x2c\n+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER\tGENMASK(19, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13\t0x34\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)\n+#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)\n+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)\n+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)\n+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)\n+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)\n+#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN\tBIT(1)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60\n+#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE\tBIT(0)\n+\n+/* HSGMII_PCS */\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_1\t\t0x0\n+#define AIROHA_PCS_TBI_10B_MODE\t\tBIT(30)\n+#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN\tBIT(24)\n+#define AIROHA_PCS_REMOTE_FAULT_DIS\t\tBIT(12)\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_3\t\t0x8\n+#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME\tGENMASK(19, 0)\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_6\t\t0x14\n+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)\n+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)\n+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)\n+#define AIROHA_PCS_HSGMII_PCS_MAC_MODE\tBIT(8)\n+#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE\tBIT(4)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT\tBIT(1)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20\n+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)\n+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT\tBIT(4)\n+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)\n+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)\n+#define ARIOHA_PCS_HSGMII_PCS_STATE_2\t\t0x104\n+#define AIROHA_PCS_HSGMII_PCS_RX_SYNC\t\tBIT(5)\n+#define AIROHA_PCS_HSGMII_PCS_AN_DONE\t\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_INT_STATE\t\t0x15c\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS\tBIT(3)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC\tBIT(1)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE\tBIT(0)\n+\n+/* HSGMII_ANA */\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6\t0x18\n+#define AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC\tBIT(20)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8\t0x20\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR GENMASK(11, 8)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 GENMASK(7, 4)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0 GENMASK(3, 0)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11\t0x2c\n+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED\tGENMASK(3, 2)\n+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x0)\n+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x1)\n+#define AIROHA_PCS_HSGMII_ANA_TPHY_MODE\tGENMASK(1, 0)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18\t0x48\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV\tGENMASK(28, 27)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19\t0x4c\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV GENMASK(15, 8)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_LV GENMASK(7, 0)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG GENMASK(2, 0)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_GND FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x0)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONFBK_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x1)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x2)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONREF_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x3)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_CKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x4)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_FBCKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x5)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_TX2500M_A FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x6)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_CDR_250M_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x7)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24\t0x60\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE GENMASK(31, 24)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26\t0x68\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY GENMASK(7, 6)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x0)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x1)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x2)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x3)\n+\n+/* MULTI_SGMII */\n+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0\t0x14\n+#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18\n+#define AIROHA_PCS_LINK_MODE_P0\t\tGENMASK(5, 4)\n+#define AIROHA_PCS_LINK_MODE_P0_2_5G\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)\n+#define AIROHA_PCS_LINK_MODE_P0_1G\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)\n+#define AIROHA_PCS_LINK_MODE_P0_100M\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)\n+#define AIROHA_PCS_LINK_MODE_P0_10M\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)\n+#define AIROHA_PCS_FORCE_SPD_MODE_P0\t\tBIT(2)\n+#define AIROHA_PCS_FORCE_LINKDOWN_P0\t\tBIT(1)\n+#define AIROHA_PCS_FORCE_LINKUP_P0\t\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0\t0x100\n+#define AIROHA_PCS_HSGMII_XFI_SEL\t\tBIT(28)\n+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL\t0x14c\n+#define AIROHA_PCS_HSGMII_PCS_INT\t\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15\t0x43c\n+#define AIROHA_PCS_LINK_STS_P0\t\tBIT(3)\n+#define AIROHA_PCS_SPEED_STS_P0\t\tGENMASK(2, 0)\n+#define AIROHA_PCS_SPEED_STS_P0_1G\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)\n+#define AIROHA_PCS_SPEED_STS_P0_100M\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)\n+#define AIROHA_PCS_SPEED_STS_P0_10M\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18\t0x448\n+#define AIROHA_PCS_P0_SGMII_IS_10\t\tBIT(2)\n+#define AIROHA_PCS_P0_SGMII_IS_100\t\tBIT(1)\n+#define AIROHA_PCS_P0_SGMII_IS_1000\t\tBIT(0)\n+\n+/* HSGMII_RATE_ADP */\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0\t0x0\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN\tBIT(4)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1\t0x4\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6\t0x18\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8\t0x20\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11\t0x2c\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)\n+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0\t0x100\n+#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE\tBIT(31)\n+\n+/* USXGMII */\n+#define AIROHA_PCS_USXGMII_PCS_CTROL_1\t\t0x0\n+#define AIROHA_PCS_USXGMII_SPEED_SEL_H\tBIT(13)\n+#define AIROHA_PCS_USXGMII_PCS_STUS_1\t\t0x4\n+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS\tBIT(2)\n+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x1)\n+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_DOWN \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x0)\n+#define AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1 0x30\n+#define AIROHA_PCS_USXGMII_RX_LINK_STUS\tBIT(12)\n+#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)\n+#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)\n+#define AIROHA_PCS_USXGMII_PCS_BLK_LK\t\tBIT(0)\n+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116\t0x22c\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_0\t\t0x2c0\n+#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN\tBIT(24)\n+#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN\tBIT(16)\n+#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN\tBIT(8)\n+#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_1\t\t0x2c4\n+#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN\tBIT(24)\n+#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN\tBIT(16)\n+#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)\n+#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_2\t\t0x2c8\n+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)\n+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN\tBIT(16)\n+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN\tBIT(8)\n+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_3\t\t0x2cc\n+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)\n+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)\n+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN\tBIT(8)\n+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2\t0x2d8\n+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)\n+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT\tBIT(16)\n+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT\tBIT(8)\n+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3\t0x2dc\n+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)\n+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)\n+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT\tBIT(8)\n+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_4\t\t0x2e0\n+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4\t0x2e4\n+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0\t0x2f8\n+#define AIROHA_PCS_USXGMII_AN_RESTART\t\tBIT(8)\n+#define AIROHA_PCS_USXGMII_AN_ENABLE\t\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0\t0x310\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE\tGENMASK(30, 28)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)\n+#define AIROHA_PCS_USXGMII_PARTNER_ABILITY\tGENMASK(15, 0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2\t0x318\n+#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE\tBIT(24)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6\t0x31c\n+#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7\t0x320\n+#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE\tBIT(12)\n+#define AIROHA_PCS_USXGMII_MODE\t\tGENMASK(10, 8)\n+#define AIROHA_PCS_USXGMII_MODE_10000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)\n+#define AIROHA_PCS_USXGMII_MODE_5000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1)\n+#define AIROHA_PCS_USXGMII_MODE_2500\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)\n+#define AIROHA_PCS_USXGMII_MODE_1000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)\n+#define AIROHA_PCS_USXGMII_MODE_100\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)\n+\n+/* PMA_PHYA */\n+#define AIROHA_PCS_ANA_PXP_CMN_EN\t\t0x0\n+#define AIROHA_PCS_ANA_CMN_EN\t\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN\t0x4\n+#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST\tGENMASK(29, 24)\n+#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS\tGENMASK(21, 16)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR\t\t0x8\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BWR\t\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BP\t\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BC\t\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BR\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC\t0xc\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE\tGENMASK(23, 16)\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION\tBIT(8)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BWC\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC\t0x10\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_KS\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_KF\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14\n+#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5\tBIT(24)\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 0x0\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 0x1\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 0x2\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 0x3\n+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY\t0x1c\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB\t\tBIT(8)\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY\t\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 0x4\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 0x5\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 0x6\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM\t0x20\n+#define AIROHA_PCS_ANA_JCPLL_SDM_OUT\t\tBIT(24)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_SDM_MODE\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_IFM\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN\t0x24\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 0x4\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_HREN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN\t0x28\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8\t0x4\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16\t0x6\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV\t\t0x2c\n+#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_JCPLL_VCODIV\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_JCPLL_VCODIV_1\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_VCODIV_2\t0x1\n+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR\t0x30\n+#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI\tBIT(17)\n+#define AIROHA_PCS_ANA_JCPLL_SSC_EN\t\tBIT(16)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN\t0x34\n+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1\tGENMASK(23, 8)\n+#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA\t0x38\n+#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H\t0x48\n+#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_JCPLL_SPARE_L\t\tGENMASK(15, 8)\n+#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO\tBIT(5)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS\t0x50\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BC\t\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BR\t\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST\tGENMASK(13, 8)\n+#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS\tGENMASK(5, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP\t\t0x54\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION\tBIT(24)\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BWC\t\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BWR\t\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BP\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE\t0x58\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_KF\t\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS\t0x5c\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 0x0\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 0x1\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 0x2\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 0x3\n+#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_KS\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL\t0x64\n+#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB\t\tBIT(24)\n+#define AIROHA_PCS_ANA_TXPLL_RST_DLY\t\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4\t0x3\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN\t0x68\n+#define AIROHA_PCS_ANA_TXPLL_SDM_MODE\t\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_IFM\t\tBIT(16)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15\t0x3\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD\t0x6c\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_HREN\t\tBIT(16)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_OUT\t\tBIT(8)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM\t0x3\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN\t0x70\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 0x1\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4\t0x3\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6\t0x4\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN\t0x74\n+#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX\t\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_TXPLL_VCODIV\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_TXPLL_VCODIV_1\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_VCODIV_2\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4\t0x3\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8\t0x4\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16\t0x6\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN\t0x78\n+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)\n+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN\t\t0x7c\n+#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI\tBIT(8)\n+#define AIROHA_PCS_ANA_TXPLL_SSC_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1\t0x80\n+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD\t0x84\n+#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_TXPLL_LDO_OUT\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF\t0x94\n+#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN\t\t0xc4\n+#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_TX_CKLDO_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL\t0xcc\n+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE\tBIT(24)\n+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL\t\tBIT(16)\n+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR 0x0\n+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES 0x1\n+#define AIROHA_PCS_ANA_PXP_RX_REV_0\t\t0xd4\n+#define AIROHA_PCS_ANA_RX_REV_1\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)\n+#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)\n+#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK\tGENMASK(19, 18)\n+#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB\tBIT(16)\n+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV\t\t0xd8\n+#define AIROHA_PCS_ANA_RX_TDC_CK_SEL\t\tBIT(24)\n+#define AIROHA_PCS_ANA_RX_PHYCK_RSTB\t\tBIT(16)\n+#define AIROHA_PCS_ANA_RX_PHYCK_SEL\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_RX_PHYCK_DIV\t\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc\n+#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS\tBIT(8)\n+#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO\t0xe8\n+#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM\tGENMASK(26, 8)\n+#define AIROHA_PCS_ANA_CDR_LPF_RATIO\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE\t0xf4\n+#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC\t0xf8\n+#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL\tGENMASK(19, 16)\n+#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS\tGENMASK(11, 8)\n+#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC\tGENMASK(6, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc\n+#define AIROHA_PCS_ANA_CDR_PR_FBKSEL\t\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN\t0x10c\n+#define AIROHA_PCS_ANA_RX_DAC_MON\t\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_CDR_PR_CAP_EN\t\tBIT(19)\n+#define AIROHA_PCS_ANA_CDR_BUF_IN_SR\t\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN\tBIT(2)\n+#define AIROHA_PCS_ANA_CDR_PR_MONPI_EN\tBIT(1)\n+#define AIROHA_PCS_ANA_CDR_PR_MONPR_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE\t\t0x110\n+#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH\t0x114\n+#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_RX_SIGDET_PEAK\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN\t0x118\n+#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB\t0x11c\n+#define AIROHA_PCS_ANA_RX_FE_VCM_GEN_PWDB\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW\t0x120\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE\t\tGENMASK(17, 8)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS BIT(0)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS BIT(1)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS BIT(2)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS BIT(3)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS BIT(4)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS BIT(5)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS BIT(6)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS BIT(7)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH\tBIT(8)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS BIT(9)\n+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE\t\t0x13c\n+#define AIROHA_PCS_ANA_AEQ_OFORCE\t\tGENMASK(19, 8)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS\tBIT(0)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1\tBIT(1)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2\tBIT(2)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3\tBIT(3)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4\tBIT(4)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5\tBIT(5)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6\tBIT(6)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7\tBIT(7)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA\tBIT(8)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE\tBIT(9)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT\tBIT(10)\n+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144\n+#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ\t0x148\n+#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ\tBIT(24)\n+#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ\tBIT(16)\n+#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ\tBIT(8)\n+#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ\tBIT(0)\n+\n+/* PMA_PHYA 2L */\n+#define AIROHA_PCS_ANA_PXP_2L_CMN_EN\t\t0x0\n+#define AIROHA_PCS_ANA_2L_CMN_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN\t0x4\n+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IOFST\tGENMASK(29, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IBIAS\tGENMASK(21, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_SHCK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR\t0x8\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWR\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BP\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BC\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BR\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC\t0xc\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_CODE\tGENMASK(23, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_OPTION\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWC\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC\t0x10\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KS\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KF\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KFC\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE 0x14\n+#define AIROHA_PCS_ANA_2L_JCPLL_POSTDIV_D5\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_2 0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_3 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_4 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_1 0x3\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY\t0x1c\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_23 0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_21 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_19 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_15 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_PLL_RSTB\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_20_25 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_40_50 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_80_100 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_150_200 0x4\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_300_400 0x5\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_600_800 0x6\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM\t0x20\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_OUT\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_INT\t0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_1SDM 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_2SDM 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_3SDM 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_MODE\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_IFM\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN\t0x24\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_VREF\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_2 0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_4 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_6 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_8 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_10 0x4\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_HREN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN\t0x28\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_0_5 0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_1 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_2 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_4 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_8 0x4\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_16 0x6\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV\t0x2c\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_SCAPWR\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_HALFLSB_EN BIT(16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_CFIX\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_1\t0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_2\t0x1\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR\t0x30\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(18, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_TCLVAR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN\t0x38\n+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_TRI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1\t0x3c\n+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA1\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD\t0x40\n+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_PERIOD\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN\t0x4c\n+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L\tGENMASK(31, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L_LDO\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF 0x50\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_KBAND_VREF GENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN\t0x54\n+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IBIAS\tGENMASK(29, 24)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST\t0x58\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BP\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BC\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BR\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IOFST\tGENMASK(5, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR\t0x5c\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_CODE\tGENMASK(31, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_OPTION\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWC\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWR\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV\t0x60\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KS\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KF\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KFC\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_DIV\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN\t0x64\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE GENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_2 0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_3 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_4 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_1 0x3\n+#define AIROHA_PCS_ANA_2L_TXPLL_POSTDIV_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN\t0x68\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_INTERNAL BIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV\t0x6c\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_PLL_RSTB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_RST_DLY\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_1\t0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_2\t0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_3\t0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_4\t0x3\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS\t0x70\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_INT\t0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_1SDM 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_2SDM 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_3SDM 0x3\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_MODE\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_IFM\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_23 0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_21 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_19 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_15 0x3\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT\t0x74\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2 0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2_5 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_3 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_4 0x3\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_6 0x4\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_HREN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_OUT\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF 0x78\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_VREF\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW\t0x7c\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_HALFLSB_EN BIT(24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_CFIX\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_1\t0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_2\t0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_0_5 0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_1 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_2 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_4 0x3\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_8 0x4\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_16 0x6\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR\t0x80\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(18, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_TCLVAR\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_SCAPWR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN\t0x84\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_TRI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PHASE_INI\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1\t0x88\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA1\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD\t0x8c\n+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_VCO_OUT\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_OUT\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PERIOD\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF 0x9c\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN\t0xcc\n+#define AIROHA_PCS_ANA_2L_TX0_DMEDGEGEN_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_TX0_CKLDO_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN\t0xe8\n+#define AIROHA_PCS_ANA_2L_TX1_DMEDGEGEN_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_TX1_CKLDO_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL\t0xf4\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FORCE BIT(24)\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_REV_0\t\t0xfc\n+#define AIROHA_PCS_ANA_2L_RX0_REV_1\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)\n+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)\n+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_REV_0\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)\n+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)\n+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV\tGENMASK(3, 2)\n+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4\tBIT(1)\n+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV\t0x100\n+#define AIROHA_PCS_ANA_2L_RX0_TDC_CK_SEL\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_RSTB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_SEL\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_DIV\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV 0x104\n+#define AIROHA_PCS_ANA_2L_CDR0_PD_EDGE_DIS\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PD_PICAL_CKD8_INV BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO\t0x110\n+#define AIROHA_PCS_ANA_2L_CDR0_LPF_TOP_LIM\tGENMASK(26, 8)\n+#define AIROHA_PCS_ANA_2L_CDR0_LPF_RATIO\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE\t0x11c\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_INJ_FORCE_OFF BIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC\t0x120\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_SEL\tGENMASK(19, 16)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_VCOADC_OS\tGENMASK(11, 8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_DAC\tGENMASK(6, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL 0x124\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_FBKSEL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_DAC_BAND\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_CKBUF_VAL GENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_IBAND_VAL GENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN 0x130\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPR_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN\t0x134\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_XFICK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR\t0x138\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_CAP_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_BUF_IN_SR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON\t0x13c\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_MON\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN 0x140\n+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_PEAK\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_LPF_CTRL\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL 0x144\n+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ1_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_RX0_FE_EQ_HZEN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_VTH_SEL\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN\t0x148\n+#define AIROHA_PCS_ANA_2L_RX0_FE_VCM_GEN_PWDB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ3_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ2_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE\t0x150\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE\tGENMASK(17, 8)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2VOS BIT(0)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2IOS BIT(1)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1VOS BIT(2)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1IOS BIT(3)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2VOS BIT(4)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2IOS BIT(5)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1VOS BIT(6)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1IOS BIT(7)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_LVSH BIT(8)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_COMPOS BIT(9)\n+#define AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE\t0x170\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE\t\tGENMASK(19, 8)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_SAOS\tBIT(0)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP1 BIT(1)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP2 BIT(2)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP3 BIT(3)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP4 BIT(4)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP5 BIT(5)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP6 BIT(6)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP7 BIT(7)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_VGA\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_CTLE\tBIT(9)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_ATT\tBIT(10)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ 0x17c\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_E1_BYPASS_AEQ BIT(24)\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_E0_BYPASS_AEQ BIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_D1_BYPASS_AEQ BIT(8)\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_D0_BYPASS_AEQ BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ 0x180\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_EYE_BYPASS_AEQ BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB 0x234\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_D0_BYPASS_AEQ BIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL\t0x1ac\n+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL_FORCE BIT(24)\n+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_REV_0\t\t0x1b4\n+#define AIROHA_PCS_ANA_2L_RX1_REV_1\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)\n+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)\n+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX1_REV_0\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)\n+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)\n+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV\tGENMASK(3, 2)\n+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4\tBIT(1)\n+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV\t0x1b8\n+#define AIROHA_PCS_ANA_2L_RX1_TDC_CK_SEL\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_RSTB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_SEL\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_DIV\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV 0x1bc\n+#define AIROHA_PCS_ANA_2L_CDR1_PD_EDGE_DIS\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PD_PICAL_CKD8_INV BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO\t0x1c8\n+#define AIROHA_PCS_ANA_2L_CDR1_LPF_TOP_LIM\tGENMASK(26, 8)\n+#define AIROHA_PCS_ANA_2L_CDR1_LPF_RATIO\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE\t0x1d4\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_INJ_FORCE_OFF BIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC\t0x1d8\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_SEL\tGENMASK(19, 16)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_VCOADC_OS\tGENMASK(11, 8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_DAC\tGENMASK(6, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL 0x1dc\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_FBKSEL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_DAC_BAND\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_CKBUF_VAL GENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_IBAND_VAL GENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN 0x1e8\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPR_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN\t0x1ec\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_XFICK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR\t0x1f0\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_MON\t\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_CAP_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_BUF_IN_SR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE\t0x1f4\n+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_LPF_CTRL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH\t0x1f8\n+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_VTH_SEL\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_PEAK\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL\t0x1fc\n+#define AIROHA_PCS_ANA_2L_RX1_FE_EQ_HZEN\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN\t0x200\n+#define AIROHA_PCS_ANA_2L_RX1_FE_VCM_GEN_PWDB\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ3_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ2_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ1_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW 0x208\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE\tGENMASK(25, 16)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2VOS BIT(0)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2IOS BIT(1)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1VOS BIT(2)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1IOS BIT(3)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2VOS BIT(4)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2IOS BIT(5)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1VOS BIT(6)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1IOS BIT(7)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_LVSH BIT(8)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_COMPOS BIT(9)\n+#define AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE\t0x228\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE\t\tGENMASK(27, 16)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_SAOS\tBIT(0)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP1 BIT(1)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP2 BIT(2)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP3 BIT(3)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP4 BIT(4)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP5 BIT(5)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP6 BIT(6)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP7 BIT(7)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_VGA\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_CTLE\tBIT(9)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_ATT\tBIT(10)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ 0x238\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_EYE_BYPASS_AEQ BIT(24)\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_E1_BYPASS_AEQ BIT(16)\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_E0_BYPASS_AEQ BIT(8)\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_D1_BYPASS_AEQ BIT(0)\n+\n+/* PMA_PHYD */\n+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0\t0x0\n+#define AIROHA_PCS_PMA_SW_LCPLL_EN\t\tBIT(24)\n+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1\t0x4\n+#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2\t0x88\n+#define AIROHA_PCS_PMA_DATA_SHIFT\t\tBIT(8)\n+#define AIROHA_PCS_PMA_EYECNT_FAST\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0\t0x8c\n+#define AIROHA_PCS_PMA_RX_OS_START\t\tGENMASK(23, 8)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT\t\tGENMASK(2, 0)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1\t0x90\n+#define AIROHA_PCS_PMA_RX_PICAL_END\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_PICAL_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2\t0x94\n+#define AIROHA_PCS_PMA_RX_PDOS_END\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_PDOS_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3\t0x98\n+#define AIROHA_PCS_PMA_RX_FEOS_END\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_FEOS_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4\t0x9c\n+#define AIROHA_PCS_PMA_RX_SDCAL_END\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_SDCAL_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5\t0x100\n+#define AIROHA_PCS_PMA_RX_RDY\t\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6\t0x104\n+#define AIROHA_PCS_PMA_RX_OS_END\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c\n+#define AIROHA_PCS_PMA_DISB_RX_RDY\t\tBIT(24)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114\n+#define AIROHA_PCS_PMA_FORCE_RX_RDY\t\tBIT(24)\n+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2\t\t0x120\n+#define AIROHA_PCS_PMA_EQ_DEBUG_SEL\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_PMA_FOM_NUM_ORDER\t\tGENMASK(12, 8)\n+#define AIROHA_PCS_PMA_A_SEL\t\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1\t\t0x14c\n+#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_LOCK_CYCLECNT\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2\t\t0x150\n+#define AIROHA_PCS_PMA_LOCK_TARGET_END\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_LOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3\t\t0x154\n+#define AIROHA_PCS_PMA_UNLOCK_TARGET_END\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4\t\t0x158\n+#define AIROHA_PCS_PMA_LOCK_UNLOCKTH\t\tGENMASK(15, 12)\n+#define AIROHA_PCS_PMA_LOCK_LOCKTH\t\tGENMASK(11, 8)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN\tGENMASK(2, 0)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT\tFIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL\tFIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)\n+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1\t\t0x16c\n+#define AIROHA_PCS_PMA_SIGDET_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FLL_1\t\t\t0x174\n+#define AIROHA_PCS_PMA_LPATH_IDAC\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_RX_FLL_2\t\t\t0x178\n+#define AIROHA_PCS_PMA_CK_RATE\t\tGENMASK(18, 16)\n+#define AIROHA_PCS_PMA_CK_RATE_20\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)\n+#define AIROHA_PCS_PMA_CK_RATE_10\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)\n+#define AIROHA_PCS_PMA_CK_RATE_5\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)\n+#define AIROHA_PCS_PMA_RX_FLL_5\t\t\t0x184\n+#define AIROHA_PCS_PMA_FLL_IDAC_MIN\t\tGENMASK(26, 16)\n+#define AIROHA_PCS_PMA_FLL_IDAC_MAX\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_RX_FLL_B\t\t\t0x19c\n+#define AIROHA_PCS_PMA_LOAD_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_RESET_1\t\t0x208\n+#define AIROHA_PCS_PMA_SIGDET_RST_B\t\tBIT(8)\n+#define AIROHA_PCS_PMA_TX_RST_B\t\t\t0x260\n+#define AIROHA_PCS_PMA_TXCALIB_RST_B\t\tBIT(8)\n+#define AIROHA_PCS_PMA_TX_TOP_RST_B\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_4\t\t0x320\n+#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET\tBIT(24)\n+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9\t\t0x330\n+#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_8\t\t0x33c\n+#define AIROHA_PCS_PMA_DISB_FBCK_LOCK\t\tBIT(0)\n+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0\t0x34c\n+#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB\tBIT(24)\n+#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB\tBIT(16)\n+#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB\tBIT(8)\n+#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB\tBIT(0)\n+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1\t0x350\n+#define AIROHA_PCS_PMA_RX_SIDGET_PWDB\t\tBIT(0)\n+#define AIROHA_PCS_PMA_DIG_RESERVE_0\t\t0x360\n+#define AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN\tGENMASK(17, 16)\n+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1\t0x374\n+#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2\t\t0x380\n+#define AIROHA_PCS_RX_SIGDET\t\t\tBIT(8)\n+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0\t\t0x38c\n+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0\t0x390\n+#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1\t0x394\n+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3\t0x39c\n+#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH\tGENMASK(11, 8)\n+#define AIROHA_PCS_PMA_ADD_XPON_MODE_1\t\t0x414\n+#define AIROHA_PCS_PMA_XFI_RX_MODE\t\tGENMASK(11, 9)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_10G3\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x0)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_5G15\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x1)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_6G25\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x2)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_2G57\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x3)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_3G12\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x4)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_1G25\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x5)\n+#define AIROHA_PCS_PMA_R2T_MODE\t\tBIT(8)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE\t\tGENMASK(5, 3)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_10G3\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x0)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_5G15\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x1)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_6G25\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x2)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_2G57\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x3)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_3G12\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x4)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_1G25\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x5)\n+#define AIROHA_PCS_PMA_SW_RST_SET\t\t0x460\n+#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N\tBIT(11)\n+#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N\tBIT(10)\n+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)\n+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N\tBIT(8)\n+#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N\tBIT(7)\n+#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N\tBIT(6)\n+#define AIROHA_PCS_PMA_SW_REF_RST_N\t\tBIT(5)\n+#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N\tBIT(4)\n+#define AIROHA_PCS_PMA_SW_PMA_RST_N\t\tBIT(3)\n+#define AIROHA_PCS_PMA_SW_TX_RST_N\t\tBIT(2)\n+#define AIROHA_PCS_PMA_SW_RX_RST_N\t\tBIT(1)\n+#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N\tBIT(0)\n+#define AIROHA_PCS_PMA_XPON_INT_EN_3\t\t0x474\n+#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_XPON_INT_STA_3\t\t0x47c\n+#define AIROHA_PCS_PMA_RX_SIGDET_INT\t\tBIT(16)\n+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL\t\t0x48c\n+#define AIROHA_PCS_PMA_DISB_LEQ\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FREQDET\t\t0x530\n+#define AIROHA_PCS_PMA_FL_OUT\t\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_FBCK_LOCK\t\tBIT(0)\n+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL\t0x580\n+#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN\t0x768\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)\n+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED\t\t0x76c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL\tBIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL\tGENMASK(17, 16)\n+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B\t\t0x778\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1\tGENMASK(20, 16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL\t\t0x77c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL\tGENMASK(2, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1\t\t0x780\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2\tGENMASK(20, 16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL\t\t0x784\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC\t\t0x794\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)\n+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW\t0x798\n+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW\tGENMASK(30, 0)\n+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS\t\t0x79c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS\tBIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW\t0x800\n+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW\tGENMASK(30, 0)\n+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS\t\t0x80c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON\tBIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB\t\t0x814\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA\t0x818\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB\t\t0x81c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN\t0x820\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB\t0x824\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN\t0x828\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN\tBIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B\t0x84c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B\t BIT(0)\n+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN\t0x854\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN\tBIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN\t\t0x874\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL\t\t0x88c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB\t\t0x894\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB\t BIT(0)\n+#define AIROHA_PCS_PMA_DIG_RESERVE_29\t\t0x910\n+#define AIROHA_PCS_PMA_2L_TX_RATE_CTRL\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_2L_RX_RATE_CTRL\tGENMASK(5, 4)\n+\n+#define AIROHA_PCS_MAX_CALIBRATION_TRY\t\t50\n+#define AIROHA_PCS_MAX_RX_SIGDET_TRY\t\t6\n+#define AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT\t4\n+#define AIROHA_PCS_MAX_NUM_RSTS\t\t\t2\n+\n+enum xfi_port_type {\n+\tAIROHA_PCS_ETH,\n+\tAIROHA_PCS_PON,\n+\tAIROHA_PCS_USB,\n+\tAIROHA_PCS_PCIE,\n+};\n+\n+struct airoha_pcs_maps {\n+\tstruct regmap *pcs_mac;\n+\tstruct regmap *hsgmii_an;\n+\tstruct regmap *hsgmii_pcs;\n+\tstruct regmap *hsgmii_rate_adp;\n+\tstruct regmap *multi_sgmii;\n+\tstruct regmap *usxgmii_pcs;\n+};\n+\n+struct airoha_pcs_priv {\n+\tstruct device *dev;\n+\tconst struct airoha_pcs_match_data *data;\n+\n+\tstruct airoha_pcs_port *ports;\n+\n+\tstruct regmap *scu;\n+\n+\tstruct airoha_pcs_maps maps[2];\n+\n+\tstruct regmap *pcs_pma[2];\n+\tstruct regmap *pcs_ana;\n+\tstruct regmap_field **pcs_ana_fields[2];\n+\n+\tstruct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];\n+\n+\tstruct phy *phy;\n+\n+\tbool manual_rx_calib;\n+};\n+\n+struct airoha_pcs_port {\n+\tstruct airoha_pcs_priv *priv;\n+\tphy_interface_t interface;\n+\tint index;\n+\n+\tstruct phylink_pcs pcs;\n+};\n+\n+struct airoha_pcs_match_data {\n+\tint num_port;\n+\tenum xfi_port_type port_type;\n+\n+\tint (*alloc_regmap_fields)(struct airoha_pcs_priv *priv);\n+\tint (*bringup)(struct airoha_pcs_priv *priv,\n+\t\t int index, phy_interface_t interface);\n+\tvoid (*link_up)(struct airoha_pcs_priv *priv, int index);\n+\tint (*rxlock_workaround)(struct airoha_pcs_priv *priv, int index);\n+};\n+\n+#define to_airoha_pcs_port(n) container_of(n, struct airoha_pcs_port, pcs)\n+\n+#if IS_ENABLED(CONFIG_PCS_AIROHA_AN7581)\n+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv);\n+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv);\n+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,\n+\t\t int index, phy_interface_t interface);\n+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t int index, phy_interface_t interface);\n+\n+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index);\n+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index);\n+#else\n+static inline int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index, phy_interface_t interface)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index)\n+{\n+}\n+\n+static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index)\n+{\n+\treturn 0;\n+}\n+#endif\ndiff --git a/drivers/net/pcs/airoha/pcs-an7581.c b/drivers/net/pcs/airoha/pcs-an7581.c\nnew file mode 100644\nindex 00000000000000..24fc15b6e29e14\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/pcs-an7581.c\n@@ -0,0 +1,2093 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+#include \u003clinux/math.h\u003e\n+#include \u003clinux/phy/phy.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+\n+#include \"pcs-airoha.h\"\n+\n+#include \u003clinux/of.h\u003e\n+\n+enum {\n+\tAN7581_PCS_CMN_EN,\n+\n+\tAN7581_PCS_JCPLL_SPARE_L,\n+\tAN7581_PCS_JCPLL_RST_DLY,\n+\tAN7581_PCS_JCPLL_PLL_RSTB,\n+\tAN7581_PCS_JCPLL_SDM_DI_EN,\n+\tAN7581_PCS_JCPLL_SDM_DI_LS,\n+\n+\tAN7581_PCS_JCPLL_SDM_OUT,\n+\tAN7581_PCS_JCPLL_SDM_ORD,\n+\tAN7581_PCS_JCPLL_SDM_MODE,\n+\tAN7581_PCS_JCPLL_SDM_IFM,\n+\tAN7581_PCS_JCPLL_SDM_HREN,\n+\n+\tAN7581_PCS_JCPLL_CHP_IOFST,\n+\tAN7581_PCS_JCPLL_CHP_IBIAS,\n+\tAN7581_PCS_JCPLL_LPF_SHCK_EN,\n+\n+\tAN7581_PCS_JCPLL_LPF_BWR,\n+\tAN7581_PCS_JCPLL_LPF_BP,\n+\tAN7581_PCS_JCPLL_LPF_BC,\n+\tAN7581_PCS_JCPLL_LPF_BR,\n+\tAN7581_PCS_JCPLL_LPF_BWC,\n+\n+\tAN7581_PCS_JCPLL_VCO_SCAPWR,\n+\tAN7581_PCS_JCPLL_VCO_HALFLSB_EN,\n+\tAN7581_PCS_JCPLL_VCO_CFIX,\n+\tAN7581_PCS_JCPLL_VCODIV,\n+\tAN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L,\n+\tAN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H,\n+\tAN7581_PCS_JCPLL_VCO_TCLVAR,\n+\n+\tAN7581_PCS_JCPLL_POSTDIV_D5,\n+\tAN7581_PCS_JCPLL_MMD_PREDIV_MODE,\n+\n+\tAN7581_PCS_JCPLL_KBAND_KS,\n+\tAN7581_PCS_JCPLL_KBAND_KF,\n+\tAN7581_PCS_JCPLL_KBAND_KFC,\n+\tAN7581_PCS_JCPLL_KBAND_DIV,\n+\tAN7581_PCS_JCPLL_KBAND_CODE,\n+\tAN7581_PCS_JCPLL_KBAND_OPTION,\n+\n+\tAN7581_PCS_JCPLL_TCL_AMP_VREF,\n+\tAN7581_PCS_JCPLL_TCL_AMP_GAIN,\n+\tAN7581_PCS_JCPLL_TCL_AMP_EN,\n+\n+\tAN7581_PCS_JCPLL_TCL_LPF_BW,\n+\tAN7581_PCS_JCPLL_TCL_LPF_EN,\n+\n+\tAN7581_PCS_JCPLL_SSC_DELTA,\n+\tAN7581_PCS_JCPLL_SSC_DELTA1,\n+\tAN7581_PCS_JCPLL_SSC_PERIOD,\n+\tAN7581_PCS_JCPLL_SSC_TRI_EN,\n+\tAN7581_PCS_JCPLL_SSC_EN,\n+\tAN7581_PCS_JCPLL_SSC_PHASE_INI,\n+\tAN7581_PCS_JCPLL_TCL_KBAND_VREF,\n+\n+\tAN7581_PCS_TXPLL_LDO_VCO_OUT,\n+\tAN7581_PCS_TXPLL_LDO_OUT,\n+\tAN7581_PCS_TXPLL_PLL_RSTB,\n+\tAN7581_PCS_TXPLL_RST_DLY,\n+\tAN7581_PCS_TXPLL_REFIN_DIV,\n+\tAN7581_PCS_TXPLL_REFIN_INTERNAL,\n+\tAN7581_PCS_TXPLL_SDM_MODE,\n+\tAN7581_PCS_TXPLL_SDM_IFM,\n+\tAN7581_PCS_TXPLL_SDM_DI_LS,\n+\tAN7581_PCS_TXPLL_SDM_DI_EN,\n+\tAN7581_PCS_TXPLL_SDM_HREN,\n+\tAN7581_PCS_TXPLL_SDM_ORD,\n+\tAN7581_PCS_TXPLL_SDM_OUT,\n+\tAN7581_PCS_TXPLL_SSC_DELTA1,\n+\tAN7581_PCS_TXPLL_SSC_DELTA,\n+\tAN7581_PCS_TXPLL_SSC_TRI_EN,\n+\tAN7581_PCS_TXPLL_SSC_PHASE_INI,\n+\tAN7581_PCS_TXPLL_SSC_EN,\n+\tAN7581_PCS_TXPLL_SSC_PERIOD,\n+\tAN7581_PCS_TXPLL_LPF_BC,\n+\tAN7581_PCS_TXPLL_LPF_BR,\n+\tAN7581_PCS_TXPLL_LPF_BP,\n+\tAN7581_PCS_TXPLL_LPF_BWC,\n+\tAN7581_PCS_TXPLL_LPF_BWR,\n+\tAN7581_PCS_TXPLL_CHP_IOFST,\n+\tAN7581_PCS_TXPLL_CHP_IBIAS,\n+\tAN7581_PCS_TXPLL_VCO_CFIX,\n+\tAN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L,\n+\tAN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H,\n+\tAN7581_PCS_TXPLL_VCO_TCLVAR,\n+\tAN7581_PCS_TXPLL_VCO_SCAPWR,\n+\tAN7581_PCS_TXPLL_VCO_HALFLSB_EN,\n+\tAN7581_PCS_TXPLL_KBAND_CODE,\n+\tAN7581_PCS_TXPLL_KBAND_OPTION,\n+\tAN7581_PCS_TXPLL_KBAND_KS,\n+\tAN7581_PCS_TXPLL_KBAND_KF,\n+\tAN7581_PCS_TXPLL_KBAND_KFC,\n+\tAN7581_PCS_TXPLL_KBAND_DIV,\n+\tAN7581_PCS_TXPLL_MMD_PREDIV_MODE,\n+\tAN7581_PCS_TXPLL_POSTDIV_EN,\n+\tAN7581_PCS_TXPLL_VCODIV,\n+\tAN7581_PCS_TXPLL_TCL_KBAND_VREF,\n+\tAN7581_PCS_TXPLL_TCL_AMP_GAIN,\n+\tAN7581_PCS_TXPLL_TCL_AMP_VREF,\n+\tAN7581_PCS_TXPLL_TCL_LPF_BW,\n+\tAN7581_PCS_TXPLL_TCL_LPF_EN,\n+\tAN7581_PCS_TXPLL_TCL_AMP_EN,\n+\n+\tAN7581_PCS_TX_DMEDGEGEN_EN,\n+\tAN7581_PCS_TX_CKLDO_EN,\n+\n+\tAN7581_PCS_RX_DAC_EYE_BYPASS_AEQ,\n+\tAN7581_PCS_RX_DAC_E1_BYPASS_AEQ,\n+\tAN7581_PCS_RX_DAC_E0_BYPASS_AEQ,\n+\tAN7581_PCS_RX_DAC_D1_BYPASS_AEQ,\n+\tAN7581_PCS_RX_DAC_D0_BYPASS_AEQ,\n+\tAN7581_PCS_RX_FE_VCM_GEN_PWDB,\n+\tAN7581_PCS_RX_OSCAL_FORCE,\n+\tAN7581_PCS_RX_DAC_MON,\n+\tAN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL,\n+\tAN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL,\n+\tAN7581_PCS_RX_REV_1_SIGDET_ILEAK,\n+\tAN7581_PCS_RX_FE_VB_EQ3_EN,\n+\tAN7581_PCS_RX_FE_VB_EQ2_EN,\n+\tAN7581_PCS_RX_FE_VB_EQ1_EN,\n+\tAN7581_PCS_RX_FE_EQ_HZEN,\n+\tAN7581_PCS_RX_SIGDET_VTH_SEL,\n+\tAN7581_PCS_RX_SIGDET_PEAK,\n+\tAN7581_PCS_RX_SIGDET_LPF_CTRL,\n+\tAN7581_PCS_RX_TDC_CK_SEL,\n+\tAN7581_PCS_RX_PHYCK_RSTB,\n+\tAN7581_PCS_RX_PHYCK_SEL,\n+\tAN7581_PCS_RX_PHYCK_DIV,\n+\tAN7581_PCS_RX_PHY_CK_SEL_FORCE,\n+\tAN7581_PCS_RX_PHY_CK_SEL,\n+\n+\tAN7581_PCS_AEQ_OFORCE,\n+\n+\tAN7581_PCS_CDR_PD_EDGE_DIS,\n+\tAN7581_PCS_CDR_PD_PICAL_CKD8_INV,\n+\n+\tAN7581_PCS_CDR_PR_XFICK_EN,\n+\tAN7581_PCS_CDR_PR_MONPI_EN,\n+\tAN7581_PCS_CDR_PR_MONPR_EN,\n+\tAN7581_PCS_CDR_PR_KBAND_DIV,\n+\tAN7581_PCS_CDR_PR_BETA_SEL,\n+\tAN7581_PCS_CDR_PR_VCOADC_OS,\n+\tAN7581_PCS_CDR_PR_BETA_DAC,\n+\tAN7581_PCS_CDR_PR_FBKSEL,\n+\tAN7581_PCS_CDR_PR_DAC_BAND,\n+\tAN7581_PCS_CDR_PR_VREG_CKBUF_VAL,\n+\tAN7581_PCS_CDR_PR_VREG_IBAND_VAL,\n+\tAN7581_PCS_CDR_PR_CAP_EN,\n+\tAN7581_PCS_CDR_PR_INJ_FORCE_OFF,\n+\n+\tAN7581_PCS_CDR_BUF_IN_SR,\n+\n+\tAN7581_PCS_CDR_LPF_TOP_LIM,\n+\tAN7581_PCS_CDR_LPF_RATIO,\n+\n+\tAN7581_PCS_FIELDS_MAX,\n+};\n+\n+static const struct reg_field an7581_pcs_fields[AN7581_PCS_FIELDS_MAX] = {\n+\t[AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CMN_EN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 8, 15),\n+\n+\t[AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 0, 2),\n+\t[AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 8, 8),\n+\t[AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 16, 16),\n+\t[AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 24, 25),\n+\n+\t[AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 24, 24),\n+\t[AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 16, 17),\n+\t[AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 8, 9),\n+\t[AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 0, 0),\n+\t[AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 16, 31),\n+\t[AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 8, 23),\n+\t[AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 0, 0),\n+\t[AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 17, 17),\n+\t[AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 16, 16),\n+\t[AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 16, 20),\n+\n+\t[AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 24, 29),\n+\t[AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 16, 21),\n+\t[AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 24, 28),\n+\t[AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 16, 20),\n+\t[AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 8, 12),\n+\t[AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 0, 4),\n+\t[AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 24, 26),\n+\t[AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 16, 16),\n+\t[AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 8, 9),\n+\t[AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 0, 1),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 8, 10),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 3, 5),\n+\t[AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 0, 2),\n+\n+\t[AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 24, 24),\n+\t[AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 0, 1),\n+\n+\t[AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 16, 17),\n+\t[AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 8, 9),\n+\t[AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 0, 1),\n+\t[AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 24, 26),\n+\t[AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 16, 23),\n+\t[AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 24, 28),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 16, 18),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 24, 26),\n+\t[AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 16, 16),\n+\n+\t[AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 24, 25),\n+\t[AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 16, 17),\n+\t[AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 24, 24),\n+\t[AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 16, 18),\n+\t[AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 8, 9),\n+\t[AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 0, 0),\n+\t[AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 24, 25),\n+\t[AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 16, 16),\n+\t[AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 8, 9),\n+\t[AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 16, 16),\n+\t[AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 0, 1),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 24, 28),\n+\t[AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 16, 20),\n+\t[AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 8, 13),\n+\t[AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 0, 5),\n+\t[AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 16, 20),\n+\t[AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 8, 12),\n+\t[AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 0, 4),\n+\t[AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 24, 25),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 27, 29),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 24, 26),\n+\t[AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 16, 18),\n+\t[AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 8, 10),\n+\t[AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 0, 7),\n+\t[AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 24, 24),\n+\t[AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 0, 1),\n+\t[AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 24, 25),\n+\t[AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 16, 17),\n+\t[AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 8, 10),\n+\t[AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 16, 17),\n+\t[AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 8, 8),\n+\t[AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 16, 17),\n+\t[AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 0, 2),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 8, 12),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 8, 10),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 24, 24),\n+\n+\t[AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 24, 24),\n+\t[AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 24, 24),\n+\t[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 16, 16),\n+\t[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 8, 8),\n+\t[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 0, 0),\n+\t[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB, 24, 24),\n+\t[AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB, 0, 0),\n+\n+\t[AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_AEQ_CFORCE, 8, 19),\n+\t[AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW, 8, 17),\n+\n+\t[AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 8, 8),\n+\t[AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 24, 28),\n+\t[AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 2, 2),\n+\t[AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 1, 1),\n+\t[AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 0, 0),\n+\n+\t[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 24, 26),\n+\t[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 20, 22),\n+\t[AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 18, 19),\n+\n+\t[AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 8, 26),\n+\t[AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 0, 1),\n+\n+\t[AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 24, 26),\n+\t[AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 16, 19),\n+\t[AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 8, 11),\n+\t[AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 0, 6),\n+\t[AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 24, 25),\n+\t[AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 16, 20),\n+\t[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 8, 10),\n+\t[AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 0, 2),\n+\n+\t[AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 24, 24),\n+\t[AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 16, 16),\n+\t[AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 8, 8),\n+\t[AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 0, 0),\n+\n+\t[AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 19, 19),\n+\t[AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 16, 18),\n+\n+\t[AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 16, 20),\n+\t[AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 8, 9),\n+\t[AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_RANGE, 24, 25),\n+\n+\t[AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 24, 24),\n+\t[AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 16, 16),\n+\t[AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 8, 9),\n+\t[AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 0, 7),\n+\t[AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 24, 24),\n+\t[AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 16, 16),\n+\n+\t[AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, 24, 24),\n+};\n+\n+static const struct reg_field an7581_pcs_pcie0_fields[AN7581_PCS_FIELDS_MAX] = {\n+\t[AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),\n+\n+\t[AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),\n+\t[AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),\n+\t[AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),\n+\t[AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),\n+\n+\t[AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),\n+\t[AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),\n+\t[AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),\n+\t[AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),\n+\t[AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),\n+\t[AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),\n+\t[AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),\n+\t[AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),\n+\t[AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),\n+\t[AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),\n+\t[AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),\n+\t[AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),\n+\t[AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),\n+\t[AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),\n+\t[AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),\n+\n+\t[AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),\n+\t[AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),\n+\n+\t[AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),\n+\t[AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),\n+\t[AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),\n+\t[AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),\n+\t[AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),\n+\t[AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),\n+\t[AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),\n+\n+\t[AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),\n+\t[AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),\n+\t[AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),\n+\t[AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),\n+\t[AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),\n+\t[AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),\n+\t[AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),\n+\t[AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),\n+\t[AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),\n+\t[AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),\n+\t[AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),\n+\t[AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),\n+\t[AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),\n+\t[AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),\n+\t[AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),\n+\t[AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),\n+\t[AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),\n+\t[AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),\n+\t[AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),\n+\t[AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),\n+\t[AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),\n+\t[AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),\n+\t[AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),\n+\t[AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),\n+\t[AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),\n+\t[AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),\n+\t[AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),\n+\t[AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),\n+\t[AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),\n+\t[AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),\n+\n+\t[AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 24, 24),\n+\t[AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ, 0, 0),\n+\t[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 24, 24),\n+\t[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 16, 16),\n+\t[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 8, 8),\n+\t[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 0, 0),\n+\t[AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 16, 16),\n+\n+\t[AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE, 8, 19),\n+\t[AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE, 8, 17),\n+\n+\t[AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 8, 8),\n+\t[AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON, 0, 4),\n+\t[AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 8, 8),\n+\t[AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 0, 0),\n+\t[AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN, 24, 24),\n+\n+\t[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 24, 26),\n+\t[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 20, 22),\n+\t[AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 18, 19),\n+\n+\t[AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 8, 26),\n+\t[AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 0, 1),\n+\n+\t[AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 24, 26),\n+\t[AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 16, 19),\n+\t[AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 8, 11),\n+\t[AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 0, 6),\n+\t[AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 24, 25),\n+\t[AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 16, 20),\n+\t[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 8, 10),\n+\t[AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 0, 2),\n+\n+\t[AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 8, 8),\n+\t[AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 0, 0),\n+\t[AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 24, 24),\n+\t[AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 16, 16),\n+\n+\t[AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 8, 8),\n+\t[AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 0, 2),\n+\n+\t[AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 0, 4),\n+\t[AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 24, 25),\n+\t[AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 8, 9),\n+\n+\t[AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 24, 24),\n+\t[AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 16, 16),\n+\t[AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 8, 9),\n+\t[AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 0, 7),\n+\t[AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 24, 24),\n+\t[AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 16, 16),\n+\n+\t[AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE, 24, 24),\n+};\n+\n+static const struct reg_field an7581_pcs_pcie1_fields[AN7581_PCS_FIELDS_MAX] = {\n+\t[AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),\n+\n+\t[AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),\n+\t[AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),\n+\t[AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),\n+\t[AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),\n+\n+\t[AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),\n+\t[AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),\n+\t[AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),\n+\t[AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),\n+\t[AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),\n+\t[AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),\n+\t[AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),\n+\t[AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),\n+\t[AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),\n+\t[AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),\n+\t[AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),\n+\t[AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),\n+\t[AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),\n+\t[AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),\n+\t[AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),\n+\n+\t[AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),\n+\t[AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),\n+\n+\t[AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),\n+\t[AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),\n+\t[AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),\n+\t[AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),\n+\t[AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),\n+\t[AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),\n+\t[AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),\n+\n+\t[AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),\n+\t[AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),\n+\t[AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),\n+\t[AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),\n+\t[AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),\n+\t[AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),\n+\t[AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),\n+\t[AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),\n+\t[AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),\n+\t[AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),\n+\t[AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),\n+\t[AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),\n+\t[AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),\n+\t[AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),\n+\t[AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),\n+\t[AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),\n+\t[AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),\n+\t[AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),\n+\t[AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),\n+\t[AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),\n+\t[AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),\n+\t[AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),\n+\t[AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),\n+\t[AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),\n+\t[AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),\n+\t[AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),\n+\t[AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),\n+\t[AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),\n+\t[AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),\n+\t[AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),\n+\n+\t[AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 24, 24),\n+\t[AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 24, 24),\n+\t[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 16, 16),\n+\t[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 8, 8),\n+\t[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 0, 0),\n+\t[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB, 24, 24),\n+\t[AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 24, 24),\n+\n+\t[AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE, 16, 27),\n+\t[AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW, 16, 25),\n+\n+\t[AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 8, 8),\n+\t[AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 16, 20),\n+\t[AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 8, 8),\n+\t[AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 0, 0),\n+\t[AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN, 24, 24),\n+\n+\t[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 24, 26),\n+\t[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 20, 22),\n+\t[AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 18, 19),\n+\n+\t[AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 8, 26),\n+\t[AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 0, 1),\n+\n+\t[AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 24, 26),\n+\t[AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 16, 19),\n+\t[AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 8, 11),\n+\t[AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 0, 6),\n+\t[AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 24, 25),\n+\t[AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 16, 20),\n+\t[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 8, 10),\n+\t[AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 0, 2),\n+\n+\t[AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 16, 16),\n+\t[AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 8, 8),\n+\t[AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 0, 0),\n+\t[AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL, 24, 24),\n+\n+\t[AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 8, 8),\n+\t[AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 0, 2),\n+\n+\t[AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 16, 20),\n+\t[AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 8, 9),\n+\t[AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE, 24, 25),\n+\n+\t[AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 24, 24),\n+\t[AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 16, 16),\n+\t[AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 8, 9),\n+\t[AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 0, 7),\n+\t[AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 24, 24),\n+\t[AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 16, 16),\n+\n+\t[AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE, 24, 24),\n+};\n+\n+static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tstruct regmap *pcs_pma;\n+\tu32 kband_vref;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tkband_vref = 0x10;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tkband_vref = 0xf;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* This comment only apply to Serdes PCIe that expose\n+\t * 2 PCS.\n+\t *\n+\t * The Serdes PCIe expose 2 PCS but always require\n+\t * the PMA for the first PCS to be configured\n+\t * for correct functionality for JCPLL.\n+\t */\n+\tpcs_pma = priv-\u003epcs_pma[0];\n+\n+\t/* Setup LDO */\n+\tusleep_range(200, 300);\n+\n+\tregmap_field_set_bits(pcs_ana_fields[AN7581_PCS_JCPLL_SPARE_L],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);\n+\n+\t/* Setup RSTB */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_RST_DLY],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_PLL_RSTB], 0x1);\n+\n+\t/* Enable PLL force selection and Force Disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);\n+\n+\t/* Setup SDM */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_LS],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_EN], 0x0);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_OUT], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_ORD],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_MODE], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_IFM], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_HREN], 0x0);\n+\n+\t/* Setup SSC */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA1], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PERIOD], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_TRI_EN], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_EN], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PHASE_INI], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0);\n+\n+\t/* Setup LPF */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IOFST], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IBIAS], 0x18);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_SHCK_EN], 0);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWR], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BP], 0x10);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BC], 0x1f);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BR], BIT(3) | BIT(1));\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWC], 0x0);\n+\n+\t/* Setup VCO */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_SCAPWR], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_HALFLSB_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_CFIX], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H], 0x3);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x3);\n+\n+\t/* Setup PCW */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);\n+\n+\t/* Setup DIV */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_POSTDIV_D5], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_MMD_PREDIV_MODE],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCODIV],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_VCODIV_1);\n+\n+\t/* Setup KBand */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KS], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KF], 0x3);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KFC], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_DIV], 0x2);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_CODE], 0xe4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_OPTION], 0x0);\n+\n+\t/* Setup TCL */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_KBAND_VREF],\n+\t\t\t kband_vref);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_VREF], 0x5);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_GAIN],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_EN], 0x1);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_BW],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_EN], 0x1);\n+\n+\t/* Enable PLL */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);\n+\n+\t/* Enale PLL Output */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);\n+}\n+\n+static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tu32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;\n+\tstruct regmap *pcs_pma;\n+\tu32 tcl_amp_vref;\n+\tbool sdm_hren;\n+\tu32 vco_cfix;\n+\tbool vcodiv;\n+\tu32 pcw;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tlpf_chp_ibias = 0xf;\n+\t\tlpf_bp = BIT(1);\n+\t\tlpf_bwr = BIT(3) | BIT(1) | BIT(0);\n+\t\tlpf_bwc = BIT(4) | BIT(3);\n+\t\tvco_cfix = BIT(1) | BIT(0);\n+\t\tpcw = BIT(27);\n+\t\ttcl_amp_vref = BIT(3) | BIT(1) | BIT(0);\n+\t\tvcodiv = false;\n+\t\tsdm_hren = false;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tlpf_chp_ibias = 0xa;\n+\t\tlpf_bp = BIT(2) | BIT(0);\n+\t\tlpf_bwr = 0;\n+\t\tlpf_bwc = 0;\n+\t\tvco_cfix = 0;\n+\t\tpcw = BIT(27) | BIT(25);\n+\t\ttcl_amp_vref = BIT(3) | BIT(2) | BIT(0);\n+\t\tvcodiv = true;\n+\t\tsdm_hren = false;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tlpf_chp_ibias = 0xf;\n+\t\tlpf_bp = BIT(1);\n+\t\tlpf_bwr = BIT(3) | BIT(1) | BIT(0);\n+\t\tlpf_bwc = BIT(4) | BIT(3);\n+\t\tvco_cfix = BIT(0);\n+\t\tpcw = BIT(27) | BIT(22);\n+\t\ttcl_amp_vref = BIT(3) | BIT(1) | BIT(0);\n+\t\tvcodiv = false;\n+\t\tsdm_hren = true;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* This comment only apply to Serdes PCIe that expose\n+\t * 2 PCS.\n+\t *\n+\t * The Serdes PCIe expose 2 PCS but always require\n+\t * the PMA for the first PCS to be configured\n+\t * for correct functionality for TXPLL.\n+\t */\n+\tpcs_pma = priv-\u003epcs_pma[0];\n+\n+\t/* Setup VCO LDO Output */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_VCO_OUT], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_OUT], 0x1);\n+\n+\t/* Setup RSTB */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_PLL_RSTB], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_RST_DLY], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_DIV],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_INTERNAL], 0x1);\n+\n+\t/* Enable PLL force selection and Force Disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);\n+\n+\t/* Setup SDM */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_MODE], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_IFM], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_LS],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_HREN], sdm_hren);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_OUT], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_ORD],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);\n+\n+\t/* Setup SSC */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA1], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_TRI_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PHASE_INI], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PERIOD], 0x0);\n+\n+\t/* Setup LPF */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IBIAS],\n+\t\t\t lpf_chp_ibias);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IOFST], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BC], 0x1f);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BR], 0x5);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWC], lpf_bwc);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWR], lpf_bwr);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BP], lpf_bp);\n+\n+\t/* Setup VCO */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_CFIX], vco_cfix);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_TCLVAR], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_SCAPWR], 0x7);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_HALFLSB_EN], 0x1);\n+\n+\t/* Setup PCW */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);\n+\n+\t/* Setup KBand */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_CODE], 0xe4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_OPTION], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KS], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KF], 0x3);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KFC], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_DIV], 0x4);\n+\n+\t/* Setup DIV */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_POSTDIV_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_MMD_PREDIV_MODE],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCODIV],\n+\t\t\t vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :\n+\t\t\t\t AIROHA_PCS_ANA_TXPLL_VCODIV_1);\n+\n+\t/* Setup TCL */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_KBAND_VREF], 0xf);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_VREF],\n+\t\t\t tcl_amp_vref);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_GAIN],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_BW],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_EN], 0x1);\n+\n+\t/* Enable PLL */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);\n+\n+\t/* Enale PLL Output */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);\n+}\n+\n+static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tu32 fir_cn1, fir_c0b, fir_c1;\n+\tu32 tx_rate_ctrl;\n+\tu32 ckin_divisor;\n+\tu32 xfi_tx_mode;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tckin_divisor = BIT(1);\n+\t\ttx_rate_ctrl = BIT(0);\n+\t\tfir_cn1 = 0;\n+\t\tfir_c0b = 12;\n+\t\tfir_c1 = 0;\n+\t\txfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_1G25;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tckin_divisor = BIT(2);\n+\t\ttx_rate_ctrl = BIT(0);\n+\t\tfir_cn1 = 0;\n+\t\tfir_c0b = 11;\n+\t\tfir_c1 = 1;\n+\t\txfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_3G12;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tckin_divisor = BIT(2) | BIT(0);\n+\t\ttx_rate_ctrl = BIT(1);\n+\t\tfir_cn1 = 1;\n+\t\tfir_c0b = 1;\n+\t\tfir_c1 = 11;\n+\t\txfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_10G3;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* Set TX rate ctrl */\n+\tif (priv-\u003edata-\u003eport_type == AIROHA_PCS_PCIE) {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,\n+\t\t\t\t AIROHA_PCS_PMA_2L_TX_RATE_CTRL,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_2L_TX_RATE_CTRL,\n+\t\t\t\t\t tx_rate_ctrl));\n+\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,\n+\t\t\t\t AIROHA_PCS_PMA_XFI_TX_MODE,\n+\t\t\t\t xfi_tx_mode);\n+\t} else {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,\n+\t\t\t\t AIROHA_PCS_PMA_PON_TX_RATE_CTRL,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,\n+\t\t\t\t\t tx_rate_ctrl));\n+\t}\n+\n+\t/* Setup TX Config */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TX_DMEDGEGEN_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TX_CKLDO_EN], 0x1);\n+\n+\tudelay(1);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);\n+\n+\t/* FIXME: Ask Airoha TX term is OK to reset? */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,\n+\t\t\t\t ckin_divisor));\n+\n+\tif (priv-\u003edata-\u003eport_type != AIROHA_PCS_PCIE) {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,\n+\t\t\t\t\t tx_rate_ctrl));\n+\t}\n+\n+\t/* Setup TX FIR Load Parameters (Reference 660mV) */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));\n+\n+\t/* Reset TX Bar */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B,\n+\t\t\tAIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);\n+}\n+\n+static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tu32 phyck_div, phyck_sel;\n+\tu32 pr_cdr_beta_dac;\n+\tu32 cdr_pr_buf_in_sr;\n+\tbool cdr_pr_cap_en;\n+\tu32 sigdet_vth_sel;\n+\tu32 rx_rate_ctrl;\n+\tu32 xfi_rx_mode;\n+\tu32 osr;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tosr = BIT(1) | BIT(0); /* 1.25G */\n+\t\tpr_cdr_beta_dac = BIT(3);\n+\t\trx_rate_ctrl = 0;\n+\t\tcdr_pr_cap_en = false;\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);\n+\t\tsigdet_vth_sel = BIT(2) | BIT(1);\n+\t\tphyck_div = BIT(5) | BIT(3) | BIT(0);\n+\t\tphyck_sel = BIT(0);\n+\t\txfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_1G25;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tosr = BIT(0); /* 2.5G */\n+\t\tpr_cdr_beta_dac = BIT(2) | BIT(1);\n+\t\trx_rate_ctrl = 0;\n+\t\tcdr_pr_cap_en = true;\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1);\n+\t\tsigdet_vth_sel = BIT(2) | BIT(1);\n+\t\tphyck_div = BIT(3) | BIT(1) | BIT(0);\n+\t\tphyck_sel = BIT(0);\n+\t\txfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_3G12;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tosr = 0; /* 10G */\n+\t\tcdr_pr_cap_en = false;\n+\t\tpr_cdr_beta_dac = BIT(3);\n+\t\trx_rate_ctrl = BIT(1);\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);\n+\t\tsigdet_vth_sel = BIT(1);\n+\t\tphyck_div = BIT(6) | BIT(1);\n+\t\tphyck_sel = BIT(1);\n+\t\txfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_10G3;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* Set RX rate ctrl */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_2,\n+\t\t\t\t AIROHA_PCS_PMA_CK_RATE,\n+\t\t\t\t AIROHA_PCS_PMA_CK_RATE_10);\n+\n+\tif (priv-\u003edata-\u003eport_type == AIROHA_PCS_PCIE) {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,\n+\t\t\t\t AIROHA_PCS_PMA_2L_RX_RATE_CTRL,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_2L_RX_RATE_CTRL,\n+\t\t\t\t\t rx_rate_ctrl));\n+\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,\n+\t\t\t\t AIROHA_PCS_PMA_XFI_RX_MODE,\n+\t\t\t\t xfi_rx_mode);\n+\t} else {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,\n+\t\t\t\t AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,\n+\t\t\t\t\t rx_rate_ctrl));\n+\t}\n+\n+\t/* Setup RX Path */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_5,\n+\t\t\t AIROHA_PCS_PMA_FLL_IDAC_MIN |\n+\t\t\t AIROHA_PCS_PMA_FLL_IDAC_MAX,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VCM_GEN_PWDB], 0x1);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,\n+\t\t\tAIROHA_PCS_PMA_LCPLL_MAN_PWDB);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_AEQ_OFORCE],\n+\t\t\t AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_OSCAL_FORCE],\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,\n+\t\t\t AIROHA_PCS_PMA_DISB_BLWC_OFFSET);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,\n+\t\t\t AIROHA_PCS_PMA_DISB_LEQ);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_PICAL_CKD8_INV], 0x0);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_MON], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_XFICK_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPI_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPR_EN], 0x0);\n+\n+\t/* Setup FE Gain and FE Peacking */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0));\n+\n+\t/* Setup FE VOS */\n+\tif (interface != PHY_INTERFACE_MODE_USXGMII \u0026\u0026\n+\t interface != PHY_INTERFACE_MODE_10GBASER)\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_DA_FE_VOS,\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));\n+\n+\t/* Setup FLL PR FMeter (no bypass mode)*/\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,\n+\t\t\t AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,\n+\t\t\t AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |\n+\t\t\t AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,\n+\t\t\t AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));\n+\n+\t/* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */\n+\t/* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */\n+\t/* Setup REV */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL],\n+\t\t\t BIT(2));\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL],\n+\t\t\t BIT(2));\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_SIGDET_ILEAK], 0x0);\n+\n+\t/* Setup Rdy Timeout */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,\n+\t\t\t AIROHA_PCS_PMA_RX_RDY |\n+\t\t\t AIROHA_PCS_PMA_RX_BLWC_RDY_EN,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));\n+\n+\t/* Setup CaBoundry Init */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,\n+\t\t\t AIROHA_PCS_PMA_RX_OS_START |\n+\t\t\t AIROHA_PCS_PMA_OSC_SPEED_OPT,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |\n+\t\t\t AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,\n+\t\t\t AIROHA_PCS_PMA_RX_OS_END,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,\n+\t\t\t AIROHA_PCS_PMA_RX_PICAL_END |\n+\t\t\t AIROHA_PCS_PMA_RX_PICAL_START,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,\n+\t\t\t AIROHA_PCS_PMA_RX_SDCAL_END |\n+\t\t\t AIROHA_PCS_PMA_RX_SDCAL_START,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,\n+\t\t\t AIROHA_PCS_PMA_RX_PDOS_END |\n+\t\t\t AIROHA_PCS_PMA_RX_PDOS_START,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,\n+\t\t\t AIROHA_PCS_PMA_RX_FEOS_END |\n+\t\t\t AIROHA_PCS_PMA_RX_FEOS_START,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));\n+\n+\t/* Setup By Serdes*/\n+\t/* Setup RX OSR */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], !!osr);\n+\n+\t/* Setup CDR LPF Ratio */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_TOP_LIM], 0x20000);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_RATIO], osr);\n+\n+\t/* Setup CDR PR */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_KBAND_DIV], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_SEL], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VCOADC_OS], 0x8);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_DAC],\n+\t\t\t pr_cdr_beta_dac);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_FBKSEL], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_DAC_BAND],\n+\t\t\t pr_cdr_beta_dac);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL], 0x6);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_IBAND_VAL], 0x6);\n+\n+\t/* Setup Eye Mon */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,\n+\t\t\t AIROHA_PCS_PMA_EQ_DEBUG_SEL |\n+\t\t\t AIROHA_PCS_PMA_FOM_NUM_ORDER |\n+\t\t\t AIROHA_PCS_PMA_A_SEL,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,\n+\t\t\t AIROHA_PCS_PMA_DATA_SHIFT |\n+\t\t\t AIROHA_PCS_PMA_EYECNT_FAST,\n+\t\t\t AIROHA_PCS_PMA_EYECNT_FAST);\n+\n+\t/* Calibration Start */\n+\n+\t/* Enable SYS */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,\n+\t\t\t AIROHA_PCS_PMA_RX_SYS_EN_SEL,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,\n+\t\t\tAIROHA_PCS_PMA_SW_LCPLL_EN);\n+\n+\tusleep_range(500, 600);\n+\n+\t/* Setup FLL PR FMeter (bypass mode)*/\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,\n+\t\t\t AIROHA_PCS_PMA_DISB_FBCK_LOCK);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,\n+\t\t\tAIROHA_PCS_PMA_FORCE_FBCK_LOCK);\n+\n+\t/* Enable CMLEQ */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_EQ_HZEN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ3_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ2_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ1_EN], 0x1);\n+\n+\t/* Setup CDR PR */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_CAP_EN],\n+\t\t\t cdr_pr_cap_en);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_BUF_IN_SR],\n+\t\t\t cdr_pr_buf_in_sr);\n+\n+\t/* Setup CDR xxx Pwdb, set force and disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,\n+\t\t\t AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |\n+\t\t\t AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |\n+\t\t\t AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |\n+\t\t\t AIROHA_PCS_PMA_XPON_RX_FE_PWDB);\n+\n+\t/* FIXME: Ask Airoha WHY it's cleared? */\n+\t/* regmap_clear_bits(priv-\u003epcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,\n+\t *\t\t AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);\n+\t */\n+\n+\t/* Setup SigDet */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_VTH_SEL],\n+\t\t\t sigdet_vth_sel);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_PEAK],\n+\t\t\t BIT(1));\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_LPF_CTRL],\n+\t\t\t BIT(1) | BIT(0));\n+\n+\t/* Disable SigDet Pwdb */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,\n+\t\t\t AIROHA_PCS_PMA_RX_SIDGET_PWDB);\n+\n+\t/* Setup PHYCK */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_TDC_CK_SEL], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_RSTB], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_SEL],\n+\t\t\t phyck_sel);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_DIV],\n+\t\t\t phyck_div);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL_FORCE], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL], 0x0);\n+\n+\tusleep_range(100, 200);\n+\n+\t/* Enable CDR xxx Pwdb */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PD_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PW_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_RX_FE_PWDB);\n+\n+\t/* Enable SigDet Pwdb */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,\n+\t\t\tAIROHA_PCS_PMA_RX_SIDGET_PWDB);\n+}\n+\n+static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t\t int index, u32 cdr_pr_idac)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tu32 val;\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\t AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,\n+\t\t\t\t cdr_pr_idac));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t AIROHA_PCS_PMA_FREQLOCK_DET_EN,\n+\t\t\t AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t AIROHA_PCS_PMA_FREQLOCK_DET_EN,\n+\t\t\t AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);\n+\n+\tusleep_range(5000, 7000);\n+\n+\tregmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, \u0026val);\n+\n+\treturn FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);\n+}\n+\n+static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index, u32 target_fl_out)\n+{\n+\tunsigned int fl_out_diff = UINT_MAX;\n+\tunsigned int prcal_search;\n+\tu32 cdr_pr_idac = 0;\n+\n+\tfor (prcal_search = 0; prcal_search \u003c 8 ; prcal_search++) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tunsigned int fl_out;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\t/* try to find the upper value by setting the last 3 bit */\n+\t\tcdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t prcal_search);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs_diff(fl_out, target_fl_out);\n+\t\tdev_dbg(priv-\u003edev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\t\tif (fl_out_diff_new \u003c fl_out_diff) {\n+\t\t\tcdr_pr_idac = cdr_pr_idac_tmp;\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\t\t}\n+\t}\n+\n+\treturn cdr_pr_idac;\n+}\n+\n+static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\t u32 target_fl_out, u32 cdr_pr_idac_major)\n+{\n+\tunsigned int remaining_prcal_search_bits = 0;\n+\tu32 cdr_pr_idac = cdr_pr_idac_major;\n+\tunsigned int fl_out, fl_out_diff;\n+\tint best_prcal_search_bit = -1;\n+\tint prcal_search_bit;\n+\n+\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);\n+\tfl_out_diff = abs_diff(fl_out, target_fl_out);\n+\n+\t/* Deadline search part.\n+\t * We start from top bits to bottom as we progressively decrease the\n+\t * signal.\n+\t */\n+\tfor (prcal_search_bit = 7; prcal_search_bit \u003e= 0; prcal_search_bit--) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tcdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs_diff(fl_out, target_fl_out);\n+\t\tdev_dbg(priv-\u003edev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\t\tif (fl_out_diff_new \u003c fl_out_diff) {\n+\t\t\tbest_prcal_search_bit = prcal_search_bit;\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\t\t}\n+\t}\n+\n+\t/* Set the idac with the best value we found and\n+\t * reset the search bit to start from bottom to top.\n+\t */\n+\tif (best_prcal_search_bit \u003e= 0) {\n+\t\tcdr_pr_idac |= BIT(best_prcal_search_bit);\n+\t\tremaining_prcal_search_bits = best_prcal_search_bit;\n+\t\tprcal_search_bit = 0;\n+\t}\n+\n+\t/* Fine tune part.\n+\t * Test remaining bits to find an even closer signal level to target\n+\t * by increasing the signal.\n+\t */\n+\twhile (remaining_prcal_search_bits) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tcdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs_diff(fl_out, target_fl_out);\n+\t\t/* Assume we found the deadline when the new absolue signal difference\n+\t\t * from target is greater than the previous and the difference is at\n+\t\t * least 10% greater between the old and new value.\n+\t\t * This is to account for signal detection level tollerance making\n+\t\t * sure we are actually over a deadline (AKA we are getting farther\n+\t\t * from target)\n+\t\t */\n+\t\tdev_dbg(priv-\u003edev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\t\tif (fl_out_diff \u0026\u0026 fl_out_diff_new \u003e fl_out_diff \u0026\u0026\n+\t\t (abs_diff(fl_out_diff_new, fl_out_diff) * 100) / fl_out_diff \u003e 10) {\n+\t\t\t/* Exit early if we are already at the deadline */\n+\t\t\tif (prcal_search_bit == 0)\n+\t\t\t\tbreak;\n+\n+\t\t\t/* We found the deadline, set the value to the previous\n+\t\t\t * bit, and reset the loop to fine tune with the\n+\t\t\t * remaining values.\n+\t\t\t */\n+\t\t\tcdr_pr_idac |= BIT(prcal_search_bit - 1);\n+\t\t\tremaining_prcal_search_bits = prcal_search_bit - 1;\n+\t\t\tprcal_search_bit = 0;\n+\t\t} else {\n+\t\t\t/* Update the signal level diff and try the next bit */\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\n+\t\t\t/* If we didn't found the deadline, set the last bit\n+\t\t\t * and reset the loop to fine tune with the remainig\n+\t\t\t * values.\n+\t\t\t */\n+\t\t\tif (prcal_search_bit == remaining_prcal_search_bits - 1) {\n+\t\t\t\tcdr_pr_idac |= BIT(prcal_search_bit);\n+\t\t\t\tremaining_prcal_search_bits = prcal_search_bit;\n+\t\t\t\tprcal_search_bit = 0;\n+\t\t\t} else {\n+\t\t\t\tprcal_search_bit++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn cdr_pr_idac;\n+}\n+\n+static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv,\n+\t\t\t\tint index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tu32 cdr_pr_idac_major, cdr_pr_idac;\n+\tunsigned int fl_out, fl_out_diff;\n+\n+\tu32 target_fl_out;\n+\tu32 cyclecnt;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\ttarget_fl_out = 0xa3d6;\n+\t\tcyclecnt = 32767;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */\n+\t\ttarget_fl_out = 0xa000;\n+\t\tcyclecnt = 20000;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\ttarget_fl_out = 0x9edf;\n+\t\tcyclecnt = 32767;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tusleep_range(100, 200);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,\n+\t\t\t AIROHA_PCS_PMA_LOCK_TARGET_END |\n+\t\t\t AIROHA_PCS_PMA_LOCK_TARGET_BEG,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,\n+\t\t\t AIROHA_PCS_PMA_UNLOCK_CYCLECNT |\n+\t\t\t AIROHA_PCS_PMA_LOCK_CYCLECNT,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t AIROHA_PCS_PMA_LOCK_UNLOCKTH |\n+\t\t\t AIROHA_PCS_PMA_LOCK_LOCKTH,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,\n+\t\t\t AIROHA_PCS_PMA_UNLOCK_TARGET_END |\n+\t\t\t AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x1);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\t/* Calibration logic:\n+\t * First check the major value by looping with every\n+\t * value in the last 3 bit of CDR_PR_IDAC.\n+\t * Get the signal level and save the value that is closer to\n+\t * the target.\n+\t *\n+\t * Then check each remaining 7 bits in search of the deadline\n+\t * where the signal gets farther than signal target.\n+\t *\n+\t * Finally fine tune for the remaining bits to find the one that\n+\t * produce the closest signal level.\n+\t */\n+\tcdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv, index, target_fl_out);\n+\n+\tcdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, index,\n+\t\t\t\t\t\t target_fl_out, cdr_pr_idac_major);\n+\n+\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);\n+\tfl_out_diff = abs_diff(fl_out, target_fl_out);\n+\tif (fl_out_diff \u003e 100) {\n+\t\tu32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t cdr_pr_idac_major);\n+\t\tunsigned int fl_out_tmp, fl_out_diff_tmp;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tif (pr_idac_major \u003e 0) {\n+\t\t\tcdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t\t pr_idac_major - 1);\n+\n+\t\t\tdev_dbg(priv-\u003edev, \"Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\\n\",\n+\t\t\t\tfl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp);\n+\n+\t\t\tcdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, index,\n+\t\t\t\t\t\t\t\t\t target_fl_out,\n+\t\t\t\t\t\t\t\t\t cdr_pr_idac_tmp);\n+\n+\t\t\tfl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, index,\n+\t\t\t\t\t\t\t\t cdr_pr_idac_tmp);\n+\t\t\tfl_out_diff_tmp = abs_diff(fl_out_tmp, target_fl_out);\n+\t\t\tif (fl_out_diff_tmp \u003c fl_out_diff) {\n+\t\t\t\tfl_out = fl_out_tmp;\n+\t\t\t\tfl_out_diff = fl_out_diff_tmp;\n+\t\t\t\tcdr_pr_idac = cdr_pr_idac_tmp;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tdev_dbg(priv-\u003edev, \"Selected CDR Pr Idac: %x Fl Out: %x\\n\", cdr_pr_idac, fl_out);\n+\tif (fl_out_diff \u003e 100)\n+\t\tdev_dbg(priv-\u003edev, \"Fl Out is %d far from target %d on intermediate calibration.\\n\",\n+\t\t\tfl_out_diff, target_fl_out);\n+\n+\t/* Setup Load Band */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x0);\n+\n+\t/* Disable force of LPF C previously enabled */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_B,\n+\t\t\tAIROHA_PCS_PMA_LOAD_EN);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_1,\n+\t\t\t AIROHA_PCS_PMA_LPATH_IDAC,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t AIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tusleep_range(100, 200);\n+}\n+\n+/* This is used to both calibrate and lock to signal (after a previous\n+ * calibration) after a global reset.\n+ */\n+static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t phy_interface_t interface, bool calibrate)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\n+\t/* Setup LPF L2D force and disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);\n+\n+\t/* Calibrate IDAC and setup Load Band */\n+\tif (calibrate)\n+\t\tan7581_pcs_rx_prcal(priv, index, interface);\n+\n+\t/* Setup LPF RSTB force and disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);\n+\n+\tusleep_range(700, 1000);\n+\n+\t/* Force Enable LPF RSTB */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);\n+\n+\tusleep_range(100, 200);\n+\n+\t/* Force Enable LPF L2D */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);\n+\n+\t/* Disable LPF RSTB force bit */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);\n+\n+\t/* Disable LPF L2D force bit */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);\n+}\n+\n+static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tint calibration_try = 0;\n+\tu32 val;\n+\n+\tan7581_pcs_tx_bringup(priv, index, interface);\n+\tan7581_pcs_rx_bringup(priv, index, interface);\n+\n+\tusleep_range(100, 200);\n+\n+retry_calibration:\n+\tan7581_pcs_cdr_reset(priv, index, interface, priv-\u003emanual_rx_calib);\n+\n+\t/* Global reset clear */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_REF_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_ALLPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_PMA_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_TX_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_RX_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,\n+\t\t\t AIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tusleep_range(100, 200);\n+\n+\t/* Global reset */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_TX_FIFO_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_REF_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_ALLPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_PMA_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_TX_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_RX_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_RX_FIFO_RST_N);\n+\n+\tusleep_range(5000, 7000);\n+\n+\tan7581_pcs_cdr_reset(priv, index, interface, false);\n+\n+\t/* Manual RX calibration is required only for SoC before E2\n+\t * revision. E2+ SoC autocalibrate RX and only CDR reset is needed.\n+\t */\n+\tif (!priv-\u003emanual_rx_calib)\n+\t\treturn 0;\n+\n+\t/* It was discovered that after a global reset and auto mode gets\n+\t * actually enabled, the fl_out from calibration might change and\n+\t * might deviates a lot from the expected value it was calibrated for.\n+\t * To correctly work, the PCS FreqDet module needs to Lock to the fl_out\n+\t * (frequency level output) or no signal can correctly be transmitted.\n+\t * This is detected by checking the FreqDet module Lock bit.\n+\t *\n+\t * If it's detected that the FreqDet module is not locked, retry\n+\t * calibration. From observation on real hardware with a 10g SFP module,\n+\t * it required a maximum of an additional calibration to actually make\n+\t * the FreqDet module to lock. Try 10 times before failing to handle\n+\t * really strange case.\n+\t */\n+\tregmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, \u0026val);\n+\tif (!(val \u0026 AIROHA_PCS_PMA_FBCK_LOCK)) {\n+\t\tif (calibration_try \u003e AIROHA_PCS_MAX_CALIBRATION_TRY) {\n+\t\t\tdev_err(priv-\u003edev, \"No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\\n\",\n+\t\t\t\tAIROHA_PCS_MAX_CALIBRATION_TRY);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tcalibration_try++;\n+\n+\t\tdev_dbg(priv-\u003edev, \"No FBCK Lock from FreqDet module, retry calibration.\\n\");\n+\t\tgoto retry_calibration;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tan7581_pcs_jcpll_bringup(priv, index, interface);\n+\n+\tusleep_range(200, 300);\n+\n+\tan7581_pcs_txpll_bringup(priv, index, interface);\n+\n+\tusleep_range(200, 300);\n+}\n+\n+int an7581_pcs_bringup(struct airoha_pcs_priv *priv, int index,\n+\t\t phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\n+\t/* Enable Analog Common Lane */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CMN_EN], 0x1);\n+\n+\t/* Setup PLL */\n+\tan7581_pcs_pll_bringup(priv, index, interface);\n+\n+\tmsleep(100);\n+\n+\t/* Setup PHYA */\n+\treturn an7581_pcs_phya_bringup(priv, index, interface);\n+}\n+\n+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t int index, phy_interface_t interface)\n+{\n+\tint ret;\n+\n+\tret = phy_set_mode_ext(priv-\u003ephy, PHY_MODE_ETHERNET, interface);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR |\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 |\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR, 0xf) |\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1, 0xc) |\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, 0x3));\n+\n+\t\tregmap_set_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,\n+\t\t\t\tAIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);\n+\t} else {\n+\t\tregmap_clear_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);\n+\t}\n+\n+\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32);\n+\n+\tregmap_clear_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE);\n+\n+\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV,\n+\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, 0x1));\n+\n+\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,\n+\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK)));\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII);\n+\telse\n+\t\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII);\n+\n+\treturn 0;\n+}\n+\n+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\n+\t/* Reset TXPCS on link up */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);\n+\n+\tusleep_range(100, 200);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);\n+}\n+\n+static int __an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\t const struct reg_field *fields)\n+{\n+\tstruct device *dev = priv-\u003edev;\n+\tint i;\n+\n+\tpriv-\u003epcs_ana_fields[index] = devm_kcalloc(dev, AN7581_PCS_FIELDS_MAX,\n+\t\t\t\t\t\t sizeof(*priv-\u003epcs_ana_fields[index]),\n+\t\t\t\t\t\t GFP_KERNEL);\n+\tif (!priv-\u003epcs_ana_fields[index])\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0; i \u003c AN7581_PCS_FIELDS_MAX; i++) {\n+\t\tstruct regmap_field *field;\n+\n+\t\tfield = devm_regmap_field_alloc(dev, priv-\u003epcs_ana,\n+\t\t\t\t\t\tfields[i]);\n+\t\tif (IS_ERR(field))\n+\t\t\treturn PTR_ERR(field);\n+\n+\t\tpriv-\u003epcs_ana_fields[index][i] = field;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)\n+{\n+\treturn __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_fields);\n+}\n+\n+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)\n+{\n+\tint ret;\n+\n+\tret = __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_pcie0_fields);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn __an7581_pcs_alloc_regmap_fields(priv, 1, an7581_pcs_pcie1_fields);\n+}\n+\n+static bool an7581_pcs_have_rx_signal(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tunsigned int count = 0;\n+\tu32 val;\n+\tint i;\n+\n+\tregmap_write(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_0,\n+\t\t AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN);\n+\n+\t/* Scan 6 times for RX sigdet module to detect RX signal */\n+\tfor (i = 0; i \u003c AIROHA_PCS_MAX_RX_SIGDET_TRY; i++) {\n+\t\tregmap_read(pcs_pma, AIROHA_PCS_PMA_DIG_RO_RESERVE_2,\n+\t\t\t \u0026val);\n+\t\tif (val \u0026 AIROHA_PCS_RX_SIGDET)\n+\t\t\tcount++;\n+\t}\n+\n+\t/* Consider signal presence if we detect signal at least 4 times */\n+\treturn count \u003e= AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT;\n+}\n+\n+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 val;\n+\n+\t/* Check if PCS is UP or Down */\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_STUS_1, \u0026val);\n+\tif (val \u0026 AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP)\n+\t\treturn 0;\n+\n+\t/* Validate if this is consistent with RX SigDet module */\n+\tif (!an7581_pcs_have_rx_signal(priv, index))\n+\t\treturn 0;\n+\n+\t/* If PCS is down but RX SigDet module detected signal,\n+\t * trigger CDR reset.\n+\t */\n+\tan7581_pcs_cdr_reset(priv, index, PHY_INTERFACE_MODE_NA, false);\n+\n+\t/* Report there is an error with Link Detection and we\n+\t * should test again later.\n+\t */\n+\treturn -EINVAL;\n+}\ndiff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c\nnew file mode 100644\nindex 00000000000000..7a9d91b2a34da7\n--- /dev/null\n+++ b/drivers/net/pcs/pcs.c\n@@ -0,0 +1,261 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+\n+#include \u003clinux/mutex.h\u003e\n+#include \u003clinux/property.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/pcs/pcs.h\u003e\n+#include \u003clinux/pcs/pcs-provider.h\u003e\n+\n+MODULE_DESCRIPTION(\"PCS library\");\n+MODULE_AUTHOR(\"Christian Marangi \u003cansuelsmth@gmail.com\u003e\");\n+MODULE_LICENSE(\"GPL\");\n+\n+struct fwnode_pcs_provider {\n+\tstruct list_head link;\n+\n+\tstruct fwnode_handle *fwnode;\n+\tstruct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t void *data);\n+\n+\tvoid *data;\n+};\n+\n+static LIST_HEAD(fwnode_pcs_providers);\n+static DEFINE_MUTEX(fwnode_pcs_mutex);\n+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);\n+\n+int register_fwnode_pcs_notifier(struct notifier_block *nb)\n+{\n+\treturn blocking_notifier_chain_register(\u0026fwnode_pcs_notify_list, nb);\n+}\n+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);\n+\n+int unregister_fwnode_pcs_notifier(struct notifier_block *nb)\n+{\n+\treturn blocking_notifier_chain_unregister(\u0026fwnode_pcs_notify_list, nb);\n+}\n+EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier);\n+\n+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t void *data)\n+{\n+\treturn data;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);\n+\n+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,\n+\t\t\t struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t\t void *data),\n+\t\t\t void *data)\n+{\n+\tstruct fwnode_pcs_provider *pp;\n+\n+\tif (!fwnode)\n+\t\treturn 0;\n+\n+\tpp = kzalloc_obj(*pp);\n+\tif (!pp)\n+\t\treturn -ENOMEM;\n+\n+\tpp-\u003efwnode = fwnode_handle_get(fwnode);\n+\tpp-\u003edata = data;\n+\tpp-\u003eget = get;\n+\n+\tmutex_lock(\u0026fwnode_pcs_mutex);\n+\tlist_add(\u0026pp-\u003elink, \u0026fwnode_pcs_providers);\n+\tmutex_unlock(\u0026fwnode_pcs_mutex);\n+\tpr_debug(\"Added pcs provider from %pfwf\\n\", fwnode);\n+\n+\tfwnode_dev_initialized(fwnode, true);\n+\n+\tblocking_notifier_call_chain(\u0026fwnode_pcs_notify_list,\n+\t\t\t\t FWNODE_PCS_PROVIDER_ADD,\n+\t\t\t\t fwnode);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);\n+\n+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)\n+{\n+\tstruct fwnode_pcs_provider *pp;\n+\n+\tif (!fwnode)\n+\t\treturn;\n+\n+\tmutex_lock(\u0026fwnode_pcs_mutex);\n+\tlist_for_each_entry(pp, \u0026fwnode_pcs_providers, link) {\n+\t\tif (pp-\u003efwnode == fwnode) {\n+\t\t\tlist_del(\u0026pp-\u003elink);\n+\t\t\tfwnode_dev_initialized(pp-\u003efwnode, false);\n+\t\t\tfwnode_handle_put(pp-\u003efwnode);\n+\t\t\tkfree(pp);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tmutex_unlock(\u0026fwnode_pcs_mutex);\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);\n+\n+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode,\n+\t\t\t\tint index, const char *name,\n+\t\t\t\tstruct fwnode_reference_args *out_args)\n+{\n+\tint ret;\n+\n+\tif (!fwnode)\n+\t\treturn -EINVAL;\n+\n+\tif (name) {\n+\t\tindex = fwnode_property_match_string(fwnode, \"pcs-names\",\n+\t\t\t\t\t\t name);\n+\t\tif (index \u003c 0)\n+\t\t\treturn index;\n+\t}\n+\n+\tret = fwnode_property_get_reference_args(fwnode, \"pcs-handle\",\n+\t\t\t\t\t\t \"#pcs-cells\",\n+\t\t\t\t\t\t -1, index, out_args);\n+\tif (ret || (name \u0026\u0026 index \u003c 0))\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static struct phylink_pcs *\n+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)\n+{\n+\tstruct fwnode_pcs_provider *provider;\n+\tstruct phylink_pcs *pcs = ERR_PTR(-ENODEV);\n+\n+\tif (!pcsspec)\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\tmutex_lock(\u0026fwnode_pcs_mutex);\n+\tlist_for_each_entry(provider, \u0026fwnode_pcs_providers, link) {\n+\t\tif (provider-\u003efwnode == pcsspec-\u003efwnode) {\n+\t\t\tpcs = provider-\u003eget(pcsspec, provider-\u003edata);\n+\t\t\tif (!IS_ERR(pcs))\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\tmutex_unlock(\u0026fwnode_pcs_mutex);\n+\n+\treturn pcs;\n+}\n+\n+static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,\n+\t\t\t\t\t unsigned int index, const char *con_id)\n+{\n+\tstruct fwnode_reference_args pcsspec;\n+\tstruct phylink_pcs *pcs;\n+\tint ret;\n+\n+\tret = fwnode_parse_pcsspec(fwnode, index, con_id, \u0026pcsspec);\n+\tif (ret)\n+\t\treturn ERR_PTR(ret);\n+\n+\tpcs = fwnode_pcs_get_from_pcsspec(\u0026pcsspec);\n+\tfwnode_handle_put(pcsspec.fwnode);\n+\n+\treturn pcs;\n+}\n+\n+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, unsigned int index)\n+{\n+\treturn __fwnode_pcs_get(fwnode, index, NULL);\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_get);\n+\n+struct phylink_pcs *\n+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,\n+\t\t\t\t struct fwnode_handle *pcs_fwnode)\n+{\n+\tstruct fwnode_reference_args pcsspec;\n+\tint index = 0;\n+\tint ret;\n+\n+\t/* Loop until we find a matching PCS node or\n+\t * fwnode_parse_pcsspec() returns error\n+\t * if we don't have any other PCS reference to check.\n+\t */\n+\twhile (true) {\n+\t\tret = fwnode_parse_pcsspec(fwnode, index, NULL, \u0026pcsspec);\n+\t\tif (ret)\n+\t\t\treturn ERR_PTR(ret);\n+\n+\t\t/* Exit loop if we found the matching PCS node */\n+\t\tif (pcsspec.fwnode == pcs_fwnode) {\n+\t\t\tfwnode_handle_put(pcsspec.fwnode);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Check the next PCS reference */\n+\t\tfwnode_handle_put(pcsspec.fwnode);\n+\t\tindex++;\n+\t}\n+\n+\treturn fwnode_pcs_get(fwnode, index);\n+}\n+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_get_from_fwnode);\n+\n+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)\n+{\n+\tstruct fwnode_reference_args out_args;\n+\tint index = 0;\n+\tint ret;\n+\n+\twhile (true) {\n+\t\tret = fwnode_property_get_reference_args(fwnode, \"pcs-handle\",\n+\t\t\t\t\t\t\t \"#pcs-cells\",\n+\t\t\t\t\t\t\t -1, index, \u0026out_args);\n+\t\t/* We expect to reach an -ENOENT error while counting */\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\tfwnode_handle_put(out_args.fwnode);\n+\t\tindex++;\n+\t}\n+\n+\treturn index;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_count);\n+\n+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,\n+\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t unsigned int num_pcs)\n+{\n+\tunsigned int i, found = 0;\n+\n+\tif (!available_pcs)\n+\t\treturn -EINVAL;\n+\n+\tif (!fwnode_property_present(fwnode, \"pcs-handle\"))\n+\t\treturn -ENODEV;\n+\n+\tfor (i = 0; i \u003c num_pcs; i++) {\n+\t\tstruct phylink_pcs *pcs;\n+\n+\t\tpcs = fwnode_pcs_get(fwnode, i);\n+\t\tif (IS_ERR(pcs)) {\n+\t\t\t/* Exit early if no PCS remain.*/\n+\t\t\tif (PTR_ERR(pcs) == -ENOENT)\n+\t\t\t\tbreak;\n+\n+\t\t\t/*\n+\t\t\t * Ignore -ENODEV error for PCS that still\n+\t\t\t * needs to probe.\n+\t\t\t */\n+\t\t\tif (PTR_ERR(pcs) == -ENODEV)\n+\t\t\t\tcontinue;\n+\n+\t\t\treturn PTR_ERR(pcs);\n+\t\t}\n+\n+\t\tavailable_pcs[found] = pcs;\n+\t\tfound++;\n+\t}\n+\n+\treturn found;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);\ndiff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c\nindex 59dfe35afa54fc..e36a6647d7e81b 100644\n--- a/drivers/net/phy/phylink.c\n+++ b/drivers/net/phy/phylink.c\n@@ -12,6 +12,7 @@\n #include \u003clinux/netdevice.h\u003e\n #include \u003clinux/of.h\u003e\n #include \u003clinux/of_mdio.h\u003e\n+#include \u003clinux/pcs/pcs.h\u003e\n #include \u003clinux/phy.h\u003e\n #include \u003clinux/phy_fixed.h\u003e\n #include \u003clinux/phylink.h\u003e\n@@ -60,6 +61,15 @@ struct phylink {\n \t/* The link configuration settings */\n \tstruct phylink_link_state link_config;\n \n+\t/* List of available PCS */\n+\tstruct list_head pcs_list;\n+\tstruct notifier_block fwnode_pcs_nb;\n+\n+\t/* What interface are supported by the current link.\n+\t * Can change on removal or addition of new PCS.\n+\t */\n+\tDECLARE_PHY_INTERFACE_MASK(supported_interfaces);\n+\n \t/* The current settings */\n \tphy_interface_t cur_interface;\n \n@@ -149,6 +159,10 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {\n \n static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);\n \n+static void phylink_run_resolve(struct phylink *pl);\n+static void phylink_link_down(struct phylink *pl);\n+static void phylink_pcs_disable(struct phylink_pcs *pcs);\n+\n /**\n * phylink_set_port_modes() - set the port type modes in the ethtool mask\n * @mask: ethtool link mode mask\n@@ -512,12 +526,29 @@ static void phylink_validate_mask_caps(unsigned long *supported,\n \tlinkmode_and(state-\u003eadvertising, state-\u003eadvertising, mask);\n }\n \n+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,\n+\t\t\t\t\t phy_interface_t interface)\n+{\n+\t/* If PCS define an empty supported_interfaces value, assume\n+\t * all interface are supported.\n+\t */\n+\tif (phy_interface_empty(pcs-\u003esupported_interfaces))\n+\t\treturn 0;\n+\n+\t/* Ensure that this PCS supports the interface mode */\n+\tif (!test_bit(interface, pcs-\u003esupported_interfaces))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n static int phylink_validate_mac_and_pcs(struct phylink *pl,\n \t\t\t\t\tunsigned long *supported,\n \t\t\t\t\tstruct phylink_link_state *state)\n {\n-\tstruct phylink_pcs *pcs = NULL;\n \tunsigned long capabilities;\n+\tstruct phylink_pcs *pcs;\n+\tbool pcs_found = false;\n \tint ret;\n \n \t/* Get the PCS for this interface mode */\n@@ -525,9 +556,24 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,\n \t\tpcs = pl-\u003emac_ops-\u003emac_select_pcs(pl-\u003econfig, state-\u003einterface);\n \t\tif (IS_ERR(pcs))\n \t\t\treturn PTR_ERR(pcs);\n+\n+\t\tpcs_found = !!pcs;\n+\t/*\n+\t * Find a PCS in available PCS list for the requested interface.\n+\t *\n+\t * Skip searching if the MAC doesn't require a dedicated PCS for\n+\t * the requested interface.\n+\t */\n+\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\n+\t\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list) {\n+\t\t\tif (!phylink_validate_pcs_interface(pcs, state-\u003einterface)) {\n+\t\t\t\tpcs_found = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \t}\n \n-\tif (pcs) {\n+\tif (pcs_found) {\n \t\t/* The PCS, if present, must be setup before phylink_create()\n \t\t * has been called. If the ops is not initialised, print an\n \t\t * error and backtrace rather than oopsing the kernel.\n@@ -539,13 +585,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,\n \t\t\treturn -EINVAL;\n \t\t}\n \n-\t\t/* Ensure that this PCS supports the interface which the MAC\n-\t\t * returned it for. It is an error for the MAC to return a PCS\n-\t\t * that does not support the interface mode.\n-\t\t */\n-\t\tif (!phy_interface_empty(pcs-\u003esupported_interfaces) \u0026\u0026\n-\t\t !test_bit(state-\u003einterface, pcs-\u003esupported_interfaces)) {\n-\t\t\tphylink_err(pl, \"MAC returned PCS which does not support %s\\n\",\n+\t\t/* Recheck PCS to handle legacy way for .mac_select_pcs */\n+\t\tret = phylink_validate_pcs_interface(pcs, state-\u003einterface);\n+\t\tif (ret) {\n+\t\t\tphylink_err(pl, \"selected PCS does not support %s\\n\",\n \t\t\t\t phy_modes(state-\u003einterface));\n \t\t\treturn -EINVAL;\n \t\t}\n@@ -628,7 +671,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,\n static int phylink_validate(struct phylink *pl, unsigned long *supported,\n \t\t\t struct phylink_link_state *state)\n {\n-\tconst unsigned long *interfaces = pl-\u003econfig-\u003esupported_interfaces;\n+\tconst unsigned long *interfaces = pl-\u003esupported_interfaces;\n \n \tif (state-\u003einterface == PHY_INTERFACE_MODE_NA)\n \t\treturn phylink_validate_mask(pl, NULL, supported, state,\n@@ -878,6 +921,60 @@ static void phylink_resolve_an_pause(struct phylink_link_state *state)\n \t}\n }\n \n+/**\n+ * phylink_release_pcs - Removes a PCS from the phylink PCS available list\n+ * @pcs: a pointer to the phylink_pcs struct to be released\n+ *\n+ * This function release a PCS from the phylink PCS available list if\n+ * actually in use. It also refreshes the supported interfaces of the\n+ * phylink instance by copying the supported interfaces from the phylink\n+ * conf and merging the supported interfaces of the remaining available PCS\n+ * in the list and trigger a resolve.\n+ */\n+void phylink_release_pcs(struct phylink_pcs *pcs)\n+{\n+\tstruct phylink *pl;\n+\n+\tASSERT_RTNL();\n+\n+\tpl = pcs-\u003ephylink;\n+\tif (!pl)\n+\t\treturn;\n+\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\n+\tlist_del(\u0026pcs-\u003elist);\n+\tpcs-\u003ephylink = NULL;\n+\n+\t/*\n+\t * Check if we are removing the PCS currently\n+\t * in use by phylink. If this is the case, tear down\n+\t * the link, force phylink resolve to reconfigure the\n+\t * interface mode, disable the current PCS and set the\n+\t * phylink PCS to NULL.\n+\t */\n+\tif (pl-\u003epcs == pcs) {\n+\t\tphylink_link_down(pl);\n+\t\tphylink_pcs_disable(pl-\u003epcs);\n+\n+\t\tpl-\u003eforce_major_config = true;\n+\t\tpl-\u003epcs = NULL;\n+\t}\n+\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n+\t/* Refresh supported interfaces */\n+\tphy_interface_copy(pl-\u003esupported_interfaces,\n+\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n+\t\tphy_interface_or(pl-\u003esupported_interfaces,\n+\t\t\t\t pl-\u003esupported_interfaces,\n+\t\t\t\t pcs-\u003esupported_interfaces);\n+\n+\tphylink_run_resolve(pl);\n+}\n+EXPORT_SYMBOL_GPL(phylink_release_pcs);\n+\n static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs,\n \t\t\t\t phy_interface_t interface)\n {\n@@ -940,6 +1037,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,\n \t\tpcs-\u003eops-\u003epcs_link_up(pcs, neg_mode, interface, speed, duplex);\n }\n \n+static void phylink_pcs_link_down(struct phylink_pcs *pcs)\n+{\n+\tif (pcs \u0026\u0026 pcs-\u003eops-\u003epcs_link_down)\n+\t\tpcs-\u003eops-\u003epcs_link_down(pcs);\n+}\n+\n static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)\n {\n \tif (pcs \u0026\u0026 pcs-\u003eops-\u003epcs_disable_eee)\n@@ -959,12 +1062,22 @@ static unsigned int phylink_inband_caps(struct phylink *pl,\n \t\t\t\t\t phy_interface_t interface)\n {\n \tstruct phylink_pcs *pcs;\n+\tbool pcs_found = false;\n \n-\tif (!pl-\u003emac_ops-\u003emac_select_pcs)\n-\t\treturn 0;\n+\tif (pl-\u003emac_ops-\u003emac_select_pcs) {\n+\t\tpcs = pl-\u003emac_ops-\u003emac_select_pcs(pl-\u003econfig,\n+\t\t\t\t\t\t interface);\n+\t\tpcs_found = !!pcs;\n+\t} else if (test_bit(interface, pl-\u003econfig-\u003epcs_interfaces)) {\n+\t\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list) {\n+\t\t\tif (!phylink_validate_pcs_interface(pcs, interface)) {\n+\t\t\t\tpcs_found = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n \n-\tpcs = pl-\u003emac_ops-\u003emac_select_pcs(pl-\u003econfig, interface);\n-\tif (!pcs)\n+\tif (!pcs_found)\n \t\treturn 0;\n \n \treturn phylink_pcs_inband_caps(pcs, interface);\n@@ -1259,10 +1372,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,\n \t\t\tpl-\u003emajor_config_failed = true;\n \t\t\treturn;\n \t\t}\n+\t/* Find a PCS in available PCS list for the requested interface.\n+\t * This doesn't overwrite the previous .mac_select_pcs as either\n+\t * .mac_select_pcs or PCS list implementation are permitted.\n+\t *\n+\t * Skip searching if the MAC doesn't require a dedicated PCS for\n+\t * the requested interface.\n+\t */\n+\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\n+\t\tbool pcs_found = false;\n+\n+\t\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list) {\n+\t\t\tif (!phylink_validate_pcs_interface(pcs,\n+\t\t\t\t\t\t\t state-\u003einterface)) {\n+\t\t\t\tpcs_found = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \n-\t\tpcs_changed = pl-\u003epcs != pcs;\n+\t\tif (!pcs_found) {\n+\t\t\tphylink_err(pl,\n+\t\t\t\t \"couldn't find a PCS for %s\\n\",\n+\t\t\t\t phy_modes(state-\u003einterface));\n+\n+\t\t\tpl-\u003emajor_config_failed = true;\n+\t\t\treturn;\n+\t\t}\n \t}\n \n+\tpcs_changed = pl-\u003epcs != pcs;\n+\n \tphylink_pcs_neg_mode(pl, pcs, state-\u003einterface, state-\u003eadvertising);\n \n \tphylink_dbg(pl, \"major config, active %s/%s/%s\\n\",\n@@ -1289,13 +1428,15 @@ static void phylink_major_config(struct phylink *pl, bool restart,\n \tif (pcs_changed) {\n \t\tphylink_pcs_disable(pl-\u003epcs);\n \n-\t\tif (pl-\u003epcs)\n-\t\t\tpl-\u003epcs-\u003ephylink = NULL;\n+\t\tif (pl-\u003emac_ops-\u003emac_select_pcs) {\n+\t\t\tif (pl-\u003epcs)\n+\t\t\t\tpl-\u003epcs-\u003ephylink = NULL;\n \n-\t\tif (pcs)\n-\t\t\tpcs-\u003ephylink = pl;\n+\t\t\tif (pcs)\n+\t\t\t\tpcs-\u003ephylink = pl;\n+\t\t}\n \n-\t\tpl-\u003epcs = pcs;\n+\t\tWRITE_ONCE(pl-\u003epcs, pcs);\n \t}\n \n \tif (pl-\u003epcs)\n@@ -1603,6 +1744,9 @@ static void phylink_link_down(struct phylink *pl)\n \n \tpl-\u003emac_ops-\u003emac_link_down(pl-\u003econfig, pl-\u003eact_link_an_mode,\n \t\t\t\t pl-\u003ecur_interface);\n+\n+\tphylink_pcs_link_down(pl-\u003epcs);\n+\n \tphylink_info(pl, \"Link is Down\\n\");\n }\n \n@@ -1828,6 +1972,91 @@ int phylink_set_fixed_link(struct phylink *pl,\n }\n EXPORT_SYMBOL_GPL(phylink_set_fixed_link);\n \n+static int phylink_fill_available_pcs(struct phylink *pl,\n+\t\t\t\t struct phylink_config *config)\n+{\n+\tstruct phylink_pcs **pcss;\n+\tint i, ret;\n+\n+\tif (!config-\u003enum_possible_pcs)\n+\t\treturn 0;\n+\n+\tif (!config-\u003efill_available_pcs) {\n+\t\tdev_err(config-\u003edev,\n+\t\t\t\"phylink: error: num_possible_pcs defined but no fill_available_pcs\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpcss = kzalloc_objs(*pcss, config-\u003enum_possible_pcs);\n+\tif (!pcss)\n+\t\treturn -ENOMEM;\n+\n+\tret = config-\u003efill_available_pcs(config, pcss, config-\u003enum_possible_pcs);\n+\tif (ret \u003c 0)\n+\t\tgoto out;\n+\n+\tfor (i = 0; i \u003c config-\u003enum_possible_pcs; i++) {\n+\t\tstruct phylink_pcs *pcs = pcss[i];\n+\n+\t\tif (!pcs)\n+\t\t\tcontinue;\n+\n+\t\tlist_add(\u0026pcs-\u003elist, \u0026pl-\u003epcs_list);\n+\t}\n+\n+out:\n+\tkfree(pcss);\n+\n+\treturn ret;\n+}\n+\n+static int pcs_provider_notify(struct notifier_block *self,\n+\t\t\t unsigned long val, void *data)\n+{\n+\tstruct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);\n+\tstruct fwnode_handle *pcs_fwnode = data;\n+\tstruct phylink_pcs *pcs;\n+\n+\trtnl_lock();\n+\n+\t/* Check if the just added PCS provider is\n+\t * in the phylink instance pcs-handle property.\n+\t */\n+\tpcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl-\u003econfig-\u003edev),\n+\t\t\t\t\t\t pcs_fwnode);\n+\tif (IS_ERR(pcs)) {\n+\t\trtnl_unlock();\n+\t\treturn NOTIFY_DONE;\n+\t}\n+\n+\t/* Add the PCS */\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\n+\t/* Link PCS with phylink */\n+\tlist_add(\u0026pcs-\u003elist, \u0026pl-\u003epcs_list);\n+\tpcs-\u003ephylink = pl;\n+\n+\t/* Refresh supported interfaces */\n+\tphy_interface_copy(pl-\u003esupported_interfaces,\n+\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n+\t\tphy_interface_or(pl-\u003esupported_interfaces,\n+\t\t\t\t pl-\u003esupported_interfaces,\n+\t\t\t\t pcs-\u003esupported_interfaces);\n+\n+\t/* Force an interface reconfig if major config fail */\n+\tif (pl-\u003emajor_config_failed)\n+\t\tpl-\u003eforce_major_config = true;\n+\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n+\trtnl_unlock();\n+\n+\tphylink_run_resolve(pl);\n+\n+\treturn NOTIFY_OK;\n+}\n+\n /**\n * phylink_create() - create a phylink instance\n * @config: a pointer to the target \u0026struct phylink_config\n@@ -1849,13 +2078,17 @@ struct phylink *phylink_create(struct phylink_config *config,\n \t\t\t phy_interface_t iface,\n \t\t\t const struct phylink_mac_ops *mac_ops)\n {\n+\tstruct phylink_pcs *pcs;\n \tstruct phylink *pl;\n \tint ret;\n \n-\t/* Validate the supplied configuration */\n-\tif (phy_interface_empty(config-\u003esupported_interfaces)) {\n+\t/*\n+\t * Make sure either PCS internal validation or .mac_select_pcs\n+\t * is used. Return error if both are defined.\n+\t */\n+\tif (config-\u003enum_possible_pcs \u0026\u0026 mac_ops-\u003emac_select_pcs) {\n \t\tdev_err(config-\u003edev,\n-\t\t\t\"phylink: error: empty supported_interfaces\\n\");\n+\t\t\t\"phylink: error: either phylink_config .num_possible_pcs or .mac_select_pcs must be used\\n\");\n \t\treturn ERR_PTR(-EINVAL);\n \t}\n \n@@ -1866,6 +2099,25 @@ struct phylink *phylink_create(struct phylink_config *config,\n \tmutex_init(\u0026pl-\u003ephydev_mutex);\n \tmutex_init(\u0026pl-\u003estate_mutex);\n \tINIT_WORK(\u0026pl-\u003eresolve, phylink_resolve);\n+\tINIT_LIST_HEAD(\u0026pl-\u003epcs_list);\n+\n+\t/* Fill the PCS list with available PCS from phylink config */\n+\tret = phylink_fill_available_pcs(pl, config);\n+\tif (ret \u003c 0)\n+\t\tgoto free_pl;\n+\n+\t/* Link available PCS to phylink */\n+\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n+\t\tpcs-\u003ephylink = pl;\n+\n+\tphy_interface_copy(pl-\u003esupported_interfaces,\n+\t\t\t config-\u003esupported_interfaces);\n+\n+\t/* Update supported interfaces */\n+\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n+\t\tphy_interface_or(pl-\u003esupported_interfaces,\n+\t\t\t\t pl-\u003esupported_interfaces,\n+\t\t\t\t pcs-\u003esupported_interfaces);\n \n \tpl-\u003econfig = config;\n \tif (config-\u003etype == PHYLINK_NETDEV) {\n@@ -1874,8 +2126,7 @@ struct phylink *phylink_create(struct phylink_config *config,\n \t} else if (config-\u003etype == PHYLINK_DEV) {\n \t\tpl-\u003edev = config-\u003edev;\n \t} else {\n-\t\tkfree(pl);\n-\t\treturn ERR_PTR(-EINVAL);\n+\t\tgoto unlink_pcs_list;\n \t}\n \n \tpl-\u003emac_supports_eee_ops = phylink_mac_implements_lpi(mac_ops);\n@@ -1908,28 +2159,35 @@ struct phylink *phylink_create(struct phylink_config *config,\n \tphylink_validate(pl, pl-\u003esupported, \u0026pl-\u003elink_config);\n \n \tret = phylink_parse_mode(pl, fwnode);\n-\tif (ret \u003c 0) {\n-\t\tkfree(pl);\n-\t\treturn ERR_PTR(ret);\n-\t}\n+\tif (ret \u003c 0)\n+\t\tgoto unlink_pcs_list;\n \n \tif (pl-\u003ecfg_link_an_mode == MLO_AN_FIXED) {\n \t\tret = phylink_parse_fixedlink(pl, fwnode);\n-\t\tif (ret \u003c 0) {\n-\t\t\tkfree(pl);\n-\t\t\treturn ERR_PTR(ret);\n-\t\t}\n+\t\tif (ret \u003c 0)\n+\t\t\tgoto unlink_pcs_list;\n \t}\n \n \tpl-\u003ereq_link_an_mode = pl-\u003ecfg_link_an_mode;\n \n \tret = phylink_register_sfp(pl, fwnode);\n-\tif (ret \u003c 0) {\n-\t\tkfree(pl);\n-\t\treturn ERR_PTR(ret);\n+\tif (ret \u003c 0)\n+\t\tgoto unlink_pcs_list;\n+\n+\t/* Register notifier for late PCS attach */\n+\tif (!phy_interface_empty(config-\u003epcs_interfaces)) {\n+\t\tpl-\u003efwnode_pcs_nb.notifier_call = pcs_provider_notify;\n+\t\tregister_fwnode_pcs_notifier(\u0026pl-\u003efwnode_pcs_nb);\n \t}\n \n \treturn pl;\n+\n+unlink_pcs_list:\n+\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n+\t\tpcs-\u003ephylink = NULL;\n+free_pl:\n+\tkfree(pl);\n+\treturn ERR_PTR(ret);\n }\n EXPORT_SYMBOL_GPL(phylink_create);\n \n@@ -1944,11 +2202,24 @@ EXPORT_SYMBOL_GPL(phylink_create);\n */\n void phylink_destroy(struct phylink *pl)\n {\n+\tstruct phylink_pcs *pcs, *tmp;\n+\n \tsfp_bus_del_upstream(pl-\u003esfp_bus);\n \tif (pl-\u003elink_gpio)\n \t\tgpiod_put(pl-\u003elink_gpio);\n \n+\t/* Unregister notifier for late PCS attach */\n+\tif (pl-\u003efwnode_pcs_nb.notifier_call)\n+\t\tunregister_fwnode_pcs_notifier(\u0026pl-\u003efwnode_pcs_nb);\n+\n \tcancel_work_sync(\u0026pl-\u003eresolve);\n+\n+\t/* Drop link between PCS and phylink */\n+\tlist_for_each_entry_safe(pcs, tmp, \u0026pl-\u003epcs_list, list) {\n+\t\tpcs-\u003ephylink = NULL;\n+\t\tlist_del(\u0026pcs-\u003elist);\n+\t}\n+\n \tkfree(pl);\n }\n EXPORT_SYMBOL_GPL(phylink_destroy);\n@@ -2025,7 +2296,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,\n \t\t * those which the host supports.\n \t\t */\n \t\tphy_interface_and(interfaces, phy-\u003epossible_interfaces,\n-\t\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\t\t\t\t pl-\u003esupported_interfaces);\n \n \t\tif (phy_interface_empty(interfaces)) {\n \t\t\tphylink_err(pl, \"PHY has no common interfaces\\n\");\n@@ -2404,8 +2675,15 @@ void phylink_pcs_change(struct phylink_pcs *pcs, bool up)\n {\n \tstruct phylink *pl = pcs-\u003ephylink;\n \n-\tif (pl)\n-\t\tphylink_link_changed(pl, up, \"pcs\");\n+\t/*\n+\t * Ignore PCS link state change if the PCS is not\n+\t * attached to a phylink instance or the phylink\n+\t * instance is not currently using this PCS.\n+\t */\n+\tif (!pl || READ_ONCE(pl-\u003epcs) != pcs)\n+\t\treturn;\n+\n+\tphylink_link_changed(pl, up, \"pcs\");\n }\n EXPORT_SYMBOL_GPL(phylink_pcs_change);\n \n@@ -2827,12 +3105,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,\n \t\treturn interface;\n \t}\n \n-\tif (!test_bit(interface, pl-\u003econfig-\u003esupported_interfaces)) {\n+\tif (!test_bit(interface, pl-\u003esupported_interfaces)) {\n \t\tphylink_err(pl,\n \t\t\t \"selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\\n\",\n \t\t\t phy_modes(interface), interface,\n \t\t\t (int)PHY_INTERFACE_MODE_MAX,\n-\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\t\t\t pl-\u003esupported_interfaces);\n \t\treturn PHY_INTERFACE_MODE_NA;\n \t}\n \n@@ -3760,14 +4038,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)\n \n \tphylink_dbg(pl, \"optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\\n\",\n \t\t (int)PHY_INTERFACE_MODE_MAX,\n-\t\t pl-\u003econfig-\u003esupported_interfaces,\n+\t\t pl-\u003esupported_interfaces,\n \t\t (int)PHY_INTERFACE_MODE_MAX,\n \t\t pl-\u003esfp_interfaces);\n \n \t/* Find the union of the supported interfaces by the PCS/MAC and\n \t * the SFP module.\n \t */\n-\tphy_interface_and(pl-\u003esfp_interfaces, pl-\u003econfig-\u003esupported_interfaces,\n+\tphy_interface_and(pl-\u003esfp_interfaces, pl-\u003esupported_interfaces,\n \t\t\t pl-\u003esfp_interfaces);\n \tif (phy_interface_empty(pl-\u003esfp_interfaces)) {\n \t\tphylink_err(pl, \"unsupported SFP module: no common interface modes\\n\");\n@@ -3938,7 +4216,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)\n \n \t/* Set the PHY's host supported interfaces */\n \tphy_interface_and(phy-\u003ehost_interfaces, phylink_sfp_interfaces,\n-\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\t\t\t pl-\u003esupported_interfaces);\n \n \t/* Do the initial configuration */\n \treturn phylink_sfp_config_phy(pl, phy);\ndiff --git a/drivers/of/property.c b/drivers/of/property.c\nindex 72cf12907de034..91c3e3931fa6e3 100644\n--- a/drivers/of/property.c\n+++ b/drivers/of/property.c\n@@ -1415,6 +1415,7 @@ DEFINE_SIMPLE_PROP(access_controllers, \"access-controllers\", \"#access-controller\n DEFINE_SIMPLE_PROP(pses, \"pses\", \"#pse-cells\")\n DEFINE_SIMPLE_PROP(power_supplies, \"power-supplies\", NULL)\n DEFINE_SIMPLE_PROP(mmc_pwrseq, \"mmc-pwrseq\", NULL)\n+DEFINE_SIMPLE_PROP(pcs_handle, \"pcs-handle\", \"#pcs-cells\")\n DEFINE_SUFFIX_PROP(regulators, \"-supply\", NULL)\n DEFINE_SUFFIX_PROP(gpio, \"-gpio\", \"#gpio-cells\")\n \n@@ -1571,6 +1572,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {\n \t{ .parse_prop = parse_interrupts, },\n \t{ .parse_prop = parse_interrupt_map, },\n \t{ .parse_prop = parse_access_controllers, },\n+\t{ .parse_prop = parse_pcs_handle, },\n \t{ .parse_prop = parse_regulators, },\n \t{ .parse_prop = parse_gpio, },\n \t{ .parse_prop = parse_gpios, },\ndiff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h\nnew file mode 100644\nindex 00000000000000..ae51c108147e33\n--- /dev/null\n+++ b/include/linux/pcs/pcs-provider.h\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+#ifndef __LINUX_PCS_PROVIDER_H\n+#define __LINUX_PCS_PROVIDER_H\n+\n+/**\n+ * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS\n+ * @pcsspec: reference arguments\n+ * @data: Context data (assumed assigned to the single PCS)\n+ *\n+ * Returns: the PCS pointed by data.\n+ */\n+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t void *data);\n+\n+/**\n+ * fwnode_pcs_add_provider - Registers a new PCS provider\n+ * @fwnode: Firmware node\n+ * @get: xlate function to retrieve the PCS\n+ * @data: Context data\n+ *\n+ * Register and add a new PCS to the global providers list\n+ * for the firmware node. A function to get the PCS from\n+ * firmware node with the use fwnode reference arguments.\n+ * To the get function is also passed the interface type\n+ * requested for the PHY. PCS driver will use the passed\n+ * interface to understand if the PCS can support it or not.\n+ *\n+ * Returns: 0 on success or -ENOMEM on allocation failure.\n+ */\n+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,\n+\t\t\t struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t\t void *data),\n+\t\t\t void *data);\n+\n+/**\n+ * fwnode_pcs_del_provider - Removes a PCS provider\n+ * @fwnode: Firmware node\n+ */\n+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);\n+\n+#endif /* __LINUX_PCS_PROVIDER_H */\ndiff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h\nnew file mode 100644\nindex 00000000000000..45e8f96662db26\n--- /dev/null\n+++ b/include/linux/pcs/pcs.h\n@@ -0,0 +1,140 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+#ifndef __LINUX_PCS_H\n+#define __LINUX_PCS_H\n+\n+#include \u003clinux/phylink.h\u003e\n+\n+enum fwnode_pcs_notify_event {\n+\tFWNODE_PCS_PROVIDER_ADD,\n+};\n+\n+#if IS_ENABLED(CONFIG_FWNODE_PCS)\n+/**\n+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode\n+ *\t\t\t\t PCS events\n+ * @nb: pointer to the notifier block\n+ *\n+ * Registers a notifier block to the fwnode_pcs_notify_list blocking\n+ * notifier chain. This allows phylink instance to subscribe for\n+ * PCS provider events.\n+ *\n+ * Returns: 0 or a negative error.\n+ */\n+int register_fwnode_pcs_notifier(struct notifier_block *nb);\n+\n+/**\n+ * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode\n+ *\t\t\t\t PCS events\n+ * @nb: pointer to the notifier block\n+ *\n+ * Unregisters a notifier block to the fwnode_pcs_notify_list blocking\n+ * notifier chain.\n+ *\n+ * Returns: 0 or a negative error.\n+ */\n+int unregister_fwnode_pcs_notifier(struct notifier_block *nb);\n+\n+/**\n+ * fwnode_pcs_get - Retrieves a PCS from a firmware node\n+ * @fwnode: firmware node\n+ * @index: index fwnode PCS handle in firmware node\n+ *\n+ * Get a PCS from the firmware node at index.\n+ *\n+ * Returns: a pointer to the phylink_pcs or a negative\n+ * error pointer. Can return -ENODEV if the PCS is not\n+ * present in global providers list (either due to driver\n+ * still needs to be probed or it failed to probe/removed).\n+ */\n+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,\n+\t\t\t\t unsigned int index);\n+\n+/**\n+ * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided\n+ *\t\t\t\t\tby the firmware node from a\n+ *\t\t\t\t\tfirmware node\n+ * @fwnode: firmware node\n+ * @pcs_fwnode: PCS firmware node\n+ *\n+ * Parse 'pcs-handle' in 'fwnode' and get the PCS that match\n+ * 'pcs_fwnode' firmware node.\n+ *\n+ * Returns: a pointer to the phylink_pcs or a negative\n+ * error pointer. Can return -EPROBE_DEFER if the PCS is not\n+ * present in global providers list (either due to driver\n+ * still needs to be probed or it failed to probe/removed)\n+ */\n+struct phylink_pcs *\n+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,\n+\t\t\t\t struct fwnode_handle *pcs_fwnode);\n+\n+/**\n+ * fwnode_phylink_pcs_count - count PCS entries described in firmware node\n+ * @fwnode: firmware node\n+ *\n+ * Helper function to count the number of PCS entries referenced by the\n+ * \"pcs-handle\" property in a firmware node.\n+ *\n+ * Note that this function counts all PCS references in the firmware node,\n+ * regardless of whether the corresponding PCS devices are already probed.\n+ *\n+ * Returns: number of PCS entries described in the firmware node.\n+ */\n+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode);\n+\n+/**\n+ * fwnode_phylink_pcs_parse - parse available PCS from firmware node\n+ * @fwnode: firmware node\n+ * @available_pcs: pointer to preallocated array of PCS\n+ * @num_pcs: maximum number of PCS entries to scan\n+ *\n+ * Helper function that parses PCS references from the \"pcs-handle\"\n+ * property of a firmware node and fills @available_pcs with PCS that are\n+ * currently available up to @num_pcs.\n+ *\n+ * Only PCS that are currently available are stored in @available_pcs.\n+ * PCS that returns -ENODEV are skipped.\n+ *\n+ * Returns: number of PCS stored in @available_pcs, or negative error code.\n+ */\n+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,\n+\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t unsigned int num_pcs);\n+#else\n+static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline int unregister_fwnode_pcs_notifier(struct notifier_block *nb)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,\n+\t\t\t\t\t\t unsigned int index)\n+{\n+\treturn ERR_PTR(-ENOENT);\n+}\n+\n+static inline struct phylink_pcs *\n+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,\n+\t\t\t\t struct fwnode_handle *pcs_fwnode)\n+{\n+\treturn ERR_PTR(-ENOENT);\n+}\n+\n+static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)\n+{\n+\treturn 0;\n+}\n+\n+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,\n+\t\t\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t\t\t unsigned int num_pcs)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+#endif\n+\n+#endif /* __LINUX_PCS_H */\ndiff --git a/include/linux/phylink.h b/include/linux/phylink.h\nindex 2bc0db3d52ac8d..ecf4c384fd31ca 100644\n--- a/include/linux/phylink.h\n+++ b/include/linux/phylink.h\n@@ -12,6 +12,7 @@ struct ethtool_cmd;\n struct fwnode_handle;\n struct net_device;\n struct phylink;\n+struct phylink_pcs;\n \n enum {\n \tMLO_PAUSE_NONE,\n@@ -151,6 +152,8 @@ enum phylink_op_type {\n *\t\t if MAC link is at %MLO_AN_FIXED mode.\n * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx\n * are supported by the MAC/PCS.\n+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a\n+ *\t\t dedicated PCS is required.\n * @lpi_interfaces: bitmap describing which PHY interface modes can support\n *\t\t LPI signalling.\n * @mac_capabilities: MAC pause/speed/duplex capabilities.\n@@ -160,6 +163,10 @@ enum phylink_op_type {\n * @wol_phy_legacy: Use Wake-on-Lan with PHY even if phy_can_wakeup() is false\n * @wol_phy_speed_ctrl: Use phy speed control on suspend/resume\n * @wol_mac_support: Bitmask of MAC supported %WAKE_* options\n+ * @num_possible_pcs: num of possible phylink_pcs PCS\n+ * @fill_available_pcs: callback to fill the available PCS in the passed\n+ *\t\t\tarray struct of phylink_pcs PCS available_pcs up to\n+ *\t\t\tnum_possible_pcs.\n */\n struct phylink_config {\n \tstruct device *dev;\n@@ -172,6 +179,7 @@ struct phylink_config {\n \tvoid (*get_fixed_state)(struct phylink_config *config,\n \t\t\t\tstruct phylink_link_state *state);\n \tDECLARE_PHY_INTERFACE_MASK(supported_interfaces);\n+\tDECLARE_PHY_INTERFACE_MASK(pcs_interfaces);\n \tDECLARE_PHY_INTERFACE_MASK(lpi_interfaces);\n \tunsigned long mac_capabilities;\n \tunsigned long lpi_capabilities;\n@@ -182,6 +190,11 @@ struct phylink_config {\n \tbool wol_phy_legacy;\n \tbool wol_phy_speed_ctrl;\n \tu32 wol_mac_support;\n+\n+\tunsigned int num_possible_pcs;\n+\tint (*fill_available_pcs)(struct phylink_config *config,\n+\t\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t\t unsigned int num_possible_pcs);\n };\n \n void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);\n@@ -497,6 +510,9 @@ struct phylink_pcs {\n \tstruct phylink *phylink;\n \tbool poll;\n \tbool rxc_always_on;\n+\n+\t/* private: */\n+\tstruct list_head list;\n };\n \n /**\n@@ -512,6 +528,7 @@ struct phylink_pcs {\n * @pcs_an_restart: restart 802.3z BaseX autonegotiation.\n * @pcs_link_up: program the PCS for the resolved link configuration\n * (where necessary).\n+ * @pcs_link_down: tear down link between MAC and PCS.\n * @pcs_disable_eee: optional notification to PCS that EEE has been disabled\n *\t\t at the MAC.\n * @pcs_enable_eee: optional notification to PCS that EEE will be enabled at\n@@ -539,6 +556,7 @@ struct phylink_pcs_ops {\n \tvoid (*pcs_an_restart)(struct phylink_pcs *pcs);\n \tvoid (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,\n \t\t\t phy_interface_t interface, int speed, int duplex);\n+\tvoid (*pcs_link_down)(struct phylink_pcs *pcs);\n \tvoid (*pcs_disable_eee)(struct phylink_pcs *pcs);\n \tvoid (*pcs_enable_eee)(struct phylink_pcs *pcs);\n \tint (*pcs_pre_init)(struct phylink_pcs *pcs);\n@@ -674,6 +692,16 @@ void pcs_an_restart(struct phylink_pcs *pcs);\n void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,\n \t\t phy_interface_t interface, int speed, int duplex);\n \n+/**\n+ * pcs_link_up() - tear down link between MAC and PCS\n+ * @pcs: a pointer to a \u0026struct phylink_pcs.\n+ *\n+ * This call will be made just after mac_link_down() to inform the PCS the\n+ * link has gone down. PCS should be configured to stop processing packets\n+ * for transmission and reception.\n+ */\n+void pcs_link_down(struct phylink_pcs *pcs);\n+\n /**\n * pcs_disable_eee() - Disable EEE at the PCS\n * @pcs: a pointer to a \u0026struct phylink_pcs\n@@ -735,6 +763,8 @@ void phylink_disconnect_phy(struct phylink *);\n int phylink_set_fixed_link(struct phylink *,\n \t\t\t const struct phylink_link_state *);\n \n+void phylink_release_pcs(struct phylink_pcs *pcs);\n+\n void phylink_mac_change(struct phylink *, bool up);\n void phylink_pcs_change(struct phylink_pcs *, bool up);\n \n"
} |
| 2/1 | 2026/07/17 08:41 | agent | patch-evaluator |
5mModel:gemini-3.1-pro-preview Args: null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch introduces a new PCS subsystem and an Airoha AN7581 PCS driver, and modifies the Airoha ethernet driver to use it. The new PCS subsystem and the modifications to phylink are only used by the Airoha driver. The Airoha driver is a hardware-specific platform driver that requires a specific device tree structure (child nodes, reset lines, syscon) and hardware registers to probe successfully. Therefore, the new code paths are impossible to reach in virtualized environments like GCE or QEMU.",
"WorthFuzzing": false
}Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Do not list too generic configs (we already have them enabled). Only list those that specifically cover the modified code. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes:
commit 4da378eff5f142d2ebbe83411747eb176ed016cd
Author: syz-cluster <triage@syzkaller.com>
Date: Fri Jul 17 08:41:20 2026 +0000
syz-cluster: applied patch under review
diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 00000000000000..9c1d116c1b016d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,261 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+ the various Serdes port supporting different Media Independent Interface
+ (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+ compatible:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+ - airoha,an7581-pcs-pcie
+ - airoha,an7581-pcs-usb
+
+ reg:
+ minItems: 6
+ maxItems: 15
+
+ reg-names:
+ minItems: 6
+ maxItems: 15
+
+ airoha,scu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the SCU node required to configure
+ the serdes line to the correct interface mode.
+
+ phys:
+ maxItems: 1
+
+ "#pcs-cells": true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#pcs-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: USXGMII reg
+ - description: HSGMII rate adaption reg
+ - description: PCS Analog register
+ - description: PCS PMA (Physical Medium Attachment) register
+
+ reg-names:
+ items:
+ - const: pcs_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: usxgmii
+ - const: hsgmii_rate_adp
+ - const: pcs_ana
+ - const: pcs_pma
+
+ phys: false
+
+ "#pcs-cells":
+ const: 0
+
+ required:
+ - airoha,scu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: airoha,an7581-pcs-pcie
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC 0 reg
+ - description: HSGMII AN 0 reg
+ - description: HSGMII PCS 0 reg
+ - description: MULTI SGMII 0 reg
+ - description: USXGMII 0 reg
+ - description: HSGMII rate adaption 0 reg
+ - description: PCS MAC 1 reg
+ - description: HSGMII AN 1 reg
+ - description: HSGMII PCS 1 reg
+ - description: MULTI SGMII 1 reg
+ - description: USXGMII 1 reg
+ - description: HSGMII rate adaption 1 reg
+ - description: PCS Analog register
+ - description: PCS PMA (Physical Medium Attachment) 0 register
+ - description: PCS PMA (Physical Medium Attachment) 1 register
+
+ reg-names:
+ items:
+ - const: pcs_mac0
+ - const: hsgmii_an0
+ - const: hsgmii_pcs0
+ - const: multi_sgmii0
+ - const: usxgmii0
+ - const: hsgmii_rate_adp0
+ - const: pcs_mac1
+ - const: hsgmii_an1
+ - const: hsgmii_pcs1
+ - const: multi_sgmii1
+ - const: usxgmii1
+ - const: hsgmii_rate_adp1
+ - const: pcs_ana
+ - const: pcs_pma0
+ - const: pcs_pma1
+
+ phys: false
+
+ "#pcs-cells":
+ const: 1
+
+ required:
+ - airoha,scu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: airoha,an7581-pcs-usb
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: HSGMII rate adaption reg
+ - description: PCS Analog register
+
+ reg-names:
+ items:
+ - const: pcs_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: hsgmii_rate_adp
+ - const: pcs_ana
+
+ airoha,scu: false
+
+ "#pcs-cells":
+ const: 0
+
+ required:
+ - phys
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ pcs@1fa08000 {
+ compatible = "airoha,an7581-pcs-pon";
+ reg = <0x1fa08000 0x1000>,
+ <0x1fa80000 0x60>,
+ <0x1fa80a00 0x164>,
+ <0x1fa84000 0x450>,
+ <0x1fa85900 0x338>,
+ <0x1fa86000 0x300>,
+ <0x1fa8a000 0x1000>,
+ <0x1fa8b000 0x1000>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "pcs_ana", "pcs_pma";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa09000 {
+ compatible = "airoha,an7581-pcs-eth";
+ reg = <0x1fa09000 0x1000>,
+ <0x1fa70000 0x60>,
+ <0x1fa70a00 0x164>,
+ <0x1fa74000 0x450>,
+ <0x1fa75900 0x338>,
+ <0x1fa76000 0x300>,
+ <0x1fa7a000 0x1000>,
+ <0x1fa7b000 0x1000>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "pcs_ana", "pcs_pma";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa04000 {
+ compatible = "airoha,an7581-pcs-pcie";
+ reg = <0x1fa04000 0x1000>,
+ <0x1fa50000 0x60>,
+ <0x1fa50a00 0x164>,
+ <0x1fa54000 0x450>,
+ <0x1fa55900 0x338>,
+ <0x1fa56000 0x300>,
+ <0x1fa05000 0x1000>,
+ <0x1fa60000 0x60>,
+ <0x1fa60a00 0x164>,
+ <0x1fa64000 0x450>,
+ <0x1fa65900 0x338>,
+ <0x1fa66000 0x300>,
+ <0x1fa5a000 0x1000>,
+ <0x1fa5b000 0x1000>,
+ <0x1fa5c000 0x1000>;
+ reg-names = "pcs_mac0", "hsgmii_an0", "hsgmii_pcs0",
+ "multi_sgmii0", "usxgmii0",
+ "hsgmii_rate_adp0",
+ "pcs_mac1", "hsgmii_an1", "hsgmii_pcs1",
+ "multi_sgmii1", "usxgmii1",
+ "hsgmii_rate_adp1",
+ "pcs_ana", "pcs_pma0", "pcs_pma1";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <1>;
+ };
+
+ pcs@1fa07000 {
+ compatible = "airoha,an7581-pcs-usb";
+ reg = <0x1fa07000 0x1000>,
+ <0x1fa90000 0x60>,
+ <0x1fa90a00 0x164>,
+ <0x1fa94000 0x450>,
+ <0x1fa96000 0x300>,
+ <0x1fa9a000 0x600>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "hsgmii_rate_adp","pcs_ana";
+
+ phys = <&usb0_phy PHY_TYPE_USB3>;
+
+ #pcs-cells = <0>;
+ };
diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst
index 44a422ad3b0553..3fce8f6ac089ee 100644
--- a/Documentation/networking/index.rst
+++ b/Documentation/networking/index.rst
@@ -28,6 +28,7 @@ Contents:
net_failover
page_pool
phy
+ pcs
sfp-phylink
alias
bridge
diff --git a/Documentation/networking/pcs.rst b/Documentation/networking/pcs.rst
new file mode 100644
index 00000000000000..98592cdee3ef20
--- /dev/null
+++ b/Documentation/networking/pcs.rst
@@ -0,0 +1,229 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=============
+PCS Subsystem
+=============
+
+The PCS (Physical Coding Sublayer) subsystem handles the registration and lookup
+of PCS devices. These devices contain the upper sublayers of the Ethernet
+physical layer, generally handling framing, scrambling, and encoding tasks. PCS
+devices may also include PMA (Physical Medium Attachment) components. PCS
+devices transfer data between the Link-layer MAC device, and the rest of the
+physical layer, typically via a serdes. The output of the serdes may be
+connected more-or-less directly to the medium when using fiber-optic or
+backplane connections (1000BASE-SX, 1000BASE-KX, etc). It may also communicate
+with a separate PHY (such as over SGMII) which handles the connection to the
+medium (such as 1000BASE-T).
+
+Remark on usage of .mac_select_pcs and fw_node PCS
+--------------------------------------------------
+
+There are generally two ways to look up a PCS device.
+
+1. MAC OP struct .mac_select_pcs (considered legacy)
+2. firmware node (fwnode) PCS entirely handled by phylink
+
+Implementation 1 leaves the entire handling of the PCS to the MAC
+driver with the selection of the PCS driven by .mac_select_pcs.
+Custom implementations are required if the PCS is external to the MAC
+and needs to be handled by a separate driver.
+
+This implementation is considered legacy and it's suggested to
+switch to the new fwnode PCS.
+
+Looking up PCS Devices (fwnode implementation)
+-----------------------------------------------
+
+The lookup of a PCS device follows the common producer/consumer implementation
+used by similar subsystems with a ``#pcs-cells`` on the producer and a
+``pcs-handle`` property on the consumer::
+
+ pcs: pcs {
+ // ...
+ #pcs-cells = <0>;
+ };
+
+ ethernet-controller {
+ // ...
+ pcs-handle = <&pcs>;
+ };
+
+On :c:func:`phylink_create`, phylink will use the ``num_possible_pcs``
+value and ``fill_available_pcs`` helper function in
+:c:struct:`phylink_config` to compose the list of available PCS that can be
+used for the phylink instance.
+
+Phylink will then internally handle the selection of the correct PCS for
+the requested interface mode based on the interface modes configured in
+``pcs_interfaces`` in :c:struct:`phylink_config` struct and
+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.
+
+A PCS is considered eligible when the requested interface mode is present
+in both ``pcs_interfaces`` in :c:struct:`phylink_config` struct and
+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.
+
+``supported_interfaces`` describes all interface modes supported by the MAC,
+whereas ``pcs_interfaces`` identifies the subset that require PCS selection.
+
+For the special implementation where the PCS is internal or part of the MAC
+and a dedicated driver is not needed, it's possible to leave the implementation
+of the PCS to the MAC driver and just implement the ``num_possible_pcs``
+value and ``fill_available_pcs`` helper function in
+:c:struct:`phylink_config` referencing the local :c:struct:`phylink_pcs`
+struct allocated from the MAC driver.
+
+Using PCS Devices
+-----------------
+
+It's mandatory to either implement the ``mac_select_pcs`` callback
+of :c:struct:`phylink_mac_ops` or ``num_possible_pcs`` and ``fill_available_pcs``
+of :c:struct:`phylink_config` to use a PCS for a MAC.
+
+The fwnode implementation exposes simple helpers to parse the PCS from
+the fwnode :c:func:`fwnode_phylink_pcs_count` and
+:c:func:`fwnode_phylink_pcs_parse`. The :c:func:`fwnode_phylink_pcs_count` helper
+takes the fwnode where the ``pcs-handle`` should be parsed and return the
+number of PCS entries described in the fwnode.
+The :c:func:`fwnode_phylink_pcs_parse` helper takes three arguments,
+the fwnode where the ``pcs-handle`` should be parsed, an allocated array
+of :c:struct:`phylink_pcs` pointer where to put the parsed PCS from the fwnode
+and the maximum number of PCS to parse.
+Contrary to :c:func:`fwnode_phylink_pcs_count`, :c:func:`fwnode_phylink_pcs_parse`
+helper fills the allocated array with ONLY the available PCS and return the
+number of available PCS found. PCS that returns -ENODEV will be skipped and
+won't be inserted in the allocated array.
+
+A phylink instance may use multiple PCS devices. The maximum number is reported
+through ``num_possible_pcs``.
+
+It's mandatory to specify for what interface a PCS is needed. This can be done
+by filling the ``pcs_interfaces`` in :c:struct:`phylink_config` struct.
+If the requested interface mode is not present in this bitmask, phylink does
+not search for a PCS for that specific mode. (example MAC doesn't need a PCS
+for SGMII but require one for USXGMII)
+
+With the use of the :c:func:`fwnode_phylink_pcs_parse` a common implementation
+is the following::
+
+ static int mac_fill_available_pcs(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs)
+ {
+ struct device *dev = config->dev;
+
+ return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
+ num_possible_pcs);
+ }
+
+ static int mac_setup_phylink(struct net_device *netdev)
+ {
+ struct phylink_config *config;
+
+ // ...
+
+ config->dev = &netdev->dev;
+
+ // ...
+
+ // Parse possible PCS and fill num_possible_pcs.
+ config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(&netdev->dev));
+ config->fill_available_pcs = mac_fill_available_pcs;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces);
+
+ // PCS required only for USXGMII
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config->pcs_interfaces);
+
+ phylink = phylink_create(config, //...
+
+It's worth to mention that it's phylink code that takes care of allocating
+the array of :c:struct:`phylink_pcs` pointer for ``fill_available_pcs``
+callback based on the value set in ``num_possible_pcs`` for
+:c:struct:`phylink_config` struct.
+
+The ``fill_available_pcs`` callback must not write more than
+``num_possible_pcs`` entries. The third argument may be used to validate
+that there is enough space to fill all the available PCS in the passed array
+of :c:struct:`phylink_pcs` pointer.
+
+The ``fill_available_pcs`` callback is called only on :c:func:`phylink_create`
+and is used only to compose the initial available PCS list. Ownership of PCS
+is held by phylink and :c:func:`phylink_release_pcs` should be used to release
+them.
+
+Writing PCS Drivers
+-------------------
+
+To write a PCS driver, first implement :c:struct:`phylink_pcs_ops`. Then,
+register your PCS in your probe function using :c:func:`fwnode_pcs_add_provider`.
+The :c:func:`fwnode_pcs_add_provider` takes three arguments, the fwnode where
+the PCS provider should be registered to, a get function to return the requested
+PCS based on ``#pcs-cells`` and a pointer to reference private data for the get
+function.
+
+The PCS will then be registered to a global list of PCS provider that the
+PCS fwnode implementation will use to parse it.
+
+For the simple case where the PCS driver expose a single PCS,
+:c:func:`fwnode_pcs_simple_get` can be used as the get function.
+
+You must call :c:func:`fwnode_pcs_del_provider` from your remove function and
+release the PCS from any phylink instance under RTNL lock with
+:c:func:`phylink_release_pcs`::
+
+ fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+ rtnl_lock();
+
+ for (i = 0; i < data->num_port; i++) {
+ struct pcs_port *port = &priv->ports[i];
+
+ phylink_release_pcs(&port->pcs);
+ }
+
+ rtnl_unlock();
+
+Late PCS registration handling
+------------------------------
+
+It's possible that a PCS becomes available after the MAC finished probing.
+Contrary to the usual producer/consumer implementation, when a PCS is not
+registered and can't be found, the fwnode parser helper returns ``-ENODEV``
+instead of ``-EPROBE_DEFER``.
+
+This is to prevent race condition with particular devices that register
+MAC and PCS with USB or PCIe and require the MAC to be registered before
+the PCS.
+
+The phylink logic correctly handle this special case and keep the phylink
+instance in a fail condition.
+
+The PCS fwnode implementation provides a notifier to which each phylink
+instance with a non-empty ``pcs_interfaces`` in :c:type:`phylink_config`
+registers. When a new PCS provider is registered, the notifier is called
+triggering the :c:func:`pcs_provider_notify` function.
+
+Function :c:func:`pcs_provider_notify` will check if the just added PCS
+should be used by the phylink instance. If it should be used then,
+it's added to the internal list of available PCS and a phylink major
+config is forced.
+
+If a phylink instance was in a failure state, with the just added PCS
+now part of the available PCS internal phylink list, provided all other
+conditions are satisfied, the configuration is retried and the failure
+condition is cleared.
+
+API Reference
+-------------
+
+.. kernel-doc:: include/linux/phylink.h
+ :identifiers: phylink_pcs
+
+.. kernel-doc:: include/linux/pcs/pcs.h
+ :internal:
+
+.. kernel-doc:: include/linux/pcs/pcs-provider.h
+ :internal:
diff --git a/MAINTAINERS b/MAINTAINERS
index f3218abefd0c6b..51704a90ca4683 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9682,6 +9682,15 @@ F: include/uapi/linux/if_bridge.h
F: include/linux/netfilter_bridge/
F: net/bridge/
+ETHERNET PCS SUBSYSTEM
+M: Christian Marangi <ansuelsmth@gmail.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/networking/pcs.rst
+F: drivers/net/pcs/pcs.c
+F: include/linux/pcs/pcs-provider.h
+F: include/linux/pcs/pcs.h
+
ETHERNET PHY LIBRARY
M: Andrew Lunn <andrew@lunn.ch>
M: Heiner Kallweit <hkallweit1@gmail.com>
diff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig
index 1f6640a15fc947..789906516bf8fb 100644
--- a/drivers/net/ethernet/airoha/Kconfig
+++ b/drivers/net/ethernet/airoha/Kconfig
@@ -20,6 +20,7 @@ config NET_AIROHA
depends on NET_DSA || !NET_DSA
select NET_AIROHA_NPU
select PAGE_POOL
+ select PHYLINK
help
This driver supports the gigabit ethernet MACs in the
Airoha SoC family.
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 59001fd4b6f740..ed1ac032f33747 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -8,6 +8,7 @@
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/tcp.h>
+#include <linux/pcs/pcs.h>
#include <linux/u64_stats_sync.h>
#include <net/dst_metadata.h>
#include <net/page_pool/helpers.h>
@@ -1837,7 +1838,7 @@ static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)
struct airoha_gdm_port *port = dev->port;
int i;
- spin_lock(&port->stats_lock);
+ spin_lock(&port->lock);
for (i = 0; i < ARRAY_SIZE(port->devs); i++) {
if (port->devs[i])
@@ -1848,7 +1849,7 @@ static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)
airoha_fe_set(dev->eth, REG_FE_GDM_MIB_CLEAR(port->id),
FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK);
- spin_unlock(&port->stats_lock);
+ spin_unlock(&port->lock);
}
static void airoha_dev_set_xmit_frame_size(struct net_device *netdev)
@@ -1870,6 +1871,14 @@ static int airoha_dev_open(struct net_device *netdev)
u32 pse_port = FE_PSE_PORT_PPE1;
int err;
+ err = phylink_of_phy_connect(dev->phylink, netdev->dev.of_node, 0);
+ if (err) {
+ netdev_err(netdev, "could not attach PHY: %d\n", err);
+ return err;
+ }
+
+ phylink_start(dev->phylink);
+
netif_tx_start_all_queues(netdev);
err = airoha_set_vip_for_gdm_port(dev, true);
if (err)
@@ -1909,6 +1918,10 @@ static int airoha_dev_stop(struct net_device *netdev)
airoha_set_gdm_port_fwd_cfg(qdma->eth,
REG_GDM_FWD_CFG(port->id),
FE_PSE_PORT_DROP);
+
+ phylink_stop(dev->phylink);
+ phylink_disconnect_phy(dev->phylink);
+
return 0;
}
@@ -2389,6 +2402,24 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,
} while (u64_stats_fetch_retry(&dev->stats.syncp, start));
}
+static int
+airoha_ethtool_get_link_ksettings(struct net_device *netdev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ return phylink_ethtool_ksettings_get(dev->phylink, cmd);
+}
+
+static int
+airoha_ethtool_set_link_ksettings(struct net_device *netdev,
+ const struct ethtool_link_ksettings *cmd)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ return phylink_ethtool_ksettings_set(dev->phylink, cmd);
+}
+
static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev,
int channel, enum tx_sched_mode mode,
const u16 *weights, u8 n_weights)
@@ -3120,7 +3151,8 @@ static const struct ethtool_ops airoha_ethtool_ops = {
.get_drvinfo = airoha_ethtool_get_drvinfo,
.get_eth_mac_stats = airoha_ethtool_get_mac_stats,
.get_rmon_stats = airoha_ethtool_get_rmon_stats,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .get_link_ksettings = airoha_ethtool_get_link_ksettings,
+ .set_link_ksettings = airoha_ethtool_set_link_ksettings,
.get_link = ethtool_op_get_link,
};
@@ -3176,6 +3208,155 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
return false;
}
+/* Nothing to do in MAC, everything is handled in PCS */
+static void airoha_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+}
+
+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
+ unsigned int mode, phy_interface_t interface,
+ int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+ struct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev,
+ phylink_config);
+ struct airoha_gdm_port *port = dev->port;
+ struct airoha_eth *eth = dev->eth;
+ u32 frag_size_tx, frag_size_rx;
+ u32 mask, val;
+
+ /* TX/RX frag is configured only for GDM4 */
+ if (port->id != AIROHA_GDM4_IDX)
+ return;
+
+ switch (speed) {
+ case SPEED_10000:
+ case SPEED_5000:
+ frag_size_tx = 8;
+ frag_size_rx = 8;
+ break;
+ case SPEED_2500:
+ frag_size_tx = 2;
+ frag_size_rx = 1;
+ break;
+ default:
+ frag_size_tx = 1;
+ frag_size_rx = 0;
+ }
+
+ spin_lock(&port->lock);
+
+ /* Configure TX/RX frag based on speed */
+ if (dev->nbq == 1) {
+ mask = GDM4_SGMII1_TX_FRAG_SIZE_MASK;
+ val = FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK,
+ frag_size_tx);
+ } else {
+ mask = GDM4_SGMII0_TX_FRAG_SIZE_MASK;
+ val = FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK,
+ frag_size_tx);
+ }
+ airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG, mask, val);
+
+ if (dev->nbq == 1) {
+ mask = GDM4_SGMII1_RX_FRAG_SIZE_MASK;
+ val = FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK,
+ frag_size_rx);
+ } else {
+ mask = GDM4_SGMII0_RX_FRAG_SIZE_MASK;
+ val = FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK,
+ frag_size_rx);
+ }
+ airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG, mask, val);
+
+ spin_unlock(&port->lock);
+}
+
+/* Nothing to do in MAC, everything is handled in PCS */
+static void airoha_mac_link_down(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+}
+
+static const struct phylink_mac_ops airoha_phylink_ops = {
+ .mac_config = airoha_mac_config,
+ .mac_link_up = airoha_mac_link_up,
+ .mac_link_down = airoha_mac_link_down,
+};
+
+static int airoha_fill_available_pcs(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs)
+{
+ struct device *dev = config->dev;
+
+ return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
+ num_possible_pcs);
+}
+
+static int airoha_setup_phylink(struct net_device *netdev)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+ struct device_node *np = netdev->dev.of_node;
+ struct airoha_gdm_port *port = dev->port;
+ struct phylink_config *config;
+ phy_interface_t phy_mode;
+ struct phylink *phylink;
+ int err;
+
+ err = of_get_phy_mode(np, &phy_mode);
+ if (err) {
+ dev_err(&netdev->dev, "incorrect phy-mode\n");
+ return err;
+ }
+
+ config = &dev->phylink_config;
+ config->dev = &netdev->dev;
+ config->type = PHYLINK_NETDEV;
+
+ /*
+ * GDM1 only supports internal for Embedded Switch
+ * and doesn't require a PCS.
+ */
+ if (port->id == AIROHA_GDM1_IDX) {
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10000FD;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ } else {
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000 |
+ MAC_2500FD | MAC_5000FD | MAC_10000FD;
+
+ config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config->dev));
+ config->fill_available_pcs = airoha_fill_available_pcs;
+
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ config->supported_interfaces);
+
+ phy_interface_copy(config->pcs_interfaces,
+ config->supported_interfaces);
+ }
+
+ phylink = phylink_create(config, of_fwnode_handle(np),
+ phy_mode, &airoha_phylink_ops);
+ if (IS_ERR(phylink))
+ return PTR_ERR(phylink);
+
+ dev->phylink = phylink;
+
+ return 0;
+}
+
static int airoha_alloc_gdm_device(struct airoha_eth *eth,
struct airoha_gdm_port *port,
int nbq, struct device_node *np)
@@ -3239,7 +3420,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
dev->nbq = nbq;
port->devs[index] = dev;
- return 0;
+ return airoha_setup_phylink(netdev);
}
static int airoha_alloc_gdm_port(struct airoha_eth *eth,
@@ -3274,7 +3455,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
return -ENOMEM;
port->id = id;
- spin_lock_init(&port->stats_lock);
+ spin_lock_init(&port->lock);
eth->ports[p] = port;
err = airoha_metadata_dst_alloc(port);
@@ -3471,6 +3652,8 @@ static int airoha_probe(struct platform_device *pdev)
netdev = netdev_from_priv(dev);
if (netdev->reg_state == NETREG_REGISTERED)
unregister_netdev(netdev);
+ if (dev->phylink)
+ phylink_destroy(dev->phylink);
of_node_put(netdev->dev.of_node);
}
airoha_metadata_dst_free(port);
@@ -3509,6 +3692,7 @@ static void airoha_remove(struct platform_device *pdev)
netdev = netdev_from_priv(dev);
unregister_netdev(netdev);
+ phylink_destroy(dev->phylink);
of_node_put(netdev->dev.of_node);
}
airoha_metadata_dst_free(port);
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index f6d01a8e8da139..b49fc5304b3aaf 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -561,6 +561,9 @@ struct airoha_gdm_dev {
int nbq;
struct airoha_hw_stats stats;
+
+ struct phylink *phylink;
+ struct phylink_config phylink_config;
};
struct airoha_gdm_port {
@@ -568,8 +571,8 @@ struct airoha_gdm_port {
int id;
int users;
- /* protect concurrent hw_stats accesses */
- spinlock_t stats_lock;
+ /* protect concurrent hw_stats and frag register accesses */
+ spinlock_t lock;
struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
};
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index 6fed63d013b412..8df02f51211c48 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -357,6 +357,18 @@
#define IP_FRAGMENT_PORT_MASK GENMASK(8, 5)
#define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0)
+#define REG_FE_GDM4_TMBI_FRAG 0x2028
+#define GDM4_SGMII1_TX_WEIGHT_MASK GENMASK(31, 26)
+#define GDM4_SGMII1_TX_FRAG_SIZE_MASK GENMASK(25, 16)
+#define GDM4_SGMII0_TX_WEIGHT_MASK GENMASK(15, 10)
+#define GDM4_SGMII0_TX_FRAG_SIZE_MASK GENMASK(9, 0)
+
+#define REG_FE_GDM4_RMBI_FRAG 0x202c
+#define GDM4_SGMII1_RX_WEIGHT_MASK GENMASK(31, 26)
+#define GDM4_SGMII1_RX_FRAG_SIZE_MASK GENMASK(25, 16)
+#define GDM4_SGMII0_RX_WEIGHT_MASK GENMASK(15, 10)
+#define GDM4_SGMII0_RX_FRAG_SIZE_MASK GENMASK(9, 0)
+
#define REG_MC_VLAN_EN 0x2100
#define MC_VLAN_EN_MASK BIT(0)
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index e417fd66f660ad..10ac9af045940a 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,12 @@
menu "PCS device drivers"
+config FWNODE_PCS
+ bool "PCS Firmware Node"
+ depends on (ACPI || OF)
+ help
+ Firmware node PCS accessors
+
config PCS_XPCS
tristate "Synopsys DesignWare Ethernet XPCS"
select PHYLINK
@@ -35,4 +41,6 @@ config PCS_RZN1_MIIC
Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to
RMII/RGMII, or can be set in pass-through mode for MII.
+source "drivers/net/pcs/airoha/Kconfig"
+
endmenu
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b9005..91593aa8d92664 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for Linux PCS drivers
+obj-$(CONFIG_FWNODE_PCS) += pcs.o
pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
pcs-xpcs-nxp.o pcs-xpcs-wx.o
@@ -8,3 +9,5 @@ obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o
obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
+
+obj-$(CONFIG_PCS_AIROHA) += airoha/
diff --git a/drivers/net/pcs/airoha/Kconfig b/drivers/net/pcs/airoha/Kconfig
new file mode 100644
index 00000000000000..4ddd527b365fd7
--- /dev/null
+++ b/drivers/net/pcs/airoha/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PCS_AIROHA
+ tristate
+ select FWNODE_PCS
+
+config PCS_AIROHA_AN7581
+ tristate "Airoha AN7581 PCS driver"
+ select PCS_AIROHA
+ help
+ This module provides helper to phylink for managing the Airoha
+ AN7581 PCS for SoC Ethernet and PON SERDES.
diff --git a/drivers/net/pcs/airoha/Makefile b/drivers/net/pcs/airoha/Makefile
new file mode 100644
index 00000000000000..c5201d5cc3569e
--- /dev/null
+++ b/drivers/net/pcs/airoha/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PCS_AIROHA) := pcs-airoha.o
+pcs-airoha-objs := pcs-airoha-common.o
+ifdef CONFIG_PCS_AIROHA_AN7581
+pcs-airoha-objs += pcs-an7581.o
+endif
diff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c
new file mode 100644
index 00000000000000..781f89adf3abfa
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c
@@ -0,0 +1,1324 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/rtnetlink.h>
+
+#include "pcs-airoha.h"
+
+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
+ AIROHA_SCU_ETH_XSI_SEL,
+ xsi_sel);
+}
+
+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel, wan_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PON_XSI_SEL,
+ xsi_sel);
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+ AIROHA_SCU_WAN_SEL,
+ wan_sel);
+}
+
+static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ if (index == 0) {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_PCIE_XSI0_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI0_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI0_SEL,
+ xsi_sel);
+ } else {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI1_SEL,
+ xsi_sel);
+ }
+}
+
+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ int ret;
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ airoha_pcs_setup_scu_eth(priv, interface);
+ break;
+ case AIROHA_PCS_PON:
+ airoha_pcs_setup_scu_pon(priv, interface);
+ break;
+ case AIROHA_PCS_PCIE:
+ airoha_pcs_setup_scu_pcie(priv, index, interface);
+ break;
+ case AIROHA_PCS_USB:
+ break;
+ }
+
+ /* TODO better handle reset from MAC */
+ ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_set_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ /* Disable Hibernation */
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+ AIROHA_PCS_USXGMII_SPEED_SEL_H);
+
+ /* FIXME: wait Airoha */
+ /* Avoid PCS sending garbage to MAC in some HW revision (E0) */
+ regmap_write(maps->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+}
+
+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE,
+ priv->phy ? 0 : AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
+
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
+}
+
+static void airoha_pcs_init(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_init_sgmii(priv, index);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_init_hsgmii(priv, index);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_init_usxgmii(priv, index);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ /* Disable every interrupt */
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+ /* Clear interrupt */
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+}
+
+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ /* Disable every Interrupt */
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
+ AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
+ AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
+ AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
+
+ /* Clear any pending interrupt */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT);
+
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT);
+
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
+
+ /* Interrupt saddly seems to be not weel supported for Link Down.
+ * PCS Poll is a must to correctly read and react on Cable Deatch
+ * as only cable attach interrupt are fired and Link Down interrupt
+ * are fired only in special case like AN restart.
+ */
+}
+
+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return airoha_pcs_interrupt_init_sgmii(priv, index);
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ return airoha_pcs_interrupt_init_usxgmii(priv, index);
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
+ unsigned int neg_mode, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr, lpa;
+
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
+ &lpa);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+ lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
+ phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_hsgmii(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr;
+
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+
+ state->link = !!(bmsr & BMSR_LSTATUS);
+ state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
+ state->speed = SPEED_2500;
+ state->duplex = DUPLEX_FULL;
+}
+
+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 an_done, lpa;
+
+ /* Trigger HW workaround if needed. If an error is reported,
+ * consider link down and test again later.
+ */
+ if (data->rxlock_workaround && data->rxlock_workaround(priv, index)) {
+ state->link = false;
+ return;
+ }
+
+ /* Toggle AN Status */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_2, &an_done);
+
+ state->link = !!(lpa & MDIO_USXGMII_LINK);
+ state->an_complete = !!(an_done & AIROHA_PCS_USXGMII_PCS_AN_COMPLETE);
+
+ phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void airoha_pcs_get_state_10gbaser(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 status, curr_mode;
+
+ /* Toggle AN Status */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1,
+ &status);
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &curr_mode);
+
+ state->link = !!(status & AIROHA_PCS_USXGMII_RX_LINK_STUS);
+
+ switch (curr_mode & AIROHA_PCS_USXGMII_CUR_USXGMII_MODE) {
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G:
+ state->speed = SPEED_10000;
+ break;
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G:
+ state->speed = SPEED_5000;
+ break;
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G:
+ state->speed = SPEED_2500;
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ return;
+ }
+
+ state->duplex = DUPLEX_FULL;
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
+ unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_get_state_sgmii(priv, neg_mode, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_get_state_hsgmii(priv, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ airoha_pcs_get_state_usxgmii(priv, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_get_state_10gbaser(priv, port->index, state);
+ break;
+ default:
+ return;
+ }
+}
+
+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ const struct airoha_pcs_match_data *data;
+ struct airoha_pcs_maps *maps;
+ int index = port->index;
+ u32 rate_adapt;
+ int ret;
+
+ maps = &priv->maps[port->index];
+ port->interface = interface;
+ data = priv->data;
+
+ /* Apply Analog and Digital configuration for PCS */
+ if (data->bringup) {
+ ret = data->bringup(priv, index, interface);
+ if (ret)
+ return ret;
+ }
+
+ /* Set final configuration for various modes */
+ airoha_pcs_init(priv, index, interface);
+
+ /* Configure Interrupt for various modes */
+ airoha_pcs_interrupt_init(priv, index, interface);
+
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ rate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS;
+
+ /* AN Auto Settings (Rate Adaptation) */
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+ else
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
+ } else {
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
+ }
+ }
+
+ /* Clear any force bit that my be set by bootloader */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0 |
+ AIROHA_PCS_FORCE_LINKDOWN_P0 |
+ AIROHA_PCS_FORCE_LINKUP_P0);
+ }
+
+ /* Toggle Rate Adaption for SGMII/HSGMII mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_clear_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ else
+ regmap_set_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ }
+
+ /* Setup AN Link Timer */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 an_timer;
+
+ an_timer = phylink_get_link_timer_ns(interface);
+
+ /* Value needs to be shifted by 4, seems value is internally * 16 */
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ an_timer >> 4));
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
+ AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ an_timer >> 4));
+ }
+
+ /* Setup SGMII AN and advertisement in DEV_ABILITY */
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+ advertising);
+ if (advertise < 0)
+ return advertise;
+
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
+ AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ advertise));
+
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ } else {
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ }
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
+
+ /* Toggle SGMII or 1000base-x mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN;
+
+ if (neg_mode & PHYLINK_PCS_NEG_INBAND)
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+ else
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* Clear force speed bits and MAC mode */
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ } else {
+ /* Enable compatibility with MAC PCS Layer */
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
+
+ /* AN off force rate adaption, speed is set later in Link Up */
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ }
+
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
+ AIROHA_PCS_HSGMII_PCS_MODE2_EN);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_1000BASEX &&
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
+ AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY);
+ }
+
+ /* Configure Flow Control on XFI */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
+ permit_pause_to_mac ?
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
+ 0);
+
+ return 0;
+}
+
+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ switch (port->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface, int speed, int duplex)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ const struct airoha_pcs_match_data *data;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+ data = priv->data;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
+ udelay(1);
+ regmap_update_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
+ }
+ } else {
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ u32 mode;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_10000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
+ mode = AIROHA_PCS_USXGMII_MODE_10000;
+ break;
+ case SPEED_5000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
+ mode = AIROHA_PCS_USXGMII_MODE_5000;
+ break;
+ case SPEED_2500:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
+ mode = AIROHA_PCS_USXGMII_MODE_2500;
+ break;
+ case SPEED_1000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
+ mode = AIROHA_PCS_USXGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
+ mode = AIROHA_PCS_USXGMII_MODE_100;
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ /* Force USXGMII to selected speed */
+ regmap_update_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_MODE, mode);
+
+ if (interface == PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 force_speed;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_1000:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
+ break;
+ case SPEED_100:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
+ break;
+ case SPEED_10:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
+ force_speed | rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ u32 ck_gen_mode;
+ u32 speed_reg;
+ u32 if_mode;
+
+ switch (speed) {
+ case SPEED_2500:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
+ break;
+ case SPEED_1000:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
+ break;
+ case SPEED_10:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
+ break;
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
+ if_mode);
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
+ ck_gen_mode |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
+ }
+
+ regmap_update_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0,
+ speed_reg |
+ AIROHA_PCS_FORCE_SPD_MODE_P0);
+ }
+ }
+
+ if (data->link_up)
+ data->link_up(priv, port->index);
+
+ /* BPI BMI enable */
+ regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_link_down(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* MPI MBI disable */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* Select HSGMII or USXGMII in SCU regs */
+ airoha_pcs_setup_scu(priv, port->index, interface);
+
+ /* MPI MBI disable */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+
+ /* Write 1 to trigger reset and clear */
+ regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+ AIROHA_PCS_XFI_MAC_LOGIC_RST);
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+ AIROHA_PCS_XFI_MAC_LOGIC_RST);
+
+ usleep_range(1000, 2000);
+
+ /* Clear XFI MAC counter */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,
+ AIROHA_PCS_XFI_GLB_CNT_CLR);
+}
+
+static int airoha_pcs_post_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* Frag disable */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RX_FRAG_LEN,
+ FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31));
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FRAG_LEN,
+ FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31));
+
+ /* IPG NUM */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_IPG_NUM,
+ FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10));
+
+ /* Enable TX/RX flow control */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FC_EN);
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RX_FC_EN);
+
+ return 0;
+}
+
+static unsigned int airoha_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
+}
+
+static const struct phylink_pcs_ops airoha_pcs_ops = {
+ .pcs_inband_caps = airoha_pcs_inband_caps,
+ .pcs_pre_config = airoha_pcs_pre_config,
+ .pcs_post_config = airoha_pcs_post_config,
+ .pcs_get_state = airoha_pcs_get_state,
+ .pcs_config = airoha_pcs_config,
+ .pcs_an_restart = airoha_pcs_an_restart,
+ .pcs_link_up = airoha_pcs_link_up,
+ .pcs_link_down = airoha_pcs_link_down,
+};
+
+static int airoha_pcs_init_named_regmap(struct platform_device *pdev,
+ const char *name, struct regmap **regmap)
+{
+ struct regmap_config config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ };
+ void *base;
+
+ base = devm_platform_ioremap_resource_byname(pdev, name);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ config.name = name;
+ *regmap = devm_regmap_init_mmio(&pdev->dev, base, &config);
+
+ return PTR_ERR_OR_ZERO(*regmap);
+}
+
+static int airoha_pcs_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[0];
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii", &maps->usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static int airoha_pcs_usb_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[0];
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sgmii);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = priv->maps;
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac0", &maps[0].pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an0", &maps[0].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs0", &maps[0].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp0", &maps[0].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii0", &maps[0].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii0", &maps[0].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac1", &maps[1].pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an1", &maps[1].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs1", &maps[1].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp1", &maps[1].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii1", &maps[1].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii1", &maps[1].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma0", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma1", &priv->pcs_pma[1]);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static struct phylink_pcs *airoha_pcs_get(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ struct airoha_pcs_priv *priv = data;
+ struct device *dev = priv->dev;
+ u64 index = 0;
+
+ switch (priv->data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ case AIROHA_PCS_USB:
+ if (pcsspec->nargs) {
+ dev_err(dev, "invalid number of cells in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ break;
+ case AIROHA_PCS_PCIE:
+ if (pcsspec->nargs != 1) {
+ dev_err(dev, "invalid number of cells in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ break;
+ }
+
+ if (pcsspec->nargs)
+ index = pcsspec->args[0];
+
+ if (index >= priv->data->num_port) {
+ dev_err(dev, "invalid index cell in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &priv->ports[index].pcs;
+}
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+ const struct airoha_pcs_match_data *data;
+ struct device *dev = &pdev->dev;
+ struct airoha_pcs_priv *priv;
+ int index, ret;
+
+ data = of_device_get_match_data(dev);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->ports = devm_kcalloc(dev, data->num_port,
+ sizeof(*priv->ports), GFP_KERNEL);
+ if (!priv->ports)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->data = data;
+
+ if (data->port_type == AIROHA_PCS_USB) {
+ struct phy *phy;
+
+ phy = devm_phy_get(dev, NULL);
+ if (IS_ERR(phy))
+ return dev_err_probe(dev, PTR_ERR(phy), "failed to get phy\n");
+
+ priv->phy = phy;
+ }
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ ret = airoha_pcs_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ case AIROHA_PCS_PCIE:
+ ret = airoha_pcs_pcie_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ case AIROHA_PCS_USB:
+ ret = airoha_pcs_usb_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ }
+
+ if (data->alloc_regmap_fields) {
+ ret = data->alloc_regmap_fields(priv);
+ if (ret)
+ return ret;
+ }
+
+ /* SCU is used to toggle XFI or HSGMII in global SoC registers */
+ if (!priv->phy) {
+ priv->scu = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu");
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+ }
+
+ priv->rsts[0].id = "mac";
+ priv->rsts[1].id = "phy";
+ ret = devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
+ /* For Ethernet PCS, read the AN7581 SoC revision to check if
+ * manual rx calibration is needed. This is only limited to
+ * any SoC revision before E2.
+ */
+ if (device_is_compatible(dev, "airoha,an7581-pcs-eth")) {
+ u32 val;
+
+ ret = regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val);
+ if (ret)
+ return ret;
+
+ if (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) < 0x2)
+ priv->manual_rx_calib = true;
+ }
+
+ for (index = 0; index < data->num_port; index++) {
+ struct airoha_pcs_port *port = &priv->ports[index];
+
+ port->priv = priv;
+ port->index = index;
+ port->pcs.poll = true;
+ port->pcs.ops = &airoha_pcs_ops;
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ case AIROHA_PCS_PCIE:
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ port->pcs.supported_interfaces);
+ fallthrough;
+ case AIROHA_PCS_USB:
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ port->pcs.supported_interfaces);
+ break;
+ }
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ return fwnode_pcs_add_provider(dev_fwnode(dev), airoha_pcs_get, priv);
+}
+
+static void airoha_pcs_remove(struct platform_device *pdev)
+{
+ struct airoha_pcs_priv *priv = platform_get_drvdata(pdev);
+ const struct airoha_pcs_match_data *data = priv->data;
+ int i;
+
+ fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+ rtnl_lock();
+
+ for (i = 0; i < data->num_port; i++) {
+ struct airoha_pcs_port *port = &priv->ports[i];
+
+ phylink_release_pcs(&port->pcs);
+ }
+
+ rtnl_unlock();
+}
+
+static const struct airoha_pcs_match_data an7581_pcs_eth = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_ETH,
+ .alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+ .rxlock_workaround = an7581_pcs_rxlock_workaround,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pon = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_PON,
+ .alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pcie = {
+ .num_port = 2,
+ .port_type = AIROHA_PCS_PCIE,
+ .alloc_regmap_fields = an7581_pcs_pcie_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_usb = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_USB,
+ .bringup = an7581_pcs_usb_bringup,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+ { .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+ { .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+ { .compatible = "airoha,an7581-pcs-pcie", .data = &an7581_pcs_pcie },
+ { .compatible = "airoha,an7581-pcs-usb", .data = &an7581_pcs_usb },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
+
+static struct platform_driver airoha_pcs_driver = {
+ .driver = {
+ .name = "airoha-pcs",
+ .of_match_table = airoha_pcs_of_table,
+ },
+ .probe = airoha_pcs_probe,
+ .remove = airoha_pcs_remove,
+};
+module_platform_driver(airoha_pcs_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Airoha PCS driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
diff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h
new file mode 100644
index 00000000000000..8a76d51b5d2c8e
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha.h
@@ -0,0 +1,1311 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* SCU*/
+#define AIROHA_SCU_PDIDR 0x5c
+#define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0)
+#define AIROHA_SCU_WAN_CONF 0x70
+#define AIROHA_SCU_WAN_SEL GENMASK(7, 0)
+#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
+#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
+#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
+#define AIROHA_SCU_SSR3 0x94
+#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13)
+#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
+#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
+#define AIROHA_SCU_SSTR 0x9c
+#define AIROHA_SCU_PCIE_XSI0_SEL GENMASK(14, 13)
+#define AIROHA_SCU_PCIE_XSI0_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x1)
+#define AIROHA_SCU_PCIE_XSI0_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x2)
+#define AIROHA_SCU_PCIE_XSI1_SEL GENMASK(12, 11)
+#define AIROHA_SCU_PCIE_XSI1_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x1)
+#define AIROHA_SCU_PCIE_XSI1_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x2)
+#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9)
+#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
+#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
+
+/* XFI_MAC */
+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0
+#define AIROHA_PCS_XFI_RX_FRAG_LEN GENMASK(26, 22)
+#define AIROHA_PCS_XFI_TX_FRAG_LEN GENMASK(21, 17)
+#define AIROHA_PCS_XFI_IPG_NUM GENMASK(15, 10)
+#define AIROHA_PCS_XFI_TX_FC_EN BIT(5)
+#define AIROHA_PCS_XFI_RX_FC_EN BIT(4)
+#define AIROHA_PCS_XFI_RXMPI_STOP BIT(3)
+#define AIROHA_PCS_XFI_RXMBI_STOP BIT(2)
+#define AIROHA_PCS_XFI_TXMPI_STOP BIT(1)
+#define AIROHA_PCS_XFI_TXMBI_STOP BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST 0x10
+#define AIROHA_PCS_XFI_MAC_LOGIC_RST BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH 0x60
+#define AIROHA_PCS_XFI_MAC_MACADDRH GENMASK(15, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL 0x64
+#define AIROHA_PCS_XFI_MAC_MACADDRL GENMASK(31, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR 0x100
+#define AIROHA_PCS_XFI_GLB_CNT_CLR BIT(0)
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0
+#define AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY BIT(15)
+#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */
+#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10
+#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */
+#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
+#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1)
+#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
+#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0)
+
+/* HSGMII_PCS */
+#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_TBI_10B_MODE BIT(30)
+#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24)
+#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8
+#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8)
+#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
+#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104
+#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5)
+#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c
+#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0)
+
+/* HSGMII_ANA */
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6 0x18
+#define AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC BIT(20)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8 0x20
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR GENMASK(11, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 GENMASK(7, 4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0 GENMASK(3, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11 0x2c
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_MODE GENMASK(1, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18 0x48
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV GENMASK(28, 27)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19 0x4c
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV GENMASK(15, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_LV GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG GENMASK(2, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_GND FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONFBK_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONREF_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x3)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_CKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_FBCKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x5)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_TX2500M_A FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_CDR_250M_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x7)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24 0x60
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE GENMASK(31, 24)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26 0x68
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY GENMASK(7, 6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x3)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14
+#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
+#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4)
+#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
+#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
+#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
+#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
+#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2)
+#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1)
+#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28)
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c
+#define AIROHA_PCS_HSGMII_PCS_INT BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c
+#define AIROHA_PCS_LINK_STS_P0 BIT(3)
+#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0)
+#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
+#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
+#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448
+#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2)
+#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1)
+#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0)
+
+/* HSGMII_RATE_ADP */
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31)
+
+/* USXGMII */
+#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13)
+#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x4
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP \
+ FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x1)
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_DOWN \
+ FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x0)
+#define AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1 0x30
+#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12)
+#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
+#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0)
+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c
+#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0
+#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4
+#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8
+#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8)
+#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
+#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318
+#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c
+#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320
+#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12)
+#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8)
+#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)
+
+/* PMA_PHYA */
+#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0
+#define AIROHA_PCS_ANA_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 0x1
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 0x2
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 0x3
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 0x4
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 0x5
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 0x6
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 0x1
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 0x2
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 0x3
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 0x4
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17)
+#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
+#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8)
+#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38
+#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16)
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48
+#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO BIT(5)
+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50
+#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54
+#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64
+#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 0x0
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 0x1
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 0x2
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68
+#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 0x2
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 0x4
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74
+#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c
+#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84
+#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94
+#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4
+#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4
+#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8
+#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
+#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8
+#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4
+#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8
+#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
+#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c
+#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24)
+#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19)
+#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2)
+#define AIROHA_PCS_ANA_CDR_PR_MONPI_EN BIT(1)
+#define AIROHA_PCS_ANA_CDR_PR_MONPR_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110
+#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114
+#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8)
+#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c
+#define AIROHA_PCS_ANA_RX_FE_VCM_GEN_PWDB BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c
+#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
+#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148
+#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYA 2L */
+#define AIROHA_PCS_ANA_PXP_2L_CMN_EN 0x0
+#define AIROHA_PCS_ANA_2L_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_2L_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_20_25 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_40_50 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_80_100 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_150_200 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_300_400 0x5
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_600_800 0x6
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_4 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_6 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_8 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_10 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN 0x38
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1 0x3c
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD 0x40
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN 0x4c
+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L GENMASK(31, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF 0x50
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN 0x54
+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IBIAS GENMASK(29, 24)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST 0x58
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BP GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IOFST GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR 0x5c
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_CODE GENMASK(31, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_OPTION BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV 0x60
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KF GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KFC GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_DIV GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN 0x64
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_POSTDIV_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN 0x68
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_INTERNAL BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV 0x6c
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_PLL_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_RST_DLY GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_1 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_2 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_3 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_4 0x3
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS 0x70
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_IFM BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT 0x74
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2_5 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_3 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_4 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_6 0x4
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_HREN BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_OUT BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF 0x78
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW 0x7c
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_HALFLSB_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_CFIX GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW GENMASK(2, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR 0x80
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_TCLVAR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_SCAPWR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN 0x84
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1 0x88
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD 0x8c
+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF 0x9c
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN 0xcc
+#define AIROHA_PCS_ANA_2L_TX0_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TX0_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN 0xe8
+#define AIROHA_PCS_ANA_2L_TX1_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TX1_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL 0xf4
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_2L_RX0_REV_0 0xfc
+#define AIROHA_PCS_ANA_2L_RX0_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV 0x100
+#define AIROHA_PCS_ANA_2L_RX0_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV 0x104
+#define AIROHA_PCS_ANA_2L_CDR0_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO 0x110
+#define AIROHA_PCS_ANA_2L_CDR0_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE 0x11c
+#define AIROHA_PCS_ANA_2L_CDR0_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC 0x120
+#define AIROHA_PCS_ANA_2L_CDR0_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL 0x124
+#define AIROHA_PCS_ANA_2L_CDR0_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN 0x130
+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPR_EN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN 0x134
+#define AIROHA_PCS_ANA_2L_CDR0_PR_XFICK_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR 0x138
+#define AIROHA_PCS_ANA_2L_CDR0_PR_CAP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BUF_IN_SR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON 0x13c
+#define AIROHA_PCS_ANA_2L_RX0_DAC_MON GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN 0x140
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_PEAK GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_LPF_CTRL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL 0x144
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ1_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_FE_EQ_HZEN BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_VTH_SEL GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN 0x148
+#define AIROHA_PCS_ANA_2L_RX0_FE_VCM_GEN_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ3_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ2_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE 0x150
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE 0x170
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ 0x17c
+#define AIROHA_PCS_ANA_2L_RX0_DAC_E1_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_E0_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_D1_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_D0_BYPASS_AEQ BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ 0x180
+#define AIROHA_PCS_ANA_2L_RX0_DAC_EYE_BYPASS_AEQ BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB 0x234
+#define AIROHA_PCS_ANA_2L_RX1_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL 0x1ac
+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_2L_RX1_REV_0 0x1b4
+#define AIROHA_PCS_ANA_2L_RX1_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV 0x1b8
+#define AIROHA_PCS_ANA_2L_RX1_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV 0x1bc
+#define AIROHA_PCS_ANA_2L_CDR1_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO 0x1c8
+#define AIROHA_PCS_ANA_2L_CDR1_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE 0x1d4
+#define AIROHA_PCS_ANA_2L_CDR1_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC 0x1d8
+#define AIROHA_PCS_ANA_2L_CDR1_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL 0x1dc
+#define AIROHA_PCS_ANA_2L_CDR1_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN 0x1e8
+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPR_EN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN 0x1ec
+#define AIROHA_PCS_ANA_2L_CDR1_PR_XFICK_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR 0x1f0
+#define AIROHA_PCS_ANA_2L_RX1_DAC_MON GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_CAP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BUF_IN_SR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE 0x1f4
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH 0x1f8
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL 0x1fc
+#define AIROHA_PCS_ANA_2L_RX1_FE_EQ_HZEN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN 0x200
+#define AIROHA_PCS_ANA_2L_RX1_FE_VCM_GEN_PWDB BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ3_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ2_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ1_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW 0x208
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE GENMASK(25, 16)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE 0x228
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE GENMASK(27, 16)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ 0x238
+#define AIROHA_PCS_ANA_2L_RX1_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYD */
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0
+#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4
+#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88
+#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8)
+#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c
+#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90
+#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94
+#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98
+#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c
+#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100
+#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104
+#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
+#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
+#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120
+#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8)
+#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c
+#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150
+#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158
+#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12)
+#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c
+#define AIROHA_PCS_PMA_SIGDET_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_1 0x174
+#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_2 0x178
+#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16)
+#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
+#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
+#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_RX_FLL_5 0x184
+#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16)
+#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_B 0x19c
+#define AIROHA_PCS_PMA_LOAD_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_1 0x208
+#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_RST_B 0x260
+#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320
+#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330
+#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c
+#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c
+#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24)
+#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16)
+#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8)
+#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350
+#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360
+#define AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN GENMASK(17, 16)
+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374
+#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2 0x380
+#define AIROHA_PCS_RX_SIGDET BIT(8)
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390
+#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c
+#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414
+#define AIROHA_PCS_PMA_XFI_RX_MODE GENMASK(11, 9)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x0)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x1)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x2)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x3)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x4)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x5)
+#define AIROHA_PCS_PMA_R2T_MODE BIT(8)
+#define AIROHA_PCS_PMA_XFI_TX_MODE GENMASK(5, 3)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x0)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x1)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x2)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x3)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x4)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x5)
+#define AIROHA_PCS_PMA_SW_RST_SET 0x460
+#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11)
+#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8)
+#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7)
+#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6)
+#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5)
+#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4)
+#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3)
+#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2)
+#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1)
+#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0)
+#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474
+#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16)
+#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c
+#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
+#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
+#define AIROHA_PCS_PMA_RX_FREQDET 0x530
+#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580
+#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)
+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_29 0x910
+#define AIROHA_PCS_PMA_2L_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_2L_RX_RATE_CTRL GENMASK(5, 4)
+
+#define AIROHA_PCS_MAX_CALIBRATION_TRY 50
+#define AIROHA_PCS_MAX_RX_SIGDET_TRY 6
+#define AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT 4
+#define AIROHA_PCS_MAX_NUM_RSTS 2
+
+enum xfi_port_type {
+ AIROHA_PCS_ETH,
+ AIROHA_PCS_PON,
+ AIROHA_PCS_USB,
+ AIROHA_PCS_PCIE,
+};
+
+struct airoha_pcs_maps {
+ struct regmap *pcs_mac;
+ struct regmap *hsgmii_an;
+ struct regmap *hsgmii_pcs;
+ struct regmap *hsgmii_rate_adp;
+ struct regmap *multi_sgmii;
+ struct regmap *usxgmii_pcs;
+};
+
+struct airoha_pcs_priv {
+ struct device *dev;
+ const struct airoha_pcs_match_data *data;
+
+ struct airoha_pcs_port *ports;
+
+ struct regmap *scu;
+
+ struct airoha_pcs_maps maps[2];
+
+ struct regmap *pcs_pma[2];
+ struct regmap *pcs_ana;
+ struct regmap_field **pcs_ana_fields[2];
+
+ struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
+
+ struct phy *phy;
+
+ bool manual_rx_calib;
+};
+
+struct airoha_pcs_port {
+ struct airoha_pcs_priv *priv;
+ phy_interface_t interface;
+ int index;
+
+ struct phylink_pcs pcs;
+};
+
+struct airoha_pcs_match_data {
+ int num_port;
+ enum xfi_port_type port_type;
+
+ int (*alloc_regmap_fields)(struct airoha_pcs_priv *priv);
+ int (*bringup)(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+ void (*link_up)(struct airoha_pcs_priv *priv, int index);
+ int (*rxlock_workaround)(struct airoha_pcs_priv *priv, int index);
+};
+
+#define to_airoha_pcs_port(n) container_of(n, struct airoha_pcs_port, pcs)
+
+#if IS_ENABLED(CONFIG_PCS_AIROHA_AN7581)
+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv);
+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv);
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index);
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index);
+#else
+static inline int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv,
+ int index)
+{
+}
+
+static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv,
+ int index)
+{
+ return 0;
+}
+#endif
diff --git a/drivers/net/pcs/airoha/pcs-an7581.c b/drivers/net/pcs/airoha/pcs-an7581.c
new file mode 100644
index 00000000000000..24fc15b6e29e14
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-an7581.c
@@ -0,0 +1,2093 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/math.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/regmap.h>
+
+#include "pcs-airoha.h"
+
+#include <linux/of.h>
+
+enum {
+ AN7581_PCS_CMN_EN,
+
+ AN7581_PCS_JCPLL_SPARE_L,
+ AN7581_PCS_JCPLL_RST_DLY,
+ AN7581_PCS_JCPLL_PLL_RSTB,
+ AN7581_PCS_JCPLL_SDM_DI_EN,
+ AN7581_PCS_JCPLL_SDM_DI_LS,
+
+ AN7581_PCS_JCPLL_SDM_OUT,
+ AN7581_PCS_JCPLL_SDM_ORD,
+ AN7581_PCS_JCPLL_SDM_MODE,
+ AN7581_PCS_JCPLL_SDM_IFM,
+ AN7581_PCS_JCPLL_SDM_HREN,
+
+ AN7581_PCS_JCPLL_CHP_IOFST,
+ AN7581_PCS_JCPLL_CHP_IBIAS,
+ AN7581_PCS_JCPLL_LPF_SHCK_EN,
+
+ AN7581_PCS_JCPLL_LPF_BWR,
+ AN7581_PCS_JCPLL_LPF_BP,
+ AN7581_PCS_JCPLL_LPF_BC,
+ AN7581_PCS_JCPLL_LPF_BR,
+ AN7581_PCS_JCPLL_LPF_BWC,
+
+ AN7581_PCS_JCPLL_VCO_SCAPWR,
+ AN7581_PCS_JCPLL_VCO_HALFLSB_EN,
+ AN7581_PCS_JCPLL_VCO_CFIX,
+ AN7581_PCS_JCPLL_VCODIV,
+ AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L,
+ AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H,
+ AN7581_PCS_JCPLL_VCO_TCLVAR,
+
+ AN7581_PCS_JCPLL_POSTDIV_D5,
+ AN7581_PCS_JCPLL_MMD_PREDIV_MODE,
+
+ AN7581_PCS_JCPLL_KBAND_KS,
+ AN7581_PCS_JCPLL_KBAND_KF,
+ AN7581_PCS_JCPLL_KBAND_KFC,
+ AN7581_PCS_JCPLL_KBAND_DIV,
+ AN7581_PCS_JCPLL_KBAND_CODE,
+ AN7581_PCS_JCPLL_KBAND_OPTION,
+
+ AN7581_PCS_JCPLL_TCL_AMP_VREF,
+ AN7581_PCS_JCPLL_TCL_AMP_GAIN,
+ AN7581_PCS_JCPLL_TCL_AMP_EN,
+
+ AN7581_PCS_JCPLL_TCL_LPF_BW,
+ AN7581_PCS_JCPLL_TCL_LPF_EN,
+
+ AN7581_PCS_JCPLL_SSC_DELTA,
+ AN7581_PCS_JCPLL_SSC_DELTA1,
+ AN7581_PCS_JCPLL_SSC_PERIOD,
+ AN7581_PCS_JCPLL_SSC_TRI_EN,
+ AN7581_PCS_JCPLL_SSC_EN,
+ AN7581_PCS_JCPLL_SSC_PHASE_INI,
+ AN7581_PCS_JCPLL_TCL_KBAND_VREF,
+
+ AN7581_PCS_TXPLL_LDO_VCO_OUT,
+ AN7581_PCS_TXPLL_LDO_OUT,
+ AN7581_PCS_TXPLL_PLL_RSTB,
+ AN7581_PCS_TXPLL_RST_DLY,
+ AN7581_PCS_TXPLL_REFIN_DIV,
+ AN7581_PCS_TXPLL_REFIN_INTERNAL,
+ AN7581_PCS_TXPLL_SDM_MODE,
+ AN7581_PCS_TXPLL_SDM_IFM,
+ AN7581_PCS_TXPLL_SDM_DI_LS,
+ AN7581_PCS_TXPLL_SDM_DI_EN,
+ AN7581_PCS_TXPLL_SDM_HREN,
+ AN7581_PCS_TXPLL_SDM_ORD,
+ AN7581_PCS_TXPLL_SDM_OUT,
+ AN7581_PCS_TXPLL_SSC_DELTA1,
+ AN7581_PCS_TXPLL_SSC_DELTA,
+ AN7581_PCS_TXPLL_SSC_TRI_EN,
+ AN7581_PCS_TXPLL_SSC_PHASE_INI,
+ AN7581_PCS_TXPLL_SSC_EN,
+ AN7581_PCS_TXPLL_SSC_PERIOD,
+ AN7581_PCS_TXPLL_LPF_BC,
+ AN7581_PCS_TXPLL_LPF_BR,
+ AN7581_PCS_TXPLL_LPF_BP,
+ AN7581_PCS_TXPLL_LPF_BWC,
+ AN7581_PCS_TXPLL_LPF_BWR,
+ AN7581_PCS_TXPLL_CHP_IOFST,
+ AN7581_PCS_TXPLL_CHP_IBIAS,
+ AN7581_PCS_TXPLL_VCO_CFIX,
+ AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L,
+ AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H,
+ AN7581_PCS_TXPLL_VCO_TCLVAR,
+ AN7581_PCS_TXPLL_VCO_SCAPWR,
+ AN7581_PCS_TXPLL_VCO_HALFLSB_EN,
+ AN7581_PCS_TXPLL_KBAND_CODE,
+ AN7581_PCS_TXPLL_KBAND_OPTION,
+ AN7581_PCS_TXPLL_KBAND_KS,
+ AN7581_PCS_TXPLL_KBAND_KF,
+ AN7581_PCS_TXPLL_KBAND_KFC,
+ AN7581_PCS_TXPLL_KBAND_DIV,
+ AN7581_PCS_TXPLL_MMD_PREDIV_MODE,
+ AN7581_PCS_TXPLL_POSTDIV_EN,
+ AN7581_PCS_TXPLL_VCODIV,
+ AN7581_PCS_TXPLL_TCL_KBAND_VREF,
+ AN7581_PCS_TXPLL_TCL_AMP_GAIN,
+ AN7581_PCS_TXPLL_TCL_AMP_VREF,
+ AN7581_PCS_TXPLL_TCL_LPF_BW,
+ AN7581_PCS_TXPLL_TCL_LPF_EN,
+ AN7581_PCS_TXPLL_TCL_AMP_EN,
+
+ AN7581_PCS_TX_DMEDGEGEN_EN,
+ AN7581_PCS_TX_CKLDO_EN,
+
+ AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_E1_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_E0_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_D1_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_D0_BYPASS_AEQ,
+ AN7581_PCS_RX_FE_VCM_GEN_PWDB,
+ AN7581_PCS_RX_OSCAL_FORCE,
+ AN7581_PCS_RX_DAC_MON,
+ AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL,
+ AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL,
+ AN7581_PCS_RX_REV_1_SIGDET_ILEAK,
+ AN7581_PCS_RX_FE_VB_EQ3_EN,
+ AN7581_PCS_RX_FE_VB_EQ2_EN,
+ AN7581_PCS_RX_FE_VB_EQ1_EN,
+ AN7581_PCS_RX_FE_EQ_HZEN,
+ AN7581_PCS_RX_SIGDET_VTH_SEL,
+ AN7581_PCS_RX_SIGDET_PEAK,
+ AN7581_PCS_RX_SIGDET_LPF_CTRL,
+ AN7581_PCS_RX_TDC_CK_SEL,
+ AN7581_PCS_RX_PHYCK_RSTB,
+ AN7581_PCS_RX_PHYCK_SEL,
+ AN7581_PCS_RX_PHYCK_DIV,
+ AN7581_PCS_RX_PHY_CK_SEL_FORCE,
+ AN7581_PCS_RX_PHY_CK_SEL,
+
+ AN7581_PCS_AEQ_OFORCE,
+
+ AN7581_PCS_CDR_PD_EDGE_DIS,
+ AN7581_PCS_CDR_PD_PICAL_CKD8_INV,
+
+ AN7581_PCS_CDR_PR_XFICK_EN,
+ AN7581_PCS_CDR_PR_MONPI_EN,
+ AN7581_PCS_CDR_PR_MONPR_EN,
+ AN7581_PCS_CDR_PR_KBAND_DIV,
+ AN7581_PCS_CDR_PR_BETA_SEL,
+ AN7581_PCS_CDR_PR_VCOADC_OS,
+ AN7581_PCS_CDR_PR_BETA_DAC,
+ AN7581_PCS_CDR_PR_FBKSEL,
+ AN7581_PCS_CDR_PR_DAC_BAND,
+ AN7581_PCS_CDR_PR_VREG_CKBUF_VAL,
+ AN7581_PCS_CDR_PR_VREG_IBAND_VAL,
+ AN7581_PCS_CDR_PR_CAP_EN,
+ AN7581_PCS_CDR_PR_INJ_FORCE_OFF,
+
+ AN7581_PCS_CDR_BUF_IN_SR,
+
+ AN7581_PCS_CDR_LPF_TOP_LIM,
+ AN7581_PCS_CDR_LPF_RATIO,
+
+ AN7581_PCS_FIELDS_MAX,
+};
+
+static const struct reg_field an7581_pcs_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 8, 15),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 8, 23),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 0, 0),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 17, 17),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 16, 16),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 16, 20),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 3, 5),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 24, 24),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 16, 18),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 8, 9),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 24, 25),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 8, 9),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 16, 16),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 0, 1),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 24, 28),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 16, 20),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 8, 13),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 0, 5),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 0, 4),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 24, 25),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 27, 29),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 0, 0),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 0, 7),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 0, 1),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 8, 10),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 16, 17),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 8, 8),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 16, 17),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 8, 12),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 8, 10),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 24, 24),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB, 24, 24),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB, 0, 0),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_AEQ_CFORCE, 8, 19),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW, 8, 17),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 24, 28),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 2, 2),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 1, 1),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 0, 0),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 24, 24),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 16, 16),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 8, 8),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 0, 0),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 19, 19),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 16, 18),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 16, 20),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 8, 9),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_RANGE, 24, 25),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, 24, 24),
+};
+
+static const struct reg_field an7581_pcs_pcie0_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 16, 16),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE, 8, 19),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE, 8, 17),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON, 0, 4),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 8, 8),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 0, 0),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN, 24, 24),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 8, 8),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 0, 0),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 24, 24),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 8, 8),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 0, 2),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 0, 4),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 24, 25),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 8, 9),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE, 24, 24),
+};
+
+static const struct reg_field an7581_pcs_pcie1_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB, 24, 24),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 24, 24),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE, 16, 27),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW, 16, 25),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 16, 20),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 8, 8),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 0, 0),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN, 24, 24),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 16, 16),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 8, 8),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 0, 0),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL, 24, 24),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 8, 8),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 0, 2),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 16, 20),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 8, 9),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE, 24, 25),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE, 24, 24),
+};
+
+static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma;
+ u32 kband_vref;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ kband_vref = 0x10;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ kband_vref = 0xf;
+ break;
+ default:
+ return;
+ }
+
+ /* This comment only apply to Serdes PCIe that expose
+ * 2 PCS.
+ *
+ * The Serdes PCIe expose 2 PCS but always require
+ * the PMA for the first PCS to be configured
+ * for correct functionality for JCPLL.
+ */
+ pcs_pma = priv->pcs_pma[0];
+
+ /* Setup LDO */
+ usleep_range(200, 300);
+
+ regmap_field_set_bits(pcs_ana_fields[AN7581_PCS_JCPLL_SPARE_L],
+ AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
+
+ /* Setup RSTB */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_RST_DLY],
+ AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_PLL_RSTB], 0x1);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
+
+ /* Setup SDM */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_LS],
+ AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_EN], 0x0);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_OUT], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_ORD],
+ AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_MODE], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_IFM], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_HREN], 0x0);
+
+ /* Setup SSC */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA1], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PERIOD], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_TRI_EN], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_EN], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PHASE_INI], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0);
+
+ /* Setup LPF */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IOFST], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IBIAS], 0x18);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_SHCK_EN], 0);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWR], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BP], 0x10);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BC], 0x1f);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BR], BIT(3) | BIT(1));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWC], 0x0);
+
+ /* Setup VCO */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_SCAPWR], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_HALFLSB_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_CFIX], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x3);
+
+ /* Setup PCW */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
+
+ /* Setup DIV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_POSTDIV_D5], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_MMD_PREDIV_MODE],
+ AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCODIV],
+ AIROHA_PCS_ANA_JCPLL_VCODIV_1);
+
+ /* Setup KBand */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KS], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KF], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KFC], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_DIV], 0x2);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_CODE], 0xe4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_OPTION], 0x0);
+
+ /* Setup TCL */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_KBAND_VREF],
+ kband_vref);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_VREF], 0x5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_GAIN],
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_EN], 0x1);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_BW],
+ AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_EN], 0x1);
+
+ /* Enable PLL */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
+}
+
+static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
+ struct regmap *pcs_pma;
+ u32 tcl_amp_vref;
+ bool sdm_hren;
+ u32 vco_cfix;
+ bool vcodiv;
+ u32 pcw;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(1) | BIT(0);
+ pcw = BIT(27);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ lpf_chp_ibias = 0xa;
+ lpf_bp = BIT(2) | BIT(0);
+ lpf_bwr = 0;
+ lpf_bwc = 0;
+ vco_cfix = 0;
+ pcw = BIT(27) | BIT(25);
+ tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
+ vcodiv = true;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(0);
+ pcw = BIT(27) | BIT(22);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = true;
+ break;
+ default:
+ return;
+ }
+
+ /* This comment only apply to Serdes PCIe that expose
+ * 2 PCS.
+ *
+ * The Serdes PCIe expose 2 PCS but always require
+ * the PMA for the first PCS to be configured
+ * for correct functionality for TXPLL.
+ */
+ pcs_pma = priv->pcs_pma[0];
+
+ /* Setup VCO LDO Output */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_VCO_OUT], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_OUT], 0x1);
+
+ /* Setup RSTB */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_PLL_RSTB], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_RST_DLY], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_DIV],
+ AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_INTERNAL], 0x1);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+ /* Setup SDM */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_MODE], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_IFM], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_LS],
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_HREN], sdm_hren);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_OUT], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_ORD],
+ AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
+
+ /* Setup SSC */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA1], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_TRI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PHASE_INI], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PERIOD], 0x0);
+
+ /* Setup LPF */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IBIAS],
+ lpf_chp_ibias);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IOFST], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BC], 0x1f);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BR], 0x5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWC], lpf_bwc);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWR], lpf_bwr);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BP], lpf_bp);
+
+ /* Setup VCO */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_CFIX], vco_cfix);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_TCLVAR], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_SCAPWR], 0x7);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_HALFLSB_EN], 0x1);
+
+ /* Setup PCW */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+ /* Setup KBand */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_CODE], 0xe4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_OPTION], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KS], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KF], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KFC], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_DIV], 0x4);
+
+ /* Setup DIV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_POSTDIV_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_MMD_PREDIV_MODE],
+ AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCODIV],
+ vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+ AIROHA_PCS_ANA_TXPLL_VCODIV_1);
+
+ /* Setup TCL */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_KBAND_VREF], 0xf);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_VREF],
+ tcl_amp_vref);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_GAIN],
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_BW],
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_EN], 0x1);
+
+ /* Enable PLL */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+}
+
+static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 fir_cn1, fir_c0b, fir_c1;
+ u32 tx_rate_ctrl;
+ u32 ckin_divisor;
+ u32 xfi_tx_mode;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ ckin_divisor = BIT(1);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 12;
+ fir_c1 = 0;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_1G25;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ ckin_divisor = BIT(2);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 11;
+ fir_c1 = 1;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_3G12;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ ckin_divisor = BIT(2) | BIT(0);
+ tx_rate_ctrl = BIT(1);
+ fir_cn1 = 1;
+ fir_c0b = 1;
+ fir_c1 = 11;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_10G3;
+ break;
+ default:
+ return;
+ }
+
+ /* Set TX rate ctrl */
+ if (priv->data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,
+ AIROHA_PCS_PMA_2L_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_2L_TX_RATE_CTRL,
+ tx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_XFI_TX_MODE,
+ xfi_tx_mode);
+ } else {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ tx_rate_ctrl));
+ }
+
+ /* Setup TX Config */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_DMEDGEGEN_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_CKLDO_EN], 0x1);
+
+ udelay(1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+ /* FIXME: Ask Airoha TX term is OK to reset? */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+ ckin_divisor));
+
+ if (priv->data->port_type != AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ tx_rate_ctrl));
+ }
+
+ /* Setup TX FIR Load Parameters (Reference 660mV) */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+ /* Reset TX Bar */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B,
+ AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
+}
+
+static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 phyck_div, phyck_sel;
+ u32 pr_cdr_beta_dac;
+ u32 cdr_pr_buf_in_sr;
+ bool cdr_pr_cap_en;
+ u32 sigdet_vth_sel;
+ u32 rx_rate_ctrl;
+ u32 xfi_rx_mode;
+ u32 osr;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ osr = BIT(1) | BIT(0); /* 1.25G */
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = false;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(5) | BIT(3) | BIT(0);
+ phyck_sel = BIT(0);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_1G25;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ osr = BIT(0); /* 2.5G */
+ pr_cdr_beta_dac = BIT(2) | BIT(1);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = true;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(3) | BIT(1) | BIT(0);
+ phyck_sel = BIT(0);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_3G12;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ osr = 0; /* 10G */
+ cdr_pr_cap_en = false;
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = BIT(1);
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(1);
+ phyck_div = BIT(6) | BIT(1);
+ phyck_sel = BIT(1);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_10G3;
+ break;
+ default:
+ return;
+ }
+
+ /* Set RX rate ctrl */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_2,
+ AIROHA_PCS_PMA_CK_RATE,
+ AIROHA_PCS_PMA_CK_RATE_10);
+
+ if (priv->data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,
+ AIROHA_PCS_PMA_2L_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_2L_RX_RATE_CTRL,
+ rx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_XFI_RX_MODE,
+ xfi_rx_mode);
+ } else {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+ AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ rx_rate_ctrl));
+ }
+
+ /* Setup RX Path */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_5,
+ AIROHA_PCS_PMA_FLL_IDAC_MIN |
+ AIROHA_PCS_PMA_FLL_IDAC_MAX,
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VCM_GEN_PWDB], 0x1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+ AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_AEQ_OFORCE],
+ AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_OSCAL_FORCE],
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+ AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+ AIROHA_PCS_PMA_DISB_LEQ);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_PICAL_CKD8_INV], 0x0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
+ AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_MON], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_XFICK_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPR_EN], 0x0);
+
+ /* Setup FE Gain and FE Peacking */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0));
+
+ /* Setup FE VOS */
+ if (interface != PHY_INTERFACE_MODE_USXGMII &&
+ interface != PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
+
+ /* Setup FLL PR FMeter (no bypass mode)*/
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
+ AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
+ AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
+
+ /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
+ /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
+ /* Setup REV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL],
+ BIT(2));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL],
+ BIT(2));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_SIGDET_ILEAK], 0x0);
+
+ /* Setup Rdy Timeout */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+ AIROHA_PCS_PMA_RX_RDY |
+ AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+ /* Setup CaBoundry Init */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+ AIROHA_PCS_PMA_RX_OS_START |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+ AIROHA_PCS_PMA_RX_OS_END,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+ AIROHA_PCS_PMA_RX_PICAL_END |
+ AIROHA_PCS_PMA_RX_PICAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+ AIROHA_PCS_PMA_RX_SDCAL_END |
+ AIROHA_PCS_PMA_RX_SDCAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+ AIROHA_PCS_PMA_RX_PDOS_END |
+ AIROHA_PCS_PMA_RX_PDOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+ AIROHA_PCS_PMA_RX_FEOS_END |
+ AIROHA_PCS_PMA_RX_FEOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+ /* Setup By Serdes*/
+ /* Setup RX OSR */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], !!osr);
+
+ /* Setup CDR LPF Ratio */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_TOP_LIM], 0x20000);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_RATIO], osr);
+
+ /* Setup CDR PR */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_KBAND_DIV], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_SEL], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VCOADC_OS], 0x8);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_DAC],
+ pr_cdr_beta_dac);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_FBKSEL], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_DAC_BAND],
+ pr_cdr_beta_dac);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL], 0x6);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_IBAND_VAL], 0x6);
+
+ /* Setup Eye Mon */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,
+ AIROHA_PCS_PMA_EQ_DEBUG_SEL |
+ AIROHA_PCS_PMA_FOM_NUM_ORDER |
+ AIROHA_PCS_PMA_A_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
+ FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+ FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+ AIROHA_PCS_PMA_DATA_SHIFT |
+ AIROHA_PCS_PMA_EYECNT_FAST,
+ AIROHA_PCS_PMA_EYECNT_FAST);
+
+ /* Calibration Start */
+
+ /* Enable SYS */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+ AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+ AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+ usleep_range(500, 600);
+
+ /* Setup FLL PR FMeter (bypass mode)*/
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+ /* Enable CMLEQ */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_EQ_HZEN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ3_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ2_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ1_EN], 0x1);
+
+ /* Setup CDR PR */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_CAP_EN],
+ cdr_pr_cap_en);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_BUF_IN_SR],
+ cdr_pr_buf_in_sr);
+
+ /* Setup CDR xxx Pwdb, set force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* FIXME: Ask Airoha WHY it's cleared? */
+ /* regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+ * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
+ */
+
+ /* Setup SigDet */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_VTH_SEL],
+ sigdet_vth_sel);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_PEAK],
+ BIT(1));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_LPF_CTRL],
+ BIT(1) | BIT(0));
+
+ /* Disable SigDet Pwdb */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+ /* Setup PHYCK */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_TDC_CK_SEL], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_RSTB], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_SEL],
+ phyck_sel);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_DIV],
+ phyck_div);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL_FORCE], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL], 0x0);
+
+ usleep_range(100, 200);
+
+ /* Enable CDR xxx Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* Enable SigDet Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+}
+
+static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
+ int index, u32 cdr_pr_idac)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 val;
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ cdr_pr_idac));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
+
+ usleep_range(5000, 7000);
+
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+
+ return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
+}
+
+static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv,
+ int index, u32 target_fl_out)
+{
+ unsigned int fl_out_diff = UINT_MAX;
+ unsigned int prcal_search;
+ u32 cdr_pr_idac = 0;
+
+ for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
+ unsigned int fl_out_diff_new;
+ unsigned int fl_out;
+ u32 cdr_pr_idac_tmp;
+
+ /* try to find the upper value by setting the last 3 bit */
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ prcal_search);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff_new < fl_out_diff) {
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ fl_out_diff = fl_out_diff_new;
+ }
+ }
+
+ return cdr_pr_idac;
+}
+
+static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, int index,
+ u32 target_fl_out, u32 cdr_pr_idac_major)
+{
+ unsigned int remaining_prcal_search_bits = 0;
+ u32 cdr_pr_idac = cdr_pr_idac_major;
+ unsigned int fl_out, fl_out_diff;
+ int best_prcal_search_bit = -1;
+ int prcal_search_bit;
+
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);
+ fl_out_diff = abs_diff(fl_out, target_fl_out);
+
+ /* Deadline search part.
+ * We start from top bits to bottom as we progressively decrease the
+ * signal.
+ */
+ for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff_new < fl_out_diff) {
+ best_prcal_search_bit = prcal_search_bit;
+ fl_out_diff = fl_out_diff_new;
+ }
+ }
+
+ /* Set the idac with the best value we found and
+ * reset the search bit to start from bottom to top.
+ */
+ if (best_prcal_search_bit >= 0) {
+ cdr_pr_idac |= BIT(best_prcal_search_bit);
+ remaining_prcal_search_bits = best_prcal_search_bit;
+ prcal_search_bit = 0;
+ }
+
+ /* Fine tune part.
+ * Test remaining bits to find an even closer signal level to target
+ * by increasing the signal.
+ */
+ while (remaining_prcal_search_bits) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ /* Assume we found the deadline when the new absolue signal difference
+ * from target is greater than the previous and the difference is at
+ * least 10% greater between the old and new value.
+ * This is to account for signal detection level tollerance making
+ * sure we are actually over a deadline (AKA we are getting farther
+ * from target)
+ */
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff && fl_out_diff_new > fl_out_diff &&
+ (abs_diff(fl_out_diff_new, fl_out_diff) * 100) / fl_out_diff > 10) {
+ /* Exit early if we are already at the deadline */
+ if (prcal_search_bit == 0)
+ break;
+
+ /* We found the deadline, set the value to the previous
+ * bit, and reset the loop to fine tune with the
+ * remaining values.
+ */
+ cdr_pr_idac |= BIT(prcal_search_bit - 1);
+ remaining_prcal_search_bits = prcal_search_bit - 1;
+ prcal_search_bit = 0;
+ } else {
+ /* Update the signal level diff and try the next bit */
+ fl_out_diff = fl_out_diff_new;
+
+ /* If we didn't found the deadline, set the last bit
+ * and reset the loop to fine tune with the remainig
+ * values.
+ */
+ if (prcal_search_bit == remaining_prcal_search_bits - 1) {
+ cdr_pr_idac |= BIT(prcal_search_bit);
+ remaining_prcal_search_bits = prcal_search_bit;
+ prcal_search_bit = 0;
+ } else {
+ prcal_search_bit++;
+ }
+ }
+ }
+
+ return cdr_pr_idac;
+}
+
+static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 cdr_pr_idac_major, cdr_pr_idac;
+ unsigned int fl_out, fl_out_diff;
+
+ u32 target_fl_out;
+ u32 cyclecnt;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */
+ case PHY_INTERFACE_MODE_1000BASEX:
+ target_fl_out = 0xa3d6;
+ cyclecnt = 32767;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */
+ target_fl_out = 0xa000;
+ cyclecnt = 20000;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */
+ case PHY_INTERFACE_MODE_10GBASER:
+ target_fl_out = 0x9edf;
+ cyclecnt = 32767;
+ break;
+ default:
+ return;
+ }
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
+ AIROHA_PCS_PMA_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+ AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+ AIROHA_PCS_PMA_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_LOCK_UNLOCKTH |
+ AIROHA_PCS_PMA_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
+ AIROHA_PCS_PMA_UNLOCK_TARGET_END |
+ AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ /* Calibration logic:
+ * First check the major value by looping with every
+ * value in the last 3 bit of CDR_PR_IDAC.
+ * Get the signal level and save the value that is closer to
+ * the target.
+ *
+ * Then check each remaining 7 bits in search of the deadline
+ * where the signal gets farther than signal target.
+ *
+ * Finally fine tune for the remaining bits to find the one that
+ * produce the closest signal level.
+ */
+ cdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv, index, target_fl_out);
+
+ cdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, index,
+ target_fl_out, cdr_pr_idac_major);
+
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);
+ fl_out_diff = abs_diff(fl_out, target_fl_out);
+ if (fl_out_diff > 100) {
+ u32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ cdr_pr_idac_major);
+ unsigned int fl_out_tmp, fl_out_diff_tmp;
+ u32 cdr_pr_idac_tmp;
+
+ if (pr_idac_major > 0) {
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ pr_idac_major - 1);
+
+ dev_dbg(priv->dev, "Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\n",
+ fl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp);
+
+ cdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, index,
+ target_fl_out,
+ cdr_pr_idac_tmp);
+
+ fl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, index,
+ cdr_pr_idac_tmp);
+ fl_out_diff_tmp = abs_diff(fl_out_tmp, target_fl_out);
+ if (fl_out_diff_tmp < fl_out_diff) {
+ fl_out = fl_out_tmp;
+ fl_out_diff = fl_out_diff_tmp;
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ }
+ }
+ }
+ dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
+ if (fl_out_diff > 100)
+ dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n",
+ fl_out_diff, target_fl_out);
+
+ /* Setup Load Band */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x0);
+
+ /* Disable force of LPF C previously enabled */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_B,
+ AIROHA_PCS_PMA_LOAD_EN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_1,
+ AIROHA_PCS_PMA_LPATH_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+}
+
+/* This is used to both calibrate and lock to signal (after a previous
+ * calibration) after a global reset.
+ */
+static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, int index,
+ phy_interface_t interface, bool calibrate)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Setup LPF L2D force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+ /* Calibrate IDAC and setup Load Band */
+ if (calibrate)
+ an7581_pcs_rx_prcal(priv, index, interface);
+
+ /* Setup LPF RSTB force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ usleep_range(700, 1000);
+
+ /* Force Enable LPF RSTB */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+ usleep_range(100, 200);
+
+ /* Force Enable LPF L2D */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+ /* Disable LPF RSTB force bit */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ /* Disable LPF L2D force bit */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+}
+
+static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ int calibration_try = 0;
+ u32 val;
+
+ an7581_pcs_tx_bringup(priv, index, interface);
+ an7581_pcs_rx_bringup(priv, index, interface);
+
+ usleep_range(100, 200);
+
+retry_calibration:
+ an7581_pcs_cdr_reset(priv, index, interface, priv->manual_rx_calib);
+
+ /* Global reset clear */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ /* Global reset */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+ usleep_range(5000, 7000);
+
+ an7581_pcs_cdr_reset(priv, index, interface, false);
+
+ /* Manual RX calibration is required only for SoC before E2
+ * revision. E2+ SoC autocalibrate RX and only CDR reset is needed.
+ */
+ if (!priv->manual_rx_calib)
+ return 0;
+
+ /* It was discovered that after a global reset and auto mode gets
+ * actually enabled, the fl_out from calibration might change and
+ * might deviates a lot from the expected value it was calibrated for.
+ * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
+ * (frequency level output) or no signal can correctly be transmitted.
+ * This is detected by checking the FreqDet module Lock bit.
+ *
+ * If it's detected that the FreqDet module is not locked, retry
+ * calibration. From observation on real hardware with a 10g SFP module,
+ * it required a maximum of an additional calibration to actually make
+ * the FreqDet module to lock. Try 10 times before failing to handle
+ * really strange case.
+ */
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+ if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
+ if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
+ dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
+ AIROHA_PCS_MAX_CALIBRATION_TRY);
+ return -EIO;
+ }
+
+ calibration_try++;
+
+ dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
+ goto retry_calibration;
+ }
+
+ return 0;
+}
+
+static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ an7581_pcs_jcpll_bringup(priv, index, interface);
+
+ usleep_range(200, 300);
+
+ an7581_pcs_txpll_bringup(priv, index, interface);
+
+ usleep_range(200, 300);
+}
+
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv, int index,
+ phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+
+ /* Enable Analog Common Lane */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CMN_EN], 0x1);
+
+ /* Setup PLL */
+ an7581_pcs_pll_bringup(priv, index, interface);
+
+ msleep(100);
+
+ /* Setup PHYA */
+ return an7581_pcs_phya_bringup(priv, index, interface);
+}
+
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ int ret;
+
+ ret = phy_set_mode_ext(priv->phy, PHY_MODE_ETHERNET, interface);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1, 0xc) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, 0x3));
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ } else {
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ }
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32);
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, 0x1));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK)));
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII);
+ else
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII);
+
+ return 0;
+}
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Reset TXPCS on link up */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+}
+
+static int __an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv, int index,
+ const struct reg_field *fields)
+{
+ struct device *dev = priv->dev;
+ int i;
+
+ priv->pcs_ana_fields[index] = devm_kcalloc(dev, AN7581_PCS_FIELDS_MAX,
+ sizeof(*priv->pcs_ana_fields[index]),
+ GFP_KERNEL);
+ if (!priv->pcs_ana_fields[index])
+ return -ENOMEM;
+
+ for (i = 0; i < AN7581_PCS_FIELDS_MAX; i++) {
+ struct regmap_field *field;
+
+ field = devm_regmap_field_alloc(dev, priv->pcs_ana,
+ fields[i]);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ priv->pcs_ana_fields[index][i] = field;
+ }
+
+ return 0;
+}
+
+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_fields);
+}
+
+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ int ret;
+
+ ret = __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_pcie0_fields);
+ if (ret)
+ return ret;
+
+ return __an7581_pcs_alloc_regmap_fields(priv, 1, an7581_pcs_pcie1_fields);
+}
+
+static bool an7581_pcs_have_rx_signal(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ unsigned int count = 0;
+ u32 val;
+ int i;
+
+ regmap_write(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_0,
+ AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN);
+
+ /* Scan 6 times for RX sigdet module to detect RX signal */
+ for (i = 0; i < AIROHA_PCS_MAX_RX_SIGDET_TRY; i++) {
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_DIG_RO_RESERVE_2,
+ &val);
+ if (val & AIROHA_PCS_RX_SIGDET)
+ count++;
+ }
+
+ /* Consider signal presence if we detect signal at least 4 times */
+ return count >= AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT;
+}
+
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 val;
+
+ /* Check if PCS is UP or Down */
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_STUS_1, &val);
+ if (val & AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP)
+ return 0;
+
+ /* Validate if this is consistent with RX SigDet module */
+ if (!an7581_pcs_have_rx_signal(priv, index))
+ return 0;
+
+ /* If PCS is down but RX SigDet module detected signal,
+ * trigger CDR reset.
+ */
+ an7581_pcs_cdr_reset(priv, index, PHY_INTERFACE_MODE_NA, false);
+
+ /* Report there is an error with Link Detection and we
+ * should test again later.
+ */
+ return -EINVAL;
+}
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
new file mode 100644
index 00000000000000..7a9d91b2a34da7
--- /dev/null
+++ b/drivers/net/pcs/pcs.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+ struct list_head link;
+
+ struct fwnode_handle *fwnode;
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+ void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
+
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier);
+
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);
+
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return 0;
+
+ pp = kzalloc_obj(*pp);
+ if (!pp)
+ return -ENOMEM;
+
+ pp->fwnode = fwnode_handle_get(fwnode);
+ pp->data = data;
+ pp->get = get;
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_add(&pp->link, &fwnode_pcs_providers);
+ mutex_unlock(&fwnode_pcs_mutex);
+ pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+ fwnode_dev_initialized(fwnode, true);
+
+ blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+ FWNODE_PCS_PROVIDER_ADD,
+ fwnode);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return;
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(pp, &fwnode_pcs_providers, link) {
+ if (pp->fwnode == fwnode) {
+ list_del(&pp->link);
+ fwnode_dev_initialized(pp->fwnode, false);
+ fwnode_handle_put(pp->fwnode);
+ kfree(pp);
+ break;
+ }
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode,
+ int index, const char *name,
+ struct fwnode_reference_args *out_args)
+{
+ int ret;
+
+ if (!fwnode)
+ return -EINVAL;
+
+ if (name) {
+ index = fwnode_property_match_string(fwnode, "pcs-names",
+ name);
+ if (index < 0)
+ return index;
+ }
+
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells",
+ -1, index, out_args);
+ if (ret || (name && index < 0))
+ return ret;
+
+ return 0;
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+ struct fwnode_pcs_provider *provider;
+ struct phylink_pcs *pcs = ERR_PTR(-ENODEV);
+
+ if (!pcsspec)
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+ if (provider->fwnode == pcsspec->fwnode) {
+ pcs = provider->get(pcsspec, provider->data);
+ if (!IS_ERR(pcs))
+ break;
+ }
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ return pcs;
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,
+ unsigned int index, const char *con_id)
+{
+ struct fwnode_reference_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+ fwnode_handle_put(pcsspec.fwnode);
+
+ return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, unsigned int index)
+{
+ return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode)
+{
+ struct fwnode_reference_args pcsspec;
+ int index = 0;
+ int ret;
+
+ /* Loop until we find a matching PCS node or
+ * fwnode_parse_pcsspec() returns error
+ * if we don't have any other PCS reference to check.
+ */
+ while (true) {
+ ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ /* Exit loop if we found the matching PCS node */
+ if (pcsspec.fwnode == pcs_fwnode) {
+ fwnode_handle_put(pcsspec.fwnode);
+ break;
+ }
+
+ /* Check the next PCS reference */
+ fwnode_handle_put(pcsspec.fwnode);
+ index++;
+ }
+
+ return fwnode_pcs_get(fwnode, index);
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_get_from_fwnode);
+
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ struct fwnode_reference_args out_args;
+ int index = 0;
+ int ret;
+
+ while (true) {
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells",
+ -1, index, &out_args);
+ /* We expect to reach an -ENOENT error while counting */
+ if (ret)
+ break;
+
+ fwnode_handle_put(out_args.fwnode);
+ index++;
+ }
+
+ return index;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_count);
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ unsigned int i, found = 0;
+
+ if (!available_pcs)
+ return -EINVAL;
+
+ if (!fwnode_property_present(fwnode, "pcs-handle"))
+ return -ENODEV;
+
+ for (i = 0; i < num_pcs; i++) {
+ struct phylink_pcs *pcs;
+
+ pcs = fwnode_pcs_get(fwnode, i);
+ if (IS_ERR(pcs)) {
+ /* Exit early if no PCS remain.*/
+ if (PTR_ERR(pcs) == -ENOENT)
+ break;
+
+ /*
+ * Ignore -ENODEV error for PCS that still
+ * needs to probe.
+ */
+ if (PTR_ERR(pcs) == -ENODEV)
+ continue;
+
+ return PTR_ERR(pcs);
+ }
+
+ available_pcs[found] = pcs;
+ found++;
+ }
+
+ return found;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 59dfe35afa54fc..e36a6647d7e81b 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/phylink.h>
@@ -60,6 +61,15 @@ struct phylink {
/* The link configuration settings */
struct phylink_link_state link_config;
+ /* List of available PCS */
+ struct list_head pcs_list;
+ struct notifier_block fwnode_pcs_nb;
+
+ /* What interface are supported by the current link.
+ * Can change on removal or addition of new PCS.
+ */
+ DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+
/* The current settings */
phy_interface_t cur_interface;
@@ -149,6 +159,10 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {
static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
+static void phylink_run_resolve(struct phylink *pl);
+static void phylink_link_down(struct phylink *pl);
+static void phylink_pcs_disable(struct phylink_pcs *pcs);
+
/**
* phylink_set_port_modes() - set the port type modes in the ethtool mask
* @mask: ethtool link mode mask
@@ -512,12 +526,29 @@ static void phylink_validate_mask_caps(unsigned long *supported,
linkmode_and(state->advertising, state->advertising, mask);
}
+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* If PCS define an empty supported_interfaces value, assume
+ * all interface are supported.
+ */
+ if (phy_interface_empty(pcs->supported_interfaces))
+ return 0;
+
+ /* Ensure that this PCS supports the interface mode */
+ if (!test_bit(interface, pcs->supported_interfaces))
+ return -EINVAL;
+
+ return 0;
+}
+
static int phylink_validate_mac_and_pcs(struct phylink *pl,
unsigned long *supported,
struct phylink_link_state *state)
{
- struct phylink_pcs *pcs = NULL;
unsigned long capabilities;
+ struct phylink_pcs *pcs;
+ bool pcs_found = false;
int ret;
/* Get the PCS for this interface mode */
@@ -525,9 +556,24 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
if (IS_ERR(pcs))
return PTR_ERR(pcs);
+
+ pcs_found = !!pcs;
+ /*
+ * Find a PCS in available PCS list for the requested interface.
+ *
+ * Skip searching if the MAC doesn't require a dedicated PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs, state->interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
}
- if (pcs) {
+ if (pcs_found) {
/* The PCS, if present, must be setup before phylink_create()
* has been called. If the ops is not initialised, print an
* error and backtrace rather than oopsing the kernel.
@@ -539,13 +585,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
return -EINVAL;
}
- /* Ensure that this PCS supports the interface which the MAC
- * returned it for. It is an error for the MAC to return a PCS
- * that does not support the interface mode.
- */
- if (!phy_interface_empty(pcs->supported_interfaces) &&
- !test_bit(state->interface, pcs->supported_interfaces)) {
- phylink_err(pl, "MAC returned PCS which does not support %s\n",
+ /* Recheck PCS to handle legacy way for .mac_select_pcs */
+ ret = phylink_validate_pcs_interface(pcs, state->interface);
+ if (ret) {
+ phylink_err(pl, "selected PCS does not support %s\n",
phy_modes(state->interface));
return -EINVAL;
}
@@ -628,7 +671,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
static int phylink_validate(struct phylink *pl, unsigned long *supported,
struct phylink_link_state *state)
{
- const unsigned long *interfaces = pl->config->supported_interfaces;
+ const unsigned long *interfaces = pl->supported_interfaces;
if (state->interface == PHY_INTERFACE_MODE_NA)
return phylink_validate_mask(pl, NULL, supported, state,
@@ -878,6 +921,60 @@ static void phylink_resolve_an_pause(struct phylink_link_state *state)
}
}
+/**
+ * phylink_release_pcs - Removes a PCS from the phylink PCS available list
+ * @pcs: a pointer to the phylink_pcs struct to be released
+ *
+ * This function release a PCS from the phylink PCS available list if
+ * actually in use. It also refreshes the supported interfaces of the
+ * phylink instance by copying the supported interfaces from the phylink
+ * conf and merging the supported interfaces of the remaining available PCS
+ * in the list and trigger a resolve.
+ */
+void phylink_release_pcs(struct phylink_pcs *pcs)
+{
+ struct phylink *pl;
+
+ ASSERT_RTNL();
+
+ pl = pcs->phylink;
+ if (!pl)
+ return;
+
+ mutex_lock(&pl->state_mutex);
+
+ list_del(&pcs->list);
+ pcs->phylink = NULL;
+
+ /*
+ * Check if we are removing the PCS currently
+ * in use by phylink. If this is the case, tear down
+ * the link, force phylink resolve to reconfigure the
+ * interface mode, disable the current PCS and set the
+ * phylink PCS to NULL.
+ */
+ if (pl->pcs == pcs) {
+ phylink_link_down(pl);
+ phylink_pcs_disable(pl->pcs);
+
+ pl->force_major_config = true;
+ pl->pcs = NULL;
+ }
+
+ mutex_unlock(&pl->state_mutex);
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ phylink_run_resolve(pl);
+}
+EXPORT_SYMBOL_GPL(phylink_release_pcs);
+
static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs,
phy_interface_t interface)
{
@@ -940,6 +1037,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
}
+static void phylink_pcs_link_down(struct phylink_pcs *pcs)
+{
+ if (pcs && pcs->ops->pcs_link_down)
+ pcs->ops->pcs_link_down(pcs);
+}
+
static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)
{
if (pcs && pcs->ops->pcs_disable_eee)
@@ -959,12 +1062,22 @@ static unsigned int phylink_inband_caps(struct phylink *pl,
phy_interface_t interface)
{
struct phylink_pcs *pcs;
+ bool pcs_found = false;
- if (!pl->mac_ops->mac_select_pcs)
- return 0;
+ if (pl->mac_ops->mac_select_pcs) {
+ pcs = pl->mac_ops->mac_select_pcs(pl->config,
+ interface);
+ pcs_found = !!pcs;
+ } else if (test_bit(interface, pl->config->pcs_interfaces)) {
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs, interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
+ }
- pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
- if (!pcs)
+ if (!pcs_found)
return 0;
return phylink_pcs_inband_caps(pcs, interface);
@@ -1259,10 +1372,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
pl->major_config_failed = true;
return;
}
+ /* Find a PCS in available PCS list for the requested interface.
+ * This doesn't overwrite the previous .mac_select_pcs as either
+ * .mac_select_pcs or PCS list implementation are permitted.
+ *
+ * Skip searching if the MAC doesn't require a dedicated PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ bool pcs_found = false;
+
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs,
+ state->interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
- pcs_changed = pl->pcs != pcs;
+ if (!pcs_found) {
+ phylink_err(pl,
+ "couldn't find a PCS for %s\n",
+ phy_modes(state->interface));
+
+ pl->major_config_failed = true;
+ return;
+ }
}
+ pcs_changed = pl->pcs != pcs;
+
phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
phylink_dbg(pl, "major config, active %s/%s/%s\n",
@@ -1289,13 +1428,15 @@ static void phylink_major_config(struct phylink *pl, bool restart,
if (pcs_changed) {
phylink_pcs_disable(pl->pcs);
- if (pl->pcs)
- pl->pcs->phylink = NULL;
+ if (pl->mac_ops->mac_select_pcs) {
+ if (pl->pcs)
+ pl->pcs->phylink = NULL;
- if (pcs)
- pcs->phylink = pl;
+ if (pcs)
+ pcs->phylink = pl;
+ }
- pl->pcs = pcs;
+ WRITE_ONCE(pl->pcs, pcs);
}
if (pl->pcs)
@@ -1603,6 +1744,9 @@ static void phylink_link_down(struct phylink *pl)
pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
pl->cur_interface);
+
+ phylink_pcs_link_down(pl->pcs);
+
phylink_info(pl, "Link is Down\n");
}
@@ -1828,6 +1972,91 @@ int phylink_set_fixed_link(struct phylink *pl,
}
EXPORT_SYMBOL_GPL(phylink_set_fixed_link);
+static int phylink_fill_available_pcs(struct phylink *pl,
+ struct phylink_config *config)
+{
+ struct phylink_pcs **pcss;
+ int i, ret;
+
+ if (!config->num_possible_pcs)
+ return 0;
+
+ if (!config->fill_available_pcs) {
+ dev_err(config->dev,
+ "phylink: error: num_possible_pcs defined but no fill_available_pcs\n");
+ return -EINVAL;
+ }
+
+ pcss = kzalloc_objs(*pcss, config->num_possible_pcs);
+ if (!pcss)
+ return -ENOMEM;
+
+ ret = config->fill_available_pcs(config, pcss, config->num_possible_pcs);
+ if (ret < 0)
+ goto out;
+
+ for (i = 0; i < config->num_possible_pcs; i++) {
+ struct phylink_pcs *pcs = pcss[i];
+
+ if (!pcs)
+ continue;
+
+ list_add(&pcs->list, &pl->pcs_list);
+ }
+
+out:
+ kfree(pcss);
+
+ return ret;
+}
+
+static int pcs_provider_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+ struct fwnode_handle *pcs_fwnode = data;
+ struct phylink_pcs *pcs;
+
+ rtnl_lock();
+
+ /* Check if the just added PCS provider is
+ * in the phylink instance pcs-handle property.
+ */
+ pcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl->config->dev),
+ pcs_fwnode);
+ if (IS_ERR(pcs)) {
+ rtnl_unlock();
+ return NOTIFY_DONE;
+ }
+
+ /* Add the PCS */
+ mutex_lock(&pl->state_mutex);
+
+ /* Link PCS with phylink */
+ list_add(&pcs->list, &pl->pcs_list);
+ pcs->phylink = pl;
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ /* Force an interface reconfig if major config fail */
+ if (pl->major_config_failed)
+ pl->force_major_config = true;
+
+ mutex_unlock(&pl->state_mutex);
+
+ rtnl_unlock();
+
+ phylink_run_resolve(pl);
+
+ return NOTIFY_OK;
+}
+
/**
* phylink_create() - create a phylink instance
* @config: a pointer to the target &struct phylink_config
@@ -1849,13 +2078,17 @@ struct phylink *phylink_create(struct phylink_config *config,
phy_interface_t iface,
const struct phylink_mac_ops *mac_ops)
{
+ struct phylink_pcs *pcs;
struct phylink *pl;
int ret;
- /* Validate the supplied configuration */
- if (phy_interface_empty(config->supported_interfaces)) {
+ /*
+ * Make sure either PCS internal validation or .mac_select_pcs
+ * is used. Return error if both are defined.
+ */
+ if (config->num_possible_pcs && mac_ops->mac_select_pcs) {
dev_err(config->dev,
- "phylink: error: empty supported_interfaces\n");
+ "phylink: error: either phylink_config .num_possible_pcs or .mac_select_pcs must be used\n");
return ERR_PTR(-EINVAL);
}
@@ -1866,6 +2099,25 @@ struct phylink *phylink_create(struct phylink_config *config,
mutex_init(&pl->phydev_mutex);
mutex_init(&pl->state_mutex);
INIT_WORK(&pl->resolve, phylink_resolve);
+ INIT_LIST_HEAD(&pl->pcs_list);
+
+ /* Fill the PCS list with available PCS from phylink config */
+ ret = phylink_fill_available_pcs(pl, config);
+ if (ret < 0)
+ goto free_pl;
+
+ /* Link available PCS to phylink */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ pcs->phylink = pl;
+
+ phy_interface_copy(pl->supported_interfaces,
+ config->supported_interfaces);
+
+ /* Update supported interfaces */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
pl->config = config;
if (config->type == PHYLINK_NETDEV) {
@@ -1874,8 +2126,7 @@ struct phylink *phylink_create(struct phylink_config *config,
} else if (config->type == PHYLINK_DEV) {
pl->dev = config->dev;
} else {
- kfree(pl);
- return ERR_PTR(-EINVAL);
+ goto unlink_pcs_list;
}
pl->mac_supports_eee_ops = phylink_mac_implements_lpi(mac_ops);
@@ -1908,28 +2159,35 @@ struct phylink *phylink_create(struct phylink_config *config,
phylink_validate(pl, pl->supported, &pl->link_config);
ret = phylink_parse_mode(pl, fwnode);
- if (ret < 0) {
- kfree(pl);
- return ERR_PTR(ret);
- }
+ if (ret < 0)
+ goto unlink_pcs_list;
if (pl->cfg_link_an_mode == MLO_AN_FIXED) {
ret = phylink_parse_fixedlink(pl, fwnode);
- if (ret < 0) {
- kfree(pl);
- return ERR_PTR(ret);
- }
+ if (ret < 0)
+ goto unlink_pcs_list;
}
pl->req_link_an_mode = pl->cfg_link_an_mode;
ret = phylink_register_sfp(pl, fwnode);
- if (ret < 0) {
- kfree(pl);
- return ERR_PTR(ret);
+ if (ret < 0)
+ goto unlink_pcs_list;
+
+ /* Register notifier for late PCS attach */
+ if (!phy_interface_empty(config->pcs_interfaces)) {
+ pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+ register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
}
return pl;
+
+unlink_pcs_list:
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ pcs->phylink = NULL;
+free_pl:
+ kfree(pl);
+ return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(phylink_create);
@@ -1944,11 +2202,24 @@ EXPORT_SYMBOL_GPL(phylink_create);
*/
void phylink_destroy(struct phylink *pl)
{
+ struct phylink_pcs *pcs, *tmp;
+
sfp_bus_del_upstream(pl->sfp_bus);
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+ /* Unregister notifier for late PCS attach */
+ if (pl->fwnode_pcs_nb.notifier_call)
+ unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+
cancel_work_sync(&pl->resolve);
+
+ /* Drop link between PCS and phylink */
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) {
+ pcs->phylink = NULL;
+ list_del(&pcs->list);
+ }
+
kfree(pl);
}
EXPORT_SYMBOL_GPL(phylink_destroy);
@@ -2025,7 +2296,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
* those which the host supports.
*/
phy_interface_and(interfaces, phy->possible_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
if (phy_interface_empty(interfaces)) {
phylink_err(pl, "PHY has no common interfaces\n");
@@ -2404,8 +2675,15 @@ void phylink_pcs_change(struct phylink_pcs *pcs, bool up)
{
struct phylink *pl = pcs->phylink;
- if (pl)
- phylink_link_changed(pl, up, "pcs");
+ /*
+ * Ignore PCS link state change if the PCS is not
+ * attached to a phylink instance or the phylink
+ * instance is not currently using this PCS.
+ */
+ if (!pl || READ_ONCE(pl->pcs) != pcs)
+ return;
+
+ phylink_link_changed(pl, up, "pcs");
}
EXPORT_SYMBOL_GPL(phylink_pcs_change);
@@ -2827,12 +3105,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,
return interface;
}
- if (!test_bit(interface, pl->config->supported_interfaces)) {
+ if (!test_bit(interface, pl->supported_interfaces)) {
phylink_err(pl,
"selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\n",
phy_modes(interface), interface,
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
return PHY_INTERFACE_MODE_NA;
}
@@ -3760,14 +4038,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)
phylink_dbg(pl, "optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\n",
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces,
+ pl->supported_interfaces,
(int)PHY_INTERFACE_MODE_MAX,
pl->sfp_interfaces);
/* Find the union of the supported interfaces by the PCS/MAC and
* the SFP module.
*/
- phy_interface_and(pl->sfp_interfaces, pl->config->supported_interfaces,
+ phy_interface_and(pl->sfp_interfaces, pl->supported_interfaces,
pl->sfp_interfaces);
if (phy_interface_empty(pl->sfp_interfaces)) {
phylink_err(pl, "unsupported SFP module: no common interface modes\n");
@@ -3938,7 +4216,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
/* Set the PHY's host supported interfaces */
phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
/* Do the initial configuration */
return phylink_sfp_config_phy(pl, phy);
diff --git a/drivers/of/property.c b/drivers/of/property.c
index 72cf12907de034..91c3e3931fa6e3 100644
--- a/drivers/of/property.c
+++ b/drivers/of/property.c
@@ -1415,6 +1415,7 @@ DEFINE_SIMPLE_PROP(access_controllers, "access-controllers", "#access-controller
DEFINE_SIMPLE_PROP(pses, "pses", "#pse-cells")
DEFINE_SIMPLE_PROP(power_supplies, "power-supplies", NULL)
DEFINE_SIMPLE_PROP(mmc_pwrseq, "mmc-pwrseq", NULL)
+DEFINE_SIMPLE_PROP(pcs_handle, "pcs-handle", "#pcs-cells")
DEFINE_SUFFIX_PROP(regulators, "-supply", NULL)
DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells")
@@ -1571,6 +1572,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
{ .parse_prop = parse_interrupts, },
{ .parse_prop = parse_interrupt_map, },
{ .parse_prop = parse_access_controllers, },
+ { .parse_prop = parse_pcs_handle, },
{ .parse_prop = parse_regulators, },
{ .parse_prop = parse_gpio, },
{ .parse_prop = parse_gpios, },
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 00000000000000..ae51c108147e33
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+/**
+ * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns: the PCS pointed by data.
+ */
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @fwnode: Firmware node
+ * @get: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS to the global providers list
+ * for the firmware node. A function to get the PCS from
+ * firmware node with the use fwnode reference arguments.
+ * To the get function is also passed the interface type
+ * requested for the PHY. PCS driver will use the passed
+ * interface to understand if the PCS can support it or not.
+ *
+ * Returns: 0 on success or -ENOMEM on allocation failure.
+ */
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @fwnode: Firmware node
+ */
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 00000000000000..45e8f96662db26
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+enum fwnode_pcs_notify_event {
+ FWNODE_PCS_PROVIDER_ADD,
+};
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns: 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
+/**
+ * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Unregisters a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain.
+ *
+ * Returns: 0 or a negative error.
+ */
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb);
+
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -ENODEV if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed).
+ */
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+ unsigned int index);
+
+/**
+ * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
+ * by the firmware node from a
+ * firmware node
+ * @fwnode: firmware node
+ * @pcs_fwnode: PCS firmware node
+ *
+ * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
+ * 'pcs_fwnode' firmware node.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode);
+
+/**
+ * fwnode_phylink_pcs_count - count PCS entries described in firmware node
+ * @fwnode: firmware node
+ *
+ * Helper function to count the number of PCS entries referenced by the
+ * "pcs-handle" property in a firmware node.
+ *
+ * Note that this function counts all PCS references in the firmware node,
+ * regardless of whether the corresponding PCS devices are already probed.
+ *
+ * Returns: number of PCS entries described in the firmware node.
+ */
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode);
+
+/**
+ * fwnode_phylink_pcs_parse - parse available PCS from firmware node
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: maximum number of PCS entries to scan
+ *
+ * Helper function that parses PCS references from the "pcs-handle"
+ * property of a firmware node and fills @available_pcs with PCS that are
+ * currently available up to @num_pcs.
+ *
+ * Only PCS that are currently available are stored in @available_pcs.
+ * PCS that returns -ENODEV are skipped.
+ *
+ * Returns: number of PCS stored in @available_pcs, or negative error code.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs);
+#else
+static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+ unsigned int index)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ return 0;
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 2bc0db3d52ac8d..ecf4c384fd31ca 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -12,6 +12,7 @@ struct ethtool_cmd;
struct fwnode_handle;
struct net_device;
struct phylink;
+struct phylink_pcs;
enum {
MLO_PAUSE_NONE,
@@ -151,6 +152,8 @@ enum phylink_op_type {
* if MAC link is at %MLO_AN_FIXED mode.
* @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
* are supported by the MAC/PCS.
+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
+ * dedicated PCS is required.
* @lpi_interfaces: bitmap describing which PHY interface modes can support
* LPI signalling.
* @mac_capabilities: MAC pause/speed/duplex capabilities.
@@ -160,6 +163,10 @@ enum phylink_op_type {
* @wol_phy_legacy: Use Wake-on-Lan with PHY even if phy_can_wakeup() is false
* @wol_phy_speed_ctrl: Use phy speed control on suspend/resume
* @wol_mac_support: Bitmask of MAC supported %WAKE_* options
+ * @num_possible_pcs: num of possible phylink_pcs PCS
+ * @fill_available_pcs: callback to fill the available PCS in the passed
+ * array struct of phylink_pcs PCS available_pcs up to
+ * num_possible_pcs.
*/
struct phylink_config {
struct device *dev;
@@ -172,6 +179,7 @@ struct phylink_config {
void (*get_fixed_state)(struct phylink_config *config,
struct phylink_link_state *state);
DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+ DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
unsigned long mac_capabilities;
unsigned long lpi_capabilities;
@@ -182,6 +190,11 @@ struct phylink_config {
bool wol_phy_legacy;
bool wol_phy_speed_ctrl;
u32 wol_mac_support;
+
+ unsigned int num_possible_pcs;
+ int (*fill_available_pcs)(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs);
};
void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
@@ -497,6 +510,9 @@ struct phylink_pcs {
struct phylink *phylink;
bool poll;
bool rxc_always_on;
+
+ /* private: */
+ struct list_head list;
};
/**
@@ -512,6 +528,7 @@ struct phylink_pcs {
* @pcs_an_restart: restart 802.3z BaseX autonegotiation.
* @pcs_link_up: program the PCS for the resolved link configuration
* (where necessary).
+ * @pcs_link_down: tear down link between MAC and PCS.
* @pcs_disable_eee: optional notification to PCS that EEE has been disabled
* at the MAC.
* @pcs_enable_eee: optional notification to PCS that EEE will be enabled at
@@ -539,6 +556,7 @@ struct phylink_pcs_ops {
void (*pcs_an_restart)(struct phylink_pcs *pcs);
void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface, int speed, int duplex);
+ void (*pcs_link_down)(struct phylink_pcs *pcs);
void (*pcs_disable_eee)(struct phylink_pcs *pcs);
void (*pcs_enable_eee)(struct phylink_pcs *pcs);
int (*pcs_pre_init)(struct phylink_pcs *pcs);
@@ -674,6 +692,16 @@ void pcs_an_restart(struct phylink_pcs *pcs);
void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface, int speed, int duplex);
+/**
+ * pcs_link_up() - tear down link between MAC and PCS
+ * @pcs: a pointer to a &struct phylink_pcs.
+ *
+ * This call will be made just after mac_link_down() to inform the PCS the
+ * link has gone down. PCS should be configured to stop processing packets
+ * for transmission and reception.
+ */
+void pcs_link_down(struct phylink_pcs *pcs);
+
/**
* pcs_disable_eee() - Disable EEE at the PCS
* @pcs: a pointer to a &struct phylink_pcs
@@ -735,6 +763,8 @@ void phylink_disconnect_phy(struct phylink *);
int phylink_set_fixed_link(struct phylink *,
const struct phylink_link_state *);
+void phylink_release_pcs(struct phylink_pcs *pcs);
+
void phylink_mac_change(struct phylink *, bool up);
void phylink_pcs_change(struct phylink_pcs *, bool up);
|
| 3/2 | 2026/07/17 08:41 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 137335 output: 24 thoughts: 510 Thoughts: **Analyzing the Airoha Ethernet Driver's Reachability** Okay, so we have this patch series introducing a new PCS subsystem and a driver for the Airoha AN7581 PCS. And, critically, it's modifying the Airoha ethernet driver (`drivers/net/ethernet/airoha/airoha_eth.c`) to make use of this new PCS driver. My immediate thought is, what's changed in `airoha_eth.c`? Let's break it down: `airoha_setup_phylink` is being updated to leverage the new PCS. It's now using `fwnode_phylink_pcs_count` and `airoha_fill_available_pcs`. We're setting up `phylink_create`, using `airoha_phylink_ops` which has empty `mac_config` and `mac_link_down`, and a `mac_link_up` that configures TX/RX frag. The PCS driver itself is nestled in `drivers/net/pcs/airoha/`. The core question now is, is this thing even *reachable* in a virtualized environment? The Airoha ethernet driver is a platform driver, specifically for the Airoha AN7581. Let's dig into the details: does it match some existing device? Does it have any kind of probe routine that might run? Yes, it matches the device identifier `airoha,en7581-eth`. Can this be probed? It needs that specific SoC. My gut feeling is, platform drivers like this for specific SoCs are usually a pain to reach without some special QEMU setup, or device tree overlays. I'm recalling the potential of `syz_dev_platform_add` or similar in Syzkaller to inject platform devices. But, remember, we are talking about a hardware-specific driver. However, Syzkaller *can* fuzz platform drivers if the dependencies aren't too complex or it can mock them. But wait, the prompt is very clear: "Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware". So, the key question is: is the Airoha ethernet driver actually reachable from within the confines of our testing setup? I better re-examine that `drivers/net/ethernet/airoha/airoha_eth.c` file! |
| 4/2 | 2026/07/17 08:41 | tool | grepper |
0mArgs:{
"Expression": "airoha,en7581-eth"
}Results: {
"Output": "Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml-3----\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml:4:$id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml=16=properties:\n--\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml-18- enum:\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml:19: - airoha,en7581-eth\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml-20- - airoha,an7583-eth\n--\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml=87=allOf:\n--\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml-93- enum:\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml:94: - airoha,en7581-eth\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml-95- then:\n--\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml=182=examples:\n--\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml-192- eth: ethernet@1fb50000 {\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml:193: compatible = \"airoha,en7581-eth\";\nDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml-194- reg = \u003c0 0x1fb50000 0 0x2600\u003e,\n--\nMAINTAINERS=759=S:\tMaintained\nMAINTAINERS:760:F:\tDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml\nMAINTAINERS-761-F:\tdrivers/net/ethernet/airoha/\n--\narch/arm64/boot/dts/airoha/en7581.dtsi=350=\t\teth: ethernet@1fb50000 {\narch/arm64/boot/dts/airoha/en7581.dtsi:351:\t\t\tcompatible = \"airoha,en7581-eth\";\narch/arm64/boot/dts/airoha/en7581.dtsi-352-\t\t\treg = \u003c0 0x1fb50000 0 0x2600\u003e,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c=3896=static const struct of_device_id of_airoha_match[] = {\ndrivers/net/ethernet/airoha/airoha_eth.c:3897:\t{ .compatible = \"airoha,en7581-eth\", .data = \u0026en7581_soc_data },\ndrivers/net/ethernet/airoha/airoha_eth.c-3898-\t{ .compatible = \"airoha,an7583-eth\", .data = \u0026an7583_soc_data },\n"
} |
| 5/2 | 2026/07/17 08:41 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 139350 output: 18 thoughts: 88 Thoughts: **Analyzing the Airoha EN7581 SoC Driver in QEMU** Okay, so I'm looking at this Airoha EN7581 SoC driver. Specifically, the question is whether I can get it running within a QEMU environment. My initial thought, given my experience, is that I'm likely to hit a wall. Platform drivers, the ones that use `devm_platform_ioremap_resource` and directly access hardware registers, *almost always* implode or at least fail spectacularly during the probe if the underlying hardware isn't actually there. So, I need to check the code to see if this driver is making assumptions it can't rely on in a virtual environment. Let me dive into the `airoha_probe` function within `drivers/net/ethernet/airoha/airoha_eth.c` and see what's really happening. I need to understand exactly how it's interacting with the hardware and if those interactions will cause a problem. |
| 6/2 | 2026/07/17 08:42 | tool | grepper |
0mArgs:{
"Expression": "airoha_probe"
}Results: {
"Output": "drivers/net/ethernet/airoha/airoha_eth.c=3506=static int airoha_register_gdm_devices(struct airoha_eth *eth)\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3534-\ndrivers/net/ethernet/airoha/airoha_eth.c:3535:static int airoha_probe(struct platform_device *pdev)\ndrivers/net/ethernet/airoha/airoha_eth.c-3536-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c=3903=static struct platform_driver airoha_driver = {\ndrivers/net/ethernet/airoha/airoha_eth.c:3904:\t.probe = airoha_probe,\ndrivers/net/ethernet/airoha/airoha_eth.c-3905-\t.remove = airoha_remove,\n"
} |
| 7/2 | 2026/07/17 08:42 | llm | patch-evaluator |
1mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 139915 output: 46 thoughts: 10 Thoughts: Okay, here's my interpretation of that thought process, tailored for an expert audience, and written in the first person: **Initial Assessment: Airoha Probe File** Alright, let's dive in. The instruction suggests we're dealing with `airoha_probe`. I immediately assume this relates to debugging or probing within an Airoha chipset environment. Given my experience, I'm expecting this file to contain critical information for understanding device behavior, likely related to: * **Low-level hardware access:** This could range from register definitions, memory maps, or even instruction traces specific to the Airoha silicon. I need to keep an eye out for elements that could allow me to determine the silicon revsion, or identify potential security vulnerabilities. * **Protocol analysis:** Airoha is commonly used for Bluetooth and Wi-Fi applications. I anticipate protocol-specific data structures, packet dumps, or possibly even firmware loading sequences within this file. The depth of the probing will be important to understanding the communications. * **Debugging symbols:** Depending on the context, there could be symbols that were generated during the creation of a firmware load for the chip. I will keep an eye out for these. I am interested in what is in it, what is recorded in the file, and what I can do with it. The deeper understanding of the file is paramount to my work. |
| 8/2 | 2026/07/17 08:43 | tool | read-file |
0mArgs:{
"File": "drivers/net/ethernet/airoha/airoha_eth.c",
"FirstLine": 3535,
"LineCount": 100
}Results: {
"Contents": "3535:\tstatic int airoha_probe(struct platform_device *pdev)\n3536:\t{\n3537:\t\tstruct reset_control_bulk_data *xsi_rsts;\n3538:\t\tstruct device_node *np;\n3539:\t\tstruct airoha_eth *eth;\n3540:\t\tint i, err;\n3541:\t\n3542:\t\teth = devm_kzalloc(\u0026pdev-\u003edev, sizeof(*eth), GFP_KERNEL);\n3543:\t\tif (!eth)\n3544:\t\t\treturn -ENOMEM;\n3545:\t\n3546:\t\teth-\u003esoc = of_device_get_match_data(\u0026pdev-\u003edev);\n3547:\t\tif (!eth-\u003esoc)\n3548:\t\t\treturn -EINVAL;\n3549:\t\n3550:\t\teth-\u003edev = \u0026pdev-\u003edev;\n3551:\t\n3552:\t\terr = dma_set_mask_and_coherent(eth-\u003edev, DMA_BIT_MASK(32));\n3553:\t\tif (err) {\n3554:\t\t\tdev_err(eth-\u003edev, \"failed configuring DMA mask\\n\");\n3555:\t\t\treturn err;\n3556:\t\t}\n3557:\t\n3558:\t\teth-\u003efe_regs = devm_platform_ioremap_resource_byname(pdev, \"fe\");\n3559:\t\tif (IS_ERR(eth-\u003efe_regs))\n3560:\t\t\treturn dev_err_probe(eth-\u003edev, PTR_ERR(eth-\u003efe_regs),\n3561:\t\t\t\t\t \"failed to iomap fe regs\\n\");\n3562:\t\n3563:\t\teth-\u003ersts[0].id = \"fe\";\n3564:\t\teth-\u003ersts[1].id = \"pdma\";\n3565:\t\teth-\u003ersts[2].id = \"qdma\";\n3566:\t\terr = devm_reset_control_bulk_get_exclusive(eth-\u003edev,\n3567:\t\t\t\t\t\t\t ARRAY_SIZE(eth-\u003ersts),\n3568:\t\t\t\t\t\t\t eth-\u003ersts);\n3569:\t\tif (err) {\n3570:\t\t\tdev_err(eth-\u003edev, \"failed to get bulk reset lines\\n\");\n3571:\t\t\treturn err;\n3572:\t\t}\n3573:\t\n3574:\t\txsi_rsts = devm_kcalloc(eth-\u003edev,\n3575:\t\t\t\t\teth-\u003esoc-\u003enum_xsi_rsts, sizeof(*xsi_rsts),\n3576:\t\t\t\t\tGFP_KERNEL);\n3577:\t\tif (!xsi_rsts)\n3578:\t\t\treturn -ENOMEM;\n3579:\t\n3580:\t\teth-\u003exsi_rsts = xsi_rsts;\n3581:\t\tfor (i = 0; i \u003c eth-\u003esoc-\u003enum_xsi_rsts; i++)\n3582:\t\t\teth-\u003exsi_rsts[i].id = eth-\u003esoc-\u003exsi_rsts_names[i];\n3583:\t\n3584:\t\terr = devm_reset_control_bulk_get_exclusive(eth-\u003edev,\n3585:\t\t\t\t\t\t\t eth-\u003esoc-\u003enum_xsi_rsts,\n3586:\t\t\t\t\t\t\t eth-\u003exsi_rsts);\n3587:\t\tif (err) {\n3588:\t\t\tdev_err(eth-\u003edev, \"failed to get bulk xsi reset lines\\n\");\n3589:\t\t\treturn err;\n3590:\t\t}\n3591:\t\n3592:\t\teth-\u003enapi_dev = alloc_netdev_dummy(0);\n3593:\t\tif (!eth-\u003enapi_dev)\n3594:\t\t\treturn -ENOMEM;\n3595:\t\n3596:\t\t/* Enable threaded NAPI by default */\n3597:\t\teth-\u003enapi_dev-\u003ethreaded = true;\n3598:\t\tstrscpy(eth-\u003enapi_dev-\u003ename, \"qdma_eth\", sizeof(eth-\u003enapi_dev-\u003ename));\n3599:\t\tplatform_set_drvdata(pdev, eth);\n3600:\t\n3601:\t\terr = airoha_hw_init(pdev, eth);\n3602:\t\tif (err)\n3603:\t\t\tgoto error_netdev_free;\n3604:\t\n3605:\t\tfor (i = 0; i \u003c ARRAY_SIZE(eth-\u003eqdma); i++) {\n3606:\t\t\tairoha_qdma_start_napi(\u0026eth-\u003eqdma[i]);\n3607:\t\t\tairoha_qdma_set(\u0026eth-\u003eqdma[i], REG_QDMA_GLOBAL_CFG,\n3608:\t\t\t\t\tGLOBAL_CFG_TX_DMA_EN_MASK |\n3609:\t\t\t\t\tGLOBAL_CFG_RX_DMA_EN_MASK);\n3610:\t\t}\n3611:\t\n3612:\t\tfor_each_child_of_node(pdev-\u003edev.of_node, np) {\n3613:\t\t\tif (!of_device_is_compatible(np, \"airoha,eth-mac\"))\n3614:\t\t\t\tcontinue;\n3615:\t\n3616:\t\t\tif (!of_device_is_available(np))\n3617:\t\t\t\tcontinue;\n3618:\t\n3619:\t\t\terr = airoha_alloc_gdm_port(eth, np);\n3620:\t\t\tif (err) {\n3621:\t\t\t\tof_node_put(np);\n3622:\t\t\t\tgoto error_napi_stop;\n3623:\t\t\t}\n3624:\t\t}\n3625:\t\n3626:\t\terr = airoha_register_gdm_devices(eth);\n3627:\t\tif (err)\n3628:\t\t\tgoto error_napi_stop;\n3629:\t\n3630:\t\treturn 0;\n3631:\t\n3632:\terror_napi_stop:\n3633:\t\tfor (i = 0; i \u003c ARRAY_SIZE(eth-\u003eqdma); i++) {\n3634:\t\t\tairoha_qdma_stop_napi(\u0026eth-\u003eqdma[i]);\n"
} |
| 9/2 | 2026/07/17 08:43 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 141878 output: 45 thoughts: 197 Thoughts: **Analyzing Driver Dependencies in a Virtualized Environment** Okay, so I'm looking at this driver, and it looks like it's pretty dependent on specific hardware resources. It needs `fe` iomem, and reset lines for `fe`, `pdma`, and `qdma`. Right off the bat, I know that this is going to be a problem in a virtualized environment like QEMU. Unless we specifically model these pieces of hardware, the device tree isn't going to have this device at all. Even if we somehow force it in, the probe will probably fail because either the reset lines won't exist or ioremap will crash. Basically, it'll barf when trying to access hardware. Wait a second, syzkaller *can* inject platform devices. But, and this is a big but, it can't magically emulate the actual hardware registers. So any driver that actually tries to read or write to these registers is just going to crash or fail to probe, depending on how robust the error handling is. Hold on... I seem to recall that `devm_platform_ioremap_resource_byname` will just happily map some memory if syzkaller feeds it a dummy resource. Okay, but that means `airoha_hw_init` will probably try to use those mapped addresses. Let's see what that initialization function is doing. I need to dive into `airoha_hw_init`. Let's see... |
| 10/2 | 2026/07/17 08:43 | tool | read-file |
0mArgs:{
"File": "drivers/net/ethernet/airoha/airoha_eth.c",
"FirstLine": 3470,
"LineCount": 50
}Results: {
"Contents": "3470:\t\t\t * external arbiter.\n3471:\t\t\t */\n3472:\t\t\tconst __be32 *nbq_ptr;\n3473:\t\n3474:\t\t\tif (!of_device_is_compatible(node, \"airoha,eth-port\"))\n3475:\t\t\t\tcontinue;\n3476:\t\n3477:\t\t\td++;\n3478:\t\t\tif (!of_device_is_available(node))\n3479:\t\t\t\tcontinue;\n3480:\t\n3481:\t\t\tnbq_ptr = of_get_property(node, \"reg\", NULL);\n3482:\t\t\tif (!nbq_ptr) {\n3483:\t\t\t\tdev_err(eth-\u003edev, \"missing nbq id\\n\");\n3484:\t\t\t\tof_node_put(node);\n3485:\t\t\t\treturn -EINVAL;\n3486:\t\t\t}\n3487:\t\n3488:\t\t\t/* Verify the provided nbq parameter is valid */\n3489:\t\t\tnbq = be32_to_cpup(nbq_ptr);\n3490:\t\t\terr = eth-\u003esoc-\u003eops.get_sport(port, nbq);\n3491:\t\t\tif (err \u003c 0) {\n3492:\t\t\t\tof_node_put(node);\n3493:\t\t\t\treturn err;\n3494:\t\t\t}\n3495:\t\n3496:\t\t\terr = airoha_alloc_gdm_device(eth, port, nbq, node);\n3497:\t\t\tif (err) {\n3498:\t\t\t\tof_node_put(node);\n3499:\t\t\t\treturn err;\n3500:\t\t\t}\n3501:\t\t}\n3502:\t\n3503:\t\treturn !d ? airoha_alloc_gdm_device(eth, port, nbq, np) : 0;\n3504:\t}\n3505:\t\n3506:\tstatic int airoha_register_gdm_devices(struct airoha_eth *eth)\n3507:\t{\n3508:\t\tint i;\n3509:\t\n3510:\t\tfor (i = 0; i \u003c ARRAY_SIZE(eth-\u003eports); i++) {\n3511:\t\t\tstruct airoha_gdm_port *port = eth-\u003eports[i];\n3512:\t\t\tint j;\n3513:\t\n3514:\t\t\tif (!port)\n3515:\t\t\t\tcontinue;\n3516:\t\n3517:\t\t\tfor (j = 0; j \u003c ARRAY_SIZE(port-\u003edevs); j++) {\n3518:\t\t\t\tstruct airoha_gdm_dev *dev = port-\u003edevs[j];\n3519:\t\t\t\tint err;\n"
} |
| 11/2 | 2026/07/17 08:43 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 143152 output: 20 thoughts: 286 Thoughts: **Fuzzing Feasibility Check** Okay, so the task at hand is to determine if this new code is worth fuzzing. The instructions are pretty clear about what constitutes a "no-go" for fuzzing – documentation changes, decorative stuff like logging, harmless constant modifications, and unreachable code paths in virtualized environments. I need to figure out if this patch falls into any of those categories. Hmm, this patch introduces a new PCS subsystem, specifically `drivers/net/pcs/pcs.c`, plus some Airoha driver files under that. The subsystem itself looks generic, with functions like `fwnode_pcs_add_provider` and `fwnode_pcs_get`. The key question is whether this is *reachable* code. The provided prompt gives a lot of very specific and narrow cases that are not worth fuzzing, but the addition of entirely new code seems like it *might* be reachable. Right, so it's used by `airoha_eth.c`, which is a good starting point. But I need to go deeper. Just because it's used by one driver doesn't automatically exclude it from fuzzing. The more interesting question is, is this subsystem used *only* by this one driver? I need to check if those generic PCS functions, like `fwnode_pcs_add_provider` and `fwnode_pcs_get`, are called anywhere else in the code base. That would solidify its relevance. Checking use cases is the most efficient next step. |
| 12/2 | 2026/07/17 08:43 | tool | grepper |
0mArgs:{
"Expression": "fwnode_pcs_"
}Results: {
"Output": "Documentation/networking/pcs.rst=160=To write a PCS driver, first implement :c:struct:`phylink_pcs_ops`. Then,\nDocumentation/networking/pcs.rst:161:register your PCS in your probe function using :c:func:`fwnode_pcs_add_provider`.\nDocumentation/networking/pcs.rst:162:The :c:func:`fwnode_pcs_add_provider` takes three arguments, the fwnode where\nDocumentation/networking/pcs.rst-163-the PCS provider should be registered to, a get function to return the requested\n--\nDocumentation/networking/pcs.rst=170=For the simple case where the PCS driver expose a single PCS,\nDocumentation/networking/pcs.rst:171::c:func:`fwnode_pcs_simple_get` can be used as the get function.\nDocumentation/networking/pcs.rst-172-\nDocumentation/networking/pcs.rst:173:You must call :c:func:`fwnode_pcs_del_provider` from your remove function and\nDocumentation/networking/pcs.rst-174-release the PCS from any phylink instance under RTNL lock with\n--\nDocumentation/networking/pcs.rst-176-\nDocumentation/networking/pcs.rst:177: fwnode_pcs_del_provider(dev_fwnode(\u0026pdev-\u003edev));\nDocumentation/networking/pcs.rst-178-\n--\ndrivers/net/pcs/airoha/pcs-airoha-common.c=1132=static int airoha_pcs_probe(struct platform_device *pdev)\n--\ndrivers/net/pcs/airoha/pcs-airoha-common.c-1249-\ndrivers/net/pcs/airoha/pcs-airoha-common.c:1250:\treturn fwnode_pcs_add_provider(dev_fwnode(dev), airoha_pcs_get, priv);\ndrivers/net/pcs/airoha/pcs-airoha-common.c-1251-}\n--\ndrivers/net/pcs/airoha/pcs-airoha-common.c=1253=static void airoha_pcs_remove(struct platform_device *pdev)\n--\ndrivers/net/pcs/airoha/pcs-airoha-common.c-1258-\ndrivers/net/pcs/airoha/pcs-airoha-common.c:1259:\tfwnode_pcs_del_provider(dev_fwnode(\u0026pdev-\u003edev));\ndrivers/net/pcs/airoha/pcs-airoha-common.c-1260-\n--\ndrivers/net/pcs/pcs.c=11=MODULE_LICENSE(\"GPL\");\ndrivers/net/pcs/pcs.c-12-\ndrivers/net/pcs/pcs.c:13:struct fwnode_pcs_provider {\ndrivers/net/pcs/pcs.c-14-\tstruct list_head link;\n--\ndrivers/net/pcs/pcs.c-22-\ndrivers/net/pcs/pcs.c:23:static LIST_HEAD(fwnode_pcs_providers);\ndrivers/net/pcs/pcs.c:24:static DEFINE_MUTEX(fwnode_pcs_mutex);\ndrivers/net/pcs/pcs.c:25:static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);\ndrivers/net/pcs/pcs.c-26-\ndrivers/net/pcs/pcs.c:27:int register_fwnode_pcs_notifier(struct notifier_block *nb)\ndrivers/net/pcs/pcs.c-28-{\ndrivers/net/pcs/pcs.c:29:\treturn blocking_notifier_chain_register(\u0026fwnode_pcs_notify_list, nb);\ndrivers/net/pcs/pcs.c-30-}\ndrivers/net/pcs/pcs.c:31:EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);\ndrivers/net/pcs/pcs.c-32-\ndrivers/net/pcs/pcs.c:33:int unregister_fwnode_pcs_notifier(struct notifier_block *nb)\ndrivers/net/pcs/pcs.c-34-{\ndrivers/net/pcs/pcs.c:35:\treturn blocking_notifier_chain_unregister(\u0026fwnode_pcs_notify_list, nb);\ndrivers/net/pcs/pcs.c-36-}\ndrivers/net/pcs/pcs.c:37:EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier);\ndrivers/net/pcs/pcs.c-38-\ndrivers/net/pcs/pcs.c:39:struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,\ndrivers/net/pcs/pcs.c-40-\t\t\t\t\t void *data)\n--\ndrivers/net/pcs/pcs.c-43-}\ndrivers/net/pcs/pcs.c:44:EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);\ndrivers/net/pcs/pcs.c-45-\ndrivers/net/pcs/pcs.c:46:int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,\ndrivers/net/pcs/pcs.c-47-\t\t\t struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,\n--\ndrivers/net/pcs/pcs.c-50-{\ndrivers/net/pcs/pcs.c:51:\tstruct fwnode_pcs_provider *pp;\ndrivers/net/pcs/pcs.c-52-\n--\ndrivers/net/pcs/pcs.c-63-\ndrivers/net/pcs/pcs.c:64:\tmutex_lock(\u0026fwnode_pcs_mutex);\ndrivers/net/pcs/pcs.c:65:\tlist_add(\u0026pp-\u003elink, \u0026fwnode_pcs_providers);\ndrivers/net/pcs/pcs.c:66:\tmutex_unlock(\u0026fwnode_pcs_mutex);\ndrivers/net/pcs/pcs.c-67-\tpr_debug(\"Added pcs provider from %pfwf\\n\", fwnode);\n--\ndrivers/net/pcs/pcs.c-70-\ndrivers/net/pcs/pcs.c:71:\tblocking_notifier_call_chain(\u0026fwnode_pcs_notify_list,\ndrivers/net/pcs/pcs.c-72-\t\t\t\t FWNODE_PCS_PROVIDER_ADD,\n--\ndrivers/net/pcs/pcs.c-76-}\ndrivers/net/pcs/pcs.c:77:EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);\ndrivers/net/pcs/pcs.c-78-\ndrivers/net/pcs/pcs.c:79:void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)\ndrivers/net/pcs/pcs.c-80-{\ndrivers/net/pcs/pcs.c:81:\tstruct fwnode_pcs_provider *pp;\ndrivers/net/pcs/pcs.c-82-\n--\ndrivers/net/pcs/pcs.c-85-\ndrivers/net/pcs/pcs.c:86:\tmutex_lock(\u0026fwnode_pcs_mutex);\ndrivers/net/pcs/pcs.c:87:\tlist_for_each_entry(pp, \u0026fwnode_pcs_providers, link) {\ndrivers/net/pcs/pcs.c-88-\t\tif (pp-\u003efwnode == fwnode) {\n--\ndrivers/net/pcs/pcs.c-95-\t}\ndrivers/net/pcs/pcs.c:96:\tmutex_unlock(\u0026fwnode_pcs_mutex);\ndrivers/net/pcs/pcs.c-97-}\ndrivers/net/pcs/pcs.c:98:EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);\ndrivers/net/pcs/pcs.c-99-\n--\ndrivers/net/pcs/pcs.c=125=static struct phylink_pcs *\ndrivers/net/pcs/pcs.c:126:fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)\ndrivers/net/pcs/pcs.c-127-{\ndrivers/net/pcs/pcs.c:128:\tstruct fwnode_pcs_provider *provider;\ndrivers/net/pcs/pcs.c-129-\tstruct phylink_pcs *pcs = ERR_PTR(-ENODEV);\n--\ndrivers/net/pcs/pcs.c-133-\ndrivers/net/pcs/pcs.c:134:\tmutex_lock(\u0026fwnode_pcs_mutex);\ndrivers/net/pcs/pcs.c:135:\tlist_for_each_entry(provider, \u0026fwnode_pcs_providers, link) {\ndrivers/net/pcs/pcs.c-136-\t\tif (provider-\u003efwnode == pcsspec-\u003efwnode) {\n--\ndrivers/net/pcs/pcs.c-141-\t}\ndrivers/net/pcs/pcs.c:142:\tmutex_unlock(\u0026fwnode_pcs_mutex);\ndrivers/net/pcs/pcs.c-143-\n--\ndrivers/net/pcs/pcs.c-146-\ndrivers/net/pcs/pcs.c:147:static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,\ndrivers/net/pcs/pcs.c-148-\t\t\t\t\t unsigned int index, const char *con_id)\n--\ndrivers/net/pcs/pcs.c-157-\ndrivers/net/pcs/pcs.c:158:\tpcs = fwnode_pcs_get_from_pcsspec(\u0026pcsspec);\ndrivers/net/pcs/pcs.c-159-\tfwnode_handle_put(pcsspec.fwnode);\n--\ndrivers/net/pcs/pcs.c-163-\ndrivers/net/pcs/pcs.c:164:struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, unsigned int index)\ndrivers/net/pcs/pcs.c-165-{\ndrivers/net/pcs/pcs.c:166:\treturn __fwnode_pcs_get(fwnode, index, NULL);\ndrivers/net/pcs/pcs.c-167-}\ndrivers/net/pcs/pcs.c:168:EXPORT_SYMBOL_GPL(fwnode_pcs_get);\ndrivers/net/pcs/pcs.c-169-\n--\ndrivers/net/pcs/pcs.c=171=fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,\n--\ndrivers/net/pcs/pcs.c-197-\ndrivers/net/pcs/pcs.c:198:\treturn fwnode_pcs_get(fwnode, index);\ndrivers/net/pcs/pcs.c-199-}\n--\ndrivers/net/pcs/pcs.c=224=int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,\n--\ndrivers/net/pcs/pcs.c-238-\ndrivers/net/pcs/pcs.c:239:\t\tpcs = fwnode_pcs_get(fwnode, i);\ndrivers/net/pcs/pcs.c-240-\t\tif (IS_ERR(pcs)) {\n--\ndrivers/net/phy/phylink.c=42=struct phylink {\n--\ndrivers/net/phy/phylink.c-65-\tstruct list_head pcs_list;\ndrivers/net/phy/phylink.c:66:\tstruct notifier_block fwnode_pcs_nb;\ndrivers/net/phy/phylink.c-67-\n--\ndrivers/net/phy/phylink.c=2013=static int pcs_provider_notify(struct notifier_block *self,\n--\ndrivers/net/phy/phylink.c-2015-{\ndrivers/net/phy/phylink.c:2016:\tstruct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);\ndrivers/net/phy/phylink.c-2017-\tstruct fwnode_handle *pcs_fwnode = data;\n--\ndrivers/net/phy/phylink.c=2076=struct phylink *phylink_create(struct phylink_config *config,\n--\ndrivers/net/phy/phylink.c-2178-\tif (!phy_interface_empty(config-\u003epcs_interfaces)) {\ndrivers/net/phy/phylink.c:2179:\t\tpl-\u003efwnode_pcs_nb.notifier_call = pcs_provider_notify;\ndrivers/net/phy/phylink.c:2180:\t\tregister_fwnode_pcs_notifier(\u0026pl-\u003efwnode_pcs_nb);\ndrivers/net/phy/phylink.c-2181-\t}\n--\ndrivers/net/phy/phylink.c=2203=void phylink_destroy(struct phylink *pl)\n--\ndrivers/net/phy/phylink.c-2211-\t/* Unregister notifier for late PCS attach */\ndrivers/net/phy/phylink.c:2212:\tif (pl-\u003efwnode_pcs_nb.notifier_call)\ndrivers/net/phy/phylink.c:2213:\t\tunregister_fwnode_pcs_notifier(\u0026pl-\u003efwnode_pcs_nb);\ndrivers/net/phy/phylink.c-2214-\n--\ninclude/linux/pcs/pcs-provider.h-5-/**\ninclude/linux/pcs/pcs-provider.h:6: * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS\ninclude/linux/pcs/pcs-provider.h-7- * @pcsspec: reference arguments\n--\ninclude/linux/pcs/pcs-provider.h-11- */\ninclude/linux/pcs/pcs-provider.h:12:struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,\ninclude/linux/pcs/pcs-provider.h-13-\t\t\t\t\t void *data);\n--\ninclude/linux/pcs/pcs-provider.h-15-/**\ninclude/linux/pcs/pcs-provider.h:16: * fwnode_pcs_add_provider - Registers a new PCS provider\ninclude/linux/pcs/pcs-provider.h-17- * @fwnode: Firmware node\n--\ninclude/linux/pcs/pcs-provider.h-29- */\ninclude/linux/pcs/pcs-provider.h:30:int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,\ninclude/linux/pcs/pcs-provider.h-31-\t\t\t struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,\n--\ninclude/linux/pcs/pcs-provider.h-35-/**\ninclude/linux/pcs/pcs-provider.h:36: * fwnode_pcs_del_provider - Removes a PCS provider\ninclude/linux/pcs/pcs-provider.h-37- * @fwnode: Firmware node\ninclude/linux/pcs/pcs-provider.h-38- */\ninclude/linux/pcs/pcs-provider.h:39:void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);\ninclude/linux/pcs/pcs-provider.h-40-\n--\ninclude/linux/pcs/pcs.h-6-\ninclude/linux/pcs/pcs.h:7:enum fwnode_pcs_notify_event {\ninclude/linux/pcs/pcs.h-8-\tFWNODE_PCS_PROVIDER_ADD,\n--\ninclude/linux/pcs/pcs.h-12-/**\ninclude/linux/pcs/pcs.h:13: * register_fwnode_pcs_notifier - Register a notifier block for fwnode\ninclude/linux/pcs/pcs.h-14- *\t\t\t\t PCS events\n--\ninclude/linux/pcs/pcs.h-16- *\ninclude/linux/pcs/pcs.h:17: * Registers a notifier block to the fwnode_pcs_notify_list blocking\ninclude/linux/pcs/pcs.h-18- * notifier chain. This allows phylink instance to subscribe for\n--\ninclude/linux/pcs/pcs.h-22- */\ninclude/linux/pcs/pcs.h:23:int register_fwnode_pcs_notifier(struct notifier_block *nb);\ninclude/linux/pcs/pcs.h-24-\ninclude/linux/pcs/pcs.h-25-/**\ninclude/linux/pcs/pcs.h:26: * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode\ninclude/linux/pcs/pcs.h-27- *\t\t\t\t PCS events\n--\ninclude/linux/pcs/pcs.h-29- *\ninclude/linux/pcs/pcs.h:30: * Unregisters a notifier block to the fwnode_pcs_notify_list blocking\ninclude/linux/pcs/pcs.h-31- * notifier chain.\n--\ninclude/linux/pcs/pcs.h-34- */\ninclude/linux/pcs/pcs.h:35:int unregister_fwnode_pcs_notifier(struct notifier_block *nb);\ninclude/linux/pcs/pcs.h-36-\ninclude/linux/pcs/pcs.h-37-/**\ninclude/linux/pcs/pcs.h:38: * fwnode_pcs_get - Retrieves a PCS from a firmware node\ninclude/linux/pcs/pcs.h-39- * @fwnode: firmware node\n--\ninclude/linux/pcs/pcs.h-48- */\ninclude/linux/pcs/pcs.h:49:struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,\ninclude/linux/pcs/pcs.h-50-\t\t\t\t unsigned int index);\n--\ninclude/linux/pcs/pcs.h=100=int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,\n--\ninclude/linux/pcs/pcs.h-103-#else\ninclude/linux/pcs/pcs.h:104:static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)\ninclude/linux/pcs/pcs.h-105-{\n--\ninclude/linux/pcs/pcs.h-108-\ninclude/linux/pcs/pcs.h:109:static inline int unregister_fwnode_pcs_notifier(struct notifier_block *nb)\ninclude/linux/pcs/pcs.h-110-{\n--\ninclude/linux/pcs/pcs.h-113-\ninclude/linux/pcs/pcs.h:114:static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,\ninclude/linux/pcs/pcs.h-115-\t\t\t\t\t\t unsigned int index)\n"
} |
| 13/2 | 2026/07/17 08:43 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 148481 output: 47 thoughts: 203 Thoughts: **Analyzing the PCS Subsystem's Usage** Okay, so the PCS subsystem, as the code indicates, is currently exclusive to the Airoha driver. That much is clear. Let's dig deeper. The critical function, `fwnode_pcs_add_provider`, is *only* called within `drivers/net/pcs/airoha/pcs-airoha-common.c`. I need to confirm that this file is actually reachable within the build and that it isn't some vestigial code. Right, it's a platform driver. That's good; makes things easier to track. I see the `airoha_pcs_driver` structure defined, with the driver name "airoha-pcs" and an OF match table. This means it's driven by device tree information. If syzkaller, for instance, were to generate a platform device entry with the compatible string "airoha,an7581-pcs-eth", the probe function, `airoha_pcs_probe`, would be executed. I need to take a look at that probe function. It's the point of entry and will reveal how the PCS subsystem is actually used in this specific Airoha context. |
| 14/2 | 2026/07/17 08:44 | tool | read-file |
0mArgs:{
"File": "drivers/net/pcs/airoha/pcs-airoha-common.c",
"FirstLine": 1132,
"LineCount": 100
}Results: {
"Contents": "1132:\tstatic int airoha_pcs_probe(struct platform_device *pdev)\n1133:\t{\n1134:\t\tconst struct airoha_pcs_match_data *data;\n1135:\t\tstruct device *dev = \u0026pdev-\u003edev;\n1136:\t\tstruct airoha_pcs_priv *priv;\n1137:\t\tint index, ret;\n1138:\t\n1139:\t\tdata = of_device_get_match_data(dev);\n1140:\t\n1141:\t\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n1142:\t\tif (!priv)\n1143:\t\t\treturn -ENOMEM;\n1144:\t\n1145:\t\tpriv-\u003eports = devm_kcalloc(dev, data-\u003enum_port,\n1146:\t\t\t\t\t sizeof(*priv-\u003eports), GFP_KERNEL);\n1147:\t\tif (!priv-\u003eports)\n1148:\t\t\treturn -ENOMEM;\n1149:\t\n1150:\t\tpriv-\u003edev = dev;\n1151:\t\tpriv-\u003edata = data;\n1152:\t\n1153:\t\tif (data-\u003eport_type == AIROHA_PCS_USB) {\n1154:\t\t\tstruct phy *phy;\n1155:\t\n1156:\t\t\tphy = devm_phy_get(dev, NULL);\n1157:\t\t\tif (IS_ERR(phy))\n1158:\t\t\t\treturn dev_err_probe(dev, PTR_ERR(phy), \"failed to get phy\\n\");\n1159:\t\n1160:\t\t\tpriv-\u003ephy = phy;\n1161:\t\t}\n1162:\t\n1163:\t\tswitch (data-\u003eport_type) {\n1164:\t\tcase AIROHA_PCS_ETH:\n1165:\t\tcase AIROHA_PCS_PON:\n1166:\t\t\tret = airoha_pcs_alloc_maps(pdev, priv);\n1167:\t\t\tif (ret)\n1168:\t\t\t\treturn ret;\n1169:\t\n1170:\t\t\tbreak;\n1171:\t\tcase AIROHA_PCS_PCIE:\n1172:\t\t\tret = airoha_pcs_pcie_alloc_maps(pdev, priv);\n1173:\t\t\tif (ret)\n1174:\t\t\t\treturn ret;\n1175:\t\n1176:\t\t\tbreak;\n1177:\t\tcase AIROHA_PCS_USB:\n1178:\t\t\tret = airoha_pcs_usb_alloc_maps(pdev, priv);\n1179:\t\t\tif (ret)\n1180:\t\t\t\treturn ret;\n1181:\t\n1182:\t\t\tbreak;\n1183:\t\t}\n1184:\t\n1185:\t\tif (data-\u003ealloc_regmap_fields) {\n1186:\t\t\tret = data-\u003ealloc_regmap_fields(priv);\n1187:\t\t\tif (ret)\n1188:\t\t\t\treturn ret;\n1189:\t\t}\n1190:\t\n1191:\t\t/* SCU is used to toggle XFI or HSGMII in global SoC registers */\n1192:\t\tif (!priv-\u003ephy) {\n1193:\t\t\tpriv-\u003escu = syscon_regmap_lookup_by_phandle(dev-\u003eof_node, \"airoha,scu\");\n1194:\t\t\tif (IS_ERR(priv-\u003escu))\n1195:\t\t\t\treturn PTR_ERR(priv-\u003escu);\n1196:\t\t}\n1197:\t\n1198:\t\tpriv-\u003ersts[0].id = \"mac\";\n1199:\t\tpriv-\u003ersts[1].id = \"phy\";\n1200:\t\tret = devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(priv-\u003ersts),\n1201:\t\t\t\t\t\t\t\t priv-\u003ersts);\n1202:\t\tif (ret)\n1203:\t\t\treturn dev_err_probe(dev, ret, \"failed to get bulk reset lines\\n\");\n1204:\t\n1205:\t\t/* For Ethernet PCS, read the AN7581 SoC revision to check if\n1206:\t\t * manual rx calibration is needed. This is only limited to\n1207:\t\t * any SoC revision before E2.\n1208:\t\t */\n1209:\t\tif (device_is_compatible(dev, \"airoha,an7581-pcs-eth\")) {\n1210:\t\t\tu32 val;\n1211:\t\n1212:\t\t\tret = regmap_read(priv-\u003escu, AIROHA_SCU_PDIDR, \u0026val);\n1213:\t\t\tif (ret)\n1214:\t\t\t\treturn ret;\n1215:\t\n1216:\t\t\tif (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) \u003c 0x2)\n1217:\t\t\t\tpriv-\u003emanual_rx_calib = true;\n1218:\t\t}\n1219:\t\n1220:\t\tfor (index = 0; index \u003c data-\u003enum_port; index++) {\n1221:\t\t\tstruct airoha_pcs_port *port = \u0026priv-\u003eports[index];\n1222:\t\n1223:\t\t\tport-\u003epriv = priv;\n1224:\t\t\tport-\u003eindex = index;\n1225:\t\t\tport-\u003epcs.poll = true;\n1226:\t\t\tport-\u003epcs.ops = \u0026airoha_pcs_ops;\n1227:\t\n1228:\t\t\tswitch (data-\u003eport_type) {\n1229:\t\t\tcase AIROHA_PCS_ETH:\n1230:\t\t\tcase AIROHA_PCS_PON:\n1231:\t\t\tcase AIROHA_PCS_PCIE:\n"
} |
| 15/2 | 2026/07/17 08:44 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 150499 output: 40 thoughts: 394 Thoughts: **Analyzing the Potential Vulnerability in Airoha PCS Driver** Okay, so I'm looking at this Airoha PCS driver and immediately see that `airoha_pcs_alloc_maps` calls `airoha_pcs_init_named_regmap`, which is responsible for mapping memory regions. Specifically, it uses `devm_platform_ioremap_resource_byname` to do this mapping. The function itself, `airoha_pcs_init_named_regmap`, looks fairly standard using a `regmap`. Now, the interesting thing here is that syzkaller is mentioned. It seems if syzkaller creates a platform device, it can potentially provide dummy resources. The key piece is `syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu")`. My first instinct is, if "airoha,scu" isn't present in the device tree, that lookup will fail. And while syzkaller can inject device tree nodes, constructing a *valid* one with all these dependencies (syscon, phy, reset lines, etc.) for this hardware-specific driver is a pretty low probability. It would likely just end up reading/writing to dummy memory. It's a risk, but it does not immediately present a massive attack vector. But, the real point here is that the patch also modifies `drivers/net/phy/phylink.c`. *That's* the part that has me a little concerned. `phylink.c` is core networking code, used by all sorts of different drivers. Given that this is a network stack issue, I'm going to take a closer look at the changes there because that's where the real potential for a serious vulnerability will lie. I'm going to start with the `phylink.c` changes and see if anything jumps out. |
| 16/2 | 2026/07/17 08:44 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 1970,
"LineCount": 100
}Results: {
"Contents": "1970:\t\n1971:\t\treturn 0;\n1972:\t}\n1973:\tEXPORT_SYMBOL_GPL(phylink_set_fixed_link);\n1974:\t\n1975:\tstatic int phylink_fill_available_pcs(struct phylink *pl,\n1976:\t\t\t\t\t struct phylink_config *config)\n1977:\t{\n1978:\t\tstruct phylink_pcs **pcss;\n1979:\t\tint i, ret;\n1980:\t\n1981:\t\tif (!config-\u003enum_possible_pcs)\n1982:\t\t\treturn 0;\n1983:\t\n1984:\t\tif (!config-\u003efill_available_pcs) {\n1985:\t\t\tdev_err(config-\u003edev,\n1986:\t\t\t\t\"phylink: error: num_possible_pcs defined but no fill_available_pcs\\n\");\n1987:\t\t\treturn -EINVAL;\n1988:\t\t}\n1989:\t\n1990:\t\tpcss = kzalloc_objs(*pcss, config-\u003enum_possible_pcs);\n1991:\t\tif (!pcss)\n1992:\t\t\treturn -ENOMEM;\n1993:\t\n1994:\t\tret = config-\u003efill_available_pcs(config, pcss, config-\u003enum_possible_pcs);\n1995:\t\tif (ret \u003c 0)\n1996:\t\t\tgoto out;\n1997:\t\n1998:\t\tfor (i = 0; i \u003c config-\u003enum_possible_pcs; i++) {\n1999:\t\t\tstruct phylink_pcs *pcs = pcss[i];\n2000:\t\n2001:\t\t\tif (!pcs)\n2002:\t\t\t\tcontinue;\n2003:\t\n2004:\t\t\tlist_add(\u0026pcs-\u003elist, \u0026pl-\u003epcs_list);\n2005:\t\t}\n2006:\t\n2007:\tout:\n2008:\t\tkfree(pcss);\n2009:\t\n2010:\t\treturn ret;\n2011:\t}\n2012:\t\n2013:\tstatic int pcs_provider_notify(struct notifier_block *self,\n2014:\t\t\t\t unsigned long val, void *data)\n2015:\t{\n2016:\t\tstruct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);\n2017:\t\tstruct fwnode_handle *pcs_fwnode = data;\n2018:\t\tstruct phylink_pcs *pcs;\n2019:\t\n2020:\t\trtnl_lock();\n2021:\t\n2022:\t\t/* Check if the just added PCS provider is\n2023:\t\t * in the phylink instance pcs-handle property.\n2024:\t\t */\n2025:\t\tpcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl-\u003econfig-\u003edev),\n2026:\t\t\t\t\t\t\t pcs_fwnode);\n2027:\t\tif (IS_ERR(pcs)) {\n2028:\t\t\trtnl_unlock();\n2029:\t\t\treturn NOTIFY_DONE;\n2030:\t\t}\n2031:\t\n2032:\t\t/* Add the PCS */\n2033:\t\tmutex_lock(\u0026pl-\u003estate_mutex);\n2034:\t\n2035:\t\t/* Link PCS with phylink */\n2036:\t\tlist_add(\u0026pcs-\u003elist, \u0026pl-\u003epcs_list);\n2037:\t\tpcs-\u003ephylink = pl;\n2038:\t\n2039:\t\t/* Refresh supported interfaces */\n2040:\t\tphy_interface_copy(pl-\u003esupported_interfaces,\n2041:\t\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n2042:\t\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n2043:\t\t\tphy_interface_or(pl-\u003esupported_interfaces,\n2044:\t\t\t\t\t pl-\u003esupported_interfaces,\n2045:\t\t\t\t\t pcs-\u003esupported_interfaces);\n2046:\t\n2047:\t\t/* Force an interface reconfig if major config fail */\n2048:\t\tif (pl-\u003emajor_config_failed)\n2049:\t\t\tpl-\u003eforce_major_config = true;\n2050:\t\n2051:\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n2052:\t\n2053:\t\trtnl_unlock();\n2054:\t\n2055:\t\tphylink_run_resolve(pl);\n2056:\t\n2057:\t\treturn NOTIFY_OK;\n2058:\t}\n2059:\t\n2060:\t/**\n2061:\t * phylink_create() - create a phylink instance\n2062:\t * @config: a pointer to the target \u0026struct phylink_config\n2063:\t * @fwnode: a pointer to a \u0026struct fwnode_handle describing the network\n2064:\t *\tinterface\n2065:\t * @iface: the desired link mode defined by \u0026typedef phy_interface_t\n2066:\t * @mac_ops: a pointer to a \u0026struct phylink_mac_ops for the MAC.\n2067:\t *\n2068:\t * Create a new phylink instance, and parse the link parameters found in @np.\n2069:\t * This will parse in-band modes, fixed-link or SFP configuration.\n"
} |
| 17/2 | 2026/07/17 08:44 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 152755 output: 19 thoughts: 122 Thoughts: **Analyzing the Phylink Modification** Okay, so this patch is digging into `phylink`, which, as I recall, is a pretty fundamental subsystem for a ton of Ethernet drivers. It seems to be touching several key functions like `phylink_create`, `phylink_destroy`, the MAC and PCS validation, resource release and major configuration routines. I need to understand the implications of these changes, given how deeply ingrained `phylink` is. Ah, but it looks like the new functionality here is conditionally enabled. It's only going to kick in if either `config->num_possible_pcs` or `config->pcs_interfaces` are set within the configuration. That's good; it prevents unnecessary regressions across the board. Now the question is, *who* is using these new parameters? I need to quickly identify if any other drivers in the system are already leveraging these configuration options. I'll need to know which of our supported hardware this will affect. Let's start digging. |
| 18/2 | 2026/07/17 08:45 | tool | grepper |
0mArgs:{
"Expression": "num_possible_pcs"
}Results: {
"Output": "Documentation/networking/pcs.rst=38=used by similar subsystems with a ``#pcs-cells`` on the producer and a\n--\nDocumentation/networking/pcs.rst-50-\nDocumentation/networking/pcs.rst:51:On :c:func:`phylink_create`, phylink will use the ``num_possible_pcs``\nDocumentation/networking/pcs.rst-52-value and ``fill_available_pcs`` helper function in\n--\nDocumentation/networking/pcs.rst=69=and a dedicated driver is not needed, it's possible to leave the implementation\nDocumentation/networking/pcs.rst:70:of the PCS to the MAC driver and just implement the ``num_possible_pcs``\nDocumentation/networking/pcs.rst-71-value and ``fill_available_pcs`` helper function in\n--\nDocumentation/networking/pcs.rst=78=It's mandatory to either implement the ``mac_select_pcs`` callback\nDocumentation/networking/pcs.rst:79:of :c:struct:`phylink_mac_ops` or ``num_possible_pcs`` and ``fill_available_pcs``\nDocumentation/networking/pcs.rst-80-of :c:struct:`phylink_config` to use a PCS for a MAC.\n--\nDocumentation/networking/pcs.rst=96=A phylink instance may use multiple PCS devices. The maximum number is reported\nDocumentation/networking/pcs.rst:97:through ``num_possible_pcs``.\nDocumentation/networking/pcs.rst-98-\n--\nDocumentation/networking/pcs.rst=106=is the following::\n--\nDocumentation/networking/pcs.rst-109- \t\t\t\t struct phylink_pcs **available_pcs,\nDocumentation/networking/pcs.rst:110:\t\t\t\t\t unsigned int num_possible_pcs)\nDocumentation/networking/pcs.rst-111- {\n--\nDocumentation/networking/pcs.rst-114- \treturn fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,\nDocumentation/networking/pcs.rst:115:\t\t\t\t\t\t num_possible_pcs);\nDocumentation/networking/pcs.rst-116- }\n--\nDocumentation/networking/pcs.rst-127-\nDocumentation/networking/pcs.rst:128: // Parse possible PCS and fill num_possible_pcs.\nDocumentation/networking/pcs.rst:129: config-\u003enum_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(\u0026netdev-\u003edev));\nDocumentation/networking/pcs.rst-130- config-\u003efill_available_pcs = mac_fill_available_pcs;\n--\nDocumentation/networking/pcs.rst=143=the array of :c:struct:`phylink_pcs` pointer for ``fill_available_pcs``\nDocumentation/networking/pcs.rst:144:callback based on the value set in ``num_possible_pcs`` for\nDocumentation/networking/pcs.rst-145-:c:struct:`phylink_config` struct.\n--\nDocumentation/networking/pcs.rst=147=The ``fill_available_pcs`` callback must not write more than\nDocumentation/networking/pcs.rst:148:``num_possible_pcs`` entries. The third argument may be used to validate\nDocumentation/networking/pcs.rst-149-that there is enough space to fill all the available PCS in the passed array\n--\ndrivers/net/ethernet/airoha/airoha_eth.c=3287=static int airoha_fill_available_pcs(struct phylink_config *config,\ndrivers/net/ethernet/airoha/airoha_eth.c-3288-\t\t\t\t struct phylink_pcs **available_pcs,\ndrivers/net/ethernet/airoha/airoha_eth.c:3289:\t\t\t\t unsigned int num_possible_pcs)\ndrivers/net/ethernet/airoha/airoha_eth.c-3290-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3293-\treturn fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,\ndrivers/net/ethernet/airoha/airoha_eth.c:3294:\t\t\t\t\tnum_possible_pcs);\ndrivers/net/ethernet/airoha/airoha_eth.c-3295-}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c=3297=static int airoha_setup_phylink(struct net_device *netdev)\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3331-\ndrivers/net/ethernet/airoha/airoha_eth.c:3332:\t\tconfig-\u003enum_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config-\u003edev));\ndrivers/net/ethernet/airoha/airoha_eth.c-3333-\t\tconfig-\u003efill_available_pcs = airoha_fill_available_pcs;\n--\ndrivers/net/phy/phylink.c=1975=static int phylink_fill_available_pcs(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-1980-\ndrivers/net/phy/phylink.c:1981:\tif (!config-\u003enum_possible_pcs)\ndrivers/net/phy/phylink.c-1982-\t\treturn 0;\n--\ndrivers/net/phy/phylink.c-1985-\t\tdev_err(config-\u003edev,\ndrivers/net/phy/phylink.c:1986:\t\t\t\"phylink: error: num_possible_pcs defined but no fill_available_pcs\\n\");\ndrivers/net/phy/phylink.c-1987-\t\treturn -EINVAL;\n--\ndrivers/net/phy/phylink.c-1989-\ndrivers/net/phy/phylink.c:1990:\tpcss = kzalloc_objs(*pcss, config-\u003enum_possible_pcs);\ndrivers/net/phy/phylink.c-1991-\tif (!pcss)\n--\ndrivers/net/phy/phylink.c-1993-\ndrivers/net/phy/phylink.c:1994:\tret = config-\u003efill_available_pcs(config, pcss, config-\u003enum_possible_pcs);\ndrivers/net/phy/phylink.c-1995-\tif (ret \u003c 0)\n--\ndrivers/net/phy/phylink.c-1997-\ndrivers/net/phy/phylink.c:1998:\tfor (i = 0; i \u003c config-\u003enum_possible_pcs; i++) {\ndrivers/net/phy/phylink.c-1999-\t\tstruct phylink_pcs *pcs = pcss[i];\n--\ndrivers/net/phy/phylink.c=2076=struct phylink *phylink_create(struct phylink_config *config,\n--\ndrivers/net/phy/phylink.c-2088-\t */\ndrivers/net/phy/phylink.c:2089:\tif (config-\u003enum_possible_pcs \u0026\u0026 mac_ops-\u003emac_select_pcs) {\ndrivers/net/phy/phylink.c-2090-\t\tdev_err(config-\u003edev,\ndrivers/net/phy/phylink.c:2091:\t\t\t\"phylink: error: either phylink_config .num_possible_pcs or .mac_select_pcs must be used\\n\");\ndrivers/net/phy/phylink.c-2092-\t\treturn ERR_PTR(-EINVAL);\n--\ninclude/linux/phylink.h=133=enum phylink_op_type {\n--\ninclude/linux/phylink.h-165- * @wol_mac_support: Bitmask of MAC supported %WAKE_* options\ninclude/linux/phylink.h:166: * @num_possible_pcs: num of possible phylink_pcs PCS\ninclude/linux/phylink.h-167- * @fill_available_pcs: callback to fill the available PCS in the passed\ninclude/linux/phylink.h-168- *\t\t\tarray struct of phylink_pcs PCS available_pcs up to\ninclude/linux/phylink.h:169: *\t\t\tnum_possible_pcs.\ninclude/linux/phylink.h-170- */\ninclude/linux/phylink.h=171=struct phylink_config {\n--\ninclude/linux/phylink.h-193-\ninclude/linux/phylink.h:194:\tunsigned int num_possible_pcs;\ninclude/linux/phylink.h-195-\tint (*fill_available_pcs)(struct phylink_config *config,\ninclude/linux/phylink.h-196-\t\t\t\t struct phylink_pcs **available_pcs,\ninclude/linux/phylink.h:197:\t\t\t\t unsigned int num_possible_pcs);\ninclude/linux/phylink.h-198-};\n"
} |
| 19/2 | 2026/07/17 08:45 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 155306 output: 17 thoughts: 39 Thoughts: Okay, here's my interpretation of those thoughts, framed as an expert's internal monologue: **Investigating Driver Initialization** Right, so I'm digging into this driver code and I see something that jumps out. It looks like the `num_possible_pcs` and `pcs_interfaces` variables – these are crucial for hardware configuration, if I'm remembering correctly – are *only* set within the Airoha driver. That's a bit of a red flag, right? Makes me want to understand the dependencies and if this is intended functionality or just a historical side effect. Wait, let me double-check that `pcs_interfaces` thing... yeah, it appears that *also* is exclusively managed by the Airoha driver. Okay, so all of this is specific to this chip manufacturer. I'd like to understand how this Airoha Driver handles these variables, and how they interact with the core functionality. I'll need to follow the data flow to ensure there are no unintended consequences when working with other drivers. |
| 20/2 | 2026/07/17 08:46 | tool | grepper |
0mArgs:{
"Expression": "pcs_interfaces"
}Results: {
"Output": "Documentation/networking/pcs.rst=57=the requested interface mode based on the interface modes configured in\nDocumentation/networking/pcs.rst:58:``pcs_interfaces`` in :c:struct:`phylink_config` struct and\nDocumentation/networking/pcs.rst-59-``supported_interfaces`` in :c:struct:`phylink_pcs` struct.\n--\nDocumentation/networking/pcs.rst=61=A PCS is considered eligible when the requested interface mode is present\nDocumentation/networking/pcs.rst:62:in both ``pcs_interfaces`` in :c:struct:`phylink_config` struct and\nDocumentation/networking/pcs.rst-63-``supported_interfaces`` in :c:struct:`phylink_pcs` struct.\n--\nDocumentation/networking/pcs.rst-65-``supported_interfaces`` describes all interface modes supported by the MAC,\nDocumentation/networking/pcs.rst:66:whereas ``pcs_interfaces`` identifies the subset that require PCS selection.\nDocumentation/networking/pcs.rst-67-\n--\nDocumentation/networking/pcs.rst=99=It's mandatory to specify for what interface a PCS is needed. This can be done\nDocumentation/networking/pcs.rst:100:by filling the ``pcs_interfaces`` in :c:struct:`phylink_config` struct.\nDocumentation/networking/pcs.rst-101-If the requested interface mode is not present in this bitmask, phylink does\n--\nDocumentation/networking/pcs.rst=106=is the following::\n--\nDocumentation/networking/pcs.rst-137- // PCS required only for USXGMII\nDocumentation/networking/pcs.rst:138: __set_bit(PHY_INTERFACE_MODE_USXGMII, config-\u003epcs_interfaces);\nDocumentation/networking/pcs.rst-139-\n--\nDocumentation/networking/pcs.rst=204=The PCS fwnode implementation provides a notifier to which each phylink\nDocumentation/networking/pcs.rst:205:instance with a non-empty ``pcs_interfaces`` in :c:type:`phylink_config`\nDocumentation/networking/pcs.rst-206-registers. When a new PCS provider is registered, the notifier is called\n--\ndrivers/net/ethernet/airoha/airoha_eth.c=3297=static int airoha_setup_phylink(struct net_device *netdev)\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3345-\ndrivers/net/ethernet/airoha/airoha_eth.c:3346:\t\tphy_interface_copy(config-\u003epcs_interfaces,\ndrivers/net/ethernet/airoha/airoha_eth.c-3347-\t\t\t\t config-\u003esupported_interfaces);\n--\ndrivers/net/phy/phylink.c=545=static int phylink_validate_mac_and_pcs(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-566-\t */\ndrivers/net/phy/phylink.c:567:\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\ndrivers/net/phy/phylink.c-568-\t\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list) {\n--\ndrivers/net/phy/phylink.c=1061=static unsigned int phylink_inband_caps(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-1070-\t\tpcs_found = !!pcs;\ndrivers/net/phy/phylink.c:1071:\t} else if (test_bit(interface, pl-\u003econfig-\u003epcs_interfaces)) {\ndrivers/net/phy/phylink.c-1072-\t\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list) {\n--\ndrivers/net/phy/phylink.c=1351=static void phylink_major_config(struct phylink *pl, bool restart,\n--\ndrivers/net/phy/phylink.c-1381-\t */\ndrivers/net/phy/phylink.c:1382:\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\ndrivers/net/phy/phylink.c-1383-\t\tbool pcs_found = false;\n--\ndrivers/net/phy/phylink.c=2076=struct phylink *phylink_create(struct phylink_config *config,\n--\ndrivers/net/phy/phylink.c-2177-\t/* Register notifier for late PCS attach */\ndrivers/net/phy/phylink.c:2178:\tif (!phy_interface_empty(config-\u003epcs_interfaces)) {\ndrivers/net/phy/phylink.c-2179-\t\tpl-\u003efwnode_pcs_nb.notifier_call = pcs_provider_notify;\n--\ninclude/linux/phylink.h=133=enum phylink_op_type {\n--\ninclude/linux/phylink.h-154- * are supported by the MAC/PCS.\ninclude/linux/phylink.h:155: * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a\ninclude/linux/phylink.h-156- *\t\t dedicated PCS is required.\n--\ninclude/linux/phylink.h=171=struct phylink_config {\n--\ninclude/linux/phylink.h-181-\tDECLARE_PHY_INTERFACE_MASK(supported_interfaces);\ninclude/linux/phylink.h:182:\tDECLARE_PHY_INTERFACE_MASK(pcs_interfaces);\ninclude/linux/phylink.h-183-\tDECLARE_PHY_INTERFACE_MASK(lpi_interfaces);\n"
} |
| 21/2 | 2026/07/17 08:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 156981 output: 45 thoughts: 521 Thoughts: **Analyzing the Airoha Driver and Potential Syzkaller Exploitation**
Okay, so the new feature is *only* used by the Airoha driver. This Airoha driver is a platform driver specifically for an SoC. It's designed to interface with hardware, mapping registers and failing if the hardware isn't present. The critical thing is that there's no way to get to the new PCS or modified phylink code without the Airoha driver probing successfully, or so I thought. No other driver even touches this stuff.
Wait, could I use Syzkaller to my advantage here? Could Syzkaller create a dummy platform device that pretends to be "airoha,en7581-eth" and provide it with fake resources? Yes, absolutely. Syzkaller can inject platform devices.
If it does, that will trigger `airoha_probe`. The code then does `devm_platform_ioremap_resource_byname(pdev, "fe")` to map some dummy memory. Then, crucially, it calls `devm_reset_control_bulk_get_exclusive`. If the device tree node doesn't define reset lines, this will fail.
Can Syzkaller inject a device tree node with reset lines? Not really. Syzkaller's `syz_dev_platform_add` function isn't that sophisticated. It can't inject arbitrary device tree nodes with complex dependencies like reset controllers or syscon. Usually, it's just basic memory and IRQs.
Even if it could, `airoha_hw_init` has a critical dependency:
```c
for_each_child_of_node(pdev->dev.of_node, np) {
if (!of_device_is_compatible(np, "airoha,eth-mac"))
continue;
```
It *requires* child nodes with specific compatibles. Syzkaller's platform device injection doesn't create child nodes. So, `airoha_probe` is very likely to just return 0, without registering any netdev because `d` will be 0:
```c
return !d ? airoha_alloc_gdm_device(eth, port, nbq, np) : 0;
```
But wait a minute, if `d` is 0, the code calls `airoha_alloc_gdm_device(eth, port, nbq, np)`. Hmm, *`port` and `nbq` are uninitialized!* That's a potential vulnerability. Let's go back and re-examine the `airoha_hw_init` function. I need to understand how these variables are supposed to be initialized.
|
| 22/2 | 2026/07/17 08:46 | tool | read-file |
0mArgs:{
"File": "drivers/net/ethernet/airoha/airoha_eth.c",
"FirstLine": 3450,
"LineCount": 60
}Results: {
"Contents": "3450:\t\t\treturn -EINVAL;\n3451:\t\t}\n3452:\t\n3453:\t\tport = devm_kzalloc(eth-\u003edev, sizeof(*port), GFP_KERNEL);\n3454:\t\tif (!port)\n3455:\t\t\treturn -ENOMEM;\n3456:\t\n3457:\t\tport-\u003eid = id;\n3458:\t\tspin_lock_init(\u0026port-\u003elock);\n3459:\t\teth-\u003eports[p] = port;\n3460:\t\n3461:\t\terr = airoha_metadata_dst_alloc(port);\n3462:\t\tif (err)\n3463:\t\t\treturn err;\n3464:\t\n3465:\t\t/* Default nbq value to ensure backward compatibility */\n3466:\t\tnbq = id == AIROHA_GDM3_IDX \u0026\u0026 airoha_is_7581(eth) ? 4 : 0;\n3467:\t\n3468:\t\tfor_each_child_of_node(np, node) {\n3469:\t\t\t/* Multiple external serdes connected to the FE GDM port via an\n3470:\t\t\t * external arbiter.\n3471:\t\t\t */\n3472:\t\t\tconst __be32 *nbq_ptr;\n3473:\t\n3474:\t\t\tif (!of_device_is_compatible(node, \"airoha,eth-port\"))\n3475:\t\t\t\tcontinue;\n3476:\t\n3477:\t\t\td++;\n3478:\t\t\tif (!of_device_is_available(node))\n3479:\t\t\t\tcontinue;\n3480:\t\n3481:\t\t\tnbq_ptr = of_get_property(node, \"reg\", NULL);\n3482:\t\t\tif (!nbq_ptr) {\n3483:\t\t\t\tdev_err(eth-\u003edev, \"missing nbq id\\n\");\n3484:\t\t\t\tof_node_put(node);\n3485:\t\t\t\treturn -EINVAL;\n3486:\t\t\t}\n3487:\t\n3488:\t\t\t/* Verify the provided nbq parameter is valid */\n3489:\t\t\tnbq = be32_to_cpup(nbq_ptr);\n3490:\t\t\terr = eth-\u003esoc-\u003eops.get_sport(port, nbq);\n3491:\t\t\tif (err \u003c 0) {\n3492:\t\t\t\tof_node_put(node);\n3493:\t\t\t\treturn err;\n3494:\t\t\t}\n3495:\t\n3496:\t\t\terr = airoha_alloc_gdm_device(eth, port, nbq, node);\n3497:\t\t\tif (err) {\n3498:\t\t\t\tof_node_put(node);\n3499:\t\t\t\treturn err;\n3500:\t\t\t}\n3501:\t\t}\n3502:\t\n3503:\t\treturn !d ? airoha_alloc_gdm_device(eth, port, nbq, np) : 0;\n3504:\t}\n3505:\t\n3506:\tstatic int airoha_register_gdm_devices(struct airoha_eth *eth)\n3507:\t{\n3508:\t\tint i;\n3509:\t\n"
} |
| 23/2 | 2026/07/17 08:46 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 158988 output: 141 thoughts: 844 Thoughts: **Analysis of the Airoha Ethernet Driver Patch** Okay, let's break this down. My initial observation is that `airoha_alloc_gdm_port` is the key function. It's only called if there are child nodes under `pdev->dev.of_node` that are compatible with "airoha,eth-mac." If no such child nodes exist, then `airoha_alloc_gdm_port` is never called. This is critical. Consequently, if no child nodes are present, the subsequent call to `airoha_register_gdm_devices` does nothing because `eth->ports` will be empty. This means no netdev is registered. Since the netdev isn't registered, `airoha_setup_phylink` is never called. Therefore, all the new PCS code and the modified phylink code are completely unreachable in a virtualized environment *without* a very specific device tree configuration. The patch itself introduces a new PCS subsystem, Airoha PCS driver, and modifications to both `airoha_eth.c` and `phylink.c` to integrate with this new subsystem. However, this new PCS subsystem and the changes to phylink are *only* accessed if the Airoha driver utilizes them. The Airoha driver is a hardware-specific platform driver, meaning it is only going to work on very specific hardware, and it expects a very specific device tree structure with particular compatibles, reset lines, and syscon configurations to probe successfully and register a netdev. If that device tree isn't present, the driver doesn't probe, and the new code isn't touched. So, without the netdev, `airoha_setup_phylink` isn't called, meaning the new PCS code is never executed. This makes this whole patch impossible to reach in virtualized environments, like GCE or QEMU. I've already run a quick check for other uses of `fwnode_pcs_add_provider`, `fwnode_pcs_get`, `num_possible_pcs`, and `pcs_interfaces` and confirmed my suspicion – it's all Airoha-specific. Based on the prompt, it says I should return `WorthFuzzing=false` if the patch contains unreachable code in virtualized environments. The new code is strictly tied to this unreachable Airoha driver and PCS driver. Therefore, given the restrictions of the device tree and hardware requirements of the Airoha driver, this code is *impossible* to reach in standard virtualization setups. Thus, I'll set `WorthFuzzing=false`. |
| 24/2 | 2026/07/17 08:47 | tool | set-results |
0mArgs:{
"EnableConfigs": [],
"FocusSymbols": [],
"Reasoning": "The patch introduces a new PCS subsystem and an Airoha AN7581 PCS driver, and modifies the Airoha ethernet driver to use it. The new PCS subsystem and the modifications to phylink are only used by the Airoha driver. The Airoha driver is a hardware-specific platform driver that requires a specific device tree structure (child nodes, reset lines, syscon) and hardware registers to probe successfully. Therefore, the new code paths are impossible to reach in virtualized environments like GCE or QEMU.",
"WorthFuzzing": false
}Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch introduces a new PCS subsystem and an Airoha AN7581 PCS driver, and modifies the Airoha ethernet driver to use it. The new PCS subsystem and the modifications to phylink are only used by the Airoha driver. The Airoha driver is a hardware-specific platform driver that requires a specific device tree structure (child nodes, reset lines, syscon) and hardware registers to probe successfully. Therefore, the new code paths are impossible to reach in virtualized environments like GCE or QEMU.",
"WorthFuzzing": false
} |
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