AI Trajectory

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies hardware parity error (RAS) handling routines for the Intel QuickAssist Technology (QAT) Gen 6 driver (drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c). This code requires physical Intel QAT Gen 6 PCIe accelerator hardware which is not emulated in standard virtualized environments (QEMU/GCE), making the modified code structurally unreachable for fuzzing.",
  "WorthFuzzing": false
}

null

{
  "PatchDiff": "commit e8f8e3e4a0b65687f1139bec86d2962595fdcd41\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Thu Sep 17 21:11:34 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c b/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c\nindex 967253082a984..902c4b1a23e3b 100644\n--- a/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c\n+++ b/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c\n@@ -323,14 +323,26 @@ static void adf_handle_ti_cd_par_sts(struct adf_accel_dev *accel_dev, void __iom\n \tu32 ti_cd_par_sts;\n \n \tti_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_STS);\n-\tti_cd_par_sts \u0026= ADF_GEN6_TI_CD_PAR_STS_MASK;\n+\tti_cd_par_sts \u0026= ADF_GEN6_TI_CD_PAR_STS_TI_INT_ERR_DEVHALT_MASK;\n \tif (ti_cd_par_sts) {\n \t\tdev_err(\u0026GET_DEV(accel_dev), \"TI CD parity error: %#x\\n\", ti_cd_par_sts);\n-\t\tADF_RAS_ERR_CTR_INC(accel_dev-\u003eras_errors, ADF_RAS_UNCORR);\n \t\tADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_STS, ti_cd_par_sts);\n \t}\n }\n \n+static void adf_handle_ti_misc_cd_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)\n+{\n+\tu32 ti_misc_cd_par_sts;\n+\n+\tti_misc_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_STS);\n+\tti_misc_cd_par_sts \u0026= ADF_GEN6_TI_CD_PAR_STS_TI_MISC_MASK;\n+\tif (ti_misc_cd_par_sts) {\n+\t\tdev_err(\u0026GET_DEV(accel_dev), \"TI MISC CD parity error: %#x\\n\", ti_misc_cd_par_sts);\n+\t\tADF_RAS_ERR_CTR_INC(accel_dev-\u003eras_errors, ADF_RAS_UNCORR);\n+\t\tADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_STS, ti_misc_cd_par_sts);\n+\t}\n+}\n+\n static void adf_handle_ti_trnsb_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)\n {\n \tu32 ti_trnsb_par_sts;\n@@ -367,7 +379,6 @@ static void adf_handle_ti_err(struct adf_accel_dev *accel_dev, void __iomem *csr\n \tadf_handle_ti_ci_par_sts(accel_dev, csr);\n \tadf_handle_ti_pullfub_par_sts(accel_dev, csr);\n \tadf_handle_ti_pushfub_par_sts(accel_dev, csr);\n-\tadf_handle_ti_cd_par_sts(accel_dev, csr);\n \tadf_handle_ti_trnsb_par_sts(accel_dev, csr);\n \tadf_handle_iosfp_cmd_parerr(accel_dev, csr);\n }\n@@ -591,6 +602,8 @@ static void adf_handle_timiscsts(struct adf_accel_dev *accel_dev, void __iomem *\n \tif (!(errsou \u0026 ADF_GEN6_ERRSOU3_TIMISCSTS_BIT))\n \t\treturn;\n \n+\tadf_handle_ti_misc_cd_par_sts(accel_dev, csr);\n+\n \ttimiscsts = ADF_CSR_RD(csr, ADF_GEN6_TIMISCSTS);\n \tif (timiscsts) {\n \t\tdev_err(\u0026GET_DEV(accel_dev), \"Fatal error in transmit interface: %#x\\n\",\n@@ -730,6 +743,7 @@ static void adf_handle_ti_int_err_devhalt(struct adf_accel_dev *accel_dev, void\n \tif (!(errsou \u0026 ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT))\n \t\treturn;\n \n+\tadf_handle_ti_cd_par_sts(accel_dev, csr);\n \tdev_err(\u0026GET_DEV(accel_dev), \"DEVHALT due to a TI internal memory error\\n\");\n \tADF_RAS_ERR_CTR_INC(accel_dev-\u003eras_errors, ADF_RAS_FATAL);\n }\ndiff --git a/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h b/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h\nindex 66ced271d1733..11f7b2986f567 100644\n--- a/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h\n+++ b/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h\n@@ -170,23 +170,25 @@ struct adf_ras_ops;\n #define ADF_GEN6_TI_CD_PAR_ERR_MASK\t\t\t0x500638\n \n /*\n- * TI CD parity status mask\n+ * TI CD parity status mask - TI_INT_ERR_DEVHALT bits\n  * BIT(0) - BIT(15) - CtxMdRam[0:15]_sts parity status\n  * BIT(16) - Leaf2ClusterRam_sts parity status\n  * BIT(17) - BIT(18) - Ring2LeafRam[0:1]_sts parity status\n- * BIT(19) - VirtualQ_sts parity status\n- * BIT(20) - DtRdQ_sts parity status\n- * BIT(21) - DtWrQ_sts parity status\n- * BIT(22) - RiCmdQ_sts parity status\n- * BIT(23) - BypassQ_sts parity status\n- * BIT(24) - DtRdQ_sc_sts parity status\n- * BIT(25) - DtWrQ_sc_sts parity status\n  */\n-#define ADF_GEN6_TI_CD_PAR_STS_MASK \\\n+#define ADF_GEN6_TI_CD_PAR_STS_TI_INT_ERR_DEVHALT_MASK \\\n \t(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \\\n \t BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \\\n-\t BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \\\n-\t BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25))\n+\t BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18))\n+\n+/*\n+ * TI CD parity status mask - TIMISCSTS bit\n+ * BIT(19) - VirtualQ_sts parity status\n+ */\n+#define ADF_GEN6_TI_CD_PAR_STS_TI_MISC_MASK\t\tBIT(19)\n+\n+#define ADF_GEN6_TI_CD_PAR_STS_MASK \\\n+\t(ADF_GEN6_TI_CD_PAR_STS_TI_INT_ERR_DEVHALT_MASK | \\\n+\t ADF_GEN6_TI_CD_PAR_STS_TI_MISC_MASK)\n \n /* TI TRNSB parity status */\n #define ADF_GEN6_TI_TRNSB_PAR_STS\t\t\t0x500648\n"
}

core

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies hardware parity error (RAS) handling routines for the Intel QuickAssist Technology (QAT) Gen 6 driver (drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c). This code requires physical Intel QAT Gen 6 PCIe accelerator hardware which is not emulated in standard virtualized environments (QEMU/GCE), making the modified code structurally unreachable for fuzzing.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit e8f8e3e4a0b65687f1139bec86d2962595fdcd41
Author: syz-cluster <triage@syzkaller.com>
Date:   Thu Sep 17 21:11:34 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c b/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c
index 967253082a984..902c4b1a23e3b 100644
--- a/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c
@@ -323,14 +323,26 @@ static void adf_handle_ti_cd_par_sts(struct adf_accel_dev *accel_dev, void __iom
 	u32 ti_cd_par_sts;
 
 	ti_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_STS);
-	ti_cd_par_sts &= ADF_GEN6_TI_CD_PAR_STS_MASK;
+	ti_cd_par_sts &= ADF_GEN6_TI_CD_PAR_STS_TI_INT_ERR_DEVHALT_MASK;
 	if (ti_cd_par_sts) {
 		dev_err(&GET_DEV(accel_dev), "TI CD parity error: %#x\n", ti_cd_par_sts);
-		ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
 		ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_STS, ti_cd_par_sts);
 	}
 }
 
+static void adf_handle_ti_misc_cd_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)
+{
+	u32 ti_misc_cd_par_sts;
+
+	ti_misc_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_STS);
+	ti_misc_cd_par_sts &= ADF_GEN6_TI_CD_PAR_STS_TI_MISC_MASK;
+	if (ti_misc_cd_par_sts) {
+		dev_err(&GET_DEV(accel_dev), "TI MISC CD parity error: %#x\n", ti_misc_cd_par_sts);
+		ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
+		ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_STS, ti_misc_cd_par_sts);
+	}
+}
+
 static void adf_handle_ti_trnsb_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)
 {
 	u32 ti_trnsb_par_sts;
@@ -367,7 +379,6 @@ static void adf_handle_ti_err(struct adf_accel_dev *accel_dev, void __iomem *csr
 	adf_handle_ti_ci_par_sts(accel_dev, csr);
 	adf_handle_ti_pullfub_par_sts(accel_dev, csr);
 	adf_handle_ti_pushfub_par_sts(accel_dev, csr);
-	adf_handle_ti_cd_par_sts(accel_dev, csr);
 	adf_handle_ti_trnsb_par_sts(accel_dev, csr);
 	adf_handle_iosfp_cmd_parerr(accel_dev, csr);
 }
@@ -591,6 +602,8 @@ static void adf_handle_timiscsts(struct adf_accel_dev *accel_dev, void __iomem *
 	if (!(errsou & ADF_GEN6_ERRSOU3_TIMISCSTS_BIT))
 		return;
 
+	adf_handle_ti_misc_cd_par_sts(accel_dev, csr);
+
 	timiscsts = ADF_CSR_RD(csr, ADF_GEN6_TIMISCSTS);
 	if (timiscsts) {
 		dev_err(&GET_DEV(accel_dev), "Fatal error in transmit interface: %#x\n",
@@ -730,6 +743,7 @@ static void adf_handle_ti_int_err_devhalt(struct adf_accel_dev *accel_dev, void
 	if (!(errsou & ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT))
 		return;
 
+	adf_handle_ti_cd_par_sts(accel_dev, csr);
 	dev_err(&GET_DEV(accel_dev), "DEVHALT due to a TI internal memory error\n");
 	ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
 }
diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h b/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h
index 66ced271d1733..11f7b2986f567 100644
--- a/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h
@@ -170,23 +170,25 @@ struct adf_ras_ops;
 #define ADF_GEN6_TI_CD_PAR_ERR_MASK			0x500638
 
 /*
- * TI CD parity status mask
+ * TI CD parity status mask - TI_INT_ERR_DEVHALT bits
  * BIT(0) - BIT(15) - CtxMdRam[0:15]_sts parity status
  * BIT(16) - Leaf2ClusterRam_sts parity status
  * BIT(17) - BIT(18) - Ring2LeafRam[0:1]_sts parity status
- * BIT(19) - VirtualQ_sts parity status
- * BIT(20) - DtRdQ_sts parity status
- * BIT(21) - DtWrQ_sts parity status
- * BIT(22) - RiCmdQ_sts parity status
- * BIT(23) - BypassQ_sts parity status
- * BIT(24) - DtRdQ_sc_sts parity status
- * BIT(25) - DtWrQ_sc_sts parity status
  */
-#define ADF_GEN6_TI_CD_PAR_STS_MASK \
+#define ADF_GEN6_TI_CD_PAR_STS_TI_INT_ERR_DEVHALT_MASK \
 	(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
 	 BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \
-	 BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
-	 BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25))
+	 BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18))
+
+/*
+ * TI CD parity status mask - TIMISCSTS bit
+ * BIT(19) - VirtualQ_sts parity status
+ */
+#define ADF_GEN6_TI_CD_PAR_STS_TI_MISC_MASK		BIT(19)
+
+#define ADF_GEN6_TI_CD_PAR_STS_MASK \
+	(ADF_GEN6_TI_CD_PAR_STS_TI_INT_ERR_DEVHALT_MASK | \
+	 ADF_GEN6_TI_CD_PAR_STS_TI_MISC_MASK)
 
 /* TI TRNSB parity status */
 #define ADF_GEN6_TI_TRNSB_PAR_STS			0x500648

gemini-3.8-flash

null

null

							input: 4728
							output: 35
							thoughts: 189
						

**Analyzing the Intel QAT Driver for Potential Unreachable Hardware Issues**

Okay, so I'm looking at this patch, specifically in `drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c` and `adf_gen6_ras.h`. My immediate thought is, "Right, Intel QuickAssist Technology (QAT) driver." Now, I need to understand the context. Is this QAT implementation actually a hardware crypto accelerator, likely a PCIe device? That's the critical question here.

The criteria I need to consider are outlined in section 2. It flags structurally unreachable hardware which can include vendor-specific PCIe switches, SmartNICs, or GPU drivers. Things like `mlxsw`, `pds_core`, `qed`, `ionic`, and `amdgpu`. These are systems that typically require physical ASIC/PCIe cards and aren't emulated in a standard QEMU environment.

So, the next logical step is to determine where Intel QAT fits into this. Can it be emulated or virtualized, or does it *require* physical ASIC hardware? To answer this, I'm going to dig into the `drivers/crypto/intel/qat` directory. This is where I'll get the information I need to confirm whether this driver is working with unreachable hardware, or if it has some form of virtualization available.

{
  "Expression": "config CRYPTO_DEV_QAT",
  "PathPrefix": "drivers/crypto/intel/qat"
}

{
  "Output": "drivers/crypto/intel/qat/Kconfig-1-# SPDX-License-Identifier: GPL-2.0-only\ndrivers/crypto/intel/qat/Kconfig:2:config CRYPTO_DEV_QAT\ndrivers/crypto/intel/qat/Kconfig-3-\ttristate\n--\ndrivers/crypto/intel/qat/Kconfig-18-\ndrivers/crypto/intel/qat/Kconfig:19:config CRYPTO_DEV_QAT_DH895xCC\ndrivers/crypto/intel/qat/Kconfig-20-\ttristate \"Support for Intel(R) DH895xCC\"\n--\ndrivers/crypto/intel/qat/Kconfig-29-\ndrivers/crypto/intel/qat/Kconfig:30:config CRYPTO_DEV_QAT_C3XXX\ndrivers/crypto/intel/qat/Kconfig-31-\ttristate \"Support for Intel(R) C3XXX\"\n--\ndrivers/crypto/intel/qat/Kconfig-40-\ndrivers/crypto/intel/qat/Kconfig:41:config CRYPTO_DEV_QAT_C62X\ndrivers/crypto/intel/qat/Kconfig-42-\ttristate \"Support for Intel(R) C62X\"\n--\ndrivers/crypto/intel/qat/Kconfig-51-\ndrivers/crypto/intel/qat/Kconfig:52:config CRYPTO_DEV_QAT_4XXX\ndrivers/crypto/intel/qat/Kconfig-53-\ttristate \"Support for Intel(R) QAT_4XXX\"\n--\ndrivers/crypto/intel/qat/Kconfig-62-\ndrivers/crypto/intel/qat/Kconfig:63:config CRYPTO_DEV_QAT_420XX\ndrivers/crypto/intel/qat/Kconfig-64-\ttristate \"Support for Intel(R) QAT_420XX\"\n--\ndrivers/crypto/intel/qat/Kconfig-73-\ndrivers/crypto/intel/qat/Kconfig:74:config CRYPTO_DEV_QAT_6XXX\ndrivers/crypto/intel/qat/Kconfig-75-\ttristate \"Support for Intel(R) QuickAssist Technology QAT_6XXX\"\n--\ndrivers/crypto/intel/qat/Kconfig-85-\ndrivers/crypto/intel/qat/Kconfig:86:config CRYPTO_DEV_QAT_DH895xCCVF\ndrivers/crypto/intel/qat/Kconfig-87-\ttristate \"Support for Intel(R) DH895xCC Virtual Function\"\n--\ndrivers/crypto/intel/qat/Kconfig-98-\ndrivers/crypto/intel/qat/Kconfig:99:config CRYPTO_DEV_QAT_C3XXXVF\ndrivers/crypto/intel/qat/Kconfig-100-\ttristate \"Support for Intel(R) C3XXX Virtual Function\"\n--\ndrivers/crypto/intel/qat/Kconfig-110-\ndrivers/crypto/intel/qat/Kconfig:111:config CRYPTO_DEV_QAT_C62XVF\ndrivers/crypto/intel/qat/Kconfig-112-\ttristate \"Support for Intel(R) C62X Virtual Function\"\n--\ndrivers/crypto/intel/qat/Kconfig-122-\ndrivers/crypto/intel/qat/Kconfig:123:config CRYPTO_DEV_QAT_ERROR_INJECTION\ndrivers/crypto/intel/qat/Kconfig-124-\tbool \"Support for Intel(R) QAT Devices Heartbeat Error Injection\"\n"
}

gemini-3.8-flash

null

null

							input: 6107
							output: 33
							thoughts: 18
						

Here's my attempt at summarizing the thought process, tailored for an expert audience:

**Tracing the Compilation of `adf_gen6_ras.c`**

Okay, so I need to figure out where `adf_gen6_ras.c` is being compiled. This isn't a particularly complex task, but knowing *how* it's being compiled is key to understanding its place in the overall build process, especially if I'm looking at dependencies or trying to debug potential issues. My initial thought process is usually:

1.  **Locate the Build System:** First, I'll need to figure out what build system is in use. Is it a standard `make` setup, autotools, CMake, or something custom? The file naming convention gives me a vague idea that it's related to Intel and, therefore, the build is most likely using `make`, Ninja, or a build system related to the Intel toolchain. I'll need to dig into the project structure to confirm.
2.  **Search the Build Files:** Once the build system is identified, I'll start with a straightforward grep or find command across the build-related files. I'll be looking for the filename itself, `adf_gen6_ras.c`, or parts of it, like just `adf_gen6_ras`. Then, I'd extend the search to find the compiler flags used (`-c`, `-I`, `-D`, etc.) associated with the file. These flags provide clues about include paths, preprocessor definitions, and other compile-time dependencies.
3.  **Analyze the Makefiles (or Equivalent):** If it's a `make` setup, I'll examine the relevant `Makefile` or `Makefile.inc` files to understand the compilation rules and dependencies. The goal is to trace back the compilation command from the object file to the source file, checking if there are any specific options or flags affecting that file's compilation. I would also see the other files linked into the build.
4.  **Consider Dependency Management:** I'll also consider whether there are any generated dependency files (e.g., `.d` files generated by `make` or similar) that provide an explicit mapping of source files to their dependencies. This is often the quickest way to find the compile commands.
5.  **Look for Cross-Compilation Clues:** Based on the codebase, I need to check if there are any cross-compilation environments. If so, I need to know which target architecture is being used. Then, I can filter the results and concentrate on the specific target.
6.  **Context Matters:** Finally, I'll need to keep the broader context in mind. What's the purpose of `adf_gen6_ras.c`? What other modules does it interact with? Knowing this will help me understand why the file is compiled the way it is and identify potential areas of concern. For example, if it's related to some error reporting function, the compiler flags are probably tuned for error checking.

{
  "Expression": "adf_gen6_ras",
  "PathPrefix": "drivers/crypto/intel/qat"
}

{
  "Output": "drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-19-#include \u003cadf_gen6_pm.h\u003e\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:20:#include \u003cadf_gen6_ras.h\u003e\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-21-#include \u003cadf_gen6_shared.h\u003e\n--\ndrivers/crypto/intel/qat/qat_common/Makefile=4=intel_qat-y := adf_accel_engine.o \\\n--\ndrivers/crypto/intel/qat/qat_common/Makefile-22-\tadf_gen4_vf_mig.o \\\ndrivers/crypto/intel/qat/qat_common/Makefile:23:\tadf_gen6_ras.o \\\ndrivers/crypto/intel/qat/qat_common/Makefile-24-\tadf_gen6_shared.o \\\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-6-#include \"adf_common_drv.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:7:#include \"adf_gen6_ras.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-8-#include \"adf_sysfs_ras_counters.h\"\n"
}

gemini-3.8-flash

null

null

							input: 7160
							output: 37
							thoughts: 66
						

Here's my summary, as if I were thinking it:

**Digging into QAT Driver Dependencies**

Okay, so I'm looking into this `qat_6xxx/adf_6xxx_hw_data.c` file, and it seems pretty clear it's leveraging `adf_gen6_ras.h`. Makes sense, considering the hardware it's likely targeting. Now, to get a better handle on the broader picture, I need to understand where this fits into the build process and configuration. Time to check the `drivers/crypto/intel/qat/qat_common/Makefile` and the `drivers/crypto/intel/qat/Kconfig` files. That should give me the dependencies, build rules, and any conditional compilation flags related to the QAT components and specifically this RAS integration. I want to see how these pieces are orchestrated, so I can understand the bigger picture and potential implications of any changes here.

{
  "File": "drivers/crypto/intel/qat/Kconfig",
  "FirstLine": 60,
  "LineCount": 40
}

{
  "Contents": "  60:\t\t  To compile this as a module, choose M here: the module\n  61:\t\t  will be called qat_4xxx.\n  62:\t\n  63:\tconfig CRYPTO_DEV_QAT_420XX\n  64:\t\ttristate \"Support for Intel(R) QAT_420XX\"\n  65:\t\tdepends on PCI \u0026\u0026 (!CPU_BIG_ENDIAN || COMPILE_TEST)\n  66:\t\tselect CRYPTO_DEV_QAT\n  67:\t\thelp\n  68:\t\t  Support for Intel(R) QuickAssist Technology QAT_420xx\n  69:\t\t  for accelerating crypto and compression workloads.\n  70:\t\n  71:\t\t  To compile this as a module, choose M here: the module\n  72:\t\t  will be called qat_420xx.\n  73:\t\n  74:\tconfig CRYPTO_DEV_QAT_6XXX\n  75:\t\ttristate \"Support for Intel(R) QuickAssist Technology QAT_6XXX\"\n  76:\t\tdepends on (X86 || COMPILE_TEST)\n  77:\t\tdepends on PCI\n  78:\t\tselect CRYPTO_DEV_QAT\n  79:\t\thelp\n  80:\t\t  Support for Intel(R) QuickAssist Technology QAT_6xxx\n  81:\t\t  for accelerating crypto and compression workloads.\n  82:\t\n  83:\t\t  To compile this as a module, choose M here: the module\n  84:\t\t  will be called qat_6xxx.\n  85:\t\n  86:\tconfig CRYPTO_DEV_QAT_DH895xCCVF\n  87:\t\ttristate \"Support for Intel(R) DH895xCC Virtual Function\"\n  88:\t\tdepends on PCI \u0026\u0026 (!CPU_BIG_ENDIAN || COMPILE_TEST)\n  89:\t\tselect PCI_IOV\n  90:\t\tselect CRYPTO_DEV_QAT\n  91:\t\n  92:\t\thelp\n  93:\t\t  Support for Intel(R) DH895xcc with Intel(R) QuickAssist Technology\n  94:\t\t  Virtual Function for accelerating crypto and compression workloads.\n  95:\t\n  96:\t\t  To compile this as a module, choose M here: the module\n  97:\t\t  will be called qat_dh895xccvf.\n  98:\t\n  99:\tconfig CRYPTO_DEV_QAT_C3XXXVF\n"
}

gemini-3.8-flash

null

null

							input: 8085
							output: 32
							thoughts: 76
						

**My Initial Thoughts on Intel QAT Gen 6 (CRYPTO_DEV_QAT_6XXX)**

Alright, so I'm looking at this Intel QAT Gen 6, specifically the CRYPTO_DEV_QAT_6XXX version. Immediately, I know this is QuickAssist Technology – a hardware accelerator, and a PCI device at that. My first instinct is to understand its integration, so I'm going to look into how the driver binds to it. That's step one.

Next, I need to get a handle on what the `adf_gen6_ras.c` file is doing. Is it related to RAS (Reliability, Availability, Serviceability)? Probably. I'll need to figure out exactly what functions are defined in the file. So, I'm going to grep for the references in that file. That will give me a good overview of the important functions. With that, I should get a good overview of the code that needs my attention.

{
  "Expression": "adf_gen6_",
  "PathPrefix": "drivers/crypto/intel/qat"
}

{
  "Output": "drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-18-#include \u003cadf_fw_config.h\u003e\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:19:#include \u003cadf_gen6_pm.h\u003e\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:20:#include \u003cadf_gen6_ras.h\u003e\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:21:#include \u003cadf_gen6_shared.h\u003e\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:22:#include \u003cadf_gen6_tl.h\u003e\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-23-#include \u003cadf_timer.h\u003e\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=44=static u32 rmask_two_services[] = {\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-48-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:49:enum adf_gen6_rps {\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-50-\tRP0 = 0,\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=199=static int get_rp_config(struct adf_accel_dev *accel_dev, struct adf_ring_config *rp_config,\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-252-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:253:static u32 adf_gen6_get_arb_mask(struct adf_accel_dev *accel_dev, unsigned int ae)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-254-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=467=static bool adf_anti_rb_enabled(struct adf_accel_dev *accel_dev)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-473-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:474:static void adf_gen6_init_anti_rb(struct adf_anti_rb_hw_data *anti_rb_data)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-475-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=537=static int build_decomp_block(void *ctx, enum adf_dc_algo algo)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-560-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:561:static void adf_gen6_init_dc_ops(struct adf_dc_ops *dc_ops)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-562-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-566-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:567:static int adf_gen6_init_thd2arb_map(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-568-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-573-\tfor (i = 0; i \u003c hw_data-\u003enum_engines; i++) {\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:574:\t\tthd2arb_map[i] = adf_gen6_get_arb_mask(accel_dev, i);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-575-\t\tdev_dbg(\u0026GET_DEV(accel_dev), \"ME:%d arb_mask:%#x\\n\", i, thd2arb_map[i]);\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=581=static void init_num_svc_aes(struct adf_rl_hw_data *device_data)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-610-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:611:static u32 adf_gen6_get_svc_slice_cnt(struct adf_accel_dev *accel_dev,\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-612-\t\t\t\t      enum adf_base_services svc)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=644=static int set_vc_config(struct adf_accel_dev *accel_dev)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-673-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:674:static int adf_gen6_set_vc(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-675-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=881=static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-882-{\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:883:\tif (adf_gen6_init_thd2arb_map(accel_dev))\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-884-\t\tdev_warn(\u0026GET_DEV(accel_dev),\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=890=static int adf_init_device(struct adf_accel_dev *accel_dev)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-918-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:919:\tret = adf_gen6_set_vc(accel_dev);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-920-\tif (ret)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=926=static int enable_pm(struct adf_accel_dev *accel_dev)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-934-\t/* Initialize PM internal data */\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:935:\tadf_gen6_init_dev_pm_data(accel_dev);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-936-\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=940=static int dev_config(struct adf_accel_dev *accel_dev)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-954-\tcase SVC_DCC:\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:955:\t\tret = adf_gen6_comp_dev_config(accel_dev);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-956-\t\tbreak;\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-957-\tdefault:\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:958:\t\tret = adf_gen6_no_dev_config(accel_dev);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-959-\t\tbreak;\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-968-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:969:static void adf_gen6_init_kpt(struct adf_kpt_hw_data *kpt_data)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-970-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-980-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:981:static void adf_gen6_init_rl_data(struct adf_rl_hw_data *rl_data)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-982-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-999-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1000:static void adf_gen6_init_services_supported(struct adf_hw_device_data *hw_data)\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-1001-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c=1008=void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-1065-\thw_data-\u003eclock_frequency = ADF_6XXX_AE_FREQ;\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1066:\thw_data-\u003eget_svc_slice_cnt = adf_gen6_get_svc_slice_cnt;\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-1067-\thw_data-\u003eaccel_capabilities_ext_mask = ADF_ACCEL_CAPABILITIES_EXT_ZSTD;\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-1068-\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1069:\tadf_gen6_init_services_supported(hw_data);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1070:\tadf_gen6_init_hw_csr_ops(\u0026hw_data-\u003ecsr_ops);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1071:\tadf_gen6_init_pf_pfvf_ops(\u0026hw_data-\u003epfvf_ops);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1072:\tadf_gen6_init_dc_ops(\u0026hw_data-\u003edc_ops);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1073:\tadf_gen6_init_vf_mig_ops(\u0026hw_data-\u003evfmig_ops);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1074:\tadf_gen6_init_ras_ops(\u0026hw_data-\u003eras_ops);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1075:\tadf_gen6_init_tl_data(\u0026hw_data-\u003etl_data);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1076:\tadf_gen6_init_rl_data(\u0026hw_data-\u003erl_data);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1077:\tadf_gen6_init_anti_rb(\u0026hw_data-\u003eanti_rb_data);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c:1078:\tadf_gen6_init_kpt(\u0026hw_data-\u003ekpt_data);\ndrivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c-1079-}\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-17-\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c:18:#include \"adf_gen6_shared.h\"\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-19-#include \"adf_6xxx_hw_data.h\"\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c=53=static void adf_devmgr_remove(void *accel_dev)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-57-\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c:58:static int adf_gen6_cfg_dev_init(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-59-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c=87=static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-170-\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c:171:\tret = adf_gen6_cfg_dev_init(accel_dev);\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-172-\tif (ret)\n--\ndrivers/crypto/intel/qat/qat_common/Makefile=4=intel_qat-y := adf_accel_engine.o \\\n--\ndrivers/crypto/intel/qat/qat_common/Makefile-22-\tadf_gen4_vf_mig.o \\\ndrivers/crypto/intel/qat/qat_common/Makefile:23:\tadf_gen6_ras.o \\\ndrivers/crypto/intel/qat/qat_common/Makefile:24:\tadf_gen6_shared.o \\\ndrivers/crypto/intel/qat/qat_common/Makefile-25-\tadf_hw_arbiter.o \\\n--\ndrivers/crypto/intel/qat/qat_common/Makefile=52=intel_qat-$(CONFIG_DEBUG_FS) += adf_cnv_dbgfs.o \\\n--\ndrivers/crypto/intel/qat/qat_common/Makefile-56-\t\t\t\tadf_gen4_tl.o \\\ndrivers/crypto/intel/qat/qat_common/Makefile:57:\t\t\t\tadf_gen6_pm_dbgfs.o \\\ndrivers/crypto/intel/qat/qat_common/Makefile:58:\t\t\t\tadf_gen6_tl.o \\\ndrivers/crypto/intel/qat/qat_common/Makefile-59-\t\t\t\tadf_heartbeat_dbgfs.o \\\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm.h=9=struct adf_accel_dev;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm.h-44-#ifdef CONFIG_DEBUG_FS\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm.h:45:void adf_gen6_init_dev_pm_data(struct adf_accel_dev *accel_dev);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm.h-46-#else\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm.h:47:static inline void adf_gen6_init_dev_pm_data(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm.h-48-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c-8-#include \"adf_common_drv.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c:9:#include \"adf_gen6_pm.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c-10-#include \"adf_pm_dbgfs_utils.h\"\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c=38=static_assert(sizeof(struct icp_qat_fw_init_admin_pm_info) \u003c PAGE_SIZE);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c-39-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c:40:static ssize_t adf_gen6_print_pm_status(struct adf_accel_dev *accel_dev,\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c-41-\t\t\t\t\tchar __user *buf, size_t count,\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c-118-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c:119:void adf_gen6_init_dev_pm_data(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c-120-{\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c:121:\taccel_dev-\u003epower_management.print_pm_status = adf_gen6_print_pm_status;\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c-122-\taccel_dev-\u003epower_management.present = true;\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c-123-}\ndrivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c:124:EXPORT_SYMBOL_GPL(adf_gen6_init_dev_pm_data);\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-6-#include \"adf_common_drv.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:7:#include \"adf_gen6_ras.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-8-#include \"adf_sysfs_ras_counters.h\"\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c=94=static void enable_ssm_error_reporting(struct adf_accel_dev *accel_dev,\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-100-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:101:static void adf_gen6_enable_ras(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-102-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c=185=static void disable_ssm_error_reporting(void __iomem *csr)\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-190-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:191:static void adf_gen6_disable_ras(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-192-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-201-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:202:static void adf_gen6_process_errsou0(struct adf_accel_dev *accel_dev, void __iomem *csr)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-203-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c=386=static void adf_handle_sfi_cmd_parerr(struct adf_accel_dev *accel_dev, void __iomem *csr,\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-397-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:398:static void adf_gen6_process_errsou1(struct adf_accel_dev *accel_dev, void __iomem *csr,\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-399-\t\t\t\t     u32 errsou)\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c=558=static void adf_handle_cpp_cfc_err(struct adf_accel_dev *accel_dev, void __iomem *csr,\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-585-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:586:static void adf_gen6_process_errsou2(struct adf_accel_dev *accel_dev, void __iomem *csr,\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-587-\t\t\t\t     u32 errsou)\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c=740=static void adf_handle_ti_int_err_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-750-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:751:static void adf_gen6_process_errsou3(struct adf_accel_dev *accel_dev, void __iomem *csr,\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-752-\t\t\t\t     u32 errsou)\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-770-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:771:static void adf_gen6_is_reset_required(struct adf_accel_dev *accel_dev, void __iomem *csr,\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-772-\t\t\t\t       bool *reset_required)\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-790-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:791:static bool adf_gen6_handle_interrupt(struct adf_accel_dev *accel_dev, bool *reset_required)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-792-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-798-\tif (errsou \u0026 ADF_GEN6_ERRSOU0_MASK) {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:799:\t\tadf_gen6_process_errsou0(accel_dev, csr);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-800-\t\thandled = true;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-804-\tif (errsou \u0026 ADF_GEN6_ERRSOU1_MASK) {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:805:\t\tadf_gen6_process_errsou1(accel_dev, csr, errsou);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-806-\t\thandled = true;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-810-\tif (errsou \u0026 ADF_GEN6_ERRSOU2_MASK) {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:811:\t\tadf_gen6_process_errsou2(accel_dev, csr, errsou);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-812-\t\thandled = true;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-816-\tif (errsou \u0026 ADF_GEN6_ERRSOU3_MASK) {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:817:\t\tadf_gen6_process_errsou3(accel_dev, csr, errsou);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-818-\t\thandled = true;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-820-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:821:\tadf_gen6_is_reset_required(accel_dev, csr, reset_required);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-822-\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-825-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:826:void adf_gen6_init_ras_ops(struct adf_ras_ops *ras_ops)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-827-{\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:828:\tras_ops-\u003eenable_ras_errors = adf_gen6_enable_ras;\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:829:\tras_ops-\u003edisable_ras_errors = adf_gen6_disable_ras;\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:830:\tras_ops-\u003ehandle_interrupt = adf_gen6_handle_interrupt;\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c-831-}\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.c:832:EXPORT_SYMBOL_GPL(adf_gen6_init_ras_ops);\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.h=8=struct adf_ras_ops;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.h-503-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.h:504:void adf_gen6_init_ras_ops(struct adf_ras_ops *ras_ops);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_ras.h-505-\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-8-#include \"adf_gen4_vf_mig.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:9:#include \"adf_gen6_shared.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-10-\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c=13=struct adf_hw_csr_ops;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-21- */\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:22:void adf_gen6_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-23-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-25-}\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:26:EXPORT_SYMBOL_GPL(adf_gen6_init_pf_pfvf_ops);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-27-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:28:void adf_gen6_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-29-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-31-}\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:32:EXPORT_SYMBOL_GPL(adf_gen6_init_hw_csr_ops);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-33-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:34:int adf_gen6_comp_dev_config(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-35-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-37-}\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:38:EXPORT_SYMBOL_GPL(adf_gen6_comp_dev_config);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-39-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:40:int adf_gen6_no_dev_config(struct adf_accel_dev *accel_dev)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-41-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-43-}\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:44:EXPORT_SYMBOL_GPL(adf_gen6_no_dev_config);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-45-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:46:void adf_gen6_init_vf_mig_ops(struct qat_migdev_ops *vfmig_ops)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-47-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c-49-}\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.c:50:EXPORT_SYMBOL_GPL(adf_gen6_init_vf_mig_ops);\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.h=9=struct adf_pfvf_ops;\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.h-10-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.h:11:void adf_gen6_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.h:12:void adf_gen6_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.h:13:int adf_gen6_comp_dev_config(struct adf_accel_dev *accel_dev);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.h:14:int adf_gen6_no_dev_config(struct adf_accel_dev *accel_dev);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.h:15:void adf_gen6_init_vf_mig_ops(struct qat_migdev_ops *vfmig_ops);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_shared.h-16-#endif/* ADF_GEN6_SHARED_H_ */\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c-4-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c:5:#include \"adf_gen6_tl.h\"\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c-6-#include \"adf_telemetry.h\"\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c=196=static const struct adf_tl_dbg_counter rp_counters[] = {\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c-227-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c:228:void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c-229-{\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c-257-}\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.c:258:EXPORT_SYMBOL_GPL(adf_gen6_init_tl_data);\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h=8=struct adf_tl_hw_data;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-41-/**\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:42: * struct adf_gen6_tl_slice_data_regs - HW slice data as populated by FW.\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-43- * @reg_tm_slice_exec_cnt: Slice execution count.\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-45- */\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:46:struct adf_gen6_tl_slice_data_regs {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-47-\t__u32 reg_tm_slice_exec_cnt;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-50-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:51:#define ADF_GEN6_TL_SLICE_REG_SZ sizeof(struct adf_gen6_tl_slice_data_regs)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-52-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-53-/**\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:54: * struct adf_gen6_tl_cmdq_data_regs - HW CMDQ data as populated by FW.\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-55- * @reg_tm_cmdq_wait_cnt: CMDQ wait count.\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-58- */\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:59:struct adf_gen6_tl_cmdq_data_regs {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-60-\t__u32 reg_tm_cmdq_wait_cnt;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-65-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:66:#define ADF_GEN6_TL_CMDQ_REG_SZ sizeof(struct adf_gen6_tl_cmdq_data_regs)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-67-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-68-/**\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:69: * struct adf_gen6_tl_device_data_regs - This structure stores device telemetry\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-70- * counter values as are being populated periodically by device.\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-102- */\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:103:struct adf_gen6_tl_device_data_regs {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-104-\t__u64 reg_tl_rd_lat_acc;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-120-\t__u32 reserved;\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:121:\tstruct adf_gen6_tl_slice_data_regs ath_slices[MAX_ATH_SL_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:122:\tstruct adf_gen6_tl_slice_data_regs cnv_slices[MAX_CNV_SL_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:123:\tstruct adf_gen6_tl_slice_data_regs dcprz_slices[MAX_DCPRZ_SL_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:124:\tstruct adf_gen6_tl_slice_data_regs pke_slices[MAX_PKE_SL_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:125:\tstruct adf_gen6_tl_slice_data_regs ucs_slices[MAX_UCS_SL_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:126:\tstruct adf_gen6_tl_slice_data_regs wat_slices[MAX_WAT_SL_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:127:\tstruct adf_gen6_tl_slice_data_regs wcp_slices[MAX_WCP_SL_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:128:\tstruct adf_gen6_tl_cmdq_data_regs ath_cmdq[MAX_ATH_CMDQ_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:129:\tstruct adf_gen6_tl_cmdq_data_regs cnv_cmdq[MAX_CNV_CMDQ_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:130:\tstruct adf_gen6_tl_cmdq_data_regs dcprz_cmdq[MAX_DCPRZ_CMDQ_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:131:\tstruct adf_gen6_tl_cmdq_data_regs pke_cmdq[MAX_PKE_CMDQ_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:132:\tstruct adf_gen6_tl_cmdq_data_regs ucs_cmdq[MAX_UCS_CMDQ_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:133:\tstruct adf_gen6_tl_cmdq_data_regs wat_cmdq[MAX_WAT_CMDQ_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:134:\tstruct adf_gen6_tl_cmdq_data_regs wcp_cmdq[MAX_WCP_CMDQ_COUNT];\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-135-};\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-137-/**\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:138: * struct adf_gen6_tl_ring_pair_data_regs - This structure stores ring pair\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-139- * telemetry counter values as they are being populated periodically by device.\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-152- */\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:153:struct adf_gen6_tl_ring_pair_data_regs {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-154-\t__u64 reg_tl_gp_lat_acc;\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-167-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:168:#define ADF_GEN6_TL_RP_REG_SZ sizeof(struct adf_gen6_tl_ring_pair_data_regs)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-169-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-170-/**\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:171: * struct adf_gen6_tl_layout - This structure represents the entire telemetry\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-172- * counters data: Device + 4 Ring Pairs as they are being populated periodically\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-178- */\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:179:struct adf_gen6_tl_layout {\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:180:\tstruct adf_gen6_tl_device_data_regs tl_device_data_regs;\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:181:\tstruct adf_gen6_tl_ring_pair_data_regs\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-182-\t\ttl_ring_pairs_data_regs[ADF_GEN6_TL_MAX_RP_NUM];\n--\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-186-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:187:#define ADF_GEN6_TL_LAYOUT_SZ sizeof(struct adf_gen6_tl_layout)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-188-#define ADF_GEN6_TL_MSG_CNT_OFF \\\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:189:\toffsetof(struct adf_gen6_tl_layout, reg_tl_msg_cnt)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-190-\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-191-#ifdef CONFIG_DEBUG_FS\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:192:void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data);\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-193-#else\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h:194:static inline void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data)\ndrivers/crypto/intel/qat/qat_common/adf_gen6_tl.h-195-{\n"
}

gemini-3.8-flash

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							input: 20349
							output: 38
							thoughts: 67
						

**Investigating the Intel QAT Gen 6 Driver**

Okay, so I'm diving into this `qat_6xxx` driver, and from the name itself, I'm pretty sure it's the Intel QAT Gen 6 driver. Now, the next logical step is to pinpoint the core of its functionality, so I need to check out the source code – specifically, `drivers/crypto/intel/qat/qat_6xxx/adf_drv.c`. That's where the action is likely happening. My focus at this point is on understanding how the driver interacts with the underlying hardware, so a critical detail to identify is which PCI IDs it's bound to. That will tell me which specific Intel QAT hardware this driver is designed to work with.

{
  "Expression": "pci_device_id",
  "PathPrefix": "drivers/crypto/intel/qat/qat_6xxx"
}

{
  "Output": "drivers/crypto/intel/qat/qat_6xxx/adf_drv.c=58=static int adf_gen6_cfg_dev_init(struct adf_accel_dev *accel_dev)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-86-\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c:87:static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-88-{\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c=230=static void adf_shutdown(struct pci_dev *pdev)\n--\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-236-\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c:237:static const struct pci_device_id adf_pci_tbl[] = {\ndrivers/crypto/intel/qat/qat_6xxx/adf_drv.c-238-\t{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QAT_6XXX) },\n"
}

gemini-3.8-flash

null

null

							input: 20938
							output: 119
							thoughts: 1527
						

**Analysis of Intel QAT Gen 6 RAS Error Handling for Fuzzing**

Okay, so the initial check shows this patch is touching `adf_pci_tbl` and specifically targets `PCI_DEVICE_ID_INTEL_QAT_6XXX`. Right away, my mind goes to emulation - are there any QAT emulations, perhaps software mocks in QEMU? No, that's not the case. QAT is Intel's physical QuickAssist Technology, a hardware accelerator. And QEMU? Nope, no QAT emulation there either.

Okay, so what about VFIO? Can we do a hardware passthrough of this QAT device? Yes, that *would* require the physical hardware.

Let's quickly review the prompt's section 2: "Structurally unreachable hardware" – PCIe switches, SmartNICs, GPUs requiring physical ASICs. That's a red flag. Specifically mentioned are things like `mlxsw`, `pds_core`, etc., which I know are all reliant on dedicated hardware.

Let's confirm that `drivers/crypto/intel/qat` falls into this category. And, as suspected, Intel QAT devices, the DH895xCC, C3XXX, C62X, 4XXX, 420XX, and 6XXX families, are indeed Intel PCIe hardware accelerators for cryptography and compression.

Now, let's look at the patch itself. It's modifying Reliability, Availability, and Serviceability (RAS) error handling, specifically in `adf_gen6_ras.c`. It looks like it's handling parity error interrupts, which is a hardware-level event. The code changes in the patch confirm this. This is *explicitly* hardware error interrupt handling for Intel QAT Gen 6. To even *reach* this code, two things need to happen: First, a *physical* Intel QAT Gen 6 PCIe card must be present and probed. Second, a *hardware* parity error interrupt must occur on that device.

So, are there any software emulations or virtual devices for Intel QAT in standard QEMU or syzkaller? I'll do a quick sweep for any related `syzkaller` pseudo-syscalls or references to "qat" or "CRYPTO_DEV_QAT" in virtual test setups, netdevs, or USB gadgets. Nothing. QAT is *purely* physical Intel QuickAssist Technology PCIe hardware.

Let's reiterate the core principles: Reachability is key. Fuzzing can only find bugs in code that can run in standard virtualized environments (GCE or QEMU, with software-emulated devices like USB gadgets, netdev, and tun/tap). If the code is unreachable, *it cannot be fuzzed*.

We're dealing with "Structurally unreachable hardware" – vendor-specific PCIe cards not emulated in QEMU. This patch modifies `drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c` and `.h`. These files implement RAS error reporting and parity error handling for Intel QuickAssist Technology Gen 6 PCIe devices, requiring physical Intel QAT Gen 6 hardware, which is *not* emulated in standard QEMU or GCE.

Therefore, `WorthFuzzing` is unequivocally false.

So, I will formulate the response in the required format:

`WorthFuzzing: false`
`FocusSymbols: []`
`EnableConfigs: []`
`Reasoning: The patch modifies hardware parity error (RAS) handling routines in the Intel QuickAssist Technology (QAT) Gen 6 driver (drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c). This code requires physical Intel QAT Gen 6 PCIe accelerator hardware which is not emulated in standard virtualized fuzzing environments (QEMU/GCE). Consequently, the modified code is structurally unreachable for syzkaller.`

That should be perfectly clear and directly addresses the guidelines.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies hardware parity error (RAS) handling routines for the Intel QuickAssist Technology (QAT) Gen 6 driver (drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c). This code requires physical Intel QAT Gen 6 PCIe accelerator hardware which is not emulated in standard virtualized environments (QEMU/GCE), making the modified code structurally unreachable for fuzzing.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies hardware parity error (RAS) handling routines for the Intel QuickAssist Technology (QAT) Gen 6 driver (drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c). This code requires physical Intel QAT Gen 6 PCIe accelerator hardware which is not emulated in standard virtualized environments (QEMU/GCE), making the modified code structurally unreachable for fuzzing.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

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