AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/09/25 05:38	flow	patch-triage	3m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.", "WorthFuzzing": false }
1/1	2026/09/25 05:38	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit f0b5e1ec09b73c16ba34999b4655ca2ca2376168\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Fri Sep 25 05:38:45 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\nindex f8ab347f7b5b9..3ccd29ea7ab0e 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n@@ -167,6 +167,11 @@\n #define XGMAC_HW_FEATURE4\t\t0x0000012c\n #define XGMAC_HWFEAT_EASP\t\tBIT(4)\n #define XGMAC_HWFEAT_PCSEL\t\tGENMASK(1, 0)\n+#define XGMAC_EXT_CFG0\t\t\t0x140\n+#define XGMAC_EXT_CFG0_VPRE\t\tBIT(8)\n+#define XGMAC_EXT_CFG1\t\t\t0x00000144\n+#define XGMAC_CONFIG1_SAVE_EN\t\tBIT(24)\n+#define XGMAC_CONFIG1_SPLM(v)\t\tFIELD_PREP(GENMASK(9, 8), v)\n #define XGMAC_MAC_DPP_FSM_INT_STATUS\t0x00000150\n #define XGMAC_MAC_FSM_CONTROL\t\t0x00000158\n #define XGMAC_PRTYEN\t\t\tBIT(1)\n@@ -434,6 +439,7 @@\n #define XGMAC_RDES2_L4FM\t\tBIT(28)\n #define XGMAC_RDES2_L3FM\t\tBIT(27)\n #define XGMAC_RDES2_HL\t\t\tGENMASK(9, 0)\n+#define XGMAC_RDES2_NONIPHL\t\tGENMASK(9, 2)\n #define XGMAC_RDES3_OWN\t\t\tBIT(31)\n #define XGMAC_RDES3_CTXT\t\tBIT(30)\n #define XGMAC_RDES3_IOC\t\t\tBIT(30)\n@@ -441,6 +447,7 @@\n #define XGMAC_RDES3_CDA\t\t\tBIT(27)\n #define XGMAC_RDES3_RSV\t\t\tBIT(26)\n #define XGMAC_RDES3_L34T\t\tGENMASK(23, 20)\n+#define XGMAC_RDES3_L2T\t\t\tGENMASK(19, 16)\n #define XGMAC_RDES3_ET_LT\t\tGENMASK(19, 16)\n #define XGMAC_L34T_IP4TCP\t\t0x1\n #define XGMAC_L34T_IP4UDP\t\t0x2\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c\nindex 6719ac6e395bc..65ac5403ec583 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c\n@@ -292,8 +292,18 @@ static int dwxgmac2_get_rx_hash(struct dma_desc p, u32 hash,\n \n static void dwxgmac2_get_rx_header_len(struct dma_desc p, unsigned int len)\n {\n-\tif (le32_to_cpu(p-\u003edes3) \u0026 XGMAC_RDES3_L34T)\n+\tu32 rdes3 = le32_to_cpu(p-\u003edes3);\n+\n+\t/* when FD=1 and LD=0, HL is RDES2[9:0] /\n+\tif (!(rdes3 \u0026 XGMAC_RDES3_LD)) {\n+\t\tlen = le32_to_cpu(p-\u003edes2) \u0026 XGMAC_RDES2_HL;\n+\t\treturn;\n+\t}\n+\n+\tif (rdes3 \u0026 XGMAC_RDES3_L34T)\n \t\tlen = le32_to_cpu(p-\u003edes2) \u0026 XGMAC_RDES2_HL;\n+\telse if (rdes3 \u0026 XGMAC_RDES3_L2T)\n+\t\tlen = (le32_to_cpu(p-\u003edes2) \u0026 XGMAC_RDES2_NONIPHL) \u003e\u003e 2;\n }\n \n static void dwxgmac2_set_sec_addr(struct dma_desc p, dma_addr_t addr, bool is_valid)\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\nindex ff83858ebc1f3..0a9c787305a4e 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\n@@ -561,6 +561,16 @@ static void dwxgmac2_enable_sph(struct stmmac_priv priv, void __iomem ioaddr,\n \tvalue \|= XGMAC_CONFIG_HDSMS_256; / Segment max 256 bytes /\n \twritel(value, ioaddr + XGMAC_RX_CONFIG);\n \n+\tvalue = readl(ioaddr + XGMAC_EXT_CFG1);\n+\tvalue \|= XGMAC_CONFIG1_SPLM(1);\n+\tvalue \|= XGMAC_CONFIG1_SAVE_EN;\n+\twritel(value, ioaddr + XGMAC_EXT_CFG1);\n+\n+\t/ Disable variable preambles to keep the L2 split offset deterministic. */\n+\tvalue = readl(ioaddr + XGMAC_EXT_CFG0);\n+\tvalue \u0026= ~XGMAC_EXT_CFG0_VPRE;\n+\twritel(value, ioaddr + XGMAC_EXT_CFG0);\n+\n \tvalue = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));\n \tif (en)\n \t\tvalue \|= XGMAC_SPH;\n" }
2/1	2026/09/25 05:38	agent	patch-evaluator	3m Model: core Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer and security engineer. Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on internal assumptions. You must actively use your code access tools to inspect the actual source code, callers, and surrounding context. ================================================================================ 1. CORE TRIAGE PHILOSOPHY ================================================================================ The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs, and newly triggered assertions introduced by the patch series. - REACHABILITY IS THE PRIMARY GATE: Fuzzing can only discover bugs in code that can actually execute in standard virtualized environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap). If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed, regardless of whether it adds assertions or complex logic. - DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS: Patch authors routinely label changes as "cleanups", "refactorings", or state "No functional change intended". Do NOT take these claims at face value. Code refactorings that rearrange logic, introduce helper functions, or alter state management in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs. If reachable executable code is modified or refactored, it MUST be fuzzed. - NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED: When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON, VM_WARN_ON, BUG_ON, lockdep_assert) in reachable code paths, it enforces new or stricter invariants. Even if the author believes the invariant always holds, fuzzing is essential to verify whether an unusual sequence of operations can violate it. ================================================================================ 2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA) ================================================================================ Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories: - Non-kernel and non-executable changes: * Modifications to Documentation/, comments, or spelling fixes. * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/) that do not affect the compiled kernel image (vmlinux) or kernel modules. * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints that do not alter control flow or data structures. * Build system or Kconfig changes that do not alter compiled C logic. - Structurally unreachable hardware: * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU. - Unreachable execution paths: * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during physical PCI hot-unplug or manual sysfs driver unbinding. * Code paths exclusive to architectures other than the target architecture. ================================================================================ 3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA) ================================================================================ Return WorthFuzzing=true whenever the patch touches reachable executable code, including: - Core Subsystems: * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/), BPF, scheduler, core networking, VFS, or syscall handling. - Refactorings and Code Cleanups: * Any restructuring of reachable data structures, helper abstractions, or algorithm flows. - Runtime Assertions and Defensive Checks: * Any introduction or alteration of assertions (WARN_ON, VM_WARN_ON, BUG_ON, etc.) in reachable paths. - Reachable Drivers and Protocols: Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.). ================================================================================ 4. EXTRACTING FocusSymbols (PREVENTING DILUTION) ================================================================================ When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer: - AVOID UBIQUITOUS LIFECYCLE HOT-PATHS: Do NOT list generic, ubiquitous functions called by almost every program in the corpus (including, but not limited to: general memory allocators and deallocators, page fault and trap handlers, or core synchronization primitives; this is not an exhaustive list). Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused", which severely dilutes fuzzing effort away from the actual changes. - TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS: List functions that specifically implement the logic being added or altered, or direct API entrypoints for the subsystem feature under review. - HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h): Compiler-inlined static functions (such as static inlines in mm/.h or include/linux/.h) lack distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters. If the changes are primarily in static inline helpers, identify non-static, feature-specific caller functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers). ================================================================================ 5. IDENTIFYING EnableConfigs ================================================================================ Identify any specific CONFIG_ options required to properly compile and reach the modified code: - Inspect Kconfig files and #ifdef guards; do not make assumptions. - Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed. - Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: Target architecture: amd64 For your convenience, here is the diff of the changes: commit f0b5e1ec09b73c16ba34999b4655ca2ca2376168 Author: syz-cluster <triage@syzkaller.com> Date: Fri Sep 25 05:38:45 2026 +0000 syz-cluster: applied patch under review diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index f8ab347f7b5b9..3ccd29ea7ab0e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -167,6 +167,11 @@ #define XGMAC_HW_FEATURE4 0x0000012c #define XGMAC_HWFEAT_EASP BIT(4) #define XGMAC_HWFEAT_PCSEL GENMASK(1, 0) +#define XGMAC_EXT_CFG0 0x140 +#define XGMAC_EXT_CFG0_VPRE BIT(8) +#define XGMAC_EXT_CFG1 0x00000144 +#define XGMAC_CONFIG1_SAVE_EN BIT(24) +#define XGMAC_CONFIG1_SPLM(v) FIELD_PREP(GENMASK(9, 8), v) #define XGMAC_MAC_DPP_FSM_INT_STATUS 0x00000150 #define XGMAC_MAC_FSM_CONTROL 0x00000158 #define XGMAC_PRTYEN BIT(1) @@ -434,6 +439,7 @@ #define XGMAC_RDES2_L4FM BIT(28) #define XGMAC_RDES2_L3FM BIT(27) #define XGMAC_RDES2_HL GENMASK(9, 0) +#define XGMAC_RDES2_NONIPHL GENMASK(9, 2) #define XGMAC_RDES3_OWN BIT(31) #define XGMAC_RDES3_CTXT BIT(30) #define XGMAC_RDES3_IOC BIT(30) @@ -441,6 +447,7 @@ #define XGMAC_RDES3_CDA BIT(27) #define XGMAC_RDES3_RSV BIT(26) #define XGMAC_RDES3_L34T GENMASK(23, 20) +#define XGMAC_RDES3_L2T GENMASK(19, 16) #define XGMAC_RDES3_ET_LT GENMASK(19, 16) #define XGMAC_L34T_IP4TCP 0x1 #define XGMAC_L34T_IP4UDP 0x2 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c index 6719ac6e395bc..65ac5403ec583 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c @@ -292,8 +292,18 @@ static int dwxgmac2_get_rx_hash(struct dma_desc p, u32 hash, static void dwxgmac2_get_rx_header_len(struct dma_desc p, unsigned int len) { - if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T) + u32 rdes3 = le32_to_cpu(p->des3); + + /* when FD=1 and LD=0, HL is RDES2[9:0] / + if (!(rdes3 & XGMAC_RDES3_LD)) { + len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; + return; + } + + if (rdes3 & XGMAC_RDES3_L34T) len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; + else if (rdes3 & XGMAC_RDES3_L2T) + len = (le32_to_cpu(p->des2) & XGMAC_RDES2_NONIPHL) >> 2; } static void dwxgmac2_set_sec_addr(struct dma_desc p, dma_addr_t addr, bool is_valid) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index ff83858ebc1f3..0a9c787305a4e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -561,6 +561,16 @@ static void dwxgmac2_enable_sph(struct stmmac_priv priv, void __iomem ioaddr, value \|= XGMAC_CONFIG_HDSMS_256; / Segment max 256 bytes / writel(value, ioaddr + XGMAC_RX_CONFIG); + value = readl(ioaddr + XGMAC_EXT_CFG1); + value \|= XGMAC_CONFIG1_SPLM(1); + value \|= XGMAC_CONFIG1_SAVE_EN; + writel(value, ioaddr + XGMAC_EXT_CFG1); + + / Disable variable preambles to keep the L2 split offset deterministic. */ + value = readl(ioaddr + XGMAC_EXT_CFG0); + value &= ~XGMAC_EXT_CFG0_VPRE; + writel(value, ioaddr + XGMAC_EXT_CFG0); + value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); if (en) value \|= XGMAC_SPH;
3/2	2026/09/25 05:38	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 4312 output: 37 thoughts: 239 Thoughts: Analyzing a Kernel Patch Series for the dwxgmac2 Driver Okay, so I need to dig into this patch series for the kernel repo. My initial focus is always on understanding the scope of the changes. Let's see... the patch touches these files: `drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h`, `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c`, and `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c`. Right, that confirms it's the `dwxgmac2` part of the `stmmac` driver – the Synopsys DesignWare Enterprise Ethernet controller, specifically the 10G/XGMAC variant. Now, my next thought is about practical implications for testing. Can I easily get this running in a typical virtualized environment? I need to quickly assess if `stmmac` or specifically `dwxgmac2` is accessible within common setups like GCE or with QEMU and emulated network devices such as USB gadgets, or tun/tap interfaces. But hold on, before I dive into the testing, it's smarter to consider the hardware this affects. Let me quickly determine which platforms or buses are actually using this specific `dwxgmac2` implementation within `stmmac`. I should use `grepper` or scan the codebase directly to determine the hardware this patch will impact. That will guide my subsequent test setup.
4/2	2026/09/25 05:39	tool	grepper	0m Args: { "Expression": "dwxgmac2", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac" } Results: { "Output": "\nFull output is too long, showing 500 out of 694 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/stmicro/stmmac/Makefile=3=stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o\t\\\n--\ndrivers/net/ethernet/stmicro/stmmac/Makefile-7-\t dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \\\ndrivers/net/ethernet/stmicro/stmmac/Makefile:8:\t stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \\\ndrivers/net/ethernet/stmicro/stmmac/Makefile-9-\t stmmac_xdp.o stmmac_est.o stmmac_fpe.o stmmac_vlan.o \\\n--\ndrivers/net/ethernet/stmicro/stmmac/common.h=657=int dwmac4_setup(struct stmmac_priv priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h:658:int dwxgmac2_setup(struct stmmac_priv priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h-659-int dwxlgmac2_setup(struct stmmac_priv priv);\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-18-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:19:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-20-#include \"stmmac.h\"\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-471-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:472:extern const struct stmmac_ops dwxgmac210_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-473-extern const struct stmmac_ops dwxlgmac2_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:474:extern const struct stmmac_dma_ops dwxgmac210_dma_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:475:extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-476-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-14-#include \"dwxlgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:15:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-16-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:17:static void dwxgmac2_core_init(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-18-\t\t\t struct net_device dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-30-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:31:static void dwxgmac2_irq_modify(struct mac_device_info hw, u32 disable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-32-\t\t\t\tu32 enable)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-44-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:45:static void dwxgmac2_update_caps(struct stmmac_priv priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-46-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-50-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:51:static void dwxgmac2_set_mac(void __iomem ioaddr, bool enable)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-52-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-67-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:68:static int dwxgmac2_rx_ipc(struct mac_device_info hw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-69-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-82-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:83:static void dwxgmac2_rx_queue_enable(struct mac_device_info hw, u8 mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-84-\t\t\t\t u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-96-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:97:static void dwxgmac2_rx_queue_prio(struct mac_device_info hw, u32 prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-98-\t\t\t\t u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-137-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:138:static void dwxgmac2_tx_queue_prio(struct mac_device_info hw, u32 prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-139-\t\t\t\t u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-154-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:155:static void dwxgmac2_rx_queue_routing(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-156-\t\t\t\t u8 packet, u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-160-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:161:\tstatic const struct stmmac_rx_routing dwxgmac2_route_possibilities[] = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-162-\t\t{ XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT },\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-171-\t/ routing configuration /\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:172:\tvalue \u0026= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:173:\tvalue \|= (queue \u003c\u003c dwxgmac2_route_possibilities[packet - 1].reg_shift) \u0026\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:174:\t\t dwxgmac2_route_possibilities[packet - 1].reg_mask;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-175-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-184-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:185:static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-186-\t\t\t\t\t u32 rx_alg)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-206-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:207:static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-208-\t\t\t\t\t u32 tx_alg)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-244-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:245:static void dwxgmac2_set_mtl_tx_queue_weight(struct stmmac_priv priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-246-\t\t\t\t\t struct mac_device_info hw,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-253-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:254:static void dwxgmac2_map_mtl_to_dma(struct mac_device_info hw, u32 queue,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-255-\t\t\t\t u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-270-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:271:static void dwxgmac2_config_cbs(struct stmmac_priv priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-272-\t\t\t\tstruct mac_device_info hw,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-289-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:290:static void dwxgmac2_dump_regs(struct mac_device_info hw, u32 reg_space)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-291-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-298-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:299:static int dwxgmac2_host_irq_status(struct stmmac_priv priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-300-\t\t\t\t struct stmmac_extra_stats x)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-335-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:336:static int dwxgmac2_host_mtl_irq_status(struct stmmac_priv priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-337-\t\t\t\t\tstruct mac_device_info hw, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-355-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:356:static void dwxgmac2_flow_ctrl(struct mac_device_info hw, unsigned int duplex,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-357-\t\t\t unsigned int fc, unsigned int pause_time,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-376-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:377:static void dwxgmac2_pmt(struct mac_device_info hw, unsigned long mode)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-378-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-394-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:395:static void dwxgmac2_set_umac_addr(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-396-\t\t\t\t const unsigned char addr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-408-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:409:static void dwxgmac2_get_umac_addr(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-410-\t\t\t\t unsigned char addr, unsigned int reg_n)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-427-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:428:static int dwxgmac2_set_lpi_mode(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-429-\t\t\t\t enum stmmac_lpi_mode mode,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-451-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:452:static void dwxgmac2_set_eee_pls(struct mac_device_info hw, int link)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-453-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-464-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:465:static void dwxgmac2_set_eee_timer(struct mac_device_info hw, int ls, int tw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-466-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-473-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:474:static void dwxgmac2_set_mchash(void __iomem ioaddr, u32 mcfilterbits,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-475-\t\t\t\tint mcbitslog2)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-496-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:497:static void dwxgmac2_set_filter(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-498-\t\t\t\tstruct net_device dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-531-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:532:\tdwxgmac2_set_mchash(ioaddr, mc_filter, mcbitslog2);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-533-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-541-\t\tnetdev_for_each_uc_addr(ha, dev) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:542:\t\t\tdwxgmac2_set_umac_addr(hw, ha-\u003eaddr, reg);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-543-\t\t\treg++;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-554-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:555:static void dwxgmac2_set_mac_loopback(void __iomem ioaddr, bool enable)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-556-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-566-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:567:static int dwxgmac2_rss_write_reg(void __iomem ioaddr, bool is_key, int idx,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-568-\t\t\t\t u32 val)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-581-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:582:static int dwxgmac2_rss_configure(struct mac_device_info hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-583-\t\t\t\t struct stmmac_rss cfg, u32 num_rxq)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-597-\tfor (i = 0; i \u003c (ARRAY_SIZE(cfg-\u003ekey) / sizeof(u32)); i++) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:598:\t\tret = dwxgmac2_rss_write_reg(ioaddr, true, i, key[i]);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-599-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-603-\tfor (i = 0; i \u003c ARRAY_SIZE(cfg-\u003etable); i++) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:604:\t\tret = dwxgmac2_rss_write_reg(ioaddr, false, i, cfg-\u003etable[i]);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-605-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-609-\tfor (i = 0; i \u003c num_rxq; i++)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:610:\t\tdwxgmac2_map_mtl_to_dma(hw, i, XGMAC_QDDMACH);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-611-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1055=static int dwxgmac3_rxp_config(void __iomem ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1142-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1143:static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info hw, u64 ts)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1144-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1156-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1157:static int dwxgmac2_flex_pps_config(void __iomem ioaddr, int index,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1158-\t\t\t\t struct stmmac_pps_cfg cfg, bool enable,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1220-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1221:static void dwxgmac2_sarc_configure(void __iomem ioaddr, int val)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1222-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1229-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1230:static int dwxgmac2_filter_wait(struct mac_device_info hw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1231-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1240-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1241:static int dwxgmac2_filter_read(struct mac_device_info hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1242-\t\t\t\tu8 reg, u32 data)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1247-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1248:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1249-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1257-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1258:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1259-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1265-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1266:static int dwxgmac2_filter_write(struct mac_device_info hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1267-\t\t\t\t u8 reg, u32 data)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1272-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1273:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1274-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1284-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1285:\treturn dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1286-}\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1287-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1288:static int dwxgmac2_config_l3_filter(struct mac_device_info hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1289-\t\t\t\t bool en, bool ipv6, bool sa, bool inv,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1299-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1300:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1301-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1330-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1331:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1332-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1335-\tif (sa) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1336:\t\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR0, match);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1337-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1339-\t} else {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1340:\t\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR1, match);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1341-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1345-\tif (!en)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1346:\t\treturn dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1347-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1350-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1351:static int dwxgmac2_config_l4_filter(struct mac_device_info hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1352-\t\t\t\t bool en, bool udp, bool sa, bool inv,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1362-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1363:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1364-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1386-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1387:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1388-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1390-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1391:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L4_ADDR, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1392-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1402-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1403:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1404-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1407-\tif (!en)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1408:\t\treturn dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1409-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1412-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1413:const struct stmmac_ops dwxgmac210_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1414:\t.core_init = dwxgmac2_core_init,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1415:\t.irq_modify = dwxgmac2_irq_modify,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1416:\t.update_caps = dwxgmac2_update_caps,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1417:\t.set_mac = dwxgmac2_set_mac,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1418:\t.rx_ipc = dwxgmac2_rx_ipc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1419:\t.rx_queue_enable = dwxgmac2_rx_queue_enable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1420:\t.rx_queue_prio = dwxgmac2_rx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1421:\t.tx_queue_prio = dwxgmac2_tx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1422:\t.rx_queue_routing = dwxgmac2_rx_queue_routing,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1423:\t.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1424:\t.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1425:\t.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1426:\t.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1427:\t.config_cbs = dwxgmac2_config_cbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1428:\t.dump_regs = dwxgmac2_dump_regs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1429:\t.host_irq_status = dwxgmac2_host_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1430:\t.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1431:\t.flow_ctrl = dwxgmac2_flow_ctrl,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1432:\t.pmt = dwxgmac2_pmt,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1433:\t.set_umac_addr = dwxgmac2_set_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1434:\t.get_umac_addr = dwxgmac2_get_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1435:\t.set_lpi_mode = dwxgmac2_set_lpi_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1436:\t.set_eee_timer = dwxgmac2_set_eee_timer,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1437:\t.set_eee_pls = dwxgmac2_set_eee_pls,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1438-\t.debug = NULL,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1439:\t.set_filter = dwxgmac2_set_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1440-\t.safety_feat_config = dwxgmac3_safety_feat_config,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1442-\t.safety_feat_dump = dwxgmac3_safety_feat_dump,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1443:\t.set_mac_loopback = dwxgmac2_set_mac_loopback,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1444:\t.rss_configure = dwxgmac2_rss_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1445-\t.rxp_config = dwxgmac3_rxp_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1446:\t.get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1447:\t.flex_pps_config = dwxgmac2_flex_pps_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1448:\t.sarc_configure = dwxgmac2_sarc_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1449:\t.config_l3_filter = dwxgmac2_config_l3_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1450:\t.config_l4_filter = dwxgmac2_config_l4_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1451-\t.fpe_map_preemption_class = dwxgmac3_fpe_map_preemption_class,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1468=const struct stmmac_ops dwxlgmac2_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1469:\t.core_init = dwxgmac2_core_init,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1470:\t.irq_modify = dwxgmac2_irq_modify,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1471:\t.set_mac = dwxgmac2_set_mac,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1472:\t.rx_ipc = dwxgmac2_rx_ipc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1473-\t.rx_queue_enable = dwxlgmac2_rx_queue_enable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1474:\t.rx_queue_prio = dwxgmac2_rx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1475:\t.tx_queue_prio = dwxgmac2_tx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1476:\t.rx_queue_routing = dwxgmac2_rx_queue_routing,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1477:\t.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1478:\t.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1479:\t.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1480:\t.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1481:\t.config_cbs = dwxgmac2_config_cbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1482:\t.dump_regs = dwxgmac2_dump_regs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1483:\t.host_irq_status = dwxgmac2_host_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1484:\t.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1485:\t.flow_ctrl = dwxgmac2_flow_ctrl,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1486:\t.pmt = dwxgmac2_pmt,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1487:\t.set_umac_addr = dwxgmac2_set_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1488:\t.get_umac_addr = dwxgmac2_get_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1489:\t.set_lpi_mode = dwxgmac2_set_lpi_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1490:\t.set_eee_timer = dwxgmac2_set_eee_timer,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1491:\t.set_eee_pls = dwxgmac2_set_eee_pls,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1492-\t.debug = NULL,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1493:\t.set_filter = dwxgmac2_set_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1494-\t.safety_feat_config = dwxgmac3_safety_feat_config,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1496-\t.safety_feat_dump = dwxgmac3_safety_feat_dump,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1497:\t.set_mac_loopback = dwxgmac2_set_mac_loopback,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1498:\t.rss_configure = dwxgmac2_rss_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1499-\t.rxp_config = dwxgmac3_rxp_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1500:\t.get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1501:\t.flex_pps_config = dwxgmac2_flex_pps_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1502:\t.sarc_configure = dwxgmac2_sarc_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1503:\t.config_l3_filter = dwxgmac2_config_l3_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1504:\t.config_l4_filter = dwxgmac2_config_l4_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1505-\t.fpe_map_preemption_class = dwxgmac3_fpe_map_preemption_class,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1507-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1508:int dwxgmac2_setup(struct stmmac_priv priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1509-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-9-#include \"common.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:10:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-11-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:12:static int dwxgmac2_get_tx_status(struct stmmac_extra_stats x,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-13-\t\t\t\t struct dma_desc p, void __iomem ioaddr)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-25-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:26:static int dwxgmac2_get_rx_status(struct stmmac_extra_stats x,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-27-\t\t\t\t struct dma_desc p)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-48-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:49:static void dwxgmac2_set_tx_owner(struct dma_desc p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-50-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-53-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:54:static void dwxgmac2_set_rx_owner(struct dma_desc p, int disable_rx_ic)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-55-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-63-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:64:static u16 dwxgmac2_wrback_get_rx_vlan_tci(struct dma_desc p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-65-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-68-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:69:static bool dwxgmac2_wrback_get_rx_vlan_valid(struct dma_desc p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-70-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-78-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:79:static int dwxgmac2_get_rx_frame_len(struct dma_desc p, int rx_coe)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-80-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-83-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:84:static void dwxgmac2_enable_tx_timestamp(struct dma_desc p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-85-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-88-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:89:static int dwxgmac2_get_tx_timestamp_status(struct dma_desc p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-90-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-93-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:94:static inline void dwxgmac2_get_timestamp(void desc, u32 ats, u64 ts)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-95-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-104-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:105:static int dwxgmac2_rx_check_timestamp(void desc)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-106-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-124-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:125:static int dwxgmac2_get_rx_timestamp_status(void desc, void next_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-126-\t\t\t\t\t u32 ats)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-132-\tif (likely(rdes3 \u0026 XGMAC_RDES3_CDA))\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:133:\t\tret = dwxgmac2_rx_check_timestamp(next_desc);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-134-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-137-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:138:static void dwxgmac2_init_rx_desc(struct dma_desc p, int disable_rx_ic,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-139-\t\t\t\t u8 descriptor_mode, int end, int bfsize)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-140-{\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:141:\tdwxgmac2_set_rx_owner(p, disable_rx_ic);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-142-}\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-143-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:144:static void dwxgmac2_init_tx_desc(struct dma_desc p, u8 descriptor_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-145-\t\t\t\t int end)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-152-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:153:static void dwxgmac2_prepare_tx_desc(struct dma_desc p, int is_fs, int len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-154-\t\t\t\t bool csum_flag, u8 descriptor_mode,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-191-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:192:static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc p, int is_fs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-193-\t\t\t\t\t int len1, int len2, bool tx_own,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-229-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:230:static void dwxgmac2_release_tx_desc(struct dma_desc p, u8 descriptor_mode)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-231-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-237-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:238:static void dwxgmac2_set_tx_ic(struct dma_desc p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-239-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-242-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:243:static void dwxgmac2_set_mss(struct dma_desc p, unsigned int mss)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-244-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-250-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:251:static void dwxgmac2_set_addr(struct dma_desc p, dma_addr_t addr)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-252-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-256-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:257:static void dwxgmac2_clear(struct dma_desc p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-258-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-264-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:265:static int dwxgmac2_get_rx_hash(struct dma_desc p, u32 hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-266-\t\t\t\tenum pkt_hash_types type)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-292-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:293:static void dwxgmac2_get_rx_header_len(struct dma_desc p, unsigned int len)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-294-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-308-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:309:static void dwxgmac2_set_sec_addr(struct dma_desc p, dma_addr_t addr, bool is_valid)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-310-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-314-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:315:static void dwxgmac2_set_sarc(struct dma_desc p, u32 sarc_type)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-316-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-319-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:320:static void dwxgmac2_set_vlan_tag(struct dma_desc p, u16 tag, u16 inner_tag,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-321-\t\t\t\t u32 inner_type)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-344-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:345:static void dwxgmac2_set_vlan(struct dma_desc p, u32 type)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-346-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-349-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:350:static void dwxgmac2_set_tbs(struct dma_edesc p, u32 sec, u32 nsec)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-351-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-357-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:358:const struct stmmac_desc_ops dwxgmac210_desc_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:359:\t.tx_status = dwxgmac2_get_tx_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:360:\t.rx_status = dwxgmac2_get_rx_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:361:\t.set_tx_owner = dwxgmac2_set_tx_owner,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:362:\t.set_rx_owner = dwxgmac2_set_rx_owner,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:363:\t.get_rx_vlan_tci = dwxgmac2_wrback_get_rx_vlan_tci,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:364:\t.get_rx_vlan_valid = dwxgmac2_wrback_get_rx_vlan_valid,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:365:\t.get_rx_frame_len = dwxgmac2_get_rx_frame_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:366:\t.enable_tx_timestamp = dwxgmac2_enable_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:367:\t.get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:368:\t.get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:369:\t.get_timestamp = dwxgmac2_get_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:370:\t.set_tx_ic = dwxgmac2_set_tx_ic,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:371:\t.prepare_tx_desc = dwxgmac2_prepare_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:372:\t.prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:373:\t.release_tx_desc = dwxgmac2_release_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:374:\t.init_rx_desc = dwxgmac2_init_rx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:375:\t.init_tx_desc = dwxgmac2_init_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:376:\t.set_mss = dwxgmac2_set_mss,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:377:\t.set_addr = dwxgmac2_set_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:378:\t.clear = dwxgmac2_clear,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:379:\t.get_rx_hash = dwxgmac2_get_rx_hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:380:\t.get_rx_header_len = dwxgmac2_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:381:\t.set_sec_addr = dwxgmac2_set_sec_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:382:\t.set_sarc = dwxgmac2_set_sarc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:383:\t.set_vlan_tag = dwxgmac2_set_vlan_tag,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:384:\t.set_vlan = dwxgmac2_set_vlan,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:385:\t.set_tbs = dwxgmac2_set_tbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-386-};\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-8-#include \"stmmac.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:9:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-10-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:11:static int dwxgmac2_dma_reset(void __iomem *ioaddr)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-12-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-21-\n\n" }
5/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 21801 output: 39 thoughts: 21 Thoughts: Okay, let's dive into this code. Investigating the `dwxgmac2_setup` Function Right, my immediate focus is understanding the scope and impact of `dwxgmac2_setup`. I need to figure out where it's being invoked and, crucially, what other components or functions are relying on its output or actions. This is classic debugging - understanding dependencies is key to any efficient troubleshooting or modification. I'll start by tracing the calls to this function. Knowing its immediate call sites will tell me the context in which it's operating. From there, I can begin to reason about its role in the larger system. Is it setting up hardware, initializing data structures, or something else entirely? The call graph will give me the starting point for this investigation.
6/2	2026/09/25 05:39	tool	grepper	0m Args: { "Expression": "dwxgmac2_setup", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/common.h=657=int dwmac4_setup(struct stmmac_priv priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h:658:int dwxgmac2_setup(struct stmmac_priv priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h-659-int dwxlgmac2_setup(struct stmmac_priv priv);\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1468=const struct stmmac_ops dwxlgmac2_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1507-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1508:int dwxgmac2_setup(struct stmmac_priv priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1509-{\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-266-\t\t.est = \u0026dwmac510_est_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:267:\t\t.setup = dwxgmac2_setup,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-268-\t\t.quirks = NULL,\n" }
7/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 22458 output: 46 thoughts: 31 Thoughts: Okay, here's my take on those thoughts, tailored for an expert audience: Investigating dwxgmac2_setup Usage Alright, let's dig into this. I'm thinking the best way to get a handle on what's going on with `dwxgmac2_setup` is to go directly to the source. Specifically, I'm going to jump into `hwif.c`, probably around line 267. That seems like a reasonable starting point, given my experience with this codebase. From there, I'll be looking to see precisely which hardware or driver implementations are actually calling that function. I'm expecting this will likely point me towards specific SoCs, MAC controllers, or perhaps even broader architectural patterns within the system. I'm anticipating that I'll quickly be able to ascertain the context within which this function is being called and get a sense of its general importance to the system.
8/2	2026/09/25 05:39	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/hwif.c", "FirstLine": 240, "LineCount": 40 } Results: { "Contents": " 240:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 241:\t\t\t.mode = \u0026dwmac4_ring_mode_ops,\n 242:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 243:\t\t\t.mmc = \u0026dwmac_mmc_ops,\n 244:\t\t\t.est = \u0026dwmac510_est_ops,\n 245:\t\t\t.setup = dwmac4_setup,\n 246:\t\t\t.quirks = NULL,\n 247:\t\t}, {\n 248:\t\t\t.core_type = DWMAC_CORE_XGMAC,\n 249:\t\t\t.min_id = DWXGMAC_CORE_2_10,\n 250:\t\t\t.dev_id = DWXGMAC_ID,\n 251:\t\t\t.regs = {\n 252:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 253:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 254:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 255:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 256:\t\t\t},\n 257:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n 258:\t\t\t.dma = \u0026dwxgmac210_dma_ops,\n 259:\t\t\t.mac = \u0026dwxgmac210_ops,\n 260:\t\t\t.vlan = \u0026dwxgmac210_vlan_ops,\n 261:\t\t\t.hwtimestamp = \u0026stmmac_ptp,\n 262:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 263:\t\t\t.mode = NULL,\n 264:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 265:\t\t\t.mmc = \u0026dwxgmac_mmc_ops,\n 266:\t\t\t.est = \u0026dwmac510_est_ops,\n 267:\t\t\t.setup = dwxgmac2_setup,\n 268:\t\t\t.quirks = NULL,\n 269:\t\t}, {\n 270:\t\t\t.core_type = DWMAC_CORE_XGMAC,\n 271:\t\t\t.min_id = DWXLGMAC_CORE_2_00,\n 272:\t\t\t.dev_id = DWXLGMAC_ID,\n 273:\t\t\t.regs = {\n 274:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 275:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 276:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 277:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 278:\t\t\t},\n 279:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n" }
9/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 23499 output: 39 thoughts: 26 Thoughts: Okay, here's my attempt at summarizing that thought process, keeping in mind the user is an expert: Tracing the Origins of the STMMAC Hardware Interface Right, let's get down to brass tacks. I need to understand the initialization flow of this `stmmac hwif` thing. The `hwif` part screams "hardware interface," so I'm guessing it's the core structure representing the hardware abstraction. The immediate question is: where does this whole thing kick off? Specifically, I need to know who or what is responsible for calling `stmmac_hwif_init` or any function with a similar purpose. I need to trace back from that initialization point to understand the lifecycle of the hardware interface. Understanding the call chain will tell me a lot about the dependencies and the overall architecture. Time to dig into the code and start sleuthing!
10/2	2026/09/25 05:39	tool	grepper	0m Args: { "Expression": "stmmac_hwif", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/hwif.c=100=int stmmac_reset(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-110-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:111:static const struct stmmac_hwif_entry {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-112-\tenum dwmac_core_type core_type;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-292-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:293:static const struct stmmac_hwif_entry \ndrivers/net/ethernet/stmicro/stmmac/hwif.c:294:stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-295-{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:296:\tconst struct stmmac_hwif_entry entry;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-297-\tint i;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-316-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:317:int stmmac_hwif_init(struct stmmac_priv priv)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-318-{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-319-\tenum dwmac_core_type core_type = priv-\u003eplat-\u003ecore_type;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:320:\tconst struct stmmac_hwif_entry entry;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-321-\tstruct stmmac_version version;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-348-\t/ Use synopsys_id var because some setups can override this /\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:349:\tentry = stmmac_hwif_find(core_type, priv-\u003esynopsys_id, version.dev_id);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-350-\tif (!entry) {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h=694=int stmmac_reset(struct stmmac_priv priv);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:695:int stmmac_hwif_init(struct stmmac_priv priv);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-696-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7463=static int stmmac_hw_init(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7472-\t/* Initialize HW Interface */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7473:\tret = stmmac_hwif_init(priv);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7474-\tif (ret)\n" }
11/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 24714 output: 42 thoughts: 65 Thoughts: Okay, let's break this down. Investigating the STMMAC Driver Alright, I need to get a clear picture of `stmmac`. My immediate questions are: What devices are actually using this driver? Where does the `stmmac` driver bind itself within the system? Is it primarily associated with physical Ethernet interfaces – perhaps MAC/IP configurations on various System-on-Chip (SoC) architectures, or even PCIe cards? To clarify this, I'll need to dig into the source code. The obvious starting points are the configuration and build files. I'll head over to the kernel source directory and examine `drivers/net/ethernet/stmicro/stmmac/`. I need to review `Kconfig` for the configuration options related to the driver and understand its dependency and then I will examine `Makefile` to see how it's built and the specific hardware dependencies it might have. This should give me the core information I'm after.
12/2	2026/09/25 05:39	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig", "FirstLine": 1, "LineCount": 80 } Results: { "Contents": " 1:\t# SPDX-License-Identifier: GPL-2.0-only\n 2:\tconfig STMMAC_ETH\n 3:\t\ttristate \"STMicroelectronics Multi-Gigabit Ethernet driver\"\n 4:\t\tdepends on HAS_IOMEM \u0026\u0026 HAS_DMA\n 5:\t\tdepends on PTP_1588_CLOCK_OPTIONAL\n 6:\t\tdepends on ETHTOOL_NETLINK\n 7:\t\tselect MII\n 8:\t\tselect PCS_XPCS\n 9:\t\tselect PAGE_POOL\n 10:\t\tselect PHYLINK\n 11:\t\tselect CRC32\n 12:\t\tselect RESET_CONTROLLER\n 13:\t\tselect NET_DEVLINK\n 14:\t\thelp\n 15:\t\t This is the driver for the Ethernet IPs built around a\n 16:\t\t Synopsys IP Core.\n 17:\t\n 18:\tif STMMAC_ETH\n 19:\t\n 20:\tconfig STMMAC_SELFTESTS\n 21:\t\tbool \"Support for STMMAC Selftests\"\n 22:\t\tdepends on INET\n 23:\t\tdefault n\n 24:\t\thelp\n 25:\t\t This adds support for STMMAC Selftests using ethtool. Enable this\n 26:\t\t feature if you are facing problems with your HW and submit the test\n 27:\t\t results to the netdev Mailing List.\n 28:\t\n 29:\tconfig STMMAC_PLATFORM\n 30:\t\ttristate \"STMMAC Platform bus support\"\n 31:\t\tselect MFD_SYSCON\n 32:\t\tdefault y\n 33:\t\thelp\n 34:\t\t This selects the platform specific bus support for the stmmac driver.\n 35:\t\t This is the driver used on several SoCs:\n 36:\t\t STi, Allwinner, Amlogic Meson, Altera SOCFPGA.\n 37:\t\n 38:\t\t If you have a controller with this interface, say Y or M here.\n 39:\t\n 40:\t\t If unsure, say N.\n 41:\t\n 42:\tif STMMAC_PLATFORM\n 43:\t\n 44:\tconfig DWMAC_DWC_QOS_ETH\n 45:\t\ttristate \"Support for snps,dwc-qos-ethernet.txt DT binding.\"\n 46:\t\tselect CRC32\n 47:\t\tselect MII\n 48:\t\tdepends on OF \u0026\u0026 HAS_DMA\n 49:\t\thelp\n 50:\t\t Support for chips using the snps,dwc-qos-ethernet.txt DT binding.\n 51:\t\n 52:\tconfig DWMAC_GENERIC\n 53:\t\ttristate \"Generic driver for DWMAC\"\n 54:\t\tdefault STMMAC_PLATFORM\n 55:\t\thelp\n 56:\t\t Generic DWMAC driver for platforms that don't require any\n 57:\t\t platform specific code to function or is using platform\n 58:\t\t data for setup.\n 59:\t\n 60:\tconfig DWMAC_ANARION\n 61:\t\ttristate \"Adaptrum Anarion GMAC support\"\n 62:\t\tdefault ARC\n 63:\t\tdepends on OF \u0026\u0026 (ARC \|\| COMPILE_TEST)\n 64:\t\thelp\n 65:\t\t Support for Adaptrum Anarion GMAC Ethernet controller.\n 66:\t\n 67:\t\t This selects the Anarion SoC glue layer support for the stmmac driver.\n 68:\t\n 69:\tconfig DWMAC_EIC7700\n 70:\t\ttristate \"Support for Eswin eic7700 ethernet driver\"\n 71:\t\tdepends on OF \u0026\u0026 HAS_DMA \u0026\u0026 ARCH_ESWIN \|\| COMPILE_TEST\n 72:\t\thelp\n 73:\t\t This driver supports the Eswin EIC7700 Ethernet controller,\n 74:\t\t which integrates Synopsys DesignWare QoS features. It enables\n 75:\t\t high-speed networking with DMA acceleration and is optimized\n 76:\t\t for embedded systems.\n 77:\t\n 78:\tconfig DWMAC_INGENIC\n 79:\t\ttristate \"Ingenic MAC support\"\n 80:\t\tdefault MACH_INGENIC\n" }
13/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 26115 output: 43 thoughts: 25 Thoughts: Here's my thought process, as if I were considering this myself: Investigating STMMAC_ETH Usage Within the Kconfig System Okay, so I've identified `STMMAC_ETH`. Now I need to understand its wider implications within the kernel configuration. The logical next step is to delve deeper into the Kconfig files themselves. My immediate thought is to check how `STMMAC_ETH` is used. I'm specifically interested in seeing if it's connected to other important subsystems, and the first thing that jumps to mind is PCI. Are there any dependencies? Are there other configurations that also use it? I want to see the broader picture, and understand the relationships between different parts of the network stack. This will help me understand its scope and the implications of changing its settings. Let's see what the Kconfig files reveal.
14/2	2026/09/25 05:39	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig", "FirstLine": 81, "LineCount": 80 } Results: { "Contents": " 81:\t\tdepends on OF \u0026\u0026 HAS_IOMEM \u0026\u0026 (MACH_INGENIC \|\| COMPILE_TEST)\n 82:\t\tselect MFD_SYSCON\n 83:\t\thelp\n 84:\t\t Support for ethernet controller on Ingenic SoCs.\n 85:\t\n 86:\t\t This selects Ingenic SoCs glue layer support for the stmmac\n 87:\t\t device driver. This driver is used on for the Ingenic SoCs\n 88:\t\t MAC ethernet controller.\n 89:\t\n 90:\tconfig DWMAC_IPQ806X\n 91:\t\ttristate \"QCA IPQ806x DWMAC support\"\n 92:\t\tdefault ARCH_QCOM\n 93:\t\tdepends on OF \u0026\u0026 (ARCH_QCOM \|\| COMPILE_TEST)\n 94:\t\tselect MFD_SYSCON\n 95:\t\thelp\n 96:\t\t Support for QCA IPQ806X DWMAC Ethernet.\n 97:\t\n 98:\t\t This selects the IPQ806x SoC glue layer support for the stmmac\n 99:\t\t device driver. This driver does not use any of the hardware\n 100:\t\t acceleration features available on this SoC. Network devices\n 101:\t\t will behave like standard non-accelerated ethernet interfaces.\n 102:\t\n 103:\t\t Select the QCOM_SOCINFO config flag to enable specific dwmac\n 104:\t\t fixup based on the ipq806x SoC revision.\n 105:\t\n 106:\tconfig DWMAC_LPC18XX\n 107:\t\ttristate \"NXP LPC18xx/43xx DWMAC support\"\n 108:\t\tdefault ARCH_LPC18XX\n 109:\t\tdepends on OF \u0026\u0026 (ARCH_LPC18XX \|\| COMPILE_TEST)\n 110:\t\tselect MFD_SYSCON\n 111:\t\thelp\n 112:\t\t Support for NXP LPC18xx/43xx DWMAC Ethernet.\n 113:\t\n 114:\tconfig DWMAC_MEDIATEK\n 115:\t\ttristate \"MediaTek MT27xx GMAC support\"\n 116:\t\tdepends on OF \u0026\u0026 (ARCH_MEDIATEK \|\| COMPILE_TEST)\n 117:\t\thelp\n 118:\t\t Support for MediaTek GMAC Ethernet controller.\n 119:\t\n 120:\t\t This selects the MT2712 SoC support for the stmmac driver.\n 121:\t\n 122:\tconfig DWMAC_MESON\n 123:\t\ttristate \"Amlogic Meson dwmac support\"\n 124:\t\tdefault ARCH_MESON\n 125:\t\tdepends on OF \u0026\u0026 COMMON_CLK \u0026\u0026 (ARCH_MESON \|\| COMPILE_TEST)\n 126:\t\thelp\n 127:\t\t Support for Ethernet controller on Amlogic Meson SoCs.\n 128:\t\n 129:\t\t This selects the Amlogic Meson SoC glue layer support for\n 130:\t\t the stmmac device driver. This driver is used for Meson6,\n 131:\t\t Meson8, Meson8b and GXBB SoCs.\n 132:\t\n 133:\tconfig DWMAC_NUVOTON\n 134:\t\ttristate \"Nuvoton MA35 dwmac support\"\n 135:\t\tdefault ARCH_MA35\n 136:\t\tdepends on OF \u0026\u0026 (ARCH_MA35 \|\| COMPILE_TEST)\n 137:\t\tselect MFD_SYSCON\n 138:\t\thelp\n 139:\t\t Support for Ethernet controller on Nuvoton MA35 series SoC.\n 140:\t\n 141:\t\t This selects the Nuvoton MA35 series SoC glue layer support\n 142:\t\t for the stmmac device driver. The nuvoton-dwmac driver is\n 143:\t\t used for MA35 series SoCs.\n 144:\t\n 145:\tconfig DWMAC_QCOM_ETHQOS\n 146:\t\ttristate \"Qualcomm ETHQOS support\"\n 147:\t\tdefault ARCH_QCOM\n 148:\t\tdepends on OF \u0026\u0026 (ARCH_QCOM \|\| COMPILE_TEST)\n 149:\t\thelp\n 150:\t\t Support for the Qualcomm ETHQOS core.\n 151:\t\n 152:\t\t This selects the Qualcomm ETHQOS glue layer support for the\n 153:\t\t stmmac device driver.\n 154:\t\n 155:\tconfig DWMAC_RENESAS_GBETH\n 156:\t\ttristate \"Renesas RZ/V2H(P) GBETH and RZ/T2H, RZ/N2H GMAC support\"\n 157:\t\tdefault ARCH_RENESAS\n 158:\t\tdepends on OF \u0026\u0026 (ARCH_RENESAS \|\| COMPILE_TEST)\n 159:\t\tselect PCS_RZN1_MIIC\n 160:\t\thelp\n" }
15/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 27664 output: 45 thoughts: 9 Thoughts: Okay, here's my attempt at summarizing the thought process, tailored for an expert audience, and written in the first person: Diving Deeper into Kconfig Alright, time to dig into this Kconfig file further. I've got a handle on the basics, but I need to understand the nuances of this particular configuration. I want to see how these options are related, how dependencies are defined, and what the implications of each selection might be. I'm looking for the structure, the conditional logic, and the overall design philosophy embedded within this specific Kconfig file. Let's see if there are any subtle tricks or unusual approaches here that I can learn from. I'm particularly interested in seeing how they've handled potential conflicts or edge cases. Time to parse this and gain a deeper understanding of its implications. Let's get to it.
16/2	2026/09/25 05:39	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig", "FirstLine": 161, "LineCount": 100 } Results: { "Contents": " 161:\t\t Support for Gigabit Ethernet Interface (GBETH)/ Ethernet MAC (GMAC)\n 162:\t\t on Renesas SoCs.\n 163:\t\n 164:\t\t This selects Renesas SoC glue layer support for the stmmac device\n 165:\t\t driver. This driver is used for the RZ/V2H(P) family, RZ/T2H and\n 166:\t\t RZ/N2H SoCs.\n 167:\t\n 168:\tconfig DWMAC_ROCKCHIP\n 169:\t\ttristate \"Rockchip dwmac support\"\n 170:\t\tdefault ARCH_ROCKCHIP\n 171:\t\tdepends on OF \u0026\u0026 (ARCH_ROCKCHIP \|\| COMPILE_TEST)\n 172:\t\tselect MFD_SYSCON\n 173:\t\thelp\n 174:\t\t Support for Ethernet controller on Rockchip RK3288 SoC.\n 175:\t\n 176:\t\t This selects the Rockchip RK3288 SoC glue layer support for\n 177:\t\t the stmmac device driver.\n 178:\t\n 179:\tconfig DWMAC_RZN1\n 180:\t\ttristate \"Renesas RZ/N1 dwmac support\"\n 181:\t\tdefault ARCH_RZN1\n 182:\t\tdepends on OF \u0026\u0026 (ARCH_RZN1 \|\| COMPILE_TEST)\n 183:\t\tselect PCS_RZN1_MIIC\n 184:\t\thelp\n 185:\t\t Support for Ethernet controller on Renesas RZ/N1 SoC family.\n 186:\t\n 187:\t\t This selects the Renesas RZ/N1 SoC glue layer support for\n 188:\t\t the stmmac device driver. This support can make use of a custom MII\n 189:\t\t converter PCS device.\n 190:\t\n 191:\tconfig DWMAC_S32\n 192:\t\ttristate \"NXP S32G/S32R GMAC support\"\n 193:\t\tdefault ARCH_S32\n 194:\t\tdepends on OF \u0026\u0026 (ARCH_S32 \|\| COMPILE_TEST)\n 195:\t\thelp\n 196:\t\t Support for ethernet controller on NXP S32CC SOCs.\n 197:\t\n 198:\t\t This selects NXP SoC glue layer support for the stmmac\n 199:\t\t device driver. This driver is used for the S32CC series\n 200:\t\t SOCs GMAC ethernet controller, ie. S32G2xx, S32G3xx and\n 201:\t\t S32R45.\n 202:\t\n 203:\tconfig DWMAC_SOCFPGA\n 204:\t\ttristate \"SOCFPGA dwmac support\"\n 205:\t\tdefault ARCH_INTEL_SOCFPGA\n 206:\t\tdepends on OF \u0026\u0026 (ARCH_INTEL_SOCFPGA \|\| COMPILE_TEST)\n 207:\t\tselect MFD_SYSCON\n 208:\t\tselect MDIO_REGMAP\n 209:\t\tselect REGMAP_MMIO\n 210:\t\tselect PCS_LYNX\n 211:\t\thelp\n 212:\t\t Support for ethernet controller on Altera SOCFPGA\n 213:\t\n 214:\t\t This selects the Altera SOCFPGA SoC glue layer support\n 215:\t\t for the stmmac device driver. This driver is used for\n 216:\t\t arria5 and cyclone5 FPGA SoCs.\n 217:\t\n 218:\tconfig DWMAC_SOPHGO\n 219:\t\ttristate \"Sophgo dwmac support\"\n 220:\t\tdepends on OF \u0026\u0026 (ARCH_SOPHGO \|\| COMPILE_TEST)\n 221:\t\tdefault m if ARCH_SOPHGO\n 222:\t\thelp\n 223:\t\t Support for ethernet controllers on Sophgo RISC-V SoCs\n 224:\t\n 225:\t\t This selects the Sophgo SoC specific glue layer support\n 226:\t\t for the stmmac device driver. This driver is used for the\n 227:\t\t ethernet controllers on various Sophgo SoCs.\n 228:\t\n 229:\tconfig DWMAC_SPACEMIT\n 230:\t\ttristate \"Spacemit dwmac support\"\n 231:\t\tdepends on OF \u0026\u0026 (ARCH_SPACEMIT \|\| COMPILE_TEST)\n 232:\t\tselect MFD_SYSCON\n 233:\t\tdefault m if ARCH_SPACEMIT\n 234:\t\thelp\n 235:\t\t Support for ethernet controllers on Spacemit RISC-V SoCs\n 236:\t\n 237:\t\t This selects the Spacemit platform specific glue layer support\n 238:\t\t for the stmmac device driver. This driver is used for the\n 239:\t\t Spacemit K3 ethernet controllers.\n 240:\t\n 241:\tconfig DWMAC_STARFIVE\n 242:\t\ttristate \"StarFive dwmac support\"\n 243:\t\tdepends on OF \u0026\u0026 (ARCH_STARFIVE \|\| COMPILE_TEST)\n 244:\t\tselect MFD_SYSCON\n 245:\t\tdefault m if ARCH_STARFIVE\n 246:\t\thelp\n 247:\t\t Support for ethernet controllers on StarFive RISC-V SoCs\n 248:\t\n 249:\t\t This selects the StarFive platform specific glue layer support\n 250:\t\t for the stmmac device driver. This driver is used for the\n 251:\t\t StarFive JH7100 and JH7110 ethernet controllers.\n 252:\t\n 253:\tconfig DWMAC_STI\n 254:\t\ttristate \"STi GMAC support\"\n 255:\t\tdefault ARCH_STI\n 256:\t\tdepends on OF \u0026\u0026 (ARCH_STI \|\| COMPILE_TEST)\n 257:\t\tselect MFD_SYSCON\n 258:\t\thelp\n 259:\t\t Support for ethernet controller on STi SOCs.\n 260:\t\n" }
17/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 29483 output: 44 thoughts: 8 Thoughts: Okay, here's the summary, assuming I'm deeply familiar with Kconfig: Diving Back into Kconfig Alright, time to get back into Kconfig. No time to waste. I need to keep moving through the documentation/code/whatever this refers to. It's a fundamental part of the build system, so understanding it thoroughly is key. Let's see what interesting tidbits and nuances await this time. I expect that I'll either learn something new or find something familiar that I can better explain to someone else. Time to delve back in!
18/2	2026/09/25 05:39	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig", "FirstLine": 261, "LineCount": 80 } Results: { "Contents": " 261:\t\t This selects STi SoC glue layer support for the stmmac\n 262:\t\t device driver. This driver is used on for the STi series\n 263:\t\t SOCs GMAC ethernet controller.\n 264:\t\n 265:\tconfig DWMAC_STM32\n 266:\t\ttristate \"STM32 DWMAC support\"\n 267:\t\tdefault ARCH_STM32\n 268:\t\tdepends on OF \u0026\u0026 HAS_IOMEM \u0026\u0026 (ARCH_STM32 \|\| COMPILE_TEST)\n 269:\t\tselect MFD_SYSCON\n 270:\t\thelp\n 271:\t\t Support for ethernet controller on STM32 SOCs.\n 272:\t\n 273:\t\t This selects STM32 SoC glue layer support for the stmmac\n 274:\t\t device driver. This driver is used on for the STM32 series\n 275:\t\t SOCs GMAC ethernet controller.\n 276:\t\n 277:\tconfig DWMAC_SUNXI\n 278:\t\ttristate \"Allwinner GMAC support\"\n 279:\t\tdefault ARCH_SUNXI\n 280:\t\tdepends on OF \u0026\u0026 (ARCH_SUNXI \|\| COMPILE_TEST)\n 281:\t\thelp\n 282:\t\t Support for Allwinner A20/A31 GMAC ethernet controllers.\n 283:\t\n 284:\t\t This selects Allwinner SoC glue layer support for the\n 285:\t\t stmmac device driver. This driver is used for A20/A31\n 286:\t\t GMAC ethernet controller.\n 287:\t\n 288:\tconfig DWMAC_SUN8I\n 289:\t\ttristate \"Allwinner sun8i GMAC support\"\n 290:\t\tdefault ARCH_SUNXI\n 291:\t\tdepends on OF \u0026\u0026 (ARCH_SUNXI \|\| COMPILE_TEST)\n 292:\t\tselect MDIO_BUS_MUX\n 293:\t\thelp\n 294:\t\t Support for Allwinner H3 A83T A64 EMAC ethernet controllers.\n 295:\t\n 296:\t\t This selects Allwinner SoC glue layer support for the\n 297:\t\t stmmac device driver. This driver is used for H3/A83T/A64\n 298:\t\t EMAC ethernet controller.\n 299:\t\n 300:\tconfig DWMAC_SUN55I\n 301:\t\ttristate \"Allwinner sun55i GMAC200 support\"\n 302:\t\tdefault ARCH_SUNXI\n 303:\t\tdepends on OF \u0026\u0026 (ARCH_SUNXI \|\| COMPILE_TEST)\n 304:\t\tselect MDIO_BUS_MUX\n 305:\t\thelp\n 306:\t\t Support for Allwinner A523/T527 GMAC200 ethernet controllers.\n 307:\t\n 308:\t\t This selects Allwinner SoC glue layer support for the\n 309:\t\t stmmac device driver. This driver is used for A523/T527\n 310:\t\t GMAC200 ethernet controller.\n 311:\t\n 312:\tconfig DWMAC_THEAD\n 313:\t\ttristate \"T-HEAD dwmac support\"\n 314:\t\tdepends on OF \u0026\u0026 (ARCH_THEAD \|\| COMPILE_TEST)\n 315:\t\thelp\n 316:\t\t Support for ethernet controllers on T-HEAD RISC-V SoCs\n 317:\t\n 318:\t\t This selects the T-HEAD platform specific glue layer support for\n 319:\t\t the stmmac device driver. This driver is used for T-HEAD TH1520\n 320:\t\t ethernet controller.\n 321:\t\n 322:\tconfig DWMAC_ULTRARISC\n 323:\t\ttristate \"UltraRISC DWMAC support\"\n 324:\t\tdefault ARCH_ULTRARISC\n 325:\t\tdepends on OF \u0026\u0026 (ARCH_ULTRARISC \|\| COMPILE_TEST)\n 326:\t\thelp\n 327:\t\t Support for the Ethernet controller on the UltraRISC DP1000 SoC.\n 328:\t\n 329:\t\t This selects the UltraRISC platform specific glue layer support\n 330:\t\t for the stmmac device driver. This driver is used for the DP1000\n 331:\t\t GMAC Ethernet controller.\n 332:\t\n 333:\tconfig DWMAC_IMX8\n 334:\t\ttristate \"NXP IMX8 DWMAC support\"\n 335:\t\tdefault ARCH_MXC\n 336:\t\tdepends on OF \u0026\u0026 (ARCH_MXC \|\| COMPILE_TEST)\n 337:\t\tselect MFD_SYSCON\n 338:\t\thelp\n 339:\t\t Support for ethernet controller on NXP i.MX8 SOCs.\n 340:\t\n" }
19/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 30940 output: 44 thoughts: 15 Thoughts: Here's my take on those thoughts: Peering into the Kconfig Depths Okay, let's dive in. I need to understand the implications of something – presumably, a configuration option or dependency – and the logical starting point is the Kconfig file. Line 340, huh? That's a specific entry point. It suggests I have a pretty good idea of the general area I'm interested in, or at least a hunch about where the relevant configuration might be defined or influenced. Let's see what the code at line 340 tells me, and what it relates to. This will guide my understanding of the relevant Kconfig options and their dependencies.
20/2	2026/09/25 05:39	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig", "FirstLine": 341, "LineCount": 80 } Results: { "Contents": " 341:\t\t This selects NXP SoC glue layer support for the stmmac\n 342:\t\t device driver. This driver is used for i.MX8 series like\n 343:\t\t iMX8MP/iMX8DXL GMAC ethernet controller.\n 344:\t\n 345:\tconfig DWMAC_INTEL_PLAT\n 346:\t\ttristate \"Intel dwmac support\"\n 347:\t\tdepends on OF \u0026\u0026 COMMON_CLK\n 348:\t\thelp\n 349:\t\t Support for ethernet controllers on Intel SoCs\n 350:\t\n 351:\t\t This selects the Intel platform specific glue layer support for\n 352:\t\t the stmmac device driver. This driver is used for the Intel Keem Bay\n 353:\t\t SoC.\n 354:\t\n 355:\tconfig DWMAC_LOONGSON1\n 356:\t\ttristate \"Loongson1 GMAC support\"\n 357:\t\tdefault MACH_LOONGSON32\n 358:\t\tdepends on OF \u0026\u0026 (MACH_LOONGSON32 \|\| COMPILE_TEST)\n 359:\t\thelp\n 360:\t\t Support for ethernet controller on Loongson1 SoC.\n 361:\t\n 362:\t\t This selects Loongson1 SoC glue layer support for the stmmac\n 363:\t\t device driver. This driver is used for Loongson1-based boards\n 364:\t\t like Loongson LS1B/LS1C.\n 365:\t\n 366:\tconfig DWMAC_TEGRA\n 367:\t\ttristate \"NVIDIA Tegra MGBE support\"\n 368:\t\tdepends on ARCH_TEGRA \|\| COMPILE_TEST\n 369:\t\thelp\n 370:\t\t This selects the Multi-GigaBit Ethernet (MGBE) Controller that is\n 371:\t\t found on the NVIDIA Tegra SoC devices. This driver provides the glue\n 372:\t\t layer on top of the stmmac driver required for these NVIDIA Tegra SoC\n 373:\t\t devices.\n 374:\t\n 375:\tconfig DWMAC_VISCONTI\n 376:\t\ttristate \"Toshiba Visconti DWMAC support\"\n 377:\t\tdefault ARCH_VISCONTI\n 378:\t\tdepends on OF \u0026\u0026 COMMON_CLK \u0026\u0026 (ARCH_VISCONTI \|\| COMPILE_TEST)\n 379:\t\thelp\n 380:\t\t Support for ethernet controller on Visconti SoCs.\n 381:\t\n 382:\tendif # STMMAC_PLATFORM\n 383:\t\n 384:\tconfig STMMAC_LIBPCI\n 385:\t\ttristate\n 386:\t\thelp\n 387:\t\t This option enables the PCI bus helpers for the stmmac driver.\n 388:\t\n 389:\tconfig DWMAC_INTEL\n 390:\t\ttristate \"Intel GMAC support\"\n 391:\t\tdefault X86\n 392:\t\tdepends on X86 \u0026\u0026 PCI\n 393:\t\tdepends on COMMON_CLK\n 394:\t\tdepends on ACPI\n 395:\t\thelp\n 396:\t\t This selects the Intel platform specific bus support for the\n 397:\t\t stmmac driver. This driver is used for Intel Quark/EHL/TGL.\n 398:\t\n 399:\tconfig DWMAC_LOONGSON\n 400:\t\ttristate \"Loongson PCI DWMAC support\"\n 401:\t\tdefault MACH_LOONGSON64\n 402:\t\tdepends on (MACH_LOONGSON64 \|\| COMPILE_TEST) \u0026\u0026 PCI\n 403:\t\tdepends on COMMON_CLK\n 404:\t\tselect STMMAC_LIBPCI\n 405:\t\thelp\n 406:\t\t This selects the LOONGSON PCI bus support for the stmmac driver,\n 407:\t\t Support for ethernet controller on Loongson-2K1000 SoC and LS7A1000 bridge.\n 408:\t\n 409:\tconfig DWMAC_MOTORCOMM\n 410:\t\ttristate \"Motorcomm PCI DWMAC support\"\n 411:\t\tdepends on PCI\n 412:\t\tselect MOTORCOMM_PHY\n 413:\t\tselect STMMAC_LIBPCI\n 414:\t\thelp\n 415:\t\t This enables glue driver for Motorcomm DWMAC-based PCI Ethernet\n 416:\t\t controllers. Currently only YT6801 is supported.\n 417:\t\n 418:\tconfig STMMAC_PCI\n 419:\t\ttristate \"STMMAC PCI bus support\"\n 420:\t\tdepends on PCI\n" }
21/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 32366 output: 23 thoughts: 77 Thoughts: Okay, here's my thought process as I'd articulate it: Digging into the DWMAC Driver Landscape Right, let's start by surveying the DWMAC drivers, cataloging what's available. I'm seeing `DWMAC_INTEL`, `DWMAC_LOONGSON`, `DWMAC_MOTORCOMM`, and `STMMAC_PCI`. But that's a bit broad. What I really want to understand is which of these specifically leverage `dwxgmac2`. I need to isolate the code that's tied to that particular XGMAC implementation. So, instead of just generally surveying, I'll refine my search. I'm going to look for either `DWMAC_CORE_XGMAC` or the literal string `dwxgmac2` across the entire kernel source tree. That should give me a much more focused view of where this specific XGMAC variant is used and, therefore, the key drivers I should be examining more closely. This will tell me which drivers are actually using the specific XGMAC feature set of interest.
22/2	2026/09/25 05:39	tool	grepper	0m Args: { "Expression": "DWMAC_CORE_XGMAC" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/common.h=49=static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)\ndrivers/net/ethernet/stmicro/stmmac/common.h-50-{\ndrivers/net/ethernet/stmicro/stmmac/common.h:51:\treturn core_type == DWMAC_CORE_GMAC4 \|\| core_type == DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/common.h-52-}\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=569=static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-572-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:573:\tplat_dat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-574-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c=214=static int tegra_mgbe_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-325-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c:326:\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-327-\tplat-\u003eflags \|= STMMAC_FLAG_TSO_EN;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=21=static void stmmac_get_version(struct stmmac_priv priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-49-\tver-\u003esnpsver = FIELD_GET(DWMAC_SNPSVER, version);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:50:\tif (core_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-51-\t\tver-\u003edev_id = FIELD_GET(DWMAC_USERVER, version);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-247-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:248:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-249-\t\t.min_id = DWXGMAC_CORE_2_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-269-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:270:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-271-\t\t.min_id = DWXLGMAC_CORE_2_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=294=stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-306-\t\t\tcontinue;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:307:\t\tif (core_type == DWMAC_CORE_XGMAC \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-308-\t\t dev_id != entry-\u003edev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=28=static int est_configure(struct stmmac_priv priv, struct stmmac_est cfg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-55-\tctrl = readl(est_addr + EST_CONTROL);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:56:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-57-\t\tctrl \u0026= ~EST_XGMAC_PTOV;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=83=static void est_irq_status(struct stmmac_priv priv, struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-150-\tif (status \u0026 EST_BTRE) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:151:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-152-\t\t\tbtrl = FIELD_GET(EST_XGMAC_BTRL, status);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=301=static void stmmac_ethtool_getdrvinfo(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-308-\t\tstrscpy(info-\u003edriver, GMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:309:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-310-\t\tstrscpy(info-\u003edriver, XGMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=350=static int stmmac_ethtool_get_regs_len(struct net_device dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-353-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:354:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-355-\t\treturn XGMAC_REGSIZE 4;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=361=static void stmmac_ethtool_gregs(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-375-\t\t NUM_DWMAC4_DMA_REGS 4);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:376:\t} else if (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-377-\t\tmemcpy(\u0026reg_space[ETHTOOL_DMA_OFFSET],\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=642=static int stmmac_hwtstamp_set(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-759-\t\t\tif (priv-\u003esynopsys_id \u003c DWMAC_CORE_3_70 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:760:\t\t\t priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-761-\t\t\t\tts_event_en = PTP_TCR_TSEVNTENA;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6608=static int stmmac_dma_cap_show(struct seq_file seq, void v)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6643-\t\t (priv-\u003edma_cap.half_duplex) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6644:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6645-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6679-\t\t (priv-\u003edma_cap.atime_stamp) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6680:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6681-\t\tseq_printf(seq, \"\\tTimestamp System Time Source: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6688-\tif (priv-\u003esynopsys_id \u003e= DWMAC_CORE_4_00 \|\|\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6689:\t priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6690-\t\tseq_printf(seq, \"\\tIP Checksum Offload in RX: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7421=static void stmmac_print_actphyif(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7436-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7437:\tcase DWMAC_CORE_XGMAC:\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7438-\t\tphyif_table = stmmac_dwxgmac_phyif;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7463=static int stmmac_hw_init(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7612-\tif ((priv-\u003esynopsys_id \u003e= DWMAC_CORE_3_50 \|\|\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7613:\t priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7614-\t !priv-\u003eplat-\u003eriwt_off) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7878=static int __stmmac_dvr_probe(struct device device,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8085-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:8086:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8087-\t\tndev-\u003emax_mtu = XGMAC_JUMBO_LEN;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=536=static u32 stmmac_clk_csr_set(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-554-\t\trates = stmmac_sun8i_csr_to_mdc;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:555:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-556-\t\trates = stmmac_xgmac_csr_to_mdc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=595=int stmmac_mdio_register(struct net_device ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-621-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:622:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-623-\t\tnew_bus-\u003eread = \u0026stmmac_xgmac2_mdio_read_c22;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-665-\t/* Looks like we need a dummy read for XGMAC only and C45 PHYs /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:666:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-667-\t\tstmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c=415=stmmac_probe_config_dt(struct platform_device pdev, u8 *mac)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-546-\tif (of_device_is_compatible(np, \"snps,dwxgmac\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:547:\t\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-548-\t\tplat-\u003epmt = true;\n--\ninclude/linux/stmmac.h=191=enum dwmac_core_type {\n--\ninclude/linux/stmmac.h-194-\tDWMAC_CORE_GMAC4,\ninclude/linux/stmmac.h:195:\tDWMAC_CORE_XGMAC,\ninclude/linux/stmmac.h-196-};\n" }
23/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 36758 output: 49 thoughts: 219 Thoughts: Analyzing DWMAC_CORE_XGMAC Implementations Okay, let's break this down. My initial thought process is to trace where `DWMAC_CORE_XGMAC` is actually defined and utilized. I've noted three key areas so far: first, in the `socfpga_agilex5_setup_plat_dat` function within `dwmac-socfpga.c`, which clearly pertains to Altera/Intel SoC FPGA Agilex5 systems (ARM64 with Device Tree). Second, `dwmac-tegra.c` and its `tegra_mgbe_probe` function indicates use within NVIDIA Tegra platforms (also ARM64 with Device Tree). Then there's `stmmac_platform.c`, where there's an `if` condition using `of_device_is_compatible` checking for "snps,dwxgmac" in Open Firmware Device Tree platforms; if found, we set the core type. The next obvious question is whether there are any PCI-based instances of this? My mental checklist now jumps to the PCI-specific files: `stmmac_pci.c`, `dwmac-intel.c`, and potentially `dwmac-loongson.c`, etc. I need to quickly scan those sources to see if XGMAC is also configured through PCI. This is important to determine the complete scope of where this core is deployed. I need to make sure I understand all the possible instantiations of this core.
24/2	2026/09/25 05:39	tool	grepper	0m Error: no matches Args: { "Expression": "dwxgmac\|XGMAC", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c" } Results: { "error": "no matches" }
25/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 37363 output: 47 thoughts: 12 Thoughts: Okay, let's dive in. Here's my understanding of what we're looking at, framed as my own mental process: Diving into the `dwmac-intel.c` Source Code Alright, I'm thinking, time to crack open `dwmac-intel.c`. That's where I need to start, I'm sure of it. This file is going to be key to understanding the Intel-specific aspects of this DWMAC driver implementation. I expect to see the hardware initialization, the register definitions, interrupt handling specific to Intel chipsets... all the low-level details that deviate from the more generic DWMAC framework. I need to get a handle on how they've customized the core MAC driver for Intel's network controllers. I anticipate potential hardware quirks, special registers, and platform-specific clock configuration code lurking within. It's time to become familiar with Intel's interpretation of the standard DWMAC interface. Let's see what interesting tidbits we can dig up.
26/2	2026/09/25 05:39	tool	grepper	0m Error: no matches Args: { "Expression": "dwxgmac\|XGMAC", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c" } Results: { "error": "no matches" }
27/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 37652 output: 37 thoughts: 23 Thoughts: Okay, here's my summary, tailored for an expert audience, presented as if it were my thought process: Diving into the `stmmac_pci.c` Code Alright, before I get too deep into this, I need to understand how this particular STMMAC device is being initialized, particularly on the PCI bus. Let's see... the `stmmac_pci.c` file should hold the key, right? I want to pinpoint where the driver sets the `core_type`. That will give me a critical piece of the puzzle to proceed. Let's start there.
28/2	2026/09/25 05:39	tool	grepper	0m Args: { "Expression": "core_type", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/common.h-48-\ndrivers/net/ethernet/stmicro/stmmac/common.h:49:static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)\ndrivers/net/ethernet/stmicro/stmmac/common.h-50-{\ndrivers/net/ethernet/stmicro/stmmac/common.h:51:\treturn core_type == DWMAC_CORE_GMAC4 \|\| core_type == DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/common.h-52-}\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c=36=static int dwc_eth_dwmac_config_dt(struct platform_device pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c-87-\t/ dwc-qos needs GMAC4, AAL, TSO and PMT /\ndrivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c:88:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c-89-\tplat_dat-\u003edma_cfg-\u003eaal = 1;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=596=static void common_default_data(struct plat_stmmacenet_data plat)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-599-\tplat-\u003eclk_csr = STMMAC_CSR_20_35M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:600:\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-601-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=616=static int intel_mgbe_common_data(struct pci_dev pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-626-\tplat-\u003eclk_csr = STMMAC_CSR_250_300M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:627:\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-628-\tplat-\u003eforce_sf_dma_mode = 0;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c=374=static int ipq806x_gmac_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c-475-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c:476:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c-477-\tplat_dat-\u003ebsp_priv = gmac;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c=86=static void loongson_default_data(struct pci_dev pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c-95-\tplat-\u003eclk_csr = STMMAC_CSR_100_150M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c:96:\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c-97-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c=42=static int lpc18xx_dwmac_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c-56-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c:57:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c-58-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c=208=motorcomm_default_plat_data(struct pci_dev pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c-247-\tplat-\u003eclk_ref_rate\t= 125000000;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c:248:\tplat-\u003ecore_type\t\t= DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c-249-\tplat-\u003esuspend\t\t= stmmac_pci_plat_suspend;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c=684=static int qcom_ethqos_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c-776-\tplat_dat-\u003eptp_clk_freq_config = ethqos_ptp_clk_freq_config;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c:777:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c-778-\tif (ethqos-\u003ehas_emac_ge_3)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c=1571=static int rk_gmac_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c-1594-\t /\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c:1595:\tif (plat_dat-\u003ecore_type != DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c:1596:\t\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c-1597-\t\tplat_dat-\u003erx_fifo_size = 4096;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-s32.c=144=static int s32_dwmac_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-s32.c-195-\t/ S32CC core feature set /\ndrivers/net/ethernet/stmicro/stmmac/dwmac-s32.c:196:\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-s32.c-197-\tplat-\u003epmt = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=559=static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-562-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:563:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-564-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=569=static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-572-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:573:\tplat_dat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-574-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c=99=static int sun7i_gmac_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c-138-\tplat_dat-\u003etx_coe = true;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c:139:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c-140-\tplat_dat-\u003ebsp_priv = gmac;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c=214=static int tegra_mgbe_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-325-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c:326:\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-327-\tplat-\u003eflags \|= STMMAC_FLAG_TSO_EN;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=21=static void stmmac_get_version(struct stmmac_priv priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-23-{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:24:\tenum dwmac_core_type core_type = priv-\u003eplat-\u003ecore_type;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-25-\tunsigned int version_offset;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-30-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:31:\tif (core_type == DWMAC_CORE_MAC100)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-32-\t\treturn;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-33-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:34:\tif (core_type == DWMAC_CORE_GMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-35-\t\tversion_offset = GMAC_VERSION;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-49-\tver-\u003esnpsver = FIELD_GET(DWMAC_SNPSVER, version);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:50:\tif (core_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-51-\t\tver-\u003edev_id = FIELD_GET(DWMAC_USERVER, version);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:112:\tenum dwmac_core_type core_type;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-113-\tu32 min_id;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-130-\t{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:131:\t\t.core_type = DWMAC_CORE_MAC100,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-132-\t\t.min_id = 0,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-147-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:148:\t\t.core_type = DWMAC_CORE_GMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-149-\t\t.min_id = 0,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-164-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:165:\t\t.core_type = DWMAC_CORE_GMAC4,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-166-\t\t.min_id = 0,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-184-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:185:\t\t.core_type = DWMAC_CORE_GMAC4,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-186-\t\t.min_id = DWMAC_CORE_4_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-205-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:206:\t\t.core_type = DWMAC_CORE_GMAC4,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-207-\t\t.min_id = DWMAC_CORE_4_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-226-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:227:\t\t.core_type = DWMAC_CORE_GMAC4,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-228-\t\t.min_id = DWMAC_CORE_5_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-247-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:248:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-249-\t\t.min_id = DWXGMAC_CORE_2_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-269-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:270:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-271-\t\t.min_id = DWXLGMAC_CORE_2_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=293=static const struct stmmac_hwif_entry \ndrivers/net/ethernet/stmicro/stmmac/hwif.c:294:stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-295-{\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-301-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:302:\t\tif (core_type != entry-\u003ecore_type)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-303-\t\t\tcontinue;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-306-\t\t\tcontinue;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:307:\t\tif (core_type == DWMAC_CORE_XGMAC \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-308-\t\t dev_id != entry-\u003edev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=317=int stmmac_hwif_init(struct stmmac_priv priv)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-318-{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:319:\tenum dwmac_core_type core_type = priv-\u003eplat-\u003ecore_type;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-320-\tconst struct stmmac_hwif_entry entry;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-348-\t/ Use synopsys_id var because some setups can override this /\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:349:\tentry = stmmac_hwif_find(core_type, priv-\u003esynopsys_id, version.dev_id);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-350-\tif (!entry) {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-352-\t\t\t\"Failed to find HW IF (id=0x%x, gmac=%d/%d)\\n\",\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:353:\t\t\tversion.snpsver, core_type == DWMAC_CORE_GMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:354:\t\t\tcore_type == DWMAC_CORE_GMAC4);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-355-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=28=static int est_configure(struct stmmac_priv priv, struct stmmac_est cfg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-55-\tctrl = readl(est_addr + EST_CONTROL);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:56:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-57-\t\tctrl \u0026= ~EST_XGMAC_PTOV;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=83=static void est_irq_status(struct stmmac_priv priv, struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-150-\tif (status \u0026 EST_BTRE) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:151:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-152-\t\t\tbtrl = FIELD_GET(EST_XGMAC_BTRL, status);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=301=static void stmmac_ethtool_getdrvinfo(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-305-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:306:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC \|\|\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:307:\t priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-308-\t\tstrscpy(info-\u003edriver, GMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:309:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-310-\t\tstrscpy(info-\u003edriver, XGMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=350=static int stmmac_ethtool_get_regs_len(struct net_device dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-353-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:354:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-355-\t\treturn XGMAC_REGSIZE 4;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:356:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-357-\t\treturn GMAC4_REG_SPACE_SIZE;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=361=static void stmmac_ethtool_gregs(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-370-\t/ Copy DMA registers to where ethtool expects them /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:371:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-372-\t\t/ GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR /\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-375-\t\t NUM_DWMAC4_DMA_REGS 4);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:376:\t} else if (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-377-\t\tmemcpy(\u0026reg_space[ETHTOOL_DMA_OFFSET],\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=576=static void stmmac_get_rx_hwtstamp(struct stmmac_priv priv, struct dma_desc p,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-585-\t/* For GMAC4, the valid timestamp is from CTX next desc. /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:586:\tif (dwmac_is_xmac(priv-\u003eplat-\u003ecore_type))\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-587-\t\tdesc = np;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=604=static void stmmac_update_subsecond_increment(struct stmmac_priv priv)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-605-{\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:606:\tbool xmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-607-\tu32 sec_inc = 0;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=642=static int stmmac_hwtstamp_set(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-759-\t\t\tif (priv-\u003esynopsys_id \u003c DWMAC_CORE_3_70 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:760:\t\t\t priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-761-\t\t\t\tts_event_en = PTP_TCR_TSEVNTENA;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=910=static int stmmac_init_timestamping(struct stmmac_priv priv)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-911-{\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:912:\tbool xmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-913-\tint ret;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=2600=static void stmmac_dma_operation_mode(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-2616-\t/ Split up the shared Tx/Rx FIFO memory on DW QoS Eth and DW XGMAC /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:2617:\tif (dwmac_is_xmac(priv-\u003eplat-\u003ecore_type)) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-2618-\t\trxfifosz /= rx_channels_count;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=4428=static void stmmac_set_gso_features(struct net_device ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-4457-\tndev-\u003ehw_features \|= NETIF_F_TSO \| NETIF_F_TSO6;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:4458:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-4459-\t\tndev-\u003ehw_features \|= NETIF_F_GSO_UDP_L4;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=5206=static unsigned int stmmac_rx_buf2_len(struct stmmac_priv priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-5231-\t/ Not GMAC4 and not last descriptor /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:5232:\tif (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_GMAC4 \u0026\u0026 (status \u0026 rx_not_ls))\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-5233-\t\treturn priv-\u003edma_conf.dma_buf_sz;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6290=static void stmmac_common_interrupt(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6297-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6298:\txmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6299-\tqueues_count = (rx_cnt \u003e tx_cnt) ? rx_cnt : tx_cnt;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6311-\t/* To handle GMAC own interrupts /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6312:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC \|\| xmac) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6313-\t\tint status = stmmac_host_irq_status(priv, \u0026priv-\u003exstats);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6608=static int stmmac_dma_cap_show(struct seq_file seq, void v)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6643-\t\t (priv-\u003edma_cap.half_duplex) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6644:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6645-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6647-\t\t\t priv-\u003edma_cap.multi_addr);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6648:\t} else if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6649-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6679-\t\t (priv-\u003edma_cap.atime_stamp) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6680:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6681-\t\tseq_printf(seq, \"\\tTimestamp System Time Source: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6688-\tif (priv-\u003esynopsys_id \u003e= DWMAC_CORE_4_00 \|\|\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6689:\t priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6690-\t\tseq_printf(seq, \"\\tIP Checksum Offload in RX: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7421=static void stmmac_print_actphyif(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7426-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7427:\tswitch (priv-\u003eplat-\u003ecore_type) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7428-\tcase DWMAC_CORE_MAC100:\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7463=static int stmmac_hw_init(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7563-\t /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7564:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7565-\t\tpriv-\u003ehw-\u003emulti_addr = priv-\u003edma_cap.multi_addr;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7612-\tif ((priv-\u003esynopsys_id \u003e= DWMAC_CORE_3_50 \|\|\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7613:\t priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7614-\t !priv-\u003eplat-\u003eriwt_off) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7722=static int stmmac_xdp_rx_timestamp(const struct xdp_md _ctx, u64 timestamp)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7734-\t/* For GMAC4, the valid timestamp is from CTX next desc. /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7735:\tif (dwmac_is_xmac(priv-\u003eplat-\u003ecore_type))\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7736-\t\tdesc_contains_ts = ndesc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7878=static int __stmmac_dvr_probe(struct device device,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8056-\tndev-\u003efeatures \|= NETIF_F_HW_VLAN_CTAG_RX \| NETIF_F_HW_VLAN_STAG_RX;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:8057:\tif (dwmac_is_xmac(priv-\u003eplat-\u003ecore_type)) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8058-\t\tndev-\u003ehw_features \|= NETIF_F_HW_VLAN_CTAG_RX;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8085-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:8086:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8087-\t\tndev-\u003emax_mtu = XGMAC_JUMBO_LEN;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=299=static int stmmac_mdio_read_c22(struct mii_bus bus, int phyaddr, int phyreg)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-303-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:304:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-305-\t\tcmd = MII_GMAC4_READ;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=341=static int stmmac_mdio_write_c22(struct mii_bus bus, int phyaddr, int phyreg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-346-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:347:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-348-\t\tcmd = MII_GMAC4_WRITE;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=381=int stmmac_mdio_reset(struct mii_bus bus)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-419-\t /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:420:\tif (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-421-\t\twritel(0, priv-\u003eioaddr + mii_address);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=536=static u32 stmmac_clk_csr_set(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-554-\t\trates = stmmac_sun8i_csr_to_mdc;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:555:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-556-\t\trates = stmmac_xgmac_csr_to_mdc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=595=int stmmac_mdio_register(struct net_device ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-621-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:622:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-623-\t\tnew_bus-\u003eread = \u0026stmmac_xgmac2_mdio_read_c22;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-639-\t\tnew_bus-\u003ewrite = \u0026stmmac_mdio_write_c22;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:640:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-641-\t\t\tnew_bus-\u003eread_c45 = \u0026stmmac_mdio_read_c45;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-665-\t/* Looks like we need a dummy read for XGMAC only and C45 PHYs /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:666:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-667-\t\tstmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c=23=static void common_default_data(struct plat_stmmacenet_data plat)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-26-\tplat-\u003eclk_csr = STMMAC_CSR_20_35M;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c:27:\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-28-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c=54=static int snps_gmac5_default_data(struct pci_dev pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-59-\tplat-\u003eclk_csr = STMMAC_CSR_250_300M;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c:60:\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-61-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c=415=stmmac_probe_config_dt(struct platform_device pdev, u8 mac)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-519-\t\t\t\t\u0026pdev-\u003edev, plat-\u003emulticast_filter_bins);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:520:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-521-\t\tplat-\u003epmt = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-524-\tif (of_device_is_compatible(np, \"snps,dwmac-3.40a\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:525:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-526-\t\tplat-\u003eenh_desc = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-532-\tif (of_device_compatible_match(np, stmmac_gmac4_compats)) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:533:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-534-\t\tplat-\u003epmt = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-546-\tif (of_device_is_compatible(np, \"snps,dwxgmac\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:547:\t\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-548-\t\tplat-\u003epmt = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c=49=static int stmmac_adjust_time(struct ptp_clock_info ptp, s64 delta)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c-59-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c:60:\txmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c-61-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c=335=void stmmac_ptp_register(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c-348-\tpriv-\u003eplat-\u003ecdc_error_adj = 0;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c:349:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c-350-\t\tpriv-\u003eplat-\u003ecdc_error_adj = (2 NSEC_PER_SEC) / priv-\u003eplat-\u003eclk_ptp_rate;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c=799=static int stmmac_test_flowctrl(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c-818-\t /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c:819:\tif (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_MAC100 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c-820-\t rx_fifo_size / priv-\u003eplat-\u003erx_queues_to_use \u003c 4096)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c=1678=static int __stmmac_test_jumbo(struct stmmac_priv *priv, u16 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c-1682-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c:1683:\tif (!dwmac_is_xmac(priv-\u003eplat-\u003ecore_type))\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c-1684-\t\tsize -= NET_IP_ALIGN;\n" }
29/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 50155 output: 26 thoughts: 1814 Thoughts: Analyzing the Reachability of `DWMAC_CORE_XGMAC` and Patch Applicability Okay, first things first, let's trace where `DWMAC_CORE_XGMAC` is actually used. It's set in a few specific places: `dwmac-socfpga.c`, `dwmac-tegra.c`, and in `stmmac_platform.c` if the OpenFirmware device tree has the "snps,dwxgmac" compatible string. Hmm, so this limits its scope considerably, but is it completely limited? My next thought is, is `dwxgmac` being used or reachable anywhere else? Let me check the associated structures - `dwxgmac210_ops`, `dwxgmac210_dma_ops`, and `dwxgmac210_desc_ops`. Aha! They're all referencing `DWMAC_CORE_XGMAC` which we previously identified. This makes perfect sense; the driver is using a common interface that depends on that core type. Now, who's actually using the `dwxgmac` core? Well, the Agilex5, the Tegra Orin, and any device described by a DT node compatible with "snps,dwxgmac." Okay, that's still pretty specific. Can QEMU emulate a dwxgmac device? That's the critical question for our fuzzing strategy. I'm pretty sure it doesn't. Let's confirm: e1000, e1000e, rtl8139, virtio-net, igb, vmxnet3, ne2k_pci, pcnet... Nope, not seeing dwxgmac or even a generic "dwmac". Even for ARM, it's various other drivers, but no dwxgmac. And remember, our target architecture is AMD64! I need to be sure; is it possible to instantiate a dwxgmac on AMD64, perhaps through configfs or sysfs or an OF overlay? Let's check the triage philosophy, section 2. We should only return `WorthFuzzing=false` if the code change falls into certain negative criteria. The relevant one here is "structurally unreachable hardware". This specifically calls out vendor-specific PCIe switches and drivers not emulated in standard QEMU. Is dwxgmac effectively in that category? STMMAC / dwxgmac physical hardware not emulated in QEMU? Yes, that's what I am leaning towards, but let's see. Let's look at the patch itself to confirm. I need to understand what this patch actually does. Okay, the patch updates `dwxgmac2_descs.c` and `dwxgmac2_dma.c`. Specifically, it alters how the header length is determined in received descriptors, and modifies the DMA configuration to enable some SPH functionality, including setting save/segment and disabling variable preambles. Let's search git for this commit or read the commit message for the context. This will show us if the patch itself makes anything more reachable. Let's examine the commit message more thoroughly to understand the patch's purpose and impact on the device's behavior in general. This should provide some insight.
30/2	2026/09/25 05:39	tool	grepper	0m Args: { "Expression": "dwxgmac2_get_rx_header_len" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=265=static int dwxgmac2_get_rx_hash(struct dma_desc p, u32 hash,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-292-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:293:static void dwxgmac2_get_rx_header_len(struct dma_desc p, unsigned int len)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-294-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=358=const struct stmmac_desc_ops dwxgmac210_desc_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-379-\t.get_rx_hash = dwxgmac2_get_rx_hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:380:\t.get_rx_header_len = dwxgmac2_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-381-\t.set_sec_addr = dwxgmac2_set_sec_addr,\n" }
31/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 53105 output: 41 thoughts: 107 Thoughts: Okay, let's break this down. Investigating the dwxgmac2 Driver's SPH Functionality Right, so I need to understand how the SPH (Source Port Header) functionality is being enabled and used within this `dwxgmac2` driver. I see that `dwxgmac2_get_rx_header_len` lives within `dwxgmac210_desc_ops.get_rx_header_len`, that's straightforward enough. Now, `dwxgmac2_enable_sph` is located in `dwxgmac210_dma_ops`, which is interesting. It indicates SPH enabling is likely linked to the DMA (Direct Memory Access) operations, which makes sense. My next step is to pinpoint the exact call path for `dwxgmac2_enable_sph`. I need to trace where this function is actually invoked to see what triggers the SPH feature. More specifically, I should check how `enable_sph` is set within `dwxgmac2_dma.c`. This is where the configuration logic that enables or disables the SPH feature would be located.
32/2	2026/09/25 05:39	tool	grepper	0m Args: { "Expression": "dwxgmac2_enable_sph", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=545=static void dwxgmac2_set_bfsize(struct stmmac_priv priv, void __iomem ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-554-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:555:static void dwxgmac2_enable_sph(struct stmmac_priv priv, void __iomem ioaddr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-556-\t\t\t\tbool en, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=605=const struct stmmac_dma_ops dwxgmac210_dma_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-630-\t.set_bfsize = dwxgmac2_set_bfsize,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:631:\t.enable_sph = dwxgmac2_enable_sph,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-632-\t.enable_tbs = dwxgmac2_enable_tbs,\n" }
33/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 53888 output: 44 thoughts: 73 Thoughts: Okay, let's break this down. Analyzing Recent Code Changes in the stmmac Driver Alright, so the modifications center around two specific functions: `dwxgmac210_dma_ops.enable_sph` and `dwxgmac210_desc_ops.get_rx_header_len`. My initial question is always, "Where are these functions actually being used within the stmmac driver?" Understanding the call graph is crucial here. I need to trace back from these modified functions to their points of invocation. This is the starting point for understanding the impact of these changes. Are they core to the data path? Are they only used in a corner case? The answer to those questions influences how urgent I consider a review, and also whether I need to carefully consider testing specific scenarios related to their uses.
34/2	2026/09/25 05:39	tool	grepper	0m Args: { "Expression": "enable_sph\|get_rx_header_len", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c=508=static void dwmac4_set_vlan(struct dma_desc p, u32 type)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c-512-\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c:513:static void dwmac4_get_rx_header_len(struct dma_desc p, unsigned int len)\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c-514-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c=537=const struct stmmac_desc_ops dwmac4_desc_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c-561-\t.set_vlan = dwmac4_set_vlan,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c:562:\t.get_rx_header_len = dwmac4_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c-563-\t.set_sec_addr = dwmac4_set_sec_addr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c=515=static void dwmac4_set_bfsize(struct stmmac_priv priv, void __iomem ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-525-\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c:526:static void dwmac4_enable_sph(struct stmmac_priv priv, void __iomem ioaddr,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-527-\t\t\t bool en, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c=571=const struct stmmac_dma_ops dwmac4_dma_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-597-\t.set_bfsize = dwmac4_set_bfsize,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c:598:\t.enable_sph = dwmac4_enable_sph,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-599-};\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c=601=const struct stmmac_dma_ops dwmac410_dma_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-627-\t.set_bfsize = dwmac4_set_bfsize,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c:628:\t.enable_sph = dwmac4_enable_sph,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-629-\t.enable_tbs = dwmac4_enable_tbs,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=265=static int dwxgmac2_get_rx_hash(struct dma_desc p, u32 hash,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-292-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:293:static void dwxgmac2_get_rx_header_len(struct dma_desc p, unsigned int len)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-294-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=358=const struct stmmac_desc_ops dwxgmac210_desc_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-379-\t.get_rx_hash = dwxgmac2_get_rx_hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:380:\t.get_rx_header_len = dwxgmac2_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-381-\t.set_sec_addr = dwxgmac2_set_sec_addr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=545=static void dwxgmac2_set_bfsize(struct stmmac_priv priv, void __iomem ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-554-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:555:static void dwxgmac2_enable_sph(struct stmmac_priv priv, void __iomem ioaddr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-556-\t\t\t\tbool en, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=605=const struct stmmac_dma_ops dwxgmac210_dma_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-630-\t.set_bfsize = dwxgmac2_set_bfsize,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:631:\t.enable_sph = dwxgmac2_enable_sph,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-632-\t.enable_tbs = dwxgmac2_enable_tbs,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h=39=struct stmmac_desc_ops {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-94-\t\t\t enum pkt_hash_types type);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:95:\tvoid (get_rx_header_len)(struct dma_desc p, unsigned int len);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-96-\tvoid (set_sec_addr)(struct dma_desc p, dma_addr_t addr, bool buf2_valid);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-149-\tstmmac_do_callback(__priv, desc, get_rx_hash, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:150:#define stmmac_get_rx_header_len(__priv, __args...) \\\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:151:\tstmmac_do_void_callback(__priv, desc, get_rx_header_len, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-152-#define stmmac_set_desc_sec_addr(__priv, __args...) \\\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h=167=struct stmmac_dma_ops {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-229-\t\t\t int bfsize, u32 chan);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:230:\tvoid (enable_sph)(struct stmmac_priv priv, void __iomem ioaddr,\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-231-\t\t\t bool en, u32 chan);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-291-\tstmmac_do_void_callback(__priv, dma, set_bfsize, __priv, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:292:#define stmmac_enable_sph(__priv, __args...) \\\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:293:\tstmmac_do_void_callback(__priv, dma, enable_sph, __priv, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-294-#define stmmac_enable_tbs(__priv, __args...) \\\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=3670=static int stmmac_hw_setup(struct net_device dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-3763-\tfor (chan = 0; chan \u003c rx_cnt; chan++)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:3764:\t\tstmmac_enable_sph(priv, priv-\u003eioaddr, sph_en, chan);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-3765-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=5178=static unsigned int stmmac_rx_buf1_len(struct stmmac_priv priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-5189-\t/* First descriptor, get split header length /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:5190:\tstmmac_get_rx_header_len(priv, p, \u0026hlen);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-5191-\tif (priv-\u003esph_active \u0026\u0026 hlen) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6255=static int stmmac_set_features(struct net_device netdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6274-\t\tfor (chan = 0; chan \u003c priv-\u003eplat-\u003erx_queues_to_use; chan++)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6275:\t\t\tstmmac_enable_sph(priv, priv-\u003eioaddr, sph_en, chan);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6276-\t}\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7184=int stmmac_xdp_open(struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7232-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7233:\t\tstmmac_enable_sph(priv, priv-\u003eioaddr, sph_en, chan);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7234-\t}\n" }
35/2	2026/09/25 05:39	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 57227 output: 49 thoughts: 875 Thoughts: Reachability Analysis for `dwxgmac2` in an AMD64 Environment Okay, let's break this down. My goal is to determine if `dwxgmac2` is reachable in a standard QEMU / GCE amd64 environment. First, I need to remind myself of the triage instructions. Specifically, what constitutes "structurally unreachable hardware" and "unreachable execution paths". The instructions highlight things like vendor-specific PCIe switches, specialized NICs, and driver teardown paths tied to physical hot-unplug, none of which seems directly relevant to probing the driver. The initial question then is: can the `stmmac` driver for `dwxgmac2` even be probed in this setup? Can any device bind to `dwxgmac2` on amd64? I need to trace the setup path. My first step is to check all callers of `dwxgmac2_setup`. Looking at `hwif.c`, I see that `dwxgmac2_setup` is used within a table, `stmmac_hwif_entry`. This table associates `dwxgmac2_setup` with devices having `.core_type = DWMAC_CORE_XGMAC` and specific device IDs. I need to understand what sets this `core_type`. A quick grep for `DWMAC_CORE_XGMAC` identifies a few interesting spots: `dwmac-socfpga.c` (Intel FPGA SoC), `dwmac-tegra.c` (NVIDIA Tegra), and `stmmac_platform.c`. The latter, specifically `stmmac_probe_config_dt`, is intriguing, as it uses Device Tree entries: `of_device_is_compatible(np, "snps,dwxgmac")`. So, it appears the path is through Device Tree compatibility. Here's the problem. AMD64/x86 typically uses ACPI/PCI, not Device Tree, so I need to know if the Device Tree can be used on AMD64. Even if an OF overlay could be loaded, the main question is, does any QEMU virtual machine emulate a Synopsys DesignWare 10G Ethernet MAC (`dwxgmac`)? This is critical! If QEMU doesn't emulate it, it's a dead end, even if I could load a Device Tree. Time to search the kernel or QEMU documentation. Does QEMU even have a `snps,dwxgmac` or anything like a `dwxgmac` emulation? Based on my previous knowledge, the answer is no. QEMU does not emulate a Synopsys dwxgmac at all! And, even if QEMU had a dwmac, that's not `dwxgmac`, and this is AMD64, so that's irrelevant. So, I need to look at the PCI setup. I'm going to investigate `stmmac_pci.c`, to see what PCI devices it actually supports to verify this assumption.
36/2	2026/09/25 05:40	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c", "FirstLine": 1, "LineCount": 100 } Results: { "Contents": " 1:\t// SPDX-License-Identifier: GPL-2.0-only\n 2:\t/*****************************************************************************\n 3:\t This contains the functions to handle the pci driver.\n 4:\t\n 5:\t Copyright (C) 2011-2012 Vayavya Labs Pvt Ltd\n 6:\t\n 7:\t\n 8:\t Author: Rayagond Kokatanur \u003crayagond@vayavyalabs.com\u003e\n 9:\t Author: Giuseppe Cavallaro \u003cpeppe.cavallaro@st.com\u003e\n 10:\t****************************************************************************/\n 11:\t\n 12:\t#include \u003clinux/clk-provider.h\u003e\n 13:\t#include \u003clinux/pci.h\u003e\n 14:\t#include \u003clinux/dmi.h\u003e\n 15:\t\n 16:\t#include \"stmmac.h\"\n 17:\t#include \"stmmac_libpci.h\"\n 18:\t\n 19:\tstruct stmmac_pci_info {\n 20:\t\tint (setup)(struct pci_dev pdev, struct plat_stmmacenet_data plat);\n 21:\t};\n 22:\t\n 23:\tstatic void common_default_data(struct plat_stmmacenet_data plat)\n 24:\t{\n 25:\t\t/ clk_csr_i = 20-35MHz \u0026 MDC = clk_csr_i/16 /\n 26:\t\tplat-\u003eclk_csr = STMMAC_CSR_20_35M;\n 27:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\n 28:\t\tplat-\u003eforce_sf_dma_mode = true;\n 29:\t\n 30:\t\tplat-\u003emdio_bus_data-\u003eneeds_reset = true;\n 31:\t}\n 32:\t\n 33:\tstatic int stmmac_default_data(struct pci_dev pdev,\n 34:\t\t\t\t struct plat_stmmacenet_data plat)\n 35:\t{\n 36:\t\t/ Set common default data first /\n 37:\t\tcommon_default_data(plat);\n 38:\t\n 39:\t\tplat-\u003ebus_id = 1;\n 40:\t\tplat-\u003ephy_addr = 0;\n 41:\t\tplat-\u003ephy_interface = PHY_INTERFACE_MODE_GMII;\n 42:\t\n 43:\t\tplat-\u003edma_cfg-\u003epbl = 32;\n 44:\t\tplat-\u003edma_cfg-\u003epblx8 = true;\n 45:\t\t/ TODO: AXI /\n 46:\t\n 47:\t\treturn 0;\n 48:\t}\n 49:\t\n 50:\tstatic const struct stmmac_pci_info stmmac_pci_info = {\n 51:\t\t.setup = stmmac_default_data,\n 52:\t};\n 53:\t\n 54:\tstatic int snps_gmac5_default_data(struct pci_dev pdev,\n 55:\t\t\t\t\t struct plat_stmmacenet_data plat)\n 56:\t{\n 57:\t\tint i;\n 58:\t\n 59:\t\tplat-\u003eclk_csr = STMMAC_CSR_250_300M;\n 60:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\n 61:\t\tplat-\u003eforce_sf_dma_mode = true;\n 62:\t\tplat-\u003eflags \|= STMMAC_FLAG_TSO_EN;\n 63:\t\tplat-\u003epmt = true;\n 64:\t\n 65:\t\t/ Set default number of RX and TX queues to use /\n 66:\t\tplat-\u003etx_queues_to_use = 4;\n 67:\t\tplat-\u003erx_queues_to_use = 4;\n 68:\t\n 69:\t\tplat-\u003etx_sched_algorithm = MTL_TX_ALGORITHM_WRR;\n 70:\t\tfor (i = 0; i \u003c plat-\u003etx_queues_to_use; i++) {\n 71:\t\t\tplat-\u003etx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;\n 72:\t\t\tplat-\u003etx_queues_cfg[i].weight = 25;\n 73:\t\t\tif (i \u003e 0)\n 74:\t\t\t\tplat-\u003etx_queues_cfg[i].tbs_en = 1;\n 75:\t\t}\n 76:\t\n 77:\t\tplat-\u003erx_sched_algorithm = MTL_RX_ALGORITHM_SP;\n 78:\t\tfor (i = 0; i \u003c plat-\u003erx_queues_to_use; i++)\n 79:\t\t\tplat-\u003erx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;\n 80:\t\n 81:\t\tplat-\u003ebus_id = 1;\n 82:\t\tplat-\u003ephy_interface = PHY_INTERFACE_MODE_GMII;\n 83:\t\n 84:\t\tplat-\u003edma_cfg-\u003epbl = 32;\n 85:\t\tplat-\u003edma_cfg-\u003epblx8 = true;\n 86:\t\n 87:\t\t/ Axi Configuration /\n 88:\t\tplat-\u003eaxi = devm_kzalloc(\u0026pdev-\u003edev, sizeof(plat-\u003eaxi), GFP_KERNEL);\n 89:\t\tif (!plat-\u003eaxi)\n 90:\t\t\treturn -ENOMEM;\n 91:\t\n 92:\t\tplat-\u003eaxi-\u003eaxi_wr_osr_lmt = 31;\n 93:\t\tplat-\u003eaxi-\u003eaxi_rd_osr_lmt = 31;\n 94:\t\n 95:\t\tplat-\u003eaxi-\u003eaxi_fb = false;\n 96:\t\tplat-\u003eaxi-\u003eaxi_blen_regval = DMA_AXI_BLEN4 \| DMA_AXI_BLEN8 \|\n 97:\t\t\t\t\t DMA_AXI_BLEN16 \| DMA_AXI_BLEN32;\n 98:\t\n 99:\t\treturn 0;\n 100:\t}\n" }
37/2	2026/09/25 05:40	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 60389 output: 51 thoughts: 17 Thoughts: Okay, here's my take on those thoughts, tailored for an expert audience, and delivered as a first-person summary: Diving Back into stmmac_pci.c Alright, time to get back to `stmmac_pci.c`. We've covered the basics, but there's always more lurking in these drivers, isn't there? I need to meticulously go through the rest of this file. Let's see what else they've implemented, any subtle nuances in the PCI-specific initialization, resource allocation strategies, and of course, the interrupt handling. I'm especially keen to look for any potential areas of concern for our specific hardware revisions, maybe specific workaround applied for hardware errata. Gotta make sure we haven't missed anything in the context of our recent performance issues...or, heaven forbid, security vulnerabilities. It's a deep dive, but necessary. Let's get to it.
38/2	2026/09/25 05:40	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c", "FirstLine": 101, "LineCount": 100 } Results: { "Contents": " 101:\t\n 102:\tstatic const struct stmmac_pci_info snps_gmac5_pci_info = {\n 103:\t\t.setup = snps_gmac5_default_data,\n 104:\t};\n 105:\t\n 106:\t/*\n 107:\t stmmac_pci_probe\n 108:\t \n 109:\t @pdev: pci device pointer\n 110:\t * @id: pointer to table of device id/id's.\n 111:\t \n 112:\t Description: This probing function gets called for all PCI devices which\n 113:\t * match the ID table and are not \"owned\" by other driver yet. This function\n 114:\t * gets passed a \"struct pci_dev \" for each device whose entry in the ID table\n 115:\t matches the device. The probe functions returns zero when the driver choose\n 116:\t * to take \"ownership\" of the device or an error code(-ve no) otherwise.\n 117:\t /\n 118:\tstatic int stmmac_pci_probe(struct pci_dev pdev,\n 119:\t\t\t\t const struct pci_device_id id)\n 120:\t{\n 121:\t\tstruct stmmac_pci_info info = (struct stmmac_pci_info )id-\u003edriver_data;\n 122:\t\tstruct plat_stmmacenet_data plat;\n 123:\t\tstruct stmmac_resources res = {};\n 124:\t\tint ret;\n 125:\t\tint i;\n 126:\t\n 127:\t\tplat = stmmac_plat_dat_alloc(\u0026pdev-\u003edev);\n 128:\t\tif (!plat)\n 129:\t\t\treturn -ENOMEM;\n 130:\t\n 131:\t\tplat-\u003emdio_bus_data = devm_kzalloc(\u0026pdev-\u003edev,\n 132:\t\t\t\t\t\t sizeof(plat-\u003emdio_bus_data),\n 133:\t\t\t\t\t\t GFP_KERNEL);\n 134:\t\tif (!plat-\u003emdio_bus_data)\n 135:\t\t\treturn -ENOMEM;\n 136:\t\n 137:\t\tplat-\u003esafety_feat_cfg = devm_kzalloc(\u0026pdev-\u003edev,\n 138:\t\t\t\t\t\t sizeof(plat-\u003esafety_feat_cfg),\n 139:\t\t\t\t\t\t GFP_KERNEL);\n 140:\t\tif (!plat-\u003esafety_feat_cfg)\n 141:\t\t\treturn -ENOMEM;\n 142:\t\n 143:\t\t/* Enable pci device /\n 144:\t\tret = pcim_enable_device(pdev);\n 145:\t\tif (ret) {\n 146:\t\t\tdev_err(\u0026pdev-\u003edev, \"%s: ERROR: failed to enable device\\n\",\n 147:\t\t\t\t__func__);\n 148:\t\t\treturn ret;\n 149:\t\t}\n 150:\t\n 151:\t\t/ Get the base address of device /\n 152:\t\tfor (i = 0; i \u003c PCI_STD_NUM_BARS; i++) {\n 153:\t\t\tif (pci_resource_len(pdev, i) == 0)\n 154:\t\t\t\tcontinue;\n 155:\t\t\tres.addr = pcim_iomap_region(pdev, i, STMMAC_RESOURCE_NAME);\n 156:\t\t\tif (IS_ERR(res.addr))\n 157:\t\t\t\treturn PTR_ERR(res.addr);\n 158:\t\t\tbreak;\n 159:\t\t}\n 160:\t\n 161:\t\tpci_set_master(pdev);\n 162:\t\n 163:\t\tret = info-\u003esetup(pdev, plat);\n 164:\t\tif (ret)\n 165:\t\t\treturn ret;\n 166:\t\n 167:\t\tres.wol_irq = pdev-\u003eirq;\n 168:\t\tres.irq = pdev-\u003eirq;\n 169:\t\n 170:\t\tplat-\u003esafety_feat_cfg-\u003etsoee = 1;\n 171:\t\tplat-\u003esafety_feat_cfg-\u003emrxpee = 1;\n 172:\t\tplat-\u003esafety_feat_cfg-\u003emestee = 1;\n 173:\t\tplat-\u003esafety_feat_cfg-\u003emrxee = 1;\n 174:\t\tplat-\u003esafety_feat_cfg-\u003emtxee = 1;\n 175:\t\tplat-\u003esafety_feat_cfg-\u003eepsi = 1;\n 176:\t\tplat-\u003esafety_feat_cfg-\u003eedpp = 1;\n 177:\t\tplat-\u003esafety_feat_cfg-\u003eprtyen = 1;\n 178:\t\tplat-\u003esafety_feat_cfg-\u003etmouten = 1;\n 179:\t\n 180:\t\tplat-\u003esuspend = stmmac_pci_plat_suspend;\n 181:\t\tplat-\u003eresume = stmmac_pci_plat_resume;\n 182:\t\n 183:\t\treturn stmmac_dvr_probe(\u0026pdev-\u003edev, plat, \u0026res);\n 184:\t}\n 185:\t\n 186:\t/\n 187:\t stmmac_pci_remove\n 188:\t \n 189:\t @pdev: platform device pointer\n 190:\t * Description: this function calls the main to free the net resources.\n 191:\t /\n 192:\tstatic void stmmac_pci_remove(struct pci_dev pdev)\n 193:\t{\n 194:\t\tstmmac_dvr_remove(\u0026pdev-\u003edev);\n 195:\t}\n 196:\t\n 197:\t/* synthetic ID, no official vendor */\n 198:\t#define PCI_VENDOR_ID_STMMAC\t\t0x0700\n 199:\t\n 200:\t#define PCI_DEVICE_ID_STMMAC_STMMAC\t\t0x1108\n" }
39/2	2026/09/25 05:40	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 62252 output: 50 thoughts: 17 Thoughts: Okay, here's my take on those thoughts, tailored for an expert audience, and delivered as a first-person summary: Digging into stmmac_pci.c Alright, so I need to get a handle on the rest of this `stmmac_pci.c` file. I've been over the initial sections, but I'm thinking I'm missing some crucial context. I'm already visualizing the PCI device probing and initialization sequences it probably contains. I'm mentally parsing where the interrupt handling might be defined – is it a direct interrupt, MSI, or something else entirely? I bet there's a good chunk dedicated to DMA setup and buffer management, especially considering it's a network device. I'm keen to see how they're handling the power management aspects and resource allocation. Are they using the standard PCI resource management functions, or have they implemented something custom to optimize performance or handle the specific requirements of the STMMAC? I need to look for any interesting tricks they're employing for link status detection or offload features. I'm guessing there's a section on error handling and how they manage device resets if things go sideways. I should also be mindful of any platform-specific dependencies they might be using that relate to the STMMAC core itself. Gotta be sure to understand any of those potential gotchas. Basically, I want to map out the whole lifecycle of this driver's interaction with the PCI bus and the underlying hardware. Knowing that will give me a comprehensive understanding of the driver.
40/2	2026/09/25 05:40	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c", "FirstLine": 201, "LineCount": 40 } Results: { "Contents": " 201:\t#define PCI_DEVICE_ID_SYNOPSYS_GMAC5_ID\t\t0x7102\n 202:\t\n 203:\tstatic const struct pci_device_id stmmac_id_table[] = {\n 204:\t\t{ PCI_DEVICE_DATA(STMMAC, STMMAC, \u0026stmmac_pci_info) },\n 205:\t\t{ PCI_DEVICE_DATA(STMICRO, MAC, \u0026stmmac_pci_info) },\n 206:\t\t{ PCI_DEVICE_DATA(SYNOPSYS, GMAC5_ID, \u0026snps_gmac5_pci_info) },\n 207:\t\t{}\n 208:\t};\n 209:\t\n 210:\tMODULE_DEVICE_TABLE(pci, stmmac_id_table);\n 211:\t\n 212:\tstatic struct pci_driver stmmac_pci_driver = {\n 213:\t\t.name = STMMAC_RESOURCE_NAME,\n 214:\t\t.id_table = stmmac_id_table,\n 215:\t\t.probe = stmmac_pci_probe,\n 216:\t\t.remove = stmmac_pci_remove,\n 217:\t\t.driver = {\n 218:\t\t\t.pm = \u0026stmmac_simple_pm_ops,\n 219:\t\t},\n 220:\t};\n 221:\t\n 222:\tmodule_pci_driver(stmmac_pci_driver);\n 223:\t\n 224:\tMODULE_DESCRIPTION(\"STMMAC 10/100/1000 Ethernet PCI driver\");\n 225:\tMODULE_AUTHOR(\"Rayagond Kokatanur \u003crayagond.kokatanur@vayavyalabs.com\u003e\");\n 226:\tMODULE_AUTHOR(\"Giuseppe Cavallaro \u003cpeppe.cavallaro@st.com\u003e\");\n 227:\tMODULE_LICENSE(\"GPL\");\n" }
41/2	2026/09/25 05:40	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 63169 output: 43 thoughts: 112 Thoughts: Investigating the Core Type Assignment for DWMAC Drivers Okay, so I'm digging into how the `core_type` is being assigned for these DWMAC drivers, specifically regarding XGMAC support. I noticed that when looking at the `snps_gmac5_pci_info` structure, it explicitly sets `plat->core_type` to `DWMAC_CORE_GMAC4`. Similarly, `stmmac_pci_info` assigns `DWMAC_CORE_GMAC`. Neither of these is setting `DWMAC_CORE_XGMAC`, which is what I'm interested in. That's a red flag. My next move is to check the `dwmac-intel.c` file. I need to know if Intel's DWMAC driver has any XGMAC implementations, and if so, how it handles the `core_type` assignment. Let's get into that file and see what's going on there. I'm hoping to find the missing piece of this puzzle and how they are handled.
42/2	2026/09/25 05:40	tool	grepper	0m Args: { "Expression": "core_type", "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=596=static void common_default_data(struct plat_stmmacenet_data plat)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-599-\tplat-\u003eclk_csr = STMMAC_CSR_20_35M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:600:\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-601-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=616=static int intel_mgbe_common_data(struct pci_dev pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-626-\tplat-\u003eclk_csr = STMMAC_CSR_250_300M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:627:\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-628-\tplat-\u003eforce_sf_dma_mode = 0;\n" }
43/2	2026/09/25 05:40	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 63926 output: 24 thoughts: 373 Thoughts: Investigating the DWMAC Core Types and XGMAC Usage Okay, so I'm looking at these DWMAC core types, specifically in relation to how they're being used. I see that `dwmac-intel.c` is only using `DWMAC_CORE_GMAC` and `DWMAC_CORE_GMAC4`. Alright, that's fine. What about the others? `dwmac-loongson.c` only uses `DWMAC_CORE_GMAC`. Okay. `dwmac-motorcomm.c` uses `DWMAC_CORE_GMAC4`. Fine, that seems normal. But then it hits me: what about `DWMAC_CORE_XGMAC`? Is any PCI driver actually setting that? I can't recall any offhand. Let's double-check the grep results for `DWMAC_CORE_XGMAC`. Ah, here we go. The places where `core_type = DWMAC_CORE_XGMAC` are: 1. `dwmac-socfpga.c`: Specifically, `socfpga_agilex5_setup_plat_dat`. Agilex5 is, of course, an Intel Altera SoC FPGA, which is ARM64. Got it. 2. `dwmac-tegra.c`: Specifically, `tegra_mgbe_probe`. And the Tegra Orin MGBE is ARM64 too. 3. `stmmac_platform.c`: This one is interesting: `of_device_is_compatible(np, "snps,dwxgmac")`. That's using Device Tree for platform devices. More ARM/ARM64-type systems, which is what I suspected. Wait a second. What about those specific sets of ops, `dwxgmac210_ops`, `dwxgmac210_dma_ops`, and `dwxgmac210_desc_ops`? Are they referenced anywhere else? Let's check where `dwxgmac210_dma_ops`, `dwxgmac210_desc_ops`, and `dwxgmac2_setup` are being used. It's time to dig deeper!
44/2	2026/09/25 05:40	tool	grepper	0m Args: { "Expression": "dwxgmac210_desc_ops" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h=474=extern const struct stmmac_dma_ops dwxgmac210_dma_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:475:extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-476-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=350=static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-357-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:358:const struct stmmac_desc_ops dwxgmac210_desc_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-359-\t.tx_status = dwxgmac2_get_tx_status,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-256-\t\t},\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:257:\t\t.desc = \u0026dwxgmac210_desc_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-258-\t\t.dma = \u0026dwxgmac210_dma_ops,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-278-\t\t},\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:279:\t\t.desc = \u0026dwxgmac210_desc_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-280-\t\t.dma = \u0026dwxgmac210_dma_ops,\n" }
45/2	2026/09/25 05:40	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 65403 output: 25 thoughts: 45 Thoughts: Here's my take on those thoughts: Concerning STMMAC and DMA Operations Okay, so I'm digging into this `stmmac` situation, and something's pinging my radar. This `stmmac_hwif_entry`... it seems to only be relevant, or at least only used, when dealing with `DWMAC_CORE_XGMAC`. That's a key observation. It raises a question in my mind: what about the operations tied to the `dwxgmac210_dma_ops`? Are those implicitly handled, or are there specific conditions I'm missing that dictate when those operations are relevant? I need to understand the relationship between these two, especially in a wider context. This detail is important, and I need to solidify the architecture around this point.
46/2	2026/09/25 05:40	tool	grepper	0m Args: { "Expression": "dwxgmac210_dma_ops" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h=473=extern const struct stmmac_ops dwxlgmac2_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:474:extern const struct stmmac_dma_ops dwxgmac210_dma_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-475-extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=582=static int dwxgmac2_enable_tbs(struct stmmac_priv priv, void __iomem ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-604-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:605:const struct stmmac_dma_ops dwxgmac210_dma_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-606-\t.reset = dwxgmac2_dma_reset,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-257-\t\t.desc = \u0026dwxgmac210_desc_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:258:\t\t.dma = \u0026dwxgmac210_dma_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-259-\t\t.mac = \u0026dwxgmac210_ops,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-279-\t\t.desc = \u0026dwxgmac210_desc_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:280:\t\t.dma = \u0026dwxgmac210_dma_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-281-\t\t.mac = \u0026dwxlgmac2_ops,\n" }
47/2	2026/09/25 05:40	llm	patch-evaluator-compressor	0m Model: gemini-3.8-flash Args: null Results: null Reply: ### 1. Approaches Tried and Results * Diff inspection: * Patch f0b5e1ec09b7 ("syz-cluster: applied patch under review") modifies: * `drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h`: Adds register and bit definitions (`XGMAC_EXT_CFG0`, `XGMAC_EXT_CFG0_VPRE`, `XGMAC_EXT_CFG1`, `XGMAC_CONFIG1_SAVE_EN`, `XGMAC_CONFIG1_SPLM(v)`, `XGMAC_RDES2_NONIPHL`, `XGMAC_RDES3_L2T`). * `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c`: Modifies `dwxgmac2_get_rx_header_len()` to parse L2 split headers and handle `!XGMAC_RDES3_LD` descriptors. * `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c`: Modifies `dwxgmac2_enable_sph()` to program `XGMAC_EXT_CFG1` and `XGMAC_EXT_CFG0` for split header mode. * Driver architecture and HWIF analysis: * Traced `dwxgmac2_setup()` and associated ops (`dwxgmac210_desc_ops`, `dwxgmac210_dma_ops`, `dwxgmac210_ops`) to `drivers/net/ethernet/stmicro/stmmac/hwif.c`. * In `hwif.c`, these ops are registered only for entries matching `core_type == DWMAC_CORE_XGMAC` with `min_id = DWXGMAC_CORE_2_10` / `DWXLGMAC_CORE_2_00` and matching `snpsver` / `dev_id`. * Hardware instantiation and bus probing analysis: * Grepped for `DWMAC_CORE_XGMAC` across the entire codebase. * Found occurrences setting `plat_dat->core_type = DWMAC_CORE_XGMAC` only in: 1. `drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c`: `socfpga_agilex5_setup_plat_dat()` (Intel Agilex5 SoC FPGA, ARM64 Device Tree). 2. `drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c`: `tegra_mgbe_probe()` (NVIDIA Tegra Orin/Thor MGBE, ARM64 Device Tree). 3. `drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c`: `stmmac_probe_config_dt()` if `of_device_is_compatible(np, "snps,dwxgmac")` (OF / Device Tree platform devices). * Checked PCI glue drivers (`stmmac_pci.c`, `dwmac-intel.c`, `dwmac-loongson.c`, `dwmac-motorcomm.c`): * `stmmac_pci.c` sets `DWMAC_CORE_GMAC` or `DWMAC_CORE_GMAC4`. * `dwmac-intel.c` sets `DWMAC_CORE_GMAC` or `DWMAC_CORE_GMAC4`. * `dwmac-motorcomm.c` sets `DWMAC_CORE_GMAC4`. * None set `DWMAC_CORE_XGMAC`. * Grepped `dwxgmac\|XGMAC` in `stmmac_pci.c` and `dwmac-intel.c` — returned no matches. ### 2. Current Hypotheses and Lines of Investigation * Target Architecture: amd64. * Reachability Hypothesis: * The modified code (`dwxgmac2_descs.c`, `dwxgmac2_dma.c`) is exclusively tied to `dwxgmac2` (Synopsys DesignWare 10G/XGMAC IP core). * It requires `core_type == DWMAC_CORE_XGMAC`. * The only drivers using `DWMAC_CORE_XGMAC` are DT/OF-based platform drivers for ARM64 SoCs (Agilex 5, NVIDIA Tegra MGBE) or generic OF device-tree nodes compatible with `snps,dwxgmac`. * No standard QEMU or GCE virtualized environment on amd64 emulates Synopsys XGMAC 10G IP (`snps,dwxgmac` or Tegra MGBE or Agilex 5). * The code is structurally unreachable on amd64 in standard virtualized environments (falls under Section 2: Structurally unreachable hardware / physical ASIC or vendor platform devices not emulated in standard QEMU, as well as code paths exclusive to architectures / DT platforms not present in standard amd64 VMs). * Therefore, `WorthFuzzing` should evaluate to `false`. ### 3. Critical Code and References * Modified Functions: * `dwxgmac2_get_rx_header_len()` in `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c`: ```c static void dwxgmac2_get_rx_header_len(struct dma_desc p, unsigned int len) { u32 rdes3 = le32_to_cpu(p->des3); /* when FD=1 and LD=0, HL is RDES2[9:0] / if (!(rdes3 & XGMAC_RDES3_LD)) { len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; return; } if (rdes3 & XGMAC_RDES3_L34T) len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; else if (rdes3 & XGMAC_RDES3_L2T) len = (le32_to_cpu(p->des2) & XGMAC_RDES2_NONIPHL) >> 2; } ``` * `dwxgmac2_enable_sph()` in `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c`: ```c static void dwxgmac2_enable_sph(struct stmmac_priv priv, void __iomem ioaddr, bool en, u32 chan) { ... value = readl(ioaddr + XGMAC_EXT_CFG1); value \|= XGMAC_CONFIG1_SPLM(1); value \|= XGMAC_CONFIG1_SAVE_EN; writel(value, ioaddr + XGMAC_EXT_CFG1); /* Disable variable preambles to keep the L2 split offset deterministic. / value = readl(ioaddr + XGMAC_EXT_CFG0); value &= ~XGMAC_EXT_CFG0_VPRE; writel(value, ioaddr + XGMAC_EXT_CFG0); ... } ``` HW Registration in `drivers/net/ethernet/stmicro/stmmac/hwif.c`: * Bound via `.core_type = DWMAC_CORE_XGMAC` -> `dwxgmac210_desc_ops`, `dwxgmac210_dma_ops`. * Platform Invocations: * `drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c`: `socfpga_agilex5_setup_plat_dat()` * `drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c`: `tegra_mgbe_probe()` * `drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c`: `of_device_is_compatible(np, "snps,dwxgmac")` ### 4. Next Steps & Warnings * Do NOT repeat searches for `DWMAC_CORE_XGMAC` or `stmmac_pci.c`. The PCI vs OF driver split has been established. * Verify if there is any synthetic/mock device or test module (e.g. netkit, dummy, usbnet) that can route into `dwxgmac2_desc_ops` or `dwxgmac210_dma_ops`. (None exist; stmmac ops are strictly invoked by `stmmac_main.c` on physical/platform mmio controllers). * Prepare to call `set-results` tool with `WorthFuzzing=false` due to unreachable hardware on amd64 QEMU/GCE. Tokens: input: 52565 output: 2136 thoughts: 0
48/2	2026/09/25 05:40	llm	patch-evaluator	1m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 19139 output: 46 thoughts: 0
49/2	2026/09/25 05:41	tool	read-file	0m Args: { "File": "drivers/net/ethernet/stmicro/stmmac/hwif.c", "FirstLine": 250, "LineCount": 40 } Results: { "Contents": " 250:\t\t\t.dev_id = DWXGMAC_ID,\n 251:\t\t\t.regs = {\n 252:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 253:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 254:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 255:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 256:\t\t\t},\n 257:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n 258:\t\t\t.dma = \u0026dwxgmac210_dma_ops,\n 259:\t\t\t.mac = \u0026dwxgmac210_ops,\n 260:\t\t\t.vlan = \u0026dwxgmac210_vlan_ops,\n 261:\t\t\t.hwtimestamp = \u0026stmmac_ptp,\n 262:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 263:\t\t\t.mode = NULL,\n 264:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 265:\t\t\t.mmc = \u0026dwxgmac_mmc_ops,\n 266:\t\t\t.est = \u0026dwmac510_est_ops,\n 267:\t\t\t.setup = dwxgmac2_setup,\n 268:\t\t\t.quirks = NULL,\n 269:\t\t}, {\n 270:\t\t\t.core_type = DWMAC_CORE_XGMAC,\n 271:\t\t\t.min_id = DWXLGMAC_CORE_2_00,\n 272:\t\t\t.dev_id = DWXLGMAC_ID,\n 273:\t\t\t.regs = {\n 274:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 275:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 276:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 277:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 278:\t\t\t},\n 279:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n 280:\t\t\t.dma = \u0026dwxgmac210_dma_ops,\n 281:\t\t\t.mac = \u0026dwxlgmac2_ops,\n 282:\t\t\t.vlan = \u0026dwxlgmac2_vlan_ops,\n 283:\t\t\t.hwtimestamp = \u0026stmmac_ptp,\n 284:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 285:\t\t\t.mode = NULL,\n 286:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 287:\t\t\t.mmc = \u0026dwxgmac_mmc_ops,\n 288:\t\t\t.est = \u0026dwmac510_est_ops,\n 289:\t\t\t.setup = dwxlgmac2_setup,\n" }
50/2	2026/09/25 05:41	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 19963 output: 23 thoughts: 0
51/2	2026/09/25 05:41	tool	grepper	0m Args: { "Expression": "DWMAC_CORE_XGMAC" } Results: { "Output": "drivers/net/ethernet/stmicro/stmmac/common.h=49=static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)\ndrivers/net/ethernet/stmicro/stmmac/common.h-50-{\ndrivers/net/ethernet/stmicro/stmmac/common.h:51:\treturn core_type == DWMAC_CORE_GMAC4 \|\| core_type == DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/common.h-52-}\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=569=static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-572-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:573:\tplat_dat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-574-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c=214=static int tegra_mgbe_probe(struct platform_device pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-325-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c:326:\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-327-\tplat-\u003eflags \|= STMMAC_FLAG_TSO_EN;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=21=static void stmmac_get_version(struct stmmac_priv priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-49-\tver-\u003esnpsver = FIELD_GET(DWMAC_SNPSVER, version);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:50:\tif (core_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-51-\t\tver-\u003edev_id = FIELD_GET(DWMAC_USERVER, version);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-247-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:248:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-249-\t\t.min_id = DWXGMAC_CORE_2_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-269-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:270:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-271-\t\t.min_id = DWXLGMAC_CORE_2_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=294=stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-306-\t\t\tcontinue;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:307:\t\tif (core_type == DWMAC_CORE_XGMAC \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-308-\t\t dev_id != entry-\u003edev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=28=static int est_configure(struct stmmac_priv priv, struct stmmac_est cfg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-55-\tctrl = readl(est_addr + EST_CONTROL);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:56:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-57-\t\tctrl \u0026= ~EST_XGMAC_PTOV;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=83=static void est_irq_status(struct stmmac_priv priv, struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-150-\tif (status \u0026 EST_BTRE) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:151:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-152-\t\t\tbtrl = FIELD_GET(EST_XGMAC_BTRL, status);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=301=static void stmmac_ethtool_getdrvinfo(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-308-\t\tstrscpy(info-\u003edriver, GMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:309:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-310-\t\tstrscpy(info-\u003edriver, XGMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=350=static int stmmac_ethtool_get_regs_len(struct net_device dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-353-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:354:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-355-\t\treturn XGMAC_REGSIZE 4;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=361=static void stmmac_ethtool_gregs(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-375-\t\t NUM_DWMAC4_DMA_REGS 4);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:376:\t} else if (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-377-\t\tmemcpy(\u0026reg_space[ETHTOOL_DMA_OFFSET],\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=642=static int stmmac_hwtstamp_set(struct net_device dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-759-\t\t\tif (priv-\u003esynopsys_id \u003c DWMAC_CORE_3_70 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:760:\t\t\t priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-761-\t\t\t\tts_event_en = PTP_TCR_TSEVNTENA;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6608=static int stmmac_dma_cap_show(struct seq_file seq, void v)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6643-\t\t (priv-\u003edma_cap.half_duplex) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6644:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6645-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6679-\t\t (priv-\u003edma_cap.atime_stamp) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6680:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6681-\t\tseq_printf(seq, \"\\tTimestamp System Time Source: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6688-\tif (priv-\u003esynopsys_id \u003e= DWMAC_CORE_4_00 \|\|\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6689:\t priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6690-\t\tseq_printf(seq, \"\\tIP Checksum Offload in RX: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7421=static void stmmac_print_actphyif(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7436-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7437:\tcase DWMAC_CORE_XGMAC:\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7438-\t\tphyif_table = stmmac_dwxgmac_phyif;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7463=static int stmmac_hw_init(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7612-\tif ((priv-\u003esynopsys_id \u003e= DWMAC_CORE_3_50 \|\|\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7613:\t priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7614-\t !priv-\u003eplat-\u003eriwt_off) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7878=static int __stmmac_dvr_probe(struct device device,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8085-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:8086:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8087-\t\tndev-\u003emax_mtu = XGMAC_JUMBO_LEN;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=536=static u32 stmmac_clk_csr_set(struct stmmac_priv priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-554-\t\trates = stmmac_sun8i_csr_to_mdc;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:555:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-556-\t\trates = stmmac_xgmac_csr_to_mdc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=595=int stmmac_mdio_register(struct net_device ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-621-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:622:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-623-\t\tnew_bus-\u003eread = \u0026stmmac_xgmac2_mdio_read_c22;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-665-\t/* Looks like we need a dummy read for XGMAC only and C45 PHYs /\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:666:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-667-\t\tstmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c=415=stmmac_probe_config_dt(struct platform_device pdev, u8 *mac)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-546-\tif (of_device_is_compatible(np, \"snps,dwxgmac\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:547:\t\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-548-\t\tplat-\u003epmt = true;\n--\ninclude/linux/stmmac.h=191=enum dwmac_core_type {\n--\ninclude/linux/stmmac.h-194-\tDWMAC_CORE_GMAC4,\ninclude/linux/stmmac.h:195:\tDWMAC_CORE_XGMAC,\ninclude/linux/stmmac.h-196-};\n" }
52/2	2026/09/25 05:41	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 24041 output: 202 thoughts: 1230 Thoughts: Analysis of the Code's Reachability Okay, let's break this down systematically. My initial assessment indicates the patch touches files related to the Synopsys DesignWare 10G/XGMAC IP core. Specifically, I'm looking at definitions in `dwxgmac2.h` and functions in `dwxgmac2_descs.c` and `dwxgmac2_dma.c`. The functions, `dwxgmac2_get_rx_header_len()` and `dwxgmac2_enable_sph()`, are implemented as part of the `dwxgmac210_desc_ops` and `dwxgmac210_dma_ops` structures respectively. These structures are referenced only in `hwif.c`. The `stmmac_hwif_entry` table and its matching criteria, using `core_type == DWMAC_CORE_XGMAC`, are key here. I need to understand where `plat->core_type` gets set to `DWMAC_CORE_XGMAC`. I've found three potential locations: `dwmac-socfpga.c` (Intel Agilex5 SoC FPGA), `dwmac-tegra.c` (NVIDIA Tegra Orin/Thor MGBE), and `stmmac_platform.c` (via Device Tree, if compatible with "snps,dwxgmac"). Now, the crucial question: can any of these be triggered on an amd64 system in a standard QEMU / syzkaller environment? The answer is looking like a firm no. Even if DT could theoretically be booted on x86, QEMU does not emulate the "snps,dwxgmac" device or Tegra MGBE or Agilex5. I can't think of a way to synthesize a platform device in userspace. The driver relies on OF / DT table `stmmac_dt_ids`. QEMU has nothing that emulates `snps,dwxgmac`. It only emulates standard NICs like e1000, virtio-net, etc. So, standard QEMU x86_64, which is the target environment, doesn't emulate the Synopsys DesignWare 10G/XGMAC (or GMAC) IP core. This implies that the code requires actual hardware - an Intel Agilex 5, an NVIDIA Tegra Orin SoC, or a real Synopsys XGMAC core. Let's apply the negative criteria. The prompt says to return `WorthFuzzing=false` if the modified code falls strictly into "structurally unreachable hardware". This clearly matches the situation: vendor-specific hardware requiring physical ASIC/PCIe cards that are not emulated in standard QEMU. Given all of this, the code modifications are fundamentally unreachable in my target testing environment. I'm ready to mark this as un-fuzzable and proceed to the next analysis.
53/2	2026/09/25 05:41	tool	set-results	0m Error: FocusSymbols must be empty if WorthFuzzing is false Args: { "EnableConfigs": [ "STMMAC_ETH", "DWMAC_DWC_QOS_ETH" ], "FocusSymbols": [ "dwxgmac2_get_rx_header_len", "dwxgmac2_enable_sph" ], "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.", "WorthFuzzing": false } Results: { "error": "FocusSymbols must be empty if WorthFuzzing is false" }
54/2	2026/09/25 05:41	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 26140 output: 156 thoughts: 36 Thoughts: Okay, here's my take on those thoughts, tailored for an expert audience: Addressing a Potential Configuration Inconsistency Alright, let's nail this down. If `WorthFuzzing` is set to `false`, then logically, the `FocusSymbols` collection must be empty. There's no point in specifying focus symbols if fuzzing isn't even enabled, it just adds unnecessary complexity and potential for misinterpretation. Similarly, the `EnableConfigs` list, that should also be empty (or even better, explicitly `null`) in the same scenario. If fuzzing is off, these settings are not needed. I'm seeing a potential for a subtle but important configuration inconsistency here. Time to refactor and ensure that these properties are appropriately managed, and prevent users from inadvertently setting options that have no effect.
55/2	2026/09/25 05:41	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.", "WorthFuzzing": false }
56/1	2026/09/25 05:41	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

{
  "PatchDiff": "commit f0b5e1ec09b73c16ba34999b4655ca2ca2376168\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Fri Sep 25 05:38:45 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\nindex f8ab347f7b5b9..3ccd29ea7ab0e 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n@@ -167,6 +167,11 @@\n #define XGMAC_HW_FEATURE4\t\t0x0000012c\n #define XGMAC_HWFEAT_EASP\t\tBIT(4)\n #define XGMAC_HWFEAT_PCSEL\t\tGENMASK(1, 0)\n+#define XGMAC_EXT_CFG0\t\t\t0x140\n+#define XGMAC_EXT_CFG0_VPRE\t\tBIT(8)\n+#define XGMAC_EXT_CFG1\t\t\t0x00000144\n+#define XGMAC_CONFIG1_SAVE_EN\t\tBIT(24)\n+#define XGMAC_CONFIG1_SPLM(v)\t\tFIELD_PREP(GENMASK(9, 8), v)\n #define XGMAC_MAC_DPP_FSM_INT_STATUS\t0x00000150\n #define XGMAC_MAC_FSM_CONTROL\t\t0x00000158\n #define XGMAC_PRTYEN\t\t\tBIT(1)\n@@ -434,6 +439,7 @@\n #define XGMAC_RDES2_L4FM\t\tBIT(28)\n #define XGMAC_RDES2_L3FM\t\tBIT(27)\n #define XGMAC_RDES2_HL\t\t\tGENMASK(9, 0)\n+#define XGMAC_RDES2_NONIPHL\t\tGENMASK(9, 2)\n #define XGMAC_RDES3_OWN\t\t\tBIT(31)\n #define XGMAC_RDES3_CTXT\t\tBIT(30)\n #define XGMAC_RDES3_IOC\t\t\tBIT(30)\n@@ -441,6 +447,7 @@\n #define XGMAC_RDES3_CDA\t\t\tBIT(27)\n #define XGMAC_RDES3_RSV\t\t\tBIT(26)\n #define XGMAC_RDES3_L34T\t\tGENMASK(23, 20)\n+#define XGMAC_RDES3_L2T\t\t\tGENMASK(19, 16)\n #define XGMAC_RDES3_ET_LT\t\tGENMASK(19, 16)\n #define XGMAC_L34T_IP4TCP\t\t0x1\n #define XGMAC_L34T_IP4UDP\t\t0x2\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c\nindex 6719ac6e395bc..65ac5403ec583 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c\n@@ -292,8 +292,18 @@ static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,\n \n static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)\n {\n-\tif (le32_to_cpu(p-\u003edes3) \u0026 XGMAC_RDES3_L34T)\n+\tu32 rdes3 = le32_to_cpu(p-\u003edes3);\n+\n+\t/* when FD=1 and LD=0, HL is RDES2[9:0] */\n+\tif (!(rdes3 \u0026 XGMAC_RDES3_LD)) {\n+\t\t*len = le32_to_cpu(p-\u003edes2) \u0026 XGMAC_RDES2_HL;\n+\t\treturn;\n+\t}\n+\n+\tif (rdes3 \u0026 XGMAC_RDES3_L34T)\n \t\t*len = le32_to_cpu(p-\u003edes2) \u0026 XGMAC_RDES2_HL;\n+\telse if (rdes3 \u0026 XGMAC_RDES3_L2T)\n+\t\t*len = (le32_to_cpu(p-\u003edes2) \u0026 XGMAC_RDES2_NONIPHL) \u003e\u003e 2;\n }\n \n static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\nindex ff83858ebc1f3..0a9c787305a4e 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\n@@ -561,6 +561,16 @@ static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,\n \tvalue |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */\n \twritel(value, ioaddr + XGMAC_RX_CONFIG);\n \n+\tvalue = readl(ioaddr + XGMAC_EXT_CFG1);\n+\tvalue |= XGMAC_CONFIG1_SPLM(1);\n+\tvalue |= XGMAC_CONFIG1_SAVE_EN;\n+\twritel(value, ioaddr + XGMAC_EXT_CFG1);\n+\n+\t/* Disable variable preambles to keep the L2 split offset deterministic. */\n+\tvalue = readl(ioaddr + XGMAC_EXT_CFG0);\n+\tvalue \u0026= ~XGMAC_EXT_CFG0_VPRE;\n+\twritel(value, ioaddr + XGMAC_EXT_CFG0);\n+\n \tvalue = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));\n \tif (en)\n \t\tvalue |= XGMAC_SPH;\n"
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit f0b5e1ec09b73c16ba34999b4655ca2ca2376168
Author: syz-cluster <triage@syzkaller.com>
Date:   Fri Sep 25 05:38:45 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index f8ab347f7b5b9..3ccd29ea7ab0e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -167,6 +167,11 @@
 #define XGMAC_HW_FEATURE4		0x0000012c
 #define XGMAC_HWFEAT_EASP		BIT(4)
 #define XGMAC_HWFEAT_PCSEL		GENMASK(1, 0)
+#define XGMAC_EXT_CFG0			0x140
+#define XGMAC_EXT_CFG0_VPRE		BIT(8)
+#define XGMAC_EXT_CFG1			0x00000144
+#define XGMAC_CONFIG1_SAVE_EN		BIT(24)
+#define XGMAC_CONFIG1_SPLM(v)		FIELD_PREP(GENMASK(9, 8), v)
 #define XGMAC_MAC_DPP_FSM_INT_STATUS	0x00000150
 #define XGMAC_MAC_FSM_CONTROL		0x00000158
 #define XGMAC_PRTYEN			BIT(1)
@@ -434,6 +439,7 @@
 #define XGMAC_RDES2_L4FM		BIT(28)
 #define XGMAC_RDES2_L3FM		BIT(27)
 #define XGMAC_RDES2_HL			GENMASK(9, 0)
+#define XGMAC_RDES2_NONIPHL		GENMASK(9, 2)
 #define XGMAC_RDES3_OWN			BIT(31)
 #define XGMAC_RDES3_CTXT		BIT(30)
 #define XGMAC_RDES3_IOC			BIT(30)
@@ -441,6 +447,7 @@
 #define XGMAC_RDES3_CDA			BIT(27)
 #define XGMAC_RDES3_RSV			BIT(26)
 #define XGMAC_RDES3_L34T		GENMASK(23, 20)
+#define XGMAC_RDES3_L2T			GENMASK(19, 16)
 #define XGMAC_RDES3_ET_LT		GENMASK(19, 16)
 #define XGMAC_L34T_IP4TCP		0x1
 #define XGMAC_L34T_IP4UDP		0x2
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
index 6719ac6e395bc..65ac5403ec583 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
@@ -292,8 +292,18 @@ static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,
 
 static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)
 {
-	if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T)
+	u32 rdes3 = le32_to_cpu(p->des3);
+
+	/* when FD=1 and LD=0, HL is RDES2[9:0] */
+	if (!(rdes3 & XGMAC_RDES3_LD)) {
+		*len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
+		return;
+	}
+
+	if (rdes3 & XGMAC_RDES3_L34T)
 		*len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
+	else if (rdes3 & XGMAC_RDES3_L2T)
+		*len = (le32_to_cpu(p->des2) & XGMAC_RDES2_NONIPHL) >> 2;
 }
 
 static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index ff83858ebc1f3..0a9c787305a4e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -561,6 +561,16 @@ static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,
 	value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
 	writel(value, ioaddr + XGMAC_RX_CONFIG);
 
+	value = readl(ioaddr + XGMAC_EXT_CFG1);
+	value |= XGMAC_CONFIG1_SPLM(1);
+	value |= XGMAC_CONFIG1_SAVE_EN;
+	writel(value, ioaddr + XGMAC_EXT_CFG1);
+
+	/* Disable variable preambles to keep the L2 split offset deterministic. */
+	value = readl(ioaddr + XGMAC_EXT_CFG0);
+	value &= ~XGMAC_EXT_CFG0_VPRE;
+	writel(value, ioaddr + XGMAC_EXT_CFG0);
+
 	value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
 	if (en)
 		value |= XGMAC_SPH;

							input: 4312
							output: 37
							thoughts: 239

**Analyzing a Kernel Patch Series for the dwxgmac2 Driver**

Okay, so I need to dig into this patch series for the kernel repo. My initial focus is always on understanding the scope of the changes. Let's see... the patch touches these files: `drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h`, `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c`, and `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c`. Right, that confirms it's the `dwxgmac2` part of the `stmmac` driver – the Synopsys DesignWare Enterprise Ethernet controller, specifically the 10G/XGMAC variant.

Now, my next thought is about practical implications for testing. Can I easily get this running in a typical virtualized environment? I need to quickly assess if `stmmac` or specifically `dwxgmac2` is accessible within common setups like GCE or with QEMU and emulated network devices such as USB gadgets, or tun/tap interfaces.

But hold on, before I dive into the testing, it's smarter to consider the hardware this affects. Let me quickly determine which platforms or buses are actually *using* this specific `dwxgmac2` implementation within `stmmac`. I should use `grepper` or scan the codebase directly to determine the hardware this patch will impact. That will guide my subsequent test setup.

{
  "Expression": "dwxgmac2",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac"
}

{
  "Output": "\nFull output is too long, showing 500 out of 694 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/stmicro/stmmac/Makefile=3=stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o\t\\\n--\ndrivers/net/ethernet/stmicro/stmmac/Makefile-7-\t      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \\\ndrivers/net/ethernet/stmicro/stmmac/Makefile:8:\t      stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \\\ndrivers/net/ethernet/stmicro/stmmac/Makefile-9-\t      stmmac_xdp.o stmmac_est.o stmmac_fpe.o stmmac_vlan.o \\\n--\ndrivers/net/ethernet/stmicro/stmmac/common.h=657=int dwmac4_setup(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h:658:int dwxgmac2_setup(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h-659-int dwxlgmac2_setup(struct stmmac_priv *priv);\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-18-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:19:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-20-#include \"stmmac.h\"\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-471-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:472:extern const struct stmmac_ops dwxgmac210_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-473-extern const struct stmmac_ops dwxlgmac2_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:474:extern const struct stmmac_dma_ops dwxgmac210_dma_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:475:extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-476-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-14-#include \"dwxlgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:15:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-16-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:17:static void dwxgmac2_core_init(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-18-\t\t\t       struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-30-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:31:static void dwxgmac2_irq_modify(struct mac_device_info *hw, u32 disable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-32-\t\t\t\tu32 enable)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-44-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:45:static void dwxgmac2_update_caps(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-46-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-50-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:51:static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-52-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-67-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:68:static int dwxgmac2_rx_ipc(struct mac_device_info *hw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-69-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-82-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:83:static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-84-\t\t\t\t     u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-96-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:97:static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-98-\t\t\t\t   u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-137-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:138:static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-139-\t\t\t\t   u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-154-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:155:static void dwxgmac2_rx_queue_routing(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-156-\t\t\t\t      u8 packet, u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-160-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:161:\tstatic const struct stmmac_rx_routing dwxgmac2_route_possibilities[] = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-162-\t\t{ XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT },\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-171-\t/* routing configuration */\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:172:\tvalue \u0026= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:173:\tvalue |= (queue \u003c\u003c dwxgmac2_route_possibilities[packet - 1].reg_shift) \u0026\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:174:\t\t dwxgmac2_route_possibilities[packet - 1].reg_mask;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-175-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-184-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:185:static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-186-\t\t\t\t\t    u32 rx_alg)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-206-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:207:static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-208-\t\t\t\t\t    u32 tx_alg)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-244-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:245:static void dwxgmac2_set_mtl_tx_queue_weight(struct stmmac_priv *priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-246-\t\t\t\t\t     struct mac_device_info *hw,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-253-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:254:static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-255-\t\t\t\t    u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-270-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:271:static void dwxgmac2_config_cbs(struct stmmac_priv *priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-272-\t\t\t\tstruct mac_device_info *hw,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-289-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:290:static void dwxgmac2_dump_regs(struct mac_device_info *hw, u32 *reg_space)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-291-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-298-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:299:static int dwxgmac2_host_irq_status(struct stmmac_priv *priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-300-\t\t\t\t    struct stmmac_extra_stats *x)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-335-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:336:static int dwxgmac2_host_mtl_irq_status(struct stmmac_priv *priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-337-\t\t\t\t\tstruct mac_device_info *hw, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-355-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:356:static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-357-\t\t\t       unsigned int fc, unsigned int pause_time,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-376-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:377:static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-378-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-394-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:395:static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-396-\t\t\t\t   const unsigned char *addr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-408-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:409:static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-410-\t\t\t\t   unsigned char *addr, unsigned int reg_n)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-427-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:428:static int dwxgmac2_set_lpi_mode(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-429-\t\t\t\t enum stmmac_lpi_mode mode,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-451-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:452:static void dwxgmac2_set_eee_pls(struct mac_device_info *hw, int link)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-453-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-464-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:465:static void dwxgmac2_set_eee_timer(struct mac_device_info *hw, int ls, int tw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-466-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-473-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:474:static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-475-\t\t\t\tint mcbitslog2)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-496-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:497:static void dwxgmac2_set_filter(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-498-\t\t\t\tstruct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-531-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:532:\tdwxgmac2_set_mchash(ioaddr, mc_filter, mcbitslog2);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-533-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-541-\t\tnetdev_for_each_uc_addr(ha, dev) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:542:\t\t\tdwxgmac2_set_umac_addr(hw, ha-\u003eaddr, reg);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-543-\t\t\treg++;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-554-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:555:static void dwxgmac2_set_mac_loopback(void __iomem *ioaddr, bool enable)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-556-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-566-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:567:static int dwxgmac2_rss_write_reg(void __iomem *ioaddr, bool is_key, int idx,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-568-\t\t\t\t  u32 val)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-581-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:582:static int dwxgmac2_rss_configure(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-583-\t\t\t\t  struct stmmac_rss *cfg, u32 num_rxq)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-597-\tfor (i = 0; i \u003c (ARRAY_SIZE(cfg-\u003ekey) / sizeof(u32)); i++) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:598:\t\tret = dwxgmac2_rss_write_reg(ioaddr, true, i, key[i]);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-599-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-603-\tfor (i = 0; i \u003c ARRAY_SIZE(cfg-\u003etable); i++) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:604:\t\tret = dwxgmac2_rss_write_reg(ioaddr, false, i, cfg-\u003etable[i]);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-605-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-609-\tfor (i = 0; i \u003c num_rxq; i++)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:610:\t\tdwxgmac2_map_mtl_to_dma(hw, i, XGMAC_QDDMACH);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-611-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1055=static int dwxgmac3_rxp_config(void __iomem *ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1142-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1143:static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *ts)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1144-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1156-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1157:static int dwxgmac2_flex_pps_config(void __iomem *ioaddr, int index,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1158-\t\t\t\t    struct stmmac_pps_cfg *cfg, bool enable,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1220-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1221:static void dwxgmac2_sarc_configure(void __iomem *ioaddr, int val)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1222-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1229-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1230:static int dwxgmac2_filter_wait(struct mac_device_info *hw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1231-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1240-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1241:static int dwxgmac2_filter_read(struct mac_device_info *hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1242-\t\t\t\tu8 reg, u32 *data)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1247-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1248:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1249-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1257-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1258:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1259-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1265-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1266:static int dwxgmac2_filter_write(struct mac_device_info *hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1267-\t\t\t\t u8 reg, u32 data)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1272-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1273:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1274-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1284-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1285:\treturn dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1286-}\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1287-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1288:static int dwxgmac2_config_l3_filter(struct mac_device_info *hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1289-\t\t\t\t     bool en, bool ipv6, bool sa, bool inv,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1299-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1300:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1301-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1330-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1331:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1332-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1335-\tif (sa) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1336:\t\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR0, match);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1337-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1339-\t} else {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1340:\t\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR1, match);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1341-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1345-\tif (!en)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1346:\t\treturn dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1347-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1350-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1351:static int dwxgmac2_config_l4_filter(struct mac_device_info *hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1352-\t\t\t\t     bool en, bool udp, bool sa, bool inv,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1362-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1363:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1364-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1386-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1387:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1388-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1390-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1391:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L4_ADDR, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1392-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1402-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1403:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1404-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1407-\tif (!en)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1408:\t\treturn dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1409-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1412-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1413:const struct stmmac_ops dwxgmac210_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1414:\t.core_init = dwxgmac2_core_init,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1415:\t.irq_modify = dwxgmac2_irq_modify,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1416:\t.update_caps = dwxgmac2_update_caps,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1417:\t.set_mac = dwxgmac2_set_mac,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1418:\t.rx_ipc = dwxgmac2_rx_ipc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1419:\t.rx_queue_enable = dwxgmac2_rx_queue_enable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1420:\t.rx_queue_prio = dwxgmac2_rx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1421:\t.tx_queue_prio = dwxgmac2_tx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1422:\t.rx_queue_routing = dwxgmac2_rx_queue_routing,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1423:\t.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1424:\t.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1425:\t.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1426:\t.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1427:\t.config_cbs = dwxgmac2_config_cbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1428:\t.dump_regs = dwxgmac2_dump_regs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1429:\t.host_irq_status = dwxgmac2_host_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1430:\t.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1431:\t.flow_ctrl = dwxgmac2_flow_ctrl,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1432:\t.pmt = dwxgmac2_pmt,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1433:\t.set_umac_addr = dwxgmac2_set_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1434:\t.get_umac_addr = dwxgmac2_get_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1435:\t.set_lpi_mode = dwxgmac2_set_lpi_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1436:\t.set_eee_timer = dwxgmac2_set_eee_timer,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1437:\t.set_eee_pls = dwxgmac2_set_eee_pls,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1438-\t.debug = NULL,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1439:\t.set_filter = dwxgmac2_set_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1440-\t.safety_feat_config = dwxgmac3_safety_feat_config,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1442-\t.safety_feat_dump = dwxgmac3_safety_feat_dump,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1443:\t.set_mac_loopback = dwxgmac2_set_mac_loopback,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1444:\t.rss_configure = dwxgmac2_rss_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1445-\t.rxp_config = dwxgmac3_rxp_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1446:\t.get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1447:\t.flex_pps_config = dwxgmac2_flex_pps_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1448:\t.sarc_configure = dwxgmac2_sarc_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1449:\t.config_l3_filter = dwxgmac2_config_l3_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1450:\t.config_l4_filter = dwxgmac2_config_l4_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1451-\t.fpe_map_preemption_class = dwxgmac3_fpe_map_preemption_class,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1468=const struct stmmac_ops dwxlgmac2_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1469:\t.core_init = dwxgmac2_core_init,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1470:\t.irq_modify = dwxgmac2_irq_modify,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1471:\t.set_mac = dwxgmac2_set_mac,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1472:\t.rx_ipc = dwxgmac2_rx_ipc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1473-\t.rx_queue_enable = dwxlgmac2_rx_queue_enable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1474:\t.rx_queue_prio = dwxgmac2_rx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1475:\t.tx_queue_prio = dwxgmac2_tx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1476:\t.rx_queue_routing = dwxgmac2_rx_queue_routing,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1477:\t.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1478:\t.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1479:\t.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1480:\t.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1481:\t.config_cbs = dwxgmac2_config_cbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1482:\t.dump_regs = dwxgmac2_dump_regs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1483:\t.host_irq_status = dwxgmac2_host_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1484:\t.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1485:\t.flow_ctrl = dwxgmac2_flow_ctrl,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1486:\t.pmt = dwxgmac2_pmt,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1487:\t.set_umac_addr = dwxgmac2_set_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1488:\t.get_umac_addr = dwxgmac2_get_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1489:\t.set_lpi_mode = dwxgmac2_set_lpi_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1490:\t.set_eee_timer = dwxgmac2_set_eee_timer,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1491:\t.set_eee_pls = dwxgmac2_set_eee_pls,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1492-\t.debug = NULL,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1493:\t.set_filter = dwxgmac2_set_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1494-\t.safety_feat_config = dwxgmac3_safety_feat_config,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1496-\t.safety_feat_dump = dwxgmac3_safety_feat_dump,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1497:\t.set_mac_loopback = dwxgmac2_set_mac_loopback,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1498:\t.rss_configure = dwxgmac2_rss_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1499-\t.rxp_config = dwxgmac3_rxp_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1500:\t.get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1501:\t.flex_pps_config = dwxgmac2_flex_pps_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1502:\t.sarc_configure = dwxgmac2_sarc_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1503:\t.config_l3_filter = dwxgmac2_config_l3_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1504:\t.config_l4_filter = dwxgmac2_config_l4_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1505-\t.fpe_map_preemption_class = dwxgmac3_fpe_map_preemption_class,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1507-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1508:int dwxgmac2_setup(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1509-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-9-#include \"common.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:10:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-11-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:12:static int dwxgmac2_get_tx_status(struct stmmac_extra_stats *x,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-13-\t\t\t\t  struct dma_desc *p, void __iomem *ioaddr)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-25-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:26:static int dwxgmac2_get_rx_status(struct stmmac_extra_stats *x,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-27-\t\t\t\t  struct dma_desc *p)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-48-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:49:static void dwxgmac2_set_tx_owner(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-50-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-53-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:54:static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-55-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-63-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:64:static u16 dwxgmac2_wrback_get_rx_vlan_tci(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-65-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-68-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:69:static bool dwxgmac2_wrback_get_rx_vlan_valid(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-70-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-78-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:79:static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-80-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-83-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:84:static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-85-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-88-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:89:static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-90-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-93-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:94:static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-95-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-104-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:105:static int dwxgmac2_rx_check_timestamp(void *desc)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-106-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-124-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:125:static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-126-\t\t\t\t\t    u32 ats)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-132-\tif (likely(rdes3 \u0026 XGMAC_RDES3_CDA))\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:133:\t\tret = dwxgmac2_rx_check_timestamp(next_desc);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-134-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-137-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:138:static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-139-\t\t\t\t  u8 descriptor_mode, int end, int bfsize)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-140-{\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:141:\tdwxgmac2_set_rx_owner(p, disable_rx_ic);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-142-}\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-143-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:144:static void dwxgmac2_init_tx_desc(struct dma_desc *p, u8 descriptor_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-145-\t\t\t\t  int end)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-152-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:153:static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-154-\t\t\t\t     bool csum_flag, u8 descriptor_mode,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-191-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:192:static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-193-\t\t\t\t\t int len1, int len2, bool tx_own,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-229-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:230:static void dwxgmac2_release_tx_desc(struct dma_desc *p, u8 descriptor_mode)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-231-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-237-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:238:static void dwxgmac2_set_tx_ic(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-239-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-242-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:243:static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-244-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-250-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:251:static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-252-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-256-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:257:static void dwxgmac2_clear(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-258-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-264-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:265:static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-266-\t\t\t\tenum pkt_hash_types *type)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-292-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:293:static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-294-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-308-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:309:static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-310-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-314-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:315:static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-316-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-319-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:320:static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-321-\t\t\t\t  u32 inner_type)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-344-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:345:static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-346-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-349-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:350:static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-351-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-357-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:358:const struct stmmac_desc_ops dwxgmac210_desc_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:359:\t.tx_status = dwxgmac2_get_tx_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:360:\t.rx_status = dwxgmac2_get_rx_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:361:\t.set_tx_owner = dwxgmac2_set_tx_owner,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:362:\t.set_rx_owner = dwxgmac2_set_rx_owner,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:363:\t.get_rx_vlan_tci = dwxgmac2_wrback_get_rx_vlan_tci,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:364:\t.get_rx_vlan_valid = dwxgmac2_wrback_get_rx_vlan_valid,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:365:\t.get_rx_frame_len = dwxgmac2_get_rx_frame_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:366:\t.enable_tx_timestamp = dwxgmac2_enable_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:367:\t.get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:368:\t.get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:369:\t.get_timestamp = dwxgmac2_get_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:370:\t.set_tx_ic = dwxgmac2_set_tx_ic,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:371:\t.prepare_tx_desc = dwxgmac2_prepare_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:372:\t.prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:373:\t.release_tx_desc = dwxgmac2_release_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:374:\t.init_rx_desc = dwxgmac2_init_rx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:375:\t.init_tx_desc = dwxgmac2_init_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:376:\t.set_mss = dwxgmac2_set_mss,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:377:\t.set_addr = dwxgmac2_set_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:378:\t.clear = dwxgmac2_clear,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:379:\t.get_rx_hash = dwxgmac2_get_rx_hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:380:\t.get_rx_header_len = dwxgmac2_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:381:\t.set_sec_addr = dwxgmac2_set_sec_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:382:\t.set_sarc = dwxgmac2_set_sarc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:383:\t.set_vlan_tag = dwxgmac2_set_vlan_tag,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:384:\t.set_vlan = dwxgmac2_set_vlan,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:385:\t.set_tbs = dwxgmac2_set_tbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-386-};\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-8-#include \"stmmac.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:9:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-10-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:11:static int dwxgmac2_dma_reset(void __iomem *ioaddr)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-12-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-21-\n\n"
}

							input: 21801
							output: 39
							thoughts: 21

Okay, let's dive into this code.

**Investigating the `dwxgmac2_setup` Function**

Right, my immediate focus is understanding the scope and impact of `dwxgmac2_setup`. I need to figure out where it's being invoked and, crucially, what other components or functions are *relying* on its output or actions. This is classic debugging - understanding dependencies is key to any efficient troubleshooting or modification. I'll start by tracing the calls to this function. Knowing its immediate call sites will tell me the context in which it's operating. From there, I can begin to reason about its role in the larger system. Is it setting up hardware, initializing data structures, or something else entirely? The call graph will give me the starting point for this investigation.

{
  "Expression": "dwxgmac2_setup",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/common.h=657=int dwmac4_setup(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h:658:int dwxgmac2_setup(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h-659-int dwxlgmac2_setup(struct stmmac_priv *priv);\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1468=const struct stmmac_ops dwxlgmac2_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1507-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1508:int dwxgmac2_setup(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1509-{\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-266-\t\t.est = \u0026dwmac510_est_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:267:\t\t.setup = dwxgmac2_setup,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-268-\t\t.quirks = NULL,\n"
}

							input: 22458
							output: 46
							thoughts: 31

Okay, here's my take on those thoughts, tailored for an expert audience:

**Investigating dwxgmac2_setup Usage**

Alright, let's dig into this. I'm thinking the best way to get a handle on what's going on with `dwxgmac2_setup` is to go directly to the source. Specifically, I'm going to jump into `hwif.c`, probably around line 267. That seems like a reasonable starting point, given my experience with this codebase. From there, I'll be looking to see precisely *which* hardware or driver implementations are actually calling that function. I'm expecting this will likely point me towards specific SoCs, MAC controllers, or perhaps even broader architectural patterns within the system. I'm anticipating that I'll quickly be able to ascertain the context within which this function is being called and get a sense of its general importance to the system.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/hwif.c",
  "FirstLine": 240,
  "LineCount": 40
}

{
  "Contents": " 240:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 241:\t\t\t.mode = \u0026dwmac4_ring_mode_ops,\n 242:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 243:\t\t\t.mmc = \u0026dwmac_mmc_ops,\n 244:\t\t\t.est = \u0026dwmac510_est_ops,\n 245:\t\t\t.setup = dwmac4_setup,\n 246:\t\t\t.quirks = NULL,\n 247:\t\t}, {\n 248:\t\t\t.core_type = DWMAC_CORE_XGMAC,\n 249:\t\t\t.min_id = DWXGMAC_CORE_2_10,\n 250:\t\t\t.dev_id = DWXGMAC_ID,\n 251:\t\t\t.regs = {\n 252:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 253:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 254:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 255:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 256:\t\t\t},\n 257:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n 258:\t\t\t.dma = \u0026dwxgmac210_dma_ops,\n 259:\t\t\t.mac = \u0026dwxgmac210_ops,\n 260:\t\t\t.vlan = \u0026dwxgmac210_vlan_ops,\n 261:\t\t\t.hwtimestamp = \u0026stmmac_ptp,\n 262:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 263:\t\t\t.mode = NULL,\n 264:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 265:\t\t\t.mmc = \u0026dwxgmac_mmc_ops,\n 266:\t\t\t.est = \u0026dwmac510_est_ops,\n 267:\t\t\t.setup = dwxgmac2_setup,\n 268:\t\t\t.quirks = NULL,\n 269:\t\t}, {\n 270:\t\t\t.core_type = DWMAC_CORE_XGMAC,\n 271:\t\t\t.min_id = DWXLGMAC_CORE_2_00,\n 272:\t\t\t.dev_id = DWXLGMAC_ID,\n 273:\t\t\t.regs = {\n 274:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 275:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 276:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 277:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 278:\t\t\t},\n 279:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n"
}

							input: 23499
							output: 39
							thoughts: 26

Okay, here's my attempt at summarizing that thought process, keeping in mind the user is an expert:

**Tracing the Origins of the STMMAC Hardware Interface**

Right, let's get down to brass tacks. I need to understand the initialization flow of this `stmmac hwif` thing. The `hwif` part screams "hardware interface," so I'm guessing it's the core structure representing the hardware abstraction. The immediate question is: where does this whole thing kick off? Specifically, I need to know *who* or *what* is responsible for calling `stmmac_hwif_init` or any function with a similar purpose. I need to trace back from that initialization point to understand the lifecycle of the hardware interface. Understanding the call chain will tell me a lot about the dependencies and the overall architecture. Time to dig into the code and start sleuthing!

{
  "Expression": "stmmac_hwif",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/hwif.c=100=int stmmac_reset(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-110-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:111:static const struct stmmac_hwif_entry {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-112-\tenum dwmac_core_type core_type;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-292-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:293:static const struct stmmac_hwif_entry *\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:294:stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-295-{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:296:\tconst struct stmmac_hwif_entry *entry;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-297-\tint i;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-316-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:317:int stmmac_hwif_init(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-318-{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-319-\tenum dwmac_core_type core_type = priv-\u003eplat-\u003ecore_type;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:320:\tconst struct stmmac_hwif_entry *entry;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-321-\tstruct stmmac_version version;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-348-\t/* Use synopsys_id var because some setups can override this */\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:349:\tentry = stmmac_hwif_find(core_type, priv-\u003esynopsys_id, version.dev_id);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-350-\tif (!entry) {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h=694=int stmmac_reset(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:695:int stmmac_hwif_init(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-696-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7463=static int stmmac_hw_init(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7472-\t/* Initialize HW Interface */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7473:\tret = stmmac_hwif_init(priv);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7474-\tif (ret)\n"
}

							input: 24714
							output: 42
							thoughts: 65

Okay, let's break this down.

**Investigating the STMMAC Driver**

Alright, I need to get a clear picture of `stmmac`. My immediate questions are: What devices are actually *using* this driver? Where does the `stmmac` driver bind itself within the system? Is it primarily associated with physical Ethernet interfaces – perhaps MAC/IP configurations on various System-on-Chip (SoC) architectures, or even PCIe cards?

To clarify this, I'll need to dig into the source code. The obvious starting points are the configuration and build files. I'll head over to the kernel source directory and examine `drivers/net/ethernet/stmicro/stmmac/`. I need to review `Kconfig` for the configuration options related to the driver and understand its dependency and then I will examine `Makefile` to see how it's built and the specific hardware dependencies it might have. This should give me the core information I'm after.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig",
  "FirstLine": 1,
  "LineCount": 80
}

{
  "Contents": "   1:\t# SPDX-License-Identifier: GPL-2.0-only\n   2:\tconfig STMMAC_ETH\n   3:\t\ttristate \"STMicroelectronics Multi-Gigabit Ethernet driver\"\n   4:\t\tdepends on HAS_IOMEM \u0026\u0026 HAS_DMA\n   5:\t\tdepends on PTP_1588_CLOCK_OPTIONAL\n   6:\t\tdepends on ETHTOOL_NETLINK\n   7:\t\tselect MII\n   8:\t\tselect PCS_XPCS\n   9:\t\tselect PAGE_POOL\n  10:\t\tselect PHYLINK\n  11:\t\tselect CRC32\n  12:\t\tselect RESET_CONTROLLER\n  13:\t\tselect NET_DEVLINK\n  14:\t\thelp\n  15:\t\t  This is the driver for the Ethernet IPs built around a\n  16:\t\t  Synopsys IP Core.\n  17:\t\n  18:\tif STMMAC_ETH\n  19:\t\n  20:\tconfig STMMAC_SELFTESTS\n  21:\t\tbool \"Support for STMMAC Selftests\"\n  22:\t\tdepends on INET\n  23:\t\tdefault n\n  24:\t\thelp\n  25:\t\t  This adds support for STMMAC Selftests using ethtool. Enable this\n  26:\t\t  feature if you are facing problems with your HW and submit the test\n  27:\t\t  results to the netdev Mailing List.\n  28:\t\n  29:\tconfig STMMAC_PLATFORM\n  30:\t\ttristate \"STMMAC Platform bus support\"\n  31:\t\tselect MFD_SYSCON\n  32:\t\tdefault y\n  33:\t\thelp\n  34:\t\t  This selects the platform specific bus support for the stmmac driver.\n  35:\t\t  This is the driver used on several SoCs:\n  36:\t\t  STi, Allwinner, Amlogic Meson, Altera SOCFPGA.\n  37:\t\n  38:\t\t  If you have a controller with this interface, say Y or M here.\n  39:\t\n  40:\t\t  If unsure, say N.\n  41:\t\n  42:\tif STMMAC_PLATFORM\n  43:\t\n  44:\tconfig DWMAC_DWC_QOS_ETH\n  45:\t\ttristate \"Support for snps,dwc-qos-ethernet.txt DT binding.\"\n  46:\t\tselect CRC32\n  47:\t\tselect MII\n  48:\t\tdepends on OF \u0026\u0026 HAS_DMA\n  49:\t\thelp\n  50:\t\t  Support for chips using the snps,dwc-qos-ethernet.txt DT binding.\n  51:\t\n  52:\tconfig DWMAC_GENERIC\n  53:\t\ttristate \"Generic driver for DWMAC\"\n  54:\t\tdefault STMMAC_PLATFORM\n  55:\t\thelp\n  56:\t\t  Generic DWMAC driver for platforms that don't require any\n  57:\t\t  platform specific code to function or is using platform\n  58:\t\t  data for setup.\n  59:\t\n  60:\tconfig DWMAC_ANARION\n  61:\t\ttristate \"Adaptrum Anarion GMAC support\"\n  62:\t\tdefault ARC\n  63:\t\tdepends on OF \u0026\u0026 (ARC || COMPILE_TEST)\n  64:\t\thelp\n  65:\t\t  Support for Adaptrum Anarion GMAC Ethernet controller.\n  66:\t\n  67:\t\t  This selects the Anarion SoC glue layer support for the stmmac driver.\n  68:\t\n  69:\tconfig DWMAC_EIC7700\n  70:\t\ttristate \"Support for Eswin eic7700 ethernet driver\"\n  71:\t\tdepends on OF \u0026\u0026 HAS_DMA \u0026\u0026 ARCH_ESWIN || COMPILE_TEST\n  72:\t\thelp\n  73:\t\t  This driver supports the Eswin EIC7700 Ethernet controller,\n  74:\t\t  which integrates Synopsys DesignWare QoS features. It enables\n  75:\t\t  high-speed networking with DMA acceleration and is optimized\n  76:\t\t  for embedded systems.\n  77:\t\n  78:\tconfig DWMAC_INGENIC\n  79:\t\ttristate \"Ingenic MAC support\"\n  80:\t\tdefault MACH_INGENIC\n"
}

							input: 26115
							output: 43
							thoughts: 25

Here's my thought process, as if I were considering this myself:

**Investigating STMMAC_ETH Usage Within the Kconfig System**

Okay, so I've identified `STMMAC_ETH`. Now I need to understand its wider implications within the kernel configuration. The logical next step is to delve deeper into the Kconfig files themselves. My immediate thought is to check how `STMMAC_ETH` is used. I'm specifically interested in seeing if it's connected to other important subsystems, and the first thing that jumps to mind is PCI. Are there any dependencies? Are there other configurations that also use it? I want to see the broader picture, and understand the relationships between different parts of the network stack. This will help me understand its scope and the implications of changing its settings. Let's see what the Kconfig files reveal.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig",
  "FirstLine": 81,
  "LineCount": 80
}

{
  "Contents": "  81:\t\tdepends on OF \u0026\u0026 HAS_IOMEM \u0026\u0026 (MACH_INGENIC || COMPILE_TEST)\n  82:\t\tselect MFD_SYSCON\n  83:\t\thelp\n  84:\t\t  Support for ethernet controller on Ingenic SoCs.\n  85:\t\n  86:\t\t  This selects Ingenic SoCs glue layer support for the stmmac\n  87:\t\t  device driver. This driver is used on for the Ingenic SoCs\n  88:\t\t  MAC ethernet controller.\n  89:\t\n  90:\tconfig DWMAC_IPQ806X\n  91:\t\ttristate \"QCA IPQ806x DWMAC support\"\n  92:\t\tdefault ARCH_QCOM\n  93:\t\tdepends on OF \u0026\u0026 (ARCH_QCOM || COMPILE_TEST)\n  94:\t\tselect MFD_SYSCON\n  95:\t\thelp\n  96:\t\t  Support for QCA IPQ806X DWMAC Ethernet.\n  97:\t\n  98:\t\t  This selects the IPQ806x SoC glue layer support for the stmmac\n  99:\t\t  device driver. This driver does not use any of the hardware\n 100:\t\t  acceleration features available on this SoC. Network devices\n 101:\t\t  will behave like standard non-accelerated ethernet interfaces.\n 102:\t\n 103:\t\t  Select the QCOM_SOCINFO config flag to enable specific dwmac\n 104:\t\t  fixup based on the ipq806x SoC revision.\n 105:\t\n 106:\tconfig DWMAC_LPC18XX\n 107:\t\ttristate \"NXP LPC18xx/43xx DWMAC support\"\n 108:\t\tdefault ARCH_LPC18XX\n 109:\t\tdepends on OF \u0026\u0026 (ARCH_LPC18XX || COMPILE_TEST)\n 110:\t\tselect MFD_SYSCON\n 111:\t\thelp\n 112:\t\t  Support for NXP LPC18xx/43xx DWMAC Ethernet.\n 113:\t\n 114:\tconfig DWMAC_MEDIATEK\n 115:\t\ttristate \"MediaTek MT27xx GMAC support\"\n 116:\t\tdepends on OF \u0026\u0026 (ARCH_MEDIATEK || COMPILE_TEST)\n 117:\t\thelp\n 118:\t\t  Support for MediaTek GMAC Ethernet controller.\n 119:\t\n 120:\t\t  This selects the MT2712 SoC support for the stmmac driver.\n 121:\t\n 122:\tconfig DWMAC_MESON\n 123:\t\ttristate \"Amlogic Meson dwmac support\"\n 124:\t\tdefault ARCH_MESON\n 125:\t\tdepends on OF \u0026\u0026 COMMON_CLK \u0026\u0026 (ARCH_MESON || COMPILE_TEST)\n 126:\t\thelp\n 127:\t\t  Support for Ethernet controller on Amlogic Meson SoCs.\n 128:\t\n 129:\t\t  This selects the Amlogic Meson SoC glue layer support for\n 130:\t\t  the stmmac device driver. This driver is used for Meson6,\n 131:\t\t  Meson8, Meson8b and GXBB SoCs.\n 132:\t\n 133:\tconfig DWMAC_NUVOTON\n 134:\t\ttristate \"Nuvoton MA35 dwmac support\"\n 135:\t\tdefault ARCH_MA35\n 136:\t\tdepends on OF \u0026\u0026 (ARCH_MA35 || COMPILE_TEST)\n 137:\t\tselect MFD_SYSCON\n 138:\t\thelp\n 139:\t\t  Support for Ethernet controller on Nuvoton MA35 series SoC.\n 140:\t\n 141:\t\t  This selects the Nuvoton MA35 series SoC glue layer support\n 142:\t\t  for the stmmac device driver. The nuvoton-dwmac driver is\n 143:\t\t  used for MA35 series SoCs.\n 144:\t\n 145:\tconfig DWMAC_QCOM_ETHQOS\n 146:\t\ttristate \"Qualcomm ETHQOS support\"\n 147:\t\tdefault ARCH_QCOM\n 148:\t\tdepends on OF \u0026\u0026 (ARCH_QCOM || COMPILE_TEST)\n 149:\t\thelp\n 150:\t\t  Support for the Qualcomm ETHQOS core.\n 151:\t\n 152:\t\t  This selects the Qualcomm ETHQOS glue layer support for the\n 153:\t\t  stmmac device driver.\n 154:\t\n 155:\tconfig DWMAC_RENESAS_GBETH\n 156:\t\ttristate \"Renesas RZ/V2H(P) GBETH and RZ/T2H, RZ/N2H GMAC support\"\n 157:\t\tdefault ARCH_RENESAS\n 158:\t\tdepends on OF \u0026\u0026 (ARCH_RENESAS || COMPILE_TEST)\n 159:\t\tselect PCS_RZN1_MIIC\n 160:\t\thelp\n"
}

							input: 27664
							output: 45
							thoughts: 9

Okay, here's my attempt at summarizing the thought process, tailored for an expert audience, and written in the first person:

**Diving Deeper into Kconfig**

Alright, time to dig into this Kconfig file further. I've got a handle on the basics, but I need to understand the nuances of this particular configuration. I want to see how these options are related, how dependencies are defined, and what the implications of each selection might be. I'm looking for the structure, the conditional logic, and the overall design philosophy embedded within this specific Kconfig file. Let's see if there are any subtle tricks or unusual approaches here that I can learn from. I'm particularly interested in seeing how they've handled potential conflicts or edge cases. Time to parse this and gain a deeper understanding of its implications. Let's get to it.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig",
  "FirstLine": 161,
  "LineCount": 100
}

{
  "Contents": " 161:\t\t  Support for Gigabit Ethernet Interface (GBETH)/ Ethernet MAC (GMAC)\n 162:\t\t  on Renesas SoCs.\n 163:\t\n 164:\t\t  This selects Renesas SoC glue layer support for the stmmac device\n 165:\t\t  driver. This driver is used for the RZ/V2H(P) family, RZ/T2H and\n 166:\t\t  RZ/N2H SoCs.\n 167:\t\n 168:\tconfig DWMAC_ROCKCHIP\n 169:\t\ttristate \"Rockchip dwmac support\"\n 170:\t\tdefault ARCH_ROCKCHIP\n 171:\t\tdepends on OF \u0026\u0026 (ARCH_ROCKCHIP || COMPILE_TEST)\n 172:\t\tselect MFD_SYSCON\n 173:\t\thelp\n 174:\t\t  Support for Ethernet controller on Rockchip RK3288 SoC.\n 175:\t\n 176:\t\t  This selects the Rockchip RK3288 SoC glue layer support for\n 177:\t\t  the stmmac device driver.\n 178:\t\n 179:\tconfig DWMAC_RZN1\n 180:\t\ttristate \"Renesas RZ/N1 dwmac support\"\n 181:\t\tdefault ARCH_RZN1\n 182:\t\tdepends on OF \u0026\u0026 (ARCH_RZN1 || COMPILE_TEST)\n 183:\t\tselect PCS_RZN1_MIIC\n 184:\t\thelp\n 185:\t\t  Support for Ethernet controller on Renesas RZ/N1 SoC family.\n 186:\t\n 187:\t\t  This selects the Renesas RZ/N1 SoC glue layer support for\n 188:\t\t  the stmmac device driver. This support can make use of a custom MII\n 189:\t\t  converter PCS device.\n 190:\t\n 191:\tconfig DWMAC_S32\n 192:\t\ttristate \"NXP S32G/S32R GMAC support\"\n 193:\t\tdefault ARCH_S32\n 194:\t\tdepends on OF \u0026\u0026 (ARCH_S32 || COMPILE_TEST)\n 195:\t\thelp\n 196:\t\t  Support for ethernet controller on NXP S32CC SOCs.\n 197:\t\n 198:\t\t  This selects NXP SoC glue layer support for the stmmac\n 199:\t\t  device driver. This driver is used for the S32CC series\n 200:\t\t  SOCs GMAC ethernet controller, ie. S32G2xx, S32G3xx and\n 201:\t\t  S32R45.\n 202:\t\n 203:\tconfig DWMAC_SOCFPGA\n 204:\t\ttristate \"SOCFPGA dwmac support\"\n 205:\t\tdefault ARCH_INTEL_SOCFPGA\n 206:\t\tdepends on OF \u0026\u0026 (ARCH_INTEL_SOCFPGA || COMPILE_TEST)\n 207:\t\tselect MFD_SYSCON\n 208:\t\tselect MDIO_REGMAP\n 209:\t\tselect REGMAP_MMIO\n 210:\t\tselect PCS_LYNX\n 211:\t\thelp\n 212:\t\t  Support for ethernet controller on Altera SOCFPGA\n 213:\t\n 214:\t\t  This selects the Altera SOCFPGA SoC glue layer support\n 215:\t\t  for the stmmac device driver. This driver is used for\n 216:\t\t  arria5 and cyclone5 FPGA SoCs.\n 217:\t\n 218:\tconfig DWMAC_SOPHGO\n 219:\t\ttristate \"Sophgo dwmac support\"\n 220:\t\tdepends on OF \u0026\u0026 (ARCH_SOPHGO || COMPILE_TEST)\n 221:\t\tdefault m if ARCH_SOPHGO\n 222:\t\thelp\n 223:\t\t  Support for ethernet controllers on Sophgo RISC-V SoCs\n 224:\t\n 225:\t\t  This selects the Sophgo SoC specific glue layer support\n 226:\t\t  for the stmmac device driver. This driver is used for the\n 227:\t\t  ethernet controllers on various Sophgo SoCs.\n 228:\t\n 229:\tconfig DWMAC_SPACEMIT\n 230:\t\ttristate \"Spacemit dwmac support\"\n 231:\t\tdepends on OF \u0026\u0026 (ARCH_SPACEMIT || COMPILE_TEST)\n 232:\t\tselect MFD_SYSCON\n 233:\t\tdefault m if ARCH_SPACEMIT\n 234:\t\thelp\n 235:\t\t  Support for ethernet controllers on Spacemit RISC-V SoCs\n 236:\t\n 237:\t\t  This selects the Spacemit platform specific glue layer support\n 238:\t\t  for the stmmac device driver. This driver is used for the\n 239:\t\t  Spacemit K3 ethernet controllers.\n 240:\t\n 241:\tconfig DWMAC_STARFIVE\n 242:\t\ttristate \"StarFive dwmac support\"\n 243:\t\tdepends on OF \u0026\u0026 (ARCH_STARFIVE || COMPILE_TEST)\n 244:\t\tselect MFD_SYSCON\n 245:\t\tdefault m if ARCH_STARFIVE\n 246:\t\thelp\n 247:\t\t  Support for ethernet controllers on StarFive RISC-V SoCs\n 248:\t\n 249:\t\t  This selects the StarFive platform specific glue layer support\n 250:\t\t  for the stmmac device driver. This driver is used for the\n 251:\t\t  StarFive JH7100 and JH7110 ethernet controllers.\n 252:\t\n 253:\tconfig DWMAC_STI\n 254:\t\ttristate \"STi GMAC support\"\n 255:\t\tdefault ARCH_STI\n 256:\t\tdepends on OF \u0026\u0026 (ARCH_STI || COMPILE_TEST)\n 257:\t\tselect MFD_SYSCON\n 258:\t\thelp\n 259:\t\t  Support for ethernet controller on STi SOCs.\n 260:\t\n"
}

							input: 29483
							output: 44
							thoughts: 8

Okay, here's the summary, assuming I'm deeply familiar with Kconfig:

**Diving Back into Kconfig**

Alright, time to get back into Kconfig. No time to waste. I need to keep moving through the documentation/code/whatever this refers to. It's a fundamental part of the build system, so understanding it thoroughly is key. Let's see what interesting tidbits and nuances await this time. I expect that I'll either learn something new or find something familiar that I can better explain to someone else. Time to delve back in!

{
  "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig",
  "FirstLine": 261,
  "LineCount": 80
}

{
  "Contents": " 261:\t\t  This selects STi SoC glue layer support for the stmmac\n 262:\t\t  device driver. This driver is used on for the STi series\n 263:\t\t  SOCs GMAC ethernet controller.\n 264:\t\n 265:\tconfig DWMAC_STM32\n 266:\t\ttristate \"STM32 DWMAC support\"\n 267:\t\tdefault ARCH_STM32\n 268:\t\tdepends on OF \u0026\u0026 HAS_IOMEM \u0026\u0026 (ARCH_STM32 || COMPILE_TEST)\n 269:\t\tselect MFD_SYSCON\n 270:\t\thelp\n 271:\t\t  Support for ethernet controller on STM32 SOCs.\n 272:\t\n 273:\t\t  This selects STM32 SoC glue layer support for the stmmac\n 274:\t\t  device driver. This driver is used on for the STM32 series\n 275:\t\t  SOCs GMAC ethernet controller.\n 276:\t\n 277:\tconfig DWMAC_SUNXI\n 278:\t\ttristate \"Allwinner GMAC support\"\n 279:\t\tdefault ARCH_SUNXI\n 280:\t\tdepends on OF \u0026\u0026 (ARCH_SUNXI || COMPILE_TEST)\n 281:\t\thelp\n 282:\t\t  Support for Allwinner A20/A31 GMAC ethernet controllers.\n 283:\t\n 284:\t\t  This selects Allwinner SoC glue layer support for the\n 285:\t\t  stmmac device driver. This driver is used for A20/A31\n 286:\t\t  GMAC ethernet controller.\n 287:\t\n 288:\tconfig DWMAC_SUN8I\n 289:\t\ttristate \"Allwinner sun8i GMAC support\"\n 290:\t\tdefault ARCH_SUNXI\n 291:\t\tdepends on OF \u0026\u0026 (ARCH_SUNXI || COMPILE_TEST)\n 292:\t\tselect MDIO_BUS_MUX\n 293:\t\thelp\n 294:\t\t  Support for Allwinner H3 A83T A64 EMAC ethernet controllers.\n 295:\t\n 296:\t\t  This selects Allwinner SoC glue layer support for the\n 297:\t\t  stmmac device driver. This driver is used for H3/A83T/A64\n 298:\t\t  EMAC ethernet controller.\n 299:\t\n 300:\tconfig DWMAC_SUN55I\n 301:\t\ttristate \"Allwinner sun55i GMAC200 support\"\n 302:\t\tdefault ARCH_SUNXI\n 303:\t\tdepends on OF \u0026\u0026 (ARCH_SUNXI || COMPILE_TEST)\n 304:\t\tselect MDIO_BUS_MUX\n 305:\t\thelp\n 306:\t\t  Support for Allwinner A523/T527 GMAC200 ethernet controllers.\n 307:\t\n 308:\t\t  This selects Allwinner SoC glue layer support for the\n 309:\t\t  stmmac device driver. This driver is used for A523/T527\n 310:\t\t  GMAC200 ethernet controller.\n 311:\t\n 312:\tconfig DWMAC_THEAD\n 313:\t\ttristate \"T-HEAD dwmac support\"\n 314:\t\tdepends on OF \u0026\u0026 (ARCH_THEAD || COMPILE_TEST)\n 315:\t\thelp\n 316:\t\t  Support for ethernet controllers on T-HEAD RISC-V SoCs\n 317:\t\n 318:\t\t  This selects the T-HEAD platform specific glue layer support for\n 319:\t\t  the stmmac device driver. This driver is used for T-HEAD TH1520\n 320:\t\t  ethernet controller.\n 321:\t\n 322:\tconfig DWMAC_ULTRARISC\n 323:\t\ttristate \"UltraRISC DWMAC support\"\n 324:\t\tdefault ARCH_ULTRARISC\n 325:\t\tdepends on OF \u0026\u0026 (ARCH_ULTRARISC || COMPILE_TEST)\n 326:\t\thelp\n 327:\t\t  Support for the Ethernet controller on the UltraRISC DP1000 SoC.\n 328:\t\n 329:\t\t  This selects the UltraRISC platform specific glue layer support\n 330:\t\t  for the stmmac device driver. This driver is used for the DP1000\n 331:\t\t  GMAC Ethernet controller.\n 332:\t\n 333:\tconfig DWMAC_IMX8\n 334:\t\ttristate \"NXP IMX8 DWMAC support\"\n 335:\t\tdefault ARCH_MXC\n 336:\t\tdepends on OF \u0026\u0026 (ARCH_MXC || COMPILE_TEST)\n 337:\t\tselect MFD_SYSCON\n 338:\t\thelp\n 339:\t\t  Support for ethernet controller on NXP i.MX8 SOCs.\n 340:\t\n"
}

							input: 30940
							output: 44
							thoughts: 15

Here's my take on those thoughts:

**Peering into the Kconfig Depths**

Okay, let's dive in. I need to understand the implications of something – presumably, a configuration option or dependency – and the logical starting point is the Kconfig file. Line 340, huh? That's a specific entry point. It suggests I have a pretty good idea of the general area I'm interested in, or at least a hunch about where the relevant configuration might be defined or influenced. Let's see what the code at line 340 tells me, and what it relates to. This will guide my understanding of the relevant Kconfig options and their dependencies.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/Kconfig",
  "FirstLine": 341,
  "LineCount": 80
}

{
  "Contents": " 341:\t\t  This selects NXP SoC glue layer support for the stmmac\n 342:\t\t  device driver. This driver is used for i.MX8 series like\n 343:\t\t  iMX8MP/iMX8DXL GMAC ethernet controller.\n 344:\t\n 345:\tconfig DWMAC_INTEL_PLAT\n 346:\t\ttristate \"Intel dwmac support\"\n 347:\t\tdepends on OF \u0026\u0026 COMMON_CLK\n 348:\t\thelp\n 349:\t\t  Support for ethernet controllers on Intel SoCs\n 350:\t\n 351:\t\t  This selects the Intel platform specific glue layer support for\n 352:\t\t  the stmmac device driver. This driver is used for the Intel Keem Bay\n 353:\t\t  SoC.\n 354:\t\n 355:\tconfig DWMAC_LOONGSON1\n 356:\t\ttristate \"Loongson1 GMAC support\"\n 357:\t\tdefault MACH_LOONGSON32\n 358:\t\tdepends on OF \u0026\u0026 (MACH_LOONGSON32 || COMPILE_TEST)\n 359:\t\thelp\n 360:\t\t  Support for ethernet controller on Loongson1 SoC.\n 361:\t\n 362:\t\t  This selects Loongson1 SoC glue layer support for the stmmac\n 363:\t\t  device driver. This driver is used for Loongson1-based boards\n 364:\t\t  like Loongson LS1B/LS1C.\n 365:\t\n 366:\tconfig DWMAC_TEGRA\n 367:\t\ttristate \"NVIDIA Tegra MGBE support\"\n 368:\t\tdepends on ARCH_TEGRA || COMPILE_TEST\n 369:\t\thelp\n 370:\t\t  This selects the Multi-GigaBit Ethernet (MGBE) Controller that is\n 371:\t\t  found on the NVIDIA Tegra SoC devices. This driver provides the glue\n 372:\t\t  layer on top of the stmmac driver required for these NVIDIA Tegra SoC\n 373:\t\t  devices.\n 374:\t\n 375:\tconfig DWMAC_VISCONTI\n 376:\t\ttristate \"Toshiba Visconti DWMAC support\"\n 377:\t\tdefault ARCH_VISCONTI\n 378:\t\tdepends on OF \u0026\u0026 COMMON_CLK \u0026\u0026 (ARCH_VISCONTI || COMPILE_TEST)\n 379:\t\thelp\n 380:\t\t  Support for ethernet controller on Visconti SoCs.\n 381:\t\n 382:\tendif # STMMAC_PLATFORM\n 383:\t\n 384:\tconfig STMMAC_LIBPCI\n 385:\t\ttristate\n 386:\t\thelp\n 387:\t\t  This option enables the PCI bus helpers for the stmmac driver.\n 388:\t\n 389:\tconfig DWMAC_INTEL\n 390:\t\ttristate \"Intel GMAC support\"\n 391:\t\tdefault X86\n 392:\t\tdepends on X86 \u0026\u0026 PCI\n 393:\t\tdepends on COMMON_CLK\n 394:\t\tdepends on ACPI\n 395:\t\thelp\n 396:\t\t  This selects the Intel platform specific bus support for the\n 397:\t\t  stmmac driver. This driver is used for Intel Quark/EHL/TGL.\n 398:\t\n 399:\tconfig DWMAC_LOONGSON\n 400:\t\ttristate \"Loongson PCI DWMAC support\"\n 401:\t\tdefault MACH_LOONGSON64\n 402:\t\tdepends on (MACH_LOONGSON64 || COMPILE_TEST) \u0026\u0026 PCI\n 403:\t\tdepends on COMMON_CLK\n 404:\t\tselect STMMAC_LIBPCI\n 405:\t\thelp\n 406:\t\t  This selects the LOONGSON PCI bus support for the stmmac driver,\n 407:\t\t  Support for ethernet controller on Loongson-2K1000 SoC and LS7A1000 bridge.\n 408:\t\n 409:\tconfig DWMAC_MOTORCOMM\n 410:\t\ttristate \"Motorcomm PCI DWMAC support\"\n 411:\t\tdepends on PCI\n 412:\t\tselect MOTORCOMM_PHY\n 413:\t\tselect STMMAC_LIBPCI\n 414:\t\thelp\n 415:\t\t  This enables glue driver for Motorcomm DWMAC-based PCI Ethernet\n 416:\t\t  controllers. Currently only YT6801 is supported.\n 417:\t\n 418:\tconfig STMMAC_PCI\n 419:\t\ttristate \"STMMAC PCI bus support\"\n 420:\t\tdepends on PCI\n"
}

							input: 32366
							output: 23
							thoughts: 77

Okay, here's my thought process as I'd articulate it:

**Digging into the DWMAC Driver Landscape**

Right, let's start by surveying the DWMAC drivers, cataloging what's available. I'm seeing `DWMAC_INTEL`, `DWMAC_LOONGSON`, `DWMAC_MOTORCOMM`, and `STMMAC_PCI`. But that's a bit broad. What I *really* want to understand is which of these specifically leverage `dwxgmac2`. I need to isolate the code that's tied to that particular XGMAC implementation.

So, instead of just generally surveying, I'll refine my search. I'm going to look for either `DWMAC_CORE_XGMAC` or the literal string `dwxgmac2` across the entire kernel source tree. That should give me a much more focused view of where this specific XGMAC variant is used and, therefore, the key drivers I should be examining more closely. This will tell me which drivers are actually using the specific XGMAC feature set of interest.

{
  "Expression": "DWMAC_CORE_XGMAC"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/common.h=49=static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)\ndrivers/net/ethernet/stmicro/stmmac/common.h-50-{\ndrivers/net/ethernet/stmicro/stmmac/common.h:51:\treturn core_type == DWMAC_CORE_GMAC4 || core_type == DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/common.h-52-}\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=569=static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-572-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:573:\tplat_dat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-574-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c=214=static int tegra_mgbe_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-325-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c:326:\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-327-\tplat-\u003eflags |= STMMAC_FLAG_TSO_EN;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=21=static void stmmac_get_version(struct stmmac_priv *priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-49-\tver-\u003esnpsver = FIELD_GET(DWMAC_SNPSVER, version);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:50:\tif (core_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-51-\t\tver-\u003edev_id = FIELD_GET(DWMAC_USERVER, version);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-247-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:248:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-249-\t\t.min_id = DWXGMAC_CORE_2_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-269-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:270:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-271-\t\t.min_id = DWXLGMAC_CORE_2_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=294=stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-306-\t\t\tcontinue;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:307:\t\tif (core_type == DWMAC_CORE_XGMAC \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-308-\t\t    dev_id != entry-\u003edev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=28=static int est_configure(struct stmmac_priv *priv, struct stmmac_est *cfg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-55-\tctrl = readl(est_addr + EST_CONTROL);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:56:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-57-\t\tctrl \u0026= ~EST_XGMAC_PTOV;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=83=static void est_irq_status(struct stmmac_priv *priv, struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-150-\tif (status \u0026 EST_BTRE) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:151:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-152-\t\t\tbtrl = FIELD_GET(EST_XGMAC_BTRL, status);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=301=static void stmmac_ethtool_getdrvinfo(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-308-\t\tstrscpy(info-\u003edriver, GMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:309:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-310-\t\tstrscpy(info-\u003edriver, XGMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=350=static int stmmac_ethtool_get_regs_len(struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-353-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:354:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-355-\t\treturn XGMAC_REGSIZE * 4;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=361=static void stmmac_ethtool_gregs(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-375-\t\t       NUM_DWMAC4_DMA_REGS * 4);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:376:\t} else if (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-377-\t\tmemcpy(\u0026reg_space[ETHTOOL_DMA_OFFSET],\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=642=static int stmmac_hwtstamp_set(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-759-\t\t\tif (priv-\u003esynopsys_id \u003c DWMAC_CORE_3_70 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:760:\t\t\t    priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-761-\t\t\t\tts_event_en = PTP_TCR_TSEVNTENA;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6608=static int stmmac_dma_cap_show(struct seq_file *seq, void *v)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6643-\t\t   (priv-\u003edma_cap.half_duplex) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6644:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6645-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6679-\t\t   (priv-\u003edma_cap.atime_stamp) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6680:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6681-\t\tseq_printf(seq, \"\\tTimestamp System Time Source: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6688-\tif (priv-\u003esynopsys_id \u003e= DWMAC_CORE_4_00 ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6689:\t    priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6690-\t\tseq_printf(seq, \"\\tIP Checksum Offload in RX: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7421=static void stmmac_print_actphyif(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7436-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7437:\tcase DWMAC_CORE_XGMAC:\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7438-\t\tphyif_table = stmmac_dwxgmac_phyif;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7463=static int stmmac_hw_init(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7612-\tif ((priv-\u003esynopsys_id \u003e= DWMAC_CORE_3_50 ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7613:\t     priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7614-\t    !priv-\u003eplat-\u003eriwt_off) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7878=static int __stmmac_dvr_probe(struct device *device,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8085-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:8086:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8087-\t\tndev-\u003emax_mtu = XGMAC_JUMBO_LEN;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=536=static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-554-\t\trates = stmmac_sun8i_csr_to_mdc;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:555:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-556-\t\trates = stmmac_xgmac_csr_to_mdc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=595=int stmmac_mdio_register(struct net_device *ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-621-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:622:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-623-\t\tnew_bus-\u003eread = \u0026stmmac_xgmac2_mdio_read_c22;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-665-\t/* Looks like we need a dummy read for XGMAC only and C45 PHYs */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:666:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-667-\t\tstmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c=415=stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-546-\tif (of_device_is_compatible(np, \"snps,dwxgmac\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:547:\t\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-548-\t\tplat-\u003epmt = true;\n--\ninclude/linux/stmmac.h=191=enum dwmac_core_type {\n--\ninclude/linux/stmmac.h-194-\tDWMAC_CORE_GMAC4,\ninclude/linux/stmmac.h:195:\tDWMAC_CORE_XGMAC,\ninclude/linux/stmmac.h-196-};\n"
}

							input: 36758
							output: 49
							thoughts: 219

**Analyzing DWMAC_CORE_XGMAC Implementations**

Okay, let's break this down. My initial thought process is to trace where `DWMAC_CORE_XGMAC` is actually defined and utilized. I've noted three key areas so far: first, in the `socfpga_agilex5_setup_plat_dat` function within `dwmac-socfpga.c`, which clearly pertains to Altera/Intel SoC FPGA Agilex5 systems (ARM64 with Device Tree). Second, `dwmac-tegra.c` and its `tegra_mgbe_probe` function indicates use within NVIDIA Tegra platforms (also ARM64 with Device Tree). Then there's `stmmac_platform.c`, where there's an `if` condition using `of_device_is_compatible` checking for "snps,dwxgmac" in Open Firmware Device Tree platforms; if found, we set the core type.

The next obvious question is whether there are any PCI-based instances of this? My mental checklist now jumps to the PCI-specific files: `stmmac_pci.c`, `dwmac-intel.c`, and potentially `dwmac-loongson.c`, etc. I need to quickly scan those sources to see if XGMAC is also configured through PCI. This is important to determine the complete scope of where this core is deployed. I need to make sure I understand all the possible instantiations of this core.

{
  "Expression": "dwxgmac|XGMAC",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c"
}

{
  "error": "no matches"
}

							input: 37363
							output: 47
							thoughts: 12

Okay, let's dive in. Here's my understanding of what we're looking at, framed as my own mental process:

**Diving into the `dwmac-intel.c` Source Code**

Alright, I'm thinking, time to crack open `dwmac-intel.c`. That's where I need to start, I'm sure of it. This file is going to be key to understanding the Intel-specific aspects of this DWMAC driver implementation. I expect to see the hardware initialization, the register definitions, interrupt handling specific to Intel chipsets... all the low-level details that deviate from the more generic DWMAC framework. I need to get a handle on how they've customized the core MAC driver for Intel's network controllers. I anticipate potential hardware quirks, special registers, and platform-specific clock configuration code lurking within. It's time to become familiar with Intel's interpretation of the standard DWMAC interface. Let's see what interesting tidbits we can dig up.

{
  "Expression": "dwxgmac|XGMAC",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c"
}

{
  "error": "no matches"
}

							input: 37652
							output: 37
							thoughts: 23

Okay, here's my summary, tailored for an expert audience, presented as if it were my thought process:

**Diving into the `stmmac_pci.c` Code**

Alright, before I get too deep into this, I need to understand how this particular STMMAC device is being initialized, particularly on the PCI bus. Let's see... the `stmmac_pci.c` file should hold the key, right? I want to pinpoint where the driver sets the `core_type`. That will give me a critical piece of the puzzle to proceed. Let's start there.

{
  "Expression": "core_type",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/common.h-48-\ndrivers/net/ethernet/stmicro/stmmac/common.h:49:static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)\ndrivers/net/ethernet/stmicro/stmmac/common.h-50-{\ndrivers/net/ethernet/stmicro/stmmac/common.h:51:\treturn core_type == DWMAC_CORE_GMAC4 || core_type == DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/common.h-52-}\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c=36=static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c-87-\t/* dwc-qos needs GMAC4, AAL, TSO and PMT */\ndrivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c:88:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c-89-\tplat_dat-\u003edma_cfg-\u003eaal = 1;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=596=static void common_default_data(struct plat_stmmacenet_data *plat)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-599-\tplat-\u003eclk_csr = STMMAC_CSR_20_35M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:600:\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-601-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=616=static int intel_mgbe_common_data(struct pci_dev *pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-626-\tplat-\u003eclk_csr = STMMAC_CSR_250_300M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:627:\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-628-\tplat-\u003eforce_sf_dma_mode = 0;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c=374=static int ipq806x_gmac_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c-475-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c:476:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c-477-\tplat_dat-\u003ebsp_priv = gmac;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c=86=static void loongson_default_data(struct pci_dev *pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c-95-\tplat-\u003eclk_csr = STMMAC_CSR_100_150M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c:96:\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c-97-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c=42=static int lpc18xx_dwmac_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c-56-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c:57:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c-58-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c=208=motorcomm_default_plat_data(struct pci_dev *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c-247-\tplat-\u003eclk_ref_rate\t= 125000000;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c:248:\tplat-\u003ecore_type\t\t= DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c-249-\tplat-\u003esuspend\t\t= stmmac_pci_plat_suspend;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c=684=static int qcom_ethqos_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c-776-\tplat_dat-\u003eptp_clk_freq_config = ethqos_ptp_clk_freq_config;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c:777:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c-778-\tif (ethqos-\u003ehas_emac_ge_3)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c=1571=static int rk_gmac_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c-1594-\t */\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c:1595:\tif (plat_dat-\u003ecore_type != DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c:1596:\t\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-rk.c-1597-\t\tplat_dat-\u003erx_fifo_size = 4096;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-s32.c=144=static int s32_dwmac_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-s32.c-195-\t/* S32CC core feature set */\ndrivers/net/ethernet/stmicro/stmmac/dwmac-s32.c:196:\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-s32.c-197-\tplat-\u003epmt = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=559=static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-562-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:563:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-564-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=569=static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-572-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:573:\tplat_dat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-574-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c=99=static int sun7i_gmac_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c-138-\tplat_dat-\u003etx_coe = true;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c:139:\tplat_dat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c-140-\tplat_dat-\u003ebsp_priv = gmac;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c=214=static int tegra_mgbe_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-325-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c:326:\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-327-\tplat-\u003eflags |= STMMAC_FLAG_TSO_EN;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=21=static void stmmac_get_version(struct stmmac_priv *priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-23-{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:24:\tenum dwmac_core_type core_type = priv-\u003eplat-\u003ecore_type;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-25-\tunsigned int version_offset;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-30-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:31:\tif (core_type == DWMAC_CORE_MAC100)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-32-\t\treturn;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-33-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:34:\tif (core_type == DWMAC_CORE_GMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-35-\t\tversion_offset = GMAC_VERSION;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-49-\tver-\u003esnpsver = FIELD_GET(DWMAC_SNPSVER, version);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:50:\tif (core_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-51-\t\tver-\u003edev_id = FIELD_GET(DWMAC_USERVER, version);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:112:\tenum dwmac_core_type core_type;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-113-\tu32 min_id;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-130-\t{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:131:\t\t.core_type = DWMAC_CORE_MAC100,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-132-\t\t.min_id = 0,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-147-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:148:\t\t.core_type = DWMAC_CORE_GMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-149-\t\t.min_id = 0,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-164-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:165:\t\t.core_type = DWMAC_CORE_GMAC4,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-166-\t\t.min_id = 0,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-184-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:185:\t\t.core_type = DWMAC_CORE_GMAC4,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-186-\t\t.min_id = DWMAC_CORE_4_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-205-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:206:\t\t.core_type = DWMAC_CORE_GMAC4,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-207-\t\t.min_id = DWMAC_CORE_4_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-226-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:227:\t\t.core_type = DWMAC_CORE_GMAC4,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-228-\t\t.min_id = DWMAC_CORE_5_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-247-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:248:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-249-\t\t.min_id = DWXGMAC_CORE_2_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-269-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:270:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-271-\t\t.min_id = DWXLGMAC_CORE_2_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=293=static const struct stmmac_hwif_entry *\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:294:stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-295-{\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-301-\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:302:\t\tif (core_type != entry-\u003ecore_type)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-303-\t\t\tcontinue;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-306-\t\t\tcontinue;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:307:\t\tif (core_type == DWMAC_CORE_XGMAC \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-308-\t\t    dev_id != entry-\u003edev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=317=int stmmac_hwif_init(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-318-{\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:319:\tenum dwmac_core_type core_type = priv-\u003eplat-\u003ecore_type;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-320-\tconst struct stmmac_hwif_entry *entry;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-348-\t/* Use synopsys_id var because some setups can override this */\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:349:\tentry = stmmac_hwif_find(core_type, priv-\u003esynopsys_id, version.dev_id);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-350-\tif (!entry) {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-352-\t\t\t\"Failed to find HW IF (id=0x%x, gmac=%d/%d)\\n\",\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:353:\t\t\tversion.snpsver, core_type == DWMAC_CORE_GMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:354:\t\t\tcore_type == DWMAC_CORE_GMAC4);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-355-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=28=static int est_configure(struct stmmac_priv *priv, struct stmmac_est *cfg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-55-\tctrl = readl(est_addr + EST_CONTROL);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:56:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-57-\t\tctrl \u0026= ~EST_XGMAC_PTOV;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=83=static void est_irq_status(struct stmmac_priv *priv, struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-150-\tif (status \u0026 EST_BTRE) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:151:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-152-\t\t\tbtrl = FIELD_GET(EST_XGMAC_BTRL, status);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=301=static void stmmac_ethtool_getdrvinfo(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-305-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:306:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:307:\t    priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-308-\t\tstrscpy(info-\u003edriver, GMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:309:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-310-\t\tstrscpy(info-\u003edriver, XGMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=350=static int stmmac_ethtool_get_regs_len(struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-353-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:354:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-355-\t\treturn XGMAC_REGSIZE * 4;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:356:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-357-\t\treturn GMAC4_REG_SPACE_SIZE;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=361=static void stmmac_ethtool_gregs(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-370-\t/* Copy DMA registers to where ethtool expects them */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:371:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-372-\t\t/* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-375-\t\t       NUM_DWMAC4_DMA_REGS * 4);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:376:\t} else if (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-377-\t\tmemcpy(\u0026reg_space[ETHTOOL_DMA_OFFSET],\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=576=static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-585-\t/* For GMAC4, the valid timestamp is from CTX next desc. */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:586:\tif (dwmac_is_xmac(priv-\u003eplat-\u003ecore_type))\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-587-\t\tdesc = np;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=604=static void stmmac_update_subsecond_increment(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-605-{\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:606:\tbool xmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-607-\tu32 sec_inc = 0;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=642=static int stmmac_hwtstamp_set(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-759-\t\t\tif (priv-\u003esynopsys_id \u003c DWMAC_CORE_3_70 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:760:\t\t\t    priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-761-\t\t\t\tts_event_en = PTP_TCR_TSEVNTENA;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=910=static int stmmac_init_timestamping(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-911-{\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:912:\tbool xmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-913-\tint ret;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=2600=static void stmmac_dma_operation_mode(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-2616-\t/* Split up the shared Tx/Rx FIFO memory on DW QoS Eth and DW XGMAC */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:2617:\tif (dwmac_is_xmac(priv-\u003eplat-\u003ecore_type)) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-2618-\t\trxfifosz /= rx_channels_count;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=4428=static void stmmac_set_gso_features(struct net_device *ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-4457-\tndev-\u003ehw_features |= NETIF_F_TSO | NETIF_F_TSO6;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:4458:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-4459-\t\tndev-\u003ehw_features |= NETIF_F_GSO_UDP_L4;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=5206=static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-5231-\t/* Not GMAC4 and not last descriptor */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:5232:\tif (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_GMAC4 \u0026\u0026 (status \u0026 rx_not_ls))\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-5233-\t\treturn priv-\u003edma_conf.dma_buf_sz;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6290=static void stmmac_common_interrupt(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6297-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6298:\txmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6299-\tqueues_count = (rx_cnt \u003e tx_cnt) ? rx_cnt : tx_cnt;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6311-\t/* To handle GMAC own interrupts */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6312:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC || xmac) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6313-\t\tint status = stmmac_host_irq_status(priv, \u0026priv-\u003exstats);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6608=static int stmmac_dma_cap_show(struct seq_file *seq, void *v)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6643-\t\t   (priv-\u003edma_cap.half_duplex) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6644:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6645-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6647-\t\t\t   priv-\u003edma_cap.multi_addr);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6648:\t} else if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6649-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6679-\t\t   (priv-\u003edma_cap.atime_stamp) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6680:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6681-\t\tseq_printf(seq, \"\\tTimestamp System Time Source: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6688-\tif (priv-\u003esynopsys_id \u003e= DWMAC_CORE_4_00 ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6689:\t    priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6690-\t\tseq_printf(seq, \"\\tIP Checksum Offload in RX: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7421=static void stmmac_print_actphyif(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7426-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7427:\tswitch (priv-\u003eplat-\u003ecore_type) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7428-\tcase DWMAC_CORE_MAC100:\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7463=static int stmmac_hw_init(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7563-\t */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7564:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7565-\t\tpriv-\u003ehw-\u003emulti_addr = priv-\u003edma_cap.multi_addr;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7612-\tif ((priv-\u003esynopsys_id \u003e= DWMAC_CORE_3_50 ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7613:\t     priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7614-\t    !priv-\u003eplat-\u003eriwt_off) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7722=static int stmmac_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7734-\t/* For GMAC4, the valid timestamp is from CTX next desc. */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7735:\tif (dwmac_is_xmac(priv-\u003eplat-\u003ecore_type))\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7736-\t\tdesc_contains_ts = ndesc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7878=static int __stmmac_dvr_probe(struct device *device,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8056-\tndev-\u003efeatures |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:8057:\tif (dwmac_is_xmac(priv-\u003eplat-\u003ecore_type)) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8058-\t\tndev-\u003ehw_features |= NETIF_F_HW_VLAN_CTAG_RX;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8085-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:8086:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8087-\t\tndev-\u003emax_mtu = XGMAC_JUMBO_LEN;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=299=static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-303-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:304:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-305-\t\tcmd = MII_GMAC4_READ;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=341=static int stmmac_mdio_write_c22(struct mii_bus *bus, int phyaddr, int phyreg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-346-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:347:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-348-\t\tcmd = MII_GMAC4_WRITE;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=381=int stmmac_mdio_reset(struct mii_bus *bus)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-419-\t */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:420:\tif (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-421-\t\twritel(0, priv-\u003eioaddr + mii_address);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=536=static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-554-\t\trates = stmmac_sun8i_csr_to_mdc;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:555:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-556-\t\trates = stmmac_xgmac_csr_to_mdc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=595=int stmmac_mdio_register(struct net_device *ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-621-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:622:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-623-\t\tnew_bus-\u003eread = \u0026stmmac_xgmac2_mdio_read_c22;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-639-\t\tnew_bus-\u003ewrite = \u0026stmmac_mdio_write_c22;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:640:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-641-\t\t\tnew_bus-\u003eread_c45 = \u0026stmmac_mdio_read_c45;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-665-\t/* Looks like we need a dummy read for XGMAC only and C45 PHYs */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:666:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-667-\t\tstmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c=23=static void common_default_data(struct plat_stmmacenet_data *plat)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-26-\tplat-\u003eclk_csr = STMMAC_CSR_20_35M;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c:27:\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-28-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c=54=static int snps_gmac5_default_data(struct pci_dev *pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-59-\tplat-\u003eclk_csr = STMMAC_CSR_250_300M;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c:60:\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-61-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c=415=stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-519-\t\t\t\t\u0026pdev-\u003edev, plat-\u003emulticast_filter_bins);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:520:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-521-\t\tplat-\u003epmt = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-524-\tif (of_device_is_compatible(np, \"snps,dwmac-3.40a\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:525:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-526-\t\tplat-\u003eenh_desc = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-532-\tif (of_device_compatible_match(np, stmmac_gmac4_compats)) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:533:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-534-\t\tplat-\u003epmt = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-546-\tif (of_device_is_compatible(np, \"snps,dwxgmac\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:547:\t\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-548-\t\tplat-\u003epmt = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c=49=static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c-59-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c:60:\txmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c-61-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c=335=void stmmac_ptp_register(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c-348-\tpriv-\u003eplat-\u003ecdc_error_adj = 0;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c:349:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC4)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c-350-\t\tpriv-\u003eplat-\u003ecdc_error_adj = (2 * NSEC_PER_SEC) / priv-\u003eplat-\u003eclk_ptp_rate;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c=799=static int stmmac_test_flowctrl(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c-818-\t */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c:819:\tif (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_MAC100 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c-820-\t    rx_fifo_size / priv-\u003eplat-\u003erx_queues_to_use \u003c 4096)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c=1678=static int __stmmac_test_jumbo(struct stmmac_priv *priv, u16 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c-1682-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c:1683:\tif (!dwmac_is_xmac(priv-\u003eplat-\u003ecore_type))\ndrivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c-1684-\t\tsize -= NET_IP_ALIGN;\n"
}

							input: 50155
							output: 26
							thoughts: 1814

**Analyzing the Reachability of `DWMAC_CORE_XGMAC` and Patch Applicability**

Okay, first things first, let's trace where `DWMAC_CORE_XGMAC` is actually *used*. It's set in a few specific places: `dwmac-socfpga.c`, `dwmac-tegra.c`, and in `stmmac_platform.c` if the OpenFirmware device tree has the "snps,dwxgmac" compatible string. Hmm, so this limits its scope considerably, but is it *completely* limited?

My next thought is, is `dwxgmac` being used or reachable *anywhere* else? Let me check the associated structures - `dwxgmac210_ops`, `dwxgmac210_dma_ops`, and `dwxgmac210_desc_ops`. Aha! They're all referencing `DWMAC_CORE_XGMAC` which we previously identified. This makes perfect sense; the driver is using a common interface that depends on that core type.

Now, who's actually *using* the `dwxgmac` core? Well, the Agilex5, the Tegra Orin, and any device described by a DT node compatible with "snps,dwxgmac." Okay, that's still pretty specific.

Can QEMU emulate a dwxgmac device? That's the critical question for our fuzzing strategy. I'm pretty sure it doesn't. Let's confirm: e1000, e1000e, rtl8139, virtio-net, igb, vmxnet3, ne2k_pci, pcnet... Nope, not seeing dwxgmac or even a generic "dwmac". Even for ARM, it's various other drivers, but no dwxgmac. And remember, our target architecture is AMD64! I need to be sure; is it *possible* to instantiate a dwxgmac on AMD64, perhaps through configfs or sysfs or an OF overlay?

Let's check the triage philosophy, section 2. We should only return `WorthFuzzing=false` if the code change falls into certain negative criteria. The relevant one here is "structurally unreachable hardware". This specifically calls out vendor-specific PCIe switches and drivers not emulated in standard QEMU. Is dwxgmac *effectively* in that category? STMMAC / dwxgmac physical hardware not emulated in QEMU? Yes, that's what I am leaning towards, but let's see.

Let's look at the patch itself to confirm. I need to understand what this patch actually *does*. Okay, the patch updates `dwxgmac2_descs.c` and `dwxgmac2_dma.c`. Specifically, it alters how the header length is determined in received descriptors, and modifies the DMA configuration to enable some SPH functionality, including setting save/segment and disabling variable preambles. Let's search git for this commit or read the commit message for the context. This will show us if the patch itself makes anything *more* reachable.

Let's examine the commit message more thoroughly to understand the patch's purpose and impact on the device's behavior in general. This should provide some insight.

{
  "Expression": "dwxgmac2_get_rx_header_len"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=265=static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-292-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:293:static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-294-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=358=const struct stmmac_desc_ops dwxgmac210_desc_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-379-\t.get_rx_hash = dwxgmac2_get_rx_hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:380:\t.get_rx_header_len = dwxgmac2_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-381-\t.set_sec_addr = dwxgmac2_set_sec_addr,\n"
}

							input: 53105
							output: 41
							thoughts: 107

Okay, let's break this down.

**Investigating the dwxgmac2 Driver's SPH Functionality**

Right, so I need to understand how the SPH (Source Port Header) functionality is being enabled and used within this `dwxgmac2` driver. I see that `dwxgmac2_get_rx_header_len` lives within `dwxgmac210_desc_ops.get_rx_header_len`, that's straightforward enough. Now, `dwxgmac2_enable_sph` is located in `dwxgmac210_dma_ops`, which is interesting. It indicates SPH enabling is likely linked to the DMA (Direct Memory Access) operations, which makes sense. My next step is to pinpoint the exact call path for `dwxgmac2_enable_sph`. I need to trace *where* this function is actually invoked to see what triggers the SPH feature. More specifically, I should check how `enable_sph` is set within `dwxgmac2_dma.c`. This is where the configuration logic that enables or disables the SPH feature would be located.

{
  "Expression": "dwxgmac2_enable_sph",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=545=static void dwxgmac2_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-554-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:555:static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-556-\t\t\t\tbool en, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=605=const struct stmmac_dma_ops dwxgmac210_dma_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-630-\t.set_bfsize = dwxgmac2_set_bfsize,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:631:\t.enable_sph = dwxgmac2_enable_sph,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-632-\t.enable_tbs = dwxgmac2_enable_tbs,\n"
}

							input: 53888
							output: 44
							thoughts: 73

Okay, let's break this down.

**Analyzing Recent Code Changes in the stmmac Driver**

Alright, so the modifications center around two specific functions: `dwxgmac210_dma_ops.enable_sph` and `dwxgmac210_desc_ops.get_rx_header_len`. My initial question is always, "Where are these functions *actually* being used within the stmmac driver?" Understanding the call graph is crucial here. I need to trace back from these modified functions to their points of invocation. This is the starting point for understanding the impact of these changes. Are they core to the data path? Are they only used in a corner case? The answer to those questions influences how urgent I consider a review, and also whether I need to carefully consider testing specific scenarios related to their uses.

{
  "Expression": "enable_sph|get_rx_header_len",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c=508=static void dwmac4_set_vlan(struct dma_desc *p, u32 type)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c-512-\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c:513:static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c-514-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c=537=const struct stmmac_desc_ops dwmac4_desc_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c-561-\t.set_vlan = dwmac4_set_vlan,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c:562:\t.get_rx_header_len = dwmac4_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c-563-\t.set_sec_addr = dwmac4_set_sec_addr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c=515=static void dwmac4_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-525-\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c:526:static void dwmac4_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-527-\t\t\t      bool en, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c=571=const struct stmmac_dma_ops dwmac4_dma_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-597-\t.set_bfsize = dwmac4_set_bfsize,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c:598:\t.enable_sph = dwmac4_enable_sph,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-599-};\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c=601=const struct stmmac_dma_ops dwmac410_dma_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-627-\t.set_bfsize = dwmac4_set_bfsize,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c:628:\t.enable_sph = dwmac4_enable_sph,\ndrivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c-629-\t.enable_tbs = dwmac4_enable_tbs,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=265=static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-292-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:293:static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-294-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=358=const struct stmmac_desc_ops dwxgmac210_desc_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-379-\t.get_rx_hash = dwxgmac2_get_rx_hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:380:\t.get_rx_header_len = dwxgmac2_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-381-\t.set_sec_addr = dwxgmac2_set_sec_addr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=545=static void dwxgmac2_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-554-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:555:static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-556-\t\t\t\tbool en, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=605=const struct stmmac_dma_ops dwxgmac210_dma_ops = {\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-630-\t.set_bfsize = dwxgmac2_set_bfsize,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:631:\t.enable_sph = dwxgmac2_enable_sph,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-632-\t.enable_tbs = dwxgmac2_enable_tbs,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h=39=struct stmmac_desc_ops {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-94-\t\t\t   enum pkt_hash_types *type);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:95:\tvoid (*get_rx_header_len)(struct dma_desc *p, unsigned int *len);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-96-\tvoid (*set_sec_addr)(struct dma_desc *p, dma_addr_t addr, bool buf2_valid);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-149-\tstmmac_do_callback(__priv, desc, get_rx_hash, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:150:#define stmmac_get_rx_header_len(__priv, __args...) \\\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:151:\tstmmac_do_void_callback(__priv, desc, get_rx_header_len, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-152-#define stmmac_set_desc_sec_addr(__priv, __args...) \\\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h=167=struct stmmac_dma_ops {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-229-\t\t\t   int bfsize, u32 chan);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:230:\tvoid (*enable_sph)(struct stmmac_priv *priv, void __iomem *ioaddr,\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-231-\t\t\t   bool en, u32 chan);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-291-\tstmmac_do_void_callback(__priv, dma, set_bfsize, __priv, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:292:#define stmmac_enable_sph(__priv, __args...) \\\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:293:\tstmmac_do_void_callback(__priv, dma, enable_sph, __priv, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-294-#define stmmac_enable_tbs(__priv, __args...) \\\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=3670=static int stmmac_hw_setup(struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-3763-\tfor (chan = 0; chan \u003c rx_cnt; chan++)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:3764:\t\tstmmac_enable_sph(priv, priv-\u003eioaddr, sph_en, chan);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-3765-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=5178=static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-5189-\t/* First descriptor, get split header length */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:5190:\tstmmac_get_rx_header_len(priv, p, \u0026hlen);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-5191-\tif (priv-\u003esph_active \u0026\u0026 hlen) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6255=static int stmmac_set_features(struct net_device *netdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6274-\t\tfor (chan = 0; chan \u003c priv-\u003eplat-\u003erx_queues_to_use; chan++)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6275:\t\t\tstmmac_enable_sph(priv, priv-\u003eioaddr, sph_en, chan);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6276-\t}\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7184=int stmmac_xdp_open(struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7232-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7233:\t\tstmmac_enable_sph(priv, priv-\u003eioaddr, sph_en, chan);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7234-\t}\n"
}

							input: 57227
							output: 49
							thoughts: 875

**Reachability Analysis for `dwxgmac2` in an AMD64 Environment**

Okay, let's break this down. My goal is to determine if `dwxgmac2` is reachable in a standard QEMU / GCE amd64 environment. First, I need to remind myself of the triage instructions. Specifically, what constitutes "structurally unreachable hardware" and "unreachable execution paths". The instructions highlight things like vendor-specific PCIe switches, specialized NICs, and driver teardown paths tied to physical hot-unplug, none of which seems directly relevant to *probing* the driver.

The initial question then is: can the `stmmac` driver for `dwxgmac2` even be *probed* in this setup? Can *any* device bind to `dwxgmac2` on amd64?

I need to trace the setup path. My first step is to check all callers of `dwxgmac2_setup`. Looking at `hwif.c`, I see that `dwxgmac2_setup` is used within a table, `stmmac_hwif_entry`. This table associates `dwxgmac2_setup` with devices having `.core_type = DWMAC_CORE_XGMAC` and specific device IDs. I need to understand what sets this `core_type`.

A quick grep for `DWMAC_CORE_XGMAC` identifies a few interesting spots: `dwmac-socfpga.c` (Intel FPGA SoC), `dwmac-tegra.c` (NVIDIA Tegra), and `stmmac_platform.c`. The latter, specifically `stmmac_probe_config_dt`, is intriguing, as it uses Device Tree entries: `of_device_is_compatible(np, "snps,dwxgmac")`. So, it appears the path is through Device Tree compatibility.

Here's the problem. AMD64/x86 typically uses ACPI/PCI, not Device Tree, so I need to know if the Device Tree can be used on AMD64. Even if an OF overlay could be loaded, the main question is, does *any* QEMU virtual machine emulate a Synopsys DesignWare 10G Ethernet MAC (`dwxgmac`)? This is critical! If QEMU doesn't emulate it, it's a dead end, even if I could load a Device Tree.

Time to search the kernel or QEMU documentation. Does QEMU even *have* a `snps,dwxgmac` or anything like a `dwxgmac` emulation? Based on my previous knowledge, the answer is no. QEMU does *not* emulate a Synopsys dwxgmac at all! And, even if QEMU had a dwmac, that's not `dwxgmac`, and this is AMD64, so that's irrelevant.

So, I need to look at the PCI setup. I'm going to investigate `stmmac_pci.c`, to see what PCI devices it actually supports to verify this assumption.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c",
  "FirstLine": 1,
  "LineCount": 100
}

{
  "Contents": "   1:\t// SPDX-License-Identifier: GPL-2.0-only\n   2:\t/*******************************************************************************\n   3:\t  This contains the functions to handle the pci driver.\n   4:\t\n   5:\t  Copyright (C) 2011-2012  Vayavya Labs Pvt Ltd\n   6:\t\n   7:\t\n   8:\t  Author: Rayagond Kokatanur \u003crayagond@vayavyalabs.com\u003e\n   9:\t  Author: Giuseppe Cavallaro \u003cpeppe.cavallaro@st.com\u003e\n  10:\t*******************************************************************************/\n  11:\t\n  12:\t#include \u003clinux/clk-provider.h\u003e\n  13:\t#include \u003clinux/pci.h\u003e\n  14:\t#include \u003clinux/dmi.h\u003e\n  15:\t\n  16:\t#include \"stmmac.h\"\n  17:\t#include \"stmmac_libpci.h\"\n  18:\t\n  19:\tstruct stmmac_pci_info {\n  20:\t\tint (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);\n  21:\t};\n  22:\t\n  23:\tstatic void common_default_data(struct plat_stmmacenet_data *plat)\n  24:\t{\n  25:\t\t/* clk_csr_i = 20-35MHz \u0026 MDC = clk_csr_i/16 */\n  26:\t\tplat-\u003eclk_csr = STMMAC_CSR_20_35M;\n  27:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\n  28:\t\tplat-\u003eforce_sf_dma_mode = true;\n  29:\t\n  30:\t\tplat-\u003emdio_bus_data-\u003eneeds_reset = true;\n  31:\t}\n  32:\t\n  33:\tstatic int stmmac_default_data(struct pci_dev *pdev,\n  34:\t\t\t\t       struct plat_stmmacenet_data *plat)\n  35:\t{\n  36:\t\t/* Set common default data first */\n  37:\t\tcommon_default_data(plat);\n  38:\t\n  39:\t\tplat-\u003ebus_id = 1;\n  40:\t\tplat-\u003ephy_addr = 0;\n  41:\t\tplat-\u003ephy_interface = PHY_INTERFACE_MODE_GMII;\n  42:\t\n  43:\t\tplat-\u003edma_cfg-\u003epbl = 32;\n  44:\t\tplat-\u003edma_cfg-\u003epblx8 = true;\n  45:\t\t/* TODO: AXI */\n  46:\t\n  47:\t\treturn 0;\n  48:\t}\n  49:\t\n  50:\tstatic const struct stmmac_pci_info stmmac_pci_info = {\n  51:\t\t.setup = stmmac_default_data,\n  52:\t};\n  53:\t\n  54:\tstatic int snps_gmac5_default_data(struct pci_dev *pdev,\n  55:\t\t\t\t\t   struct plat_stmmacenet_data *plat)\n  56:\t{\n  57:\t\tint i;\n  58:\t\n  59:\t\tplat-\u003eclk_csr = STMMAC_CSR_250_300M;\n  60:\t\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\n  61:\t\tplat-\u003eforce_sf_dma_mode = true;\n  62:\t\tplat-\u003eflags |= STMMAC_FLAG_TSO_EN;\n  63:\t\tplat-\u003epmt = true;\n  64:\t\n  65:\t\t/* Set default number of RX and TX queues to use */\n  66:\t\tplat-\u003etx_queues_to_use = 4;\n  67:\t\tplat-\u003erx_queues_to_use = 4;\n  68:\t\n  69:\t\tplat-\u003etx_sched_algorithm = MTL_TX_ALGORITHM_WRR;\n  70:\t\tfor (i = 0; i \u003c plat-\u003etx_queues_to_use; i++) {\n  71:\t\t\tplat-\u003etx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;\n  72:\t\t\tplat-\u003etx_queues_cfg[i].weight = 25;\n  73:\t\t\tif (i \u003e 0)\n  74:\t\t\t\tplat-\u003etx_queues_cfg[i].tbs_en = 1;\n  75:\t\t}\n  76:\t\n  77:\t\tplat-\u003erx_sched_algorithm = MTL_RX_ALGORITHM_SP;\n  78:\t\tfor (i = 0; i \u003c plat-\u003erx_queues_to_use; i++)\n  79:\t\t\tplat-\u003erx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;\n  80:\t\n  81:\t\tplat-\u003ebus_id = 1;\n  82:\t\tplat-\u003ephy_interface = PHY_INTERFACE_MODE_GMII;\n  83:\t\n  84:\t\tplat-\u003edma_cfg-\u003epbl = 32;\n  85:\t\tplat-\u003edma_cfg-\u003epblx8 = true;\n  86:\t\n  87:\t\t/* Axi Configuration */\n  88:\t\tplat-\u003eaxi = devm_kzalloc(\u0026pdev-\u003edev, sizeof(*plat-\u003eaxi), GFP_KERNEL);\n  89:\t\tif (!plat-\u003eaxi)\n  90:\t\t\treturn -ENOMEM;\n  91:\t\n  92:\t\tplat-\u003eaxi-\u003eaxi_wr_osr_lmt = 31;\n  93:\t\tplat-\u003eaxi-\u003eaxi_rd_osr_lmt = 31;\n  94:\t\n  95:\t\tplat-\u003eaxi-\u003eaxi_fb = false;\n  96:\t\tplat-\u003eaxi-\u003eaxi_blen_regval = DMA_AXI_BLEN4 | DMA_AXI_BLEN8 |\n  97:\t\t\t\t\t     DMA_AXI_BLEN16 | DMA_AXI_BLEN32;\n  98:\t\n  99:\t\treturn 0;\n 100:\t}\n"
}

							input: 60389
							output: 51
							thoughts: 17

Okay, here's my take on those thoughts, tailored for an expert audience, and delivered as a first-person summary:

**Diving Back into stmmac_pci.c**

Alright, time to get back to `stmmac_pci.c`. We've covered the basics, but there's always more lurking in these drivers, isn't there? I need to meticulously go through the rest of this file. Let's see what else they've implemented, any subtle nuances in the PCI-specific initialization, resource allocation strategies, and of course, the interrupt handling. I'm especially keen to look for any potential areas of concern for our specific hardware revisions, maybe specific workaround applied for hardware errata. Gotta make sure we haven't missed anything in the context of our recent performance issues...or, heaven forbid, security vulnerabilities. It's a deep dive, but necessary. Let's get to it.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c",
  "FirstLine": 101,
  "LineCount": 100
}

{
  "Contents": " 101:\t\n 102:\tstatic const struct stmmac_pci_info snps_gmac5_pci_info = {\n 103:\t\t.setup = snps_gmac5_default_data,\n 104:\t};\n 105:\t\n 106:\t/**\n 107:\t * stmmac_pci_probe\n 108:\t *\n 109:\t * @pdev: pci device pointer\n 110:\t * @id: pointer to table of device id/id's.\n 111:\t *\n 112:\t * Description: This probing function gets called for all PCI devices which\n 113:\t * match the ID table and are not \"owned\" by other driver yet. This function\n 114:\t * gets passed a \"struct pci_dev *\" for each device whose entry in the ID table\n 115:\t * matches the device. The probe functions returns zero when the driver choose\n 116:\t * to take \"ownership\" of the device or an error code(-ve no) otherwise.\n 117:\t */\n 118:\tstatic int stmmac_pci_probe(struct pci_dev *pdev,\n 119:\t\t\t\t    const struct pci_device_id *id)\n 120:\t{\n 121:\t\tstruct stmmac_pci_info *info = (struct stmmac_pci_info *)id-\u003edriver_data;\n 122:\t\tstruct plat_stmmacenet_data *plat;\n 123:\t\tstruct stmmac_resources res = {};\n 124:\t\tint ret;\n 125:\t\tint i;\n 126:\t\n 127:\t\tplat = stmmac_plat_dat_alloc(\u0026pdev-\u003edev);\n 128:\t\tif (!plat)\n 129:\t\t\treturn -ENOMEM;\n 130:\t\n 131:\t\tplat-\u003emdio_bus_data = devm_kzalloc(\u0026pdev-\u003edev,\n 132:\t\t\t\t\t\t   sizeof(*plat-\u003emdio_bus_data),\n 133:\t\t\t\t\t\t   GFP_KERNEL);\n 134:\t\tif (!plat-\u003emdio_bus_data)\n 135:\t\t\treturn -ENOMEM;\n 136:\t\n 137:\t\tplat-\u003esafety_feat_cfg = devm_kzalloc(\u0026pdev-\u003edev,\n 138:\t\t\t\t\t\t     sizeof(*plat-\u003esafety_feat_cfg),\n 139:\t\t\t\t\t\t     GFP_KERNEL);\n 140:\t\tif (!plat-\u003esafety_feat_cfg)\n 141:\t\t\treturn -ENOMEM;\n 142:\t\n 143:\t\t/* Enable pci device */\n 144:\t\tret = pcim_enable_device(pdev);\n 145:\t\tif (ret) {\n 146:\t\t\tdev_err(\u0026pdev-\u003edev, \"%s: ERROR: failed to enable device\\n\",\n 147:\t\t\t\t__func__);\n 148:\t\t\treturn ret;\n 149:\t\t}\n 150:\t\n 151:\t\t/* Get the base address of device */\n 152:\t\tfor (i = 0; i \u003c PCI_STD_NUM_BARS; i++) {\n 153:\t\t\tif (pci_resource_len(pdev, i) == 0)\n 154:\t\t\t\tcontinue;\n 155:\t\t\tres.addr = pcim_iomap_region(pdev, i, STMMAC_RESOURCE_NAME);\n 156:\t\t\tif (IS_ERR(res.addr))\n 157:\t\t\t\treturn PTR_ERR(res.addr);\n 158:\t\t\tbreak;\n 159:\t\t}\n 160:\t\n 161:\t\tpci_set_master(pdev);\n 162:\t\n 163:\t\tret = info-\u003esetup(pdev, plat);\n 164:\t\tif (ret)\n 165:\t\t\treturn ret;\n 166:\t\n 167:\t\tres.wol_irq = pdev-\u003eirq;\n 168:\t\tres.irq = pdev-\u003eirq;\n 169:\t\n 170:\t\tplat-\u003esafety_feat_cfg-\u003etsoee = 1;\n 171:\t\tplat-\u003esafety_feat_cfg-\u003emrxpee = 1;\n 172:\t\tplat-\u003esafety_feat_cfg-\u003emestee = 1;\n 173:\t\tplat-\u003esafety_feat_cfg-\u003emrxee = 1;\n 174:\t\tplat-\u003esafety_feat_cfg-\u003emtxee = 1;\n 175:\t\tplat-\u003esafety_feat_cfg-\u003eepsi = 1;\n 176:\t\tplat-\u003esafety_feat_cfg-\u003eedpp = 1;\n 177:\t\tplat-\u003esafety_feat_cfg-\u003eprtyen = 1;\n 178:\t\tplat-\u003esafety_feat_cfg-\u003etmouten = 1;\n 179:\t\n 180:\t\tplat-\u003esuspend = stmmac_pci_plat_suspend;\n 181:\t\tplat-\u003eresume = stmmac_pci_plat_resume;\n 182:\t\n 183:\t\treturn stmmac_dvr_probe(\u0026pdev-\u003edev, plat, \u0026res);\n 184:\t}\n 185:\t\n 186:\t/**\n 187:\t * stmmac_pci_remove\n 188:\t *\n 189:\t * @pdev: platform device pointer\n 190:\t * Description: this function calls the main to free the net resources.\n 191:\t */\n 192:\tstatic void stmmac_pci_remove(struct pci_dev *pdev)\n 193:\t{\n 194:\t\tstmmac_dvr_remove(\u0026pdev-\u003edev);\n 195:\t}\n 196:\t\n 197:\t/* synthetic ID, no official vendor */\n 198:\t#define PCI_VENDOR_ID_STMMAC\t\t0x0700\n 199:\t\n 200:\t#define PCI_DEVICE_ID_STMMAC_STMMAC\t\t0x1108\n"
}

							input: 62252
							output: 50
							thoughts: 17

Okay, here's my take on those thoughts, tailored for an expert audience, and delivered as a first-person summary:

**Digging into stmmac_pci.c**

Alright, so I need to get a handle on the rest of this `stmmac_pci.c` file. I've been over the initial sections, but I'm thinking I'm missing some crucial context. I'm already visualizing the PCI device probing and initialization sequences it probably contains. I'm mentally parsing where the interrupt handling might be defined – is it a direct interrupt, MSI, or something else entirely? I bet there's a good chunk dedicated to DMA setup and buffer management, especially considering it's a network device. I'm keen to see how they're handling the power management aspects and resource allocation. Are they using the standard PCI resource management functions, or have they implemented something custom to optimize performance or handle the specific requirements of the STMMAC? I need to look for any interesting tricks they're employing for link status detection or offload features. I'm guessing there's a section on error handling and how they manage device resets if things go sideways. I should also be mindful of any platform-specific dependencies they might be using that relate to the STMMAC core itself. Gotta be sure to understand any of those potential gotchas. Basically, I want to map out the whole lifecycle of this driver's interaction with the PCI bus and the underlying hardware. Knowing that will give me a comprehensive understanding of the driver.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c",
  "FirstLine": 201,
  "LineCount": 40
}

{
  "Contents": " 201:\t#define PCI_DEVICE_ID_SYNOPSYS_GMAC5_ID\t\t0x7102\n 202:\t\n 203:\tstatic const struct pci_device_id stmmac_id_table[] = {\n 204:\t\t{ PCI_DEVICE_DATA(STMMAC, STMMAC, \u0026stmmac_pci_info) },\n 205:\t\t{ PCI_DEVICE_DATA(STMICRO, MAC, \u0026stmmac_pci_info) },\n 206:\t\t{ PCI_DEVICE_DATA(SYNOPSYS, GMAC5_ID, \u0026snps_gmac5_pci_info) },\n 207:\t\t{}\n 208:\t};\n 209:\t\n 210:\tMODULE_DEVICE_TABLE(pci, stmmac_id_table);\n 211:\t\n 212:\tstatic struct pci_driver stmmac_pci_driver = {\n 213:\t\t.name = STMMAC_RESOURCE_NAME,\n 214:\t\t.id_table = stmmac_id_table,\n 215:\t\t.probe = stmmac_pci_probe,\n 216:\t\t.remove = stmmac_pci_remove,\n 217:\t\t.driver         = {\n 218:\t\t\t.pm     = \u0026stmmac_simple_pm_ops,\n 219:\t\t},\n 220:\t};\n 221:\t\n 222:\tmodule_pci_driver(stmmac_pci_driver);\n 223:\t\n 224:\tMODULE_DESCRIPTION(\"STMMAC 10/100/1000 Ethernet PCI driver\");\n 225:\tMODULE_AUTHOR(\"Rayagond Kokatanur \u003crayagond.kokatanur@vayavyalabs.com\u003e\");\n 226:\tMODULE_AUTHOR(\"Giuseppe Cavallaro \u003cpeppe.cavallaro@st.com\u003e\");\n 227:\tMODULE_LICENSE(\"GPL\");\n"
}

							input: 63169
							output: 43
							thoughts: 112

**Investigating the Core Type Assignment for DWMAC Drivers**

Okay, so I'm digging into how the `core_type` is being assigned for these DWMAC drivers, specifically regarding XGMAC support. I noticed that when looking at the `snps_gmac5_pci_info` structure, it explicitly sets `plat->core_type` to `DWMAC_CORE_GMAC4`. Similarly, `stmmac_pci_info` assigns `DWMAC_CORE_GMAC`. Neither of these is setting `DWMAC_CORE_XGMAC`, which is what I'm interested in. That's a red flag.

My next move is to check the `dwmac-intel.c` file. I need to know if Intel's DWMAC driver has any XGMAC implementations, and if so, how it handles the `core_type` assignment. Let's get into that file and see what's going on there. I'm hoping to find the missing piece of this puzzle and how they are handled.

{
  "Expression": "core_type",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=596=static void common_default_data(struct plat_stmmacenet_data *plat)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-599-\tplat-\u003eclk_csr = STMMAC_CSR_20_35M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:600:\tplat-\u003ecore_type = DWMAC_CORE_GMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-601-\tplat-\u003eforce_sf_dma_mode = true;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=616=static int intel_mgbe_common_data(struct pci_dev *pdev,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-626-\tplat-\u003eclk_csr = STMMAC_CSR_250_300M;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:627:\tplat-\u003ecore_type = DWMAC_CORE_GMAC4;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-628-\tplat-\u003eforce_sf_dma_mode = 0;\n"
}

							input: 63926
							output: 24
							thoughts: 373

**Investigating the DWMAC Core Types and XGMAC Usage**

Okay, so I'm looking at these DWMAC core types, specifically in relation to how they're being used. I see that `dwmac-intel.c` is only using `DWMAC_CORE_GMAC` and `DWMAC_CORE_GMAC4`. Alright, that's fine. What about the others? `dwmac-loongson.c` only uses `DWMAC_CORE_GMAC`. Okay. `dwmac-motorcomm.c` uses `DWMAC_CORE_GMAC4`. Fine, that seems normal.

But then it hits me: what about `DWMAC_CORE_XGMAC`? Is *any* PCI driver actually setting that? I can't recall any offhand. Let's double-check the grep results for `DWMAC_CORE_XGMAC`.

Ah, here we go. The places where `core_type = DWMAC_CORE_XGMAC` are:

1.  `dwmac-socfpga.c`: Specifically, `socfpga_agilex5_setup_plat_dat`. Agilex5 is, of course, an Intel Altera SoC FPGA, which is ARM64. Got it.
2.  `dwmac-tegra.c`: Specifically, `tegra_mgbe_probe`. And the Tegra Orin MGBE is ARM64 too.
3.  `stmmac_platform.c`: This one is interesting: `of_device_is_compatible(np, "snps,dwxgmac")`. That's using Device Tree for platform devices. More ARM/ARM64-type systems, which is what I suspected.

Wait a second. What about those specific sets of ops, `dwxgmac210_ops`, `dwxgmac210_dma_ops`, and `dwxgmac210_desc_ops`? Are *they* referenced anywhere else? Let's check where `dwxgmac210_dma_ops`, `dwxgmac210_desc_ops`, and `dwxgmac2_setup` are being used. It's time to dig deeper!

{
  "Expression": "dwxgmac210_desc_ops"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h=474=extern const struct stmmac_dma_ops dwxgmac210_dma_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:475:extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-476-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c=350=static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-357-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:358:const struct stmmac_desc_ops dwxgmac210_desc_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-359-\t.tx_status = dwxgmac2_get_tx_status,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-256-\t\t},\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:257:\t\t.desc = \u0026dwxgmac210_desc_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-258-\t\t.dma = \u0026dwxgmac210_dma_ops,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-278-\t\t},\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:279:\t\t.desc = \u0026dwxgmac210_desc_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-280-\t\t.dma = \u0026dwxgmac210_dma_ops,\n"
}

							input: 65403
							output: 25
							thoughts: 45

Here's my take on those thoughts:

**Concerning STMMAC and DMA Operations**

Okay, so I'm digging into this `stmmac` situation, and something's pinging my radar. This `stmmac_hwif_entry`... it seems to only be relevant, or at least only *used*, when dealing with `DWMAC_CORE_XGMAC`. That's a key observation. It raises a question in my mind: what about the operations tied to the `dwxgmac210_dma_ops`? Are those implicitly handled, or are there specific conditions I'm missing that dictate when those operations are relevant? I need to understand the relationship between these two, especially in a wider context. This detail is important, and I need to solidify the architecture around this point.

{
  "Expression": "dwxgmac210_dma_ops"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h=473=extern const struct stmmac_ops dwxlgmac2_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:474:extern const struct stmmac_dma_ops dwxgmac210_dma_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-475-extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=582=static int dwxgmac2_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-604-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:605:const struct stmmac_dma_ops dwxgmac210_dma_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-606-\t.reset = dwxgmac2_dma_reset,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-257-\t\t.desc = \u0026dwxgmac210_desc_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:258:\t\t.dma = \u0026dwxgmac210_dma_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-259-\t\t.mac = \u0026dwxgmac210_ops,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-279-\t\t.desc = \u0026dwxgmac210_desc_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:280:\t\t.dma = \u0026dwxgmac210_dma_ops,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-281-\t\t.mac = \u0026dwxlgmac2_ops,\n"
}

### 1. Approaches Tried and Results

* **Diff inspection**:
  * Patch f0b5e1ec09b7 ("syz-cluster: applied patch under review") modifies:
    * `drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h`: Adds register and bit definitions (`XGMAC_EXT_CFG0`, `XGMAC_EXT_CFG0_VPRE`, `XGMAC_EXT_CFG1`, `XGMAC_CONFIG1_SAVE_EN`, `XGMAC_CONFIG1_SPLM(v)`, `XGMAC_RDES2_NONIPHL`, `XGMAC_RDES3_L2T`).
    * `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c`: Modifies `dwxgmac2_get_rx_header_len()` to parse L2 split headers and handle `!XGMAC_RDES3_LD` descriptors.
    * `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c`: Modifies `dwxgmac2_enable_sph()` to program `XGMAC_EXT_CFG1` and `XGMAC_EXT_CFG0` for split header mode.
* **Driver architecture and HWIF analysis**:
  * Traced `dwxgmac2_setup()` and associated ops (`dwxgmac210_desc_ops`, `dwxgmac210_dma_ops`, `dwxgmac210_ops`) to `drivers/net/ethernet/stmicro/stmmac/hwif.c`.
  * In `hwif.c`, these ops are registered only for entries matching `core_type == DWMAC_CORE_XGMAC` with `min_id = DWXGMAC_CORE_2_10` / `DWXLGMAC_CORE_2_00` and matching `snpsver` / `dev_id`.
* **Hardware instantiation and bus probing analysis**:
  * Grepped for `DWMAC_CORE_XGMAC` across the entire codebase.
  * Found occurrences setting `plat_dat->core_type = DWMAC_CORE_XGMAC` only in:
    1. `drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c`: `socfpga_agilex5_setup_plat_dat()` (Intel Agilex5 SoC FPGA, ARM64 Device Tree).
    2. `drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c`: `tegra_mgbe_probe()` (NVIDIA Tegra Orin/Thor MGBE, ARM64 Device Tree).
    3. `drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c`: `stmmac_probe_config_dt()` if `of_device_is_compatible(np, "snps,dwxgmac")` (OF / Device Tree platform devices).
  * Checked PCI glue drivers (`stmmac_pci.c`, `dwmac-intel.c`, `dwmac-loongson.c`, `dwmac-motorcomm.c`):
    * `stmmac_pci.c` sets `DWMAC_CORE_GMAC` or `DWMAC_CORE_GMAC4`.
    * `dwmac-intel.c` sets `DWMAC_CORE_GMAC` or `DWMAC_CORE_GMAC4`.
    * `dwmac-motorcomm.c` sets `DWMAC_CORE_GMAC4`.
    * None set `DWMAC_CORE_XGMAC`.
  * Grepped `dwxgmac|XGMAC` in `stmmac_pci.c` and `dwmac-intel.c` — returned no matches.

### 2. Current Hypotheses and Lines of Investigation

* **Target Architecture**: amd64.
* **Reachability Hypothesis**:
  * The modified code (`dwxgmac2_descs.c`, `dwxgmac2_dma.c`) is exclusively tied to `dwxgmac2` (Synopsys DesignWare 10G/XGMAC IP core).
  * It requires `core_type == DWMAC_CORE_XGMAC`.
  * The only drivers using `DWMAC_CORE_XGMAC` are DT/OF-based platform drivers for ARM64 SoCs (Agilex 5, NVIDIA Tegra MGBE) or generic OF device-tree nodes compatible with `snps,dwxgmac`.
  * No standard QEMU or GCE virtualized environment on amd64 emulates Synopsys XGMAC 10G IP (`snps,dwxgmac` or Tegra MGBE or Agilex 5).
  * The code is structurally unreachable on amd64 in standard virtualized environments (falls under Section 2: Structurally unreachable hardware / physical ASIC or vendor platform devices not emulated in standard QEMU, as well as code paths exclusive to architectures / DT platforms not present in standard amd64 VMs).
  * Therefore, `WorthFuzzing` should evaluate to `false`.

### 3. Critical Code and References

* **Modified Functions**:
  * `dwxgmac2_get_rx_header_len()` in `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c`:
    ```c
    static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)
    {
    	u32 rdes3 = le32_to_cpu(p->des3);

    	/* when FD=1 and LD=0, HL is RDES2[9:0] */
    	if (!(rdes3 & XGMAC_RDES3_LD)) {
    		*len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
    		return;
    	}

    	if (rdes3 & XGMAC_RDES3_L34T)
    		*len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
    	else if (rdes3 & XGMAC_RDES3_L2T)
    		*len = (le32_to_cpu(p->des2) & XGMAC_RDES2_NONIPHL) >> 2;
    }
    ```
  * `dwxgmac2_enable_sph()` in `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c`:
    ```c
    static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,
    				bool en, u32 chan)
    {
    	...
    	value = readl(ioaddr + XGMAC_EXT_CFG1);
    	value |= XGMAC_CONFIG1_SPLM(1);
    	value |= XGMAC_CONFIG1_SAVE_EN;
    	writel(value, ioaddr + XGMAC_EXT_CFG1);

    	/* Disable variable preambles to keep the L2 split offset deterministic. */
    	value = readl(ioaddr + XGMAC_EXT_CFG0);
    	value &= ~XGMAC_EXT_CFG0_VPRE;
    	writel(value, ioaddr + XGMAC_EXT_CFG0);
    	...
    }
    ```
* **HW Registration in `drivers/net/ethernet/stmicro/stmmac/hwif.c`**:
  * Bound via `.core_type = DWMAC_CORE_XGMAC` -> `dwxgmac210_desc_ops`, `dwxgmac210_dma_ops`.
* **Platform Invocations**:
  * `drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c`: `socfpga_agilex5_setup_plat_dat()`
  * `drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c`: `tegra_mgbe_probe()`
  * `drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c`: `of_device_is_compatible(np, "snps,dwxgmac")`

### 4. Next Steps & Warnings

* Do NOT repeat searches for `DWMAC_CORE_XGMAC` or `stmmac_pci.c`. The PCI vs OF driver split has been established.
* Verify if there is any synthetic/mock device or test module (e.g. netkit, dummy, usbnet) that can route into `dwxgmac2_desc_ops` or `dwxgmac210_dma_ops`. (None exist; stmmac ops are strictly invoked by `stmmac_main.c` on physical/platform mmio controllers).
* Prepare to call `set-results` tool with `WorthFuzzing=false` due to unreachable hardware on amd64 QEMU/GCE.

							input: 52565
							output: 2136
							thoughts: 0

							input: 19139
							output: 46
							thoughts: 0

{
  "File": "drivers/net/ethernet/stmicro/stmmac/hwif.c",
  "FirstLine": 250,
  "LineCount": 40
}

{
  "Contents": " 250:\t\t\t.dev_id = DWXGMAC_ID,\n 251:\t\t\t.regs = {\n 252:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 253:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 254:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 255:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 256:\t\t\t},\n 257:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n 258:\t\t\t.dma = \u0026dwxgmac210_dma_ops,\n 259:\t\t\t.mac = \u0026dwxgmac210_ops,\n 260:\t\t\t.vlan = \u0026dwxgmac210_vlan_ops,\n 261:\t\t\t.hwtimestamp = \u0026stmmac_ptp,\n 262:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 263:\t\t\t.mode = NULL,\n 264:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 265:\t\t\t.mmc = \u0026dwxgmac_mmc_ops,\n 266:\t\t\t.est = \u0026dwmac510_est_ops,\n 267:\t\t\t.setup = dwxgmac2_setup,\n 268:\t\t\t.quirks = NULL,\n 269:\t\t}, {\n 270:\t\t\t.core_type = DWMAC_CORE_XGMAC,\n 271:\t\t\t.min_id = DWXLGMAC_CORE_2_00,\n 272:\t\t\t.dev_id = DWXLGMAC_ID,\n 273:\t\t\t.regs = {\n 274:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 275:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 276:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 277:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 278:\t\t\t},\n 279:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n 280:\t\t\t.dma = \u0026dwxgmac210_dma_ops,\n 281:\t\t\t.mac = \u0026dwxlgmac2_ops,\n 282:\t\t\t.vlan = \u0026dwxlgmac2_vlan_ops,\n 283:\t\t\t.hwtimestamp = \u0026stmmac_ptp,\n 284:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 285:\t\t\t.mode = NULL,\n 286:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 287:\t\t\t.mmc = \u0026dwxgmac_mmc_ops,\n 288:\t\t\t.est = \u0026dwmac510_est_ops,\n 289:\t\t\t.setup = dwxlgmac2_setup,\n"
}

							input: 19963
							output: 23
							thoughts: 0

{
  "Expression": "DWMAC_CORE_XGMAC"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/common.h=49=static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)\ndrivers/net/ethernet/stmicro/stmmac/common.h-50-{\ndrivers/net/ethernet/stmicro/stmmac/common.h:51:\treturn core_type == DWMAC_CORE_GMAC4 || core_type == DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/common.h-52-}\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=569=static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-572-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:573:\tplat_dat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-574-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c=214=static int tegra_mgbe_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-325-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c:326:\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-327-\tplat-\u003eflags |= STMMAC_FLAG_TSO_EN;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=21=static void stmmac_get_version(struct stmmac_priv *priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-49-\tver-\u003esnpsver = FIELD_GET(DWMAC_SNPSVER, version);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:50:\tif (core_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-51-\t\tver-\u003edev_id = FIELD_GET(DWMAC_USERVER, version);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-247-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:248:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-249-\t\t.min_id = DWXGMAC_CORE_2_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-269-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:270:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-271-\t\t.min_id = DWXLGMAC_CORE_2_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=294=stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-306-\t\t\tcontinue;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:307:\t\tif (core_type == DWMAC_CORE_XGMAC \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-308-\t\t    dev_id != entry-\u003edev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=28=static int est_configure(struct stmmac_priv *priv, struct stmmac_est *cfg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-55-\tctrl = readl(est_addr + EST_CONTROL);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:56:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-57-\t\tctrl \u0026= ~EST_XGMAC_PTOV;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=83=static void est_irq_status(struct stmmac_priv *priv, struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-150-\tif (status \u0026 EST_BTRE) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:151:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-152-\t\t\tbtrl = FIELD_GET(EST_XGMAC_BTRL, status);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=301=static void stmmac_ethtool_getdrvinfo(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-308-\t\tstrscpy(info-\u003edriver, GMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:309:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-310-\t\tstrscpy(info-\u003edriver, XGMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=350=static int stmmac_ethtool_get_regs_len(struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-353-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:354:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-355-\t\treturn XGMAC_REGSIZE * 4;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=361=static void stmmac_ethtool_gregs(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-375-\t\t       NUM_DWMAC4_DMA_REGS * 4);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:376:\t} else if (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-377-\t\tmemcpy(\u0026reg_space[ETHTOOL_DMA_OFFSET],\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=642=static int stmmac_hwtstamp_set(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-759-\t\t\tif (priv-\u003esynopsys_id \u003c DWMAC_CORE_3_70 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:760:\t\t\t    priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-761-\t\t\t\tts_event_en = PTP_TCR_TSEVNTENA;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6608=static int stmmac_dma_cap_show(struct seq_file *seq, void *v)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6643-\t\t   (priv-\u003edma_cap.half_duplex) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6644:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6645-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6679-\t\t   (priv-\u003edma_cap.atime_stamp) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6680:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6681-\t\tseq_printf(seq, \"\\tTimestamp System Time Source: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6688-\tif (priv-\u003esynopsys_id \u003e= DWMAC_CORE_4_00 ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6689:\t    priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6690-\t\tseq_printf(seq, \"\\tIP Checksum Offload in RX: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7421=static void stmmac_print_actphyif(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7436-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7437:\tcase DWMAC_CORE_XGMAC:\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7438-\t\tphyif_table = stmmac_dwxgmac_phyif;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7463=static int stmmac_hw_init(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7612-\tif ((priv-\u003esynopsys_id \u003e= DWMAC_CORE_3_50 ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7613:\t     priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7614-\t    !priv-\u003eplat-\u003eriwt_off) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7878=static int __stmmac_dvr_probe(struct device *device,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8085-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:8086:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-8087-\t\tndev-\u003emax_mtu = XGMAC_JUMBO_LEN;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=536=static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-554-\t\trates = stmmac_sun8i_csr_to_mdc;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:555:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-556-\t\trates = stmmac_xgmac_csr_to_mdc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=595=int stmmac_mdio_register(struct net_device *ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-621-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:622:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-623-\t\tnew_bus-\u003eread = \u0026stmmac_xgmac2_mdio_read_c22;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-665-\t/* Looks like we need a dummy read for XGMAC only and C45 PHYs */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:666:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-667-\t\tstmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c=415=stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-546-\tif (of_device_is_compatible(np, \"snps,dwxgmac\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:547:\t\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-548-\t\tplat-\u003epmt = true;\n--\ninclude/linux/stmmac.h=191=enum dwmac_core_type {\n--\ninclude/linux/stmmac.h-194-\tDWMAC_CORE_GMAC4,\ninclude/linux/stmmac.h:195:\tDWMAC_CORE_XGMAC,\ninclude/linux/stmmac.h-196-};\n"
}

							input: 24041
							output: 202
							thoughts: 1230

**Analysis of the Code's Reachability**

Okay, let's break this down systematically. My initial assessment indicates the patch touches files related to the Synopsys DesignWare 10G/XGMAC IP core. Specifically, I'm looking at definitions in `dwxgmac2.h` and functions in `dwxgmac2_descs.c` and `dwxgmac2_dma.c`. The functions, `dwxgmac2_get_rx_header_len()` and `dwxgmac2_enable_sph()`, are implemented as part of the `dwxgmac210_desc_ops` and `dwxgmac210_dma_ops` structures respectively.

These structures are referenced only in `hwif.c`. The `stmmac_hwif_entry` table and its matching criteria, using `core_type == DWMAC_CORE_XGMAC`, are key here. I need to understand where `plat->core_type` gets set to `DWMAC_CORE_XGMAC`. I've found three potential locations: `dwmac-socfpga.c` (Intel Agilex5 SoC FPGA), `dwmac-tegra.c` (NVIDIA Tegra Orin/Thor MGBE), and `stmmac_platform.c` (via Device Tree, if compatible with "snps,dwxgmac").

Now, the crucial question: can any of these be triggered on an amd64 system in a standard QEMU / syzkaller environment? The answer is looking like a firm no. Even if DT could theoretically be booted on x86, QEMU does *not* emulate the "snps,dwxgmac" device or Tegra MGBE or Agilex5. I can't think of a way to synthesize a platform device in userspace. The driver relies on OF / DT table `stmmac_dt_ids`. QEMU has nothing that emulates `snps,dwxgmac`. It only emulates standard NICs like e1000, virtio-net, etc.

So, standard QEMU x86_64, which is the target environment, doesn't emulate the Synopsys DesignWare 10G/XGMAC (or GMAC) IP core. This implies that the code requires actual hardware - an Intel Agilex 5, an NVIDIA Tegra Orin SoC, or a real Synopsys XGMAC core.

Let's apply the *negative* criteria. The prompt says to return `WorthFuzzing=false` if the modified code falls strictly into "structurally unreachable hardware". This clearly matches the situation: vendor-specific hardware requiring physical ASIC/PCIe cards that are not emulated in standard QEMU.

Given all of this, the code modifications are fundamentally unreachable in my target testing environment. I'm ready to mark this as un-fuzzable and proceed to the next analysis.

FocusSymbols must be empty if WorthFuzzing is false

{
  "EnableConfigs": [
    "STMMAC_ETH",
    "DWMAC_DWC_QOS_ETH"
  ],
  "FocusSymbols": [
    "dwxgmac2_get_rx_header_len",
    "dwxgmac2_enable_sph"
  ],
  "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

{
  "error": "FocusSymbols must be empty if WorthFuzzing is false"
}

							input: 26140
							output: 156
							thoughts: 36

Okay, here's my take on those thoughts, tailored for an expert audience:

**Addressing a Potential Configuration Inconsistency**

Alright, let's nail this down. If `WorthFuzzing` is set to `false`, then logically, the `FocusSymbols` collection *must* be empty. There's no point in specifying focus symbols if fuzzing isn't even enabled, it just adds unnecessary complexity and potential for misinterpretation. Similarly, the `EnableConfigs` list, that should also be empty (or even better, explicitly `null`) in the same scenario. If fuzzing is off, these settings are not needed. I'm seeing a potential for a subtle but important configuration inconsistency here. Time to refactor and ensure that these properties are appropriately managed, and prevent users from inadvertently setting options that have no effect.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Synopsys DesignWare 10G/XGMAC (dwxgmac2) driver, specifically the split header length parsing and DMA configuration in dwxgmac2_descs.c and dwxgmac2_dma.c. This IP core is only instantiated on specific ARM64 SoCs (e.g., Intel Agilex 5, NVIDIA Tegra) and via Device Tree ('snps,dwxgmac'). It requires physical hardware not emulated in standard QEMU or GCE virtualized environments on amd64, making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

LLM Calls Summary:
Total Calls	Total Tokens	Avg Tokens	Total Duration (Seconds)	Avg Duration (Seconds)

Tool Calls Summary:
Total Calls	Total Duration (Seconds)	Avg Duration (Seconds)