| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/06/30 18:11 | flow | patch-triage |
1mArgs:null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch modifies the Mellanox mlx5 hardware driver, specifically deep logic related to TC flows, Link Aggregation (LAG), and Multi-Port E-Switch (MPESW). Since mlx5 requires physical Mellanox hardware and there is no software emulator for it in the kernel, these code paths are impossible to reach in standard virtualized environments like GCE or QEMU.",
"WorthFuzzing": false
} |
| 1/1 | 2026/06/30 18:11 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit ab2d89faaaf676b499462aae420787c43c40320f\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Tue Jun 30 18:11:17 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c\nindex 910492eb51f276..1bc7b9019124a4 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c\n@@ -5547,6 +5547,9 @@ void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)\n \n \tmlx5_devcom_for_each_peer_entry(devcom, peer_esw, pos) {\n \t\ti = mlx5_lag_get_dev_seq(peer_esw-\u003edev);\n+\t\tif (i \u003c 0)\n+\t\t\tcontinue;\n+\n \t\tlist_for_each_entry_safe(flow, tmp, \u0026esw-\u003eoffloads.peer_flows[i], peer[i])\n \t\t\tmlx5e_tc_del_fdb_peers_flow(flow);\n \t}\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c\nindex 50bfb450c71e2f..abf72026c75133 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c\n@@ -194,8 +194,10 @@ static void mlx5_mpesw_work(struct work_struct *work)\n \tstruct mlx5_lag *ldev = mpesww-\u003elag;\n \n \tdevcom = mlx5_lag_get_devcom_comp(ldev);\n-\tif (!devcom)\n-\t\treturn;\n+\tif (!devcom) {\n+\t\tmpesww-\u003eresult = -ENODEV;\n+\t\tgoto complete;\n+\t}\n \n \tmlx5_devcom_comp_lock(devcom);\n \tmlx5_mpesw_sd_devcoms_lock(ldev);\n@@ -213,6 +215,7 @@ static void mlx5_mpesw_work(struct work_struct *work)\n \tmutex_unlock(\u0026ldev-\u003elock);\n \tmlx5_mpesw_sd_devcoms_unlock(ldev);\n \tmlx5_devcom_comp_unlock(devcom);\n+complete:\n \tcomplete(\u0026mpesww-\u003ecomp);\n }\n \ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c\nindex 113866494d164b..6b4ad3c53f2f33 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c\n@@ -78,7 +78,7 @@ static int mlx5_lag_create_single_fdb_filter(struct mlx5_lag *ldev, u32 filter)\n \t}\n \treturn 0;\n err:\n-\tmlx5_lag_for_each_reverse(j, i, 0, ldev, filter) {\n+\tmlx5_lag_for_each_reverse(j, i - 1, 0, ldev, filter) {\n \t\tstruct mlx5_eswitch *slave_esw;\n \n \t\tif (j == master_idx)\n"
} |
| 2/1 | 2026/06/30 18:11 | agent | patch-evaluator |
1mModel:gemini-3.1-pro-preview Args: null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch modifies the Mellanox mlx5 hardware driver, specifically deep logic related to TC flows, Link Aggregation (LAG), and Multi-Port E-Switch (MPESW). Since mlx5 requires physical Mellanox hardware and there is no software emulator for it in the kernel, these code paths are impossible to reach in standard virtualized environments like GCE or QEMU.",
"WorthFuzzing": false
}Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Do not list too generic configs (we already have them enabled). Only list those that specifically cover the modified code. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes:
commit ab2d89faaaf676b499462aae420787c43c40320f
Author: syz-cluster <triage@syzkaller.com>
Date: Tue Jun 30 18:11:17 2026 +0000
syz-cluster: applied patch under review
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index 910492eb51f276..1bc7b9019124a4 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -5547,6 +5547,9 @@ void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
mlx5_devcom_for_each_peer_entry(devcom, peer_esw, pos) {
i = mlx5_lag_get_dev_seq(peer_esw->dev);
+ if (i < 0)
+ continue;
+
list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows[i], peer[i])
mlx5e_tc_del_fdb_peers_flow(flow);
}
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c
index 50bfb450c71e2f..abf72026c75133 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c
@@ -194,8 +194,10 @@ static void mlx5_mpesw_work(struct work_struct *work)
struct mlx5_lag *ldev = mpesww->lag;
devcom = mlx5_lag_get_devcom_comp(ldev);
- if (!devcom)
- return;
+ if (!devcom) {
+ mpesww->result = -ENODEV;
+ goto complete;
+ }
mlx5_devcom_comp_lock(devcom);
mlx5_mpesw_sd_devcoms_lock(ldev);
@@ -213,6 +215,7 @@ static void mlx5_mpesw_work(struct work_struct *work)
mutex_unlock(&ldev->lock);
mlx5_mpesw_sd_devcoms_unlock(ldev);
mlx5_devcom_comp_unlock(devcom);
+complete:
complete(&mpesww->comp);
}
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c
index 113866494d164b..6b4ad3c53f2f33 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c
@@ -78,7 +78,7 @@ static int mlx5_lag_create_single_fdb_filter(struct mlx5_lag *ldev, u32 filter)
}
return 0;
err:
- mlx5_lag_for_each_reverse(j, i, 0, ldev, filter) {
+ mlx5_lag_for_each_reverse(j, i - 1, 0, ldev, filter) {
struct mlx5_eswitch *slave_esw;
if (j == master_idx)
|
| 3/2 | 2026/06/30 18:11 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 2638 output: 36 thoughts: 571 Thoughts: **Analyzing the Mellanox mlx5 Driver Patch for Fuzzing Potential** Okay, so I've got this patch that touches three files within the Mellanox mlx5 Ethernet driver: `en_tc.c`, `lag/mpesw.c`, and `lag/shared_fdb.c`. Let me quickly break down what this patch does, so I can start thinking about fuzzing it. It adds a check in `mlx5e_tc_clean_fdb_peer_flows`, a check and conditional jump in `mlx5_mpesw_work`, and modifies a loop in `mlx5_lag_create_single_fdb_filter`. Seems straightforward enough—functional changes. Now the question is, can I even fuzz this thing? Mellanox mlx5, that’s a hardware driver, right? Yeah, it's for Mellanox ConnectX network cards. So, I need to consider the environment. My immediate concern is whether this is going to be feasible in a standard virtualized setup, like GCE or QEMU. I need those cards, which aren't typically present unless you emulate them or pass them through. Are there any software emulators for mlx5 in the kernel? I am thinking, for example, of `netdevsim` or `mac80211_hwsim`. Let me check... nope, doesn't look like there is a dedicated mlx5 software emulator in the upstream kernel. Okay, so then the next thing I need to ask is: does syzkaller do anything with mlx5? Syzkaller is the go-to tool for kernel fuzzing, but it usually needs specific hardware or effective emulators. Well, it can fuzz PCI devices, if there is a PCI fuzzer, which is the class of hardware we are talking about here. But reaching these hardware-specific drivers without the hardware is a pain. I seem to recall that syzkaller has a vhci/PCI fuzzer of some kind, but is it actually effective for mlx5? I'll need to check if there are any configurations I can use. I wonder if it's even worth attempting to fuzz given that it is a PCI physical device driver with no software emulator. Let me think back on some previous experiences. I remember something about code paths being impossible to reach in virtualized environments, specifically in situations involving software-emulated hardware. Well, I am thinking that this applies here as mlx5 isn't reachable in standard virtualized environments. Maybe I should double-check. I will quickly search the kernel code for any evidence of mlx5 software emulation, just in case. |
| 4/2 | 2026/06/30 18:11 | tool | grepper |
0mArgs:{
"Expression": "mlx5",
"PathPrefix": "drivers/net/ethernet/mellanox/mlx5/"
}Results: {
"Output": "\nFull output is too long, showing 500 out of 99062 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig=19=config MLX5_FPGA\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-25-\t and an FPGA chip on one board. If you select this option, the\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig:26:\t mlx5_core driver will include the Innova FPGA core and allow building\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-27-\t sandbox-specific client drivers.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig=77=config MLX5_BRIDGE\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-81-\thelp\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig:82:\t mlx5 ConnectX offloads support for Ethernet Bridging (BRIDGE).\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-83-\t Enable offloading FDB rules from a bridge device containing\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig:84:\t representors of mlx5 uplink and VF ports. Supports VLANs (trunk and\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-85-\t access modes).\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig=87=config MLX5_CLS_ACT\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-91-\thelp\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig:92:\t mlx5 ConnectX offloads support for TC classifier action (NET_CLS_ACT),\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-93-\t works in both native NIC mode and Switchdev SRIOV mode.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig=210=config MLX5_EN_PSP\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-215-\thelp\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig:216:\t mlx5 device offload support for Google PSP Security Protocol offload.\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-217-\t Adds support for PSP encryption offload and for SPI and key generation\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile=7=subdir-ccflags-y += -I$(src)\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-8-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:9:obj-$(CONFIG_MLX5_CORE) += mlx5_core.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-10-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-11-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:12:# mlx5 core basic\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-13-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:14:mlx5_core-y :=\tmain.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-15-\t\thealth.o mcg.o cq.o alloc.o port.o mr.o pd.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-25-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:26:mlx5_core-$(CONFIG_MLX5_CORE_EN) += en/rqt.o en/tir.o en/rss.o en/rx_res.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-27-\t\ten/channels.o en_main.o en_common.o en_fs.o en_ethtool.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-37-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:38:mlx5_core-$(CONFIG_MLX5_EN_ARFS) += en_arfs.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:39:mlx5_core-$(CONFIG_MLX5_EN_RXNFC) += en_fs_ethtool.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:40:mlx5_core-$(CONFIG_MLX5_CORE_EN_DCB) += en_dcbnl.o en/port_buffer.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:41:mlx5_core-$(CONFIG_PCI_HYPERV_INTERFACE) += en/hv_vhca_stats.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:42:mlx5_core-$(CONFIG_MLX5_ESWITCH) += lag/mp.o lag/port_sel.o lib/geneve.o lib/port_tun.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-43-\t\t\t\t\ten_rep.o en/rep/bond.o en/mod_hdr.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-44-\t\t\t\t\ten/mapping.o lag/mpesw.o lag/shared_fdb.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:45:mlx5_core-$(CONFIG_MLX5_CLS_ACT) += en_tc.o en/rep/tc.o en/rep/neigh.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-46-\t\t\t\t\tlib/fs_chains.o en/tc_tun.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-52-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:53:mlx5_core-$(CONFIG_MLX5_CLS_ACT) += en/tc/act/act.o en/tc/act/drop.o en/tc/act/trap.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-54-\t\t\t\t\ten/tc/act/accept.o en/tc/act/mark.o en/tc/act/goto.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile=61=ifneq ($(CONFIG_MLX5_TC_CT),)\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:62:\tmlx5_core-y\t\t\t += en/tc_ct.o en/tc/ct_fs_dmfs.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:63:\tmlx5_core-$(CONFIG_MLX5_SW_STEERING) += en/tc/ct_fs_smfs.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:64:\tmlx5_core-$(CONFIG_MLX5_HW_STEERING) += en/tc/ct_fs_hmfs.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-65-endif\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-66-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:67:mlx5_core-$(CONFIG_MLX5_TC_SAMPLE) += en/tc/sample.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-68-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-71-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:72:mlx5_core-$(CONFIG_MLX5_ESWITCH) += eswitch.o eswitch_offloads.o eswitch_offloads_termtbl.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-73-\t\t\t\t ecpf.o rdma.o esw/legacy.o esw/adj_vport.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-75-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:76:mlx5_core-$(CONFIG_MLX5_ESWITCH) += esw/acl/helper.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-77-\t\t\t\t esw/acl/egress_lgcy.o esw/acl/egress_ofld.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile=80=ifneq ($(CONFIG_MLX5_EN_IPSEC),)\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:81:\tmlx5_core-$(CONFIG_MLX5_ESWITCH) += esw/ipsec_fs.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-82-endif\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-83-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:84:mlx5_core-$(CONFIG_MLX5_BRIDGE) += esw/bridge.o esw/bridge_mcast.o esw/bridge_debugfs.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-85-\t\t\t\t en/rep/bridge.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-86-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:87:mlx5_core-$(CONFIG_HWMON) += hwmon.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:88:mlx5_core-$(CONFIG_MLX5_MPFS) += lib/mpfs.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-89-ifneq ($(CONFIG_VXLAN),)\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:90:\tmlx5_core-y\t\t += lib/vxlan.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-91-endif\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:92:mlx5_core-$(CONFIG_PTP_1588_CLOCK) += lib/clock.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:93:mlx5_core-$(CONFIG_PCI_HYPERV_INTERFACE) += lib/hv.o lib/hv_vhca.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-94-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-97-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:98:mlx5_core-$(CONFIG_MLX5_CORE_IPOIB) += ipoib/ipoib.o ipoib/ethtool.o ipoib/ipoib_vlan.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-99-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-102-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:103:mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-104-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:105:mlx5_core-$(CONFIG_MLX5_MACSEC) += en_accel/macsec.o lib/macsec_fs.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-106-\t\t\t\t en_accel/macsec_stats.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-107-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:108:mlx5_core-$(CONFIG_MLX5_EN_IPSEC) += en_accel/ipsec.o en_accel/ipsec_rxtx.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-109-\t\t\t\t en_accel/ipsec_stats.o en_accel/ipsec_fs.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-111-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:112:mlx5_core-$(CONFIG_MLX5_EN_TLS) += en_accel/ktls_stats.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-113-\t\t\t\t en_accel/fs_tcp.o en_accel/ktls.o en_accel/ktls_txrx.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-115-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:116:mlx5_core-$(CONFIG_MLX5_EN_PSP) += en_accel/psp.o en_accel/psp_rxtx.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-117-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-120-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:121:mlx5_core-$(CONFIG_MLX5_SW_STEERING) += steering/sws/dr_domain.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-122-\t\t\t\t\tsteering/sws/dr_table.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-145-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:146:mlx5_core-$(CONFIG_MLX5_HW_STEERING) += steering/hws/cmd.o \\\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-147-\t\t\t\t\tsteering/hws/context.o \\\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-167-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:168:mlx5_core-$(CONFIG_MLX5_SF) += sf/vhca_event.o sf/dev/dev.o sf/dev/driver.o irq_affinity.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-169-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-172-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:173:mlx5_core-$(CONFIG_MLX5_SF_MANAGER) += sf/cmd.o sf/hw_table.o sf/devlink.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-174-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-177-#\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:178:mlx5_core-$(CONFIG_PCIE_TPH) += lib/st.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile-179-\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:180:obj-$(CONFIG_MLX5_DPLL) += mlx5_dpll.o\ndrivers/net/ethernet/mellanox/mlx5/core/Makefile:181:mlx5_dpll-y :=\tdpll.o\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-42-#include \u003clinux/seq_file.h\u003e\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:43:#include \u003clinux/mlx5/driver.h\u003e\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-44-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:45:#include \"mlx5_core.h\"\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-46-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-50-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:51:struct mlx5_db_pgdir {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-52-\tstruct list_head\tlist;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-57-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:58:struct mlx5_dma_pool {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-59-\t/* Protects page_list and per-page allocation bitmaps. */\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-61-\tstruct list_head page_list;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:62:\tstruct mlx5_core_dev *dev;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-63-\tint node;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-66-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:67:struct mlx5_dma_pool_page {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:68:\tstruct mlx5_dma_pool *pool;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-69-\tstruct list_head pool_link;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-74-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:75:struct mlx5_frag_buf_node_pools {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:76:\tstruct mlx5_dma_pool *pools[MLX5_FRAG_BUF_POOLS_NUM];\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-77-};\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-78-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:79:struct mlx5_dma_pool_stats {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-80-\tint node;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-89-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:90:static void *mlx5_dma_zalloc_coherent_node(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-91-\t\t\t\t\t size_t size, dma_addr_t *dma_handle,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-93-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:94:\tstruct device *device = mlx5_core_dma_dev(dev);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:95:\tstruct mlx5_priv *priv = \u0026dev-\u003epriv;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-96-\tint original_node;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-108-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:109:static void mlx5_dma_pool_destroy(struct mlx5_dma_pool *pool)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-110-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-114-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:115:static struct mlx5_dma_pool *mlx5_dma_pool_create(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-116-\t\t\t\t\t\t int node, u8 block_shift)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-117-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:118:\tstruct mlx5_dma_pool *pool;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-119-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-131-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:132:static struct mlx5_dma_pool_page *\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:133:mlx5_dma_pool_page_alloc(struct mlx5_dma_pool *pool)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-134-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-135-\tint blocks_per_page = BIT(PAGE_SHIFT - pool-\u003eblock_shift);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:136:\tstruct mlx5_dma_pool_page *page;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-137-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-147-\tbitmap_fill(page-\u003ebitmap, blocks_per_page);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:148:\tpage-\u003ebuf = mlx5_dma_zalloc_coherent_node(pool-\u003edev, PAGE_SIZE,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-149-\t\t\t\t\t\t \u0026page-\u003edma, pool-\u003enode);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-162-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:163:static void mlx5_dma_pool_page_free(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:164:\t\t\t\t struct mlx5_dma_pool_page *page)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-165-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:166:\tdma_free_coherent(mlx5_core_dma_dev(dev), PAGE_SIZE, page-\u003ebuf,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-167-\t\t\t page-\u003edma);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-171-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:172:static int mlx5_dma_pool_alloc_from_page(struct mlx5_dma_pool *pool,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:173:\t\t\t\t\t struct mlx5_dma_pool_page *page,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-174-\t\t\t\t\t unsigned long *idx_out)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-189-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:190:static struct mlx5_dma_pool_page *\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:191:mlx5_dma_pool_alloc(struct mlx5_dma_pool *pool, unsigned long *idx_out)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-192-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:193:\tstruct mlx5_dma_pool_page *page;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-194-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-197-\tpage = list_first_entry_or_null(\u0026pool-\u003epage_list,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:198:\t\t\t\t\tstruct mlx5_dma_pool_page, pool_link);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:199:\tif (page \u0026\u0026 !mlx5_dma_pool_alloc_from_page(pool, page, idx_out))\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-200-\t\tgoto unlock; /* successfully allocated from existing page */\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-201-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:202:\tpage = mlx5_dma_pool_page_alloc(pool);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-203-\tif (!page)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-206-\tlist_add(\u0026page-\u003epool_link, \u0026pool-\u003epage_list);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:207:\tmlx5_dma_pool_alloc_from_page(pool, page, idx_out);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-208-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-213-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:214:static void mlx5_dma_pool_free(struct mlx5_dma_pool *pool,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:215:\t\t\t struct mlx5_dma_pool_page *page,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-216-\t\t\t unsigned long idx)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-226-\t\tlist_del(\u0026page-\u003epool_link);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:227:\t\tmlx5_dma_pool_page_free(pool-\u003edev, page);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-228-\t} else {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-236-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:237:static void mlx5_dma_pool_debugfs_get_stats(struct mlx5_dma_pool *pool,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:238:\t\t\t\t\t struct mlx5_dma_pool_stats *stats)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-239-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-240-\tint blocks_per_page = BIT(PAGE_SHIFT - pool-\u003eblock_shift);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:241:\tstruct mlx5_dma_pool_page *page;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-242-\tsize_t free_blocks = 0;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-257-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:258:static void mlx5_dma_pool_debugfs_stats_print(struct seq_file *file,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:259:\t\t\t\t\t struct mlx5_dma_pool *pool)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-260-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:261:\tstruct mlx5_dma_pool_stats stats = {};\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-262-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:263:\tmlx5_dma_pool_debugfs_get_stats(pool, \u0026stats);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-264-\tseq_printf(file, \"%4d %5zu %7zu %7zu\\n\",\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-268-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:269:static void mlx5_dma_pools_debugfs_print_header(struct seq_file *file)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-270-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=274=static void\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:275:mlx5_frag_buf_node_pools_destroy(struct mlx5_frag_buf_node_pools *node_pools)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-276-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-278-\t\tif (node_pools-\u003epools[i])\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:279:\t\t\tmlx5_dma_pool_destroy(node_pools-\u003epools[i]);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-280-\tkfree(node_pools);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-282-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:283:static struct mlx5_frag_buf_node_pools *\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:284:mlx5_frag_buf_node_pools_create(struct mlx5_core_dev *dev, int node)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-285-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:286:\tstruct mlx5_frag_buf_node_pools *node_pools;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-287-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-294-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:295:\t\tnode_pools-\u003epools[i] = mlx5_dma_pool_create(dev, node,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-296-\t\t\t\t\t\t\t block_shift);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-297-\t\tif (!node_pools-\u003epools[i]) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:298:\t\t\tmlx5_frag_buf_node_pools_destroy(node_pools);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-299-\t\t\treturn NULL;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=306=static int\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:307:mlx5_frag_buf_dma_pools_debugfs_show(struct seq_file *file, void *priv)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-308-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:309:\tstruct mlx5_core_dev *dev = file-\u003eprivate;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-310-\tint node;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-311-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:312:\tmlx5_dma_pools_debugfs_print_header(file);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-313-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-317-\tfor_each_node_state(node, N_POSSIBLE) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:318:\t\tstruct mlx5_frag_buf_node_pools *node_pools;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-319-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-324-\t\tfor (int i = 0; i \u003c MLX5_FRAG_BUF_POOLS_NUM; i++) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:325:\t\t\tstruct mlx5_dma_pool *pool = node_pools-\u003epools[i];\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-326-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-329-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:330:\t\t\tmlx5_dma_pool_debugfs_stats_print(file, pool);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-331-\t\t}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-335-}\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:336:DEFINE_SHOW_ATTRIBUTE(mlx5_frag_buf_dma_pools_debugfs);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-337-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:338:void mlx5_frag_buf_pools_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-339-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:340:\tstruct mlx5_priv *priv = \u0026dev-\u003epriv;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-341-\tint node;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-346-\tfor_each_node_state(node, N_POSSIBLE) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:347:\t\tstruct mlx5_frag_buf_node_pools *node_pools;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-348-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-351-\t\t\tcontinue;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:352:\t\tmlx5_frag_buf_node_pools_destroy(node_pools);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-353-\t}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-358-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:359:int mlx5_frag_buf_pools_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-360-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:361:\tstruct mlx5_priv *priv = \u0026dev-\u003epriv;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-362-\tint node;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-369-\tfor_each_node_state(node, N_POSSIBLE) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:370:\t\tstruct mlx5_frag_buf_node_pools *node_pools;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-371-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:372:\t\tnode_pools = mlx5_frag_buf_node_pools_create(dev, node);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-373-\t\tif (!node_pools) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:374:\t\t\tmlx5_frag_buf_pools_cleanup(dev);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-375-\t\t\treturn -ENOMEM;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-382-\t\t\t\t priv-\u003edbg.dbg_root, dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:383:\t\t\t\t \u0026mlx5_frag_buf_dma_pools_debugfs_fops);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-384-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-387-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:388:int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:389:\t\t\t struct mlx5_frag_buf *buf, int node)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-390-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:391:\tstruct mlx5_dma_pool *pool;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-392-\tint pool_idx;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-408-\tfor (int i = 0; i \u003c buf-\u003enpages; i++) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:409:\t\tstruct mlx5_buf_list *frag = \u0026buf-\u003efrags[i];\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:410:\t\tstruct mlx5_dma_pool_page *page;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-411-\t\tunsigned long idx;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-412-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:413:\t\tpage = mlx5_dma_pool_alloc(pool, \u0026idx);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-414-\t\tif (!page) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:415:\t\t\tmlx5_frag_buf_free(dev, buf);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-416-\t\t\treturn -ENOMEM;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-424-}\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:425:EXPORT_SYMBOL_GPL(mlx5_frag_buf_alloc_node);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-426-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:427:void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-428-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-429-\tfor (int i = 0; i \u003c buf-\u003enpages; i++) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:430:\t\tstruct mlx5_buf_list *frag = \u0026buf-\u003efrags[i];\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:431:\t\tstruct mlx5_dma_pool_page *page;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:432:\t\tstruct mlx5_dma_pool *pool;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-433-\t\tunsigned long idx;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-440-\t\tidx = (frag-\u003emap - page-\u003edma) \u003e\u003e pool-\u003eblock_shift;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:441:\t\tmlx5_dma_pool_free(pool, page, idx);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-442-\t}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-444-}\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:445:EXPORT_SYMBOL_GPL(mlx5_frag_buf_free);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-446-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:447:static struct mlx5_db_pgdir *mlx5_alloc_db_pgdir(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-448-\t\t\t\t\t\t int node)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-450-\tu32 db_per_page = PAGE_SIZE / cache_line_size();\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:451:\tstruct mlx5_db_pgdir *pgdir;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-452-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-464-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:465:\tpgdir-\u003edb_page = mlx5_dma_zalloc_coherent_node(dev, PAGE_SIZE,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-466-\t\t\t\t\t\t \u0026pgdir-\u003edb_dma, node);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-475-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:476:static int mlx5_alloc_db_from_pgdir(struct mlx5_db_pgdir *pgdir,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:477:\t\t\t\t struct mlx5_db *db)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-478-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-500-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:501:int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, int node)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-502-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:503:\tstruct mlx5_db_pgdir *pgdir;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-504-\tint ret = 0;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-508-\tlist_for_each_entry(pgdir, \u0026dev-\u003epriv.pgdir_list, list)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:509:\t\tif (!mlx5_alloc_db_from_pgdir(pgdir, db))\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-510-\t\t\tgoto out;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-511-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:512:\tpgdir = mlx5_alloc_db_pgdir(dev, node);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-513-\tif (!pgdir) {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-520-\t/* This should never fail -- we just allocated an empty page: */\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:521:\tWARN_ON(mlx5_alloc_db_from_pgdir(pgdir, db));\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-522-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-527-}\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:528:EXPORT_SYMBOL_GPL(mlx5_db_alloc_node);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-529-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:530:void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-531-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-538-\tif (bitmap_full(db-\u003eu.pgdir-\u003ebitmap, db_per_page)) {\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:539:\t\tdma_free_coherent(mlx5_core_dma_dev(dev), PAGE_SIZE,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-540-\t\t\t\t db-\u003eu.pgdir-\u003edb_page, db-\u003eu.pgdir-\u003edb_dma);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-547-}\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:548:EXPORT_SYMBOL_GPL(mlx5_db_free);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-549-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:550:void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-551-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-557-}\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:558:EXPORT_SYMBOL_GPL(mlx5_fill_page_frag_array_perm);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-559-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:560:void mlx5_fill_page_frag_array(struct mlx5_frag_buf *buf, __be64 *pas)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-561-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:562:\tmlx5_fill_page_frag_array_perm(buf, pas, 0);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-563-}\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:564:EXPORT_SYMBOL_GPL(mlx5_fill_page_frag_array);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-39-#include \u003clinux/random.h\u003e\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:40:#include \u003clinux/mlx5/driver.h\u003e\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:41:#include \u003clinux/mlx5/eq.h\u003e\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-42-#include \u003clinux/debugfs.h\u003e\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-43-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:44:#include \"mlx5_core.h\"\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-45-#include \"lib/eq.h\"\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-49-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:50:struct mlx5_ifc_mbox_out_bits {\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-51-\tu8 status[0x8];\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-58-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:59:struct mlx5_ifc_mbox_in_bits {\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-60-\tu8 opcode[0x10];\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=97=static u16 in_to_uid(void *in)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-104- */\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:105:static bool mlx5_cmd_is_throttle_opcode(u16 op)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-106-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-117-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:118:static struct mlx5_cmd_work_ent *\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:119:cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:120:\t struct mlx5_cmd_msg *out, void *uout, int uout_size,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:121:\t mlx5_cmd_cbk_t cbk, void *context, int page_queue)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-122-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-123-\tgfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:124:\tstruct mlx5_cmd_work_ent *ent;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-125-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-144-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:145:static void cmd_free_ent(struct mlx5_cmd_work_ent *ent)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-146-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-149-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:150:static u8 alloc_token(struct mlx5_cmd *cmd)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-151-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-163-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:164:static int cmd_alloc_index(struct mlx5_cmd *cmd, struct mlx5_cmd_work_ent *ent)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-165-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-180-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:181:static void cmd_free_index(struct mlx5_cmd *cmd, int idx)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-182-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-187-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:188:static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-189-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-192-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:193:static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-194-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:195:\tstruct mlx5_cmd *cmd = ent-\u003ecmd;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-196-\tunsigned long flags;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-212-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:213:static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-214-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-217-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:218:static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-219-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=226=static u8 xor8_buf(void *buf, size_t offset, int len)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-238-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:239:static int verify_block_sig(struct mlx5_cmd_prot_block *block)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-240-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:241:\tsize_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-242-\tint xor_len = sizeof(*block) - sizeof(block-\u003edata) - 1;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-252-\n\n"
} |
| 5/2 | 2026/06/30 18:11 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 18818 output: 50 thoughts: 730 Thoughts: **Analyzing Reachability of Mellanox mlx5 Code in a Virtualized Environment** Alright, let's break this down. I need to determine if these modified Mellanox mlx5 files are reachable within a virtualized environment, specifically considering GCE or QEMU. The files in question are `en_tc.c`, `mpesw.c`, and `shared_fdb.c`. The fact that syzkaller is involved immediately piques my interest. Syzkaller is a powerful fuzzer, and the prompt explicitly highlights cases of "impossible to reach" code paths in virtualized environments. Initially, I'd assume Mellanox mlx5 is typically a physical device. However, the presence of syzkaller changes everything. I know syzkaller has a cluster and that it's applying a patch. This strongly suggests that syzkaller is successfully fuzzing mlx5, possibly through its PCI fuzzer. That's the crucial question: can syzkaller's PCI fuzzer reach deep enough into the mlx5 driver to trigger code paths in these modified files? The prompt's exclusion of "software-emulated hardware" is key. The prompt wants to exclude code that is inaccessible in GCE or QEMU even when software-emulated hardware like usb gadget or mac80211_hwsim is used. Does the PCI fuzzer qualify? Well, syzkaller does run on GCE/QEMU, and there's a strong indication that it *can* reach mlx5. The author of the patch is listed as "syz-cluster", which means syzkaller did find a bug and is testing the patch! If syzkaller is testing a patch against these files, it's clear they've found a way to trigger code in mlx5 within a virtualized environment. The PCI fuzzer is the likely culprit. I recall that syzkaller enables numerous drivers for its PCI fuzzer, suggesting that it's designed to interact with a broad range of PCI devices. Now, the nuances of emulation are critical. Does syzkaller actually *emulate* mlx5, or does it simply provide random responses to MMIO reads/writes, allowing it to pass the probe and get into the driver? It's the latter, isn't it? The prompt is trying to exclude true emulation, so I need to check the exact function that the patch modifies. Let's look at the functions themselves: `mlx5e_tc_clean_fdb_peer_flows`, `mlx5_mpesw_work`, and `mlx5_lag_create_single_fdb_filter`. Given the PCI fuzzer's approach, even though it doesn't do a full emulation, it probably means that `WorthFuzzing` should be `true`! The PCI fuzzer *is* able to pass probe, and is able to reach some code paths that are modified, and can probably trigger some interesting scenarios. |
| 6/2 | 2026/06/30 18:11 | tool | grepper |
0mArgs:{
"Expression": "mlx5e_tc_clean_fdb_peer_flows",
"PathPrefix": "drivers/net/ethernet/mellanox/mlx5/core/"
}Results: {
"Output": "drivers/net/ethernet/mellanox/mlx5/core/en_tc.c=5531=int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_tc.c-5537-\ndrivers/net/ethernet/mellanox/mlx5/core/en_tc.c:5538:void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)\ndrivers/net/ethernet/mellanox/mlx5/core/en_tc.c-5539-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch.h=744=static inline bool mlx5_esw_is_fdb_created(struct mlx5_eswitch *esw)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch.h-749-/* TODO: This mlx5e_tc function shouldn't be called by eswitch */\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch.h:750:void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch.h-751-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c=3379=static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c-3382-#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c:3383:\tmlx5e_tc_clean_fdb_peer_flows(esw);\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c-3384-#endif\n"
} |
| 7/2 | 2026/06/30 18:11 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 20790 output: 44 thoughts: 48 Thoughts: Here's my analysis of the provided information, as if these were my internal thoughts: **Dissecting the Flow Control Functionality** Okay, so I see that `mlx5e_tc_clean_fdb_peer_flows` is triggered by `mlx5_esw_offloads_unpair`. That's a key connection right there. I need to understand what this means in terms of offload management and how flows are cleaned up when something is unpaired. The dependency suggests this `mlx5e_tc_clean_fdb_peer_flows` is crucial for the overall lifecycle of these offloaded flows. Now, let me shift gears and go digging into `mlx5_mpesw_work`. I have a feeling this is where things will start to become clearer, especially the actual job or operation performed by the function mentioned previously. This probably ties directly into how the offloads and their associated flows are managed. Let's see if this function's logic gives any more insights on flow de-allocation. |
| 8/2 | 2026/06/30 18:11 | tool | grepper |
0mArgs:{
"Expression": "mlx5_mpesw_work",
"PathPrefix": "drivers/net/ethernet/mellanox/mlx5/core/"
}Results: {
"Output": "drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c=178=void mlx5_mpesw_sd_devcoms_unlock(struct mlx5_lag *ldev)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c-189-\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c:190:static void mlx5_mpesw_work(struct work_struct *work)\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c-191-{\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c:192:\tstruct mlx5_mpesw_work_st *mpesww = container_of(work, struct mlx5_mpesw_work_st, work);\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c-193-\tstruct mlx5_devcom_comp_dev *devcom;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c=222=static int mlx5_lag_mpesw_queue_work(struct mlx5_core_dev *dev,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c-225-\tstruct mlx5_lag *ldev = mlx5_lag_dev(dev);\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c:226:\tstruct mlx5_mpesw_work_st *work;\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c-227-\tint err = 0;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c-235-\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c:236:\tINIT_WORK(\u0026work-\u003ework, mlx5_mpesw_work);\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c-237-\tinit_completion(\u0026work-\u003ecomp);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h=15=enum mpesw_op {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h-19-\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h:20:struct mlx5_mpesw_work_st {\ndrivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h-21-\tstruct work_struct work;\n"
} |
| 9/2 | 2026/06/30 18:11 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 21841 output: 49 thoughts: 19 Thoughts: Here's a summary of my thought process, as requested: **Diving into `mlx5_lag_create_single_fdb_filter`** Okay, time to dig into `mlx5_lag_create_single_fdb_filter`. Given my experience with MLX5 and LAG configurations, I'm already anticipating some of the intricacies involved. I'm expecting this function to handle the creation of a Forwarding Database (FDB) filter specifically for a single destination MAC address within a Link Aggregation Group (LAG). This implies it needs to interact with the underlying hardware, likely programming some registers within the MLX5 NIC to ensure packets destined for that MAC are correctly forwarded across the aggregated links. I'll be looking for how it handles things like the LAG ID, the specific MAC address filter, the port or ports associated with the LAG, and the associated VLAN or other encapsulation parameters if applicable. I'll pay close attention to the error handling within the function. Does it check for resource exhaustion, invalid parameters, or hardware failures? How robust is it? I also want to see how it interacts with the broader FDB management system. Does it call other functions to update the FDB table, or does it directly write the necessary information to the relevant hardware structures? Understanding the internal function dependencies will be key to understanding the overall FDB management flow. Any potential race conditions or locking mechanisms used to protect the FDB will be on my radar too. I hope the code is well-commented; that will save me a ton of time. Let's get to it! |
| 10/2 | 2026/06/30 18:11 | tool | grepper |
0mArgs:{
"Expression": "mlx5_lag_create_single_fdb_filter",
"PathPrefix": "drivers/net/ethernet/mellanox/mlx5/core/"
}Results: {
"Output": "drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c=45=bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c-50-\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c:51:static int mlx5_lag_create_single_fdb_filter(struct mlx5_lag *ldev, u32 filter)\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c-52-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c=184=int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev)\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c-185-{\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c:186:\treturn mlx5_lag_create_single_fdb_filter(ldev, MLX5_LAG_FILTER_ALL);\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c-187-}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c=209=int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c-237-\t} else {\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c:238:\t\terr = mlx5_lag_create_single_fdb_filter(ldev, group_id);\ndrivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c-239-\t\tif (err) {\n"
} |
| 11/2 | 2026/06/30 18:11 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 22786 output: 37 thoughts: 419 Thoughts: **My Assessment of mlx5 Reachability in Virtualized Environments** Okay, so the prompt says to return `WorthFuzzing=false` if the patch targets unreachable code in virtualized environments. My immediate thought is, "Can mlx5 even *be* reached in GCE or QEMU?" If syzkaller found a bug related to it, then the answer must be yes, but I need to understand *how*. Syzkaller can emulate PCI devices using `syz_pci_ep` or `syz_pci_ep_write`, which means it’s providing a fake PCI config space and MMIO regions. Now, if the driver doesn't require really complex hardware handshakes that fail instantly, it might actually hit some code. The key question is whether mlx5 has such initialization requirements. Mellanox mlx5 drivers rely on firmware commands through command queues for initialization, which is a bit involved. If the PCI fuzzer is just throwing random data at the MMIO regions, the driver might fail to initialize – or, in a lucky guess, it might succeed if the right "responses" are provided, or if the driver simply doesn't check. Syzkaller does have a dedicated `syz_pci_ep` fuzzer, but it's generally not very deep unless there's an explicit emulator for the specific device. I know there's a `netdevsim` driver, but it’s not mlx5. So, does syzkaller have *any* way to test mlx5? I need to check for any software emulation. I should search for "mlx5" in the `tools/testing/selftests/` and `drivers/net/ethernet/mellanox/mlx5/core/` directories, to see if there's a mock or other form of emulation. That should give me the answer. |
| 12/2 | 2026/06/30 18:12 | tool | grepper |
0mError:no matches Args: {
"Expression": "mock",
"PathPrefix": "drivers/net/ethernet/mellanox/mlx5/core/"
}Results: {
"error": "no matches"
} |
| 13/2 | 2026/06/30 18:12 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 23661 output: 37 thoughts: 21 Thoughts: Okay, here's my summary, tailored as if I'm thinking it: **Checking for Simulation Environments for mlx5** Alright, let's get down to brass tacks. I need to figure out if there are any readily available simulation environments for the `mlx5` hardware. Specifically, I need to know if there's anything like a `hwsim` setup or a more general `sim` environment that I can leverage. Knowing these will save a huge amount of development time, if they exist. It would allow me to test and experiment without relying on the physical hardware for every minor iteration. Let's see what's out there. |
| 14/2 | 2026/06/30 18:12 | tool | grepper |
0mArgs:{
"Expression": "sim",
"PathPrefix": "drivers/net/ethernet/mellanox/mlx5/core/"
}Results: {
"Output": "drivers/net/ethernet/mellanox/mlx5/core/Kconfig=185=config MLX5_SF\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-190-\tdevice can support RDMA, netdevice and vdpa device.\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig:191:\tIt is similar to a SRIOV VF but it doesn't require SRIOV support.\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-192-\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig=193=config MLX5_SF_MANAGER\n--\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-199-\tport is managed through devlink. A subfunction supports RDMA, netdevice\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig:200:\tand vdpa device. It is similar to a SRIOV VF but it doesn't require\ndrivers/net/ethernet/mellanox/mlx5/core/Kconfig-201-\tSRIOV support.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1144=static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1151-\t/* Re-wait on the ent-\u003edone after executing the recovery flow. If the\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1152:\t * recovery flow (or any other recovery flow running simultaneously)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1153-\t * has recovered an EQE, it should cause the entry to be completed by\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1364=static const struct file_operations fops = {\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1365-\t.owner\t= THIS_MODULE,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1366:\t.open\t= simple_open,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1367-\t.write\t= dbg_write,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1550=static ssize_t data_read(struct file *filp, char __user *buf, size_t count,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1558-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1559:\treturn simple_read_from_buffer(buf, count, pos, dbg-\u003eout_msg,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1560-\t\t\t\t dbg-\u003eoutlen);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1563=static const struct file_operations dfops = {\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1564-\t.owner\t= THIS_MODULE,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1565:\t.open\t= simple_open,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1566-\t.write\t= data_write,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1570=static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1581-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1582:\treturn simple_read_from_buffer(buf, count, pos, outlen, err);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1583-}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1621=static const struct file_operations olfops = {\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1622-\t.owner\t= THIS_MODULE,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1623:\t.open\t= simple_open,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1624-\t.write\t= outlen_write,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=129=static ssize_t average_read(struct file *filp, char __user *buf, size_t count,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-142-\tret = snprintf(tbuf, sizeof(tbuf), \"%llu\\n\", field);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:143:\treturn simple_read_from_buffer(buf, count, pos, tbuf, ret);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-144-}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=167=static const struct file_operations reset_fops = {\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-168-\t.owner\t= THIS_MODULE,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:169:\t.open\t= simple_open,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-170-\t.write\t= reset_write,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=173=static const struct file_operations average_fops = {\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-174-\t.owner\t= THIS_MODULE,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:175:\t.open\t= simple_open,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-176-\t.read\t= average_read,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=179=static ssize_t slots_read(struct file *filp, char __user *buf, size_t count,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-191-\tret = snprintf(tbuf, sizeof(tbuf), \"%d\\n\", field);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:192:\treturn simple_read_from_buffer(buf, count, pos, tbuf, ret);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-193-}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=195=static const struct file_operations slots_fops = {\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-196-\t.owner\t= THIS_MODULE,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:197:\t.open\t= simple_open,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-198-\t.read\t= slots_read,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=494=static ssize_t dbg_read(struct file *filp, char __user *buf, size_t count,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-528-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:529:\treturn simple_read_from_buffer(buf, count, pos, tbuf, ret);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-530-}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=532=static const struct file_operations fops = {\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-533-\t.owner\t= THIS_MODULE,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:534:\t.open\t= simple_open,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-535-\t.read\t= dbg_read,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en.h=536=struct mlx5e_icosq {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en.h-556-\t * (NAPI softirq or process/workqueue). Always use spin_lock_bh for\ndrivers/net/ethernet/mellanox/mlx5/core/en.h:557:\t * simplicity and correctness across all contexts.\ndrivers/net/ethernet/mellanox/mlx5/core/en.h-558-\t */\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en.h=881=struct mlx5e_xsk {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en.h-895- * must not fail. Use with care and make sure the same variable is not used\ndrivers/net/ethernet/mellanox/mlx5/core/en.h:896: * simultaneously by multiple users.\ndrivers/net/ethernet/mellanox/mlx5/core/en.h-897- */\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/params.c=497=u32 mlx5e_mpwrq_max_page_size(struct mlx5_core_dev *mdev)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/params.c-502-\t/* Two MTTs are needed to form an octword. Driver is using a\ndrivers/net/ethernet/mellanox/mlx5/core/en/params.c:503:\t * single page per MTT for simplicity. Hence the limit of having\ndrivers/net/ethernet/mellanox/mlx5/core/en/params.c-504-\t * at least 2 pages per WQE.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c=247=int mlx5e_rep_setup_tc(struct net_device *dev, enum tc_setup_type type,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c-256-\tcase TC_SETUP_BLOCK:\ndrivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c:257:\t\treturn flow_block_cb_setup_simple(type_data,\ndrivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c-258-\t\t\t\t\t\t \u0026mlx5e_rep_block_tc_cb_list,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c-261-\tcase TC_SETUP_FT:\ndrivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c:262:\t\treturn flow_block_cb_setup_simple(type_data,\ndrivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c-263-\t\t\t\t\t\t \u0026mlx5e_rep_block_ft_cb_list,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c=64=static int mlx5e_tc_tun_init_encap_attr_geneve(struct net_device *tunnel_dev,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c-70-\ndrivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c:71:\t/* Reformat type for GENEVE encap is similar to VXLAN:\ndrivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c-72-\t * in both cases the HW adds in the same place a\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/xdp.c=203=enum mlx5_rss_hash_type {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/xdp.c-223-\ndrivers/net/ethernet/mellanox/mlx5/core/en/xdp.c:224:/* Invalid combinations will simply return zero, allows no boundary checks */\ndrivers/net/ethernet/mellanox/mlx5/core/en/xdp.c-225-static const enum xdp_rss_hash_type mlx5_xdp_rss_type[RSS_TYPE_MAX_TABLE] = {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c=3978=static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c-3981-\t/* MQPRIO is another toplevel qdisc that can't be attached\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c:3982:\t * simultaneously with the offloaded HTB.\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c-3983-\t */\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c=4002=static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c-4020-\t\tf-\u003eunlocked_driver_cb = true;\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c:4021:\t\treturn flow_block_cb_setup_simple(type_data,\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c-4022-\t\t\t\t\t\t \u0026mlx5e_block_cb_list,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c=5536=static void mlx5e_get_base_stats(struct net_device *dev,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c-5624-\t * - been shutdown and set to NULL, or\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c:5625:\t * - simply disabled (bit unset)\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c-5626-\t *\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c=5758=static int mlx5e_queue_stop(struct net_device *dev, void *oldq, int queue_index)\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c-5759-{\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c:5760:\t/* In mlx5 a txq cannot be simply stopped in isolation, only restarted.\ndrivers/net/ethernet/mellanox/mlx5/core/en_main.c-5761-\t * mlx5e_queue_start does not fail, we stop the old queue there.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_rx.c=1365=static inline void mlx5e_handle_csum(struct net_device *netdev,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en_rx.c-1393-\t * Detecting these padded frames requires to verify and parse\ndrivers/net/ethernet/mellanox/mlx5/core/en_rx.c:1394:\t * IP headers, so we simply force all those small frames to be\ndrivers/net/ethernet/mellanox/mlx5/core/en_rx.c-1395-\t * CHECKSUM_UNNECESSARY even if they are not padded.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c=86=mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c-104-/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c:105: * are not needed as well in the following process. So clear them all for simplicity.\ndrivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c-106- */\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lib/crypto.c=454=static int mlx5_crypto_dek_pool_push(struct mlx5_crypto_dek_pool *pool,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lib/crypto.c-476- * hweight_long(need_sync XOR in_use), and the need_sync bits can be reset\ndrivers/net/ethernet/mellanox/mlx5/core/lib/crypto.c:477: * by simply copying from in_use bits.\ndrivers/net/ethernet/mellanox/mlx5/core/lib/crypto.c-478- */\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lib/sd.c=755=static ssize_t dev_read(struct file *filp, char __user *buf, size_t count,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lib/sd.c-765-\ndrivers/net/ethernet/mellanox/mlx5/core/lib/sd.c:766:\treturn simple_read_from_buffer(buf, count, pos, tbuf, ret);\ndrivers/net/ethernet/mellanox/mlx5/core/lib/sd.c-767-}\n--\ndrivers/net/ethernet/mellanox/mlx5/core/lib/sd.c=769=static const struct file_operations dev_fops = {\ndrivers/net/ethernet/mellanox/mlx5/core/lib/sd.c-770-\t.owner\t= THIS_MODULE,\ndrivers/net/ethernet/mellanox/mlx5/core/lib/sd.c:771:\t.open\t= simple_open,\ndrivers/net/ethernet/mellanox/mlx5/core/lib/sd.c-772-\t.read\t= dev_read,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=68=static int\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:69:hws_bwc_matcher_move_all_simple(struct mlx5hws_bwc_matcher *bwc_matcher)\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-70-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=166=static int hws_bwc_matcher_move_all(struct mlx5hws_bwc_matcher *bwc_matcher)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-169-\tcase MLX5HWS_BWC_MATCHER_SIMPLE:\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:170:\t\treturn hws_bwc_matcher_move_all_simple(bwc_matcher);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-171-\tcase MLX5HWS_BWC_MATCHER_COMPLEX_FIRST:\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=180=static int hws_bwc_matcher_move(struct mlx5hws_bwc_matcher *bwc_matcher)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-225-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:226:int mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bwc_matcher *bwc_matcher,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-227-\t\t\t\t struct mlx5hws_table *table,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=320=mlx5hws_bwc_matcher_create(struct mlx5hws_table *table,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-352-\telse\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:353:\t\tret = mlx5hws_bwc_matcher_create_simple(bwc_matcher,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-354-\t\t\t\t\t\t\ttable,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-369-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:370:int mlx5hws_bwc_matcher_destroy_simple(struct mlx5hws_bwc_matcher *bwc_matcher)\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-371-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=387=int mlx5hws_bwc_matcher_destroy(struct mlx5hws_bwc_matcher *bwc_matcher)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-399-\telse\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:400:\t\tmlx5hws_bwc_matcher_destroy_simple(bwc_matcher);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-401-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=608=static int hws_bwc_rule_cnt_dec_with_shrink(struct mlx5hws_bwc_rule *bwc_rule,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-640-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:641:int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_rule *bwc_rule)\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-642-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=665=int mlx5hws_bwc_rule_destroy(struct mlx5hws_bwc_rule *bwc_rule)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-673-\telse\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:674:\t\tret = mlx5hws_bwc_rule_destroy_simple(bwc_rule);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-675-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=1000=static int hws_bwc_rule_cnt_inc_with_rehash(struct mlx5hws_bwc_rule *bwc_rule,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-1035-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:1036:int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_rule *bwc_rule,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-1037-\t\t\t\t u32 *match_param,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=1139=mlx5hws_bwc_rule_create(struct mlx5hws_bwc_matcher *bwc_matcher,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-1170-\telse\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:1171:\t\tret = mlx5hws_bwc_rule_create_simple(bwc_rule,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-1172-\t\t\t\t\t\t params-\u003ematch_buf,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h=21=enum mlx5hws_bwc_matcher_type {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-29-\t/* A submatcher that is part of a complex matcher. For most purposes\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h:30:\t * these are treated as simple matchers, except when it comes to moving\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-31-\t * rules during resize.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h=70=int\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h:71:mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bwc_matcher *bwc_matcher,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-72-\t\t\t\t struct mlx5hws_table *table,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-77-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h:78:int mlx5hws_bwc_matcher_destroy_simple(struct mlx5hws_bwc_matcher *bwc_matcher);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-79-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h=82=void mlx5hws_bwc_rule_free(struct mlx5hws_bwc_rule *bwc_rule);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-83-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h:84:int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_rule *bwc_rule,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-85-\t\t\t\t u32 *match_param,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-89-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h:90:int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_rule *bwc_rule);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h-91-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=195=static void hws_avoid_ipv6_split(struct mlx5hws_match_parameters *orig,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-216- */\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:217:static int hws_get_simple_params(struct mlx5hws_context *ctx, u8 match_criteria,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-218-\t\t\t\t struct mlx5hws_match_parameters *orig,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-266-\t\t\t *\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:267:\t\t\t * For now, keep the code simple. This results in an\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-268-\t\t\t * extra submatcher in some cases, but it's good enough.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=299=hws_bwc_matcher_split_mask(struct mlx5hws_context *ctx, u8 match_criteria,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-329-\t\t}\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:330:\t\tret = hws_get_simple_params(ctx, match_criteria, \u0026mask_copy,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-331-\t\t\t\t\t \u0026submasks[i]);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=388=static int hws_submatcher_init_first(struct mlx5hws_bwc_matcher *cmatcher,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-410-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:411:\tret = mlx5hws_bwc_matcher_create_simple(subm-\u003ebwc_matcher, subm-\u003etbl,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-412-\t\t\t\t\t\tpriority, match_criteria, mask,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-427-destroy_matcher:\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:428:\tmlx5hws_bwc_matcher_destroy_simple(subm-\u003ebwc_matcher);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-429-\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=433=static int hws_submatcher_init(struct mlx5hws_bwc_matcher *cmatcher, int idx,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-481-\t */\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:482:\tret = mlx5hws_bwc_matcher_create_simple(subm-\u003ebwc_matcher, subm-\u003etbl,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-483-\t\t\t\t\t\tpriority, match_criteria, mask,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-499-destroy_matcher:\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:500:\tmlx5hws_bwc_matcher_destroy_simple(subm-\u003ebwc_matcher);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-501-free_matcher:\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=511=static void hws_submatcher_destroy(struct mlx5hws_bwc_matcher *cmatcher,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-522-\tif (subm-\u003ebwc_matcher) {\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:523:\t\tmlx5hws_bwc_matcher_destroy_simple(subm-\u003ebwc_matcher);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-524-\t\tif (idx)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=667=__must_hold(\u0026subm-\u003ehash_lock)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-701-\t\t * Note that we don't have any indication for the rule creation\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:702:\t\t * process that a rule with similar matching params already\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-703-\t\t * exists - no harm done when this rule is be overwritten by\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=749=static int hws_complex_subrule_create(struct mlx5hws_bwc_matcher *cmatcher,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-782-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:783:\tret = mlx5hws_bwc_rule_create_simple(subrule, match_params, actions,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-784-\t\t\t\t\t flow_source, bwc_queue_idx);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=799=static int hws_complex_subrule_destroy(struct mlx5hws_bwc_rule *bwc_rule,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-816-\tbwc_rule-\u003erule-\u003eskip_delete = !is_last_rule;\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:817:\tret = mlx5hws_bwc_rule_destroy_simple(bwc_rule);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-818-\tif (unlikely(ret))\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c=969=int mlx5hws_bwc_matcher_complex_move(struct mlx5hws_bwc_matcher *bwc_matcher)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-993-\t\tlist_for_each_entry(tmp_bwc_rule, rules_list, list_node) {\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c:994:\t\t\t/* Check if a rule with similar tag has already\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c-995-\t\t\t * been moved.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.h=32=struct mlx5hws_bwc_complex_submatcher {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.h-40-\tstruct mlx5hws_action *action_tbl;\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.h:41:\t/* This submatcher's simple matcher. The first submatcher points to the\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.h-42-\t * outer (complex) matcher.\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c=721=hws_definer_conv_outer(struct mlx5hws_definer_conv_data *cd,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-814-\t\tHWS_SET_HDR(fc, match_param, IPV6_SRC_127_96_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:815:\t\t\t outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_127_96,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-816-\t\t\t ipv6_src_outer.ipv6_address_127_96);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-817-\t\tHWS_SET_HDR(fc, match_param, IPV6_SRC_95_64_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:818:\t\t\t outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_95_64,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-819-\t\t\t ipv6_src_outer.ipv6_address_95_64);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-820-\t\tHWS_SET_HDR(fc, match_param, IPV6_SRC_63_32_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:821:\t\t\t outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_63_32,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-822-\t\t\t ipv6_src_outer.ipv6_address_63_32);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-823-\t\tHWS_SET_HDR(fc, match_param, IPV6_SRC_31_0_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:824:\t\t\t outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_31_0,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-825-\t\t\t ipv6_src_outer.ipv6_address_31_0);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-827-\t\tHWS_SET_HDR(fc, match_param, IPV6_DST_127_96_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:828:\t\t\t outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_127_96,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-829-\t\t\t ipv6_dst_outer.ipv6_address_127_96);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-830-\t\tHWS_SET_HDR(fc, match_param, IPV6_DST_95_64_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:831:\t\t\t outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_95_64,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-832-\t\t\t ipv6_dst_outer.ipv6_address_95_64);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-833-\t\tHWS_SET_HDR(fc, match_param, IPV6_DST_63_32_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:834:\t\t\t outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_63_32,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-835-\t\t\t ipv6_dst_outer.ipv6_address_63_32);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-836-\t\tHWS_SET_HDR(fc, match_param, IPV6_DST_31_0_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:837:\t\t\t outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_31_0,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-838-\t\t\t ipv6_dst_outer.ipv6_address_31_0);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-841-\t\tHWS_SET_HDR(fc, match_param, IPV4_SRC_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:842:\t\t\t outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_31_0,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-843-\t\t\t ipv4_src_dest_outer.source_address);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-845-\t\tHWS_SET_HDR(fc, match_param, IPV4_DST_O,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:846:\t\t\t outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_31_0,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-847-\t\t\t ipv4_src_dest_outer.destination_address);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c=898=hws_definer_conv_inner(struct mlx5hws_definer_conv_data *cd,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-990-\t\tHWS_SET_HDR(fc, match_param, IPV6_SRC_127_96_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:991:\t\t\t inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_127_96,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-992-\t\t\t ipv6_src_inner.ipv6_address_127_96);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-993-\t\tHWS_SET_HDR(fc, match_param, IPV6_SRC_95_64_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:994:\t\t\t inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_95_64,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-995-\t\t\t ipv6_src_inner.ipv6_address_95_64);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-996-\t\tHWS_SET_HDR(fc, match_param, IPV6_SRC_63_32_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:997:\t\t\t inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_63_32,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-998-\t\t\t ipv6_src_inner.ipv6_address_63_32);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-999-\t\tHWS_SET_HDR(fc, match_param, IPV6_SRC_31_0_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:1000:\t\t\t inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_31_0,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1001-\t\t\t ipv6_src_inner.ipv6_address_31_0);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1003-\t\tHWS_SET_HDR(fc, match_param, IPV6_DST_127_96_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:1004:\t\t\t inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_127_96,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1005-\t\t\t ipv6_dst_inner.ipv6_address_127_96);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1006-\t\tHWS_SET_HDR(fc, match_param, IPV6_DST_95_64_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:1007:\t\t\t inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_95_64,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1008-\t\t\t ipv6_dst_inner.ipv6_address_95_64);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1009-\t\tHWS_SET_HDR(fc, match_param, IPV6_DST_63_32_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:1010:\t\t\t inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_63_32,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1011-\t\t\t ipv6_dst_inner.ipv6_address_63_32);\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1012-\t\tHWS_SET_HDR(fc, match_param, IPV6_DST_31_0_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:1013:\t\t\t inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_31_0,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1014-\t\t\t ipv6_dst_inner.ipv6_address_31_0);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1017-\t\tHWS_SET_HDR(fc, match_param, IPV4_SRC_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:1018:\t\t\t inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_31_0,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1019-\t\t\t ipv4_src_dest_inner.source_address);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1021-\t\tHWS_SET_HDR(fc, match_param, IPV4_DST_I,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:1022:\t\t\t inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_31_0,\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c-1023-\t\t\t ipv4_src_dest_inner.destination_address);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c-12-#include \u003casm/neon.h\u003e\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c:13:#include \u003casm/simd.h\u003e\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c-14-#endif\n--\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c=264=static void mlx5_iowrite64_copy(struct mlx5_wc_sq *sq, __be32 mmio_wqe[16],\n--\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c-268-\tif (cpu_has_neon()) {\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c:269:\t\tscoped_ksimd() {\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c-270-\t\t\tasm volatile(\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c:271:\t\t\t\t\".arch_extension simd\\n\\t\"\ndrivers/net/ethernet/mellanox/mlx5/core/wc.c-272-\t\t\t\t\"ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [%0]\\n\\t\"\n"
} |
| 15/2 | 2026/06/30 18:12 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 37764 output: 42 thoughts: 750 Thoughts: **My Thought Process on Reaching MLX5 with Syzkaller** Okay, so I'm thinking about how syzkaller might be able to interact with the `MLX5_SF` and `MLX5_SF_MANAGER` subfunctions. These are like SRIOV VFs, but without the SRIOV requirement, supporting RDMA, netdevs, and vdpa devices. The question is, can syzkaller even *create* these subfunctions? My initial thought is to leverage syzkaller's PCI fuzzer, specifically `syz_pci_ep`. That creates a fake PCI device, which the mlx5 driver could then probe. If the driver initializes far enough to register a netdevice, then syzkaller could talk to it via standard netlink or socket APIs. But, there's a problem: the mlx5 driver needs complex firmware commands during initialization. And, `syz_pci_ep` doesn't emulate that firmware. So, does syzkaller have any way to actually *reach* mlx5? I'd like to check for existing syzkaller bugs in mlx5, but without access to the full kernel history, I'm stuck. The prompt notes, "Code paths that are impossible to reach in virtualized environments like GCE or QEMU..." If mlx5 is a *physical* device driver and *not* software-emulated, then it's effectively unreachable in GCE/QEMU unless there's an emulator. And, there isn't a `mlx5_sim` or `mlx5_hwsim` equivalent. But, there's `netdevsim`. That's used for testing, but it doesn't utilize mlx5 code. Then, there's `syz_pci_ep`! It emulates *software* hardware - a PCI endpoint. So, if `syz_pci_ep` can emulate mlx5, then it *is* reachable. But here comes the problem: `syz_pci_ep` does not emulate the firmware. Drivers requiring complicated firmware handshakes, like mlx5, ice, i40e, usually fail with `syz_pci_ep` because the fuzzer can't guess the firmware's correct response sequence. Wait a second, there is something I have to look at! The patch's author is `syz-cluster <triage@syzkaller.com>`. "syz-cluster: applied patch under review". This means syzkaller *did* find a bug! It is a patch that I am reviewing! This proves it is testing this. If syzkaller found a bug, how? Is there a virtual mlx5 device in QEMU? No, QEMU doesn't have an upstream mlx5 emulator. Maybe syzkaller runs bare metal with Mellanox cards? No, syzkaller mostly runs in GCE/QEMU. Does syzkaller *itself* have an mlx5 emulator? I should check if there's any `mlx5` emulator in the kernel. |
| 16/2 | 2026/06/30 18:12 | tool | grepper |
0mArgs:{
"Expression": "mlx5_core_dev",
"PathPrefix": "drivers/net/ethernet/mellanox/mlx5/core/"
}Results: {
"Output": "\nFull output is too long, showing 500 out of 12323 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=58=struct mlx5_dma_pool {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-61-\tstruct list_head page_list;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:62:\tstruct mlx5_core_dev *dev;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-63-\tint node;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=79=struct mlx5_dma_pool_stats {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-89-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:90:static void *mlx5_dma_zalloc_coherent_node(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-91-\t\t\t\t\t size_t size, dma_addr_t *dma_handle,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=109=static void mlx5_dma_pool_destroy(struct mlx5_dma_pool *pool)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-114-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:115:static struct mlx5_dma_pool *mlx5_dma_pool_create(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-116-\t\t\t\t\t\t int node, u8 block_shift)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=133=mlx5_dma_pool_page_alloc(struct mlx5_dma_pool *pool)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-162-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:163:static void mlx5_dma_pool_page_free(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-164-\t\t\t\t struct mlx5_dma_pool_page *page)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=283=static struct mlx5_frag_buf_node_pools *\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:284:mlx5_frag_buf_node_pools_create(struct mlx5_core_dev *dev, int node)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-285-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=307=mlx5_frag_buf_dma_pools_debugfs_show(struct seq_file *file, void *priv)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-308-{\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:309:\tstruct mlx5_core_dev *dev = file-\u003eprivate;\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-310-\tint node;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=336=DEFINE_SHOW_ATTRIBUTE(mlx5_frag_buf_dma_pools_debugfs);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-337-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:338:void mlx5_frag_buf_pools_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-339-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-358-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:359:int mlx5_frag_buf_pools_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-360-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-387-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:388:int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-389-\t\t\t struct mlx5_frag_buf *buf, int node)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=425=EXPORT_SYMBOL_GPL(mlx5_frag_buf_alloc_node);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-426-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:427:void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-428-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=445=EXPORT_SYMBOL_GPL(mlx5_frag_buf_free);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-446-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:447:static struct mlx5_db_pgdir *mlx5_alloc_db_pgdir(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-448-\t\t\t\t\t\t int node)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=476=static int mlx5_alloc_db_from_pgdir(struct mlx5_db_pgdir *pgdir,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-500-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:501:int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, int node)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-502-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c=528=EXPORT_SYMBOL_GPL(mlx5_db_alloc_node);\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-529-\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c:530:void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db)\ndrivers/net/ethernet/mellanox/mlx5/core/alloc.c-531-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=283=static void poll_timeout(struct mlx5_cmd_work_ent *ent)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-284-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:285:\tstruct mlx5_core_dev *dev = container_of(ent-\u003ecmd, struct mlx5_core_dev, cmd);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-286-\tu64 cmd_to_ms = mlx5_tout_ms(dev, CMD);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=331=static void dump_buf(void *buf, int size, int data_only, int offset, int idx)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-346-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:347:static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-348-\t\t\t\t u32 *synd, u8 *status)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=793=static int cmd_status_to_err(u8 status)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-816-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:817:void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-818-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=827=EXPORT_SYMBOL(mlx5_cmd_out_err);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-828-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:829:static void cmd_status_print(struct mlx5_core_dev *dev, void *in, void *out)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-830-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-844-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:845:int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-846-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=872=EXPORT_SYMBOL(mlx5_cmd_check);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-873-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:874:static void dump_command(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-875-\t\t\t struct mlx5_cmd_work_ent *ent, int input)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-931-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:932:static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-933-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=934=static void cb_timeout_handler(struct work_struct *work)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-939-\t\t\t\t\t\t cb_timeout_work);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:940:\tstruct mlx5_core_dev *dev = container_of(ent-\u003ecmd, struct mlx5_core_dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-941-\t\t\t\t\t\t cmd);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-960-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:961:static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:962:static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-963-\t\t\t struct mlx5_cmd_msg *msg);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=965=static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-972-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:973:bool mlx5_cmd_is_down(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-974-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=980=static void cmd_work_handler(struct work_struct *work)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-985-\tstruct mlx5_cmd_layout *lay;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:986:\tstruct mlx5_core_dev *dev;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-987-\tunsigned long timeout;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-993-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:994:\tdev = container_of(cmd, struct mlx5_core_dev, cmd);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-995-\ttimeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1140=enum {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1143-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1144:static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1145-\t\t\t\t\t struct mlx5_cmd_work_ent *ent)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1168-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1169:static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1170-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1215- */\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1216:static bool mlx5_cmd_all_stalled(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1217-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1258- */\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1259:static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1260-\t\t\t struct mlx5_cmd_msg *out, void *uout, int uout_size,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1337=static ssize_t dbg_write(struct file *filp, const char __user *buf,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1339-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1340:\tstruct mlx5_core_dev *dev = filp-\u003eprivate_data;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1341-\tstruct mlx5_cmd_debug *dbg = \u0026dev-\u003ecmd.dbg;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1404=static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1436-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1437:static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1438-\t\t\t\t\t gfp_t flags)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1457-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1458:static void free_cmd_box(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1459-\t\t\t struct mlx5_cmd_mailbox *mailbox)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1464-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1465:static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1466-\t\t\t\t\t gfp_t flags, int size,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1511-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1512:static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1513-\t\t\t struct mlx5_cmd_msg *msg)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1526=static ssize_t data_write(struct file *filp, const char __user *buf,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1528-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1529:\tstruct mlx5_core_dev *dev = filp-\u003eprivate_data;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1530-\tstruct mlx5_cmd_debug *dbg = \u0026dev-\u003ecmd.dbg;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1550=static ssize_t data_read(struct file *filp, char __user *buf, size_t count,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1552-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1553:\tstruct mlx5_core_dev *dev = filp-\u003eprivate_data;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1554-\tstruct mlx5_cmd_debug *dbg = \u0026dev-\u003ecmd.dbg;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1570=static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1572-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1573:\tstruct mlx5_core_dev *dev = filp-\u003eprivate_data;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1574-\tstruct mlx5_cmd_debug *dbg = \u0026dev-\u003ecmd.dbg;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1585=static ssize_t outlen_write(struct file *filp, const char __user *buf,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1587-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1588:\tstruct mlx5_core_dev *dev = filp-\u003eprivate_data;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1589-\tstruct mlx5_cmd_debug *dbg = \u0026dev-\u003ecmd.dbg;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1621=static const struct file_operations olfops = {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1627-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1628:static void set_wqname(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1629-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1635-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1636:static void clean_debug_files(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1637-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1645-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1646:static void create_debugfs_files(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1647-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1658-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1659:void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1660-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1674-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1675:static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1676-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1691=static int cmd_comp_notifier(struct notifier_block *nb,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1693-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1694:\tstruct mlx5_core_dev *dev;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1695-\tstruct mlx5_cmd *cmd;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1698-\tcmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1699:\tdev = container_of(cmd, struct mlx5_core_dev, cmd);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1700-\teqe = data;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1708-}\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1709:void mlx5_cmd_use_events(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1710-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1715-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1716:void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1717-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1721-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1722:static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1723-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1734-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1735:static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1736-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1838-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1839:static void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1840-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1873-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1874:void mlx5_cmd_flush(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1875-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1896-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1897:static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1898-\t\t\t\t gfp_t gfp)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=1935=static int is_manage_pages(void *in)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1939-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1940:static bool mlx5_has_privileged_uid(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1941-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1944-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1945:static bool mlx5_cmd_is_privileged_uid(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1946-\t\t\t\t u16 uid)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1954- */\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:1955:static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-1956-\t\t int out_size, mlx5_cmd_cbk_t callback, void *context,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2035-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2036:static void mlx5_cmd_err_trace(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2037-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2045-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2046:static void cmd_status_log(struct mlx5_core_dev *dev, u16 opcode, u8 status,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2047-\t\t\t u32 syndrome, int err)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2071-/* preserve -EREMOTEIO for outbox.status != OK, otherwise return err as is */\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2072:static int cmd_status_err(struct mlx5_core_dev *dev, int err, u16 opcode, u16 op_mod, void *out)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2073-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2106- */\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2107:int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2108-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=2115=EXPORT_SYMBOL(mlx5_cmd_do);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2128- */\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2129:int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2130-\t\t int out_size)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=2136=EXPORT_SYMBOL(mlx5_cmd_exec);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2151- */\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2152:int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2153-\t\t\t void *out, int out_size)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=2162=EXPORT_SYMBOL(mlx5_cmd_exec_polling);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2163-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2164:void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2165-\t\t\t struct mlx5_async_ctx *ctx)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=2189=static void mlx5_cmd_exec_cb_handler(int status, void *_work)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2192-\tstruct mlx5_async_ctx *ctx;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2193:\tstruct mlx5_core_dev *dev;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2194-\tbool throttle_locked;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=2214=int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2217-{\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2218:\tstruct mlx5_core_dev *dev = ctx-\u003edev;\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2219-\tu16 uid;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=2268=EXPORT_SYMBOL(mlx5_cmd_exec_cb);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2269-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2270:int mlx5_cmd_allow_other_vhca_access(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2271-\t\t\t\t struct mlx5_cmd_allow_other_vhca_access_attr *attr)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2289-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2290:int mlx5_cmd_alias_obj_create(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2291-\t\t\t struct mlx5_cmd_alias_obj_create_attr *alias_attr,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2325-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2326:int mlx5_cmd_alias_obj_destroy(struct mlx5_core_dev *dev, u32 obj_id,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2327-\t\t\t u16 obj_type)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2338-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2339:static void destroy_msg_cache(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2340-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=2359=static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2366-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2367:static void create_msg_cache(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2368-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2392-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2393:static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2394-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2421-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2422:static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2423-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2427-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2428:static u16 cmdif_rev(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2429-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2432-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2433:int mlx5_cmd_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2434-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2453-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2454:void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2455-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2461-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2462:int mlx5_cmd_enable(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2463-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2547-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2548:void mlx5_cmd_disable(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2549-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2559-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2560:void mlx5_cmd_set_state(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2561-\t\t\tenum mlx5_cmdif_state cmdif_state)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2565-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2566:int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2567-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c=2571=EXPORT_SYMBOL(mlx5_cmd_add_privileged_uid);\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2572-\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c:2573:void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid)\ndrivers/net/ethernet/mellanox/mlx5/core/cmd.c-2574-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c=100=static void mlx5_core_cq_dummy_cb(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-107-/* Callers must verify outbox status in case of err */\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c:108:int mlx5_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-109-\t\t u32 *in, int inlen, u32 *out, int outlen)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c=178=EXPORT_SYMBOL(mlx5_create_cq);\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-180-/* oubox is checked and err val is normalized */\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c:181:int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-182-\t\t\tu32 *in, int inlen, u32 *out, int outlen)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c=188=EXPORT_SYMBOL(mlx5_core_create_cq);\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-189-\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c:190:int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq)\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-191-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c=213=EXPORT_SYMBOL(mlx5_core_destroy_cq);\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-214-\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c:215:int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-216-\t\t u32 *out)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c=224=EXPORT_SYMBOL(mlx5_core_query_cq);\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-225-\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c:226:int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-227-\t\t\tu32 *in, int inlen)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c=235=EXPORT_SYMBOL(mlx5_core_modify_cq);\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-236-\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c:237:int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev,\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-238-\t\t\t\t struct mlx5_core_cq *cq,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=96=void mlx5_unregister_debugfs(void)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-100-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:101:struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-102-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=105=EXPORT_SYMBOL(mlx5_debugfs_get_dev_root);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-106-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:107:void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-108-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=111=EXPORT_SYMBOL(mlx5_qp_debugfs_init);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-112-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:113:void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-114-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=117=EXPORT_SYMBOL(mlx5_qp_debugfs_cleanup);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-118-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:119:void mlx5_eq_debugfs_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-120-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-123-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:124:void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-125-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=202=mlx5_cmdif_alloc_stats(struct xarray *stats_xa, int opcode)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-218-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:219:void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-220-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-258-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:259:void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-260-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-269-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:270:void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-271-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-274-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:275:void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-276-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-279-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:280:void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-281-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-293-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:294:void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-295-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-298-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:299:void mlx5_pages_by_func_type_debugfs_init(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-300-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-322-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:323:void mlx5_pages_by_func_type_debugfs_cleanup(struct mlx5_core_dev *dev)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-324-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-336-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:337:static u64 qp_read_field(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-338-\t\t\t int index, int *is_str)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-416-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:417:static u64 eq_read_field(struct mlx5_core_dev *dev, struct mlx5_eq *eq,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-418-\t\t\t int index)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-456-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:457:static u64 cq_read_field(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-458-\t\t\t int index)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=532=static const struct file_operations fops = {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-537-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:538:static int add_res_tree(struct mlx5_core_dev *dev, enum dbg_rsc_type type,\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-539-\t\t\tstruct dentry *root, struct mlx5_rsc_debug **dbg,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=566=static void rem_res_tree(struct mlx5_rsc_debug *d)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-571-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:572:int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-573-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=587=EXPORT_SYMBOL(mlx5_debug_qp_add);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-588-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:589:void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp)\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-590-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c=597=EXPORT_SYMBOL(mlx5_debug_qp_remove);\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c-598-\ndrivers/net/ethernet/mellanox/mlx5/core/debugfs.c:599:int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq)\n\n"
} |
| 17/2 | 2026/06/30 18:12 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 53303 output: 37 thoughts: 1162 Thoughts: **Analyzing the Reachability of Mellanox mlx5 Code in Virtualized Environments** Okay, so I'm looking at this patch and trying to determine if it's worth fuzzing. The prompt says to return `WorthFuzzing=false` if the code paths are impossible to reach in virtualized environments like GCE or QEMU, even with software-emulated hardware. My immediate thought is, can syzkaller's PCI fuzzer get to this `mlx5` code? I know syzkaller has a PCI fuzzer that can probe any PCI driver. Mellanox mlx5 is, of course, a PCI device. So, if syzkaller can reach it with its PCI fuzzer, then it's reachable, right? But the wording "even when utilizing software-emulated hardware" gives me pause, because syzkaller's PCI fuzzer *is* emulating PCI devices. The author is listed as `syz-cluster <triage@syzkaller.com>`, which screams syzkaller bug, so I need to understand if syzkaller found this bug and how. If syzkaller found it, then it can reach it. My first thought is upstream syzbot runs on GCE. So if syzkaller found it, then it is reachable in GCE. However, what if it was found on bare metal and then backported? I know syzbot upstream is mostly GCE, but it *does* test in other environments, correct? No, syzbot upstream is GCE. So then, this must be a custom syzkaller instance. Now I need to assess whether the PCI fuzzer is capable of reaching this specific code. `mlx5e_tc_clean_fdb_peer_flows` is part of the Ethernet driver, `en_tc.c`. To hit this, the mlx5 core device must be initialized, the ethernet netdev must be registered, and then TC rules must be configured. Initializing the mlx5 core involves complex firmware commands, command queues, and event queues. The PCI fuzzer just throws random data at the device. It's highly unlikely that the PCI fuzzer can successfully initialize all that. So if it's unlikely, how did syzkaller find it? Wait, could this be a manual patch, submitted by a user for testing by syzbot? Oh, the commit message says "syz-cluster: applied patch under review". Aha! That means it *is* a user-submitted patch tested by syzbot. If syzbot tested it, then the bug was likely found in the environment in which syzbot tests. Back to the original problem: Is mlx5 reachable in GCE/QEMU? If it isn't, I should return `WorthFuzzing=false`. I need to figure out if there's any software emulation for mlx5. I will search `drivers/net/ethernet/mellanox/mlx5/core/` for a dummy or mock driver. Let's see... nothing immediately stands out. I didn't find any software emulators for mlx5 when grepping for `mock` and `sim`. Therefore, I'm thinking the code is not reachable in GCE/QEMU, and I need to return `WorthFuzzing=false`. |
| 18/2 | 2026/06/30 18:12 | tool | grepper |
0mArgs:{
"Expression": "dummy",
"PathPrefix": "drivers/net/ethernet/mellanox/mlx5/core/"
}Results: {
"Output": "drivers/net/ethernet/mellanox/mlx5/core/cq.c=98=EXPORT_SYMBOL(mlx5_add_cq_to_tasklet);\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-99-\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c:100:static void mlx5_core_cq_dummy_cb(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe)\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-101-{\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c=108=int mlx5_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-143-\tif (!cq-\u003ecomp)\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c:144:\t\tcq-\u003ecomp = mlx5_core_cq_dummy_cb;\ndrivers/net/ethernet/mellanox/mlx5/core/cq.c-145-\t/* assuming CQ will be deleted before the EQ */\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/selq.c=27=int mlx5e_selq_init(struct mlx5e_selq *selq, struct mutex *state_lock)\n--\ndrivers/net/ethernet/mellanox/mlx5/core/en/selq.c-42-\t}\ndrivers/net/ethernet/mellanox/mlx5/core/en/selq.c:43:\t/* Assign dummy values, so that mlx5e_select_queue won't crash. */\ndrivers/net/ethernet/mellanox/mlx5/core/en/selq.c-44-\t*init_params = (struct mlx5e_selq_params) {\n--\ndrivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c=285=static int mlx5i_pkey_init(struct mlx5_core_dev *mdev,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c-300-\ndrivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c:301:\t/* Use dummy rqs */\ndrivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c-302-\tpriv-\u003echannels.params.log_rq_mtu_frames = MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=226=int mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bwc_matcher *bwc_matcher,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-260-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:261:\t/* create dummy action template */\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-262-\tbwc_matcher-\u003eat[0] =\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c=842=hws_bwc_matcher_find_at(struct mlx5hws_bwc_matcher *bwc_matcher,\n--\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-847-\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c:848:\t/* start from index 1 - first action template is a dummy */\ndrivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c-849-\tfor (i = 1; i \u003c bwc_matcher-\u003enum_of_at; i++) {\n"
} |
| 19/2 | 2026/06/30 18:12 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 56305 output: 30 thoughts: 579 Thoughts: **Analyzing the Feasibility of Fuzzing a Mellanox Subfunction Patch** Okay, I see these kernel configs, `CONFIG_MLX5_SF` and `CONFIG_MLX5_SF_MANAGER`, which suggest we're dealing with Mellanox subfunctions. The description says they're like SRIOV VFs, but without the SRIOV requirement. I immediately wonder: can subfunctions *exist* in a purely virtual environment? My understanding is they're built on top of physical Mellanox hardware. Then the thought strikes: what if syzkaller *is* running on a GCE instance that *does* have a Mellanox card? I need to remember how GCE instances are typically configured. I know they can use "Google Virtual NIC" or "virtio-net". And I recall local SSDs (NVMe) and GPUs are also options. But do standard GCE instances include Mellanox cards? Aha! I remember that some high-performance GCE instances do use Mellanox ConnectX cards, specifically the ConnectX-6 or ConnectX-7 models for Tier 1 networking or A3/A2 VMs. But syzkaller VMs are usually just standard small ones like `n1-standard-2` or `e2-standard-2` and so are probably using `virtio-net` or `gve` . So, no Mellanox hardware for the standard syzkaller setup. Okay, so syzkaller *doesn't* typically have Mellanox hardware in its default GCE VMs. Now I'm thinking, how could this patch be tested? Maybe this is a bug a user reported and submitted to syzbot. If the user submitted a patch, syzbot will try to test it. If syzbot doesn't have the hardware, the test will compile and run, but likely won't even *touch* the code. It is unlikely this will reach the Mellanox code. Then I recall the core question. If the code is unreachable in GCE/QEMU, I need to flag it as `WorthFuzzing=false`. I need to reread the prompt. Let's see: "Return WorthFuzzing=false if the patch only contains... code paths that are impossible to reach in virtualized environments like GCE or QEMU..." Is this mlx5 code reachable in GCE/QEMU? If there's no software emulator for mlx5, and the PCI fuzzer can't realistically get deep into the driver (think registering a netdev and configuring TC rules), then it is impossible to reach. It needs more than simple PCI reads/writes because of complex firmware interactions. Now, does the PCI fuzzer even *reach* this? I need to quickly check if there's any `syz_pci_ep` code specifically emulating mlx5. I need to be sure. |
| 20/2 | 2026/06/30 18:12 | tool | grepper |
0mArgs:{
"Expression": "mlx5",
"PathPrefix": "tools/testing/selftests/"
}Results: {
"Output": "tools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py=35=Bandwidth Distribution:\n--\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-41-\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py:42:Hardware-Specific Behavior (mlx5):\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-43---------------------------\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py:44:mlx5 hardware enforces traffic class separation by ensuring that each transmit\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-45-queue (SQ) is associated with a single TC. If a packet is sent on a queue that\n--\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py=388=def test_no_tc_mapping_bandwidth(cfg):\n--\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-393- fail_bw_msg = \"Bandwidth matched 20/80 split without TC mapping\"\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py:394: is_mlx5 = \"driver: mlx5\" in ethtool(f\"-i {cfg.ifname}\").stdout\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-395-\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-396- if run_bandwidth_distribution_test(cfg, set_tc_mapping=False):\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py:397: if is_mlx5:\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-398- raise KsftXfailEx(fail_bw_msg)\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-399- raise KsftFailEx(fail_bw_msg)\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py:400: if is_mlx5:\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py:401: raise KsftFailEx(\"mlx5 behavior changed:\" + pass_bw_msg)\ntools/testing/selftests/drivers/net/hw/devlink_rate_tc_bw.py-402- ksft_pr(pass_bw_msg)\n"
} |
| 21/2 | 2026/06/30 18:12 | llm | patch-evaluator |
0mModel:gemini-3.1-pro-preview Args: null Results: null Tokens: input: 58262 output: 112 thoughts: 961 Thoughts: **Unfuzzable Code Path Assessment** Okay, let's break this down. My initial thought is, there's no software emulator for mlx5, which immediately flags it as a potential dead end for standard fuzzing. But wait, what about the PCI fuzzer? Could it *somehow* reach it? If there's a possibility, I have to justify it. If I'm saying "WorthFuzzing=true," then I need to provide `FocusSymbols` and `EnableConfigs`. If it's "WorthFuzzing=false," the reasoning has to be airtight. The initial reasoning is: "The patch modifies the Mellanox mlx5 hardware driver. Since mlx5 requires physical Mellanox hardware and there is no software emulator for it in the kernel, these code paths are impossible to reach in standard virtualized environments like GCE or QEMU." That sounds solid, but let's delve deeper. Does Syzkaller even try to fuzz mlx5? It has a `syz_pci_ep` fuzzer. It could be a possibility. Let's see if syzkaller has found anything. I can't do a direct search of the Syzkaller dashboard, but I can make an educated guess. Complex network drivers often require firmware interaction. While the PCI fuzzer might trigger some early probe code, hitting code paths like `mlx5e_tc_clean_fdb_peer_flows` is highly unlikely. That function needs a registered netdev, e-switch enabled, and TC rules set up – essentially, a fully functional mlx5 environment which just wouldn't be possible with a generic PCI fuzzer. Okay, let's examine the specific locations that are impacted. `mlx5_lag_create_single_fdb_filter` is in `lag/shared_fdb.c`. LAG, or Link Aggregation, needs multiple physical ports. `mlx5_mpesw_work` is in `lag/mpesw.c`. These are deep, hardware-specific features: Multi-Port E-Switch, Link Aggregation. There's almost zero chance the PCI fuzzer can reach those without a dedicated emulator, which doesn't exist. This code is essentially unreachable in a virtualized environment. Now, let me double check the Syzkaller config. Does Syzkaller enable `CONFIG_MLX5_CORE`? Yes, it does. It's fuzzing the probe function. But, the prompt is explicit: "Return WorthFuzzing=false if the patch only contains code paths that are impossible to reach in virtualized environments like GCE or QEMU." Mlx5 is a physical hardware driver, there is no `mlx5_sim` or similar software emulator, so these TC flows, LAG, and MPESW modifications will be unachievable in GCE/QEMU. The reasoning needs to be clear, so here it is: "The patch modifies the Mellanox mlx5 hardware driver, specifically deep logic related to TC flows, Link Aggregation (LAG), and Multi-Port E-Switch (MPESW). Since mlx5 requires physical Mellanox hardware and there is no software emulator for it in the kernel, these code paths are impossible to reach in standard virtualized environments like GCE or QEMU." Hold on, what about a virtual device that uses this code? Maybe `netdevsim`? No, that's a completely separate driver. Could it be used with vdpa? `vdpa` has `mlx5_vdpa`, but it *still* needs a physical mlx5 device. What about vfio? Yes, but it requires physical hardware too. The conclusion stands. This requires physical hardware. Let's do a final quick patch review. Files modified are: `drivers/net/ethernet/mellanox/mlx5/core/en_tc.c`, `drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c`, and `drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c`. All within the `drivers/net/ethernet/mellanox/mlx5/core/` directory. Yep, that confirms it: Mellanox ConnectX hardware driver. I will set `WorthFuzzing=false`. |
| 22/2 | 2026/06/30 18:13 | tool | set-results |
0mArgs:{
"EnableConfigs": [],
"FocusSymbols": [],
"Reasoning": "The patch modifies the Mellanox mlx5 hardware driver, specifically deep logic related to TC flows, Link Aggregation (LAG), and Multi-Port E-Switch (MPESW). Since mlx5 requires physical Mellanox hardware and there is no software emulator for it in the kernel, these code paths are impossible to reach in standard virtualized environments like GCE or QEMU.",
"WorthFuzzing": false
}Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch modifies the Mellanox mlx5 hardware driver, specifically deep logic related to TC flows, Link Aggregation (LAG), and Multi-Port E-Switch (MPESW). Since mlx5 requires physical Mellanox hardware and there is no software emulator for it in the kernel, these code paths are impossible to reach in standard virtualized environments like GCE or QEMU.",
"WorthFuzzing": false
} |
| Total Calls | Total Tokens | Avg Tokens | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|
| Total Calls | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|