AI Trajectory

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies the qca8k DSA switch driver, which is a hardware-specific driver for Qualcomm Atheros QCA8K Ethernet switch chips. This driver requires physical hardware connected via MDIO to probe successfully (it reads the switch ID from a hardware register during probe). Since this hardware is not emulated in standard QEMU/GCE environments used by syzkaller, the modified code paths are impossible to reach and fuzz.",
  "WorthFuzzing": false
}

null

{
  "PatchDiff": "commit 3cd945309ca42ef55e3da4d39dead4c8cc664262\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Mon Aug 10 07:16:46 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c\nindex 4c928983b8623..1d90a23aba6bb 100644\n--- a/drivers/net/dsa/qca/qca8k-8xxx.c\n+++ b/drivers/net/dsa/qca/qca8k-8xxx.c\n@@ -160,6 +160,11 @@ qca8k_set_page(struct qca8k_priv *priv, u16 page)\n \treturn 0;\n }\n \n+static bool qca8k_mgmt_eth_disabled(const struct qca8k_priv *priv)\n+{\n+\treturn priv-\u003eswitch_id == QCA8K_ID_QCA8327;\n+}\n+\n static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)\n {\n \tstruct qca8k_mgmt_eth_data *mgmt_eth_data;\n@@ -316,6 +321,9 @@ static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\n \tbool ack;\n \tint ret;\n \n+\tif (qca8k_mgmt_eth_disabled(priv))\n+\t\treturn -ENXIO;\n+\n \tskb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,\n \t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY, len);\n \tif (!skb)\n@@ -368,6 +376,9 @@ static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\n \tbool ack;\n \tint ret;\n \n+\tif (qca8k_mgmt_eth_disabled(priv))\n+\t\treturn -ENXIO;\n+\n \tskb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,\n \t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY, len);\n \tif (!skb)\n@@ -630,6 +641,9 @@ qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,\n \tint ret, ret1;\n \tbool ack;\n \n+\tif (qca8k_mgmt_eth_disabled(priv))\n+\t\treturn -ENXIO;\n+\n \tif (regnum \u003e= QCA8K_MDIO_MASTER_MAX_REG)\n \t\treturn -EINVAL;\n \n"
}

best-expensive

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the qca8k DSA switch driver, which is a hardware-specific driver for Qualcomm Atheros QCA8K Ethernet switch chips. This driver requires physical hardware connected via MDIO to probe successfully (it reads the switch ID from a hardware register during probe). Since this hardware is not emulated in standard QEMU/GCE environments used by syzkaller, the modified code paths are impossible to reach and fuzz.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer.
Your job is to review a provided patch series and determine
if it makes functional changes to the kernel that should be fuzzed.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively
use your code access tools to examine the actual source code and confirm any assumptions.

Return WorthFuzzing=false if the patch only contains:
- Modifications to Documentation/, Kconfig files, or code comments.
- Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints.
- Changes to numeric constants or macros that do not functionally alter execution flow.
- Code paths that are impossible to reach in virtualized environments like GCE or QEMU,
  even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim).
- Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed,
  ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU.
- Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove)
  that are executed only during PCI hot-unplug or sysfs driver unbind operations.

If it modifies reachable core kernel logic, drivers, or architectures, use your code search
tools to verify the code can be executed, then return WorthFuzzing=true.

When returning WorthFuzzing=true, you MUST ALSO:
1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols.
   Avoid listing generic hot-path functions to prevent skewed test distributions.
   Prefer non-static, non-inlined API entrypoint functions over internal static helper functions
   (which are inlined by the compiler and do not have distinct symbol addresses).
2. Identify any specific CONFIG_ options required to properly test this new/modified feature.
   Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions.
   Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs
   needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs
   output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

For your convenience, here is the diff of the changes:
commit 3cd945309ca42ef55e3da4d39dead4c8cc664262
Author: syz-cluster <triage@syzkaller.com>
Date:   Mon Aug 10 07:16:46 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index 4c928983b8623..1d90a23aba6bb 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -160,6 +160,11 @@ qca8k_set_page(struct qca8k_priv *priv, u16 page)
 	return 0;
 }
 
+static bool qca8k_mgmt_eth_disabled(const struct qca8k_priv *priv)
+{
+	return priv->switch_id == QCA8K_ID_QCA8327;
+}
+
 static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
 {
 	struct qca8k_mgmt_eth_data *mgmt_eth_data;
@@ -316,6 +321,9 @@ static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
 	bool ack;
 	int ret;
 
+	if (qca8k_mgmt_eth_disabled(priv))
+		return -ENXIO;
+
 	skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,
 				      QCA8K_ETHERNET_MDIO_PRIORITY, len);
 	if (!skb)
@@ -368,6 +376,9 @@ static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
 	bool ack;
 	int ret;
 
+	if (qca8k_mgmt_eth_disabled(priv))
+		return -ENXIO;
+
 	skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,
 				      QCA8K_ETHERNET_MDIO_PRIORITY, len);
 	if (!skb)
@@ -630,6 +641,9 @@ qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,
 	int ret, ret1;
 	bool ack;
 
+	if (qca8k_mgmt_eth_disabled(priv))
+		return -ENXIO;
+
 	if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 		return -EINVAL;
 

gemini-3.1-pro-preview

null

null

							input: 2479
							output: 23
							thoughts: 188
						

**Analyzing a Qualcomm Atheros QCA8K Ethernet Switch Driver Patch**

Okay, so this patch is touching `drivers/net/dsa/qca/qca8k-8xxx.c`. Interesting. It looks like they've added a check for `qca8k_mgmt_eth_disabled(priv)` within `qca8k_read_eth`, `qca8k_write_eth`, and `qca8k_phy_eth_command`. Essentially, if the `switch_id` is set to `QCA8K_ID_QCA8327`, it'll return `-ENXIO`. This is for a Qualcomm Atheros QCA8K Ethernet switch driver, a DSA driver, which usually means it's pretty tightly coupled with specific hardware.

My immediate question is, how easily could this driver be exercised in a virtualized environment? DSA drivers, by their nature, often rely on the underlying switch hardware. Could this be one of those cases, or is there some abstraction layer involved? To understand the implications of this new check, I need to understand the context.

Let's dig into the Kconfig for this driver. I need to figure out what dependencies it has, how it's configured, and whether there are any clues about its hardware requirements. That will help me understand whether this patch is simply hardening a specific hardware configuration, or if it might impact virtualized uses as well. I'll focus on anything that speaks to the hardware dependencies.

{
  "Expression": "config NET_DSA_QCA8K"
}

{
  "Output": "drivers/net/dsa/qca/Kconfig=2=config NET_DSA_AR9331\n--\ndrivers/net/dsa/qca/Kconfig-10-\ndrivers/net/dsa/qca/Kconfig:11:config NET_DSA_QCA8K\ndrivers/net/dsa/qca/Kconfig-12-\ttristate \"Qualcomm Atheros QCA8K Ethernet switch family support\"\n--\ndrivers/net/dsa/qca/Kconfig-18-\ndrivers/net/dsa/qca/Kconfig:19:config NET_DSA_QCA8K_LEDS_SUPPORT\ndrivers/net/dsa/qca/Kconfig-20-\tbool \"Qualcomm Atheros QCA8K Ethernet switch family LEDs support\"\n"
}

gemini-3.1-pro-preview

null

null

							input: 3211
							output: 38
							thoughts: 9
						

Okay, here's my attempt at summarizing the thought process, tailored for an expert audience, and written in the first person:

**Initial Assessment**

Right, let's break this down. My immediate instinct is to identify the dependencies. We're dealing with a system, a process, a problem – whatever "it" is – and understanding the foundational elements is paramount. What are the key variables? The core inputs? The underlying assumptions? Pinpointing these dependencies is the essential first step to any effective analysis. Where do we begin to unravel complexity?

{
  "File": "drivers/net/dsa/qca/Kconfig",
  "FirstLine": 1,
  "LineCount": 30
}

{
  "Contents": "   1:\t# SPDX-License-Identifier: GPL-2.0-only\n   2:\tconfig NET_DSA_AR9331\n   3:\t\ttristate \"Qualcomm Atheros AR9331 Ethernet switch support\"\n   4:\t\tdepends on NET_DSA\n   5:\t\tselect NET_DSA_TAG_AR9331\n   6:\t\tselect REGMAP\n   7:\t\thelp\n   8:\t\t  This enables support for the Qualcomm Atheros AR9331 built-in Ethernet\n   9:\t\t  switch.\n  10:\t\n  11:\tconfig NET_DSA_QCA8K\n  12:\t\ttristate \"Qualcomm Atheros QCA8K Ethernet switch family support\"\n  13:\t\tselect NET_DSA_TAG_QCA\n  14:\t\tselect REGMAP\n  15:\t\thelp\n  16:\t\t  This enables support for the Qualcomm Atheros QCA8K Ethernet\n  17:\t\t  switch chips.\n  18:\t\n  19:\tconfig NET_DSA_QCA8K_LEDS_SUPPORT\n  20:\t\tbool \"Qualcomm Atheros QCA8K Ethernet switch family LEDs support\"\n  21:\t\tdepends on NET_DSA_QCA8K\n  22:\t\tdepends on LEDS_CLASS=y || LEDS_CLASS=NET_DSA_QCA8K\n  23:\t\tdepends on LEDS_TRIGGERS\n  24:\t\thelp\n  25:\t\t  This enabled support for LEDs present on the Qualcomm Atheros\n  26:\t\t  QCA8K Ethernet switch chips.\n"
}

gemini-3.1-pro-preview

null

null

							input: 3767
							output: 20
							thoughts: 68
						

**Analyzing the QCA8K Ethernet Switch Driver**

Okay, so this is a hardware-specific driver, focusing on Qualcomm Atheros QCA8K Ethernet switch chips. My initial question is whether or not this is going to be emulatable or reachable within QEMU. From my experience with these kinds of DSA drivers, built for very specific hardware switches, it's pretty rare to see them fully emulated in a standard QEMU environment. So, I need to dig deeper. First, I have to figure out if this driver communicates via MDIO or SPI. This is the starting point for understanding its potential for integration or, frankly, the likelihood of a successful emulation effort.

{
  "Expression": "qca8k_match"
}

{
  "Output": "drivers/clk/qcom/nsscc-qca8k.c=2188=static int nss_cc_qca8k_probe(struct mdio_device *mdiodev)\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2203-\ndrivers/clk/qcom/nsscc-qca8k.c:2204:static const struct of_device_id nss_cc_qca8k_match_table[] = {\ndrivers/clk/qcom/nsscc-qca8k.c-2205-\t{ .compatible = \"qcom,qca8084-nsscc\" },\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2207-};\ndrivers/clk/qcom/nsscc-qca8k.c:2208:MODULE_DEVICE_TABLE(of, nss_cc_qca8k_match_table);\ndrivers/clk/qcom/nsscc-qca8k.c-2209-\ndrivers/clk/qcom/nsscc-qca8k.c=2210=static struct mdio_driver nss_cc_qca8k_driver = {\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2212-\t\t.name = \"qcom,qca8k-nsscc\",\ndrivers/clk/qcom/nsscc-qca8k.c:2213:\t\t.of_match_table\t= nss_cc_qca8k_match_table,\ndrivers/clk/qcom/nsscc-qca8k.c-2214-\t},\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=1121=qca8k_setup_of_pws_reg(struct qca8k_priv *priv)\ndrivers/net/dsa/qca/qca8k-8xxx.c-1122-{\ndrivers/net/dsa/qca/qca8k-8xxx.c:1123:\tconst struct qca8k_match_data *data = priv-\u003einfo;\ndrivers/net/dsa/qca/qca8k-8xxx.c-1124-\tstruct device_node *node = priv-\u003edev-\u003eof_node;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=2204=static const struct qca8k_info_ops qca8xxx_ops = {\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-2207-\ndrivers/net/dsa/qca/qca8k-8xxx.c:2208:static const struct qca8k_match_data qca8327 = {\ndrivers/net/dsa/qca/qca8k-8xxx.c-2209-\t.id = QCA8K_ID_QCA8327,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-2214-\ndrivers/net/dsa/qca/qca8k-8xxx.c:2215:static const struct qca8k_match_data qca8328 = {\ndrivers/net/dsa/qca/qca8k-8xxx.c-2216-\t.id = QCA8K_ID_QCA8327,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-2220-\ndrivers/net/dsa/qca/qca8k-8xxx.c:2221:static const struct qca8k_match_data qca833x = {\ndrivers/net/dsa/qca/qca8k-8xxx.c-2222-\t.id = QCA8K_ID_QCA8337,\n--\ndrivers/net/dsa/qca/qca8k.h=378=struct qca8k_info_ops {\n--\ndrivers/net/dsa/qca/qca8k.h-381-\ndrivers/net/dsa/qca/qca8k.h:382:struct qca8k_match_data {\ndrivers/net/dsa/qca/qca8k.h-383-\tu8 id;\n--\ndrivers/net/dsa/qca/qca8k.h=445=struct qca8k_priv {\n--\ndrivers/net/dsa/qca/qca8k.h-469-\tstruct qca8k_pcs pcs_port_6;\ndrivers/net/dsa/qca/qca8k.h:470:\tconst struct qca8k_match_data *info;\ndrivers/net/dsa/qca/qca8k.h-471-\tstruct qca8k_led ports_led[QCA8K_LED_COUNT];\n"
}

gemini-3.1-pro-preview

null

null

							input: 5261
							output: 22
							thoughts: 36
						

Okay, here's my take on those thoughts, tailored for an expert audience:

**Diving into the QCA8K-8XXX Driver**

Alright, time to get my hands dirty. I need to pinpoint the relevant part of the QCA8K-8XXX driver responsible for device matching. Let's start by zeroing in on the `qca8k_of_match` function within `drivers/net/dsa/qca/qca8k-8xxx.c`. This is where the magic should be happening – the Open Firmware matching logic. I need to refresh my memory on the specifics of how the device tree is parsed and how these drivers are attached. This file should be the starting point, the key to understanding how we identify and initialize the QCA8K-8XXX switch. Let's see what's what.

{
  "Expression": "qca8k_of_match"
}

{
  "Output": "drivers/net/dsa/qca/qca8k-8xxx.c=2221=static const struct qca8k_match_data qca833x = {\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-2226-\ndrivers/net/dsa/qca/qca8k-8xxx.c:2227:static const struct of_device_id qca8k_of_match[] = {\ndrivers/net/dsa/qca/qca8k-8xxx.c-2228-\t{ .compatible = \"qca,qca8327\", .data = \u0026qca8327 },\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=2235=static struct mdio_driver qca8kmdio_driver = {\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-2240-\t\t.name = \"qca8k\",\ndrivers/net/dsa/qca/qca8k-8xxx.c:2241:\t\t.of_match_table = qca8k_of_match,\ndrivers/net/dsa/qca/qca8k-8xxx.c-2242-\t\t.pm = \u0026qca8k_pm_ops,\n"
}

gemini-3.1-pro-preview

null

null

							input: 5849
							output: 18
							thoughts: 92
						

**MDIO Driver Investigation**

Okay, so I'm looking at this `qca8kmdio_driver` – that's an MDIO driver. My initial thought is, "Standard QEMU probably doesn't emulate MDIO devices directly, unless it's part of a more comprehensive SoC emulation or, maybe, there's a specialized MDIO bus emulator I'm not immediately thinking of". Then it hit me: wait, didn't I read something about syzkaller having *some* capability in this area? Maybe for injecting devices, or using dummy buses? It’s time to check if syzkaller has some specific support for interacting with MDIO. Let's see if that bears fruit.

{
  "Expression": "mdio_bus"
}

{
  "Output": "\nFull output is too long, showing 500 out of 2371 lines.\nUse more precise expression if possible.\n\nDocumentation/ABI/testing/sysfs-bus-mdio:1:What:          /sys/bus/mdio_bus/devices/.../statistics/\nDocumentation/ABI/testing/sysfs-bus-mdio:2:What:          /sys/class/mdio_bus/.../statistics/\nDocumentation/ABI/testing/sysfs-bus-mdio-3-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-bus-mdio=6=Description:\n--\nDocumentation/ABI/testing/sysfs-bus-mdio-9-\nDocumentation/ABI/testing/sysfs-bus-mdio:10:What:          /sys/bus/mdio_bus/devices/.../statistics/transfers\nDocumentation/ABI/testing/sysfs-bus-mdio:11:What:          /sys/class/mdio_bus/.../transfers\nDocumentation/ABI/testing/sysfs-bus-mdio-12-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-bus-mdio=15=Description:\n--\nDocumentation/ABI/testing/sysfs-bus-mdio-17-\nDocumentation/ABI/testing/sysfs-bus-mdio:18:What:          /sys/bus/mdio_bus/devices/.../statistics/errors\nDocumentation/ABI/testing/sysfs-bus-mdio:19:What:          /sys/class/mdio_bus/.../statistics/errors\nDocumentation/ABI/testing/sysfs-bus-mdio-20-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-bus-mdio=23=Description:\n--\nDocumentation/ABI/testing/sysfs-bus-mdio-25-\nDocumentation/ABI/testing/sysfs-bus-mdio:26:What:          /sys/bus/mdio_bus/devices/.../statistics/writes\nDocumentation/ABI/testing/sysfs-bus-mdio:27:What:          /sys/class/mdio_bus/.../statistics/writes\nDocumentation/ABI/testing/sysfs-bus-mdio-28-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-bus-mdio=31=Description:\n--\nDocumentation/ABI/testing/sysfs-bus-mdio-33-\nDocumentation/ABI/testing/sysfs-bus-mdio:34:What:          /sys/bus/mdio_bus/devices/.../statistics/reads\nDocumentation/ABI/testing/sysfs-bus-mdio:35:What:          /sys/class/mdio_bus/.../statistics/reads\nDocumentation/ABI/testing/sysfs-bus-mdio-36-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-bus-mdio=39=Description:\n--\nDocumentation/ABI/testing/sysfs-bus-mdio-41-\nDocumentation/ABI/testing/sysfs-bus-mdio:42:What:          /sys/bus/mdio_bus/devices/.../statistics/transfers_\u003caddr\u003e\nDocumentation/ABI/testing/sysfs-bus-mdio:43:What:          /sys/class/mdio_bus/.../statistics/transfers_\u003caddr\u003e\nDocumentation/ABI/testing/sysfs-bus-mdio-44-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-bus-mdio=47=Description:\n--\nDocumentation/ABI/testing/sysfs-bus-mdio-49-\nDocumentation/ABI/testing/sysfs-bus-mdio:50:What:          /sys/bus/mdio_bus/devices/.../statistics/errors_\u003caddr\u003e\nDocumentation/ABI/testing/sysfs-bus-mdio:51:What:          /sys/class/mdio_bus/.../statistics/errors_\u003caddr\u003e\nDocumentation/ABI/testing/sysfs-bus-mdio-52-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-bus-mdio=55=Description:\n--\nDocumentation/ABI/testing/sysfs-bus-mdio-57-\nDocumentation/ABI/testing/sysfs-bus-mdio:58:What:          /sys/bus/mdio_bus/devices/.../statistics/writes_\u003caddr\u003e\nDocumentation/ABI/testing/sysfs-bus-mdio:59:What:          /sys/class/mdio_bus/.../statistics/writes_\u003caddr\u003e\nDocumentation/ABI/testing/sysfs-bus-mdio-60-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-bus-mdio=63=Description:\n--\nDocumentation/ABI/testing/sysfs-bus-mdio-65-\nDocumentation/ABI/testing/sysfs-bus-mdio:66:What:          /sys/bus/mdio_bus/devices/.../statistics/reads_\u003caddr\u003e\nDocumentation/ABI/testing/sysfs-bus-mdio:67:What:          /sys/class/mdio_bus/.../statistics/reads_\u003caddr\u003e\nDocumentation/ABI/testing/sysfs-bus-mdio-68-Date:          January 2020\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev:1:What:\t\t/sys/class/mdio_bus/\u003cbus\u003e/\u003cdevice\u003e/attached_dev\nDocumentation/ABI/testing/sysfs-class-net-phydev-2-Date:\t\tMay 2017\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev=5=Description:\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev-8-\nDocumentation/ABI/testing/sysfs-class-net-phydev:9:What:\t\t/sys/class/mdio_bus/\u003cbus\u003e/\u003cdevice\u003e/phy_has_fixups\nDocumentation/ABI/testing/sysfs-class-net-phydev-10-Date:\t\tFebruary 2014\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev=13=Description:\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev-18-\nDocumentation/ABI/testing/sysfs-class-net-phydev:19:What:\t\t/sys/class/mdio_bus/\u003cbus\u003e/\u003cdevice\u003e/phy_id\nDocumentation/ABI/testing/sysfs-class-net-phydev-20-Date:\t\tNovember 2012\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev=23=Description:\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev-28-\nDocumentation/ABI/testing/sysfs-class-net-phydev:29:What:\t\t/sys/class/mdio_bus/\u003cbus\u003e/\u003cdevice\u003e/c45_phy_ids/mmd\u003cn\u003e_device_id\nDocumentation/ABI/testing/sysfs-class-net-phydev-30-Date:\t\tJune 2025\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev=33=Description:\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev-38-\nDocumentation/ABI/testing/sysfs-class-net-phydev:39:What:\t\t/sys/class/mdio_bus/\u003cbus\u003e/\u003cdevice\u003e/phy_interface\nDocumentation/ABI/testing/sysfs-class-net-phydev-40-Date:\t\tFebruary 2014\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev=43=Description:\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev-55-\nDocumentation/ABI/testing/sysfs-class-net-phydev:56:What:\t\t/sys/class/mdio_bus/\u003cbus\u003e/\u003cdevice\u003e/phy_standalone\nDocumentation/ABI/testing/sysfs-class-net-phydev-57-Date:\t\tMay 2019\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev=60=Description:\n--\nDocumentation/ABI/testing/sysfs-class-net-phydev-64-\nDocumentation/ABI/testing/sysfs-class-net-phydev:65:What:\t\t/sys/class/mdio_bus/\u003cbus\u003e/\u003cdevice\u003e/phy_dev_flags\nDocumentation/ABI/testing/sysfs-class-net-phydev-66-Date:\t\tMarch 2021\n--\nDocumentation/networking/device_drivers/ethernet/stmicro/stmmac.rst=352=finds::\n--\nDocumentation/networking/device_drivers/ethernet/stmicro/stmmac.rst-361-\nDocumentation/networking/device_drivers/ethernet/stmicro/stmmac.rst:362:        struct stmmac_mdio_bus_data *mdio_bus_data;\nDocumentation/networking/device_drivers/ethernet/stmicro/stmmac.rst-363-\n--\nDocumentation/networking/device_drivers/ethernet/stmicro/stmmac.rst=502=For MDIO bus data, we have:\n--\nDocumentation/networking/device_drivers/ethernet/stmicro/stmmac.rst-505-\nDocumentation/networking/device_drivers/ethernet/stmicro/stmmac.rst:506:    struct stmmac_mdio_bus_data {\nDocumentation/networking/device_drivers/ethernet/stmicro/stmmac.rst-507-\n--\nDocumentation/networking/dsa/dsa.rst=432=DSA currently leverages the following subsystems:\nDocumentation/networking/dsa/dsa.rst-433-\nDocumentation/networking/dsa/dsa.rst:434:- MDIO/PHY library: ``drivers/net/phy/phy.c``, ``mdio_bus.c``\nDocumentation/networking/dsa/dsa.rst-435-- Switchdev:``net/switchdev/*``\n--\nDocumentation/networking/kapi.rst=110=PHY Support\n--\nDocumentation/networking/kapi.rst-133-\nDocumentation/networking/kapi.rst:134:.. kernel-doc:: drivers/net/phy/mdio_bus.c\nDocumentation/networking/kapi.rst-135-   :export:\nDocumentation/networking/kapi.rst-136-\nDocumentation/networking/kapi.rst:137:.. kernel-doc:: drivers/net/phy/mdio_bus.c\nDocumentation/networking/kapi.rst-138-   :internal:\n--\narch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts=108=\tgmac1: mac@1 {\n--\narch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts-115-\narch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts:116:\u0026mdio_bus {\narch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts-117-\tphy15: ethernet-phy@f {\n--\narch/arm64/boot/dts/mediatek/mt7981b.dtsi=431=\t\teth: ethernet@15100000 {\n--\narch/arm64/boot/dts/mediatek/mt7981b.dtsi-476-\narch/arm64/boot/dts/mediatek/mt7981b.dtsi:477:\t\t\tmdio_bus: mdio-bus {\narch/arm64/boot/dts/mediatek/mt7981b.dtsi-478-\t\t\t\t#address-cells = \u003c1\u003e;\n--\narch/arm64/boot/dts/mediatek/mt7988a.dtsi=988=\t\t\tgmac2: mac@2 {\n--\narch/arm64/boot/dts/mediatek/mt7988a.dtsi-993-\narch/arm64/boot/dts/mediatek/mt7988a.dtsi:994:\t\t\tmdio_bus: mdio-bus {\narch/arm64/boot/dts/mediatek/mt7988a.dtsi-995-\t\t\t\t#address-cells = \u003c1\u003e;\n--\ndrivers/net/dsa/microchip/ksz9477.c=321=static int ksz9477_pcs_create(struct ksz_device *dev)\n--\ndrivers/net/dsa/microchip/ksz9477.c-332-\ndrivers/net/dsa/microchip/ksz9477.c:333:\tbus-\u003ename = \"ksz_pcs_mdio_bus\";\ndrivers/net/dsa/microchip/ksz9477.c-334-\tsnprintf(bus-\u003eid, MII_BUS_ID_SIZE, \"%s-pcs\",\n--\ndrivers/net/dsa/microchip/ksz_common.c=2125=int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum)\n--\ndrivers/net/dsa/microchip/ksz_common.c-2128-\ndrivers/net/dsa/microchip/ksz_common.c:2129:\treturn mdiobus_read_nested(dev-\u003eparent_mdio_bus, addr, regnum);\ndrivers/net/dsa/microchip/ksz_common.c-2130-}\n--\ndrivers/net/dsa/microchip/ksz_common.c=2145=int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)\n--\ndrivers/net/dsa/microchip/ksz_common.c-2148-\ndrivers/net/dsa/microchip/ksz_common.c:2149:\treturn mdiobus_write_nested(dev-\u003eparent_mdio_bus, addr, regnum, val);\ndrivers/net/dsa/microchip/ksz_common.c-2150-}\n--\ndrivers/net/dsa/microchip/ksz_common.c=2321=int ksz_mdio_register(struct ksz_device *dev)\n--\ndrivers/net/dsa/microchip/ksz_common.c-2347-\ndrivers/net/dsa/microchip/ksz_common.c:2348:\t\tdev-\u003eparent_mdio_bus = parent_bus;\ndrivers/net/dsa/microchip/ksz_common.c-2349-\t}\n--\ndrivers/net/dsa/microchip/ksz_common.h=206=struct ksz_device {\n--\ndrivers/net/dsa/microchip/ksz_common.h-258-\t/**\ndrivers/net/dsa/microchip/ksz_common.h:259:\t * @parent_mdio_bus: Pointer to the external MDIO bus controller.\ndrivers/net/dsa/microchip/ksz_common.h-260-\t *\n--\ndrivers/net/dsa/microchip/ksz_common.h-265-\t */\ndrivers/net/dsa/microchip/ksz_common.h:266:\tstruct mii_bus *parent_mdio_bus;\ndrivers/net/dsa/microchip/ksz_common.h-267-\n--\ndrivers/net/dsa/microchip/lan937x_main.c=143=static int lan937x_create_phy_addr_map(struct ksz_device *dev, bool side_mdio)\n--\ndrivers/net/dsa/microchip/lan937x_main.c-210-/**\ndrivers/net/dsa/microchip/lan937x_main.c:211: * lan937x_mdio_bus_preinit - Pre-initialize MDIO bus for accessing PHYs.\ndrivers/net/dsa/microchip/lan937x_main.c-212- * @dev: Pointer to device structure.\n--\ndrivers/net/dsa/microchip/lan937x_main.c-226- */\ndrivers/net/dsa/microchip/lan937x_main.c:227:static int lan937x_mdio_bus_preinit(struct ksz_device *dev, bool side_mdio)\ndrivers/net/dsa/microchip/lan937x_main.c-228-{\n--\ndrivers/net/dsa/microchip/lan937x_main.c=685=static int lan937x_mdio_register(struct ksz_device *dev)\n--\ndrivers/net/dsa/microchip/lan937x_main.c-711-\ndrivers/net/dsa/microchip/lan937x_main.c:712:\t\tdev-\u003eparent_mdio_bus = parent_bus;\ndrivers/net/dsa/microchip/lan937x_main.c-713-\t}\n--\ndrivers/net/dsa/microchip/lan937x_main.c-720-\ndrivers/net/dsa/microchip/lan937x_main.c:721:\tret = lan937x_mdio_bus_preinit(dev, !!parent_bus);\ndrivers/net/dsa/microchip/lan937x_main.c-722-\tif (ret)\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=126=int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-132-\ndrivers/net/dsa/mv88e6xxx/chip.c:133:struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)\ndrivers/net/dsa/mv88e6xxx/chip.c-134-{\ndrivers/net/dsa/mv88e6xxx/chip.c:135:\tstruct mv88e6xxx_mdio_bus *mdio_bus;\ndrivers/net/dsa/mv88e6xxx/chip.c-136-\ndrivers/net/dsa/mv88e6xxx/chip.c:137:\tmdio_bus = list_first_entry_or_null(\u0026chip-\u003emdios,\ndrivers/net/dsa/mv88e6xxx/chip.c:138:\t\t\t\t\t    struct mv88e6xxx_mdio_bus, list);\ndrivers/net/dsa/mv88e6xxx/chip.c:139:\tif (!mdio_bus)\ndrivers/net/dsa/mv88e6xxx/chip.c-140-\t\treturn NULL;\ndrivers/net/dsa/mv88e6xxx/chip.c-141-\ndrivers/net/dsa/mv88e6xxx/chip.c:142:\treturn mdio_bus-\u003ebus;\ndrivers/net/dsa/mv88e6xxx/chip.c-143-}\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=3757=static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)\ndrivers/net/dsa/mv88e6xxx/chip.c-3758-{\ndrivers/net/dsa/mv88e6xxx/chip.c:3759:\tstruct mv88e6xxx_mdio_bus *mdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/chip.c:3760:\tstruct mv88e6xxx_chip *chip = mdio_bus-\u003echip;\ndrivers/net/dsa/mv88e6xxx/chip.c-3761-\tu16 prod_id;\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=3783=static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-3785-{\ndrivers/net/dsa/mv88e6xxx/chip.c:3786:\tstruct mv88e6xxx_mdio_bus *mdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/chip.c:3787:\tstruct mv88e6xxx_chip *chip = mdio_bus-\u003echip;\ndrivers/net/dsa/mv88e6xxx/chip.c-3788-\tu16 val;\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=3801=static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)\ndrivers/net/dsa/mv88e6xxx/chip.c-3802-{\ndrivers/net/dsa/mv88e6xxx/chip.c:3803:\tstruct mv88e6xxx_mdio_bus *mdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/chip.c:3804:\tstruct mv88e6xxx_chip *chip = mdio_bus-\u003echip;\ndrivers/net/dsa/mv88e6xxx/chip.c-3805-\tint err;\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=3817=static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-3819-{\ndrivers/net/dsa/mv88e6xxx/chip.c:3820:\tstruct mv88e6xxx_mdio_bus *mdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/chip.c:3821:\tstruct mv88e6xxx_chip *chip = mdio_bus-\u003echip;\ndrivers/net/dsa/mv88e6xxx/chip.c-3822-\tint err;\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=3834=static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-3838-\tstatic int index;\ndrivers/net/dsa/mv88e6xxx/chip.c:3839:\tstruct mv88e6xxx_mdio_bus *mdio_bus;\ndrivers/net/dsa/mv88e6xxx/chip.c-3840-\tstruct mii_bus *bus;\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-3854-\ndrivers/net/dsa/mv88e6xxx/chip.c:3855:\tbus = mdiobus_alloc_size(sizeof(*mdio_bus));\ndrivers/net/dsa/mv88e6xxx/chip.c-3856-\tif (!bus)\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-3858-\ndrivers/net/dsa/mv88e6xxx/chip.c:3859:\tmdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/chip.c:3860:\tmdio_bus-\u003ebus = bus;\ndrivers/net/dsa/mv88e6xxx/chip.c:3861:\tmdio_bus-\u003echip = chip;\ndrivers/net/dsa/mv88e6xxx/chip.c:3862:\tINIT_LIST_HEAD(\u0026mdio_bus-\u003elist);\ndrivers/net/dsa/mv88e6xxx/chip.c:3863:\tmdio_bus-\u003eexternal = external;\ndrivers/net/dsa/mv88e6xxx/chip.c-3864-\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-3895-\tif (external)\ndrivers/net/dsa/mv88e6xxx/chip.c:3896:\t\tlist_add_tail(\u0026mdio_bus-\u003elist, \u0026chip-\u003emdios);\ndrivers/net/dsa/mv88e6xxx/chip.c-3897-\telse\ndrivers/net/dsa/mv88e6xxx/chip.c:3898:\t\tlist_add(\u0026mdio_bus-\u003elist, \u0026chip-\u003emdios);\ndrivers/net/dsa/mv88e6xxx/chip.c-3899-\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=3907=static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-3909-{\ndrivers/net/dsa/mv88e6xxx/chip.c:3910:\tstruct mv88e6xxx_mdio_bus *mdio_bus, *p;\ndrivers/net/dsa/mv88e6xxx/chip.c-3911-\tstruct mii_bus *bus;\ndrivers/net/dsa/mv88e6xxx/chip.c-3912-\ndrivers/net/dsa/mv88e6xxx/chip.c:3913:\tlist_for_each_entry_safe(mdio_bus, p, \u0026chip-\u003emdios, list) {\ndrivers/net/dsa/mv88e6xxx/chip.c:3914:\t\tbus = mdio_bus-\u003ebus;\ndrivers/net/dsa/mv88e6xxx/chip.c-3915-\ndrivers/net/dsa/mv88e6xxx/chip.c:3916:\t\tif (!mdio_bus-\u003eexternal)\ndrivers/net/dsa/mv88e6xxx/chip.c-3917-\t\t\tmv88e6xxx_g2_irq_mdio_free(chip, bus);\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=3980=static int mv88e6xxx_setup(struct dsa_switch *ds)\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-3991-\tchip-\u003eds = ds;\ndrivers/net/dsa/mv88e6xxx/chip.c:3992:\tds-\u003euser_mii_bus = mv88e6xxx_default_mdio_bus(chip);\ndrivers/net/dsa/mv88e6xxx/chip.c-3993-\n--\ndrivers/net/dsa/mv88e6xxx/chip.h=488=struct mv88e6xxx_bus_ops {\n--\ndrivers/net/dsa/mv88e6xxx/chip.h-493-\ndrivers/net/dsa/mv88e6xxx/chip.h:494:struct mv88e6xxx_mdio_bus {\ndrivers/net/dsa/mv88e6xxx/chip.h-495-\tstruct mii_bus *bus;\n--\ndrivers/net/dsa/mv88e6xxx/chip.h=873=int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,\ndrivers/net/dsa/mv88e6xxx/chip.h-874-\t\t       int bit, int val);\ndrivers/net/dsa/mv88e6xxx/chip.h:875:struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);\ndrivers/net/dsa/mv88e6xxx/chip.h-876-\n--\ndrivers/net/dsa/mv88e6xxx/global2.c=787=int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip,\n--\ndrivers/net/dsa/mv88e6xxx/global2.c-790-{\ndrivers/net/dsa/mv88e6xxx/global2.c:791:\tstruct mv88e6xxx_mdio_bus *mdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/global2.c:792:\tbool external = mdio_bus-\u003eexternal;\ndrivers/net/dsa/mv88e6xxx/global2.c-793-\n--\ndrivers/net/dsa/mv88e6xxx/global2.c=798=int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,\n--\ndrivers/net/dsa/mv88e6xxx/global2.c-801-{\ndrivers/net/dsa/mv88e6xxx/global2.c:802:\tstruct mv88e6xxx_mdio_bus *mdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/global2.c:803:\tbool external = mdio_bus-\u003eexternal;\ndrivers/net/dsa/mv88e6xxx/global2.c-804-\n--\ndrivers/net/dsa/mv88e6xxx/global2.c=809=int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip,\n--\ndrivers/net/dsa/mv88e6xxx/global2.c-812-{\ndrivers/net/dsa/mv88e6xxx/global2.c:813:\tstruct mv88e6xxx_mdio_bus *mdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/global2.c:814:\tbool external = mdio_bus-\u003eexternal;\ndrivers/net/dsa/mv88e6xxx/global2.c-815-\n--\ndrivers/net/dsa/mv88e6xxx/global2.c=820=int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,\n--\ndrivers/net/dsa/mv88e6xxx/global2.c-823-{\ndrivers/net/dsa/mv88e6xxx/global2.c:824:\tstruct mv88e6xxx_mdio_bus *mdio_bus = bus-\u003epriv;\ndrivers/net/dsa/mv88e6xxx/global2.c:825:\tbool external = mdio_bus-\u003eexternal;\ndrivers/net/dsa/mv88e6xxx/global2.c-826-\n--\ndrivers/net/dsa/mv88e6xxx/pcs-6352.c=321=static int mv88e6352_pcs_init(struct mv88e6xxx_chip *chip, int port)\n--\ndrivers/net/dsa/mv88e6xxx/pcs-6352.c-333-\tirq = mv88e6xxx_serdes_irq_mapping(chip, port);\ndrivers/net/dsa/mv88e6xxx/pcs-6352.c:334:\tbus = mv88e6xxx_default_mdio_bus(chip);\ndrivers/net/dsa/mv88e6xxx/pcs-6352.c-335-\tdev = chip-\u003edev;\n--\ndrivers/net/dsa/mv88e6xxx/pcs-639x.c=549=static int mv88e6390_pcs_init(struct mv88e6xxx_chip *chip, int port)\n--\ndrivers/net/dsa/mv88e6xxx/pcs-639x.c-559-\ndrivers/net/dsa/mv88e6xxx/pcs-639x.c:560:\tbus = mv88e6xxx_default_mdio_bus(chip);\ndrivers/net/dsa/mv88e6xxx/pcs-639x.c-561-\tdev = chip-\u003edev;\n--\ndrivers/net/dsa/mv88e6xxx/pcs-639x.c=927=static int mv88e6393x_pcs_init(struct mv88e6xxx_chip *chip, int port)\n--\ndrivers/net/dsa/mv88e6xxx/pcs-639x.c-937-\ndrivers/net/dsa/mv88e6xxx/pcs-639x.c:938:\tbus = mv88e6xxx_default_mdio_bus(chip);\ndrivers/net/dsa/mv88e6xxx/pcs-639x.c-939-\tdev = chip-\u003edev;\n--\ndrivers/net/dsa/mv88e6xxx/phy.c=28=int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, int reg, u16 *val)\n--\ndrivers/net/dsa/mv88e6xxx/phy.c-32-\ndrivers/net/dsa/mv88e6xxx/phy.c:33:\tbus = mv88e6xxx_default_mdio_bus(chip);\ndrivers/net/dsa/mv88e6xxx/phy.c-34-\tif (!bus)\n--\ndrivers/net/dsa/mv88e6xxx/phy.c=43=int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, int reg, u16 val)\n--\ndrivers/net/dsa/mv88e6xxx/phy.c-47-\ndrivers/net/dsa/mv88e6xxx/phy.c:48:\tbus = mv88e6xxx_default_mdio_bus(chip);\ndrivers/net/dsa/mv88e6xxx/phy.c-49-\tif (!bus)\n--\ndrivers/net/dsa/mv88e6xxx/phy.c=58=int mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad,\n--\ndrivers/net/dsa/mv88e6xxx/phy.c-63-\ndrivers/net/dsa/mv88e6xxx/phy.c:64:\tbus = mv88e6xxx_default_mdio_bus(chip);\ndrivers/net/dsa/mv88e6xxx/phy.c-65-\tif (!bus)\n--\ndrivers/net/dsa/mv88e6xxx/phy.c=74=int mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int devad,\n--\ndrivers/net/dsa/mv88e6xxx/phy.c-79-\ndrivers/net/dsa/mv88e6xxx/phy.c:80:\tbus = mv88e6xxx_default_mdio_bus(chip);\ndrivers/net/dsa/mv88e6xxx/phy.c-81-\tif (!bus)\n--\ndrivers/net/dsa/netc/netc_main.c=133=static int netc_port_get_info_from_dt(struct netc_port *np,\n--\ndrivers/net/dsa/netc/netc_main.c-148-\ndrivers/net/dsa/netc/netc_main.c:149:static int netc_port_create_emdio_bus(struct netc_port *np,\ndrivers/net/dsa/netc/netc_main.c-150-\t\t\t\t      struct device_node *node)\n--\ndrivers/net/dsa/netc/netc_main.c-189-\ndrivers/net/dsa/netc/netc_main.c:190:static int netc_port_create_mdio_bus(struct netc_port *np,\ndrivers/net/dsa/netc/netc_main.c-191-\t\t\t\t     struct device_node *node)\n--\ndrivers/net/dsa/netc/netc_main.c-197-\tif (mdio_node) {\ndrivers/net/dsa/netc/netc_main.c:198:\t\terr = netc_port_create_emdio_bus(np, mdio_node);\ndrivers/net/dsa/netc/netc_main.c-199-\t\tof_node_put(mdio_node);\n--\ndrivers/net/dsa/netc/netc_main.c=241=static int netc_init_all_ports(struct netc_switch *priv)\n--\ndrivers/net/dsa/netc/netc_main.c-283-\t\tif (dsa_port_is_user(dp)) {\ndrivers/net/dsa/netc/netc_main.c:284:\t\t\terr = netc_port_create_mdio_bus(np, dp-\u003edn);\ndrivers/net/dsa/netc/netc_main.c-285-\t\t\tif (err) {\n--\ndrivers/net/dsa/ocelot/felix.c=1517=static int felix_init_structs(struct felix *felix, int num_phys_ports)\n--\ndrivers/net/dsa/ocelot/felix.c-1602-\ndrivers/net/dsa/ocelot/felix.c:1603:\tif (felix-\u003einfo-\u003emdio_bus_alloc) {\ndrivers/net/dsa/ocelot/felix.c:1604:\t\terr = felix-\u003einfo-\u003emdio_bus_alloc(ocelot);\ndrivers/net/dsa/ocelot/felix.c-1605-\t\tif (err \u003c 0)\n--\ndrivers/net/dsa/ocelot/felix.c=1696=static int felix_setup(struct dsa_switch *ds)\n--\ndrivers/net/dsa/ocelot/felix.c-1768-out_mdiobus_free:\ndrivers/net/dsa/ocelot/felix.c:1769:\tif (felix-\u003einfo-\u003emdio_bus_free)\ndrivers/net/dsa/ocelot/felix.c:1770:\t\tfelix-\u003einfo-\u003emdio_bus_free(ocelot);\ndrivers/net/dsa/ocelot/felix.c-1771-\n--\ndrivers/net/dsa/ocelot/felix.c=1775=static void felix_teardown(struct dsa_switch *ds)\n--\ndrivers/net/dsa/ocelot/felix.c-1792-\ndrivers/net/dsa/ocelot/felix.c:1793:\tif (felix-\u003einfo-\u003emdio_bus_free)\ndrivers/net/dsa/ocelot/felix.c:1794:\t\tfelix-\u003einfo-\u003emdio_bus_free(ocelot);\ndrivers/net/dsa/ocelot/felix.c-1795-}\n--\ndrivers/net/dsa/ocelot/felix.h=22=struct felix_info {\n--\ndrivers/net/dsa/ocelot/felix.h-55-\ndrivers/net/dsa/ocelot/felix.h:56:\tint\t(*mdio_bus_alloc)(struct ocelot *ocelot);\ndrivers/net/dsa/ocelot/felix.h:57:\tvoid\t(*mdio_bus_free)(struct ocelot *ocelot);\ndrivers/net/dsa/ocelot/felix.h-58-\tint\t(*port_setup_tc)(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/ocelot/felix_vsc9959.c=951=static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)\n--\ndrivers/net/dsa/ocelot/felix_vsc9959.c-956-\ndrivers/net/dsa/ocelot/felix_vsc9959.c:957:static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)\ndrivers/net/dsa/ocelot/felix_vsc9959.c-958-{\n--\ndrivers/net/dsa/ocelot/felix_vsc9959.c-1044-\ndrivers/net/dsa/ocelot/felix_vsc9959.c:1045:static void vsc9959_mdio_bus_free(struct ocelot *ocelot)\ndrivers/net/dsa/ocelot/felix_vsc9959.c-1046-{\n--\ndrivers/net/dsa/ocelot/felix_vsc9959.c=2659=static const struct felix_info felix_info_vsc9959 = {\n--\ndrivers/net/dsa/ocelot/felix_vsc9959.c-2675-\t.ptp_caps\t\t= \u0026vsc9959_ptp_caps,\ndrivers/net/dsa/ocelot/felix_vsc9959.c:2676:\t.mdio_bus_alloc\t\t= vsc9959_mdio_bus_alloc,\ndrivers/net/dsa/ocelot/felix_vsc9959.c:2677:\t.mdio_bus_free\t\t= vsc9959_mdio_bus_free,\ndrivers/net/dsa/ocelot/felix_vsc9959.c-2678-\t.port_modes\t\t= vsc9959_port_modes,\n--\ndrivers/net/dsa/ocelot/seville_vsc9953.c=869=static const struct ocelot_ops vsc9953_ops = {\n--\ndrivers/net/dsa/ocelot/seville_vsc9953.c-877-\ndrivers/net/dsa/ocelot/seville_vsc9953.c:878:static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot)\ndrivers/net/dsa/ocelot/seville_vsc9953.c-879-{\n--\ndrivers/net/dsa/ocelot/seville_vsc9953.c-934-\ndrivers/net/dsa/ocelot/seville_vsc9953.c:935:static void vsc9953_mdio_bus_free(struct ocelot *ocelot)\ndrivers/net/dsa/ocelot/seville_vsc9953.c-936-{\n--\ndrivers/net/dsa/ocelot/seville_vsc9953.c=950=static const struct felix_info seville_info_vsc9953 = {\n--\ndrivers/net/dsa/ocelot/seville_vsc9953.c-964-\t.num_ports\t\t= VSC9953_NUM_PORTS,\ndrivers/net/dsa/ocelot/seville_vsc9953.c:965:\t.mdio_bus_alloc\t\t= vsc9953_mdio_bus_alloc,\ndrivers/net/dsa/ocelot/seville_vsc9953.c:966:\t.mdio_bus_free\t\t= vsc9953_mdio_bus_free,\ndrivers/net/dsa/ocelot/seville_vsc9953.c-967-\t.port_modes\t\t= vsc9953_port_modes,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=807=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:808:qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)\ndrivers/net/dsa/qca/qca8k-8xxx.c-809-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=830=qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-854-\ndrivers/net/dsa/qca/qca8k-8xxx.c:855:\tret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,\ndrivers/net/dsa/qca/qca8k-8xxx.c-856-\t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=868=qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-891-\ndrivers/net/dsa/qca/qca8k-8xxx.c:892:\tret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,\ndrivers/net/dsa/qca/qca8k-8xxx.c-893-\t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=961=qca8k_mdio_register(struct qca8k_priv *priv)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-978-\ndrivers/net/dsa/qca/qca8k-8xxx.c:979:\tpriv-\u003einternal_mdio_bus = bus;\ndrivers/net/dsa/qca/qca8k-8xxx.c-980-\tbus-\u003epriv = (void *)priv;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=1008=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:1009:qca8k_setup_mdio_bus(struct qca8k_priv *priv)\ndrivers/net/dsa/qca/qca8k-8xxx.c-1010-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=1857=qca8k_setup(struct dsa_switch *ds)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-1874-\ndrivers/net/dsa/qca/qca8k-8xxx.c:1875:\tret = qca8k_setup_mdio_bus(priv);\ndrivers/net/dsa/qca/qca8k-8xxx.c-1876-\tif (ret)\n--\ndrivers/net/dsa/qca/qca8k-leds.c=365=qca8k_parse_port_leds(struct qca8k_priv *priv, struct fwnode_handle *port, int port_num)\n--\ndrivers/net/dsa/qca/qca8k-leds.c-431-\t\tinit_data.devicename = kasprintf(GFP_KERNEL, \"%s:0%d\",\ndrivers/net/dsa/qca/qca8k-leds.c:432:\t\t\t\t\t\t priv-\u003einternal_mdio_bus ?\ndrivers/net/dsa/qca/qca8k-leds.c:433:\t\t\t\t\t\t priv-\u003einternal_mdio_bus-\u003eid : priv-\u003ebus-\u003eid,\ndrivers/net/dsa/qca/qca8k-leds.c-434-\t\t\t\t\t\t port_num);\n--\ndrivers/net/dsa/qca/qca8k.h=445=struct qca8k_priv {\n--\ndrivers/net/dsa/qca/qca8k.h-458-\tstruct mii_bus *bus;\ndrivers/net/dsa/qca/qca8k.h:459:\tstruct mii_bus *internal_mdio_bus;\ndrivers/net/dsa/qca/qca8k.h-460-\tstruct dsa_switch *ds;\n--\ndrivers/net/dsa/vitesse-vsc73xx-core.c=521=static int vsc73xx_detect(struct vsc73xx *vsc)\n--\ndrivers/net/dsa/vitesse-vsc73xx-core.c-604-\ndrivers/net/dsa/vitesse-vsc73xx-core.c:605:static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc)\ndrivers/net/dsa/vitesse-vsc73xx-core.c-606-{\n--\ndrivers/net/dsa/vitesse-vsc73xx-core.c=621=static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum)\n--\ndrivers/net/dsa/vitesse-vsc73xx-core.c-627-\ndrivers/net/dsa/vitesse-vsc73xx-core.c:628:\tret = vsc73xx_mdio_busy_check(vsc);\ndrivers/net/dsa/vitesse-vsc73xx-core.c-629-\tif (ret)\n--\n\n"
}

gemini-3.1-pro-preview

null

null

							input: 18859
							output: 18
							thoughts: 205
						

**MDIO & QCA8K Driver Fuzzing - A Quick Assessment**

Okay, so syzkaller *might* be able to touch MDIO. But wait, MDIO itself is just a bus, right? It's not a driver in the way we usually think of them. My immediate thought is, does QEMU even *have* an MDIO emulator? Yeah, some SoCs do, that's right. However, I'm pretty sure syzkaller usually bypasses hardware specific drivers unless there's a netlink/sysfs interface or a dummy driver available.

Right, let's see if we can even *reach* `qca8k-8xxx.c`. Is there a clever way to instantiate it with a device tree overlay within the syzkaller context? I remember `syz_mount_image`, or something similar, but that typically won't instantiate random platform devices or MDIO devices unless there's a dedicated pseudo-syscall.

Hang on... I should be thinking more broadly. Syzkaller has `syz_genetlink_get_family` and `syz_open_dev` and so on, right? So it might be possible.

Okay, let's cut the speculation. Time to just check the syzkaller descriptions. I need to see if there's *any* mention of MDIO or the QCA8K family. That's the first step.

{
  "Expression": "qca8k"
}

{
  "Output": "\nFull output is too long, showing 500 out of 1999 lines.\nUse more precise expression if possible.\n\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml-3----\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:4:$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml=13=description: |\n--\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml-17-  See also::\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:18:    include/dt-bindings/clock/qcom,qca8k-nsscc.h\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:19:    include/dt-bindings/reset/qcom,qca8k-nsscc.h\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml-20-\n--\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml=63=examples:\n--\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml-74-        clocks = \u003c\u0026pcs0_pll\u003e,\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:75:                 \u003c\u0026qca8k_uniphy0_rx\u003e,\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:76:                 \u003c\u0026qca8k_uniphy0_tx\u003e,\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:77:                 \u003c\u0026qca8k_uniphy1_rx\u003e,\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:78:                 \u003c\u0026qca8k_uniphy1_tx\u003e,\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:79:                 \u003c\u0026qca8k_uniphy1_rx312p5m\u003e,\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml:80:                 \u003c\u0026qca8k_uniphy1_tx312p5m\u003e;\nDocumentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml-81-        #clock-cells = \u003c1\u003e;\n--\nDocumentation/devicetree/bindings/net/dsa/qca8k.yaml-3----\nDocumentation/devicetree/bindings/net/dsa/qca8k.yaml:4:$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#\nDocumentation/devicetree/bindings/net/dsa/qca8k.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\ndrivers/clk/qcom/Kconfig=503=config IPQ_NSSCC_QCA8K\n--\ndrivers/clk/qcom/Kconfig-509-\t  Say Y or M if you want to use network features of switch or\ndrivers/clk/qcom/Kconfig:510:\t  PHY device. Select this for the root clock of qca8k.\ndrivers/clk/qcom/Kconfig-511-\n--\ndrivers/clk/qcom/Makefile=67=obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o\ndrivers/clk/qcom/Makefile:68:obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o\ndrivers/clk/qcom/Makefile-69-obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o\n--\ndrivers/clk/qcom/nsscc-qca8k.c-15-\ndrivers/clk/qcom/nsscc-qca8k.c:16:#include \u003cdt-bindings/clock/qcom,qca8k-nsscc.h\u003e\ndrivers/clk/qcom/nsscc-qca8k.c:17:#include \u003cdt-bindings/reset/qcom,qca8k-nsscc.h\u003e\ndrivers/clk/qcom/nsscc-qca8k.c-18-\n--\ndrivers/clk/qcom/nsscc-qca8k.c=1819=static struct clk_branch nss_cc_gephy3_sys_clk = {\n--\ndrivers/clk/qcom/nsscc-qca8k.c-1835-\ndrivers/clk/qcom/nsscc-qca8k.c:1836:static struct clk_regmap *nss_cc_qca8k_clocks[] = {\ndrivers/clk/qcom/nsscc-qca8k.c-1837-\t[NSS_CC_SWITCH_CORE_CLK_SRC] = \u0026nss_cc_switch_core_clk_src.clkr,\n--\ndrivers/clk/qcom/nsscc-qca8k.c-1938-\ndrivers/clk/qcom/nsscc-qca8k.c:1939:static const struct qcom_reset_map nss_cc_qca8k_resets[] = {\ndrivers/clk/qcom/nsscc-qca8k.c-1940-\t[NSS_CC_SWITCH_CORE_ARES] = { 0xc, 2 },\n--\ndrivers/clk/qcom/nsscc-qca8k.c=2024=static inline void convert_reg_to_mii_addr(u32 regaddr, u16 *reg, u16 *phy_addr, u16 *page)\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2030-\ndrivers/clk/qcom/nsscc-qca8k.c:2031:static int qca8k_mii_read(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 *val)\ndrivers/clk/qcom/nsscc-qca8k.c-2032-{\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2044-\tif (ret \u003c 0)\ndrivers/clk/qcom/nsscc-qca8k.c:2045:\t\tdev_err_ratelimited(\u0026bus-\u003edev, \"fail to read qca8k mii register\\n\");\ndrivers/clk/qcom/nsscc-qca8k.c-2046-\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2049-\ndrivers/clk/qcom/nsscc-qca8k.c:2050:static void qca8k_mii_write(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 val)\ndrivers/clk/qcom/nsscc-qca8k.c-2051-{\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2059-\tif (ret \u003c 0)\ndrivers/clk/qcom/nsscc-qca8k.c:2060:\t\tdev_err_ratelimited(\u0026bus-\u003edev, \"fail to write qca8k mii register\\n\");\ndrivers/clk/qcom/nsscc-qca8k.c-2061-}\ndrivers/clk/qcom/nsscc-qca8k.c-2062-\ndrivers/clk/qcom/nsscc-qca8k.c:2063:static int qca8k_mii_page_set(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u16 page)\ndrivers/clk/qcom/nsscc-qca8k.c-2064-{\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2073-\ndrivers/clk/qcom/nsscc-qca8k.c:2074:static int qca8k_regmap_read(void *context, unsigned int regaddr, unsigned int *val)\ndrivers/clk/qcom/nsscc-qca8k.c-2075-{\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2083-\tmutex_lock(\u0026bus-\u003emdio_lock);\ndrivers/clk/qcom/nsscc-qca8k.c:2084:\tret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page);\ndrivers/clk/qcom/nsscc-qca8k.c-2085-\tif (ret \u003c 0)\ndrivers/clk/qcom/nsscc-qca8k.c:2086:\t\tgoto qca8k_read_exit;\ndrivers/clk/qcom/nsscc-qca8k.c-2087-\ndrivers/clk/qcom/nsscc-qca8k.c:2088:\tret = qca8k_mii_read(bus, phy_addr, reg, val);\ndrivers/clk/qcom/nsscc-qca8k.c-2089-\ndrivers/clk/qcom/nsscc-qca8k.c:2090:qca8k_read_exit:\ndrivers/clk/qcom/nsscc-qca8k.c-2091-\tmutex_unlock(\u0026bus-\u003emdio_lock);\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2094-\ndrivers/clk/qcom/nsscc-qca8k.c:2095:static int qca8k_regmap_write(void *context, unsigned int regaddr, unsigned int val)\ndrivers/clk/qcom/nsscc-qca8k.c-2096-{\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2104-\tmutex_lock(\u0026bus-\u003emdio_lock);\ndrivers/clk/qcom/nsscc-qca8k.c:2105:\tret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page);\ndrivers/clk/qcom/nsscc-qca8k.c-2106-\tif (ret \u003c 0)\ndrivers/clk/qcom/nsscc-qca8k.c:2107:\t\tgoto qca8k_write_exit;\ndrivers/clk/qcom/nsscc-qca8k.c-2108-\ndrivers/clk/qcom/nsscc-qca8k.c:2109:\tqca8k_mii_write(bus, phy_addr, reg, val);\ndrivers/clk/qcom/nsscc-qca8k.c-2110-\ndrivers/clk/qcom/nsscc-qca8k.c:2111:qca8k_write_exit:\ndrivers/clk/qcom/nsscc-qca8k.c-2112-\tmutex_unlock(\u0026bus-\u003emdio_lock);\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2115-\ndrivers/clk/qcom/nsscc-qca8k.c:2116:static int qca8k_regmap_update_bits(void *context, unsigned int regaddr,\ndrivers/clk/qcom/nsscc-qca8k.c-2117-\t\t\t\t    unsigned int mask, unsigned int value)\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2127-\tmutex_lock(\u0026bus-\u003emdio_lock);\ndrivers/clk/qcom/nsscc-qca8k.c:2128:\tret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page);\ndrivers/clk/qcom/nsscc-qca8k.c-2129-\tif (ret \u003c 0)\ndrivers/clk/qcom/nsscc-qca8k.c:2130:\t\tgoto qca8k_update_exit;\ndrivers/clk/qcom/nsscc-qca8k.c-2131-\ndrivers/clk/qcom/nsscc-qca8k.c:2132:\tret = qca8k_mii_read(bus, phy_addr, reg, \u0026val);\ndrivers/clk/qcom/nsscc-qca8k.c-2133-\tif (ret \u003c 0)\ndrivers/clk/qcom/nsscc-qca8k.c:2134:\t\tgoto qca8k_update_exit;\ndrivers/clk/qcom/nsscc-qca8k.c-2135-\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2137-\tval |= value;\ndrivers/clk/qcom/nsscc-qca8k.c:2138:\tqca8k_mii_write(bus, phy_addr, reg, val);\ndrivers/clk/qcom/nsscc-qca8k.c-2139-\ndrivers/clk/qcom/nsscc-qca8k.c:2140:qca8k_update_exit:\ndrivers/clk/qcom/nsscc-qca8k.c-2141-\tmutex_unlock(\u0026bus-\u003emdio_lock);\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2144-\ndrivers/clk/qcom/nsscc-qca8k.c:2145:static const struct regmap_config nss_cc_qca8k_regmap_config = {\ndrivers/clk/qcom/nsscc-qca8k.c-2146-\t.reg_bits = 12,\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2149-\t.max_register = 0x30c,\ndrivers/clk/qcom/nsscc-qca8k.c:2150:\t.reg_read = qca8k_regmap_read,\ndrivers/clk/qcom/nsscc-qca8k.c:2151:\t.reg_write = qca8k_regmap_write,\ndrivers/clk/qcom/nsscc-qca8k.c:2152:\t.reg_update_bits = qca8k_regmap_update_bits,\ndrivers/clk/qcom/nsscc-qca8k.c-2153-\t.disable_locking = true,\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2155-\ndrivers/clk/qcom/nsscc-qca8k.c:2156:static const struct qcom_cc_desc nss_cc_qca8k_desc = {\ndrivers/clk/qcom/nsscc-qca8k.c:2157:\t.config = \u0026nss_cc_qca8k_regmap_config,\ndrivers/clk/qcom/nsscc-qca8k.c:2158:\t.clks = nss_cc_qca8k_clocks,\ndrivers/clk/qcom/nsscc-qca8k.c:2159:\t.num_clks = ARRAY_SIZE(nss_cc_qca8k_clocks),\ndrivers/clk/qcom/nsscc-qca8k.c:2160:\t.resets = nss_cc_qca8k_resets,\ndrivers/clk/qcom/nsscc-qca8k.c:2161:\t.num_resets = ARRAY_SIZE(nss_cc_qca8k_resets),\ndrivers/clk/qcom/nsscc-qca8k.c-2162-};\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2167- */\ndrivers/clk/qcom/nsscc-qca8k.c:2168:static int nss_cc_qca8k_clock_enable_and_reset(struct device *dev)\ndrivers/clk/qcom/nsscc-qca8k.c-2169-{\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2187-\ndrivers/clk/qcom/nsscc-qca8k.c:2188:static int nss_cc_qca8k_probe(struct mdio_device *mdiodev)\ndrivers/clk/qcom/nsscc-qca8k.c-2189-{\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2192-\ndrivers/clk/qcom/nsscc-qca8k.c:2193:\tret = nss_cc_qca8k_clock_enable_and_reset(\u0026mdiodev-\u003edev);\ndrivers/clk/qcom/nsscc-qca8k.c-2194-\tif (ret)\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2196-\ndrivers/clk/qcom/nsscc-qca8k.c:2197:\tregmap = devm_regmap_init(\u0026mdiodev-\u003edev, NULL, mdiodev-\u003ebus, nss_cc_qca8k_desc.config);\ndrivers/clk/qcom/nsscc-qca8k.c-2198-\tif (IS_ERR(regmap))\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2200-\ndrivers/clk/qcom/nsscc-qca8k.c:2201:\treturn qcom_cc_really_probe(\u0026mdiodev-\u003edev, \u0026nss_cc_qca8k_desc, regmap);\ndrivers/clk/qcom/nsscc-qca8k.c-2202-}\ndrivers/clk/qcom/nsscc-qca8k.c-2203-\ndrivers/clk/qcom/nsscc-qca8k.c:2204:static const struct of_device_id nss_cc_qca8k_match_table[] = {\ndrivers/clk/qcom/nsscc-qca8k.c-2205-\t{ .compatible = \"qcom,qca8084-nsscc\" },\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2207-};\ndrivers/clk/qcom/nsscc-qca8k.c:2208:MODULE_DEVICE_TABLE(of, nss_cc_qca8k_match_table);\ndrivers/clk/qcom/nsscc-qca8k.c-2209-\ndrivers/clk/qcom/nsscc-qca8k.c:2210:static struct mdio_driver nss_cc_qca8k_driver = {\ndrivers/clk/qcom/nsscc-qca8k.c-2211-\t.mdiodrv.driver = {\ndrivers/clk/qcom/nsscc-qca8k.c:2212:\t\t.name = \"qcom,qca8k-nsscc\",\ndrivers/clk/qcom/nsscc-qca8k.c:2213:\t\t.of_match_table\t= nss_cc_qca8k_match_table,\ndrivers/clk/qcom/nsscc-qca8k.c-2214-\t},\ndrivers/clk/qcom/nsscc-qca8k.c:2215:\t.probe = nss_cc_qca8k_probe,\ndrivers/clk/qcom/nsscc-qca8k.c-2216-};\ndrivers/clk/qcom/nsscc-qca8k.c-2217-\ndrivers/clk/qcom/nsscc-qca8k.c:2218:mdio_module_driver(nss_cc_qca8k_driver);\ndrivers/clk/qcom/nsscc-qca8k.c-2219-\n--\ndrivers/net/dsa/qca/Makefile=2=obj-$(CONFIG_NET_DSA_AR9331)\t+= ar9331.o\ndrivers/net/dsa/qca/Makefile:3:obj-$(CONFIG_NET_DSA_QCA8K)\t+= qca8k.o\ndrivers/net/dsa/qca/Makefile:4:qca8k-y \t\t\t+= qca8k-common.o qca8k-8xxx.o\ndrivers/net/dsa/qca/Makefile-5-ifdef CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT\ndrivers/net/dsa/qca/Makefile:6:qca8k-y\t\t\t\t+= qca8k-leds.o\ndrivers/net/dsa/qca/Makefile-7-endif\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-23-\ndrivers/net/dsa/qca/qca8k-8xxx.c:24:#include \"qca8k.h\"\ndrivers/net/dsa/qca/qca8k-8xxx.c:25:#include \"qca8k_leds.h\"\ndrivers/net/dsa/qca/qca8k-8xxx.c-26-\ndrivers/net/dsa/qca/qca8k-8xxx.c=27=static void\ndrivers/net/dsa/qca/qca8k-8xxx.c:28:qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)\ndrivers/net/dsa/qca/qca8k-8xxx.c-29-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=40=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:41:qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-42-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-49-\t\tdev_err_ratelimited(\u0026bus-\u003edev,\ndrivers/net/dsa/qca/qca8k-8xxx.c:50:\t\t\t\t    \"failed to write qca8k 32bit lo register\\n\");\ndrivers/net/dsa/qca/qca8k-8xxx.c-51-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=55=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:56:qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-57-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-64-\t\tdev_err_ratelimited(\u0026bus-\u003edev,\ndrivers/net/dsa/qca/qca8k-8xxx.c:65:\t\t\t\t    \"failed to write qca8k 32bit hi register\\n\");\ndrivers/net/dsa/qca/qca8k-8xxx.c-66-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=70=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:71:qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-72-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-83-\tdev_err_ratelimited(\u0026bus-\u003edev,\ndrivers/net/dsa/qca/qca8k-8xxx.c:84:\t\t\t    \"failed to read qca8k 32bit lo register\\n\");\ndrivers/net/dsa/qca/qca8k-8xxx.c-85-\t*val = 0;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=90=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:91:qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-92-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-103-\tdev_err_ratelimited(\u0026bus-\u003edev,\ndrivers/net/dsa/qca/qca8k-8xxx.c:104:\t\t\t    \"failed to read qca8k 32bit hi register\\n\");\ndrivers/net/dsa/qca/qca8k-8xxx.c-105-\t*val = 0;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=110=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:111:qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-112-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-117-\ndrivers/net/dsa/qca/qca8k-8xxx.c:118:\tret = qca8k_mii_read_lo(bus, phy_id, regnum, \u0026lo);\ndrivers/net/dsa/qca/qca8k-8xxx.c-119-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-121-\ndrivers/net/dsa/qca/qca8k-8xxx.c:122:\tret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, \u0026hi);\ndrivers/net/dsa/qca/qca8k-8xxx.c-123-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=132=static void\ndrivers/net/dsa/qca/qca8k-8xxx.c:133:qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-134-{\ndrivers/net/dsa/qca/qca8k-8xxx.c:135:\tif (qca8k_mii_write_lo(bus, phy_id, regnum, val) \u003c 0)\ndrivers/net/dsa/qca/qca8k-8xxx.c-136-\t\treturn;\ndrivers/net/dsa/qca/qca8k-8xxx.c-137-\ndrivers/net/dsa/qca/qca8k-8xxx.c:138:\tqca8k_mii_write_hi(bus, phy_id, regnum + 1, val);\ndrivers/net/dsa/qca/qca8k-8xxx.c-139-}\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=141=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:142:qca8k_set_page(struct qca8k_priv *priv, u16 page)\ndrivers/net/dsa/qca/qca8k-8xxx.c-143-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-153-\t\tdev_err_ratelimited(\u0026bus-\u003edev,\ndrivers/net/dsa/qca/qca8k-8xxx.c:154:\t\t\t\t    \"failed to set qca8k page\\n\");\ndrivers/net/dsa/qca/qca8k-8xxx.c-155-\t\treturn ret;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-162-\ndrivers/net/dsa/qca/qca8k-8xxx.c:163:static bool qca8k_mgmt_eth_disabled(const struct qca8k_priv *priv)\ndrivers/net/dsa/qca/qca8k-8xxx.c-164-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-167-\ndrivers/net/dsa/qca/qca8k-8xxx.c:168:static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)\ndrivers/net/dsa/qca/qca8k-8xxx.c-169-{\ndrivers/net/dsa/qca/qca8k-8xxx.c:170:\tstruct qca8k_mgmt_eth_data *mgmt_eth_data;\ndrivers/net/dsa/qca/qca8k-8xxx.c:171:\tstruct qca8k_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/qca/qca8k-8xxx.c-172-\tstruct qca_mgmt_ethhdr *mgmt_ethhdr;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-222-\ndrivers/net/dsa/qca/qca8k-8xxx.c:223:static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,\ndrivers/net/dsa/qca/qca8k-8xxx.c-224-\t\t\t\t\t       int priority, unsigned int len)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-306-\ndrivers/net/dsa/qca/qca8k-8xxx.c:307:static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)\ndrivers/net/dsa/qca/qca8k-8xxx.c-308-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-316-\ndrivers/net/dsa/qca/qca8k-8xxx.c:317:static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\ndrivers/net/dsa/qca/qca8k-8xxx.c-318-{\ndrivers/net/dsa/qca/qca8k-8xxx.c:319:\tstruct qca8k_mgmt_eth_data *mgmt_eth_data = \u0026priv-\u003emgmt_eth_data;\ndrivers/net/dsa/qca/qca8k-8xxx.c-320-\tstruct sk_buff *skb;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-323-\ndrivers/net/dsa/qca/qca8k-8xxx.c:324:\tif (qca8k_mgmt_eth_disabled(priv))\ndrivers/net/dsa/qca/qca8k-8xxx.c-325-\t\treturn -ENXIO;\ndrivers/net/dsa/qca/qca8k-8xxx.c-326-\ndrivers/net/dsa/qca/qca8k-8xxx.c:327:\tskb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,\ndrivers/net/dsa/qca/qca8k-8xxx.c-328-\t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY, len);\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-346-\tmgmt_eth_data-\u003eseq++;\ndrivers/net/dsa/qca/qca8k-8xxx.c:347:\tqca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data-\u003eseq);\ndrivers/net/dsa/qca/qca8k-8xxx.c-348-\tmgmt_eth_data-\u003eack = false;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-371-\ndrivers/net/dsa/qca/qca8k-8xxx.c:372:static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\ndrivers/net/dsa/qca/qca8k-8xxx.c-373-{\ndrivers/net/dsa/qca/qca8k-8xxx.c:374:\tstruct qca8k_mgmt_eth_data *mgmt_eth_data = \u0026priv-\u003emgmt_eth_data;\ndrivers/net/dsa/qca/qca8k-8xxx.c-375-\tstruct sk_buff *skb;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-378-\ndrivers/net/dsa/qca/qca8k-8xxx.c:379:\tif (qca8k_mgmt_eth_disabled(priv))\ndrivers/net/dsa/qca/qca8k-8xxx.c-380-\t\treturn -ENXIO;\ndrivers/net/dsa/qca/qca8k-8xxx.c-381-\ndrivers/net/dsa/qca/qca8k-8xxx.c:382:\tskb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,\ndrivers/net/dsa/qca/qca8k-8xxx.c-383-\t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY, len);\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-401-\tmgmt_eth_data-\u003eseq++;\ndrivers/net/dsa/qca/qca8k-8xxx.c:402:\tqca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data-\u003eseq);\ndrivers/net/dsa/qca/qca8k-8xxx.c-403-\tmgmt_eth_data-\u003eack = false;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=423=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:424:qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-425-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-428-\ndrivers/net/dsa/qca/qca8k-8xxx.c:429:\tret = qca8k_read_eth(priv, reg, \u0026val, sizeof(val));\ndrivers/net/dsa/qca/qca8k-8xxx.c-430-\tif (ret)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-435-\ndrivers/net/dsa/qca/qca8k-8xxx.c:436:\treturn qca8k_write_eth(priv, reg, \u0026val, sizeof(val));\ndrivers/net/dsa/qca/qca8k-8xxx.c-437-}\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=439=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:440:qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-441-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-445-\ndrivers/net/dsa/qca/qca8k-8xxx.c:446:\tqca8k_split_addr(reg, \u0026r1, \u0026r2, \u0026page);\ndrivers/net/dsa/qca/qca8k-8xxx.c-447-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-449-\ndrivers/net/dsa/qca/qca8k-8xxx.c:450:\tret = qca8k_set_page(priv, page);\ndrivers/net/dsa/qca/qca8k-8xxx.c-451-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-453-\ndrivers/net/dsa/qca/qca8k-8xxx.c:454:\tret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);\ndrivers/net/dsa/qca/qca8k-8xxx.c-455-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=461=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:462:qca8k_write_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-463-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-467-\ndrivers/net/dsa/qca/qca8k-8xxx.c:468:\tqca8k_split_addr(reg, \u0026r1, \u0026r2, \u0026page);\ndrivers/net/dsa/qca/qca8k-8xxx.c-469-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-471-\ndrivers/net/dsa/qca/qca8k-8xxx.c:472:\tret = qca8k_set_page(priv, page);\ndrivers/net/dsa/qca/qca8k-8xxx.c-473-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-475-\ndrivers/net/dsa/qca/qca8k-8xxx.c:476:\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\ndrivers/net/dsa/qca/qca8k-8xxx.c-477-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=483=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:484:qca8k_regmap_update_bits_mii(struct qca8k_priv *priv, uint32_t reg,\ndrivers/net/dsa/qca/qca8k-8xxx.c-485-\t\t\t     uint32_t mask, uint32_t write_val)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-491-\ndrivers/net/dsa/qca/qca8k-8xxx.c:492:\tqca8k_split_addr(reg, \u0026r1, \u0026r2, \u0026page);\ndrivers/net/dsa/qca/qca8k-8xxx.c-493-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-495-\ndrivers/net/dsa/qca/qca8k-8xxx.c:496:\tret = qca8k_set_page(priv, page);\ndrivers/net/dsa/qca/qca8k-8xxx.c-497-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-499-\ndrivers/net/dsa/qca/qca8k-8xxx.c:500:\tret = qca8k_mii_read32(bus, 0x10 | r2, r1, \u0026val);\ndrivers/net/dsa/qca/qca8k-8xxx.c-501-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-505-\tval |= write_val;\ndrivers/net/dsa/qca/qca8k-8xxx.c:506:\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\ndrivers/net/dsa/qca/qca8k-8xxx.c-507-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=514=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:515:qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len,\ndrivers/net/dsa/qca/qca8k-8xxx.c-516-\t\tvoid *val_buf, size_t val_len)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-518-\tint i, count = val_len / sizeof(u32), ret;\ndrivers/net/dsa/qca/qca8k-8xxx.c:519:\tstruct qca8k_priv *priv = ctx;\ndrivers/net/dsa/qca/qca8k-8xxx.c-520-\tu32 reg = *(u16 *)reg_buf;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-522-\tif (priv-\u003emgmt_conduit \u0026\u0026\ndrivers/net/dsa/qca/qca8k-8xxx.c:523:\t    !qca8k_read_eth(priv, reg, val_buf, val_len))\ndrivers/net/dsa/qca/qca8k-8xxx.c-524-\t\treturn 0;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-527-\tfor (i = 0; i \u003c count; i++, reg += sizeof(u32)) {\ndrivers/net/dsa/qca/qca8k-8xxx.c:528:\t\tret = qca8k_read_mii(priv, reg, val_buf + i);\ndrivers/net/dsa/qca/qca8k-8xxx.c-529-\t\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=536=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:537:qca8k_bulk_gather_write(void *ctx, const void *reg_buf, size_t reg_len,\ndrivers/net/dsa/qca/qca8k-8xxx.c-538-\t\t\tconst void *val_buf, size_t val_len)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-540-\tint i, count = val_len / sizeof(u32), ret;\ndrivers/net/dsa/qca/qca8k-8xxx.c:541:\tstruct qca8k_priv *priv = ctx;\ndrivers/net/dsa/qca/qca8k-8xxx.c-542-\tu32 reg = *(u16 *)reg_buf;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-545-\tif (priv-\u003emgmt_conduit \u0026\u0026\ndrivers/net/dsa/qca/qca8k-8xxx.c:546:\t    !qca8k_write_eth(priv, reg, val, val_len))\ndrivers/net/dsa/qca/qca8k-8xxx.c-547-\t\treturn 0;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-552-\tfor (i = 0; i \u003c count; i++, reg += sizeof(u32), val++) {\ndrivers/net/dsa/qca/qca8k-8xxx.c:553:\t\tret = qca8k_write_mii(priv, reg, *val);\ndrivers/net/dsa/qca/qca8k-8xxx.c-554-\t\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=561=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:562:qca8k_bulk_write(void *ctx, const void *data, size_t bytes)\ndrivers/net/dsa/qca/qca8k-8xxx.c-563-{\ndrivers/net/dsa/qca/qca8k-8xxx.c:564:\treturn qca8k_bulk_gather_write(ctx, data, sizeof(u16), data + sizeof(u16),\ndrivers/net/dsa/qca/qca8k-8xxx.c-565-\t\t\t\t       bytes - sizeof(u16));\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=568=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:569:qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-570-{\ndrivers/net/dsa/qca/qca8k-8xxx.c:571:\tstruct qca8k_priv *priv = ctx;\ndrivers/net/dsa/qca/qca8k-8xxx.c-572-\ndrivers/net/dsa/qca/qca8k-8xxx.c:573:\tif (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))\ndrivers/net/dsa/qca/qca8k-8xxx.c-574-\t\treturn 0;\ndrivers/net/dsa/qca/qca8k-8xxx.c-575-\ndrivers/net/dsa/qca/qca8k-8xxx.c:576:\treturn qca8k_regmap_update_bits_mii(priv, reg, mask, write_val);\ndrivers/net/dsa/qca/qca8k-8xxx.c-577-}\ndrivers/net/dsa/qca/qca8k-8xxx.c-578-\ndrivers/net/dsa/qca/qca8k-8xxx.c:579:static const struct regmap_config qca8k_regmap_config = {\ndrivers/net/dsa/qca/qca8k-8xxx.c-580-\t.reg_bits = 16,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-583-\t.max_register = 0x16ac, /* end MIB - Port6 range */\ndrivers/net/dsa/qca/qca8k-8xxx.c:584:\t.read = qca8k_bulk_read,\ndrivers/net/dsa/qca/qca8k-8xxx.c:585:\t.write = qca8k_bulk_write,\ndrivers/net/dsa/qca/qca8k-8xxx.c:586:\t.reg_update_bits = qca8k_regmap_update_bits,\ndrivers/net/dsa/qca/qca8k-8xxx.c:587:\t.rd_table = \u0026qca8k_readable_table,\ndrivers/net/dsa/qca/qca8k-8xxx.c:588:\t.disable_locking = true, /* Locking is handled by qca8k read/write */\ndrivers/net/dsa/qca/qca8k-8xxx.c-589-\t.cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=597=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:598:qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data,\ndrivers/net/dsa/qca/qca8k-8xxx.c-599-\t\t\tstruct sk_buff *read_skb, u32 *val)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-611-\tmgmt_eth_data-\u003eseq++;\ndrivers/net/dsa/qca/qca8k-8xxx.c:612:\tqca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data-\u003eseq);\ndrivers/net/dsa/qca/qca8k-8xxx.c-613-\tmgmt_eth_data-\u003eack = false;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=633=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:634:qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,\ndrivers/net/dsa/qca/qca8k-8xxx.c-635-\t\t      int regnum, u16 data)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-637-\tstruct sk_buff *write_skb, *clear_skb, *read_skb;\ndrivers/net/dsa/qca/qca8k-8xxx.c:638:\tstruct qca8k_mgmt_eth_data *mgmt_eth_data;\ndrivers/net/dsa/qca/qca8k-8xxx.c-639-\tu32 write_val, clear_val = 0, val;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-643-\ndrivers/net/dsa/qca/qca8k-8xxx.c:644:\tif (qca8k_mgmt_eth_disabled(priv))\ndrivers/net/dsa/qca/qca8k-8xxx.c-645-\t\treturn -ENXIO;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-663-\t/* Prealloc all the needed skb before the lock */\ndrivers/net/dsa/qca/qca8k-8xxx.c:664:\twrite_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, \u0026write_val,\ndrivers/net/dsa/qca/qca8k-8xxx.c-665-\t\t\t\t\t    QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val));\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-668-\ndrivers/net/dsa/qca/qca8k-8xxx.c:669:\tclear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, \u0026clear_val,\ndrivers/net/dsa/qca/qca8k-8xxx.c-670-\t\t\t\t\t    QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-675-\ndrivers/net/dsa/qca/qca8k-8xxx.c:676:\tread_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, \u0026clear_val,\ndrivers/net/dsa/qca/qca8k-8xxx.c-677-\t\t\t\t\t   QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-716-\tmgmt_eth_data-\u003eseq++;\ndrivers/net/dsa/qca/qca8k-8xxx.c:717:\tqca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data-\u003eseq);\ndrivers/net/dsa/qca/qca8k-8xxx.c-718-\tmgmt_eth_data-\u003eack = false;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-738-\ndrivers/net/dsa/qca/qca8k-8xxx.c:739:\tret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1,\ndrivers/net/dsa/qca/qca8k-8xxx.c-740-\t\t\t\t!(val \u0026 QCA8K_MDIO_MASTER_BUSY), 0,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-753-\t\tmgmt_eth_data-\u003eseq++;\ndrivers/net/dsa/qca/qca8k-8xxx.c:754:\t\tqca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data-\u003eseq);\ndrivers/net/dsa/qca/qca8k-8xxx.c-755-\t\tmgmt_eth_data-\u003eack = false;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-782-\tmgmt_eth_data-\u003eseq++;\ndrivers/net/dsa/qca/qca8k-8xxx.c:783:\tqca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data-\u003eseq);\ndrivers/net/dsa/qca/qca8k-8xxx.c-784-\tmgmt_eth_data-\u003eack = false;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=807=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:808:qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)\ndrivers/net/dsa/qca/qca8k-8xxx.c-809-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-813-\ndrivers/net/dsa/qca/qca8k-8xxx.c:814:\tqca8k_split_addr(reg, \u0026r1, \u0026r2, \u0026page);\ndrivers/net/dsa/qca/qca8k-8xxx.c-815-\ndrivers/net/dsa/qca/qca8k-8xxx.c:816:\tret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val \u0026 mask), 0,\ndrivers/net/dsa/qca/qca8k-8xxx.c-817-\t\t\t\tQCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-819-\ndrivers/net/dsa/qca/qca8k-8xxx.c:820:\t/* Check if qca8k_read has failed for a different reason\ndrivers/net/dsa/qca/qca8k-8xxx.c-821-\t * before returnting -ETIMEDOUT\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=829=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:830:qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)\ndrivers/net/dsa/qca/qca8k-8xxx.c-831-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-844-\ndrivers/net/dsa/qca/qca8k-8xxx.c:845:\tqca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, \u0026r1, \u0026r2, \u0026page);\ndrivers/net/dsa/qca/qca8k-8xxx.c-846-\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-848-\n\n"
}

gemini-3.1-pro-preview

null

null

							input: 34406
							output: 22
							thoughts: 166
						

**Analyzing the QCA8K Ethernet Driver Modifications**

Okay, so I'm looking at this patch and immediately, my focus lands on `drivers/net/dsa/qca/qca8k-8xxx.c`. That's the driver file itself, so it's the core of the changes. The key functions that have been touched are `qca8k_read_eth`, `qca8k_write_eth`, and `qca8k_phy_eth_command`. Knowing these are modified tells me we're likely dealing with some fundamental Ethernet communication operations, probably reading and writing to the PHY, perhaps issuing commands.

Now, where are *these* functions called from? Ah, yes, `qca8k_bulk_read`, `qca8k_bulk_gather_write`, `qca8k_phy_eth_busy_wait`, and so on. These are hinting at optimizations or perhaps handling larger data transfers more efficiently. And I remember now – these functions are all part of the *regmap* operations. Right, this is how we're abstracting register access to the hardware. Specifically, these functions fit within the `qca8k_regmap_config` configuration.

Now the question is, how and where is this regmap initialized? It's either in `qca8k_setup` or, hmm, maybe `qca8k_sw_probe`? My initial instinct is to go with `qca8k_sw_probe`. Let's just quickly confirm that... I'll check `qca8k_sw_probe`.

{
  "Expression": "qca8k_sw_probe"
}

{
  "Output": "drivers/net/dsa/qca/qca8k-8xxx.c=2072=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:2073:qca8k_sw_probe(struct mdio_device *mdiodev)\ndrivers/net/dsa/qca/qca8k-8xxx.c-2074-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=2235=static struct mdio_driver qca8kmdio_driver = {\ndrivers/net/dsa/qca/qca8k-8xxx.c:2236:\t.probe  = qca8k_sw_probe,\ndrivers/net/dsa/qca/qca8k-8xxx.c-2237-\t.remove = qca8k_sw_remove,\n"
}

gemini-3.1-pro-preview

null

null

							input: 35175
							output: 27
							thoughts: 240
						

**MDIO Driver Instantiation: A Syzkaller Challenge**

Okay, so I'm looking at this MDIO driver and wondering how I can poke at it with syzkaller. The immediate problem is that syzkaller doesn't seem to have a *generic* method for instantiating MDIO devices. Unless there's some special pseudo-syscall or netlink interface, I'm kind of stuck. I'm aware of the existing tools like `syz_genetlink_get_family` and `syz_open_dev`, but they don't jump out as a direct solution here.

The obvious way MDIO devices are *usually* brought to life is through the device tree, and unfortunately, I can't inject device tree overlays using syzkaller. That's a dead end.

Okay, sysfs then? Can I leverage sysfs to instantiate these devices? Let me think... Could I do something like `echo "qca8k" > /sys/bus/mdio_bus/devices/...`? No, wait a minute, the MDIO bus doesn't seem to have that convenient `new_device` sysfs attribute like I2C or SPI. That's frustrating.

Let's step back, and re-think this. Syzkaller has these very specific syscalls for other subsystems, things like `syz_usb_connect` for USB and `syz_80211_inject_frame` for mac80211. Does it have anything *at all* specific to MDIO? I need to check. This feels like it might be the only route.

no matches

{
  "Expression": "syz_",
  "PathPrefix": "sys/linux/"
}

{
  "error": "no matches"
}

gemini-3.1-pro-preview

null

null

							input: 35806
							output: 20
							thoughts: 329
						

**Analyzing the Scope of My Investigation**

Okay, so the instructions are pretty clear: this tool *cannot* handle searching within syzkaller's `sys/*` descriptions or expressions using `syz_`, which makes sense because those are pseudo-syscalls and aren't directly present in the Linux kernel. They explicitly tell me to use `read-syz-spec` and `syz-grepper` for that, but hold on... I don't see those tools listed. My options here are limited to `grepper`, `codesearch-dir-index`, `read-file`, and `set-results`. So, I'm effectively blocked from looking at those syzkaller constructs directly.

But, that's alright, I can work around this based on my knowledge. MDIO devices, in general, aren't something you instantiate from user-space in a straightforward manner. There's no standard `syz_mdio_connect` equivalent or anything like that that I'm aware of. And, looking at the context, this is a hardware-specific switch driver – a Qualcomm Atheros QCA8K, specifically.

Typically, hardware-specific network switch drivers, especially DSA drivers, are completely unreachable in virtualized environments like QEMU unless you've got *very* specific hardware emulation going on. And QEMU certainly doesn't emulate QCA8K switches. Therefore, considering the limitations of what I *can* use, the chances of reaching these code paths in environments like Google Compute Engine or QEMU are slim to none. It's essentially impossible, as the code relies on interacting with the physical hardware.

Just to be thorough, I should double check to see if there's some kind of dummy MDIO bus or something similar which may probe this. However, even if there is, the driver's `qca8k_sw_probe` function reads hardware registers to identify the chip, and that will be impossible to do with a dummy implementation.

{
  "Expression": "qca8k_read"
}

{
  "Output": "drivers/clk/qcom/nsscc-qca8k.c=2074=static int qca8k_regmap_read(void *context, unsigned int regaddr, unsigned int *val)\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2085-\tif (ret \u003c 0)\ndrivers/clk/qcom/nsscc-qca8k.c:2086:\t\tgoto qca8k_read_exit;\ndrivers/clk/qcom/nsscc-qca8k.c-2087-\n--\ndrivers/clk/qcom/nsscc-qca8k.c-2089-\ndrivers/clk/qcom/nsscc-qca8k.c:2090:qca8k_read_exit:\ndrivers/clk/qcom/nsscc-qca8k.c-2091-\tmutex_unlock(\u0026bus-\u003emdio_lock);\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=307=static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-316-\ndrivers/net/dsa/qca/qca8k-8xxx.c:317:static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\ndrivers/net/dsa/qca/qca8k-8xxx.c-318-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=424=qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-428-\ndrivers/net/dsa/qca/qca8k-8xxx.c:429:\tret = qca8k_read_eth(priv, reg, \u0026val, sizeof(val));\ndrivers/net/dsa/qca/qca8k-8xxx.c-430-\tif (ret)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=439=static int\ndrivers/net/dsa/qca/qca8k-8xxx.c:440:qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val)\ndrivers/net/dsa/qca/qca8k-8xxx.c-441-{\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=515=qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-522-\tif (priv-\u003emgmt_conduit \u0026\u0026\ndrivers/net/dsa/qca/qca8k-8xxx.c:523:\t    !qca8k_read_eth(priv, reg, val_buf, val_len))\ndrivers/net/dsa/qca/qca8k-8xxx.c-524-\t\treturn 0;\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-527-\tfor (i = 0; i \u003c count; i++, reg += sizeof(u32)) {\ndrivers/net/dsa/qca/qca8k-8xxx.c:528:\t\tret = qca8k_read_mii(priv, reg, val_buf + i);\ndrivers/net/dsa/qca/qca8k-8xxx.c-529-\t\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=579=static const struct regmap_config qca8k_regmap_config = {\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-586-\t.reg_update_bits = qca8k_regmap_update_bits,\ndrivers/net/dsa/qca/qca8k-8xxx.c:587:\t.rd_table = \u0026qca8k_readable_table,\ndrivers/net/dsa/qca/qca8k-8xxx.c-588-\t.disable_locking = true, /* Locking is handled by qca8k read/write */\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=808=qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-819-\ndrivers/net/dsa/qca/qca8k-8xxx.c:820:\t/* Check if qca8k_read has failed for a different reason\ndrivers/net/dsa/qca/qca8k-8xxx.c-821-\t * before returnting -ETIMEDOUT\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=1508=static void qca8k_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-1515-\ndrivers/net/dsa/qca/qca8k-8xxx.c:1516:\tret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), \u0026reg);\ndrivers/net/dsa/qca/qca8k-8xxx.c-1517-\tif (ret \u003c 0) {\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=1548=static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-1582-\t/* Configure the SGMII parameters */\ndrivers/net/dsa/qca/qca8k-8xxx.c:1583:\tret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, \u0026val);\ndrivers/net/dsa/qca/qca8k-8xxx.c-1584-\tif (ret)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=2073=qca8k_sw_probe(struct mdio_device *mdiodev)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c-2112-\t/* Check the detected switch id */\ndrivers/net/dsa/qca/qca8k-8xxx.c:2113:\tret = qca8k_read_switch_id(priv);\ndrivers/net/dsa/qca/qca8k-8xxx.c-2114-\tif (ret)\n--\ndrivers/net/dsa/qca/qca8k-common.c=22=const struct qca8k_mib_desc ar8327_mib[] = {\n--\ndrivers/net/dsa/qca/qca8k-common.c-65-\ndrivers/net/dsa/qca/qca8k-common.c:66:int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)\ndrivers/net/dsa/qca/qca8k-common.c-67-{\n--\ndrivers/net/dsa/qca/qca8k-common.c=76=int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\n--\ndrivers/net/dsa/qca/qca8k-common.c-80-\ndrivers/net/dsa/qca/qca8k-common.c:81:static const struct regmap_range qca8k_readable_ranges[] = {\ndrivers/net/dsa/qca/qca8k-common.c-82-\tregmap_reg_range(0x0000, 0x00e4), /* Global control */\n--\ndrivers/net/dsa/qca/qca8k-common.c-98-\ndrivers/net/dsa/qca/qca8k-common.c:99:const struct regmap_access_table qca8k_readable_table = {\ndrivers/net/dsa/qca/qca8k-common.c:100:\t.yes_ranges = qca8k_readable_ranges,\ndrivers/net/dsa/qca/qca8k-common.c:101:\t.n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),\ndrivers/net/dsa/qca/qca8k-common.c-102-};\n--\ndrivers/net/dsa/qca/qca8k-common.c=164=static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd,\n--\ndrivers/net/dsa/qca/qca8k-common.c-189-\tif (cmd == QCA8K_FDB_LOAD) {\ndrivers/net/dsa/qca/qca8k-common.c:190:\t\tret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, \u0026reg);\ndrivers/net/dsa/qca/qca8k-common.c-191-\t\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-common.c=325=static int qca8k_vlan_access(struct qca8k_priv *priv,\n--\ndrivers/net/dsa/qca/qca8k-common.c-347-\tif (cmd == QCA8K_VLAN_LOAD) {\ndrivers/net/dsa/qca/qca8k-common.c:348:\t\tret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, \u0026reg);\ndrivers/net/dsa/qca/qca8k-common.c-349-\t\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-common.c=358=static int qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid,\n--\ndrivers/net/dsa/qca/qca8k-common.c-374-\ndrivers/net/dsa/qca/qca8k-common.c:375:\tret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, \u0026reg);\ndrivers/net/dsa/qca/qca8k-common.c-376-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-common.c=396=static int qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)\n--\ndrivers/net/dsa/qca/qca8k-common.c-406-\ndrivers/net/dsa/qca/qca8k-common.c:407:\tret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, \u0026reg);\ndrivers/net/dsa/qca/qca8k-common.c-408-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-common.c=493=void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/qca/qca8k-common.c-509-\ndrivers/net/dsa/qca/qca8k-common.c:510:\t\tret = qca8k_read(priv, reg, \u0026val);\ndrivers/net/dsa/qca/qca8k-common.c-511-\t\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-common.c-514-\t\tif (mib-\u003esize == 2) {\ndrivers/net/dsa/qca/qca8k-common.c:515:\t\t\tret = qca8k_read(priv, reg + 4, \u0026hi);\ndrivers/net/dsa/qca/qca8k-common.c-516-\t\t\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-common.c=536=int qca8k_set_mac_eee(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/qca/qca8k-common.c-544-\tmutex_lock(\u0026priv-\u003ereg_mutex);\ndrivers/net/dsa/qca/qca8k-common.c:545:\tret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, \u0026reg);\ndrivers/net/dsa/qca/qca8k-common.c-546-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k-common.c=1224=int qca8k_port_lag_leave(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/qca/qca8k-common.c-1229-\ndrivers/net/dsa/qca/qca8k-common.c:1230:int qca8k_read_switch_id(struct qca8k_priv *priv)\ndrivers/net/dsa/qca/qca8k-common.c-1231-{\n--\ndrivers/net/dsa/qca/qca8k-common.c-1238-\ndrivers/net/dsa/qca/qca8k-common.c:1239:\tret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, \u0026val);\ndrivers/net/dsa/qca/qca8k-common.c-1240-\tif (ret \u003c 0)\n--\ndrivers/net/dsa/qca/qca8k.h=502=extern const struct qca8k_mib_desc ar8327_mib[];\ndrivers/net/dsa/qca/qca8k.h:503:extern const struct regmap_access_table qca8k_readable_table;\ndrivers/net/dsa/qca/qca8k.h-504-int qca8k_mib_init(struct qca8k_priv *priv);\ndrivers/net/dsa/qca/qca8k.h=505=void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable);\ndrivers/net/dsa/qca/qca8k.h:506:int qca8k_read_switch_id(struct qca8k_priv *priv);\ndrivers/net/dsa/qca/qca8k.h-507-\ndrivers/net/dsa/qca/qca8k.h-508-/* Common read/write/rmw function */\ndrivers/net/dsa/qca/qca8k.h:509:int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);\ndrivers/net/dsa/qca/qca8k.h-510-int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);\n"
}

gemini-3.1-pro-preview

null

null

							input: 40684
							output: 120
							thoughts: 358
						

**Analyzing the Fuzzability of the QCA8K DSA Switch Driver**

Okay, let's break this down. My initial assessment is that this QCA8K switch driver, specifically the `qca8k_sw_probe` function, presents a significant hurdle for fuzzing. The function `qca8k_read_switch_id(priv)` is called within `qca8k_sw_probe`, and crucially, this relies on the physical presence of the hardware. Given that standard QEMU doesn't emulate these QCA8K switches, the probe will inevitably fail in a virtualized environment. Consequently, the code paths touched by this patch, involving checks for `qca8k_mgmt_eth_disabled` in `qca8k_read_eth`, `qca8k_write_eth`, and `qca8k_phy_eth_command`, are completely unreachable within environments like GCE or, critically, Syzkaller's QEMU. These functions are only called after a successful probe and switch initialization.

To be absolutely sure, I've considered potential workarounds. Is there a dummy driver out there that might instantiate this, somehow making it accessible? No, it's not. The driver relies on specific MDIO compatible strings, like "qca,qca8327," matched through the device tree (OF). Syzkaller doesn't dynamically inject OF nodes for MDIO devices, which would be needed here. Even if such a thing were possible, the probe function itself reads a switch ID from a specific register. That read would fail without an appropriate emulator, and that's not something we have available.

Therefore, after a thorough review, I'm confident in concluding that this is not worth fuzzing, and I should set `WorthFuzzing=false`. The reasoning will be straightforward: this is a hardware-specific DSA switch driver for QCA8K chips that requires physical hardware not emulated in standard QEMU.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the qca8k DSA switch driver, which is a hardware-specific driver for Qualcomm Atheros QCA8K Ethernet switch chips. This driver requires physical hardware connected via MDIO to probe successfully (it reads the switch ID from a hardware register during probe). Since this hardware is not emulated in standard QEMU/GCE environments used by syzkaller, the modified code paths are impossible to reach and fuzz.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the qca8k DSA switch driver, which is a hardware-specific driver for Qualcomm Atheros QCA8K Ethernet switch chips. This driver requires physical hardware connected via MDIO to probe successfully (it reads the switch ID from a hardware register during probe). Since this hardware is not emulated in standard QEMU/GCE environments used by syzkaller, the modified code paths are impossible to reach and fuzz.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

null