AI Trajectory

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies the Synopsys STMMAC DWXGMAC (10G MAC) timestamp interrupt handling and Altera SoCFPGA ethernet glue driver. These code paths require physical SoC/FPGA hardware (such as Intel/Altera SoCFPGA or Nvidia Tegra platforms) that is not available or emulated in standard virtualized environments like QEMU or GCE.",
  "WorthFuzzing": false
}

null

{
  "PatchDiff": "commit 29a24b3d85458a2a3b7133c449ea70ae616d9e56\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Thu Sep 3 09:38:36 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c\nindex 1d7f0a57d2889..a4d00bf814237 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c\n@@ -310,6 +310,13 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,\n \tif (priv-\u003eplat-\u003eflags \u0026 STMMAC_FLAG_EXT_SNAPSHOT_EN)\n \t\treturn -EBUSY;\n \n+\t/* The XGMAC timestamp interrupt handler clears TSIS by reading\n+\t * XGMAC_TIMESTAMP_STATUS, which would race with the TSIS poll\n+\t * below.  Mask XGMAC_TSIE for the duration of the cross-timestamp\n+\t * so the handler does not run while we own the snapshot FIFO.\n+\t */\n+\tstmmac_mac_irq_modify(priv, XGMAC_TSIE, 0);\n+\n \tmutex_lock(\u0026priv-\u003eaux_ts_lock);\n \t/* Enable Internal snapshot trigger */\n \tacr_value = readl(ptpaddr + PTP_ACR);\n@@ -329,6 +336,7 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,\n \t\tbreak;\n \tdefault:\n \t\tmutex_unlock(\u0026priv-\u003eaux_ts_lock);\n+\t\tstmmac_mac_irq_modify(priv, 0, XGMAC_TSIE);\n \t\treturn -EINVAL;\n \t}\n \twritel(acr_value, ptpaddr + PTP_ACR);\n@@ -353,6 +361,7 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,\n \tret = readl_poll_timeout(priv-\u003eioaddr + XGMAC_INT_STATUS, v,\n \t\t\t\t (v \u0026 XGMAC_INT_TSIS), 100, 10000);\n \tif (ret) {\n+\t\tstmmac_mac_irq_modify(priv, 0, XGMAC_TSIE);\n \t\tnetdev_err(priv-\u003edev, \"%s: Wait for time sync operation timeout\\n\",\n \t\t\t   __func__);\n \t\treturn ret;\n@@ -375,6 +384,8 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,\n \t\tread_unlock_irqrestore(\u0026priv-\u003eptp_lock, flags);\n \t}\n \n+\tstmmac_mac_irq_modify(priv, 0, XGMAC_TSIE);\n+\n \tget_smtgtime(priv-\u003emii, SMTG_MDIO_ADDR, \u0026smtg_time);\n \tsystem-\u003ecycles = smtg_time;\n \ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\nindex f8ab347f7b5b9..03cbae326995b 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n@@ -87,7 +87,7 @@\n #define XGMAC_TSIE\t\t\tBIT(12)\n #define XGMAC_LPIIE\t\t\tBIT(5)\n #define XGMAC_PMTIE\t\t\tBIT(4)\n-#define XGMAC_INT_DEFAULT_EN\t\t(XGMAC_LPIIE | XGMAC_PMTIE)\n+#define XGMAC_INT_DEFAULT_EN\t\t(XGMAC_LPIIE | XGMAC_PMTIE | XGMAC_TSIE)\n #define XGMAC_Qx_TX_FLOW_CTRL(x)\t(0x00000070 + (x) * 4)\n #define XGMAC_PT\t\t\tGENMASK(31, 16)\n #define XGMAC_TFE\t\t\tBIT(1)\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c\nindex 1a88cbaed70ca..891b7ceea2d45 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c\n@@ -1154,6 +1154,49 @@ static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *ts)\n \treturn 0;\n }\n \n+void dwxgmac2_timestamp_interrupt(struct stmmac_priv *priv)\n+{\n+\tu32 ts_status, pending_snapshots, acr_value, channel;\n+\tstruct ptp_clock_event event;\n+\tunsigned long flags;\n+\tu64 ptp_time;\n+\tint i;\n+\n+\t/* Read XGMAC_TIMESTAMP_STATUS to get the AUX snapshot\n+\t * count.  This read also clears the TSIS bit in\n+\t * XGMAC_INT_STATUS.\n+\t * TX timestamp polling may have already cleared TSIS\n+\t * and AUXTSTRIG, so rely on ATSNS instead.\n+\t * TXTSC is cleared by XGMAC_TXTIMESTAMP_SEC, not by\n+\t * this register, so there is no conflict.\n+\t */\n+\tts_status = readl(priv-\u003eioaddr + XGMAC_TIMESTAMP_STATUS);\n+\n+\tif (!(priv-\u003eplat-\u003eflags \u0026 STMMAC_FLAG_EXT_SNAPSHOT_EN))\n+\t\treturn;\n+\n+\tpending_snapshots = FIELD_GET(XGMAC_TIMESTAMP_ATSNS_MASK, ts_status);\n+\tif (!pending_snapshots)\n+\t\treturn;\n+\n+\tacr_value = readl(priv-\u003eptpaddr + PTP_ACR);\n+\tchannel = FIELD_GET(PTP_ACR_MASK, acr_value);\n+\tif (!channel)\n+\t\treturn;\n+\tchannel = ilog2(channel);\n+\n+\tfor (i = 0; i \u003c pending_snapshots; i++) {\n+\t\tread_lock_irqsave(\u0026priv-\u003eptp_lock, flags);\n+\t\tstmmac_get_ptptime(priv, priv-\u003eptpaddr, \u0026ptp_time);\n+\t\tread_unlock_irqrestore(\u0026priv-\u003eptp_lock, flags);\n+\n+\t\tevent.type = PTP_CLOCK_EXTTS;\n+\t\tevent.index = channel;\n+\t\tevent.timestamp = ptp_time;\n+\t\tptp_clock_event(priv-\u003eptp_clock, \u0026event);\n+\t}\n+}\n+\n static int dwxgmac2_flex_pps_config(void __iomem *ioaddr, int index,\n \t\t\t\t    struct stmmac_pps_cfg *cfg, bool enable,\n \t\t\t\t    u32 sub_second_inc, u32 systime_flags)\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c\nindex 265671170bf6e..eba87410f985a 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c\n@@ -258,7 +258,7 @@ static const struct stmmac_hwif_entry {\n \t\t.dma = \u0026dwxgmac210_dma_ops,\n \t\t.mac = \u0026dwxgmac210_ops,\n \t\t.vlan = \u0026dwxgmac210_vlan_ops,\n-\t\t.hwtimestamp = \u0026stmmac_ptp,\n+\t\t.hwtimestamp = \u0026dwxgmac2_ptp,\n \t\t.ptp = \u0026stmmac_ptp_clock_ops,\n \t\t.mode = NULL,\n \t\t.tc = \u0026dwmac510_tc_ops,\n@@ -280,7 +280,7 @@ static const struct stmmac_hwif_entry {\n \t\t.dma = \u0026dwxgmac210_dma_ops,\n \t\t.mac = \u0026dwxlgmac2_ops,\n \t\t.vlan = \u0026dwxlgmac2_vlan_ops,\n-\t\t.hwtimestamp = \u0026stmmac_ptp,\n+\t\t.hwtimestamp = \u0026dwxgmac2_ptp,\n \t\t.ptp = \u0026stmmac_ptp_clock_ops,\n \t\t.mode = NULL,\n \t\t.tc = \u0026dwmac510_tc_ops,\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h\nindex fe18f98fae451..5a308e79db4a9 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h\n@@ -672,6 +672,7 @@ extern const struct stmmac_desc_ops ndesc_ops;\n \n extern const struct stmmac_hwtimestamp stmmac_ptp;\n extern const struct stmmac_hwtimestamp dwmac1000_ptp;\n+extern const struct stmmac_hwtimestamp dwxgmac2_ptp;\n \n extern const struct stmmac_mode_ops ring_mode_ops;\n extern const struct stmmac_mode_ops chain_mode_ops;\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c\nindex b9a985fa772c9..9d7d24259abd4 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c\n@@ -277,3 +277,15 @@ const struct stmmac_hwtimestamp dwmac1000_ptp = {\n \t.get_ptptime = dwmac1000_get_ptptime,\n \t.timestamp_interrupt = dwmac1000_timestamp_interrupt,\n };\n+\n+const struct stmmac_hwtimestamp dwxgmac2_ptp = {\n+\t.config_hw_tstamping = config_hw_tstamping,\n+\t.init_systime = init_systime,\n+\t.config_sub_second_increment = config_sub_second_increment,\n+\t.config_addend = config_addend,\n+\t.adjust_systime = adjust_systime,\n+\t.get_systime = get_systime,\n+\t.get_ptptime = get_ptptime,\n+\t.timestamp_interrupt = dwxgmac2_timestamp_interrupt,\n+\t.hwtstamp_correct_latency = hwtstamp_correct_latency,\n+};\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h\nindex 3fe0e3a80e80a..dade09614163b 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h\n@@ -103,6 +103,7 @@ int dwmac1000_ptp_enable(struct ptp_clock_info *ptp,\n \n void dwmac1000_get_ptptime(void __iomem *ptpaddr, u64 *ptp_time);\n void dwmac1000_timestamp_interrupt(struct stmmac_priv *priv);\n+void dwxgmac2_timestamp_interrupt(struct stmmac_priv *priv);\n \n extern const struct ptp_clock_info stmmac_ptp_clock_ops;\n extern const struct ptp_clock_info dwmac1000_ptp_clock_ops;\n"
}

core

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Synopsys STMMAC DWXGMAC (10G MAC) timestamp interrupt handling and Altera SoCFPGA ethernet glue driver. These code paths require physical SoC/FPGA hardware (such as Intel/Altera SoCFPGA or Nvidia Tegra platforms) that is not available or emulated in standard virtualized environments like QEMU or GCE.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer.
Your job is to review a provided patch series and determine
if it makes functional changes to the kernel that should be fuzzed.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively
use your code access tools to examine the actual source code and confirm any assumptions.

Return WorthFuzzing=false if the patch only contains:
- Modifications to Documentation/, Kconfig files, or code comments.
- Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints.
- Changes to numeric constants or macros that do not functionally alter execution flow.
- Code paths that are impossible to reach in virtualized environments like GCE or QEMU,
  even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim).
- Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed,
  ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU.
- Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove)
  that are executed only during PCI hot-unplug or sysfs driver unbind operations.

If it modifies reachable core kernel logic, drivers, or architectures, use your code search
tools to verify the code can be executed, then return WorthFuzzing=true.

When returning WorthFuzzing=true, you MUST ALSO:
1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols.
   Avoid listing generic hot-path functions to prevent skewed test distributions.
   Prefer non-static, non-inlined API entrypoint functions over internal static helper functions
   (which are inlined by the compiler and do not have distinct symbol addresses).
2. Identify any specific CONFIG_ options required to properly test this new/modified feature.
   Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions.
   Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs
   needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs
   output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

For your convenience, here is the diff of the changes:
commit 29a24b3d85458a2a3b7133c449ea70ae616d9e56
Author: syz-cluster <triage@syzkaller.com>
Date:   Thu Sep 3 09:38:36 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 1d7f0a57d2889..a4d00bf814237 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -310,6 +310,13 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,
 	if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN)
 		return -EBUSY;
 
+	/* The XGMAC timestamp interrupt handler clears TSIS by reading
+	 * XGMAC_TIMESTAMP_STATUS, which would race with the TSIS poll
+	 * below.  Mask XGMAC_TSIE for the duration of the cross-timestamp
+	 * so the handler does not run while we own the snapshot FIFO.
+	 */
+	stmmac_mac_irq_modify(priv, XGMAC_TSIE, 0);
+
 	mutex_lock(&priv->aux_ts_lock);
 	/* Enable Internal snapshot trigger */
 	acr_value = readl(ptpaddr + PTP_ACR);
@@ -329,6 +336,7 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,
 		break;
 	default:
 		mutex_unlock(&priv->aux_ts_lock);
+		stmmac_mac_irq_modify(priv, 0, XGMAC_TSIE);
 		return -EINVAL;
 	}
 	writel(acr_value, ptpaddr + PTP_ACR);
@@ -353,6 +361,7 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,
 	ret = readl_poll_timeout(priv->ioaddr + XGMAC_INT_STATUS, v,
 				 (v & XGMAC_INT_TSIS), 100, 10000);
 	if (ret) {
+		stmmac_mac_irq_modify(priv, 0, XGMAC_TSIE);
 		netdev_err(priv->dev, "%s: Wait for time sync operation timeout\n",
 			   __func__);
 		return ret;
@@ -375,6 +384,8 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,
 		read_unlock_irqrestore(&priv->ptp_lock, flags);
 	}
 
+	stmmac_mac_irq_modify(priv, 0, XGMAC_TSIE);
+
 	get_smtgtime(priv->mii, SMTG_MDIO_ADDR, &smtg_time);
 	system->cycles = smtg_time;
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index f8ab347f7b5b9..03cbae326995b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -87,7 +87,7 @@
 #define XGMAC_TSIE			BIT(12)
 #define XGMAC_LPIIE			BIT(5)
 #define XGMAC_PMTIE			BIT(4)
-#define XGMAC_INT_DEFAULT_EN		(XGMAC_LPIIE | XGMAC_PMTIE)
+#define XGMAC_INT_DEFAULT_EN		(XGMAC_LPIIE | XGMAC_PMTIE | XGMAC_TSIE)
 #define XGMAC_Qx_TX_FLOW_CTRL(x)	(0x00000070 + (x) * 4)
 #define XGMAC_PT			GENMASK(31, 16)
 #define XGMAC_TFE			BIT(1)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index 1a88cbaed70ca..891b7ceea2d45 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -1154,6 +1154,49 @@ static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *ts)
 	return 0;
 }
 
+void dwxgmac2_timestamp_interrupt(struct stmmac_priv *priv)
+{
+	u32 ts_status, pending_snapshots, acr_value, channel;
+	struct ptp_clock_event event;
+	unsigned long flags;
+	u64 ptp_time;
+	int i;
+
+	/* Read XGMAC_TIMESTAMP_STATUS to get the AUX snapshot
+	 * count.  This read also clears the TSIS bit in
+	 * XGMAC_INT_STATUS.
+	 * TX timestamp polling may have already cleared TSIS
+	 * and AUXTSTRIG, so rely on ATSNS instead.
+	 * TXTSC is cleared by XGMAC_TXTIMESTAMP_SEC, not by
+	 * this register, so there is no conflict.
+	 */
+	ts_status = readl(priv->ioaddr + XGMAC_TIMESTAMP_STATUS);
+
+	if (!(priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN))
+		return;
+
+	pending_snapshots = FIELD_GET(XGMAC_TIMESTAMP_ATSNS_MASK, ts_status);
+	if (!pending_snapshots)
+		return;
+
+	acr_value = readl(priv->ptpaddr + PTP_ACR);
+	channel = FIELD_GET(PTP_ACR_MASK, acr_value);
+	if (!channel)
+		return;
+	channel = ilog2(channel);
+
+	for (i = 0; i < pending_snapshots; i++) {
+		read_lock_irqsave(&priv->ptp_lock, flags);
+		stmmac_get_ptptime(priv, priv->ptpaddr, &ptp_time);
+		read_unlock_irqrestore(&priv->ptp_lock, flags);
+
+		event.type = PTP_CLOCK_EXTTS;
+		event.index = channel;
+		event.timestamp = ptp_time;
+		ptp_clock_event(priv->ptp_clock, &event);
+	}
+}
+
 static int dwxgmac2_flex_pps_config(void __iomem *ioaddr, int index,
 				    struct stmmac_pps_cfg *cfg, bool enable,
 				    u32 sub_second_inc, u32 systime_flags)
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index 265671170bf6e..eba87410f985a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -258,7 +258,7 @@ static const struct stmmac_hwif_entry {
 		.dma = &dwxgmac210_dma_ops,
 		.mac = &dwxgmac210_ops,
 		.vlan = &dwxgmac210_vlan_ops,
-		.hwtimestamp = &stmmac_ptp,
+		.hwtimestamp = &dwxgmac2_ptp,
 		.ptp = &stmmac_ptp_clock_ops,
 		.mode = NULL,
 		.tc = &dwmac510_tc_ops,
@@ -280,7 +280,7 @@ static const struct stmmac_hwif_entry {
 		.dma = &dwxgmac210_dma_ops,
 		.mac = &dwxlgmac2_ops,
 		.vlan = &dwxlgmac2_vlan_ops,
-		.hwtimestamp = &stmmac_ptp,
+		.hwtimestamp = &dwxgmac2_ptp,
 		.ptp = &stmmac_ptp_clock_ops,
 		.mode = NULL,
 		.tc = &dwmac510_tc_ops,
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
index fe18f98fae451..5a308e79db4a9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
@@ -672,6 +672,7 @@ extern const struct stmmac_desc_ops ndesc_ops;
 
 extern const struct stmmac_hwtimestamp stmmac_ptp;
 extern const struct stmmac_hwtimestamp dwmac1000_ptp;
+extern const struct stmmac_hwtimestamp dwxgmac2_ptp;
 
 extern const struct stmmac_mode_ops ring_mode_ops;
 extern const struct stmmac_mode_ops chain_mode_ops;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
index b9a985fa772c9..9d7d24259abd4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
@@ -277,3 +277,15 @@ const struct stmmac_hwtimestamp dwmac1000_ptp = {
 	.get_ptptime = dwmac1000_get_ptptime,
 	.timestamp_interrupt = dwmac1000_timestamp_interrupt,
 };
+
+const struct stmmac_hwtimestamp dwxgmac2_ptp = {
+	.config_hw_tstamping = config_hw_tstamping,
+	.init_systime = init_systime,
+	.config_sub_second_increment = config_sub_second_increment,
+	.config_addend = config_addend,
+	.adjust_systime = adjust_systime,
+	.get_systime = get_systime,
+	.get_ptptime = get_ptptime,
+	.timestamp_interrupt = dwxgmac2_timestamp_interrupt,
+	.hwtstamp_correct_latency = hwtstamp_correct_latency,
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
index 3fe0e3a80e80a..dade09614163b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h
@@ -103,6 +103,7 @@ int dwmac1000_ptp_enable(struct ptp_clock_info *ptp,
 
 void dwmac1000_get_ptptime(void __iomem *ptpaddr, u64 *ptp_time);
 void dwmac1000_timestamp_interrupt(struct stmmac_priv *priv);
+void dwxgmac2_timestamp_interrupt(struct stmmac_priv *priv);
 
 extern const struct ptp_clock_info stmmac_ptp_clock_ops;
 extern const struct ptp_clock_info dwmac1000_ptp_clock_ops;

gemini-3.7-flash

null

null

							input: 5136
							output: 39
							thoughts: 341
						

**Analyzing the Patch for Fuzzing Potential**

Okay, so I've got this patch in front of me, and my immediate thought is to figure out if it's fuzz-worthy. Before I dive too deep into the code, I need to get a high-level view of the landscape. First, let's look at what's been touched. It looks like we're dealing with the `stmmac` driver, specifically its interaction with various PHY/MAC components: `dwmac-socfpga.c`, `dwxgmac2.h`, `dwxgmac2_core.c`, `hwif.c`, `hwif.h`, `stmmac_hwtstamp.c`, and `stmmac_ptp.h`.

Now, the important question is: what is the nature of this `stmmac` / `dwmac`? Can these components actually be exercised and tested? I need to quickly determine if these are PCI-based, platform-based, or something else entirely. Does `stmmac` have PCI glue, like `stmmac_pci` or similar drivers? Or are these specifically embedded Ethernet controllers, perhaps physical-only? I need to understand if `dwxgmac2` is used with PCI or platform devices. And then, the critical question, what about QEMU? Can I easily emulate this setup? If I can't emulate it, this is going to be far more difficult.

My next step is to go straight to the kernel source and search for the `stmmac` drivers and their associated Kconfig options. That will give me a better understanding of how these components are configured and how they are used. This will help me evaluate whether I can easily reproduce a test environment for fuzzing.

{
  "Expression": "config STMMAC_",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/Kconfig-1-# SPDX-License-Identifier: GPL-2.0-only\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:2:config STMMAC_ETH\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-3-\ttristate \"STMicroelectronics Multi-Gigabit Ethernet driver\"\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig=18=if STMMAC_ETH\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-19-\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:20:config STMMAC_SELFTESTS\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-21-\tbool \"Support for STMMAC Selftests\"\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-28-\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:29:config STMMAC_PLATFORM\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-30-\ttristate \"STMMAC Platform bus support\"\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig=371=endif # STMMAC_PLATFORM\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-372-\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:373:config STMMAC_LIBPCI\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-374-\ttristate\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig=398=config DWMAC_MOTORCOMM\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-406-\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:407:config STMMAC_PCI\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-408-\ttristate \"STMMAC PCI bus support\"\n"
}

gemini-3.7-flash

null

null

							input: 6420
							output: 37
							thoughts: 52
						

Here's my thought process, as if I were reviewing this code:

**Diving into the DWMAC Configuration**

Alright, time to dig into this `DWMAC_SOCFPGA` business. I need to understand how this driver is configured, so I'll start by checking the relevant files. I'm going to quickly scan `dwmac-socfpga.c`, since that seems to be the core of it, and then I'll also glance at `dwxgmac` – to see if there's any cross-compatibility or dependencies. The main goal here is to get a solid grasp on the configuration. My main stop will be the `Kconfig` files that control `DWMAC_SOCFPGA` and other similar `stmmac` configurations. That's where all the decision-making happens. I need to pinpoint the dependencies, options, and how it interacts with the rest of the system.

{
  "Expression": "SOCFPGA",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/Kconfig=29=config STMMAC_PLATFORM\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-35-\t  This is the driver used on several SoCs:\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:36:\t  STi, Allwinner, Amlogic Meson, Altera SOCFPGA.\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-37-\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig=191=config DWMAC_S32\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-202-\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:203:config DWMAC_SOCFPGA\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:204:\ttristate \"SOCFPGA dwmac support\"\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:205:\tdefault ARCH_INTEL_SOCFPGA\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:206:\tdepends on OF \u0026\u0026 (ARCH_INTEL_SOCFPGA || COMPILE_TEST)\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-207-\tselect MFD_SYSCON\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-211-\thelp\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:212:\t  Support for ethernet controller on Altera SOCFPGA\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-213-\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:214:\t  This selects the Altera SOCFPGA SoC glue layer support\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-215-\t  for the stmmac device driver. This driver is used for\n--\ndrivers/net/ethernet/stmicro/stmmac/Makefile=28=obj-$(CONFIG_DWMAC_S32)\t\t+= dwmac-s32.o\ndrivers/net/ethernet/stmicro/stmmac/Makefile:29:obj-$(CONFIG_DWMAC_SOCFPGA)\t+= dwmac-altr-socfpga.o\ndrivers/net/ethernet/stmicro/stmmac/Makefile-30-obj-$(CONFIG_DWMAC_SOPHGO)\t+= dwmac-sophgo.o\n"
}

gemini-3.7-flash

null

null

							input: 7356
							output: 38
							thoughts: 37
						

Here's my take:

**Investigating the dwxgmac2 Driver's Capabilities**

Okay, so I need to figure out how these specific functions – `dwxgmac210_ops`, `dwxgmac2_ptp`, and `dwxgmac2_timestamp_interrupt` – are used within the `dwxgmac2` driver context. My initial instinct is to use these function names as the starting point for a deeper investigation. I want to understand their purpose, how they're called, what data they operate on, and essentially, what their role is in the bigger picture of the driver’s functionality. Are they core operations, related to PTP (Precision Time Protocol), or handling specific interrupt scenarios? Diving into the codebase to trace these identifiers is the obvious first step. I need to understand how each of these contributes to the overall behavior of the Ethernet controller.

{
  "Expression": "dwxgmac2",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "\nFull output is too long, showing 500 out of 720 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/stmicro/stmmac/Makefile=3=stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o\t\\\n--\ndrivers/net/ethernet/stmicro/stmmac/Makefile-7-\t      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \\\ndrivers/net/ethernet/stmicro/stmmac/Makefile:8:\t      stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \\\ndrivers/net/ethernet/stmicro/stmmac/Makefile-9-\t      stmmac_xdp.o stmmac_est.o stmmac_fpe.o stmmac_vlan.o \\\n--\ndrivers/net/ethernet/stmicro/stmmac/common.h=652=int dwmac4_setup(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h:653:int dwxgmac2_setup(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/common.h-654-int dwxlgmac2_setup(struct stmmac_priv *priv);\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-18-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:19:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-20-#include \"stmmac.h\"\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-464-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:465:extern const struct stmmac_ops dwxgmac210_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-466-extern const struct stmmac_ops dwxlgmac2_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:467:extern const struct stmmac_dma_ops dwxgmac210_dma_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:468:extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-469-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-14-#include \"dwxlgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:15:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-16-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:17:static void dwxgmac2_core_init(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-18-\t\t\t       struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-30-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:31:static void dwxgmac2_irq_modify(struct mac_device_info *hw, u32 disable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-32-\t\t\t\tu32 enable)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-44-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:45:static void dwxgmac2_update_caps(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-46-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-50-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:51:static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-52-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-67-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:68:static int dwxgmac2_rx_ipc(struct mac_device_info *hw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-69-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-82-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:83:static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-84-\t\t\t\t     u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-96-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:97:static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-98-\t\t\t\t   u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-137-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:138:static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-139-\t\t\t\t   u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-154-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:155:static void dwxgmac2_rx_queue_routing(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-156-\t\t\t\t      u8 packet, u32 queue)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-160-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:161:\tstatic const struct stmmac_rx_routing dwxgmac2_route_possibilities[] = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-162-\t\t{ XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT },\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-171-\t/* routing configuration */\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:172:\tvalue \u0026= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:173:\tvalue |= (queue \u003c\u003c dwxgmac2_route_possibilities[packet - 1].reg_shift) \u0026\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:174:\t\t dwxgmac2_route_possibilities[packet - 1].reg_mask;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-175-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-184-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:185:static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-186-\t\t\t\t\t    u32 rx_alg)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-206-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:207:static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-208-\t\t\t\t\t    u32 tx_alg)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-244-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:245:static void dwxgmac2_set_mtl_tx_queue_weight(struct stmmac_priv *priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-246-\t\t\t\t\t     struct mac_device_info *hw,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-253-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:254:static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-255-\t\t\t\t    u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-270-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:271:static void dwxgmac2_config_cbs(struct stmmac_priv *priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-272-\t\t\t\tstruct mac_device_info *hw,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-289-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:290:static void dwxgmac2_dump_regs(struct mac_device_info *hw, u32 *reg_space)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-291-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-298-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:299:static int dwxgmac2_host_irq_status(struct stmmac_priv *priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-300-\t\t\t\t    struct stmmac_extra_stats *x)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-335-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:336:static int dwxgmac2_host_mtl_irq_status(struct stmmac_priv *priv,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-337-\t\t\t\t\tstruct mac_device_info *hw, u32 chan)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-355-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:356:static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-357-\t\t\t       unsigned int fc, unsigned int pause_time,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-376-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:377:static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-378-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-394-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:395:static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-396-\t\t\t\t   const unsigned char *addr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-408-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:409:static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-410-\t\t\t\t   unsigned char *addr, unsigned int reg_n)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-427-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:428:static int dwxgmac2_set_lpi_mode(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-429-\t\t\t\t enum stmmac_lpi_mode mode,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-451-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:452:static void dwxgmac2_set_eee_pls(struct mac_device_info *hw, int link)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-453-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-464-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:465:static void dwxgmac2_set_eee_timer(struct mac_device_info *hw, int ls, int tw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-466-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-473-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:474:static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-475-\t\t\t\tint mcbitslog2)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-496-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:497:static void dwxgmac2_set_filter(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-498-\t\t\t\tstruct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-531-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:532:\tdwxgmac2_set_mchash(ioaddr, mc_filter, mcbitslog2);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-533-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-541-\t\tnetdev_for_each_uc_addr(ha, dev) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:542:\t\t\tdwxgmac2_set_umac_addr(hw, ha-\u003eaddr, reg);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-543-\t\t\treg++;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-554-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:555:static void dwxgmac2_set_mac_loopback(void __iomem *ioaddr, bool enable)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-556-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-566-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:567:static int dwxgmac2_rss_write_reg(void __iomem *ioaddr, bool is_key, int idx,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-568-\t\t\t\t  u32 val)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-581-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:582:static int dwxgmac2_rss_configure(struct mac_device_info *hw,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-583-\t\t\t\t  struct stmmac_rss *cfg, u32 num_rxq)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-597-\tfor (i = 0; i \u003c (ARRAY_SIZE(cfg-\u003ekey) / sizeof(u32)); i++) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:598:\t\tret = dwxgmac2_rss_write_reg(ioaddr, true, i, key[i]);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-599-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-603-\tfor (i = 0; i \u003c ARRAY_SIZE(cfg-\u003etable); i++) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:604:\t\tret = dwxgmac2_rss_write_reg(ioaddr, false, i, cfg-\u003etable[i]);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-605-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-609-\tfor (i = 0; i \u003c num_rxq; i++)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:610:\t\tdwxgmac2_map_mtl_to_dma(hw, i, XGMAC_QDDMACH);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-611-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1055=static int dwxgmac3_rxp_config(void __iomem *ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1142-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1143:static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *ts)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1144-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1156-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1157:void dwxgmac2_timestamp_interrupt(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1158-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1199-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1200:static int dwxgmac2_flex_pps_config(void __iomem *ioaddr, int index,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1201-\t\t\t\t    struct stmmac_pps_cfg *cfg, bool enable,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1263-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1264:static void dwxgmac2_sarc_configure(void __iomem *ioaddr, int val)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1265-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1272-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1273:static int dwxgmac2_filter_wait(struct mac_device_info *hw)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1274-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1283-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1284:static int dwxgmac2_filter_read(struct mac_device_info *hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1285-\t\t\t\tu8 reg, u32 *data)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1290-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1291:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1292-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1300-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1301:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1302-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1308-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1309:static int dwxgmac2_filter_write(struct mac_device_info *hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1310-\t\t\t\t u8 reg, u32 data)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1315-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1316:\tret = dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1317-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1327-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1328:\treturn dwxgmac2_filter_wait(hw);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1329-}\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1330-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1331:static int dwxgmac2_config_l3_filter(struct mac_device_info *hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1332-\t\t\t\t     bool en, bool ipv6, bool sa, bool inv,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1342-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1343:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1344-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1373-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1374:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1375-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1378-\tif (sa) {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1379:\t\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR0, match);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1380-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1382-\t} else {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1383:\t\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR1, match);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1384-\t\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1388-\tif (!en)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1389:\t\treturn dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1390-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1393-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1394:static int dwxgmac2_config_l4_filter(struct mac_device_info *hw, u32 filter_no,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1395-\t\t\t\t     bool en, bool udp, bool sa, bool inv,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1405-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1406:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1407-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1429-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1430:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1431-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1433-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1434:\tret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L4_ADDR, \u0026value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1435-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1445-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1446:\tret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1447-\tif (ret)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1450-\tif (!en)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1451:\t\treturn dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1452-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1455-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1456:const struct stmmac_ops dwxgmac210_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1457:\t.core_init = dwxgmac2_core_init,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1458:\t.irq_modify = dwxgmac2_irq_modify,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1459:\t.update_caps = dwxgmac2_update_caps,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1460:\t.set_mac = dwxgmac2_set_mac,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1461:\t.rx_ipc = dwxgmac2_rx_ipc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1462:\t.rx_queue_enable = dwxgmac2_rx_queue_enable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1463:\t.rx_queue_prio = dwxgmac2_rx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1464:\t.tx_queue_prio = dwxgmac2_tx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1465:\t.rx_queue_routing = dwxgmac2_rx_queue_routing,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1466:\t.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1467:\t.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1468:\t.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1469:\t.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1470:\t.config_cbs = dwxgmac2_config_cbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1471:\t.dump_regs = dwxgmac2_dump_regs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1472:\t.host_irq_status = dwxgmac2_host_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1473:\t.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1474:\t.flow_ctrl = dwxgmac2_flow_ctrl,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1475:\t.pmt = dwxgmac2_pmt,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1476:\t.set_umac_addr = dwxgmac2_set_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1477:\t.get_umac_addr = dwxgmac2_get_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1478:\t.set_lpi_mode = dwxgmac2_set_lpi_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1479:\t.set_eee_timer = dwxgmac2_set_eee_timer,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1480:\t.set_eee_pls = dwxgmac2_set_eee_pls,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1481-\t.debug = NULL,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1482:\t.set_filter = dwxgmac2_set_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1483-\t.safety_feat_config = dwxgmac3_safety_feat_config,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1485-\t.safety_feat_dump = dwxgmac3_safety_feat_dump,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1486:\t.set_mac_loopback = dwxgmac2_set_mac_loopback,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1487:\t.rss_configure = dwxgmac2_rss_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1488-\t.rxp_config = dwxgmac3_rxp_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1489:\t.get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1490:\t.flex_pps_config = dwxgmac2_flex_pps_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1491:\t.sarc_configure = dwxgmac2_sarc_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1492:\t.config_l3_filter = dwxgmac2_config_l3_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1493:\t.config_l4_filter = dwxgmac2_config_l4_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1494-\t.fpe_map_preemption_class = dwxgmac3_fpe_map_preemption_class,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1511=const struct stmmac_ops dwxlgmac2_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1512:\t.core_init = dwxgmac2_core_init,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1513:\t.irq_modify = dwxgmac2_irq_modify,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1514:\t.set_mac = dwxgmac2_set_mac,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1515:\t.rx_ipc = dwxgmac2_rx_ipc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1516-\t.rx_queue_enable = dwxlgmac2_rx_queue_enable,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1517:\t.rx_queue_prio = dwxgmac2_rx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1518:\t.tx_queue_prio = dwxgmac2_tx_queue_prio,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1519:\t.rx_queue_routing = dwxgmac2_rx_queue_routing,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1520:\t.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1521:\t.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1522:\t.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1523:\t.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1524:\t.config_cbs = dwxgmac2_config_cbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1525:\t.dump_regs = dwxgmac2_dump_regs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1526:\t.host_irq_status = dwxgmac2_host_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1527:\t.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1528:\t.flow_ctrl = dwxgmac2_flow_ctrl,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1529:\t.pmt = dwxgmac2_pmt,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1530:\t.set_umac_addr = dwxgmac2_set_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1531:\t.get_umac_addr = dwxgmac2_get_umac_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1532:\t.set_lpi_mode = dwxgmac2_set_lpi_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1533:\t.set_eee_timer = dwxgmac2_set_eee_timer,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1534:\t.set_eee_pls = dwxgmac2_set_eee_pls,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1535-\t.debug = NULL,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1536:\t.set_filter = dwxgmac2_set_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1537-\t.safety_feat_config = dwxgmac3_safety_feat_config,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1539-\t.safety_feat_dump = dwxgmac3_safety_feat_dump,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1540:\t.set_mac_loopback = dwxgmac2_set_mac_loopback,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1541:\t.rss_configure = dwxgmac2_rss_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1542-\t.rxp_config = dwxgmac3_rxp_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1543:\t.get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1544:\t.flex_pps_config = dwxgmac2_flex_pps_config,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1545:\t.sarc_configure = dwxgmac2_sarc_configure,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1546:\t.config_l3_filter = dwxgmac2_config_l3_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1547:\t.config_l4_filter = dwxgmac2_config_l4_filter,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1548-\t.fpe_map_preemption_class = dwxgmac3_fpe_map_preemption_class,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1550-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1551:int dwxgmac2_setup(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1552-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-9-#include \"common.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:10:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-11-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:12:static int dwxgmac2_get_tx_status(struct stmmac_extra_stats *x,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-13-\t\t\t\t  struct dma_desc *p, void __iomem *ioaddr)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-25-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:26:static int dwxgmac2_get_rx_status(struct stmmac_extra_stats *x,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-27-\t\t\t\t  struct dma_desc *p)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-48-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:49:static void dwxgmac2_set_tx_owner(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-50-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-53-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:54:static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-55-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-63-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:64:static u16 dwxgmac2_wrback_get_rx_vlan_tci(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-65-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-68-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:69:static bool dwxgmac2_wrback_get_rx_vlan_valid(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-70-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-78-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:79:static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-80-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-83-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:84:static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-85-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-88-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:89:static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-90-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-93-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:94:static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-95-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-104-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:105:static int dwxgmac2_rx_check_timestamp(void *desc)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-106-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-124-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:125:static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-126-\t\t\t\t\t    u32 ats)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-132-\tif (likely(rdes3 \u0026 XGMAC_RDES3_CDA))\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:133:\t\tret = dwxgmac2_rx_check_timestamp(next_desc);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-134-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-137-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:138:static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-139-\t\t\t\t  u8 descriptor_mode, int end, int bfsize)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-140-{\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:141:\tdwxgmac2_set_rx_owner(p, disable_rx_ic);\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-142-}\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-143-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:144:static void dwxgmac2_init_tx_desc(struct dma_desc *p, u8 descriptor_mode,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-145-\t\t\t\t  int end)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-152-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:153:static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-154-\t\t\t\t     bool csum_flag, u8 descriptor_mode,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-191-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:192:static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-193-\t\t\t\t\t int len1, int len2, bool tx_own,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-229-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:230:static void dwxgmac2_release_tx_desc(struct dma_desc *p, u8 descriptor_mode)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-231-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-237-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:238:static void dwxgmac2_set_tx_ic(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-239-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-242-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:243:static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-244-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-250-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:251:static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-252-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-256-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:257:static void dwxgmac2_clear(struct dma_desc *p)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-258-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-264-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:265:static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-266-\t\t\t\tenum pkt_hash_types *type)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-292-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:293:static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-294-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-298-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:299:static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-300-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-304-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:305:static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-306-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-309-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:310:static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-311-\t\t\t\t  u32 inner_type)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-334-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:335:static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-336-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-339-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:340:static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-341-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-347-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:348:const struct stmmac_desc_ops dwxgmac210_desc_ops = {\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:349:\t.tx_status = dwxgmac2_get_tx_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:350:\t.rx_status = dwxgmac2_get_rx_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:351:\t.set_tx_owner = dwxgmac2_set_tx_owner,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:352:\t.set_rx_owner = dwxgmac2_set_rx_owner,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:353:\t.get_rx_vlan_tci = dwxgmac2_wrback_get_rx_vlan_tci,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:354:\t.get_rx_vlan_valid = dwxgmac2_wrback_get_rx_vlan_valid,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:355:\t.get_rx_frame_len = dwxgmac2_get_rx_frame_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:356:\t.enable_tx_timestamp = dwxgmac2_enable_tx_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:357:\t.get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:358:\t.get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:359:\t.get_timestamp = dwxgmac2_get_timestamp,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:360:\t.set_tx_ic = dwxgmac2_set_tx_ic,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:361:\t.prepare_tx_desc = dwxgmac2_prepare_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:362:\t.prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:363:\t.release_tx_desc = dwxgmac2_release_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:364:\t.init_rx_desc = dwxgmac2_init_rx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:365:\t.init_tx_desc = dwxgmac2_init_tx_desc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:366:\t.set_mss = dwxgmac2_set_mss,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:367:\t.set_addr = dwxgmac2_set_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:368:\t.clear = dwxgmac2_clear,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:369:\t.get_rx_hash = dwxgmac2_get_rx_hash,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:370:\t.get_rx_header_len = dwxgmac2_get_rx_header_len,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:371:\t.set_sec_addr = dwxgmac2_set_sec_addr,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:372:\t.set_sarc = dwxgmac2_set_sarc,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:373:\t.set_vlan_tag = dwxgmac2_set_vlan_tag,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:374:\t.set_vlan = dwxgmac2_set_vlan,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c:375:\t.set_tbs = dwxgmac2_set_tbs,\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c-376-};\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-8-#include \"stmmac.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:9:#include \"dwxgmac2.h\"\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-10-\n\n"
}

gemini-3.7-flash

null

null

							input: 24502
							output: 42
							thoughts: 76
						

**Digging into the Driver Code**

Okay, so I'm looking at these files: `dwmac-socfpga.c`, `dwxgmac2_ptp`, and `hwif.c`. My initial thought is to figure out the hardware context for `dwxgmac2`. It's a familiar interface but I need to quickly refresh my memory.

Hmm, where is `dwxgmac2` actually being *used*? I need to trace this back. The most direct approach is to check for calls to `dwxgmac2_setup` function – that'll give me a strong starting point for the driver initialization path. Alternatively, I can search for instances where `DWXGMAC` hwif entries are being employed, as that would suggest a more abstract interface. Either of these should get me to the right place to understand which hardware is actually leveraging this `dwxgmac2` functionality. Let's see what the code reveals.

{
  "Expression": "STMMAC_DWXGMAC",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-6-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:7:#ifndef __STMMAC_DWXGMAC2_H__\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:8:#define __STMMAC_DWXGMAC2_H__\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-9-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h=468=extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-469-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:470:#endif /* __STMMAC_DWXGMAC2_H__ */\n"
}

gemini-3.7-flash

null

null

							input: 25076
							output: 46
							thoughts: 22
						

Here's a summary of my immediate thought process:

**Diving into `hwif.c`**

Okay, I need to get into the code. My first instinct is to zero in on `hwif.c`. That's where I should be looking based on the current context. And I think that lines 258 and 280 are the most likely hotspots. I need to take a look at what's going on around those line numbers. I expect to be able to quickly zero in on the relevant code.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/hwif.c",
  "FirstLine": 245,
  "LineCount": 50
}

{
  "Contents": " 245:\t\t\t.setup = dwmac4_setup,\n 246:\t\t\t.quirks = NULL,\n 247:\t\t}, {\n 248:\t\t\t.core_type = DWMAC_CORE_XGMAC,\n 249:\t\t\t.min_id = DWXGMAC_CORE_2_10,\n 250:\t\t\t.dev_id = DWXGMAC_ID,\n 251:\t\t\t.regs = {\n 252:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 253:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 254:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 255:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 256:\t\t\t},\n 257:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n 258:\t\t\t.dma = \u0026dwxgmac210_dma_ops,\n 259:\t\t\t.mac = \u0026dwxgmac210_ops,\n 260:\t\t\t.vlan = \u0026dwxgmac210_vlan_ops,\n 261:\t\t\t.hwtimestamp = \u0026dwxgmac2_ptp,\n 262:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 263:\t\t\t.mode = NULL,\n 264:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 265:\t\t\t.mmc = \u0026dwxgmac_mmc_ops,\n 266:\t\t\t.est = \u0026dwmac510_est_ops,\n 267:\t\t\t.setup = dwxgmac2_setup,\n 268:\t\t\t.quirks = NULL,\n 269:\t\t}, {\n 270:\t\t\t.core_type = DWMAC_CORE_XGMAC,\n 271:\t\t\t.min_id = DWXLGMAC_CORE_2_00,\n 272:\t\t\t.dev_id = DWXLGMAC_ID,\n 273:\t\t\t.regs = {\n 274:\t\t\t\t.ptp_off = PTP_XGMAC_OFFSET,\n 275:\t\t\t\t.mmc_off = MMC_XGMAC_OFFSET,\n 276:\t\t\t\t.est_off = EST_XGMAC_OFFSET,\n 277:\t\t\t\t.fpe_reg = \u0026dwxgmac3_fpe_reg,\n 278:\t\t\t},\n 279:\t\t\t.desc = \u0026dwxgmac210_desc_ops,\n 280:\t\t\t.dma = \u0026dwxgmac210_dma_ops,\n 281:\t\t\t.mac = \u0026dwxlgmac2_ops,\n 282:\t\t\t.vlan = \u0026dwxlgmac2_vlan_ops,\n 283:\t\t\t.hwtimestamp = \u0026dwxgmac2_ptp,\n 284:\t\t\t.ptp = \u0026stmmac_ptp_clock_ops,\n 285:\t\t\t.mode = NULL,\n 286:\t\t\t.tc = \u0026dwmac510_tc_ops,\n 287:\t\t\t.mmc = \u0026dwxgmac_mmc_ops,\n 288:\t\t\t.est = \u0026dwmac510_est_ops,\n 289:\t\t\t.setup = dwxlgmac2_setup,\n 290:\t\t},\n 291:\t};\n 292:\t\n 293:\tstatic const struct stmmac_hwif_entry *\n 294:\tstmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\n"
}

gemini-3.7-flash

null

null

							input: 26203
							output: 43
							thoughts: 54
						

Here's my thought process, as if I were analyzing this code:

**Investigating STMMAC Driver Compatibility**

Okay, so I need to figure out which drivers and platforms are probing the STMMAC Ethernet driver with those specific Digital World (DW) MAC core IDs: `DWMAC_CORE_XGMAC` and `dwxgmac2`. My instinct is to first focus on those identifiers because they're the direct hooks, the "keys" if you will.

Then, to broaden the search and ensure I'm getting a complete picture, I need to look beyond those exact identifiers. So, I'll broaden my search within the kernel source to include related identifiers that STMMAC might be using, such as the more generic `DWXGMAC` and `DWXLGMAC`. This expanded search should allow me to catch any potential variations in naming conventions or aliases the code might be employing. It's about being thorough and not missing any connections. I need to see the bigger picture of where STMMAC is being used with this type of MAC core.

{
  "Expression": "DWXGMAC|DWXLGMAC",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/common.h-40-#define DWMAC_CORE_5_20\t\t0x52\ndrivers/net/ethernet/stmicro/stmmac/common.h:41:#define DWXGMAC_CORE_2_10\t0x21\ndrivers/net/ethernet/stmicro/stmmac/common.h:42:#define DWXGMAC_CORE_2_20\t0x22\ndrivers/net/ethernet/stmicro/stmmac/common.h:43:#define DWXLGMAC_CORE_2_00\t0x20\ndrivers/net/ethernet/stmicro/stmmac/common.h-44-\ndrivers/net/ethernet/stmicro/stmmac/common.h-45-/* Device ID */\ndrivers/net/ethernet/stmicro/stmmac/common.h:46:#define DWXGMAC_ID\t\t0x76\ndrivers/net/ethernet/stmicro/stmmac/common.h:47:#define DWXLGMAC_ID\t\t0x27\ndrivers/net/ethernet/stmicro/stmmac/common.h-48-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-6-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:7:#ifndef __STMMAC_DWXGMAC2_H__\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:8:#define __STMMAC_DWXGMAC2_H__\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-9-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h=468=extern const struct stmmac_desc_ops dwxgmac210_desc_ops;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h-469-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2.h:470:#endif /* __STMMAC_DWXGMAC2_H__ */\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c=362=static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-392-\tdma_cap-\u003embps_1000 = (hw_cap \u0026 XGMAC_HWFEAT_GMIISEL) \u003e\u003e 1;\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c:393:\tif (dma_cap-\u003embps_1000 \u0026\u0026 priv-\u003esynopsys_id \u003e= DWXGMAC_CORE_2_20)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c-394-\t\tdma_cap-\u003embps_10_100 = 1;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxlgmac2.h-6-\ndrivers/net/ethernet/stmicro/stmmac/dwxlgmac2.h:7:#ifndef __STMMAC_DWXLGMAC2_H__\ndrivers/net/ethernet/stmicro/stmmac/dwxlgmac2.h:8:#define __STMMAC_DWXLGMAC2_H__\ndrivers/net/ethernet/stmicro/stmmac/dwxlgmac2.h-9-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxlgmac2.h-21-\ndrivers/net/ethernet/stmicro/stmmac/dwxlgmac2.h:22:#endif /* __STMMAC_DWXLGMAC2_H__ */\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-248-\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:249:\t\t.min_id = DWXGMAC_CORE_2_10,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:250:\t\t.dev_id = DWXGMAC_ID,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-251-\t\t.regs = {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-270-\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:271:\t\t.min_id = DWXLGMAC_CORE_2_00,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:272:\t\t.dev_id = DWXLGMAC_ID,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-273-\t\t.regs = {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=72=static void stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-76-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:77:\tif (priv-\u003esynopsys_id \u003c DWXGMAC_CORE_2_20) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-78-\t\t/* Until ver 2.20 XGMAC does not support C22 addr \u003e= 4. Those\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=132=static int stmmac_xgmac2_mdio_read_c22(struct mii_bus *bus, int phyaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-138-\t/* Until ver 2.20 XGMAC does not support C22 addr \u003e= 4 */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:139:\tif (priv-\u003esynopsys_id \u003c DWXGMAC_CORE_2_20 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-140-\t    phyaddr \u003e MII_XGMAC_MAX_C22ADDR)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=195=static int stmmac_xgmac2_mdio_write_c22(struct mii_bus *bus, int phyaddr,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-201-\t/* Until ver 2.20 XGMAC does not support C22 addr \u003e= 4 */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:202:\tif (priv-\u003esynopsys_id \u003c DWXGMAC_CORE_2_20 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-203-\t    phyaddr \u003e MII_XGMAC_MAX_C22ADDR)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=595=int stmmac_mdio_register(struct net_device *ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-627-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:628:\t\tif (priv-\u003esynopsys_id \u003c DWXGMAC_CORE_2_20) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-629-\t\t\t/* Right now only C22 phys are supported */\n"
}

gemini-3.7-flash

null

null

							input: 28627
							output: 49
							thoughts: 46
						

Okay, let's dive into this.

**Examining the dwmac-socfpga Driver**

Alright, so the task at hand is to understand the role of `dwmac-socfpga.c`. My initial thought is to figure out precisely what this driver *does* in the grand scheme of things. Specifically, how does it fit into the broader Ethernet driver ecosystem – what's its relationship with `stmmac`? That's the core question. To get a handle on this, my next step is clear: I need to get my eyes on the source code of `dwmac-socfpga.c`. I'll delve into the code to trace the interactions, dependencies, and any key configuration aspects that shed light on how it communicates and integrates with the `stmmac` framework. Understanding the code's structure and the specific calls it makes will illuminate its function.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c",
  "FirstLine": 1,
  "LineCount": 100
}

{
  "Contents": "   1:\t// SPDX-License-Identifier: GPL-2.0-only\n   2:\t/* Copyright Altera Corporation (C) 2014. All rights reserved.\n   3:\t *\n   4:\t * Adopted from dwmac-sti.c\n   5:\t */\n   6:\t\n   7:\t#include \u003clinux/mfd/altera-sysmgr.h\u003e\n   8:\t#include \u003clinux/clocksource_ids.h\u003e\n   9:\t#include \u003clinux/of.h\u003e\n  10:\t#include \u003clinux/of_address.h\u003e\n  11:\t#include \u003clinux/of_net.h\u003e\n  12:\t#include \u003clinux/phy.h\u003e\n  13:\t#include \u003clinux/regmap.h\u003e\n  14:\t#include \u003clinux/mdio/mdio-regmap.h\u003e\n  15:\t#include \u003clinux/pcs-lynx.h\u003e\n  16:\t#include \u003clinux/reset.h\u003e\n  17:\t#include \u003clinux/stmmac.h\u003e\n  18:\t\n  19:\t#include \"dwxgmac2.h\"\n  20:\t#include \"stmmac.h\"\n  21:\t#include \"stmmac_platform.h\"\n  22:\t#include \"stmmac_ptp.h\"\n  23:\t\n  24:\t#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0\n  25:\t#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1\n  26:\t#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2\n  27:\t#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2\n  28:\t#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003\n  29:\t#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010\n  30:\t#define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000100\n  31:\t\n  32:\t#define SYSMGR_FPGAGRP_MODULE_REG  0x00000028\n  33:\t#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004\n  34:\t#define SYSMGR_FPGAINTF_EMAC_REG\t0x00000070\n  35:\t#define SYSMGR_FPGAINTF_EMAC_BIT\t0x1\n  36:\t\n  37:\t#define EMAC_SPLITTER_CTRL_REG\t\t\t0x0\n  38:\t#define EMAC_SPLITTER_CTRL_SPEED_MASK\t\t0x3\n  39:\t#define EMAC_SPLITTER_CTRL_SPEED_10\t\t0x2\n  40:\t#define EMAC_SPLITTER_CTRL_SPEED_100\t\t0x3\n  41:\t#define EMAC_SPLITTER_CTRL_SPEED_1000\t\t0x0\n  42:\t\n  43:\t#define SGMII_ADAPTER_CTRL_REG\t\t0x00\n  44:\t#define SGMII_ADAPTER_ENABLE\t\t0x0000\n  45:\t#define SGMII_ADAPTER_DISABLE\t\t0x0001\n  46:\t\n  47:\t#define SMTG_MDIO_ADDR\t\t0x15\n  48:\t#define SMTG_TSC_WORD0\t\t0xC\n  49:\t#define SMTG_TSC_WORD1\t\t0xD\n  50:\t#define SMTG_TSC_WORD2\t\t0xE\n  51:\t#define SMTG_TSC_WORD3\t\t0xF\n  52:\t#define SMTG_TSC_SHIFT\t\t16\n  53:\t\n  54:\tstruct socfpga_dwmac;\n  55:\tstruct socfpga_dwmac_ops {\n  56:\t\tint (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv,\n  57:\t\t\t\t    struct device *dev);\n  58:\t\tvoid (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);\n  59:\t};\n  60:\t\n  61:\tstruct socfpga_dwmac {\n  62:\t\tu32\treg_offset;\n  63:\t\tu32\treg_shift;\n  64:\t\tstruct plat_stmmacenet_data *plat_dat;\n  65:\t\tstruct regmap *sys_mgr_base_addr;\n  66:\t\tstruct reset_control *stmmac_rst;\n  67:\t\tstruct reset_control *stmmac_ocp_rst;\n  68:\t\tvoid __iomem *splitter_base;\n  69:\t\tvoid __iomem *tse_pcs_base;\n  70:\t\tvoid __iomem *sgmii_adapter_base;\n  71:\t\tbool f2h_ptp_ref_clk;\n  72:\t\tconst struct socfpga_dwmac_ops *ops;\n  73:\t};\n  74:\t\n  75:\tstatic phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)\n  76:\t{\n  77:\t\treturn dwmac-\u003eplat_dat-\u003ephy_interface;\n  78:\t}\n  79:\t\n  80:\tstatic void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable)\n  81:\t{\n  82:\t\tu16 val = enable ? SGMII_ADAPTER_ENABLE : SGMII_ADAPTER_DISABLE;\n  83:\t\n  84:\t\twritew(val, dwmac-\u003esgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);\n  85:\t}\n  86:\t\n  87:\tstatic void socfpga_dwmac_fix_mac_speed(void *bsp_priv,\n  88:\t\t\t\t\t\tphy_interface_t interface, int speed,\n  89:\t\t\t\t\t\tunsigned int mode)\n  90:\t{\n  91:\t\tstruct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)bsp_priv;\n  92:\t\tvoid __iomem *sgmii_adapter_base = dwmac-\u003esgmii_adapter_base;\n  93:\t\tphy_interface_t phymode = socfpga_get_plat_phymode(dwmac);\n  94:\t\tvoid __iomem *splitter_base = dwmac-\u003esplitter_base;\n  95:\t\tu32 val;\n  96:\t\n  97:\t\tif (sgmii_adapter_base)\n  98:\t\t\tsocfpga_sgmii_config(dwmac, false);\n  99:\t\n 100:\t\tif (splitter_base) {\n"
}

gemini-3.7-flash

null

null

							input: 30712
							output: 38
							thoughts: 738
						

**Analyzing the STMMAC Driver Patch**

Okay, let's break this down. First, this patch affects the Altera SOCFPGA platform, specifically the `dwmac-socfpga.c` file. This tells me we're dealing with an ARM or ARM64-based device that relies on a Device Tree. But what's actually *changed* in the patch? Let's trace it through the files.

*   `drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c`:  I see `stmmac_mac_irq_modify` being called to disable and then re-enable the timestamp interrupt in `smtg_crosststamp()`.  Interesting.

*   `drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h`: This defines the default interrupt enable mask, `XGMAC_INT_DEFAULT_EN`. It includes timestamp-related interrupts.

*   `drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c`: A new function, `dwxgmac2_timestamp_interrupt()`, has been added.  This is a significant change, likely the core of the timestamp functionality.

*   `drivers/net/ethernet/stmicro/stmmac/hwif.c`: This is where the interface table (`.hwtimestamp`) is updated for `DWMAC_CORE_XGMAC` devices.  Crucially, it switches from `stmmac_ptp` to `dwxgmac2_ptp`. This implies a fundamental shift in how hardware timestamping is handled for these XGMAC cores.  We're going from a generic PTP implementation to a more specialized `dwxgmac2` one.

*   `drivers/net/ethernet/stmicro/stmmac/hwif.h`: Just an external declaration of the new `dwxgmac2_ptp`. Expected.

*   `drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c`: The definition of `dwxgmac2_ptp` is the heart of the changes.  It's a structure containing all the hardware timestamping functions specific to this new implementation. The new structure includes callbacks for configuring the hardware, handling sub-second increment, and adjusting system time.

*   `drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h`: The prototype for the new `dwxgmac2_timestamp_interrupt` is defined here.

So, this patch is clearly about refining hardware timestamping support for the XGMAC core within the STMMAC driver. Now, the big question is, can this even *work* in a virtualized environment? I need to understand if STMMAC, especially DWXGMAC, relies on specific hardware features. Is it a strict hardware device?

I need to quickly check if QEMU emulates STMMAC or any of the DWMAC or DWXGMAC devices at all.  Or is STMMAC a PCI driver or platform driver? Let me check `STMMAC_PCI` and see what PCI IDs are in `stmmac_pci.c` or other stmmac PCI drivers to see if any of the hardware is emulated.

{
  "Expression": "pci_driver",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c=1415=MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-1416-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:1417:static struct pci_driver intel_eth_pci_driver = {\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-1418-\t.name = \"intel-eth-pci\",\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-1426-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:1427:module_pci_driver(intel_eth_pci_driver);\ndrivers/net/ethernet/stmicro/stmmac/dwmac-intel.c-1428-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c=602=MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table);\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c-603-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c:604:static struct pci_driver loongson_dwmac_driver = {\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c-605-\t.name = DRIVER_NAME,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c-613-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c:614:module_pci_driver(loongson_dwmac_driver);\ndrivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c-615-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c=371=MODULE_DEVICE_TABLE(pci, dwmac_motorcomm_pci_id_table);\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c-372-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c:373:static struct pci_driver dwmac_motorcomm_pci_driver = {\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c-374-\t.name = DRIVER_NAME,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c-382-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c:383:module_pci_driver(dwmac_motorcomm_pci_driver);\ndrivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c-384-\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c=210=MODULE_DEVICE_TABLE(pci, stmmac_id_table);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-211-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c:212:static struct pci_driver stmmac_pci_driver = {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-213-\t.name = STMMAC_RESOURCE_NAME,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-221-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c:222:module_pci_driver(stmmac_pci_driver);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_pci.c-223-\n"
}

gemini-3.7-flash

null

null

							input: 33262
							output: 43
							thoughts: 95
						

**Investigating XGMAC Driver Implementations**

Okay, so I need to get a handle on how these XGMAC cores are being used in different DWMAC drivers. First, I'm thinking, "Let's start by looking at a few likely suspects: `stmmac_pci.c`, `dwmac-intel.c`, `dwmac-loongson.c`, `dwmac-socfpga.c`, and so on." That should give me a good baseline.

But wait a minute, a more efficient approach would be to narrow the scope from the start. "Let's see which drivers are *actually* utilizing `DWMAC_CORE_XGMAC` or specifically probing for `dwxgmac2`." It's much more surgical.

Right, time to get to work. Now, the fastest and most comprehensive approach to understand the drivers would be a quick codebase search. So, I need to "search for `DWMAC_CORE_XGMAC` in the entire codebase." This should reveal all instances of the macro's use, providing the foundation I need to understand the relationship between the hardware and the software.

{
  "Expression": "DWMAC_CORE_XGMAC",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/common.h=49=static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)\ndrivers/net/ethernet/stmicro/stmmac/common.h-50-{\ndrivers/net/ethernet/stmicro/stmmac/common.h:51:\treturn core_type == DWMAC_CORE_GMAC4 || core_type == DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/common.h-52-}\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c=580=static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-583-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c:584:\tplat_dat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c-585-\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c=214=static int tegra_mgbe_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-325-\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c:326:\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c-327-\tplat-\u003eflags |= STMMAC_FLAG_TSO_EN;\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=21=static void stmmac_get_version(struct stmmac_priv *priv,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-49-\tver-\u003esnpsver = FIELD_GET(DWMAC_SNPSVER, version);\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:50:\tif (core_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-51-\t\tver-\u003edev_id = FIELD_GET(DWMAC_USERVER, version);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=111=static const struct stmmac_hwif_entry {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-247-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:248:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-249-\t\t.min_id = DWXGMAC_CORE_2_10,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-269-\t}, {\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:270:\t\t.core_type = DWMAC_CORE_XGMAC,\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-271-\t\t.min_id = DWXLGMAC_CORE_2_00,\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c=294=stmmac_hwif_find(enum dwmac_core_type core_type, u8 snpsver, u8 dev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-306-\t\t\tcontinue;\ndrivers/net/ethernet/stmicro/stmmac/hwif.c:307:\t\tif (core_type == DWMAC_CORE_XGMAC \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/hwif.c-308-\t\t    dev_id != entry-\u003edev_id)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=28=static int est_configure(struct stmmac_priv *priv, struct stmmac_est *cfg,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-55-\tctrl = readl(est_addr + EST_CONTROL);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:56:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-57-\t\tctrl \u0026= ~EST_XGMAC_PTOV;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c=83=static void est_irq_status(struct stmmac_priv *priv, struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-150-\tif (status \u0026 EST_BTRE) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c:151:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_est.c-152-\t\t\tbtrl = FIELD_GET(EST_XGMAC_BTRL, status);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=301=static void stmmac_ethtool_getdrvinfo(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-308-\t\tstrscpy(info-\u003edriver, GMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:309:\telse if (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-310-\t\tstrscpy(info-\u003edriver, XGMAC_ETHTOOL_NAME, sizeof(info-\u003edriver));\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=350=static int stmmac_ethtool_get_regs_len(struct net_device *dev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-353-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:354:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-355-\t\treturn XGMAC_REGSIZE * 4;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c=361=static void stmmac_ethtool_gregs(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-375-\t\t       NUM_DWMAC4_DMA_REGS * 4);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c:376:\t} else if (priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c-377-\t\tmemcpy(\u0026reg_space[ETHTOOL_DMA_OFFSET],\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=642=static int stmmac_hwtstamp_set(struct net_device *dev,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-758-\t\t\tif (priv-\u003esynopsys_id \u003c DWMAC_CORE_3_70 \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:759:\t\t\t    priv-\u003eplat-\u003ecore_type != DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-760-\t\t\t\tts_event_en = PTP_TCR_TSEVNTENA;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6545=static int stmmac_dma_cap_show(struct seq_file *seq, void *v)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6580-\t\t   (priv-\u003edma_cap.half_duplex) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6581:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6582-\t\tseq_printf(seq,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6604-\t\t   (priv-\u003edma_cap.atime_stamp) ? \"Y\" : \"N\");\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6605:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6606-\t\tseq_printf(seq, \"\\tTimestamp System Time Source: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6613-\tif (priv-\u003esynopsys_id \u003e= DWMAC_CORE_4_00 ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6614:\t    priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6615-\t\tseq_printf(seq, \"\\tIP Checksum Offload in RX: %s\\n\",\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7347=static void stmmac_print_actphyif(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7362-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7363:\tcase DWMAC_CORE_XGMAC:\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7364-\t\tphyif_table = stmmac_dwxgmac_phyif;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7389=static int stmmac_hw_init(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7511-\tif ((priv-\u003esynopsys_id \u003e= DWMAC_CORE_3_50 ||\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7512:\t     priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) \u0026\u0026\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7513-\t    !priv-\u003eplat-\u003eriwt_off) {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=7778=static int __stmmac_dvr_probe(struct device *device,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7985-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:7986:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-7987-\t\tndev-\u003emax_mtu = XGMAC_JUMBO_LEN;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=536=static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-554-\t\trates = stmmac_sun8i_csr_to_mdc;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:555:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-556-\t\trates = stmmac_xgmac_csr_to_mdc;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=595=int stmmac_mdio_register(struct net_device *ndev)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-621-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:622:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-623-\t\tnew_bus-\u003eread = \u0026stmmac_xgmac2_mdio_read_c22;\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-665-\t/* Looks like we need a dummy read for XGMAC only and C45 PHYs */\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:666:\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_XGMAC)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-667-\t\tstmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c=414=stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-545-\tif (of_device_is_compatible(np, \"snps,dwxgmac\")) {\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:546:\t\tplat-\u003ecore_type = DWMAC_CORE_XGMAC;\ndrivers/net/ethernet/stmicro/stmmac/stmmac_platform.c-547-\t\tplat-\u003epmt = true;\n"
}

gemini-3.7-flash

null

null

							input: 37609
							output: 37
							thoughts: 1367
						

**Analyzing Reachability of DesignWare XGMAC Code Paths in Virtualized Environments**

Okay, so I'm digging into this `DWMAC_CORE_XGMAC` stuff. First, I see it defined in a few places: `dwmac-socfpga.c` for Altera Agilex5, `dwmac-tegra.c` for Nvidia Tegra, and `stmmac_platform.c` for devices compatible with "snps,dwxgmac". My initial thought is to figure out if any of this can actually be reached in a virtualized environment like QEMU or Google Compute Engine (GCE), or if we're dealing with solely physical SoCs.

Now, let's refer to the instructions provided. The goal is to determine if this code is worth fuzzing. The instructions explicitly say that we should return `WorthFuzzing=false` if the changes are limited to unreachable code paths in virtualized environments. I need to keep that in mind.

I'm thinking, does QEMU even emulate "snps,dwxgmac" or anything related to those specific SoCs? Let's see what QEMU *does* support for stmmac/designware mac. I see a lot of options: `allwinner-a10-emac`, `cadence_gem`, etc., but nothing that screams "DesignWare 10Gb Ethernet" or Altera SoC FPGA. I'm not seeing any `dwxgmac` equivalent in QEMU. Nope, QEMU does NOT emulate Synopsys DesignWare Enterprise 10G Ethernet MAC or Altera SoC FPGA Agilex5. Intel stmmac is a different story, using GMAC4/GMAC5/DWMAC_CORE_GMAC4/GMAC. Loongson uses DWMAC_CORE_GMAC.

Moreover, QEMU doesn't emulate any Intel stmmac PCI / Loongson PCI / Motorcomm PCI. It emulates the usual suspects like e1000, e1000e, igb, and so on.

The question then becomes, can Syzkaller actually *reach* platform drivers, or are these specific ARM/SoC drivers (Altera socfpga, Nvidia Tegra, Synopsys dwxgmac) fundamentally tied to physical hardware? I've got to consider this. Let's look at similar cases and guidelines.

I need to quickly check if syzkaller or any fuzzing benchmarks account for ethernet drivers on embedded SoCs.

Ok, the instructions are clear: if the code paths are impossible to reach in virtualized environments, return `WorthFuzzing=false`. Also, if the code is in vendor-specific PCIe switch or SmartNIC drivers, like mlxsw, pds_core, qed, ionic, amdgpu, that require physical hardware. Driver teardown callbacks such as `.remove`, `.shutdown`, or `pci_unregister_driver` are also not fuzzable.

So, can this code (specifically `dwxgmac2_timestamp_interrupt`, or the code in `dwmac-socfpga.c`, or `dwxgmac2_ptp`) be reached in QEMU or GCE?

Let's break it down:
1. `dwmac-socfpga.c`: This is Altera SOCFPGA. Specifically, it seems `smtg_crosststamp` is called for PTP cross-timestamping on Altera Agilex/Stratix SOCFPGA. The code interacts directly with FPGA registers and MDIO registers of the SMTG time card / MDIO hardware (via `get_smtgtime`). This feels very hardware-specific.

2. `dwxgmac2_timestamp_interrupt`: This handles timestamp interrupts for the Synopsys DesignWare 10G Ethernet MAC (`dwxgmac2`). The code reads from registers like `XGMAC_TIMESTAMP_STATUS` and `PTP_ACR` and dispatches PTP events. This is hooked by `stmmac_hwif_entry` for `DWMAC_CORE_XGMAC`. It's registered in `dwxgmac2_ptp.timestamp_interrupt`. So when exactly is this `timestamp_interrupt` called? Let's check for how this interrupt handler is called. Time to grep for `timestamp_interrupt` within `drivers/net/ethernet/stmicro/stmmac/`.

{
  "Expression": "timestamp_interrupt",
  "PathPrefix": "drivers/net/ethernet/stmicro/stmmac/"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c=513=void dwmac1000_get_ptptime(void __iomem *ptpaddr, u64 *ptp_time)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c-522-\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c:523:void dwmac1000_timestamp_interrupt(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c-524-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c-552-\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c:553:static void dwmac1000_timestamp_interrupt_cfg(struct stmmac_priv *priv, bool en)\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c-554-{\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c=567=int dwmac1000_ptp_enable(struct ptp_clock_info *ptp,\n--\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c-600-\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c:601:\t\tdwmac1000_timestamp_interrupt_cfg(priv, on);\ndrivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c-602-\t\tbreak;\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c=1143=static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *ts)\n--\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1156-\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c:1157:void dwxgmac2_timestamp_interrupt(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c-1158-{\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h=497=struct stmmac_hwtimestamp {\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-506-\tvoid (*get_ptptime)(void __iomem *ioaddr, u64 *ptp_time);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:507:\tvoid (*timestamp_interrupt)(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-508-\tvoid (*hwtstamp_correct_latency)(struct stmmac_priv *priv);\n--\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-524-\tstmmac_do_void_callback(__priv, ptp, get_ptptime, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:525:#define stmmac_timestamp_interrupt(__priv, __args...) \\\ndrivers/net/ethernet/stmicro/stmmac/hwif.h:526:\tstmmac_do_void_callback(__priv, ptp, timestamp_interrupt, __args)\ndrivers/net/ethernet/stmicro/stmmac/hwif.h-527-#define stmmac_hwtstamp_correct_latency(__priv, __args...) \\\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c=204=static void get_ptptime(void __iomem *ptpaddr, u64 *ptp_time)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c-213-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c:214:static void timestamp_interrupt(struct stmmac_priv *priv)\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c-215-{\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c=258=const struct stmmac_hwtimestamp stmmac_ptp = {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c-265-\t.get_ptptime = get_ptptime,\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c:266:\t.timestamp_interrupt = timestamp_interrupt,\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c-267-\t.hwtstamp_correct_latency = hwtstamp_correct_latency,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c=270=const struct stmmac_hwtimestamp dwmac1000_ptp = {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c-277-\t.get_ptptime = dwmac1000_get_ptptime,\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c:278:\t.timestamp_interrupt = dwmac1000_timestamp_interrupt,\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c-279-};\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c=281=const struct stmmac_hwtimestamp dwxgmac2_ptp = {\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c-288-\t.get_ptptime = get_ptptime,\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c:289:\t.timestamp_interrupt = dwxgmac2_timestamp_interrupt,\ndrivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c-290-\t.hwtstamp_correct_latency = hwtstamp_correct_latency,\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=6209=static void stmmac_common_interrupt(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6244-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:6245:\t\tstmmac_timestamp_interrupt(priv, priv);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-6246-\t}\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h=104=void dwmac1000_get_ptptime(void __iomem *ptpaddr, u64 *ptp_time);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h:105:void dwmac1000_timestamp_interrupt(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h:106:void dwxgmac2_timestamp_interrupt(struct stmmac_priv *priv);\ndrivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h-107-\n"
}

gemini-3.7-flash

null

null

							input: 41989
							output: 50
							thoughts: 64
						

Okay, let's break this down. My initial question is: what actually kicks off the `stmmac_timestamp_interrupt` function? I need to understand the control flow here. So, I see that this interrupt is likely handled by `stmmac_common_interrupt`, and that's found in `stmmac_main.c`.

**Diving into the Interrupt Handling**

I'm zeroing in on `stmmac_main.c` now, specifically around lines 6209 to 6250. That's the likely region where the interrupt logic is handled. I'll need to carefully examine that section of the code to trace the conditions that lead to the `stmmac_timestamp_interrupt` being called. I need to understand the interrupt enable/disable mechanisms and interrupt status checks that take place to get the full picture. My goal is to map the path of execution to understand how this timestamp interrupt is triggered and what the critical pieces of context are for its operation.

{
  "File": "drivers/net/ethernet/stmicro/stmmac/stmmac_main.c",
  "FirstLine": 6205,
  "LineCount": 45
}

{
  "Contents": "6205:\t\n6206:\t\treturn 0;\n6207:\t}\n6208:\t\n6209:\tstatic void stmmac_common_interrupt(struct stmmac_priv *priv)\n6210:\t{\n6211:\t\tu8 rx_cnt = priv-\u003eplat-\u003erx_queues_to_use;\n6212:\t\tu8 tx_cnt = priv-\u003eplat-\u003etx_queues_to_use;\n6213:\t\tu8 queues_count;\n6214:\t\tbool xmac;\n6215:\t\tu8 queue;\n6216:\t\n6217:\t\txmac = dwmac_is_xmac(priv-\u003eplat-\u003ecore_type);\n6218:\t\tqueues_count = (rx_cnt \u003e tx_cnt) ? rx_cnt : tx_cnt;\n6219:\t\n6220:\t\tif (priv-\u003eirq_wake)\n6221:\t\t\tpm_wakeup_event(priv-\u003edevice, 0);\n6222:\t\n6223:\t\tif (priv-\u003edma_cap.estsel)\n6224:\t\t\tstmmac_est_irq_status(priv, priv, priv-\u003edev,\n6225:\t\t\t\t\t      \u0026priv-\u003exstats, tx_cnt);\n6226:\t\n6227:\t\tif (stmmac_fpe_supported(priv))\n6228:\t\t\tstmmac_fpe_irq_status(priv);\n6229:\t\n6230:\t\t/* To handle GMAC own interrupts */\n6231:\t\tif (priv-\u003eplat-\u003ecore_type == DWMAC_CORE_GMAC || xmac) {\n6232:\t\t\tint status = stmmac_host_irq_status(priv, \u0026priv-\u003exstats);\n6233:\t\n6234:\t\t\tif (unlikely(status)) {\n6235:\t\t\t\t/* For LPI we need to save the tx status */\n6236:\t\t\t\tif (status \u0026 CORE_IRQ_TX_PATH_IN_LPI_MODE)\n6237:\t\t\t\t\tpriv-\u003etx_path_in_lpi_mode = true;\n6238:\t\t\t\tif (status \u0026 CORE_IRQ_TX_PATH_EXIT_LPI_MODE)\n6239:\t\t\t\t\tpriv-\u003etx_path_in_lpi_mode = false;\n6240:\t\t\t}\n6241:\t\n6242:\t\t\tfor (queue = 0; queue \u003c queues_count; queue++)\n6243:\t\t\t\tstmmac_host_mtl_irq_status(priv, priv-\u003ehw, queue);\n6244:\t\n6245:\t\t\tstmmac_timestamp_interrupt(priv, priv);\n6246:\t\t}\n6247:\t}\n6248:\t\n6249:\t/**\n"
}

gemini-3.7-flash

null

null

							input: 43050
							output: 112
							thoughts: 1374
						

**Analysis of the Patch for Fuzzing Suitability**

Okay, let's break this down. The first thing I'm doing is trying to understand the target hardware of the code modifications in this patch. I see references to `DWMAC_CORE_XGMAC` and `dwmac-socfpga`.  `dwmac-socfpga` immediately flags as Altera/Intel SOCFPGA, specifically Agilex 5, Stratix 10, or similar.  I also see mention of `dwmac-tegra` (NVIDIA Tegra) and `snps,dwxgmac` (Synopsys DesignWare Enterprise 10G Ethernet MAC).  None of these device types are emulated in standard QEMU or Google Compute Engine, which is a key consideration.

Now, I'm checking to see *if* QEMU even provides emulation for any STMMAC or DWMAC controllers. I find that QEMU has `allwinner-a10-emac`, which is not a DWMAC but is a sun4i emac. Even if QEMU *did* emulate a basic DWMAC (like sun8i or stm32), none of those would be XGMAC (10Gbps MAC) or the Altera/Intel SOCFPGA version (`dwmac-socfpga`).

Then the thought strikes to check if there are PCI emulations. The short answer is no; QEMU lacks specific models for the Intel Elkhart Lake/Tiger Lake PSE dwmac, Loongson or Motorcomm PCI ethernet implementations.

Looking closely at the specific files being modified, I see `dwmac-socfpga.c`, which is the Altera SOCFPGA-specific driver that deals with the SMTG time stamp card interface. The other files, `dwxgmac2_timestamp_interrupt` in `dwxgmac2_core.c` and a few others, are dealing with the DWXGMAC (10Gbps DesignWare MAC) timestamp functionality.

Now, I'm re-reading the rules regarding what makes a patch *not* worth fuzzing.  This includes things that are unreachable in virtualized environments like QEMU or GCE. This includes code that relies on physical PCIe hardware cards not emulated in QEMU.

Given the rule set, the central question becomes: are STMMAC / DWXGMAC / DWMAC_SOCFPGA features reachable within QEMU or GCE? The answer is a clear no.

1.  `DWMAC-SoCFPGA` requires real Altera/Intel SoC FPGA hardware with specific system manager registers and FPGA fabric interfaces.
2.  `DWXGMAC` is a Synopsys 10G Ethernet MAC IP, found only in specific physical SoCs like Altera Agilex 5 and Nvidia Tegra234/Thor.
3.  Standard QEMU does *not* emulate these Synopsys DWXGMAC or Altera SoC FPGA Ethernet controllers.
4.  GCE doesn't provide emulation either.

Therefore, the modified code is not reachable in these environments.  I double-check the files and the descriptions of the changes, and I'm looking for any other modifications. The diffs confirm that all modifications are confined to hardware-specific driver code that relies on these physical SoCs and FPGAs.  The patch impacts things like timestamp interrupt handling for DWXGMAC and cross-timestamping in the Altera SoCFPGA driver.  Both are not accessible in QEMU or GCE.

The conclusion is that this patch is not suitable for fuzzing.  The `WorthFuzzing` flag should be set to `false`. There are no specific symbols or configurations to enable or focus on since the code can't be executed, and the reasoning is clear: the changes are hardware-dependent and can't be emulated in standard QEMU or GCE.

Finally, I'm setting the following parameters for the `set-results` tool:

*   `WorthFuzzing`: `false`
*   `FocusSymbols`: `[]`
*   `EnableConfigs`: `[]`
*   `Reasoning`: Concise explanation of why it is `false`.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Synopsys STMMAC DWXGMAC (10G MAC) timestamp interrupt handling and Altera SoCFPGA ethernet glue driver. These code paths require physical SoC/FPGA hardware (such as Intel/Altera SoCFPGA or Nvidia Tegra platforms) that is not available or emulated in standard virtualized environments like QEMU or GCE.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Synopsys STMMAC DWXGMAC (10G MAC) timestamp interrupt handling and Altera SoCFPGA ethernet glue driver. These code paths require physical SoC/FPGA hardware (such as Intel/Altera SoCFPGA or Nvidia Tegra platforms) that is not available or emulated in standard virtualized environments like QEMU or GCE.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

null