| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/10/09 19:37 | flow | patch-triage |
0mArgs:null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"KMSANReasoning": "",
"NeedsKMSAN": false,
"Reasoning": "The patch adds clock control unit (CCU) drivers for the Allwinner A733 SoC (sun60i) and updates the internal sunxi-ng sigma-delta modulation helpers. All modified code is exclusive to Allwinner ARM/ARM64 SoCs (ARCH_SUNXI) and requires hardware/Device Tree nodes not present or emulated in standard amd64 QEMU/GCE environments. Because the target architecture is amd64, the modified code is structurally unreachable.",
"WorthFuzzing": false
} |
| 1/1 | 2026/10/09 19:37 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit a9173363d90393b3f3686151263e63fb4dd6f778\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Fri Oct 9 19:37:25 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml\nnew file mode 100644\nindex 0000000000000..7c9068d3bbb05\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml\n@@ -0,0 +1,107 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/clock/allwinner,sun60i-a733-ccu.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Allwinner A733 Clock Control Unit\n+\n+maintainers:\n+ - Junhui Liu \u003cjunhui.liu@pigmoral.tech\u003e\n+\n+properties:\n+ compatible:\n+ enum:\n+ - allwinner,sun60i-a733-ccu\n+ - allwinner,sun60i-a733-r-ccu\n+\n+ reg:\n+ maxItems: 1\n+\n+ clocks:\n+ minItems: 4\n+ maxItems: 7\n+\n+ clock-names:\n+ minItems: 4\n+ maxItems: 7\n+\n+ \"#clock-cells\":\n+ const: 1\n+\n+ \"#reset-cells\":\n+ const: 1\n+\n+required:\n+ - compatible\n+ - reg\n+ - clocks\n+ - clock-names\n+ - \"#clock-cells\"\n+ - \"#reset-cells\"\n+\n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ enum:\n+ - allwinner,sun60i-a733-ccu\n+\n+ then:\n+ properties:\n+ clocks:\n+ items:\n+ - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz)\n+ - description: Low Frequency Oscillator (usually at 32kHz)\n+ - description: Internal Oscillator\n+ - description: Low Frequency Oscillator fanout\n+\n+ clock-names:\n+ items:\n+ - const: hosc\n+ - const: losc\n+ - const: iosc\n+ - const: losc-fanout\n+\n+ - if:\n+ properties:\n+ compatible:\n+ enum:\n+ - allwinner,sun60i-a733-r-ccu\n+\n+ then:\n+ properties:\n+ clocks:\n+ items:\n+ - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz)\n+ - description: Low Frequency Oscillator (usually at 32kHz)\n+ - description: Internal Oscillator\n+ - description: System 24MHz Clock\n+ - description: Peripherals PLL 0 (200 MHz output)\n+ - description: Peripherals PLL 0 (300 MHz output)\n+ - description: Peripherals PLL 1 (300 MHz output)\n+\n+ clock-names:\n+ items:\n+ - const: hosc\n+ - const: losc\n+ - const: iosc\n+ - const: sys-24m\n+ - const: pll-periph0-200m\n+ - const: pll-periph0-300m\n+ - const: pll-periph1-300m\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ clock-controller@2002000 {\n+ compatible = \"allwinner,sun60i-a733-ccu\";\n+ reg = \u003c0x02002000 0x2000\u003e;\n+ clocks = \u003c\u0026osc\u003e, \u003c\u0026rtc 0\u003e, \u003c\u0026rtc 2\u003e, \u003c\u0026rtc 1\u003e;\n+ clock-names = \"hosc\", \"losc\", \"iosc\", \"losc-fanout\";\n+ #clock-cells = \u003c1\u003e;\n+ #reset-cells = \u003c1\u003e;\n+ };\n+\n+...\ndiff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig\nindex 6af2d020e03e9..cffa83056934a 100644\n--- a/drivers/clk/sunxi-ng/Kconfig\n+++ b/drivers/clk/sunxi-ng/Kconfig\n@@ -67,6 +67,16 @@ config SUN55I_A523_R_CCU\n \tdefault ARCH_SUNXI\n \tdepends on ARM64 || COMPILE_TEST\n \n+config SUN60I_A733_CCU\n+\ttristate \"Support for the Allwinner A733 CCU\"\n+\tdefault ARCH_SUNXI\n+\tdepends on ARM64 || COMPILE_TEST\n+\n+config SUN60I_A733_R_CCU\n+\ttristate \"Support for the Allwinner A733 PRCM CCU\"\n+\tdefault ARCH_SUNXI\n+\tdepends on ARM64 || COMPILE_TEST\n+\n config SUN4I_A10_CCU\n \ttristate \"Support for the Allwinner A10/A20 CCU\"\n \tdefault ARCH_SUNXI\ndiff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile\nindex a1c4087d72417..3a39eb9287da0 100644\n--- a/drivers/clk/sunxi-ng/Makefile\n+++ b/drivers/clk/sunxi-ng/Makefile\n@@ -36,6 +36,8 @@ obj-$(CONFIG_SUN50I_H616_CCU)\t+= sun50i-h616-ccu.o\n obj-$(CONFIG_SUN55I_A523_CCU)\t+= sun55i-a523-ccu.o\n obj-$(CONFIG_SUN55I_A523_MCU_CCU)\t+= sun55i-a523-mcu-ccu.o\n obj-$(CONFIG_SUN55I_A523_R_CCU)\t+= sun55i-a523-r-ccu.o\n+obj-$(CONFIG_SUN60I_A733_CCU)\t+= sun60i-a733-ccu.o\n+obj-$(CONFIG_SUN60I_A733_R_CCU)\t+= sun60i-a733-r-ccu.o\n obj-$(CONFIG_SUN4I_A10_CCU)\t+= sun4i-a10-ccu.o\n obj-$(CONFIG_SUN5I_CCU)\t\t+= sun5i-ccu.o\n obj-$(CONFIG_SUN6I_A31_CCU)\t+= sun6i-a31-ccu.o\n@@ -64,6 +66,8 @@ sun50i-h616-ccu-y\t\t+= ccu-sun50i-h616.o\n sun55i-a523-ccu-y\t\t+= ccu-sun55i-a523.o\n sun55i-a523-mcu-ccu-y\t\t+= ccu-sun55i-a523-mcu.o\n sun55i-a523-r-ccu-y\t\t+= ccu-sun55i-a523-r.o\n+sun60i-a733-ccu-y\t\t+= ccu-sun60i-a733.o\n+sun60i-a733-r-ccu-y\t\t+= ccu-sun60i-a733-r.o\n sun4i-a10-ccu-y\t\t\t+= ccu-sun4i-a10.o\n sun5i-ccu-y\t\t\t+= ccu-sun5i.o\n sun6i-a31-ccu-y\t\t\t+= ccu-sun6i-a31.o\ndiff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c\nnew file mode 100644\nindex 0000000000000..b8f6e8c6e5073\n--- /dev/null\n+++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c\n@@ -0,0 +1,277 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (C) 2023 rengaomin@allwinnertech.com\n+ * Copyright (C) 2026 Junhui Liu \u003cjunhui.liu@pigmoral.tech\u003e\n+ * Based on the A523 CCU driver:\n+ * Copyright (C) 2024 Arm Ltd.\n+ *\n+ * When secure boot is enabled, firmware must configure PRCM_SEC_SWITCH_REG\n+ * to make the AHBS, APBS0 and APBS1 clock registers accessible to the\n+ * non-secure world.\n+ *\n+ * S_TWD_BGR_REG is fixed to be a secure register regardless of whether\n+ * secure boot is enabled, so it is not described here.\n+ */\n+\n+#include \u003clinux/clk-provider.h\u003e\n+#include \u003clinux/module.h\u003e\n+#include \u003clinux/platform_device.h\u003e\n+\n+#include \u003cdt-bindings/clock/allwinner,sun60i-a733-r-ccu.h\u003e\n+#include \u003cdt-bindings/reset/allwinner,sun60i-a733-r-ccu.h\u003e\n+\n+#include \"ccu_common.h\"\n+#include \"ccu_reset.h\"\n+\n+#include \"ccu_div.h\"\n+#include \"ccu_gate.h\"\n+#include \"ccu_mp.h\"\n+\n+static const struct clk_parent_data r_ahb_parents[] = {\n+\t{ .fw_name = \"hosc\" },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+\t{ .fw_name = \"pll-periph0-200m\" },\n+\t{ .fw_name = \"pll-periph0-300m\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX(r_ahb_clk, \"r-ahb\", r_ahb_parents, 0x000,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data r_apb_parents[] = {\n+\t{ .fw_name = \"hosc\" },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+\t{ .fw_name = \"pll-periph0-200m\" },\n+\t{ .fw_name = \"sys-24m\" },\n+};\n+\n+static SUNXI_CCU_M_DATA_WITH_MUX(r_apb0_clk, \"r-apb0\", r_apb_parents, 0x00c,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, \"r-apb1\", r_apb_parents, 0x010,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, \"r-timer0\", r_apb_parents, 0x100,\n+\t\t\t\t 1, 3,\t/* P */\n+\t\t\t\t 4, 3,\t/* mux */\n+\t\t\t\t BIT(0),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, \"r-timer1\", r_apb_parents, 0x104,\n+\t\t\t\t 1, 3,\t/* P */\n+\t\t\t\t 4, 3,\t/* mux */\n+\t\t\t\t BIT(0),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer2, \"r-timer2\", r_apb_parents, 0x108,\n+\t\t\t\t 1, 3,\t/* P */\n+\t\t\t\t 4, 3,\t/* mux */\n+\t\t\t\t BIT(0),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer3, \"r-timer3\", r_apb_parents, 0x10c,\n+\t\t\t\t 1, 3,\t/* P */\n+\t\t\t\t 4, 3,\t/* mux */\n+\t\t\t\t BIT(0),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_GATE_HW(bus_r_timer_clk, \"bus-r-timer\", \u0026r_ahb_clk.common.hw, 0x11c, BIT(0), 0);\n+\n+static const struct clk_parent_data r_pwm_parents[] = {\n+\t{ .fw_name = \"hosc\" },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+\t{ .fw_name = \"sys-24m\" },\n+};\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwm_clk, \"r-pwm\", r_pwm_parents, 0x130,\n+\t\t\t\t 24, 2,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HW(bus_r_pwm_clk, \"bus-r-pwm\",\n+\t\t\t \u0026r_apb0_clk.common.hw, 0x13c, BIT(0), 0);\n+\n+static const struct clk_parent_data r_spi_parents[] = {\n+\t{ .fw_name = \"hosc\" },\n+\t{ .fw_name = \"pll-periph0-200m\" },\n+\t{ .fw_name = \"pll-periph0-300m\" },\n+\t{ .fw_name = \"pll-periph1-300m\" },\n+\t{ .fw_name = \"sys-24m\" },\n+};\n+static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, \"r-spi\", r_spi_parents, 0x150,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HW(bus_r_spi_clk, \"bus-r-spi\", \u0026r_ahb_clk.common.hw, 0x15c, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, \"bus-r-msgbox\", \u0026r_ahb_clk.common.hw, 0x17c, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HW(bus_r_uart0_clk, \"bus-r-uart0\", \u0026r_apb1_clk.common.hw, 0x18c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HW(bus_r_uart1_clk, \"bus-r-uart1\", \u0026r_apb1_clk.common.hw, 0x18c, BIT(1), 0);\n+\n+static SUNXI_CCU_GATE_HW(bus_r_i2c0_clk, \"bus-r-i2c0\", \u0026r_apb1_clk.common.hw, 0x19c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HW(bus_r_i2c1_clk, \"bus-r-i2c1\", \u0026r_apb1_clk.common.hw, 0x19c, BIT(1), 0);\n+static SUNXI_CCU_GATE_HW(bus_r_i2c2_clk, \"bus-r-i2c2\", \u0026r_apb1_clk.common.hw, 0x19c, BIT(2), 0);\n+\n+static SUNXI_CCU_GATE_HW(bus_r_ppu_clk, \"bus-r-ppu\", \u0026r_apb0_clk.common.hw, 0x1ac, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HW(bus_r_tzma_clk, \"bus-r-tzma\", \u0026r_apb0_clk.common.hw, 0x1b0, BIT(0), 0);\n+static SUNXI_CCU_GATE_HW(bus_r_cpu_bist_clk, \"bus-r-cpu-bist\", \u0026r_apb0_clk.common.hw,\n+\t\t\t 0x1bc, BIT(0), 0);\n+\n+static const struct clk_parent_data r_ir_rx_parents[] = {\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"hosc\" },\n+\t{ .fw_name = \"sys-24m\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(r_ir_rx_clk, \"r-ir-rx\", r_ir_rx_parents, 0x1c0,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 2,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, \"bus-r-ir-rx\", \u0026r_apb0_clk.common.hw, 0x1cc, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, \"bus-r-rtc\", \u0026r_ahb_clk.common.hw, 0x20c, BIT(0), 0);\n+\n+static const struct clk_parent_data r_riscv_parents[] = {\n+\t{ .fw_name = \"hosc\" },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+};\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(r_riscv_clk, \"r-riscv\", r_riscv_parents, 0x210,\n+\t\t\t\t 24, 2,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HW(bus_r_riscv_clk, \"bus-r-riscv\", \u0026r_apb0_clk.common.hw,\n+\t\t\t 0x21c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HW(bus_r_riscv_cfg_clk, \"bus-r-riscv-cfg\", \u0026r_apb0_clk.common.hw,\n+\t\t\t 0x21c, BIT(1), 0);\n+\n+static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, \"bus-r-cpucfg\", \u0026r_apb0_clk.common.hw,\n+\t\t\t 0x22c, BIT(0), CLK_IS_CRITICAL);\n+\n+static struct ccu_common *sun60i_a733_r_ccu_clks[] = {\n+\t\u0026r_ahb_clk.common,\n+\t\u0026r_apb0_clk.common,\n+\t\u0026r_apb1_clk.common,\n+\t\u0026r_cpu_timer0.common,\n+\t\u0026r_cpu_timer1.common,\n+\t\u0026r_cpu_timer2.common,\n+\t\u0026r_cpu_timer3.common,\n+\t\u0026bus_r_timer_clk.common,\n+\t\u0026r_pwm_clk.common,\n+\t\u0026bus_r_pwm_clk.common,\n+\t\u0026r_spi_clk.common,\n+\t\u0026bus_r_spi_clk.common,\n+\t\u0026bus_r_msgbox_clk.common,\n+\t\u0026bus_r_uart0_clk.common,\n+\t\u0026bus_r_uart1_clk.common,\n+\t\u0026bus_r_i2c0_clk.common,\n+\t\u0026bus_r_i2c1_clk.common,\n+\t\u0026bus_r_i2c2_clk.common,\n+\t\u0026bus_r_ppu_clk.common,\n+\t\u0026bus_r_tzma_clk.common,\n+\t\u0026bus_r_cpu_bist_clk.common,\n+\t\u0026r_ir_rx_clk.common,\n+\t\u0026bus_r_ir_rx_clk.common,\n+\t\u0026bus_r_rtc_clk.common,\n+\t\u0026r_riscv_clk.common,\n+\t\u0026bus_r_riscv_clk.common,\n+\t\u0026bus_r_riscv_cfg_clk.common,\n+\t\u0026bus_r_cpucfg_clk.common,\n+};\n+\n+static struct clk_hw_onecell_data sun60i_a733_r_hw_clks = {\n+\t.hws = {\n+\t\t[CLK_R_AHB]\t\t= \u0026r_ahb_clk.common.hw,\n+\t\t[CLK_R_APB0]\t\t= \u0026r_apb0_clk.common.hw,\n+\t\t[CLK_R_APB1]\t\t= \u0026r_apb1_clk.common.hw,\n+\t\t[CLK_R_TIMER0]\t\t= \u0026r_cpu_timer0.common.hw,\n+\t\t[CLK_R_TIMER1]\t\t= \u0026r_cpu_timer1.common.hw,\n+\t\t[CLK_R_TIMER2]\t\t= \u0026r_cpu_timer2.common.hw,\n+\t\t[CLK_R_TIMER3]\t\t= \u0026r_cpu_timer3.common.hw,\n+\t\t[CLK_BUS_R_TIMER]\t= \u0026bus_r_timer_clk.common.hw,\n+\t\t[CLK_R_PWM]\t\t= \u0026r_pwm_clk.common.hw,\n+\t\t[CLK_BUS_R_PWM]\t\t= \u0026bus_r_pwm_clk.common.hw,\n+\t\t[CLK_R_SPI]\t\t= \u0026r_spi_clk.common.hw,\n+\t\t[CLK_BUS_R_SPI]\t\t= \u0026bus_r_spi_clk.common.hw,\n+\t\t[CLK_BUS_R_MSGBOX]\t= \u0026bus_r_msgbox_clk.common.hw,\n+\t\t[CLK_BUS_R_UART0]\t= \u0026bus_r_uart0_clk.common.hw,\n+\t\t[CLK_BUS_R_UART1]\t= \u0026bus_r_uart1_clk.common.hw,\n+\t\t[CLK_BUS_R_I2C0]\t= \u0026bus_r_i2c0_clk.common.hw,\n+\t\t[CLK_BUS_R_I2C1]\t= \u0026bus_r_i2c1_clk.common.hw,\n+\t\t[CLK_BUS_R_I2C2]\t= \u0026bus_r_i2c2_clk.common.hw,\n+\t\t[CLK_BUS_R_PPU]\t\t= \u0026bus_r_ppu_clk.common.hw,\n+\t\t[CLK_BUS_R_TZMA]\t= \u0026bus_r_tzma_clk.common.hw,\n+\t\t[CLK_BUS_R_CPU_BIST]\t= \u0026bus_r_cpu_bist_clk.common.hw,\n+\t\t[CLK_R_IR_RX]\t\t= \u0026r_ir_rx_clk.common.hw,\n+\t\t[CLK_BUS_R_IR_RX]\t= \u0026bus_r_ir_rx_clk.common.hw,\n+\t\t[CLK_BUS_R_RTC]\t\t= \u0026bus_r_rtc_clk.common.hw,\n+\t\t[CLK_R_RISCV]\t\t= \u0026r_riscv_clk.common.hw,\n+\t\t[CLK_BUS_R_RISCV]\t= \u0026bus_r_riscv_clk.common.hw,\n+\t\t[CLK_BUS_R_RISCV_CFG]\t= \u0026bus_r_riscv_cfg_clk.common.hw,\n+\t\t[CLK_BUS_R_CPUCFG]\t= \u0026bus_r_cpucfg_clk.common.hw,\n+\t},\n+\t.num = CLK_BUS_R_CPUCFG + 1,\n+};\n+\n+static const struct ccu_reset_map sun60i_a733_r_ccu_resets[] = {\n+\t[RST_BUS_R_TIMER]\t= { 0x11c, BIT(16) },\n+\t[RST_BUS_R_PWM]\t\t= { 0x13c, BIT(16) },\n+\t[RST_BUS_R_SPI]\t\t= { 0x15c, BIT(16) },\n+\t[RST_BUS_R_MSGBOX]\t= { 0x17c, BIT(16) },\n+\t[RST_BUS_R_UART0]\t= { 0x18c, BIT(16) },\n+\t[RST_BUS_R_UART1]\t= { 0x18c, BIT(17) },\n+\t[RST_BUS_R_I2C0]\t= { 0x19c, BIT(16) },\n+\t[RST_BUS_R_I2C1]\t= { 0x19c, BIT(17) },\n+\t[RST_BUS_R_I2C2]\t= { 0x19c, BIT(18) },\n+\t[RST_BUS_R_IR_RX]\t= { 0x1cc, BIT(16) },\n+\t[RST_BUS_R_RTC]\t\t= { 0x20c, BIT(16) },\n+\t[RST_BUS_R_RISCV_CFG]\t= { 0x21c, BIT(16) },\n+\t[RST_BUS_R_CPUCFG]\t= { 0x22c, BIT(16) },\n+};\n+\n+static const struct sunxi_ccu_desc sun60i_a733_r_ccu_desc = {\n+\t.ccu_clks\t= sun60i_a733_r_ccu_clks,\n+\t.num_ccu_clks\t= ARRAY_SIZE(sun60i_a733_r_ccu_clks),\n+\n+\t.hw_clks\t= \u0026sun60i_a733_r_hw_clks,\n+\n+\t.resets\t\t= sun60i_a733_r_ccu_resets,\n+\t.num_resets\t= ARRAY_SIZE(sun60i_a733_r_ccu_resets),\n+};\n+\n+static int sun60i_a733_r_ccu_probe(struct platform_device *pdev)\n+{\n+\tvoid __iomem *reg;\n+\n+\treg = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(reg))\n+\t\treturn PTR_ERR(reg);\n+\n+\treturn devm_sunxi_ccu_probe(\u0026pdev-\u003edev, reg, \u0026sun60i_a733_r_ccu_desc);\n+}\n+\n+static const struct of_device_id sun60i_a733_r_ccu_ids[] = {\n+\t{ .compatible = \"allwinner,sun60i-a733-r-ccu\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, sun60i_a733_r_ccu_ids);\n+\n+static struct platform_driver sun60i_a733_r_ccu_driver = {\n+\t.probe\t= sun60i_a733_r_ccu_probe,\n+\t.driver\t= {\n+\t\t.name\t\t\t= \"sun60i-a733-r-ccu\",\n+\t\t.suppress_bind_attrs\t= true,\n+\t\t.of_match_table\t\t= sun60i_a733_r_ccu_ids,\n+\t},\n+};\n+module_platform_driver(sun60i_a733_r_ccu_driver);\n+\n+MODULE_IMPORT_NS(\"SUNXI_CCU\");\n+MODULE_DESCRIPTION(\"Support for the Allwinner A733 PRCM CCU\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c\nnew file mode 100644\nindex 0000000000000..cc2b229e2e6a6\n--- /dev/null\n+++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c\n@@ -0,0 +1,2422 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (C) 2023 rengaomin@allwinnertech.com\n+ * Copyright (C) 2026 Junhui Liu \u003cjunhui.liu@pigmoral.tech\u003e\n+ * Based on the A523 CCU driver:\n+ * Copyright (C) 2023-2024 Arm Ltd.\n+ *\n+ * When secure boot is enabled, firmware must configure CCMU_SEC_SWITCH_REG\n+ * to make the PLL, bus and MBUS clock registers accessible to the\n+ * non-secure world.\n+ *\n+ * CPU_PERI_CLK_REG has no documented consumer, while NSI_CLK_REG has no\n+ * known kernel consumer, so they are not modelled here.\n+ *\n+ * TODO: The real parents of some bus gates, including its-pcie0-aclk,\n+ * msi-lite, npu, sgpio, lpc and i2spcm, are not documented in the\n+ * manual. For now, follow the vendor BSP, which keeps them on hosc.\n+ */\n+\n+#include \u003clinux/clk-provider.h\u003e\n+#include \u003clinux/io.h\u003e\n+#include \u003clinux/module.h\u003e\n+#include \u003clinux/platform_device.h\u003e\n+\n+#include \u003cdt-bindings/clock/allwinner,sun60i-a733-ccu.h\u003e\n+#include \u003cdt-bindings/reset/allwinner,sun60i-a733-ccu.h\u003e\n+\n+#include \"ccu_common.h\"\n+#include \"ccu_reset.h\"\n+\n+#include \"ccu_div.h\"\n+#include \"ccu_gate.h\"\n+#include \"ccu_mp.h\"\n+#include \"ccu_mult.h\"\n+#include \"ccu_mux.h\"\n+#include \"ccu_nkmp.h\"\n+#include \"ccu_nm.h\"\n+\n+/*\n+ * The DCXO oscillator, the root of most of the clock tree, which may be\n+ * 19.2MHz, 24MHz, or 26MHz.\n+ */\n+static const struct clk_parent_data hosc[] = {\n+\t{ .fw_name = \"hosc\" }\n+};\n+\n+/**************************************************************************\n+ * PLLs *\n+ **************************************************************************/\n+\n+/*\n+ * Undocumented, taken from the vendor kernel.\n+ * PLL_REF normalizes the DCXO frequency to a 24MHz reference for downstream\n+ * PLLs.\n+ */\n+#define SUN60I_A733_PLL_REF_REG\t\t0x000\n+static struct ccu_nkmp pll_ref_clk = {\n+\t.enable\t\t= BIT(27),\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT(8, 8),\n+\t.m\t\t= _SUNXI_CCU_DIV(16, 7), /* output divider */\n+\t.p\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_REF_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_DATA(\"pll-ref\", hosc,\n+\t\t\t\t\t\t\t \u0026ccu_nkmp_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+/*\n+ * Most clock-defining macros expect an *array* of parent clocks, even if\n+ * they do not contain a muxer to select between different parents.\n+ * The macros ending in just _HW take a simple clock pointer, but then create\n+ * a single-entry array out of that. The macros using _HWS take such an\n+ * array (even when it is a single entry one), this avoids having those\n+ * helper arrays created inside *every* clock definition.\n+ * This means for every clock that is referenced more than once it is\n+ * useful to create such a dummy array and use _HWS.\n+ */\n+static const struct clk_hw *pll_ref_hws[] = {\n+\t\u0026pll_ref_clk.common.hw\n+};\n+\n+/*\n+ * There is a non-software-configurable mux selecting between the DCXO and the\n+ * PLL_REF in hardware, whose output is fed to the sys-24M clock. Although both\n+ * sys-24M and pll-ref are fixed at 24 MHz, define a 1:1 fixed factor clock to\n+ * provide logical separation:\n+ * - pll-ref is dedicated to feeding other PLLs\n+ * - sys-24M serves as reference clock for downstream functional modules\n+ */\n+static CLK_FIXED_FACTOR_HWS(sys_24M_clk, \"sys-24M\", pll_ref_hws, 1, 1, 0);\n+static const struct clk_hw *sys_24M_hws[] = {\n+\t\u0026sys_24M_clk.hw\n+};\n+\n+#define SUN60I_A733_PLL_DDR_REG\t\t0x020\n+static struct ccu_nkmp pll_ddr_clk = {\n+\t.enable\t\t= BIT(27),\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(20, 3), /* output divider */\n+\t.p\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_DDR_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-ddr\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nkmp_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE |\n+\t\t\t\t\t\t\t CLK_IS_CRITICAL),\n+\t},\n+};\n+\n+/*\n+ * There is no actual clock output with that frequency (2.4 GHz), instead it\n+ * has multiple outputs with adjustable dividers from that base frequency.\n+ * Model them separately as divider clocks based on that parent here.\n+ */\n+#define SUN60I_A733_PLL_PERIPH0_REG\t0x0a0\n+static struct ccu_nm pll_periph0_4x_clk = {\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_PERIPH0_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-periph0-4x\",\n+\t\t\t\t\t\t\t pll_ref_hws, \u0026ccu_nm_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+static const struct clk_hw *pll_periph0_4x_hws[] = {\n+\t\u0026pll_periph0_4x_clk.common.hw\n+};\n+\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_2x_clk, \"pll-periph0-2x\",\n+\t\t\t\t pll_periph0_4x_hws,\n+\t\t\t\t SUN60I_A733_PLL_PERIPH0_REG,\n+\t\t\t\t 20, 3, BIT(27), 0);\n+static const struct clk_hw *pll_periph0_2x_hws[] = {\n+\t\u0026pll_periph0_2x_clk.common.hw\n+};\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_800M_clk, \"pll-periph0-800M\",\n+\t\t\t\t pll_periph0_4x_hws,\n+\t\t\t\t SUN60I_A733_PLL_PERIPH0_REG,\n+\t\t\t\t 16, 3, BIT(26), 0);\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_480M_clk, \"pll-periph0-480M\",\n+\t\t\t\t pll_periph0_4x_hws,\n+\t\t\t\t SUN60I_A733_PLL_PERIPH0_REG,\n+\t\t\t\t 2, 3, BIT(25), 0);\n+static const struct clk_hw *pll_periph0_480M_hws[] = {\n+\t\u0026pll_periph0_480M_clk.common.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, \"pll-periph0-600M\",\n+\t\t\t pll_periph0_2x_hws, 2, 1, 0);\n+static const struct clk_hw *pll_periph0_600M_hws[] = {\n+\t\u0026pll_periph0_600M_clk.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, \"pll-periph0-400M\",\n+\t\t\t pll_periph0_2x_hws, 3, 1, 0);\n+static const struct clk_hw *pll_periph0_400M_hws[] = {\n+\t\u0026pll_periph0_400M_clk.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, \"pll-periph0-300M\",\n+\t\t\t pll_periph0_600M_hws, 2, 1, 0);\n+static const struct clk_hw *pll_periph0_300M_hws[] = {\n+\t\u0026pll_periph0_300M_clk.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, \"pll-periph0-200M\",\n+\t\t\t pll_periph0_400M_hws, 2, 1, 0);\n+static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, \"pll-periph0-150M\",\n+\t\t\t pll_periph0_300M_hws, 2, 1, 0);\n+static const struct clk_hw *pll_periph0_150M_hws[] = {\n+\t\u0026pll_periph0_150M_clk.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, \"pll-periph0-160M\",\n+\t\t\t pll_periph0_480M_hws, 3, 1, 0);\n+\n+#define SUN60I_A733_PLL_PERIPH1_REG\t0x0c0\n+static struct ccu_nm pll_periph1_4x_clk = {\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_PERIPH1_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-periph1-4x\",\n+\t\t\t\t\t\t\t pll_ref_hws, \u0026ccu_nm_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+static const struct clk_hw *pll_periph1_4x_hws[] = {\n+\t\u0026pll_periph1_4x_clk.common.hw\n+};\n+\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_2x_clk, \"pll-periph1-2x\",\n+\t\t\t\t pll_periph1_4x_hws,\n+\t\t\t\t SUN60I_A733_PLL_PERIPH1_REG,\n+\t\t\t\t 20, 3, BIT(27), 0);\n+static const struct clk_hw *pll_periph1_2x_hws[] = {\n+\t\u0026pll_periph1_2x_clk.common.hw\n+};\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_800M_clk, \"pll-periph1-800M\",\n+\t\t\t\t pll_periph1_4x_hws,\n+\t\t\t\t SUN60I_A733_PLL_PERIPH1_REG,\n+\t\t\t\t 16, 3, BIT(26), 0);\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_480M_clk, \"pll-periph1-480M\",\n+\t\t\t\t pll_periph1_4x_hws,\n+\t\t\t\t SUN60I_A733_PLL_PERIPH1_REG,\n+\t\t\t\t 2, 3, BIT(25), 0);\n+static const struct clk_hw *pll_periph1_480M_hws[] = {\n+\t\u0026pll_periph1_480M_clk.common.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, \"pll-periph1-600M\",\n+\t\t\t pll_periph1_2x_hws, 2, 1, 0);\n+static const struct clk_hw *pll_periph1_600M_hws[] = {\n+\t\u0026pll_periph1_600M_clk.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, \"pll-periph1-400M\",\n+\t\t\t pll_periph1_2x_hws, 3, 1, 0);\n+static const struct clk_hw *pll_periph1_400M_hws[] = {\n+\t\u0026pll_periph1_400M_clk.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, \"pll-periph1-300M\",\n+\t\t\t pll_periph1_600M_hws, 2, 1, 0);\n+static const struct clk_hw *pll_periph1_300M_hws[] = {\n+\t\u0026pll_periph1_300M_clk.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, \"pll-periph1-200M\",\n+\t\t\t pll_periph1_400M_hws, 2, 1, 0);\n+static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, \"pll-periph1-150M\",\n+\t\t\t pll_periph1_300M_hws, 2, 1, 0);\n+static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, \"pll-periph1-160M\",\n+\t\t\t pll_periph1_480M_hws, 3, 1, 0);\n+\n+#define SUN60I_A733_PLL_GPU_REG\t\t0x0e0\n+static struct ccu_nkmp pll_gpu0_clk = {\n+\t.enable\t\t= BIT(27),\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(20, 3), /* output divider */\n+\t.p\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_GPU_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-gpu0\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nkmp_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+#define SUN60I_A733_PLL_VIDEO0_REG\t0x120\n+static struct ccu_nm pll_video0_clk = {\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_VIDEO0_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-video0\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nm_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+static const struct clk_hw *pll_video0_hws[] = {\n+\t\u0026pll_video0_clk.common.hw\n+};\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video0_4x_clk, \"pll-video0-4x\",\n+\t\t\t\t pll_video0_hws, SUN60I_A733_PLL_VIDEO0_REG,\n+\t\t\t\t 20, 3, BIT(27), CLK_SET_RATE_PARENT);\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video0_3x_clk, \"pll-video0-3x\",\n+\t\t\t\t pll_video0_hws, SUN60I_A733_PLL_VIDEO0_REG,\n+\t\t\t\t 16, 3, BIT(26), CLK_SET_RATE_PARENT);\n+\n+#define SUN60I_A733_PLL_VIDEO1_REG\t0x140\n+static struct ccu_nm pll_video1_clk = {\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_VIDEO1_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-video1\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nm_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+static const struct clk_hw *pll_video1_hws[] = {\n+\t\u0026pll_video1_clk.common.hw\n+};\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video1_4x_clk, \"pll-video1-4x\",\n+\t\t\t\t pll_video1_hws, SUN60I_A733_PLL_VIDEO1_REG,\n+\t\t\t\t 20, 3, BIT(27), CLK_SET_RATE_PARENT);\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video1_3x_clk, \"pll-video1-3x\",\n+\t\t\t\t pll_video1_hws, SUN60I_A733_PLL_VIDEO1_REG,\n+\t\t\t\t 16, 3, BIT(26), CLK_SET_RATE_PARENT);\n+\n+#define SUN60I_A733_PLL_VIDEO2_REG\t0x160\n+static struct ccu_nm pll_video2_clk = {\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_VIDEO2_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-video2\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nm_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+static const struct clk_hw *pll_video2_hws[] = {\n+\t\u0026pll_video2_clk.common.hw\n+};\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video2_4x_clk, \"pll-video2-4x\",\n+\t\t\t\t pll_video2_hws, SUN60I_A733_PLL_VIDEO2_REG,\n+\t\t\t\t 20, 3, BIT(27), CLK_SET_RATE_PARENT);\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video2_3x_clk, \"pll-video2-3x\",\n+\t\t\t\t pll_video2_hws, SUN60I_A733_PLL_VIDEO2_REG,\n+\t\t\t\t 16, 3, BIT(26), CLK_SET_RATE_PARENT);\n+\n+#define SUN60I_A733_PLL_VE0_REG\t\t0x220\n+static struct ccu_nkmp pll_ve0_clk = {\n+\t.enable\t\t= BIT(27),\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(20, 3), /* output divider */\n+\t.p\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_VE0_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-ve0\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nkmp_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+#define SUN60I_A733_PLL_VE1_REG\t\t0x240\n+static struct ccu_nkmp pll_ve1_clk = {\n+\t.enable\t\t= BIT(27),\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(20, 3), /* output divider */\n+\t.p\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_VE1_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-ve1\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nkmp_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+/*\n+ * PLL_AUDIO0 has a m1 divider in addition to the usual N, M factors.\n+ * Since we only need some fixed frequency from this PLL (22.5792MHz x 4),\n+ * ignore the divider and force it to 1 (encoded as 0), in the probe function\n+ * below.\n+ * The M factor must be an even number to produce a 50% duty cycle output.\n+ */\n+#define SUN60I_A733_PLL_AUDIO0_REG\t0x260\n+static struct ccu_sdm_setting pll_audio0_sdm_table[] = {\n+\t{ .rate = 90316800, .pattern = 0xa002872b, .m = 20, .n = 75 }, /* 22.5792 * 4 */\n+};\n+\n+static struct ccu_nm pll_audio0_4x_clk = {\n+\t.enable\t\t= BIT(27),\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(16, 7),\n+\t.sdm\t\t= _SUNXI_CCU_SDM_DUAL_PAT(pll_audio0_sdm_table, 0,\n+\t\t\t\t\t\t 0x268, BIT(31),\n+\t\t\t\t\t\t 0x26c, BIT(27) | BIT(31)),\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_AUDIO0_REG,\n+\t\t.features\t= CCU_FEATURE_SIGMA_DELTA_MOD,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-audio0-4x\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nm_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+#define SUN60I_A733_PLL_AUDIO1_REG\t0x280\n+static struct ccu_nm pll_audio1_clk = {\n+\t.enable\t\t= BIT(27),\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(1, 1),\t/* input divider */\n+\t.sdm\t\t= {\n+\t\t/* PLL_AUDIO1 does not use fractional rates. */\n+\t\t.pat0_enable\t= BIT(31),\n+\t\t.pat0_reg\t= 0x288,\n+\t\t.pat1_enable\t= BIT(27) | BIT(31),\n+\t\t.pat1_reg\t= 0x28c,\n+\t},\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_AUDIO1_REG,\n+\t\t.features\t= CCU_FEATURE_SIGMA_DELTA_MOD,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-audio1\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nm_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+static const struct clk_hw *pll_audio1_hws[] = {\n+\t\u0026pll_audio1_clk.common.hw\n+};\n+static CLK_FIXED_FACTOR_HWS(pll_audio1_div2_clk, \"pll-audio1-div2\",\n+\t\t\t pll_audio1_hws, 2, 1, CLK_SET_RATE_PARENT);\n+static CLK_FIXED_FACTOR_HWS(pll_audio1_div5_clk, \"pll-audio1-div5\",\n+\t\t\t pll_audio1_hws, 5, 1, CLK_SET_RATE_PARENT);\n+\n+#define SUN60I_A733_PLL_NPU_REG\t\t0x2a0\n+static struct ccu_nkmp pll_npu_clk = {\n+\t.enable\t\t= BIT(27),\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(20, 3), /* output divider */\n+\t.p\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_NPU_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-npu\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nkmp_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+#define SUN60I_A733_PLL_DE_REG\t\t0x2e0\n+static struct ccu_nm pll_de_clk = {\n+\t.lock\t\t= BIT(28),\n+\t.n\t\t= _SUNXI_CCU_MULT_MIN(8, 8, 11),\n+\t.m\t\t= _SUNXI_CCU_DIV(1, 1), /* input divider */\n+\t.common\t\t= {\n+\t\t.reg\t\t= SUN60I_A733_PLL_DE_REG,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_HW(\"pll-de\", pll_ref_hws,\n+\t\t\t\t\t\t\t \u0026ccu_nm_ops,\n+\t\t\t\t\t\t\t CLK_SET_RATE_GATE),\n+\t},\n+};\n+\n+static const struct clk_hw *pll_de_hws[] = {\n+\t\u0026pll_de_clk.common.hw\n+};\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_de_4x_clk, \"pll-de-4x\", pll_de_hws,\n+\t\t\t\t SUN60I_A733_PLL_DE_REG,\n+\t\t\t\t 20, 3, BIT(27), CLK_SET_RATE_PARENT);\n+static SUNXI_CCU_M_HWS_WITH_GATE(pll_de_3x_clk, \"pll-de-3x\", pll_de_hws,\n+\t\t\t\t SUN60I_A733_PLL_DE_REG,\n+\t\t\t\t 16, 3, BIT(26), CLK_SET_RATE_PARENT);\n+\n+/**************************************************************************\n+ * bus clocks *\n+ **************************************************************************/\n+\n+static const struct clk_parent_data ahb_apb_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+\t{ .hw = \u0026pll_periph0_600M_clk.hw },\n+};\n+\n+static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, \"ahb\", ahb_apb_parents, 0x500,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 24, 2,\t\t/* mux */\n+\t\t\t\t 0);\n+static const struct clk_hw *ahb_hws[] = { \u0026ahb_clk.common.hw };\n+\n+static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, \"apb0\", ahb_apb_parents, 0x510,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 24, 2,\t\t/* mux */\n+\t\t\t\t 0);\n+static const struct clk_hw *apb0_hws[] = { \u0026apb0_clk.common.hw };\n+\n+static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, \"apb1\", ahb_apb_parents, 0x518,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 24, 2,\t\t/* mux */\n+\t\t\t\t 0);\n+static const struct clk_hw *apb1_hws[] = { \u0026apb1_clk.common.hw };\n+\n+static const struct clk_parent_data apb_uart_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+\t{ .hw = \u0026pll_periph0_600M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_480M_clk.common.hw },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, \"apb-uart\", apb_uart_parents, 0x538,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t 0);\n+static const struct clk_hw *apb_uart_hws[] = {\n+\t\u0026apb_uart_clk.common.hw\n+};\n+\n+static const struct clk_parent_data trace_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+\t{ .hw = \u0026pll_periph0_300M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_400M_clk.hw },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, \"trace\", trace_parents, 0x540,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data gic_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"losc\" },\n+\t{ .hw = \u0026pll_periph0_600M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_480M_clk.common.hw },\n+\t{ .hw = \u0026pll_periph0_400M_clk.hw },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gic_clk, \"gic\", gic_parents, 0x560,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t CLK_IS_CRITICAL);\n+\n+static SUNXI_CCU_GATE_DATA(bus_its_pcie0_aclk_clk, \"bus-its-pcie0-aclk\", hosc, 0x574, BIT(1), 0);\n+\n+static const struct clk_parent_data mbus_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_periph1_600M_clk.hw },\n+\t{ .hw = \u0026pll_ddr_clk.common.hw },\n+\t{ .hw = \u0026pll_periph1_480M_clk.common.hw },\n+\t{ .hw = \u0026pll_periph1_400M_clk.hw },\n+\t{ .hw = \u0026pll_npu_clk.common.hw },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, \"mbus\", mbus_parents, 0x588,\n+\t\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t\t CLK_IS_CRITICAL,\n+\t\t\t\t\t CCU_FEATURE_UPDATE_BIT);\n+static const struct clk_hw *mbus_hws[] = { \u0026mbus_clk.common.hw };\n+\n+static SUNXI_CCU_GATE_HWS(mbus_iommu0_sys_clk, \"mbus-iommu0-sys\", mbus_hws, 0x58c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(apb_iommu0_sys_clk, \"apb-iommu0-sys\", apb0_hws, 0x58c, BIT(1), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_iommu0_sys_clk, \"ahb-iommu0-sys\", ahb_hws, 0x58c, BIT(2), 0);\n+\n+static SUNXI_CCU_GATE_DATA(bus_msi_lite0_clk, \"bus-msi-lite0\", hosc, 0x594, BIT(0), 0);\n+static SUNXI_CCU_GATE_DATA(bus_msi_lite1_clk, \"bus-msi-lite1\", hosc, 0x59c, BIT(0), 0);\n+static SUNXI_CCU_GATE_DATA(bus_msi_lite2_clk, \"bus-msi-lite2\", hosc, 0x5a4, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(mbus_iommu1_sys_clk, \"mbus-iommu1-sys\", mbus_hws, 0x5b4, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(apb_iommu1_sys_clk, \"apb-iommu1-sys\", apb0_hws, 0x5b4, BIT(1), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_iommu1_sys_clk, \"ahb-iommu1-sys\", ahb_hws, 0x5b4, BIT(2), 0);\n+\n+static SUNXI_CCU_GATE_HWS(ahb_ve_dec_clk, \"ahb-ve-dec\", ahb_hws,\n+\t\t\t 0x5c0, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_ve_enc_clk, \"ahb-ve-enc\", ahb_hws,\n+\t\t\t 0x5c0, BIT(1), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_vid_in_clk, \"ahb-vid-in\", ahb_hws,\n+\t\t\t 0x5c0, BIT(2), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_vid_cout0_clk, \"ahb-vid-cout0\", ahb_hws,\n+\t\t\t 0x5c0, BIT(3), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_vid_cout1_clk, \"ahb-vid-cout1\", ahb_hws,\n+\t\t\t 0x5c0, BIT(4), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_de_clk, \"ahb-de\", ahb_hws,\n+\t\t\t 0x5c0, BIT(5), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_npu_clk, \"ahb-npu\", ahb_hws,\n+\t\t\t 0x5c0, BIT(6), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_gpu0_clk, \"ahb-gpu0\", ahb_hws,\n+\t\t\t 0x5c0, BIT(7), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_serdes_clk, \"ahb-serdes\", ahb_hws,\n+\t\t\t 0x5c0, BIT(8), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_usb_sys_clk, \"ahb-usb-sys\", ahb_hws,\n+\t\t\t 0x5c0, BIT(9), 0);\n+static SUNXI_CCU_GATE_HWS(ahb_msi_lite0_clk, \"ahb-msi-lite0\", ahb_hws,\n+\t\t\t 0x5c0, BIT(16), 0);\n+\n+/* This gate controls access to the storage controller MMIO registers. */\n+static SUNXI_CCU_GATE_HWS(ahb_store_clk, \"ahb-store\", ahb_hws,\n+\t\t\t 0x5c0, BIT(24), 0);\n+static const struct clk_hw *ahb_store_hws[] = { \u0026ahb_store_clk.common.hw };\n+\n+/* Keep enabled for access to the CPUS domain registers. */\n+static SUNXI_CCU_GATE_HWS(ahb_cpus_clk, \"ahb-cpus\", ahb_hws,\n+\t\t\t 0x5c0, BIT(28), CLK_IS_CRITICAL);\n+\n+static SUNXI_CCU_GATE_HWS(mbus_iommu0_clk, \"mbus-iommu0\", mbus_hws,\n+\t\t\t 0x5e0, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_iommu1_clk, \"mbus-iommu1\", mbus_hws,\n+\t\t\t 0x5e0, BIT(1), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_desys_clk, \"mbus-desys\", mbus_hws,\n+\t\t\t 0x5e0, BIT(11), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_ve_enc0_gate_clk, \"mbus-ve-enc0-gate\", mbus_hws,\n+\t\t\t 0x5e0, BIT(12), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_ve_dec0_gate_clk, \"mbus-ve-dec0-gate\", mbus_hws,\n+\t\t\t 0x5e0, BIT(14), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_gpu0_clk, \"mbus-gpu0\", mbus_hws,\n+\t\t\t 0x5e0, BIT(16), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_npu_clk, \"mbus-npu\", mbus_hws,\n+\t\t\t 0x5e0, BIT(18), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_vid_in_clk, \"mbus-vid-in\", mbus_hws,\n+\t\t\t 0x5e0, BIT(24), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_serdes_clk, \"mbus-serdes\", mbus_hws,\n+\t\t\t 0x5e0, BIT(28), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_msi_lite0_clk, \"mbus-msi-lite0\", mbus_hws,\n+\t\t\t 0x5e0, BIT(29), 0);\n+\n+/* Keep enabled for the storage controller DMA paths. */\n+static SUNXI_CCU_GATE_HWS(mbus_store_clk, \"mbus-store\", mbus_hws,\n+\t\t\t 0x5e0, BIT(30), CLK_IS_CRITICAL);\n+static const struct clk_hw *mbus_store_hws[] = { \u0026mbus_store_clk.common.hw };\n+\n+static SUNXI_CCU_GATE_HWS(mbus_msi_lite2_clk, \"mbus-msi-lite2\", mbus_hws,\n+\t\t\t 0x5e0, BIT(31), 0);\n+\n+static SUNXI_CCU_GATE_HWS(mbus_dma0_clk, \"mbus-dma0\", mbus_hws,\n+\t\t\t 0x5e4, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_ve_enc0_clk, \"mbus-ve-enc0\", mbus_hws,\n+\t\t\t 0x5e4, BIT(1), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_ce_clk, \"mbus-ce\", mbus_hws,\n+\t\t\t 0x5e4, BIT(2), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_dma1_clk, \"mbus-dma1\", mbus_hws,\n+\t\t\t 0x5e4, BIT(3), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_nand0_clk, \"mbus-nand0\", mbus_store_hws,\n+\t\t\t 0x5e4, BIT(5), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_csi_clk, \"mbus-csi\", mbus_hws,\n+\t\t\t 0x5e4, BIT(8), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_isp_clk, \"mbus-isp\", mbus_hws,\n+\t\t\t 0x5e4, BIT(9), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_gmac0_clk, \"mbus-gmac0\", mbus_hws,\n+\t\t\t 0x5e4, BIT(11), 0);\n+/* Undocumented, taken from the vendor kernel. */\n+static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, \"mbus-gmac1\", mbus_hws,\n+\t\t\t 0x5e4, BIT(12), 0);\n+static SUNXI_CCU_GATE_HWS(mbus_ve_dec0_clk, \"mbus-ve-dec0\", mbus_hws,\n+\t\t\t 0x5e4, BIT(18), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_dma0_clk, \"bus-dma0\", ahb_hws,\n+\t\t\t 0x704, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_dma1_clk, \"bus-dma1\", ahb_hws,\n+\t\t\t 0x70c, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, \"bus-spinlock\", ahb_hws,\n+\t\t\t 0x724, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, \"bus-msgbox0\", ahb_hws,\n+\t\t\t 0x744, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, \"bus-pwm0\", apb0_hws,\n+\t\t\t 0x784, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, \"bus-pwm1\", apb0_hws,\n+\t\t\t 0x78c, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_dbg_clk, \"bus-dbg\", sys_24M_hws,\n+\t\t\t 0x7a4, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, \"bus-sysdap\", apb1_hws,\n+\t\t\t 0x7ac, BIT(0), 0);\n+\n+/**************************************************************************\n+ * mod clocks with gates *\n+ **************************************************************************/\n+\n+static const struct clk_parent_data timer_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"iosc\" },\n+\t{ .fw_name = \"losc\" },\n+\t{ .hw = \u0026pll_periph0_200M_clk.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer0_clk, \"timer0\", timer_parents, 0x800,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer1_clk, \"timer1\", timer_parents, 0x804,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer2_clk, \"timer2\", timer_parents, 0x808,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer3_clk, \"timer3\", timer_parents, 0x80c,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer4_clk, \"timer4\", timer_parents, 0x810,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer5_clk, \"timer5\", timer_parents, 0x814,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer6_clk, \"timer6\", timer_parents, 0x818,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer7_clk, \"timer7\", timer_parents, 0x81c,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer8_clk, \"timer8\", timer_parents, 0x820,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer9_clk, \"timer9\", timer_parents, 0x824,\n+\t\t\t\t 0, 3,\t\t/* P */\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_timer_clk, \"bus-timer\", ahb_hws, 0x850, BIT(0), 0);\n+\n+/* Undocumented, taken from the vendor kernel. */\n+static const struct clk_parent_data avs_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(avs_clk, \"avs-clk\", avs_parents, 0x880,\n+\t\t\t\t 24, 3,\t\t/* mux */\n+\t\t\t\t BIT(31),\t\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_hw *de_parents[] = {\n+\t\u0026pll_de_3x_clk.common.hw,\n+\t\u0026pll_de_4x_clk.common.hw,\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_periph0_400M_clk.hw,\n+\t\u0026pll_periph0_300M_clk.hw,\n+\t\u0026pll_video0_4x_clk.common.hw,\n+\t\u0026pll_video2_4x_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(de0_clk, \"de0\", de_parents, 0xa00,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t CLK_SET_RATE_PARENT);\n+static SUNXI_CCU_GATE_HWS(bus_de0_clk, \"bus-de0\", ahb_hws, 0xa04, BIT(0), 0);\n+\n+static const struct clk_hw *di_parents[] = {\n+\t\u0026pll_periph0_600M_clk.hw,\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_periph0_400M_clk.hw,\n+\t\u0026pll_video0_4x_clk.common.hw,\n+\t\u0026pll_video2_4x_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, \"di\", di_parents, 0xa20,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t CLK_SET_RATE_PARENT);\n+static SUNXI_CCU_GATE_HWS(bus_di_clk, \"bus-di\", ahb_hws, 0xa24, BIT(0), 0);\n+\n+static const struct clk_hw *g2d_parents[] = {\n+\t\u0026pll_periph0_400M_clk.hw,\n+\t\u0026pll_periph0_300M_clk.hw,\n+\t\u0026pll_video0_4x_clk.common.hw,\n+\t\u0026pll_video1_4x_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, \"g2d\", g2d_parents, 0xa40,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t CLK_SET_RATE_PARENT);\n+static SUNXI_CCU_GATE_HWS(bus_g2d_clk, \"bus-g2d\", ahb_hws, 0xa44, BIT(0), 0);\n+\n+static const struct clk_hw *eink_parents[] = {\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_periph0_400M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_clk, \"eink\", eink_parents, 0xa60,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t CLK_SET_RATE_PARENT);\n+\n+static const struct clk_hw *eink_panel_parents[] = {\n+\t\u0026pll_video0_4x_clk.common.hw,\n+\t\u0026pll_video0_3x_clk.common.hw,\n+\t\u0026pll_video1_4x_clk.common.hw,\n+\t\u0026pll_video1_3x_clk.common.hw,\n+\t\u0026pll_periph0_300M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, \"eink-panel\", eink_panel_parents, 0xa64,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t CLK_SET_RATE_PARENT);\n+static SUNXI_CCU_GATE_HWS(bus_eink_clk, \"bus-eink\", ahb_hws, 0xa6c, BIT(0), 0);\n+\n+static const struct clk_hw *ve_enc_parents[] = {\n+\t\u0026pll_ve0_clk.common.hw,\n+\t\u0026pll_ve1_clk.common.hw,\n+\t\u0026pll_periph0_800M_clk.common.hw,\n+\t\u0026pll_periph0_600M_clk.hw,\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_de_3x_clk.common.hw,\n+\t\u0026pll_npu_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_enc0_clk, \"ve-enc0\", ve_enc_parents, 0xa80,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t CLK_SET_RATE_PARENT);\n+\n+static const struct clk_hw *ve_dec_parents[] = {\n+\t\u0026pll_ve1_clk.common.hw,\n+\t\u0026pll_ve0_clk.common.hw,\n+\t\u0026pll_periph0_800M_clk.common.hw,\n+\t\u0026pll_periph0_600M_clk.hw,\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_de_3x_clk.common.hw,\n+\t\u0026pll_npu_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec0_clk, \"ve-dec0\", ve_dec_parents, 0xa88,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t CLK_SET_RATE_PARENT);\n+\n+static SUNXI_CCU_GATE_HWS(bus_ve_enc0_clk, \"bus-ve-enc0\", ahb_hws, 0xa8c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_ve_dec0_clk, \"bus-ve-dec0\", ahb_hws, 0xa8c, BIT(2), 0);\n+\n+static const struct clk_hw *ce_parents[] = {\n+\t\u0026sys_24M_clk.hw,\n+\t\u0026pll_periph0_400M_clk.hw,\n+\t\u0026pll_periph0_600M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, \"ce\", ce_parents, 0xac0,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_ce_clk, \"bus-ce\", ahb_hws, 0xac4, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, \"bus-ce-sys\", ahb_hws, 0xac4, BIT(1), 0);\n+\n+static const struct clk_hw *npu_parents[] = {\n+\t\u0026pll_npu_clk.common.hw,\n+\t\u0026pll_periph0_800M_clk.common.hw,\n+\t\u0026pll_periph0_600M_clk.hw,\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_ve0_clk.common.hw,\n+\t\u0026pll_ve1_clk.common.hw,\n+\t\u0026pll_de_3x_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, \"npu\", npu_parents, 0xb00,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_DATA(bus_npu_clk, \"bus-npu\", hosc, 0xb04, BIT(0), 0);\n+\n+/*\n+ * GPU_CLK = ClockSource * ((16 - M) / 16)\n+ * Here we use a div_table to select M values that result in integer divisors.\n+ */\n+static struct clk_div_table gpu_div_table[] = {\n+\t{ .val = 0, .div = 1 },\n+\t{ .val = 8, .div = 2 },\n+\t{ .val = 12, .div = 4 },\n+\t{ .val = 14, .div = 8 },\n+\t{ .val = 15, .div = 16 },\n+\t{ /* sentinel */ },\n+};\n+static const struct clk_parent_data gpu_parents[] = {\n+\t{ .hw = \u0026pll_gpu0_clk.common.hw, },\n+\t{ .hw = \u0026pll_periph0_800M_clk.common.hw, },\n+\t{ .hw = \u0026pll_periph0_600M_clk.hw, },\n+\t{ .hw = \u0026pll_periph0_400M_clk.hw, },\n+\t{ .hw = \u0026pll_periph0_300M_clk.hw, },\n+\t{ .hw = \u0026pll_periph0_200M_clk.hw, },\n+};\n+static struct ccu_div gpu0_clk = {\n+\t.enable\t\t= BIT(31),\n+\t.div\t\t= _SUNXI_CCU_DIV_TABLE(0, 4, gpu_div_table),\n+\t.mux\t\t= _SUNXI_CCU_MUX(24, 3),\n+\t.common\t\t= {\n+\t\t.reg\t\t= 0xb20,\n+\t\t.features\t= CCU_FEATURE_UPDATE_BIT,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_DATA(\"gpu0\", gpu_parents,\n+\t\t\t\t\t\t\t \u0026ccu_div_ops, 0),\n+\t}\n+};\n+static SUNXI_CCU_GATE_HWS(bus_gpu0_clk, \"bus-gpu0\", ahb_hws, 0xb24, BIT(0), 0);\n+\n+static const struct clk_parent_data dram_parents[] = {\n+\t{ .hw = \u0026pll_ddr_clk.common.hw, },\n+\t{ .hw = \u0026pll_periph0_800M_clk.common.hw, },\n+\t{ .hw = \u0026pll_periph0_600M_clk.hw, },\n+\t{ .hw = \u0026pll_de_clk.common.hw, },\n+\t{ .hw = \u0026pll_npu_clk.common.hw, },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram0_clk, \"dram0\", dram_parents, 0xc00,\n+\t\t\t\t\t 0, 4,\t/* M */\n+\t\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t\t CLK_IS_CRITICAL,\n+\t\t\t\t\t CCU_FEATURE_UPDATE_BIT);\n+static SUNXI_CCU_GATE_HWS(bus_dram0_clk, \"bus-dram0\", ahb_hws, 0xc0c,\n+\t\t\t BIT(0), CLK_IS_CRITICAL);\n+\n+static const struct clk_parent_data nand_mmc_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw, },\n+\t{ .hw = \u0026pll_periph0_400M_clk.hw, },\n+\t{ .hw = \u0026pll_periph0_300M_clk.hw, },\n+\t{ .hw = \u0026pll_periph1_400M_clk.hw, },\n+\t{ .hw = \u0026pll_periph1_300M_clk.hw, },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk0_clk, \"nand0-clk0\", nand_mmc_parents, 0xc80,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk1_clk, \"nand0-clk1\", nand_mmc_parents, 0xc84,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_nand0_clk, \"bus-nand0\", ahb_store_hws, 0xc8c, BIT(0), 0);\n+\n+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, \"mmc0\", nand_mmc_parents, 0xd00,\n+\t\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t\t 8, 5,\t/* P */\n+\t\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t\t 2,\t\t/* post div */\n+\t\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, \"bus-mmc0\", ahb_store_hws, 0xd0c, BIT(0), 0);\n+\n+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, \"mmc1\", nand_mmc_parents, 0xd10,\n+\t\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t\t 8, 5,\t/* P */\n+\t\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t\t 2,\t\t/* post div */\n+\t\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, \"bus-mmc1\", ahb_store_hws, 0xd1c, BIT(0), 0);\n+\n+static const struct clk_parent_data mmc2_mmc3_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw, },\n+\t{ .hw = \u0026pll_periph0_800M_clk.common.hw },\n+\t{ .hw = \u0026pll_periph0_600M_clk.hw },\n+\t{ .hw = \u0026pll_periph1_800M_clk.common.hw },\n+\t{ .hw = \u0026pll_periph1_600M_clk.hw },\n+};\n+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, \"mmc2\", mmc2_mmc3_parents, 0xd20,\n+\t\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t\t 8, 5,\t/* P */\n+\t\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t\t 2,\t\t/* post div */\n+\t\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, \"bus-mmc2\", ahb_store_hws, 0xd2c, BIT(0), 0);\n+\n+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, \"mmc3\", mmc2_mmc3_parents, 0xd30,\n+\t\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t\t 8, 5,\t/* P */\n+\t\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t\t 2,\t\t/* post div */\n+\t\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_mmc3_clk, \"bus-mmc3\", ahb_store_hws, 0xd3c, BIT(0), 0);\n+\n+static const struct clk_hw *ufs_axi_parents[] = {\n+\t\u0026pll_periph0_300M_clk.hw,\n+\t\u0026pll_periph0_200M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ufs_axi_clk, \"ufs-axi\", ufs_axi_parents, 0xd80,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data ufs_cfg_parents[] = {\n+\t{ .hw = \u0026pll_periph0_480M_clk.common.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, \"ufs-cfg\", ufs_cfg_parents, 0xd84,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_ufs_clk, \"bus-ufs\", ahb_store_hws, 0xd8c, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_uart0_clk, \"bus-uart0\", apb_uart_hws, 0xe00, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_uart1_clk, \"bus-uart1\", apb_uart_hws, 0xe04, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_uart2_clk, \"bus-uart2\", apb_uart_hws, 0xe08, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_uart3_clk, \"bus-uart3\", apb_uart_hws, 0xe0c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_uart4_clk, \"bus-uart4\", apb_uart_hws, 0xe10, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_uart5_clk, \"bus-uart5\", apb_uart_hws, 0xe14, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_uart6_clk, \"bus-uart6\", apb_uart_hws, 0xe18, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, \"bus-i2c0\", apb1_hws, 0xe80, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, \"bus-i2c1\", apb1_hws, 0xe84, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, \"bus-i2c2\", apb1_hws, 0xe88, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, \"bus-i2c3\", apb1_hws, 0xe8c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, \"bus-i2c4\", apb1_hws, 0xe90, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, \"bus-i2c5\", apb1_hws, 0xe94, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c6_clk, \"bus-i2c6\", apb1_hws, 0xe98, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c7_clk, \"bus-i2c7\", apb1_hws, 0xe9c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c8_clk, \"bus-i2c8\", apb1_hws, 0xea0, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c9_clk, \"bus-i2c9\", apb1_hws, 0xea4, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c10_clk, \"bus-i2c10\", apb1_hws, 0xea8, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c11_clk, \"bus-i2c11\", apb1_hws, 0xeac, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_i2c12_clk, \"bus-i2c12\", apb1_hws, 0xeb0, BIT(0), 0);\n+\n+static const struct clk_parent_data spi_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_300M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_200M_clk.hw },\n+\t{ .hw = \u0026pll_periph1_300M_clk.hw },\n+\t{ .hw = \u0026pll_periph1_200M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_480M_clk.common.hw },\n+\t{ .hw = \u0026pll_periph1_480M_clk.common.hw },\n+\t{ .fw_name = \"hosc\"},\n+};\n+static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, \"spi0\", spi_parents, 0xf00,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_spi0_clk, \"bus-spi0\", ahb_store_hws, 0xf04, BIT(0), 0);\n+\n+static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, \"spi1\", spi_parents, 0xf08,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_spi1_clk, \"bus-spi1\", ahb_store_hws, 0xf0c, BIT(0), 0);\n+\n+static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, \"spi2\", spi_parents, 0xf10,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_spi2_clk, \"bus-spi2\", ahb_store_hws, 0xf14, BIT(0), 0);\n+\n+static const struct clk_parent_data spif_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_400M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_300M_clk.hw },\n+\t{ .hw = \u0026pll_periph1_400M_clk.hw },\n+\t{ .hw = \u0026pll_periph1_300M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_160M_clk.hw },\n+\t{ .hw = \u0026pll_periph1_160M_clk.hw },\n+\t{ .fw_name = \"hosc\"},\n+};\n+static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, \"spif\", spif_parents, 0xf18,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* P */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_spif_clk, \"bus-spif\", ahb_store_hws, 0xf1c, BIT(0), 0);\n+\n+static SUNXI_CCU_DUALDIV_MUX_GATE(spi3_clk, \"spi3\", spi_parents, 0xf20,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_spi3_clk, \"bus-spi3\", ahb_store_hws, 0xf24, BIT(0), 0);\n+\n+/* Undocumented, taken from the vendor kernel. */\n+static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, \"spi4\", spi_parents, 0xf28,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_spi4_clk, \"bus-spi4\", ahb_store_hws, 0xf2c, BIT(0), 0);\n+\n+static const struct clk_parent_data gpadc0_24m_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"hosc\"},\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc0_24m_clk, \"gpadc0-24m\", gpadc0_24m_parents, 0xfc0,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_gpadc0_clk, \"bus-gpadc0\", ahb_hws, 0xfc4, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_ths0_clk, \"bus-ths0\", apb0_hws, 0xfe4, BIT(0), 0);\n+\n+static const struct clk_parent_data irrx_parents[] = {\n+\t{ .fw_name = \"losc\"},\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"hosc\"},\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, \"irrx\", irrx_parents, 0x1000,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_irrx_clk, \"bus-irrx\", apb0_hws, 0x1004, BIT(0), 0);\n+\n+static const struct clk_parent_data irtx_parents[] = {\n+\t{ .fw_name = \"losc\"},\n+\t{ .hw = \u0026pll_periph1_600M_clk.hw },\n+\t{ .fw_name = \"hosc\"},\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, \"irtx\", irtx_parents, 0x1008,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_irtx_clk, \"bus-irtx\", apb0_hws, 0x100c, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_lradc_clk, \"bus-lradc\", apb0_hws, 0x1024, BIT(0), 0);\n+\n+/* Undocumented, taken from the vendor kernel. */\n+static const struct clk_parent_data sgpio_parents[] = {\n+\t{ .fw_name = \"losc\"},\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, \"sgpio\", sgpio_parents, 0x1060,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_DATA(bus_sgpio_clk, \"bus-sgpio\", hosc, 0x1064, BIT(0), 0);\n+\n+/* Undocumented, taken from the vendor kernel. */\n+static const struct clk_hw *lpc_parents[] = {\n+\t\u0026pll_video0_3x_clk.common.hw,\n+\t\u0026pll_video1_3x_clk.common.hw,\n+\t\u0026pll_video2_3x_clk.common.hw,\n+\t\u0026pll_periph0_300M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, \"lpc\", lpc_parents, 0x1080,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_DATA(bus_lpc_clk, \"bus-lpc\", hosc, 0x1084, BIT(0), 0);\n+\n+static const struct clk_hw *i2spcm_parents[] = {\n+\t\u0026pll_audio0_4x_clk.common.hw,\n+\t\u0026pll_audio1_div2_clk.hw,\n+\t\u0026pll_audio1_div5_clk.hw,\n+\t\u0026pll_periph0_200M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm0_clk, \"i2spcm0\", i2spcm_parents, 0x1200,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_DATA(bus_i2spcm0_clk, \"bus-i2spcm0\", hosc, 0x120c, BIT(0), 0);\n+\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm1_clk, \"i2spcm1\", i2spcm_parents, 0x1210,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_DATA(bus_i2spcm1_clk, \"bus-i2spcm1\", hosc, 0x121c, BIT(0), 0);\n+\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_clk, \"i2spcm2\", i2spcm_parents, 0x1220,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_hw *i2spcm2_asrc_parents[] = {\n+\t\u0026pll_audio0_4x_clk.common.hw,\n+\t\u0026pll_audio1_div2_clk.hw,\n+\t\u0026pll_audio1_div5_clk.hw,\n+\t\u0026pll_periph0_300M_clk.hw,\n+\t\u0026pll_periph1_300M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_asrc_clk, \"i2spcm2_asrc\", i2spcm2_asrc_parents, 0x1224,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_GATE_DATA(bus_i2spcm2_clk, \"bus-i2spcm2\", hosc, 0x122c, BIT(0), 0);\n+\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm3_clk, \"i2spcm3\", i2spcm_parents, 0x1230,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_DATA(bus_i2spcm3_clk, \"bus-i2spcm3\", hosc, 0x123c, BIT(0), 0);\n+\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, \"i2spcm4\", i2spcm_parents, 0x1240,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_DATA(bus_i2spcm4_clk, \"bus-i2spcm4\", hosc, 0x124c, BIT(0), 0);\n+\n+static const struct clk_hw *spdif_tx_parents[] = {\n+\t\u0026pll_audio0_4x_clk.common.hw,\n+\t\u0026pll_audio1_div2_clk.hw,\n+\t\u0026pll_audio1_div5_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_tx_clk, \"spdif-tx\", spdif_tx_parents, 0x1280,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_hw *spdif_rx_parents[] = {\n+\t\u0026pll_periph0_200M_clk.hw,\n+\t\u0026pll_periph0_300M_clk.hw,\n+\t\u0026pll_periph0_400M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_rx_clk, \"spdif-rx\", spdif_rx_parents, 0x1284,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_spdif_clk, \"bus-spdif\", apb1_hws, 0x128c, BIT(0), 0);\n+\n+static const struct clk_hw *dmic_parents[] = {\n+\t\u0026pll_audio0_4x_clk.common.hw,\n+\t\u0026pll_audio1_div2_clk.hw,\n+\t\u0026pll_audio1_div5_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, \"dmic\", dmic_parents, 0x12c0,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_dmic_clk, \"bus-dmic\", apb1_hws, 0x12cc, BIT(0), 0);\n+\n+/*\n+ * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is\n+ * a 2x multiplier from pll-ref synchronized by pll-periph0, and is also used by\n+ * the OHCI module.\n+ */\n+static const struct clk_parent_data usb_ohci_parents[] = {\n+\t{ .hw = \u0026pll_periph0_4x_clk.common.hw },\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+};\n+static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = {\n+\t{ .index = 0, .div = 200 },\n+\t{ .index = 1, .div = 2 },\n+};\n+\n+static struct ccu_mux usb_ohci0_clk = {\n+\t.enable\t\t= BIT(31),\n+\t.mux\t\t= {\n+\t\t.shift\t\t= 24,\n+\t\t.width\t\t= 2,\n+\t\t.fixed_predivs\t= usb_ohci_predivs,\n+\t\t.n_predivs\t= ARRAY_SIZE(usb_ohci_predivs),\n+\t},\n+\t.common\t\t= {\n+\t\t.reg\t\t= 0x1300,\n+\t\t.features\t= CCU_FEATURE_FIXED_PREDIV,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_DATA(\"usb-ohci0\", usb_ohci_parents,\n+\t\t\t\t\t\t\t \u0026ccu_mux_ops, 0),\n+\t},\n+};\n+static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, \"bus-ohci0\", ahb_hws, 0x1304, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, \"bus-ehci0\", ahb_hws, 0x1304, BIT(4), 0);\n+static SUNXI_CCU_GATE_HWS(bus_otg_clk, \"bus-otg\", ahb_hws, 0x1304, BIT(8), 0);\n+\n+static struct ccu_mux usb_ohci1_clk = {\n+\t.enable\t\t= BIT(31),\n+\t.mux\t\t= {\n+\t\t.shift\t\t= 24,\n+\t\t.width\t\t= 2,\n+\t\t.fixed_predivs\t= usb_ohci_predivs,\n+\t\t.n_predivs\t= ARRAY_SIZE(usb_ohci_predivs),\n+\t},\n+\t.common\t\t= {\n+\t\t.reg\t\t= 0x1308,\n+\t\t.features\t= CCU_FEATURE_FIXED_PREDIV,\n+\t\t.hw.init\t= CLK_HW_INIT_PARENTS_DATA(\"usb-ohci1\", usb_ohci_parents,\n+\t\t\t\t\t\t\t \u0026ccu_mux_ops, 0),\n+\t},\n+};\n+static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, \"bus-ohci1\", ahb_hws, 0x130c, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, \"bus-ehci1\", ahb_hws, 0x130c, BIT(4), 0);\n+\n+static const struct clk_parent_data usb01_ref_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_MUX_DATA(usb01_ref_clk, \"usb01-ref\", usb01_ref_parents, 0x1340, 24, 3, 0);\n+\n+static SUNXI_CCU_MUX_DATA(usb2_u2_ref_clk, \"usb2-u2-ref\", usb01_ref_parents, 0x1348, 24, 3, 0);\n+\n+static const struct clk_parent_data usb2_suspend_parents[] = {\n+\t{ .fw_name = \"losc\" },\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_suspend_clk, \"usb2-suspend\", usb2_suspend_parents,\n+\t\t\t\t 0x1350,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 1,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data usb2_mf_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_300M_clk.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_mf_clk, \"usb2-mf\", usb2_mf_parents,\n+\t\t\t\t 0x1354,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data usb2_u3_utmi_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_300M_clk.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u3_utmi_clk, \"usb2-u3-utmi\", usb2_u3_utmi_parents,\n+\t\t\t\t 0x1360,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data usb2_u2_pipe_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_480M_clk.common.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u2_pipe_clk, \"usb2-u2-pipe\", usb2_u2_pipe_parents,\n+\t\t\t\t 0x1364,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data pcie_aux_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"losc\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, \"pcie-aux\", pcie_aux_parents, 0x1380,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 1,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_hw *pcie_axi_slv_parents[] = {\n+\t\u0026pll_periph0_600M_clk.hw,\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_periph0_400M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(pcie_axi_slv_clk, \"pcie-axi-slv\", pcie_axi_slv_parents, 0x1384,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_hw *serdes_phy_parents[] = {\n+\t\u0026sys_24M_clk.hw,\n+\t\u0026pll_periph0_600M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(serdes_phy_clk, \"serdes-phy\", serdes_phy_parents, 0x13c0,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data gmac_ptp_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_200M_clk.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gmac_ptp_clk, \"gmac-ptp\", gmac_ptp_parents, 0x1400,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_M_HWS_WITH_GATE(gmac0_phy_clk, \"gmac0-phy\", pll_periph0_150M_hws, 0x1410,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_gmac0_clk, \"bus-gmac0\", ahb_hws, 0x141c, BIT(0), 0);\n+\n+/* Undocumented, taken from the vendor kernel. */\n+static SUNXI_CCU_M_HWS_WITH_GATE(gmac1_phy_clk, \"gmac1-phy\", pll_periph0_150M_hws, 0x1420,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_gmac1_clk, \"bus-gmac1\", ahb_hws, 0x142c, BIT(0), 0);\n+\n+static const struct clk_hw *tcon_lcd_parents[] = {\n+\t\u0026pll_video0_4x_clk.common.hw,\n+\t\u0026pll_video1_4x_clk.common.hw,\n+\t\u0026pll_video2_4x_clk.common.hw,\n+\t\u0026pll_periph0_2x_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, \"tcon-lcd0\", tcon_lcd_parents, 0x1500,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, \"bus-tcon-lcd0\", ahb_hws, 0x1504, BIT(0), 0);\n+\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, \"tcon-lcd1\", tcon_lcd_parents, 0x1508,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, \"bus-tcon-lcd1\", ahb_hws, 0x150c, BIT(0), 0);\n+\n+/* Undocumented, taken from the vendor kernel. */\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, \"tcon-lcd2\", tcon_lcd_parents, 0x1510,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, \"bus-tcon-lcd2\", ahb_hws, 0x1514, BIT(0), 0);\n+\n+static const struct clk_hw *dsi_parents[] = {\n+\t\u0026sys_24M_clk.hw,\n+\t\u0026pll_periph0_200M_clk.hw,\n+\t\u0026pll_periph0_150M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi0_clk, \"dsi0\", dsi_parents, 0x1580,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_dsi0_clk, \"bus-dsi0\", ahb_hws, 0x1584, BIT(0), 0);\n+\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, \"dsi1\", dsi_parents, 0x1588,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_dsi1_clk, \"bus-dsi1\", ahb_hws, 0x158c, BIT(0), 0);\n+\n+static const struct clk_hw *combphy_parents[] = {\n+\t\u0026pll_video0_4x_clk.common.hw,\n+\t\u0026pll_video1_4x_clk.common.hw,\n+\t\u0026pll_video2_4x_clk.common.hw,\n+\t\u0026pll_periph0_2x_clk.common.hw,\n+\t\u0026pll_video0_3x_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy0_clk, \"combphy0\", combphy_parents, 0x15c0,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, \"combphy1\", combphy_parents, 0x15c4,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, \"bus-tcon-tv0\", ahb_hws, 0x1604, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, \"bus-tcon-tv1\", ahb_hws, 0x160c, BIT(0), 0);\n+\n+static const struct clk_hw *edp_tv_parents[] = {\n+\t\u0026pll_video0_4x_clk.common.hw,\n+\t\u0026pll_video1_4x_clk.common.hw,\n+\t\u0026pll_video2_4x_clk.common.hw,\n+\t\u0026pll_periph0_2x_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, \"edp-tv\", edp_tv_parents, 0x1640,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_edp_tv_clk, \"bus-edp-tv\", ahb_hws, 0x164c, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, \"hdmi-cec-32k\", pll_periph0_2x_hws, 0x1680,\n+\t\t\t\t BIT(30),\t/* gate */\n+\t\t\t\t 36621,\t/* pre div */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data hdmi_cec_parents[] = {\n+\t{ .fw_name = \"losc\" },\n+\t{ .hw = \u0026hdmi_cec_32k_clk.common.hw },\n+};\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, \"hdmi-cec\", hdmi_cec_parents, 0x1680,\n+\t\t\t\t 24, 1,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data hdmi_tv_parents[] = {\n+\t{ .hw = \u0026pll_video0_4x_clk.common.hw },\n+\t{ .hw = \u0026pll_video1_4x_clk.common.hw },\n+\t{ .hw = \u0026pll_video2_4x_clk.common.hw },\n+\t{ .hw = \u0026pll_periph0_2x_clk.common.hw },\n+};\n+static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, \"hdmi-tv\", hdmi_tv_parents, 0x1684,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_hdmi_tv_clk, \"bus-hdmi-tv\", ahb_hws, 0x168c, BIT(0), 0);\n+\n+static const struct clk_parent_data hdmi_sfr_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, \"hdmi-sfr\", hdmi_sfr_parents, 0x1690,\n+\t\t\t\t 24, 1,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_GATE_HWS(hdcp_esm_clk, \"hdcp-esm\", pll_periph0_300M_hws, 0x1694, BIT(31), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_dpss_top0_clk, \"bus-dpss-top0\", ahb_hws, 0x16c4, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS(bus_dpss_top1_clk, \"bus-dpss-top1\", ahb_hws, 0x16cc, BIT(0), 0);\n+\n+static const struct clk_parent_data ledc_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_periph0_600M_clk.hw },\n+\t{ .fw_name = \"hosc\" },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, \"ledc\", ledc_parents, 0x1700,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_ledc_clk, \"bus-ledc\", apb0_hws, 0x1704, BIT(0), 0);\n+\n+static SUNXI_CCU_GATE_HWS(bus_dsc_clk, \"bus-dsc\", ahb_hws, 0x1744, BIT(0), 0);\n+\n+static const struct clk_parent_data csi_master_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .hw = \u0026pll_video0_4x_clk.common.hw },\n+\t{ .hw = \u0026pll_video0_3x_clk.common.hw },\n+\t{ .hw = \u0026pll_video1_4x_clk.common.hw },\n+\t{ .hw = \u0026pll_video1_3x_clk.common.hw },\n+\t{ .hw = \u0026pll_video2_4x_clk.common.hw },\n+\t{ .hw = \u0026pll_video2_3x_clk.common.hw },\n+};\n+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master0_clk, \"csi_master0\", csi_master_parents, 0x1800,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master1_clk, \"csi_master1\", csi_master_parents, 0x1804,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master2_clk, \"csi_master2\", csi_master_parents, 0x1808,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_hw *csi_parents[] = {\n+\t\u0026pll_video2_4x_clk.common.hw,\n+\t\u0026pll_de_4x_clk.common.hw,\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_periph0_400M_clk.hw,\n+\t\u0026pll_periph0_600M_clk.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, \"csi\", csi_parents, 0x1840,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_GATE_HWS(bus_csi_clk, \"bus-csi\", ahb_hws, 0x1844, BIT(0), 0);\n+\n+static const struct clk_hw *isp_parents[] = {\n+\t\u0026pll_video2_4x_clk.common.hw,\n+\t\u0026pll_periph0_480M_clk.common.hw,\n+\t\u0026pll_periph0_400M_clk.hw,\n+\t\u0026pll_periph0_600M_clk.hw,\n+\t\u0026pll_video0_4x_clk.common.hw,\n+\t\u0026pll_video1_4x_clk.common.hw,\n+};\n+static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, \"isp\", isp_parents, 0x1860,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_GATE_DATA(res_dcap_24m_clk, \"res-dcap-24m\", hosc, 0x1a00, BIT(3), 0);\n+\n+static const struct clk_parent_data apb2jtag_parents[] = {\n+\t{ .hw = \u0026sys_24M_clk.hw },\n+\t{ .fw_name = \"losc\" },\n+\t{ .fw_name = \"iosc\" },\n+\t{ .hw = \u0026pll_periph0_480M_clk.common.hw },\n+\t{ .hw = \u0026pll_periph1_480M_clk.common.hw },\n+\t{ .hw = \u0026pll_periph0_200M_clk.hw },\n+\t{ .hw = \u0026pll_periph1_200M_clk.hw },\n+};\n+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(apb2jtag_clk, \"apb2jtag\", apb2jtag_parents, 0x1c00,\n+\t\t\t\t 0, 5,\t/* M */\n+\t\t\t\t 24, 3,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static SUNXI_CCU_GATE_HWS(fanout_24M_clk, \"fanout-24M\", sys_24M_hws, 0x1f30, BIT(0), 0);\n+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_12M_clk, \"fanout-12M\", sys_24M_hws, 0x1f30,\n+\t\t\t\t BIT(1), 2, 0);\n+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, \"fanout-16M\", pll_periph0_480M_hws, 0x1f30,\n+\t\t\t\t BIT(2), 30, 0);\n+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, \"fanout-25M\", pll_periph0_2x_hws, 0x1f30,\n+\t\t\t\t BIT(3), 48, 0);\n+\n+static const struct clk_parent_data fanout_27M_parents[] = {\n+\t{ .hw = \u0026pll_video0_4x_clk.common.hw },\n+\t{ .hw = \u0026pll_video1_4x_clk.common.hw },\n+\t{ .hw = \u0026pll_video2_4x_clk.common.hw },\n+};\n+static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, \"fanout-27M\", fanout_27M_parents, 0x1f34,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 8, 5,\t\t/* N */\n+\t\t\t\t 24, 2,\t/* mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data fanout_pclk_parents[] = {\n+\t{ .hw = \u0026apb0_clk.common.hw }\n+};\n+static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, \"fanout-pclk\", fanout_pclk_parents, 0x1f38,\n+\t\t\t\t 0, 5,\t\t/* M */\n+\t\t\t\t 5, 5,\t\t/* N */\n+\t\t\t\t 0, 0,\t\t/* no mux */\n+\t\t\t\t BIT(31),\t/* gate */\n+\t\t\t\t 0);\n+\n+static const struct clk_parent_data fanout_parents[] = {\n+\t{ .fw_name = \"losc-fanout\" },\n+\t{ .hw = \u0026fanout_12M_clk.common.hw, },\n+\t{ .hw = \u0026fanout_16M_clk.common.hw, },\n+\t{ .hw = \u0026fanout_24M_clk.common.hw, },\n+\t{ .hw = \u0026fanout_25M_clk.common.hw, },\n+\t{ .hw = \u0026fanout_27M_clk.common.hw, },\n+\t{ .hw = \u0026fanout_pclk_clk.common.hw, },\n+};\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, \"fanout0\", fanout_parents, 0x1f3c,\n+\t\t\t\t 0, 3,\t/* mux */\n+\t\t\t\t BIT(21),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, \"fanout1\", fanout_parents, 0x1f3c,\n+\t\t\t\t 3, 3,\t/* mux */\n+\t\t\t\t BIT(22),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, \"fanout2\", fanout_parents, 0x1f3c,\n+\t\t\t\t 6, 3,\t/* mux */\n+\t\t\t\t BIT(23),\t/* gate */\n+\t\t\t\t 0);\n+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout3_clk, \"fanout3\", fanout_parents, 0x1f3c,\n+\t\t\t\t 9, 3,\t/* mux */\n+\t\t\t\t BIT(24),\t/* gate */\n+\t\t\t\t 0);\n+\n+/*\n+ * Contains all clocks that are controlled by a hardware register. They\n+ * have a (sunxi) .common member, which needs to be initialised by the common\n+ * sunxi CCU code, to be filled with the MMIO base address and the shared lock.\n+ */\n+static struct ccu_common *sun60i_a733_ccu_clks[] = {\n+\t\u0026pll_ref_clk.common,\n+\t\u0026pll_ddr_clk.common,\n+\t\u0026pll_periph0_4x_clk.common,\n+\t\u0026pll_periph0_2x_clk.common,\n+\t\u0026pll_periph0_800M_clk.common,\n+\t\u0026pll_periph0_480M_clk.common,\n+\t\u0026pll_periph1_4x_clk.common,\n+\t\u0026pll_periph1_2x_clk.common,\n+\t\u0026pll_periph1_800M_clk.common,\n+\t\u0026pll_periph1_480M_clk.common,\n+\t\u0026pll_gpu0_clk.common,\n+\t\u0026pll_video0_clk.common,\n+\t\u0026pll_video0_4x_clk.common,\n+\t\u0026pll_video0_3x_clk.common,\n+\t\u0026pll_video1_clk.common,\n+\t\u0026pll_video1_4x_clk.common,\n+\t\u0026pll_video1_3x_clk.common,\n+\t\u0026pll_video2_clk.common,\n+\t\u0026pll_video2_4x_clk.common,\n+\t\u0026pll_video2_3x_clk.common,\n+\t\u0026pll_ve0_clk.common,\n+\t\u0026pll_ve1_clk.common,\n+\t\u0026pll_audio0_4x_clk.common,\n+\t\u0026pll_audio1_clk.common,\n+\t\u0026pll_npu_clk.common,\n+\t\u0026pll_de_clk.common,\n+\t\u0026pll_de_4x_clk.common,\n+\t\u0026pll_de_3x_clk.common,\n+\t\u0026ahb_clk.common,\n+\t\u0026apb0_clk.common,\n+\t\u0026apb1_clk.common,\n+\t\u0026apb_uart_clk.common,\n+\t\u0026trace_clk.common,\n+\t\u0026gic_clk.common,\n+\t\u0026bus_its_pcie0_aclk_clk.common,\n+\t\u0026mbus_clk.common,\n+\t\u0026mbus_iommu0_sys_clk.common,\n+\t\u0026apb_iommu0_sys_clk.common,\n+\t\u0026ahb_iommu0_sys_clk.common,\n+\t\u0026bus_msi_lite0_clk.common,\n+\t\u0026bus_msi_lite1_clk.common,\n+\t\u0026bus_msi_lite2_clk.common,\n+\t\u0026mbus_iommu1_sys_clk.common,\n+\t\u0026apb_iommu1_sys_clk.common,\n+\t\u0026ahb_iommu1_sys_clk.common,\n+\t\u0026ahb_ve_dec_clk.common,\n+\t\u0026ahb_ve_enc_clk.common,\n+\t\u0026ahb_vid_in_clk.common,\n+\t\u0026ahb_vid_cout0_clk.common,\n+\t\u0026ahb_vid_cout1_clk.common,\n+\t\u0026ahb_de_clk.common,\n+\t\u0026ahb_npu_clk.common,\n+\t\u0026ahb_gpu0_clk.common,\n+\t\u0026ahb_serdes_clk.common,\n+\t\u0026ahb_usb_sys_clk.common,\n+\t\u0026ahb_msi_lite0_clk.common,\n+\t\u0026ahb_store_clk.common,\n+\t\u0026ahb_cpus_clk.common,\n+\t\u0026mbus_iommu0_clk.common,\n+\t\u0026mbus_iommu1_clk.common,\n+\t\u0026mbus_desys_clk.common,\n+\t\u0026mbus_ve_enc0_gate_clk.common,\n+\t\u0026mbus_ve_dec0_gate_clk.common,\n+\t\u0026mbus_gpu0_clk.common,\n+\t\u0026mbus_npu_clk.common,\n+\t\u0026mbus_vid_in_clk.common,\n+\t\u0026mbus_serdes_clk.common,\n+\t\u0026mbus_msi_lite0_clk.common,\n+\t\u0026mbus_store_clk.common,\n+\t\u0026mbus_msi_lite2_clk.common,\n+\t\u0026mbus_dma0_clk.common,\n+\t\u0026mbus_ve_enc0_clk.common,\n+\t\u0026mbus_ce_clk.common,\n+\t\u0026mbus_dma1_clk.common,\n+\t\u0026mbus_nand0_clk.common,\n+\t\u0026mbus_csi_clk.common,\n+\t\u0026mbus_isp_clk.common,\n+\t\u0026mbus_gmac0_clk.common,\n+\t\u0026mbus_gmac1_clk.common,\n+\t\u0026mbus_ve_dec0_clk.common,\n+\t\u0026bus_dma0_clk.common,\n+\t\u0026bus_dma1_clk.common,\n+\t\u0026bus_spinlock_clk.common,\n+\t\u0026bus_msgbox0_clk.common,\n+\t\u0026bus_pwm0_clk.common,\n+\t\u0026bus_pwm1_clk.common,\n+\t\u0026bus_dbg_clk.common,\n+\t\u0026bus_sysdap_clk.common,\n+\t\u0026timer0_clk.common,\n+\t\u0026timer1_clk.common,\n+\t\u0026timer2_clk.common,\n+\t\u0026timer3_clk.common,\n+\t\u0026timer4_clk.common,\n+\t\u0026timer5_clk.common,\n+\t\u0026timer6_clk.common,\n+\t\u0026timer7_clk.common,\n+\t\u0026timer8_clk.common,\n+\t\u0026timer9_clk.common,\n+\t\u0026bus_timer_clk.common,\n+\t\u0026avs_clk.common,\n+\t\u0026de0_clk.common,\n+\t\u0026bus_de0_clk.common,\n+\t\u0026di_clk.common,\n+\t\u0026bus_di_clk.common,\n+\t\u0026g2d_clk.common,\n+\t\u0026bus_g2d_clk.common,\n+\t\u0026eink_clk.common,\n+\t\u0026eink_panel_clk.common,\n+\t\u0026bus_eink_clk.common,\n+\t\u0026ve_enc0_clk.common,\n+\t\u0026ve_dec0_clk.common,\n+\t\u0026bus_ve_enc0_clk.common,\n+\t\u0026bus_ve_dec0_clk.common,\n+\t\u0026ce_clk.common,\n+\t\u0026bus_ce_clk.common,\n+\t\u0026bus_ce_sys_clk.common,\n+\t\u0026npu_clk.common,\n+\t\u0026bus_npu_clk.common,\n+\t\u0026gpu0_clk.common,\n+\t\u0026bus_gpu0_clk.common,\n+\t\u0026dram0_clk.common,\n+\t\u0026bus_dram0_clk.common,\n+\t\u0026nand0_clk0_clk.common,\n+\t\u0026nand0_clk1_clk.common,\n+\t\u0026bus_nand0_clk.common,\n+\t\u0026mmc0_clk.common,\n+\t\u0026bus_mmc0_clk.common,\n+\t\u0026mmc1_clk.common,\n+\t\u0026bus_mmc1_clk.common,\n+\t\u0026mmc2_clk.common,\n+\t\u0026bus_mmc2_clk.common,\n+\t\u0026mmc3_clk.common,\n+\t\u0026bus_mmc3_clk.common,\n+\t\u0026ufs_axi_clk.common,\n+\t\u0026ufs_cfg_clk.common,\n+\t\u0026bus_ufs_clk.common,\n+\t\u0026bus_uart0_clk.common,\n+\t\u0026bus_uart1_clk.common,\n+\t\u0026bus_uart2_clk.common,\n+\t\u0026bus_uart3_clk.common,\n+\t\u0026bus_uart4_clk.common,\n+\t\u0026bus_uart5_clk.common,\n+\t\u0026bus_uart6_clk.common,\n+\t\u0026bus_i2c0_clk.common,\n+\t\u0026bus_i2c1_clk.common,\n+\t\u0026bus_i2c2_clk.common,\n+\t\u0026bus_i2c3_clk.common,\n+\t\u0026bus_i2c4_clk.common,\n+\t\u0026bus_i2c5_clk.common,\n+\t\u0026bus_i2c6_clk.common,\n+\t\u0026bus_i2c7_clk.common,\n+\t\u0026bus_i2c8_clk.common,\n+\t\u0026bus_i2c9_clk.common,\n+\t\u0026bus_i2c10_clk.common,\n+\t\u0026bus_i2c11_clk.common,\n+\t\u0026bus_i2c12_clk.common,\n+\t\u0026spi0_clk.common,\n+\t\u0026bus_spi0_clk.common,\n+\t\u0026spi1_clk.common,\n+\t\u0026bus_spi1_clk.common,\n+\t\u0026spi2_clk.common,\n+\t\u0026bus_spi2_clk.common,\n+\t\u0026spif_clk.common,\n+\t\u0026bus_spif_clk.common,\n+\t\u0026spi3_clk.common,\n+\t\u0026bus_spi3_clk.common,\n+\t\u0026spi4_clk.common,\n+\t\u0026bus_spi4_clk.common,\n+\t\u0026gpadc0_24m_clk.common,\n+\t\u0026bus_gpadc0_clk.common,\n+\t\u0026bus_ths0_clk.common,\n+\t\u0026irrx_clk.common,\n+\t\u0026bus_irrx_clk.common,\n+\t\u0026irtx_clk.common,\n+\t\u0026bus_irtx_clk.common,\n+\t\u0026bus_lradc_clk.common,\n+\t\u0026sgpio_clk.common,\n+\t\u0026bus_sgpio_clk.common,\n+\t\u0026lpc_clk.common,\n+\t\u0026bus_lpc_clk.common,\n+\t\u0026i2spcm0_clk.common,\n+\t\u0026bus_i2spcm0_clk.common,\n+\t\u0026i2spcm1_clk.common,\n+\t\u0026bus_i2spcm1_clk.common,\n+\t\u0026i2spcm2_clk.common,\n+\t\u0026i2spcm2_asrc_clk.common,\n+\t\u0026bus_i2spcm2_clk.common,\n+\t\u0026i2spcm3_clk.common,\n+\t\u0026bus_i2spcm3_clk.common,\n+\t\u0026i2spcm4_clk.common,\n+\t\u0026bus_i2spcm4_clk.common,\n+\t\u0026spdif_tx_clk.common,\n+\t\u0026spdif_rx_clk.common,\n+\t\u0026bus_spdif_clk.common,\n+\t\u0026dmic_clk.common,\n+\t\u0026bus_dmic_clk.common,\n+\t\u0026usb_ohci0_clk.common,\n+\t\u0026bus_ohci0_clk.common,\n+\t\u0026bus_ehci0_clk.common,\n+\t\u0026bus_otg_clk.common,\n+\t\u0026usb_ohci1_clk.common,\n+\t\u0026bus_ohci1_clk.common,\n+\t\u0026bus_ehci1_clk.common,\n+\t\u0026usb01_ref_clk.common,\n+\t\u0026usb2_u2_ref_clk.common,\n+\t\u0026usb2_suspend_clk.common,\n+\t\u0026usb2_mf_clk.common,\n+\t\u0026usb2_u3_utmi_clk.common,\n+\t\u0026usb2_u2_pipe_clk.common,\n+\t\u0026pcie_aux_clk.common,\n+\t\u0026pcie_axi_slv_clk.common,\n+\t\u0026serdes_phy_clk.common,\n+\t\u0026gmac_ptp_clk.common,\n+\t\u0026gmac0_phy_clk.common,\n+\t\u0026bus_gmac0_clk.common,\n+\t\u0026gmac1_phy_clk.common,\n+\t\u0026bus_gmac1_clk.common,\n+\t\u0026tcon_lcd0_clk.common,\n+\t\u0026bus_tcon_lcd0_clk.common,\n+\t\u0026tcon_lcd1_clk.common,\n+\t\u0026bus_tcon_lcd1_clk.common,\n+\t\u0026tcon_lcd2_clk.common,\n+\t\u0026bus_tcon_lcd2_clk.common,\n+\t\u0026dsi0_clk.common,\n+\t\u0026bus_dsi0_clk.common,\n+\t\u0026dsi1_clk.common,\n+\t\u0026bus_dsi1_clk.common,\n+\t\u0026combphy0_clk.common,\n+\t\u0026combphy1_clk.common,\n+\t\u0026bus_tcon_tv0_clk.common,\n+\t\u0026bus_tcon_tv1_clk.common,\n+\t\u0026edp_tv_clk.common,\n+\t\u0026bus_edp_tv_clk.common,\n+\t\u0026hdmi_cec_32k_clk.common,\n+\t\u0026hdmi_cec_clk.common,\n+\t\u0026hdmi_tv_clk.common,\n+\t\u0026bus_hdmi_tv_clk.common,\n+\t\u0026hdmi_sfr_clk.common,\n+\t\u0026hdcp_esm_clk.common,\n+\t\u0026bus_dpss_top0_clk.common,\n+\t\u0026bus_dpss_top1_clk.common,\n+\t\u0026ledc_clk.common,\n+\t\u0026bus_ledc_clk.common,\n+\t\u0026bus_dsc_clk.common,\n+\t\u0026csi_master0_clk.common,\n+\t\u0026csi_master1_clk.common,\n+\t\u0026csi_master2_clk.common,\n+\t\u0026csi_clk.common,\n+\t\u0026bus_csi_clk.common,\n+\t\u0026isp_clk.common,\n+\t\u0026res_dcap_24m_clk.common,\n+\t\u0026apb2jtag_clk.common,\n+\t\u0026fanout_24M_clk.common,\n+\t\u0026fanout_12M_clk.common,\n+\t\u0026fanout_16M_clk.common,\n+\t\u0026fanout_25M_clk.common,\n+\t\u0026fanout_27M_clk.common,\n+\t\u0026fanout_pclk_clk.common,\n+\t\u0026fanout0_clk.common,\n+\t\u0026fanout1_clk.common,\n+\t\u0026fanout2_clk.common,\n+\t\u0026fanout3_clk.common,\n+};\n+\n+static struct clk_hw_onecell_data sun60i_a733_hw_clks = {\n+\t.hws\t= {\n+\t\t[CLK_PLL_REF]\t\t= \u0026pll_ref_clk.common.hw,\n+\t\t[CLK_SYS_24M]\t\t= \u0026sys_24M_clk.hw,\n+\t\t[CLK_PLL_DDR]\t\t= \u0026pll_ddr_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH0_4X]\t= \u0026pll_periph0_4x_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH0_2X]\t= \u0026pll_periph0_2x_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH0_800M]\t= \u0026pll_periph0_800M_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH0_480M]\t= \u0026pll_periph0_480M_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH0_600M]\t= \u0026pll_periph0_600M_clk.hw,\n+\t\t[CLK_PLL_PERIPH0_400M]\t= \u0026pll_periph0_400M_clk.hw,\n+\t\t[CLK_PLL_PERIPH0_300M]\t= \u0026pll_periph0_300M_clk.hw,\n+\t\t[CLK_PLL_PERIPH0_200M]\t= \u0026pll_periph0_200M_clk.hw,\n+\t\t[CLK_PLL_PERIPH0_160M]\t= \u0026pll_periph0_160M_clk.hw,\n+\t\t[CLK_PLL_PERIPH0_150M]\t= \u0026pll_periph0_150M_clk.hw,\n+\t\t[CLK_PLL_PERIPH1_4X]\t= \u0026pll_periph1_4x_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH1_2X]\t= \u0026pll_periph1_2x_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH1_800M]\t= \u0026pll_periph1_800M_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH1_480M]\t= \u0026pll_periph1_480M_clk.common.hw,\n+\t\t[CLK_PLL_PERIPH1_600M]\t= \u0026pll_periph1_600M_clk.hw,\n+\t\t[CLK_PLL_PERIPH1_400M]\t= \u0026pll_periph1_400M_clk.hw,\n+\t\t[CLK_PLL_PERIPH1_300M]\t= \u0026pll_periph1_300M_clk.hw,\n+\t\t[CLK_PLL_PERIPH1_200M]\t= \u0026pll_periph1_200M_clk.hw,\n+\t\t[CLK_PLL_PERIPH1_160M]\t= \u0026pll_periph1_160M_clk.hw,\n+\t\t[CLK_PLL_PERIPH1_150M]\t= \u0026pll_periph1_150M_clk.hw,\n+\t\t[CLK_PLL_GPU0]\t\t= \u0026pll_gpu0_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO0]\t\t= \u0026pll_video0_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO0_4X]\t= \u0026pll_video0_4x_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO0_3X]\t= \u0026pll_video0_3x_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO1]\t\t= \u0026pll_video1_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO1_4X]\t= \u0026pll_video1_4x_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO1_3X]\t= \u0026pll_video1_3x_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO2]\t\t= \u0026pll_video2_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO2_4X]\t= \u0026pll_video2_4x_clk.common.hw,\n+\t\t[CLK_PLL_VIDEO2_3X]\t= \u0026pll_video2_3x_clk.common.hw,\n+\t\t[CLK_PLL_VE0]\t\t= \u0026pll_ve0_clk.common.hw,\n+\t\t[CLK_PLL_VE1]\t\t= \u0026pll_ve1_clk.common.hw,\n+\t\t[CLK_PLL_AUDIO0_4X]\t= \u0026pll_audio0_4x_clk.common.hw,\n+\t\t[CLK_PLL_AUDIO1]\t= \u0026pll_audio1_clk.common.hw,\n+\t\t[CLK_PLL_AUDIO1_DIV2]\t= \u0026pll_audio1_div2_clk.hw,\n+\t\t[CLK_PLL_AUDIO1_DIV5]\t= \u0026pll_audio1_div5_clk.hw,\n+\t\t[CLK_PLL_NPU]\t\t= \u0026pll_npu_clk.common.hw,\n+\t\t[CLK_PLL_DE]\t\t= \u0026pll_de_clk.common.hw,\n+\t\t[CLK_PLL_DE_4X]\t\t= \u0026pll_de_4x_clk.common.hw,\n+\t\t[CLK_PLL_DE_3X]\t\t= \u0026pll_de_3x_clk.common.hw,\n+\t\t[CLK_AHB]\t\t= \u0026ahb_clk.common.hw,\n+\t\t[CLK_APB0]\t\t= \u0026apb0_clk.common.hw,\n+\t\t[CLK_APB1]\t\t= \u0026apb1_clk.common.hw,\n+\t\t[CLK_APB_UART]\t\t= \u0026apb_uart_clk.common.hw,\n+\t\t[CLK_TRACE]\t\t= \u0026trace_clk.common.hw,\n+\t\t[CLK_GIC]\t\t= \u0026gic_clk.common.hw,\n+\t\t[CLK_BUS_ITS_PCIE0_ACLK] = \u0026bus_its_pcie0_aclk_clk.common.hw,\n+\t\t[CLK_MBUS]\t\t= \u0026mbus_clk.common.hw,\n+\t\t[CLK_MBUS_IOMMU0_SYS]\t= \u0026mbus_iommu0_sys_clk.common.hw,\n+\t\t[CLK_APB_IOMMU0_SYS]\t= \u0026apb_iommu0_sys_clk.common.hw,\n+\t\t[CLK_AHB_IOMMU0_SYS]\t= \u0026ahb_iommu0_sys_clk.common.hw,\n+\t\t[CLK_BUS_MSI_LITE0]\t= \u0026bus_msi_lite0_clk.common.hw,\n+\t\t[CLK_BUS_MSI_LITE1]\t= \u0026bus_msi_lite1_clk.common.hw,\n+\t\t[CLK_BUS_MSI_LITE2]\t= \u0026bus_msi_lite2_clk.common.hw,\n+\t\t[CLK_MBUS_IOMMU1_SYS]\t= \u0026mbus_iommu1_sys_clk.common.hw,\n+\t\t[CLK_APB_IOMMU1_SYS]\t= \u0026apb_iommu1_sys_clk.common.hw,\n+\t\t[CLK_AHB_IOMMU1_SYS]\t= \u0026ahb_iommu1_sys_clk.common.hw,\n+\t\t[CLK_AHB_VE_DEC]\t= \u0026ahb_ve_dec_clk.common.hw,\n+\t\t[CLK_AHB_VE_ENC]\t= \u0026ahb_ve_enc_clk.common.hw,\n+\t\t[CLK_AHB_VID_IN]\t= \u0026ahb_vid_in_clk.common.hw,\n+\t\t[CLK_AHB_VID_COUT0]\t= \u0026ahb_vid_cout0_clk.common.hw,\n+\t\t[CLK_AHB_VID_COUT1]\t= \u0026ahb_vid_cout1_clk.common.hw,\n+\t\t[CLK_AHB_DE]\t\t= \u0026ahb_de_clk.common.hw,\n+\t\t[CLK_AHB_NPU]\t\t= \u0026ahb_npu_clk.common.hw,\n+\t\t[CLK_AHB_GPU0]\t\t= \u0026ahb_gpu0_clk.common.hw,\n+\t\t[CLK_AHB_SERDES]\t= \u0026ahb_serdes_clk.common.hw,\n+\t\t[CLK_AHB_USB_SYS]\t= \u0026ahb_usb_sys_clk.common.hw,\n+\t\t[CLK_AHB_MSI_LITE0]\t= \u0026ahb_msi_lite0_clk.common.hw,\n+\t\t[CLK_AHB_STORE]\t\t= \u0026ahb_store_clk.common.hw,\n+\t\t[CLK_AHB_CPUS]\t\t= \u0026ahb_cpus_clk.common.hw,\n+\t\t[CLK_MBUS_IOMMU0]\t= \u0026mbus_iommu0_clk.common.hw,\n+\t\t[CLK_MBUS_IOMMU1]\t= \u0026mbus_iommu1_clk.common.hw,\n+\t\t[CLK_MBUS_DESYS]\t= \u0026mbus_desys_clk.common.hw,\n+\t\t[CLK_MBUS_VE_ENC0_GATE]\t= \u0026mbus_ve_enc0_gate_clk.common.hw,\n+\t\t[CLK_MBUS_VE_DEC0_GATE]\t= \u0026mbus_ve_dec0_gate_clk.common.hw,\n+\t\t[CLK_MBUS_GPU0]\t\t= \u0026mbus_gpu0_clk.common.hw,\n+\t\t[CLK_MBUS_NPU]\t\t= \u0026mbus_npu_clk.common.hw,\n+\t\t[CLK_MBUS_VID_IN]\t= \u0026mbus_vid_in_clk.common.hw,\n+\t\t[CLK_MBUS_SERDES]\t= \u0026mbus_serdes_clk.common.hw,\n+\t\t[CLK_MBUS_MSI_LITE0]\t= \u0026mbus_msi_lite0_clk.common.hw,\n+\t\t[CLK_MBUS_STORE]\t= \u0026mbus_store_clk.common.hw,\n+\t\t[CLK_MBUS_MSI_LITE2]\t= \u0026mbus_msi_lite2_clk.common.hw,\n+\t\t[CLK_MBUS_DMA0]\t\t= \u0026mbus_dma0_clk.common.hw,\n+\t\t[CLK_MBUS_VE_ENC0]\t= \u0026mbus_ve_enc0_clk.common.hw,\n+\t\t[CLK_MBUS_CE]\t\t= \u0026mbus_ce_clk.common.hw,\n+\t\t[CLK_MBUS_DMA1]\t\t= \u0026mbus_dma1_clk.common.hw,\n+\t\t[CLK_MBUS_NAND0]\t= \u0026mbus_nand0_clk.common.hw,\n+\t\t[CLK_MBUS_CSI]\t\t= \u0026mbus_csi_clk.common.hw,\n+\t\t[CLK_MBUS_ISP]\t\t= \u0026mbus_isp_clk.common.hw,\n+\t\t[CLK_MBUS_GMAC0]\t= \u0026mbus_gmac0_clk.common.hw,\n+\t\t[CLK_MBUS_GMAC1]\t= \u0026mbus_gmac1_clk.common.hw,\n+\t\t[CLK_MBUS_VE_DEC0]\t= \u0026mbus_ve_dec0_clk.common.hw,\n+\t\t[CLK_BUS_DMA0]\t\t= \u0026bus_dma0_clk.common.hw,\n+\t\t[CLK_BUS_DMA1]\t\t= \u0026bus_dma1_clk.common.hw,\n+\t\t[CLK_BUS_SPINLOCK]\t= \u0026bus_spinlock_clk.common.hw,\n+\t\t[CLK_BUS_MSGBOX0]\t= \u0026bus_msgbox0_clk.common.hw,\n+\t\t[CLK_BUS_PWM0]\t\t= \u0026bus_pwm0_clk.common.hw,\n+\t\t[CLK_BUS_PWM1]\t\t= \u0026bus_pwm1_clk.common.hw,\n+\t\t[CLK_BUS_DBG]\t\t= \u0026bus_dbg_clk.common.hw,\n+\t\t[CLK_BUS_SYSDAP]\t= \u0026bus_sysdap_clk.common.hw,\n+\t\t[CLK_TIMER0]\t\t= \u0026timer0_clk.common.hw,\n+\t\t[CLK_TIMER1]\t\t= \u0026timer1_clk.common.hw,\n+\t\t[CLK_TIMER2]\t\t= \u0026timer2_clk.common.hw,\n+\t\t[CLK_TIMER3]\t\t= \u0026timer3_clk.common.hw,\n+\t\t[CLK_TIMER4]\t\t= \u0026timer4_clk.common.hw,\n+\t\t[CLK_TIMER5]\t\t= \u0026timer5_clk.common.hw,\n+\t\t[CLK_TIMER6]\t\t= \u0026timer6_clk.common.hw,\n+\t\t[CLK_TIMER7]\t\t= \u0026timer7_clk.common.hw,\n+\t\t[CLK_TIMER8]\t\t= \u0026timer8_clk.common.hw,\n+\t\t[CLK_TIMER9]\t\t= \u0026timer9_clk.common.hw,\n+\t\t[CLK_BUS_TIMER]\t\t= \u0026bus_timer_clk.common.hw,\n+\t\t[CLK_AVS]\t\t= \u0026avs_clk.common.hw,\n+\t\t[CLK_DE0]\t\t= \u0026de0_clk.common.hw,\n+\t\t[CLK_BUS_DE0]\t\t= \u0026bus_de0_clk.common.hw,\n+\t\t[CLK_DI]\t\t= \u0026di_clk.common.hw,\n+\t\t[CLK_BUS_DI]\t\t= \u0026bus_di_clk.common.hw,\n+\t\t[CLK_G2D]\t\t= \u0026g2d_clk.common.hw,\n+\t\t[CLK_BUS_G2D]\t\t= \u0026bus_g2d_clk.common.hw,\n+\t\t[CLK_EINK]\t\t= \u0026eink_clk.common.hw,\n+\t\t[CLK_EINK_PANEL]\t= \u0026eink_panel_clk.common.hw,\n+\t\t[CLK_BUS_EINK]\t\t= \u0026bus_eink_clk.common.hw,\n+\t\t[CLK_VE_ENC0]\t\t= \u0026ve_enc0_clk.common.hw,\n+\t\t[CLK_VE_DEC0]\t\t= \u0026ve_dec0_clk.common.hw,\n+\t\t[CLK_BUS_VE_ENC0]\t= \u0026bus_ve_enc0_clk.common.hw,\n+\t\t[CLK_BUS_VE_DEC0]\t= \u0026bus_ve_dec0_clk.common.hw,\n+\t\t[CLK_CE]\t\t= \u0026ce_clk.common.hw,\n+\t\t[CLK_BUS_CE]\t\t= \u0026bus_ce_clk.common.hw,\n+\t\t[CLK_BUS_CE_SYS]\t= \u0026bus_ce_sys_clk.common.hw,\n+\t\t[CLK_NPU]\t\t= \u0026npu_clk.common.hw,\n+\t\t[CLK_BUS_NPU]\t\t= \u0026bus_npu_clk.common.hw,\n+\t\t[CLK_GPU0]\t\t= \u0026gpu0_clk.common.hw,\n+\t\t[CLK_BUS_GPU0]\t\t= \u0026bus_gpu0_clk.common.hw,\n+\t\t[CLK_DRAM0]\t\t= \u0026dram0_clk.common.hw,\n+\t\t[CLK_BUS_DRAM0]\t\t= \u0026bus_dram0_clk.common.hw,\n+\t\t[CLK_NAND0_CLK0]\t= \u0026nand0_clk0_clk.common.hw,\n+\t\t[CLK_NAND0_CLK1]\t= \u0026nand0_clk1_clk.common.hw,\n+\t\t[CLK_BUS_NAND0]\t\t= \u0026bus_nand0_clk.common.hw,\n+\t\t[CLK_MMC0]\t\t= \u0026mmc0_clk.common.hw,\n+\t\t[CLK_BUS_MMC0]\t\t= \u0026bus_mmc0_clk.common.hw,\n+\t\t[CLK_MMC1]\t\t= \u0026mmc1_clk.common.hw,\n+\t\t[CLK_BUS_MMC1]\t\t= \u0026bus_mmc1_clk.common.hw,\n+\t\t[CLK_MMC2]\t\t= \u0026mmc2_clk.common.hw,\n+\t\t[CLK_BUS_MMC2]\t\t= \u0026bus_mmc2_clk.common.hw,\n+\t\t[CLK_MMC3]\t\t= \u0026mmc3_clk.common.hw,\n+\t\t[CLK_BUS_MMC3]\t\t= \u0026bus_mmc3_clk.common.hw,\n+\t\t[CLK_UFS_AXI]\t\t= \u0026ufs_axi_clk.common.hw,\n+\t\t[CLK_UFS_CFG]\t\t= \u0026ufs_cfg_clk.common.hw,\n+\t\t[CLK_BUS_UFS]\t\t= \u0026bus_ufs_clk.common.hw,\n+\t\t[CLK_BUS_UART0]\t\t= \u0026bus_uart0_clk.common.hw,\n+\t\t[CLK_BUS_UART1]\t\t= \u0026bus_uart1_clk.common.hw,\n+\t\t[CLK_BUS_UART2]\t\t= \u0026bus_uart2_clk.common.hw,\n+\t\t[CLK_BUS_UART3]\t\t= \u0026bus_uart3_clk.common.hw,\n+\t\t[CLK_BUS_UART4]\t\t= \u0026bus_uart4_clk.common.hw,\n+\t\t[CLK_BUS_UART5]\t\t= \u0026bus_uart5_clk.common.hw,\n+\t\t[CLK_BUS_UART6]\t\t= \u0026bus_uart6_clk.common.hw,\n+\t\t[CLK_BUS_I2C0]\t\t= \u0026bus_i2c0_clk.common.hw,\n+\t\t[CLK_BUS_I2C1]\t\t= \u0026bus_i2c1_clk.common.hw,\n+\t\t[CLK_BUS_I2C2]\t\t= \u0026bus_i2c2_clk.common.hw,\n+\t\t[CLK_BUS_I2C3]\t\t= \u0026bus_i2c3_clk.common.hw,\n+\t\t[CLK_BUS_I2C4]\t\t= \u0026bus_i2c4_clk.common.hw,\n+\t\t[CLK_BUS_I2C5]\t\t= \u0026bus_i2c5_clk.common.hw,\n+\t\t[CLK_BUS_I2C6]\t\t= \u0026bus_i2c6_clk.common.hw,\n+\t\t[CLK_BUS_I2C7]\t\t= \u0026bus_i2c7_clk.common.hw,\n+\t\t[CLK_BUS_I2C8]\t\t= \u0026bus_i2c8_clk.common.hw,\n+\t\t[CLK_BUS_I2C9]\t\t= \u0026bus_i2c9_clk.common.hw,\n+\t\t[CLK_BUS_I2C10]\t\t= \u0026bus_i2c10_clk.common.hw,\n+\t\t[CLK_BUS_I2C11]\t\t= \u0026bus_i2c11_clk.common.hw,\n+\t\t[CLK_BUS_I2C12]\t\t= \u0026bus_i2c12_clk.common.hw,\n+\t\t[CLK_SPI0]\t\t= \u0026spi0_clk.common.hw,\n+\t\t[CLK_BUS_SPI0]\t\t= \u0026bus_spi0_clk.common.hw,\n+\t\t[CLK_SPI1]\t\t= \u0026spi1_clk.common.hw,\n+\t\t[CLK_BUS_SPI1]\t\t= \u0026bus_spi1_clk.common.hw,\n+\t\t[CLK_SPI2]\t\t= \u0026spi2_clk.common.hw,\n+\t\t[CLK_BUS_SPI2]\t\t= \u0026bus_spi2_clk.common.hw,\n+\t\t[CLK_SPIF]\t\t= \u0026spif_clk.common.hw,\n+\t\t[CLK_BUS_SPIF]\t\t= \u0026bus_spif_clk.common.hw,\n+\t\t[CLK_SPI3]\t\t= \u0026spi3_clk.common.hw,\n+\t\t[CLK_BUS_SPI3]\t\t= \u0026bus_spi3_clk.common.hw,\n+\t\t[CLK_SPI4]\t\t= \u0026spi4_clk.common.hw,\n+\t\t[CLK_BUS_SPI4]\t\t= \u0026bus_spi4_clk.common.hw,\n+\t\t[CLK_GPADC0_24M]\t= \u0026gpadc0_24m_clk.common.hw,\n+\t\t[CLK_BUS_GPADC0]\t= \u0026bus_gpadc0_clk.common.hw,\n+\t\t[CLK_BUS_THS0]\t\t= \u0026bus_ths0_clk.common.hw,\n+\t\t[CLK_IRRX]\t\t= \u0026irrx_clk.common.hw,\n+\t\t[CLK_BUS_IRRX]\t\t= \u0026bus_irrx_clk.common.hw,\n+\t\t[CLK_IRTX]\t\t= \u0026irtx_clk.common.hw,\n+\t\t[CLK_BUS_IRTX]\t\t= \u0026bus_irtx_clk.common.hw,\n+\t\t[CLK_BUS_LRADC]\t\t= \u0026bus_lradc_clk.common.hw,\n+\t\t[CLK_SGPIO]\t\t= \u0026sgpio_clk.common.hw,\n+\t\t[CLK_BUS_SGPIO]\t\t= \u0026bus_sgpio_clk.common.hw,\n+\t\t[CLK_LPC]\t\t= \u0026lpc_clk.common.hw,\n+\t\t[CLK_BUS_LPC]\t\t= \u0026bus_lpc_clk.common.hw,\n+\t\t[CLK_I2SPCM0]\t\t= \u0026i2spcm0_clk.common.hw,\n+\t\t[CLK_BUS_I2SPCM0]\t= \u0026bus_i2spcm0_clk.common.hw,\n+\t\t[CLK_I2SPCM1]\t\t= \u0026i2spcm1_clk.common.hw,\n+\t\t[CLK_BUS_I2SPCM1]\t= \u0026bus_i2spcm1_clk.common.hw,\n+\t\t[CLK_I2SPCM2]\t\t= \u0026i2spcm2_clk.common.hw,\n+\t\t[CLK_I2SPCM2_ASRC]\t= \u0026i2spcm2_asrc_clk.common.hw,\n+\t\t[CLK_BUS_I2SPCM2]\t= \u0026bus_i2spcm2_clk.common.hw,\n+\t\t[CLK_I2SPCM3]\t\t= \u0026i2spcm3_clk.common.hw,\n+\t\t[CLK_BUS_I2SPCM3]\t= \u0026bus_i2spcm3_clk.common.hw,\n+\t\t[CLK_I2SPCM4]\t\t= \u0026i2spcm4_clk.common.hw,\n+\t\t[CLK_BUS_I2SPCM4]\t= \u0026bus_i2spcm4_clk.common.hw,\n+\t\t[CLK_SPDIF_TX]\t\t= \u0026spdif_tx_clk.common.hw,\n+\t\t[CLK_SPDIF_RX]\t\t= \u0026spdif_rx_clk.common.hw,\n+\t\t[CLK_BUS_SPDIF]\t\t= \u0026bus_spdif_clk.common.hw,\n+\t\t[CLK_DMIC]\t\t= \u0026dmic_clk.common.hw,\n+\t\t[CLK_BUS_DMIC]\t\t= \u0026bus_dmic_clk.common.hw,\n+\t\t[CLK_USB_OHCI0]\t\t= \u0026usb_ohci0_clk.common.hw,\n+\t\t[CLK_BUS_OHCI0]\t\t= \u0026bus_ohci0_clk.common.hw,\n+\t\t[CLK_BUS_EHCI0]\t\t= \u0026bus_ehci0_clk.common.hw,\n+\t\t[CLK_BUS_OTG]\t\t= \u0026bus_otg_clk.common.hw,\n+\t\t[CLK_USB_OHCI1]\t\t= \u0026usb_ohci1_clk.common.hw,\n+\t\t[CLK_BUS_OHCI1]\t\t= \u0026bus_ohci1_clk.common.hw,\n+\t\t[CLK_BUS_EHCI1]\t\t= \u0026bus_ehci1_clk.common.hw,\n+\t\t[CLK_USB01_REF]\t\t= \u0026usb01_ref_clk.common.hw,\n+\t\t[CLK_USB2_U2_REF]\t= \u0026usb2_u2_ref_clk.common.hw,\n+\t\t[CLK_USB2_SUSPEND]\t= \u0026usb2_suspend_clk.common.hw,\n+\t\t[CLK_USB2_MF]\t\t= \u0026usb2_mf_clk.common.hw,\n+\t\t[CLK_USB2_U3_UTMI]\t= \u0026usb2_u3_utmi_clk.common.hw,\n+\t\t[CLK_USB2_U2_PIPE]\t= \u0026usb2_u2_pipe_clk.common.hw,\n+\t\t[CLK_PCIE_AUX]\t\t= \u0026pcie_aux_clk.common.hw,\n+\t\t[CLK_PCIE_AXI_SLV]\t= \u0026pcie_axi_slv_clk.common.hw,\n+\t\t[CLK_SERDES_PHY]\t= \u0026serdes_phy_clk.common.hw,\n+\t\t[CLK_GMAC_PTP]\t\t= \u0026gmac_ptp_clk.common.hw,\n+\t\t[CLK_GMAC0_PHY]\t\t= \u0026gmac0_phy_clk.common.hw,\n+\t\t[CLK_BUS_GMAC0]\t\t= \u0026bus_gmac0_clk.common.hw,\n+\t\t[CLK_GMAC1_PHY]\t\t= \u0026gmac1_phy_clk.common.hw,\n+\t\t[CLK_BUS_GMAC1]\t\t= \u0026bus_gmac1_clk.common.hw,\n+\t\t[CLK_TCON_LCD0]\t\t= \u0026tcon_lcd0_clk.common.hw,\n+\t\t[CLK_BUS_TCON_LCD0]\t= \u0026bus_tcon_lcd0_clk.common.hw,\n+\t\t[CLK_TCON_LCD1]\t\t= \u0026tcon_lcd1_clk.common.hw,\n+\t\t[CLK_BUS_TCON_LCD1]\t= \u0026bus_tcon_lcd1_clk.common.hw,\n+\t\t[CLK_TCON_LCD2]\t\t= \u0026tcon_lcd2_clk.common.hw,\n+\t\t[CLK_BUS_TCON_LCD2]\t= \u0026bus_tcon_lcd2_clk.common.hw,\n+\t\t[CLK_DSI0]\t\t= \u0026dsi0_clk.common.hw,\n+\t\t[CLK_BUS_DSI0]\t\t= \u0026bus_dsi0_clk.common.hw,\n+\t\t[CLK_DSI1]\t\t= \u0026dsi1_clk.common.hw,\n+\t\t[CLK_BUS_DSI1]\t\t= \u0026bus_dsi1_clk.common.hw,\n+\t\t[CLK_COMBPHY0]\t\t= \u0026combphy0_clk.common.hw,\n+\t\t[CLK_COMBPHY1]\t\t= \u0026combphy1_clk.common.hw,\n+\t\t[CLK_BUS_TCON_TV0]\t= \u0026bus_tcon_tv0_clk.common.hw,\n+\t\t[CLK_BUS_TCON_TV1]\t= \u0026bus_tcon_tv1_clk.common.hw,\n+\t\t[CLK_EDP_TV]\t\t= \u0026edp_tv_clk.common.hw,\n+\t\t[CLK_BUS_EDP_TV]\t= \u0026bus_edp_tv_clk.common.hw,\n+\t\t[CLK_HDMI_CEC_32K]\t= \u0026hdmi_cec_32k_clk.common.hw,\n+\t\t[CLK_HDMI_CEC]\t\t= \u0026hdmi_cec_clk.common.hw,\n+\t\t[CLK_HDMI_TV]\t\t= \u0026hdmi_tv_clk.common.hw,\n+\t\t[CLK_BUS_HDMI_TV]\t= \u0026bus_hdmi_tv_clk.common.hw,\n+\t\t[CLK_HDMI_SFR]\t\t= \u0026hdmi_sfr_clk.common.hw,\n+\t\t[CLK_HDCP_ESM]\t\t= \u0026hdcp_esm_clk.common.hw,\n+\t\t[CLK_BUS_DPSS_TOP0]\t= \u0026bus_dpss_top0_clk.common.hw,\n+\t\t[CLK_BUS_DPSS_TOP1]\t= \u0026bus_dpss_top1_clk.common.hw,\n+\t\t[CLK_LEDC]\t\t= \u0026ledc_clk.common.hw,\n+\t\t[CLK_BUS_LEDC]\t\t= \u0026bus_ledc_clk.common.hw,\n+\t\t[CLK_BUS_DSC]\t\t= \u0026bus_dsc_clk.common.hw,\n+\t\t[CLK_CSI_MASTER0]\t= \u0026csi_master0_clk.common.hw,\n+\t\t[CLK_CSI_MASTER1]\t= \u0026csi_master1_clk.common.hw,\n+\t\t[CLK_CSI_MASTER2]\t= \u0026csi_master2_clk.common.hw,\n+\t\t[CLK_CSI]\t\t= \u0026csi_clk.common.hw,\n+\t\t[CLK_BUS_CSI]\t\t= \u0026bus_csi_clk.common.hw,\n+\t\t[CLK_ISP]\t\t= \u0026isp_clk.common.hw,\n+\t\t[CLK_RES_DCAP_24M]\t= \u0026res_dcap_24m_clk.common.hw,\n+\t\t[CLK_APB2JTAG]\t\t= \u0026apb2jtag_clk.common.hw,\n+\t\t[CLK_FANOUT_24M]\t= \u0026fanout_24M_clk.common.hw,\n+\t\t[CLK_FANOUT_12M]\t= \u0026fanout_12M_clk.common.hw,\n+\t\t[CLK_FANOUT_16M]\t= \u0026fanout_16M_clk.common.hw,\n+\t\t[CLK_FANOUT_25M]\t= \u0026fanout_25M_clk.common.hw,\n+\t\t[CLK_FANOUT_27M]\t= \u0026fanout_27M_clk.common.hw,\n+\t\t[CLK_FANOUT_PCLK]\t= \u0026fanout_pclk_clk.common.hw,\n+\t\t[CLK_FANOUT0]\t\t= \u0026fanout0_clk.common.hw,\n+\t\t[CLK_FANOUT1]\t\t= \u0026fanout1_clk.common.hw,\n+\t\t[CLK_FANOUT2]\t\t= \u0026fanout2_clk.common.hw,\n+\t\t[CLK_FANOUT3]\t\t= \u0026fanout3_clk.common.hw,\n+\t},\n+\t.num\t= CLK_FANOUT3 + 1,\n+};\n+\n+static const struct ccu_reset_map sun60i_a733_ccu_resets[] = {\n+\t[RST_BUS_ITS_PCIE0]\t\t= { 0x574, BIT(16) },\n+\t[RST_BUS_IOMMU0_SYS]\t\t= { 0x58c, BIT(16) },\n+\t[RST_BUS_MSI_LITE0_AHB]\t\t= { 0x594, BIT(16) },\n+\t[RST_BUS_MSI_LITE0_MBUS]\t= { 0x594, BIT(17) },\n+\t[RST_BUS_MSI_LITE1_AHB]\t\t= { 0x59c, BIT(16) },\n+\t[RST_BUS_MSI_LITE1_MBUS]\t= { 0x59c, BIT(17) },\n+\t[RST_BUS_MSI_LITE2_AHB]\t\t= { 0x5a4, BIT(16) },\n+\t[RST_BUS_MSI_LITE2_MBUS]\t= { 0x5a4, BIT(17) },\n+\t[RST_BUS_IOMMU1_SYS]\t\t= { 0x5b4, BIT(16) },\n+\t[RST_BUS_DMA0]\t\t\t= { 0x704, BIT(16) },\n+\t[RST_BUS_DMA1]\t\t\t= { 0x70c, BIT(16) },\n+\t[RST_BUS_SPINLOCK]\t\t= { 0x724, BIT(16) },\n+\t[RST_BUS_MSGBOX]\t\t= { 0x744, BIT(16) },\n+\t[RST_BUS_PWM0]\t\t\t= { 0x784, BIT(16) },\n+\t[RST_BUS_PWM1]\t\t\t= { 0x78c, BIT(16) },\n+\t[RST_BUS_DBG]\t\t\t= { 0x7a4, BIT(16) },\n+\t[RST_BUS_SYSDAP]\t\t= { 0x7ac, BIT(16) },\n+\t[RST_BUS_TIMER0]\t\t= { 0x850, BIT(16) },\n+\t[RST_BUS_DE0]\t\t\t= { 0xa04, BIT(16) },\n+\t[RST_BUS_DI]\t\t\t= { 0xa24, BIT(16) },\n+\t[RST_BUS_G2D]\t\t\t= { 0xa44, BIT(16) },\n+\t[RST_BUS_EINK]\t\t\t= { 0xa6c, BIT(16) },\n+\t[RST_BUS_DE_SYS]\t\t= { 0xa74, BIT(16) },\n+\t[RST_BUS_VE_ENC0]\t\t= { 0xa8c, BIT(16) },\n+\t[RST_BUS_VE_DEC0]\t\t= { 0xa8c, BIT(18) },\n+\t[RST_BUS_CE]\t\t\t= { 0xac4, BIT(16) },\n+\t[RST_BUS_CE_SYS]\t\t= { 0xac4, BIT(17) },\n+\t[RST_BUS_NPU_CORE]\t\t= { 0xb04, BIT(16) },\n+\t[RST_BUS_NPU_AXI]\t\t= { 0xb04, BIT(17) },\n+\t[RST_BUS_NPU_AHB]\t\t= { 0xb04, BIT(18) },\n+\t[RST_BUS_NPU_SRAM]\t\t= { 0xb04, BIT(19) },\n+\t[RST_BUS_GPU0]\t\t\t= { 0xb24, BIT(16) },\n+\t[RST_BUS_DRAM0]\t\t\t= { 0xc0c, BIT(16) },\n+\t[RST_BUS_NAND0]\t\t\t= { 0xc8c, BIT(16) },\n+\t[RST_BUS_MMC0]\t\t\t= { 0xd0c, BIT(16) },\n+\t[RST_BUS_MMC1]\t\t\t= { 0xd1c, BIT(16) },\n+\t[RST_BUS_MMC2]\t\t\t= { 0xd2c, BIT(16) },\n+\t[RST_BUS_MMC3]\t\t\t= { 0xd3c, BIT(16) },\n+\t[RST_BUS_UFS_AHB]\t\t= { 0xd8c, BIT(16) },\n+\t[RST_BUS_UFS_AXI]\t\t= { 0xd8c, BIT(17) },\n+\t[RST_BUS_UFS_PHY]\t\t= { 0xd8c, BIT(18) },\n+\t[RST_BUS_UFS_CORE]\t\t= { 0xd8c, BIT(19) },\n+\t[RST_BUS_UART0]\t\t\t= { 0xe00, BIT(16) },\n+\t[RST_BUS_UART1]\t\t\t= { 0xe04, BIT(16) },\n+\t[RST_BUS_UART2]\t\t\t= { 0xe08, BIT(16) },\n+\t[RST_BUS_UART3]\t\t\t= { 0xe0c, BIT(16) },\n+\t[RST_BUS_UART4]\t\t\t= { 0xe10, BIT(16) },\n+\t[RST_BUS_UART5]\t\t\t= { 0xe14, BIT(16) },\n+\t[RST_BUS_UART6]\t\t\t= { 0xe18, BIT(16) },\n+\t[RST_BUS_I2C0]\t\t\t= { 0xe80, BIT(16) },\n+\t[RST_BUS_I2C1]\t\t\t= { 0xe84, BIT(16) },\n+\t[RST_BUS_I2C2]\t\t\t= { 0xe88, BIT(16) },\n+\t[RST_BUS_I2C3]\t\t\t= { 0xe8c, BIT(16) },\n+\t[RST_BUS_I2C4]\t\t\t= { 0xe90, BIT(16) },\n+\t[RST_BUS_I2C5]\t\t\t= { 0xe94, BIT(16) },\n+\t[RST_BUS_I2C6]\t\t\t= { 0xe98, BIT(16) },\n+\t[RST_BUS_I2C7]\t\t\t= { 0xe9c, BIT(16) },\n+\t[RST_BUS_I2C8]\t\t\t= { 0xea0, BIT(16) },\n+\t[RST_BUS_I2C9]\t\t\t= { 0xea4, BIT(16) },\n+\t[RST_BUS_I2C10]\t\t\t= { 0xea8, BIT(16) },\n+\t[RST_BUS_I2C11]\t\t\t= { 0xeac, BIT(16) },\n+\t[RST_BUS_I2C12]\t\t\t= { 0xeb0, BIT(16) },\n+\t[RST_BUS_SPI0]\t\t\t= { 0xf04, BIT(16) },\n+\t[RST_BUS_SPI1]\t\t\t= { 0xf0c, BIT(16) },\n+\t[RST_BUS_SPI2]\t\t\t= { 0xf14, BIT(16) },\n+\t[RST_BUS_SPIF]\t\t\t= { 0xf1c, BIT(16) },\n+\t[RST_BUS_SPI3]\t\t\t= { 0xf24, BIT(16) },\n+\t[RST_BUS_SPI4]\t\t\t= { 0xf2c, BIT(16) }, /* From the vendor kernel. */\n+\t[RST_BUS_GPADC0]\t\t= { 0xfc4, BIT(16) },\n+\t[RST_BUS_THS0]\t\t\t= { 0xfe4, BIT(16) },\n+\t[RST_BUS_IRRX]\t\t\t= { 0x1004, BIT(16) },\n+\t[RST_BUS_IRTX]\t\t\t= { 0x100c, BIT(16) },\n+\t[RST_BUS_LRADC]\t\t\t= { 0x1024, BIT(16) },\n+\t[RST_BUS_SGPIO]\t\t\t= { 0x1064, BIT(16) }, /* From the vendor kernel. */\n+\t[RST_BUS_LPC]\t\t\t= { 0x1084, BIT(16) }, /* From the vendor kernel. */\n+\t[RST_BUS_I2SPCM0]\t\t= { 0x120c, BIT(16) },\n+\t[RST_BUS_I2SPCM1]\t\t= { 0x121c, BIT(16) },\n+\t[RST_BUS_I2SPCM2]\t\t= { 0x122c, BIT(16) },\n+\t[RST_BUS_I2SPCM3]\t\t= { 0x123c, BIT(16) },\n+\t[RST_BUS_I2SPCM4]\t\t= { 0x124c, BIT(16) },\n+\t[RST_BUS_SPDIF]\t\t\t= { 0x128c, BIT(16) },\n+\t[RST_BUS_DMIC]\t\t\t= { 0x12cc, BIT(16) },\n+\t[RST_USB_PHY0]\t\t\t= { 0x1300, BIT(30) },\n+\t[RST_BUS_OHCI0]\t\t\t= { 0x1304, BIT(16) },\n+\t[RST_BUS_EHCI0]\t\t\t= { 0x1304, BIT(20) },\n+\t[RST_BUS_OTG]\t\t\t= { 0x1304, BIT(24) },\n+\t[RST_USB_PHY1]\t\t\t= { 0x1308, BIT(30) },\n+\t[RST_BUS_OHCI1]\t\t\t= { 0x130c, BIT(16) },\n+\t[RST_BUS_EHCI1]\t\t\t= { 0x130c, BIT(20) },\n+\t[RST_BUS_USB2]\t\t\t= { 0x135c, BIT(16) },\n+\t[RST_BUS_PCIE_PWRUP]\t\t= { 0x138c, BIT(16) },\n+\t[RST_BUS_PCIE]\t\t\t= { 0x138c, BIT(17) },\n+\t[RST_BUS_SERDES]\t\t= { 0x13c4, BIT(16) },\n+\t[RST_BUS_GMAC0]\t\t\t= { 0x141c, BIT(16) },\n+\t[RST_BUS_GMAC0_AXI]\t\t= { 0x141c, BIT(17) },\n+\t[RST_BUS_GMAC1]\t\t\t= { 0x142c, BIT(16) }, /* From the vendor kernel. */\n+\t[RST_BUS_GMAC1_AXI]\t\t= { 0x142c, BIT(17) }, /* From the vendor kernel. */\n+\t[RST_BUS_TCON_LCD0]\t\t= { 0x1504, BIT(16) },\n+\t[RST_BUS_TCON_LCD1]\t\t= { 0x150c, BIT(16) },\n+\t[RST_BUS_TCON_LCD2]\t\t= { 0x1514, BIT(16) }, /* From the vendor kernel. */\n+\t[RST_BUS_LVDS0]\t\t\t= { 0x1544, BIT(16) },\n+\t[RST_BUS_LVDS1]\t\t\t= { 0x154c, BIT(16) },\n+\t[RST_BUS_DSI0]\t\t\t= { 0x1584, BIT(16) },\n+\t[RST_BUS_DSI1]\t\t\t= { 0x158c, BIT(16) },\n+\t[RST_BUS_TCON_TV0]\t\t= { 0x1604, BIT(16) },\n+\t[RST_BUS_TCON_TV1]\t\t= { 0x160c, BIT(16) },\n+\t[RST_BUS_EDP]\t\t\t= { 0x164c, BIT(16) },\n+\t[RST_BUS_HDMI_MAIN]\t\t= { 0x168c, BIT(16) },\n+\t[RST_BUS_HDMI_SUB]\t\t= { 0x168c, BIT(17) },\n+\t[RST_BUS_HDMI_HDCP]\t\t= { 0x168c, BIT(18) },\n+\t[RST_BUS_DPSS_TOP0]\t\t= { 0x16c4, BIT(16) },\n+\t[RST_BUS_DPSS_TOP1]\t\t= { 0x16cc, BIT(16) },\n+\t[RST_BUS_VIDEO_OUT0]\t\t= { 0x16e4, BIT(16) },\n+\t[RST_BUS_VIDEO_OUT1]\t\t= { 0x16ec, BIT(16) },\n+\t[RST_BUS_LEDC]\t\t\t= { 0x1704, BIT(16) },\n+\t[RST_BUS_DSC]\t\t\t= { 0x1744, BIT(16) },\n+\t[RST_BUS_CSI]\t\t\t= { 0x1844, BIT(16) },\n+\t[RST_BUS_VIDEO_IN]\t\t= { 0x1884, BIT(16) },\n+\t[RST_BUS_APB2JTAG]\t\t= { 0x1c04, BIT(16) },\n+};\n+\n+static const struct sunxi_ccu_desc sun60i_a733_ccu_desc = {\n+\t.ccu_clks\t= sun60i_a733_ccu_clks,\n+\t.num_ccu_clks\t= ARRAY_SIZE(sun60i_a733_ccu_clks),\n+\n+\t.hw_clks\t= \u0026sun60i_a733_hw_clks,\n+\n+\t.resets\t\t= sun60i_a733_ccu_resets,\n+\t.num_resets\t= ARRAY_SIZE(sun60i_a733_ccu_resets),\n+};\n+\n+static const u32 pll_regs[] = {\n+\tSUN60I_A733_PLL_REF_REG,\n+\tSUN60I_A733_PLL_DDR_REG,\n+\tSUN60I_A733_PLL_PERIPH0_REG,\n+\tSUN60I_A733_PLL_PERIPH1_REG,\n+\tSUN60I_A733_PLL_GPU_REG,\n+\tSUN60I_A733_PLL_VIDEO0_REG,\n+\tSUN60I_A733_PLL_VIDEO1_REG,\n+\tSUN60I_A733_PLL_VIDEO2_REG,\n+\tSUN60I_A733_PLL_VE0_REG,\n+\tSUN60I_A733_PLL_VE1_REG,\n+\tSUN60I_A733_PLL_AUDIO0_REG,\n+\tSUN60I_A733_PLL_AUDIO1_REG,\n+\tSUN60I_A733_PLL_NPU_REG,\n+\tSUN60I_A733_PLL_DE_REG,\n+};\n+\n+static int sun60i_a733_ccu_probe(struct platform_device *pdev)\n+{\n+\tvoid __iomem *reg;\n+\tu32 val;\n+\tint i, ret;\n+\n+\treg = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(reg))\n+\t\treturn PTR_ERR(reg);\n+\n+\t/*\n+\t * The CCU framework only models one enable bit per PLL, while the\n+\t * hardware has separate PLL, LDO, lock, and output gate controls.\n+\t * Enable the common PLL, LDO, and lock controls here.\n+\t */\n+\tfor (i = 0; i \u003c ARRAY_SIZE(pll_regs); i++) {\n+\t\tval = readl(reg + pll_regs[i]);\n+\t\tval |= BIT(31) | BIT(30) | BIT(29);\n+\t\twritel(val, reg + pll_regs[i]);\n+\t}\n+\n+\t/* Enforce m1 = 0 for PLL_AUDIO0. */\n+\tval = readl(reg + SUN60I_A733_PLL_AUDIO0_REG);\n+\tval \u0026= ~BIT(1);\n+\twritel(val, reg + SUN60I_A733_PLL_AUDIO0_REG);\n+\n+\t/* Enforce the named /2 and /5 outputs for PLL_AUDIO1. */\n+\tval = readl(reg + SUN60I_A733_PLL_AUDIO1_REG);\n+\tval \u0026= ~(GENMASK(22, 20) | GENMASK(18, 16));\n+\tval |= (1 \u003c\u003c 20) | (4 \u003c\u003c 16);\n+\twritel(val, reg + SUN60I_A733_PLL_AUDIO1_REG);\n+\n+\tret = devm_sunxi_ccu_probe(\u0026pdev-\u003edev, reg, \u0026sun60i_a733_ccu_desc);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id sun60i_a733_ccu_ids[] = {\n+\t{ .compatible = \"allwinner,sun60i-a733-ccu\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, sun60i_a733_ccu_ids);\n+\n+static struct platform_driver sun60i_a733_ccu_driver = {\n+\t.probe\t= sun60i_a733_ccu_probe,\n+\t.driver\t= {\n+\t\t.name\t\t\t= \"sun60i-a733-ccu\",\n+\t\t.suppress_bind_attrs\t= true,\n+\t\t.of_match_table\t\t= sun60i_a733_ccu_ids,\n+\t},\n+};\n+module_platform_driver(sun60i_a733_ccu_driver);\n+\n+MODULE_IMPORT_NS(\"SUNXI_CCU\");\n+MODULE_DESCRIPTION(\"Support for the Allwinner A733 CCU\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/clk/sunxi-ng/ccu_sdm.c b/drivers/clk/sunxi-ng/ccu_sdm.c\nindex c564e5f9e6104..7e13ffd246d36 100644\n--- a/drivers/clk/sunxi-ng/ccu_sdm.c\n+++ b/drivers/clk/sunxi-ng/ccu_sdm.c\n@@ -18,7 +18,11 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common,\n \tif (sdm-\u003eenable \u0026\u0026 !(readl(common-\u003ebase + common-\u003ereg) \u0026 sdm-\u003eenable))\n \t\treturn false;\n \n-\treturn !!(readl(common-\u003ebase + sdm-\u003etuning_reg) \u0026 sdm-\u003etuning_enable);\n+\tif (sdm-\u003epat1_enable \u0026\u0026\n+\t (readl(common-\u003ebase + sdm-\u003epat1_reg) \u0026 sdm-\u003epat1_enable) != sdm-\u003epat1_enable)\n+\t\treturn false;\n+\n+\treturn !!(readl(common-\u003ebase + sdm-\u003epat0_reg) \u0026 sdm-\u003epat0_enable);\n }\n EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, \"SUNXI_CCU\");\n \n@@ -37,18 +41,27 @@ void ccu_sdm_helper_enable(struct ccu_common *common,\n \tfor (i = 0; i \u003c sdm-\u003etable_size; i++)\n \t\tif (sdm-\u003etable[i].rate == rate)\n \t\t\twritel(sdm-\u003etable[i].pattern,\n-\t\t\t common-\u003ebase + sdm-\u003etuning_reg);\n+\t\t\t common-\u003ebase + sdm-\u003epat0_reg);\n \n \t/* Make sure SDM is enabled */\n \tspin_lock_irqsave(common-\u003elock, flags);\n-\treg = readl(common-\u003ebase + sdm-\u003etuning_reg);\n-\twritel(reg | sdm-\u003etuning_enable, common-\u003ebase + sdm-\u003etuning_reg);\n+\treg = readl(common-\u003ebase + sdm-\u003epat0_reg);\n+\twritel(reg | sdm-\u003epat0_enable, common-\u003ebase + sdm-\u003epat0_reg);\n \tspin_unlock_irqrestore(common-\u003elock, flags);\n \n-\tspin_lock_irqsave(common-\u003elock, flags);\n-\treg = readl(common-\u003ebase + common-\u003ereg);\n-\twritel(reg | sdm-\u003eenable, common-\u003ebase + common-\u003ereg);\n-\tspin_unlock_irqrestore(common-\u003elock, flags);\n+\tif (sdm-\u003eenable) {\n+\t\tspin_lock_irqsave(common-\u003elock, flags);\n+\t\treg = readl(common-\u003ebase + common-\u003ereg);\n+\t\twritel(reg | sdm-\u003eenable, common-\u003ebase + common-\u003ereg);\n+\t\tspin_unlock_irqrestore(common-\u003elock, flags);\n+\t}\n+\n+\tif (sdm-\u003epat1_enable) {\n+\t\tspin_lock_irqsave(common-\u003elock, flags);\n+\t\treg = readl(common-\u003ebase + sdm-\u003epat1_reg);\n+\t\twritel(reg | sdm-\u003epat1_enable, common-\u003ebase + sdm-\u003epat1_reg);\n+\t\tspin_unlock_irqrestore(common-\u003elock, flags);\n+\t}\n }\n EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, \"SUNXI_CCU\");\n \n@@ -61,14 +74,23 @@ void ccu_sdm_helper_disable(struct ccu_common *common,\n \tif (!(common-\u003efeatures \u0026 CCU_FEATURE_SIGMA_DELTA_MOD))\n \t\treturn;\n \n-\tspin_lock_irqsave(common-\u003elock, flags);\n-\treg = readl(common-\u003ebase + common-\u003ereg);\n-\twritel(reg \u0026 ~sdm-\u003eenable, common-\u003ebase + common-\u003ereg);\n-\tspin_unlock_irqrestore(common-\u003elock, flags);\n+\tif (sdm-\u003eenable) {\n+\t\tspin_lock_irqsave(common-\u003elock, flags);\n+\t\treg = readl(common-\u003ebase + common-\u003ereg);\n+\t\twritel(reg \u0026 ~sdm-\u003eenable, common-\u003ebase + common-\u003ereg);\n+\t\tspin_unlock_irqrestore(common-\u003elock, flags);\n+\t}\n+\n+\tif (sdm-\u003epat1_enable) {\n+\t\tspin_lock_irqsave(common-\u003elock, flags);\n+\t\treg = readl(common-\u003ebase + sdm-\u003epat1_reg);\n+\t\twritel(reg \u0026 ~sdm-\u003epat1_enable, common-\u003ebase + sdm-\u003epat1_reg);\n+\t\tspin_unlock_irqrestore(common-\u003elock, flags);\n+\t}\n \n \tspin_lock_irqsave(common-\u003elock, flags);\n-\treg = readl(common-\u003ebase + sdm-\u003etuning_reg);\n-\twritel(reg \u0026 ~sdm-\u003etuning_enable, common-\u003ebase + sdm-\u003etuning_reg);\n+\treg = readl(common-\u003ebase + sdm-\u003epat0_reg);\n+\twritel(reg \u0026 ~sdm-\u003epat0_enable, common-\u003ebase + sdm-\u003epat0_reg);\n \tspin_unlock_irqrestore(common-\u003elock, flags);\n }\n EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, \"SUNXI_CCU\");\n@@ -123,7 +145,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,\n \tpr_debug(\"%s: clock is sigma-delta modulated\\n\",\n \t\t clk_hw_get_name(\u0026common-\u003ehw));\n \n-\treg = readl(common-\u003ebase + sdm-\u003etuning_reg);\n+\treg = readl(common-\u003ebase + sdm-\u003epat0_reg);\n \n \tpr_debug(\"%s: pattern reg is 0x%x\",\n \t\t clk_hw_get_name(\u0026common-\u003ehw), reg);\ndiff --git a/drivers/clk/sunxi-ng/ccu_sdm.h b/drivers/clk/sunxi-ng/ccu_sdm.h\nindex c1a7159b89c31..e94cef141c7de 100644\n--- a/drivers/clk/sunxi-ng/ccu_sdm.h\n+++ b/drivers/clk/sunxi-ng/ccu_sdm.h\n@@ -33,21 +33,28 @@ struct ccu_sdm_internal {\n \tu32\t\ttable_size;\n \t/* early SoCs don't have the SDM enable bit in the PLL register */\n \tu32\t\tenable;\n-\t/* second enable bit in tuning register */\n-\tu32\t\ttuning_enable;\n-\tu16\t\ttuning_reg;\n+\t/* second enable bit in pattern0 register */\n+\tu32\t\tpat0_enable;\n+\tu16\t\tpat0_reg;\n+\t/* on some platforms, the sdm enable bit in pattern1 register */\n+\tu32\t\tpat1_enable;\n+\tu16\t\tpat1_reg;\n };\n \n-#define _SUNXI_CCU_SDM(_table, _enable,\t\t\t\\\n-\t\t _reg, _reg_enable)\t\t\\\n-\t{\t\t\t\t\t\t\\\n-\t\t.table\t\t= _table,\t\t\\\n-\t\t.table_size\t= ARRAY_SIZE(_table),\t\\\n-\t\t.enable\t\t= _enable,\t\t\\\n-\t\t.tuning_enable\t= _reg_enable,\t\t\\\n-\t\t.tuning_reg\t= _reg,\t\t\t\\\n+#define _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, _pat1, _pat1_enable) \\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.table\t\t\t= _table,\t\t\t\\\n+\t\t.table_size\t\t= ARRAY_SIZE(_table),\t\t\\\n+\t\t.enable\t\t\t= _enable,\t\t\t\\\n+\t\t.pat0_enable\t\t= _pat0_enable,\t\t\t\\\n+\t\t.pat0_reg\t\t= _pat0,\t\t\t\\\n+\t\t.pat1_enable\t\t= _pat1_enable,\t\t\t\\\n+\t\t.pat1_reg\t\t= _pat1,\t\t\t\\\n \t}\n \n+#define _SUNXI_CCU_SDM(_table, _enable, _pat0, _pat0_enable)\t\\\n+\t_SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, 0, 0)\n+\n bool ccu_sdm_helper_is_enabled(struct ccu_common *common,\n \t\t\t struct ccu_sdm_internal *sdm);\n void ccu_sdm_helper_enable(struct ccu_common *common,\ndiff --git a/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h b/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h\nnew file mode 100644\nindex 0000000000000..81924cba58ec6\n--- /dev/null\n+++ b/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h\n@@ -0,0 +1,291 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (C) 2026 Junhui Liu \u003cjunhui.liu@pigmoral.tech\u003e\n+ *\n+ * The user manual uses PCLK, HCLK, and MCLK suffixes for some bus clocks.\n+ * These are represented here as APB, AHB, and MBUS prefixes respectively,\n+ * with the bus type moved to the front of the clock name.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_\n+#define _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_\n+\n+#define CLK_PLL_REF\t\t0\n+#define CLK_SYS_24M\t\t1\n+#define CLK_PLL_DDR\t\t2\n+#define CLK_PLL_PERIPH0_4X\t3\n+#define CLK_PLL_PERIPH0_2X\t4\n+#define CLK_PLL_PERIPH0_800M\t5\n+#define CLK_PLL_PERIPH0_480M\t6\n+#define CLK_PLL_PERIPH0_600M\t7\n+#define CLK_PLL_PERIPH0_400M\t8\n+#define CLK_PLL_PERIPH0_300M\t9\n+#define CLK_PLL_PERIPH0_200M\t10\n+#define CLK_PLL_PERIPH0_160M\t11\n+#define CLK_PLL_PERIPH0_150M\t12\n+#define CLK_PLL_PERIPH1_4X\t13\n+#define CLK_PLL_PERIPH1_2X\t14\n+#define CLK_PLL_PERIPH1_800M\t15\n+#define CLK_PLL_PERIPH1_480M\t16\n+#define CLK_PLL_PERIPH1_600M\t17\n+#define CLK_PLL_PERIPH1_400M\t18\n+#define CLK_PLL_PERIPH1_300M\t19\n+#define CLK_PLL_PERIPH1_200M\t20\n+#define CLK_PLL_PERIPH1_160M\t21\n+#define CLK_PLL_PERIPH1_150M\t22\n+#define CLK_PLL_GPU0\t\t23\n+#define CLK_PLL_VIDEO0\t\t24\n+#define CLK_PLL_VIDEO0_4X\t25\n+#define CLK_PLL_VIDEO0_3X\t26\n+#define CLK_PLL_VIDEO1\t\t27\n+#define CLK_PLL_VIDEO1_4X\t28\n+#define CLK_PLL_VIDEO1_3X\t29\n+#define CLK_PLL_VIDEO2\t\t30\n+#define CLK_PLL_VIDEO2_4X\t31\n+#define CLK_PLL_VIDEO2_3X\t32\n+#define CLK_PLL_VE0\t\t33\n+#define CLK_PLL_VE1\t\t34\n+#define CLK_PLL_AUDIO0_4X\t35\n+#define CLK_PLL_AUDIO1\t\t36\n+#define CLK_PLL_AUDIO1_DIV2\t37\n+#define CLK_PLL_AUDIO1_DIV5\t38\n+#define CLK_PLL_NPU\t\t39\n+#define CLK_PLL_DE\t\t40\n+#define CLK_PLL_DE_4X\t\t41\n+#define CLK_PLL_DE_3X\t\t42\n+#define CLK_AHB\t\t\t43\n+#define CLK_APB0\t\t44\n+#define CLK_APB1\t\t45\n+#define CLK_APB_UART\t\t46\n+#define CLK_TRACE\t\t47\n+#define CLK_GIC\t\t\t48\n+#define CLK_BUS_ITS_PCIE0_ACLK\t49\n+#define CLK_MBUS\t\t50\n+#define CLK_MBUS_IOMMU0_SYS\t51\n+#define CLK_APB_IOMMU0_SYS\t52\n+#define CLK_AHB_IOMMU0_SYS\t53\n+#define CLK_BUS_MSI_LITE0\t54\n+#define CLK_BUS_MSI_LITE1\t55\n+#define CLK_BUS_MSI_LITE2\t56\n+#define CLK_MBUS_IOMMU1_SYS\t57\n+#define CLK_APB_IOMMU1_SYS\t58\n+#define CLK_AHB_IOMMU1_SYS\t59\n+#define CLK_AHB_VE_DEC\t\t60\n+#define CLK_AHB_VE_ENC\t\t61\n+#define CLK_AHB_VID_IN\t\t62\n+#define CLK_AHB_VID_COUT0\t63\n+#define CLK_AHB_VID_COUT1\t64\n+#define CLK_AHB_DE\t\t65\n+#define CLK_AHB_NPU\t\t66\n+#define CLK_AHB_GPU0\t\t67\n+#define CLK_AHB_SERDES\t\t68\n+#define CLK_AHB_USB_SYS\t\t69\n+#define CLK_AHB_MSI_LITE0\t70\n+#define CLK_AHB_STORE\t\t71\n+#define CLK_AHB_CPUS\t\t72\n+#define CLK_MBUS_IOMMU0\t\t73\n+#define CLK_MBUS_IOMMU1\t\t74\n+#define CLK_MBUS_DESYS\t\t75\n+#define CLK_MBUS_VE_ENC0_GATE\t76\n+#define CLK_MBUS_VE_DEC0_GATE\t77\n+#define CLK_MBUS_GPU0\t\t78\n+#define CLK_MBUS_NPU\t\t79\n+#define CLK_MBUS_VID_IN\t\t80\n+#define CLK_MBUS_SERDES\t\t81\n+#define CLK_MBUS_MSI_LITE0\t82\n+#define CLK_MBUS_STORE\t\t83\n+#define CLK_MBUS_MSI_LITE2\t84\n+#define CLK_MBUS_DMA0\t\t85\n+#define CLK_MBUS_VE_ENC0\t86\n+#define CLK_MBUS_CE\t\t87\n+#define CLK_MBUS_DMA1\t\t88\n+#define CLK_MBUS_NAND0\t\t89\n+#define CLK_MBUS_CSI\t\t90\n+#define CLK_MBUS_ISP\t\t91\n+#define CLK_MBUS_GMAC0\t\t92\n+#define CLK_MBUS_GMAC1\t\t93\n+#define CLK_MBUS_VE_DEC0\t94\n+#define CLK_BUS_DMA0\t\t95\n+#define CLK_BUS_DMA1\t\t96\n+#define CLK_BUS_SPINLOCK\t97\n+#define CLK_BUS_MSGBOX0\t\t98\n+#define CLK_BUS_PWM0\t\t99\n+#define CLK_BUS_PWM1\t\t100\n+#define CLK_BUS_DBG\t\t101\n+#define CLK_BUS_SYSDAP\t\t102\n+#define CLK_TIMER0\t\t103\n+#define CLK_TIMER1\t\t104\n+#define CLK_TIMER2\t\t105\n+#define CLK_TIMER3\t\t106\n+#define CLK_TIMER4\t\t107\n+#define CLK_TIMER5\t\t108\n+#define CLK_TIMER6\t\t109\n+#define CLK_TIMER7\t\t110\n+#define CLK_TIMER8\t\t111\n+#define CLK_TIMER9\t\t112\n+#define CLK_BUS_TIMER\t\t113\n+#define CLK_AVS\t\t\t114\n+#define CLK_DE0\t\t\t115\n+#define CLK_BUS_DE0\t\t116\n+#define CLK_DI\t\t\t117\n+#define CLK_BUS_DI\t\t118\n+#define CLK_G2D\t\t\t119\n+#define CLK_BUS_G2D\t\t120\n+#define CLK_EINK\t\t121\n+#define CLK_EINK_PANEL\t\t122\n+#define CLK_BUS_EINK\t\t123\n+#define CLK_VE_ENC0\t\t124\n+#define CLK_VE_DEC0\t\t125\n+#define CLK_BUS_VE_ENC0\t\t126\n+#define CLK_BUS_VE_DEC0\t\t127\n+#define CLK_CE\t\t\t128\n+#define CLK_BUS_CE\t\t129\n+#define CLK_BUS_CE_SYS\t\t130\n+#define CLK_NPU\t\t\t131\n+#define CLK_BUS_NPU\t\t132\n+#define CLK_GPU0\t\t133\n+#define CLK_BUS_GPU0\t\t134\n+#define CLK_DRAM0\t\t135\n+#define CLK_BUS_DRAM0\t\t136\n+#define CLK_NAND0_CLK0\t\t137\n+#define CLK_NAND0_CLK1\t\t138\n+#define CLK_BUS_NAND0\t\t139\n+#define CLK_MMC0\t\t140\n+#define CLK_BUS_MMC0\t\t141\n+#define CLK_MMC1\t\t142\n+#define CLK_BUS_MMC1\t\t143\n+#define CLK_MMC2\t\t144\n+#define CLK_BUS_MMC2\t\t145\n+#define CLK_MMC3\t\t146\n+#define CLK_BUS_MMC3\t\t147\n+#define CLK_UFS_AXI\t\t148\n+#define CLK_UFS_CFG\t\t149\n+#define CLK_BUS_UFS\t\t150\n+#define CLK_BUS_UART0\t\t151\n+#define CLK_BUS_UART1\t\t152\n+#define CLK_BUS_UART2\t\t153\n+#define CLK_BUS_UART3\t\t154\n+#define CLK_BUS_UART4\t\t155\n+#define CLK_BUS_UART5\t\t156\n+#define CLK_BUS_UART6\t\t157\n+#define CLK_BUS_I2C0\t\t158\n+#define CLK_BUS_I2C1\t\t159\n+#define CLK_BUS_I2C2\t\t160\n+#define CLK_BUS_I2C3\t\t161\n+#define CLK_BUS_I2C4\t\t162\n+#define CLK_BUS_I2C5\t\t163\n+#define CLK_BUS_I2C6\t\t164\n+#define CLK_BUS_I2C7\t\t165\n+#define CLK_BUS_I2C8\t\t166\n+#define CLK_BUS_I2C9\t\t167\n+#define CLK_BUS_I2C10\t\t168\n+#define CLK_BUS_I2C11\t\t169\n+#define CLK_BUS_I2C12\t\t170\n+#define CLK_SPI0\t\t171\n+#define CLK_BUS_SPI0\t\t172\n+#define CLK_SPI1\t\t173\n+#define CLK_BUS_SPI1\t\t174\n+#define CLK_SPI2\t\t175\n+#define CLK_BUS_SPI2\t\t176\n+#define CLK_SPIF\t\t177\n+#define CLK_BUS_SPIF\t\t178\n+#define CLK_SPI3\t\t179\n+#define CLK_BUS_SPI3\t\t180\n+#define CLK_SPI4\t\t181\n+#define CLK_BUS_SPI4\t\t182\n+#define CLK_GPADC0_24M\t\t183\n+#define CLK_BUS_GPADC0\t\t184\n+#define CLK_BUS_THS0\t\t185\n+#define CLK_IRRX\t\t186\n+#define CLK_BUS_IRRX\t\t187\n+#define CLK_IRTX\t\t188\n+#define CLK_BUS_IRTX\t\t189\n+#define CLK_BUS_LRADC\t\t190\n+#define CLK_SGPIO\t\t191\n+#define CLK_BUS_SGPIO\t\t192\n+#define CLK_LPC\t\t\t193\n+#define CLK_BUS_LPC\t\t194\n+#define CLK_I2SPCM0\t\t195\n+#define CLK_BUS_I2SPCM0\t\t196\n+#define CLK_I2SPCM1\t\t197\n+#define CLK_BUS_I2SPCM1\t\t198\n+#define CLK_I2SPCM2\t\t199\n+#define CLK_I2SPCM2_ASRC\t200\n+#define CLK_BUS_I2SPCM2\t\t201\n+#define CLK_I2SPCM3\t\t202\n+#define CLK_BUS_I2SPCM3\t\t203\n+#define CLK_I2SPCM4\t\t204\n+#define CLK_BUS_I2SPCM4\t\t205\n+#define CLK_SPDIF_TX\t\t206\n+#define CLK_SPDIF_RX\t\t207\n+#define CLK_BUS_SPDIF\t\t208\n+#define CLK_DMIC\t\t209\n+#define CLK_BUS_DMIC\t\t210\n+#define CLK_USB_OHCI0\t\t211\n+#define CLK_BUS_OHCI0\t\t212\n+#define CLK_BUS_EHCI0\t\t213\n+#define CLK_BUS_OTG\t\t214\n+#define CLK_USB_OHCI1\t\t215\n+#define CLK_BUS_OHCI1\t\t216\n+#define CLK_BUS_EHCI1\t\t217\n+#define CLK_USB01_REF\t\t218\n+#define CLK_USB2_U2_REF\t\t219\n+#define CLK_USB2_SUSPEND\t220\n+#define CLK_USB2_MF\t\t221\n+#define CLK_USB2_U3_UTMI\t222\n+#define CLK_USB2_U2_PIPE\t223\n+#define CLK_PCIE_AUX\t\t224\n+#define CLK_PCIE_AXI_SLV\t225\n+#define CLK_SERDES_PHY\t\t226\n+#define CLK_GMAC_PTP\t\t227\n+#define CLK_GMAC0_PHY\t\t228\n+#define CLK_BUS_GMAC0\t\t229\n+#define CLK_GMAC1_PHY\t\t230\n+#define CLK_BUS_GMAC1\t\t231\n+#define CLK_TCON_LCD0\t\t232\n+#define CLK_BUS_TCON_LCD0\t233\n+#define CLK_TCON_LCD1\t\t234\n+#define CLK_BUS_TCON_LCD1\t235\n+#define CLK_TCON_LCD2\t\t236\n+#define CLK_BUS_TCON_LCD2\t237\n+#define CLK_DSI0\t\t238\n+#define CLK_BUS_DSI0\t\t239\n+#define CLK_DSI1\t\t240\n+#define CLK_BUS_DSI1\t\t241\n+#define CLK_COMBPHY0\t\t242\n+#define CLK_COMBPHY1\t\t243\n+#define CLK_BUS_TCON_TV0\t244\n+#define CLK_BUS_TCON_TV1\t245\n+#define CLK_EDP_TV\t\t246\n+#define CLK_BUS_EDP_TV\t\t247\n+#define CLK_HDMI_CEC_32K\t248\n+#define CLK_HDMI_CEC\t\t249\n+#define CLK_HDMI_TV\t\t250\n+#define CLK_BUS_HDMI_TV\t\t251\n+#define CLK_HDMI_SFR\t\t252\n+#define CLK_HDCP_ESM\t\t253\n+#define CLK_BUS_DPSS_TOP0\t254\n+#define CLK_BUS_DPSS_TOP1\t255\n+#define CLK_LEDC\t\t256\n+#define CLK_BUS_LEDC\t\t257\n+#define CLK_BUS_DSC\t\t258\n+#define CLK_CSI_MASTER0\t\t259\n+#define CLK_CSI_MASTER1\t\t260\n+#define CLK_CSI_MASTER2\t\t261\n+#define CLK_CSI\t\t\t262\n+#define CLK_BUS_CSI\t\t263\n+#define CLK_ISP\t\t\t264\n+#define CLK_RES_DCAP_24M\t265\n+#define CLK_APB2JTAG\t\t266\n+#define CLK_FANOUT_24M\t\t267\n+#define CLK_FANOUT_12M\t\t268\n+#define CLK_FANOUT_16M\t\t269\n+#define CLK_FANOUT_25M\t\t270\n+#define CLK_FANOUT_27M\t\t271\n+#define CLK_FANOUT_PCLK\t\t272\n+#define CLK_FANOUT0\t\t273\n+#define CLK_FANOUT1\t\t274\n+#define CLK_FANOUT2\t\t275\n+#define CLK_FANOUT3\t\t276\n+\n+#endif /* _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_ */\ndiff --git a/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h b/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h\nnew file mode 100644\nindex 0000000000000..401a1e66e8047\n--- /dev/null\n+++ b/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h\n@@ -0,0 +1,38 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (C) 2026 Junhui Liu \u003cjunhui.liu@pigmoral.tech\u003e\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_\n+#define _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_\n+\n+#define CLK_R_AHB\t\t0\n+#define CLK_R_APB0\t\t1\n+#define CLK_R_APB1\t\t2\n+#define CLK_R_TIMER0\t\t3\n+#define CLK_R_TIMER1\t\t4\n+#define CLK_R_TIMER2\t\t5\n+#define CLK_R_TIMER3\t\t6\n+#define CLK_BUS_R_TIMER\t\t7\n+#define CLK_R_PWM\t\t8\n+#define CLK_BUS_R_PWM\t\t9\n+#define CLK_R_SPI\t\t10\n+#define CLK_BUS_R_SPI\t\t11\n+#define CLK_BUS_R_MSGBOX\t12\n+#define CLK_BUS_R_UART0\t\t13\n+#define CLK_BUS_R_UART1\t\t14\n+#define CLK_BUS_R_I2C0\t\t15\n+#define CLK_BUS_R_I2C1\t\t16\n+#define CLK_BUS_R_I2C2\t\t17\n+#define CLK_BUS_R_PPU\t\t18\n+#define CLK_BUS_R_TZMA\t\t19\n+#define CLK_BUS_R_CPU_BIST\t20\n+#define CLK_R_IR_RX\t\t21\n+#define CLK_BUS_R_IR_RX\t\t22\n+#define CLK_BUS_R_RTC\t\t23\n+#define CLK_R_RISCV\t\t24\n+#define CLK_BUS_R_RISCV\t\t25\n+#define CLK_BUS_R_RISCV_CFG\t26\n+#define CLK_BUS_R_CPUCFG\t27\n+\n+#endif /* _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_ */\ndiff --git a/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h b/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h\nnew file mode 100644\nindex 0000000000000..a4db2f673bd03\n--- /dev/null\n+++ b/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h\n@@ -0,0 +1,129 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (C) 2026 Junhui Liu \u003cjunhui.liu@pigmoral.tech\u003e\n+ */\n+\n+#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_\n+#define _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_\n+\n+#define RST_BUS_ITS_PCIE0\t0\n+#define RST_BUS_IOMMU0_SYS\t1\n+#define RST_BUS_MSI_LITE0_AHB\t2\n+#define RST_BUS_MSI_LITE0_MBUS\t3\n+#define RST_BUS_MSI_LITE1_AHB\t4\n+#define RST_BUS_MSI_LITE1_MBUS\t5\n+#define RST_BUS_MSI_LITE2_AHB\t6\n+#define RST_BUS_MSI_LITE2_MBUS\t7\n+#define RST_BUS_IOMMU1_SYS\t8\n+#define RST_BUS_DMA0\t\t9\n+#define RST_BUS_DMA1\t\t10\n+#define RST_BUS_SPINLOCK\t11\n+#define RST_BUS_MSGBOX\t\t12\n+#define RST_BUS_PWM0\t\t13\n+#define RST_BUS_PWM1\t\t14\n+#define RST_BUS_DBG\t\t15\n+#define RST_BUS_SYSDAP\t\t16\n+#define RST_BUS_TIMER0\t\t17\n+#define RST_BUS_DE0\t\t18\n+#define RST_BUS_DI\t\t19\n+#define RST_BUS_G2D\t\t20\n+#define RST_BUS_EINK\t\t21\n+#define RST_BUS_DE_SYS\t\t22\n+#define RST_BUS_VE_ENC0\t\t23\n+#define RST_BUS_VE_DEC0\t\t24\n+#define RST_BUS_CE\t\t25\n+#define RST_BUS_CE_SYS\t\t26\n+#define RST_BUS_NPU_CORE\t27\n+#define RST_BUS_NPU_AXI\t\t28\n+#define RST_BUS_NPU_AHB\t\t29\n+#define RST_BUS_NPU_SRAM\t30\n+#define RST_BUS_GPU0\t\t31\n+#define RST_BUS_DRAM0\t\t32\n+#define RST_BUS_NAND0\t\t33\n+#define RST_BUS_MMC0\t\t34\n+#define RST_BUS_MMC1\t\t35\n+#define RST_BUS_MMC2\t\t36\n+#define RST_BUS_MMC3\t\t37\n+#define RST_BUS_UFS_AHB\t\t38\n+#define RST_BUS_UFS_AXI\t\t39\n+#define RST_BUS_UFS_PHY\t\t40\n+#define RST_BUS_UFS_CORE\t41\n+#define RST_BUS_UART0\t\t42\n+#define RST_BUS_UART1\t\t43\n+#define RST_BUS_UART2\t\t44\n+#define RST_BUS_UART3\t\t45\n+#define RST_BUS_UART4\t\t46\n+#define RST_BUS_UART5\t\t47\n+#define RST_BUS_UART6\t\t48\n+#define RST_BUS_I2C0\t\t49\n+#define RST_BUS_I2C1\t\t50\n+#define RST_BUS_I2C2\t\t51\n+#define RST_BUS_I2C3\t\t52\n+#define RST_BUS_I2C4\t\t53\n+#define RST_BUS_I2C5\t\t54\n+#define RST_BUS_I2C6\t\t55\n+#define RST_BUS_I2C7\t\t56\n+#define RST_BUS_I2C8\t\t57\n+#define RST_BUS_I2C9\t\t58\n+#define RST_BUS_I2C10\t\t59\n+#define RST_BUS_I2C11\t\t60\n+#define RST_BUS_I2C12\t\t61\n+#define RST_BUS_SPI0\t\t62\n+#define RST_BUS_SPI1\t\t63\n+#define RST_BUS_SPI2\t\t64\n+#define RST_BUS_SPIF\t\t65\n+#define RST_BUS_SPI3\t\t66\n+#define RST_BUS_SPI4\t\t67\n+#define RST_BUS_GPADC0\t\t68\n+#define RST_BUS_THS0\t\t69\n+#define RST_BUS_IRRX\t\t70\n+#define RST_BUS_IRTX\t\t71\n+#define RST_BUS_LRADC\t\t72\n+#define RST_BUS_SGPIO\t\t73\n+#define RST_BUS_LPC\t\t74\n+#define RST_BUS_I2SPCM0\t\t75\n+#define RST_BUS_I2SPCM1\t\t76\n+#define RST_BUS_I2SPCM2\t\t77\n+#define RST_BUS_I2SPCM3\t\t78\n+#define RST_BUS_I2SPCM4\t\t79\n+#define RST_BUS_SPDIF\t\t80\n+#define RST_BUS_DMIC\t\t81\n+#define RST_USB_PHY0\t\t82\n+#define RST_BUS_OHCI0\t\t83\n+#define RST_BUS_EHCI0\t\t84\n+#define RST_BUS_OTG\t\t85\n+#define RST_USB_PHY1\t\t86\n+#define RST_BUS_OHCI1\t\t87\n+#define RST_BUS_EHCI1\t\t88\n+#define RST_BUS_USB2\t\t89\n+#define RST_BUS_PCIE_PWRUP\t90\n+#define RST_BUS_PCIE\t\t91\n+#define RST_BUS_SERDES\t\t92\n+#define RST_BUS_GMAC0\t\t93\n+#define RST_BUS_GMAC0_AXI\t94\n+#define RST_BUS_GMAC1\t\t95\n+#define RST_BUS_GMAC1_AXI\t96\n+#define RST_BUS_TCON_LCD0\t97\n+#define RST_BUS_TCON_LCD1\t98\n+#define RST_BUS_TCON_LCD2\t99\n+#define RST_BUS_LVDS0\t\t100\n+#define RST_BUS_LVDS1\t\t101\n+#define RST_BUS_DSI0\t\t102\n+#define RST_BUS_DSI1\t\t103\n+#define RST_BUS_TCON_TV0\t104\n+#define RST_BUS_TCON_TV1\t105\n+#define RST_BUS_EDP\t\t106\n+#define RST_BUS_HDMI_MAIN\t107\n+#define RST_BUS_HDMI_SUB\t108\n+#define RST_BUS_HDMI_HDCP\t109\n+#define RST_BUS_DPSS_TOP0\t110\n+#define RST_BUS_DPSS_TOP1\t111\n+#define RST_BUS_VIDEO_OUT0\t112\n+#define RST_BUS_VIDEO_OUT1\t113\n+#define RST_BUS_LEDC\t\t114\n+#define RST_BUS_DSC\t\t115\n+#define RST_BUS_CSI\t\t116\n+#define RST_BUS_VIDEO_IN\t117\n+#define RST_BUS_APB2JTAG\t118\n+\n+#endif /* _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_ */\ndiff --git a/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h b/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h\nnew file mode 100644\nindex 0000000000000..69fc7d405e1d1\n--- /dev/null\n+++ b/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h\n@@ -0,0 +1,23 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (C) 2026 Junhui Liu \u003cjunhui.liu@pigmoral.tech\u003e\n+ */\n+\n+#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_\n+#define _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_\n+\n+#define RST_BUS_R_TIMER\t\t0\n+#define RST_BUS_R_PWM\t\t1\n+#define RST_BUS_R_SPI\t\t2\n+#define RST_BUS_R_MSGBOX\t3\n+#define RST_BUS_R_UART0\t\t4\n+#define RST_BUS_R_UART1\t\t5\n+#define RST_BUS_R_I2C0\t\t6\n+#define RST_BUS_R_I2C1\t\t7\n+#define RST_BUS_R_I2C2\t\t8\n+#define RST_BUS_R_IR_RX\t\t9\n+#define RST_BUS_R_RTC\t\t10\n+#define RST_BUS_R_RISCV_CFG\t11\n+#define RST_BUS_R_CPUCFG\t12\n+\n+#endif /* _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_ */\n"
} |
| 2/1 | 2026/10/09 19:37 | agent | patch-evaluator |
0mModel:core Args: null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch adds clock control unit (CCU) drivers for the Allwinner A733 SoC (sun60i) and updates the internal sunxi-ng sigma-delta modulation helpers. All modified code is exclusive to Allwinner ARM/ARM64 SoCs (ARCH_SUNXI) and requires hardware/Device Tree nodes not present or emulated in standard amd64 QEMU/GCE environments. Because the target architecture is amd64, the modified code is structurally unreachable.",
"WorthFuzzing": false
}Instruction: You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.
IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.
================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.
- REACHABILITY IS THE PRIMARY GATE:
Fuzzing can only discover bugs in code that can actually execute in standard virtualized
environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
regardless of whether it adds assertions or complex logic.
- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
Patch authors routinely label changes as "cleanups", "refactorings", or state
"No functional change intended". Do NOT take these claims at face value.
Code refactorings that rearrange logic, introduce helper functions, or alter state management
in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
If reachable executable code is modified or refactored, it MUST be fuzzed.
- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
Even if the author believes the invariant always holds, fuzzing is essential to verify whether
an unusual sequence of operations can violate it.
================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:
- Non-kernel and non-executable changes:
* Modifications to Documentation/, comments, or spelling fixes.
* User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
that do not affect the compiled kernel image (vmlinux) or kernel modules.
* Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
that do not alter control flow or data structures.
* Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
* Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
* Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
physical PCI hot-unplug or manual sysfs driver unbinding.
* Code paths exclusive to architectures other than the target architecture.
================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
* Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
* Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
* Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
* Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).
================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:
- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
Do NOT list generic, ubiquitous functions called by almost every program in the corpus
(including, but not limited to: general memory allocators and deallocators, page fault
and trap handlers, or core synchronization primitives; this is not an exhaustive list).
Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
which severely dilutes fuzzing effort away from the actual changes.
- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
List functions that specifically implement the logic being added or altered, or direct API entrypoints
for the subsystem feature under review.
- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).
================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.
Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.
Prompt: Target architecture: amd64
For your convenience, here is the diff of the changes:
commit a9173363d90393b3f3686151263e63fb4dd6f778
Author: syz-cluster <triage@syzkaller.com>
Date: Fri Oct 9 19:37:25 2026 +0000
syz-cluster: applied patch under review
diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml
new file mode 100644
index 0000000000000..7c9068d3bbb05
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/allwinner,sun60i-a733-ccu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A733 Clock Control Unit
+
+maintainers:
+ - Junhui Liu <junhui.liu@pigmoral.tech>
+
+properties:
+ compatible:
+ enum:
+ - allwinner,sun60i-a733-ccu
+ - allwinner,sun60i-a733-r-ccu
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 4
+ maxItems: 7
+
+ clock-names:
+ minItems: 4
+ maxItems: 7
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun60i-a733-ccu
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz)
+ - description: Low Frequency Oscillator (usually at 32kHz)
+ - description: Internal Oscillator
+ - description: Low Frequency Oscillator fanout
+
+ clock-names:
+ items:
+ - const: hosc
+ - const: losc
+ - const: iosc
+ - const: losc-fanout
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun60i-a733-r-ccu
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz)
+ - description: Low Frequency Oscillator (usually at 32kHz)
+ - description: Internal Oscillator
+ - description: System 24MHz Clock
+ - description: Peripherals PLL 0 (200 MHz output)
+ - description: Peripherals PLL 0 (300 MHz output)
+ - description: Peripherals PLL 1 (300 MHz output)
+
+ clock-names:
+ items:
+ - const: hosc
+ - const: losc
+ - const: iosc
+ - const: sys-24m
+ - const: pll-periph0-200m
+ - const: pll-periph0-300m
+ - const: pll-periph1-300m
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@2002000 {
+ compatible = "allwinner,sun60i-a733-ccu";
+ reg = <0x02002000 0x2000>;
+ clocks = <&osc>, <&rtc 0>, <&rtc 2>, <&rtc 1>;
+ clock-names = "hosc", "losc", "iosc", "losc-fanout";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 6af2d020e03e9..cffa83056934a 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -67,6 +67,16 @@ config SUN55I_A523_R_CCU
default ARCH_SUNXI
depends on ARM64 || COMPILE_TEST
+config SUN60I_A733_CCU
+ tristate "Support for the Allwinner A733 CCU"
+ default ARCH_SUNXI
+ depends on ARM64 || COMPILE_TEST
+
+config SUN60I_A733_R_CCU
+ tristate "Support for the Allwinner A733 PRCM CCU"
+ default ARCH_SUNXI
+ depends on ARM64 || COMPILE_TEST
+
config SUN4I_A10_CCU
tristate "Support for the Allwinner A10/A20 CCU"
default ARCH_SUNXI
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index a1c4087d72417..3a39eb9287da0 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -36,6 +36,8 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o
obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o
obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o
obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o
+obj-$(CONFIG_SUN60I_A733_CCU) += sun60i-a733-ccu.o
+obj-$(CONFIG_SUN60I_A733_R_CCU) += sun60i-a733-r-ccu.o
obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o
obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o
@@ -64,6 +66,8 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o
sun55i-a523-ccu-y += ccu-sun55i-a523.o
sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o
sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o
+sun60i-a733-ccu-y += ccu-sun60i-a733.o
+sun60i-a733-r-ccu-y += ccu-sun60i-a733-r.o
sun4i-a10-ccu-y += ccu-sun4i-a10.o
sun5i-ccu-y += ccu-sun5i.o
sun6i-a31-ccu-y += ccu-sun6i-a31.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c
new file mode 100644
index 0000000000000..b8f6e8c6e5073
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 rengaomin@allwinnertech.com
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ * Based on the A523 CCU driver:
+ * Copyright (C) 2024 Arm Ltd.
+ *
+ * When secure boot is enabled, firmware must configure PRCM_SEC_SWITCH_REG
+ * to make the AHBS, APBS0 and APBS1 clock registers accessible to the
+ * non-secure world.
+ *
+ * S_TWD_BGR_REG is fixed to be a secure register regardless of whether
+ * secure boot is enabled, so it is not described here.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h>
+#include <dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+
+static const struct clk_parent_data r_ahb_parents[] = {
+ { .fw_name = "hosc" },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+ { .fw_name = "pll-periph0-200m" },
+ { .fw_name = "pll-periph0-300m" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX(r_ahb_clk, "r-ahb", r_ahb_parents, 0x000,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ 0);
+
+static const struct clk_parent_data r_apb_parents[] = {
+ { .fw_name = "hosc" },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+ { .fw_name = "pll-periph0-200m" },
+ { .fw_name = "sys-24m" },
+};
+
+static SUNXI_CCU_M_DATA_WITH_MUX(r_apb0_clk, "r-apb0", r_apb_parents, 0x00c,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ 0);
+
+static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1", r_apb_parents, 0x010,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ 0);
+
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", r_apb_parents, 0x100,
+ 1, 3, /* P */
+ 4, 3, /* mux */
+ BIT(0), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", r_apb_parents, 0x104,
+ 1, 3, /* P */
+ 4, 3, /* mux */
+ BIT(0), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2", r_apb_parents, 0x108,
+ 1, 3, /* P */
+ 4, 3, /* mux */
+ BIT(0), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer3, "r-timer3", r_apb_parents, 0x10c,
+ 1, 3, /* P */
+ 4, 3, /* mux */
+ BIT(0), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw, 0x11c, BIT(0), 0);
+
+static const struct clk_parent_data r_pwm_parents[] = {
+ { .fw_name = "hosc" },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+ { .fw_name = "sys-24m" },
+};
+static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwm_clk, "r-pwm", r_pwm_parents, 0x130,
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HW(bus_r_pwm_clk, "bus-r-pwm",
+ &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
+
+static const struct clk_parent_data r_spi_parents[] = {
+ { .fw_name = "hosc" },
+ { .fw_name = "pll-periph0-200m" },
+ { .fw_name = "pll-periph0-300m" },
+ { .fw_name = "pll-periph1-300m" },
+ { .fw_name = "sys-24m" },
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi", &r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox", &r_ahb_clk.common.hw, 0x17c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HW(bus_r_uart0_clk, "bus-r-uart0", &r_apb1_clk.common.hw, 0x18c, BIT(0), 0);
+static SUNXI_CCU_GATE_HW(bus_r_uart1_clk, "bus-r-uart1", &r_apb1_clk.common.hw, 0x18c, BIT(1), 0);
+
+static SUNXI_CCU_GATE_HW(bus_r_i2c0_clk, "bus-r-i2c0", &r_apb1_clk.common.hw, 0x19c, BIT(0), 0);
+static SUNXI_CCU_GATE_HW(bus_r_i2c1_clk, "bus-r-i2c1", &r_apb1_clk.common.hw, 0x19c, BIT(1), 0);
+static SUNXI_CCU_GATE_HW(bus_r_i2c2_clk, "bus-r-i2c2", &r_apb1_clk.common.hw, 0x19c, BIT(2), 0);
+
+static SUNXI_CCU_GATE_HW(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_clk.common.hw, 0x1ac, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HW(bus_r_tzma_clk, "bus-r-tzma", &r_apb0_clk.common.hw, 0x1b0, BIT(0), 0);
+static SUNXI_CCU_GATE_HW(bus_r_cpu_bist_clk, "bus-r-cpu-bist", &r_apb0_clk.common.hw,
+ 0x1bc, BIT(0), 0);
+
+static const struct clk_parent_data r_ir_rx_parents[] = {
+ { .fw_name = "losc" },
+ { .fw_name = "hosc" },
+ { .fw_name = "sys-24m" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx", r_ir_rx_parents, 0x1c0,
+ 0, 5, /* M */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_clk.common.hw, 0x1cc, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_clk.common.hw, 0x20c, BIT(0), 0);
+
+static const struct clk_parent_data r_riscv_parents[] = {
+ { .fw_name = "hosc" },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+};
+static SUNXI_CCU_MUX_DATA_WITH_GATE(r_riscv_clk, "r-riscv", r_riscv_parents, 0x210,
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HW(bus_r_riscv_clk, "bus-r-riscv", &r_apb0_clk.common.hw,
+ 0x21c, BIT(0), 0);
+static SUNXI_CCU_GATE_HW(bus_r_riscv_cfg_clk, "bus-r-riscv-cfg", &r_apb0_clk.common.hw,
+ 0x21c, BIT(1), 0);
+
+static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_clk.common.hw,
+ 0x22c, BIT(0), CLK_IS_CRITICAL);
+
+static struct ccu_common *sun60i_a733_r_ccu_clks[] = {
+ &r_ahb_clk.common,
+ &r_apb0_clk.common,
+ &r_apb1_clk.common,
+ &r_cpu_timer0.common,
+ &r_cpu_timer1.common,
+ &r_cpu_timer2.common,
+ &r_cpu_timer3.common,
+ &bus_r_timer_clk.common,
+ &r_pwm_clk.common,
+ &bus_r_pwm_clk.common,
+ &r_spi_clk.common,
+ &bus_r_spi_clk.common,
+ &bus_r_msgbox_clk.common,
+ &bus_r_uart0_clk.common,
+ &bus_r_uart1_clk.common,
+ &bus_r_i2c0_clk.common,
+ &bus_r_i2c1_clk.common,
+ &bus_r_i2c2_clk.common,
+ &bus_r_ppu_clk.common,
+ &bus_r_tzma_clk.common,
+ &bus_r_cpu_bist_clk.common,
+ &r_ir_rx_clk.common,
+ &bus_r_ir_rx_clk.common,
+ &bus_r_rtc_clk.common,
+ &r_riscv_clk.common,
+ &bus_r_riscv_clk.common,
+ &bus_r_riscv_cfg_clk.common,
+ &bus_r_cpucfg_clk.common,
+};
+
+static struct clk_hw_onecell_data sun60i_a733_r_hw_clks = {
+ .hws = {
+ [CLK_R_AHB] = &r_ahb_clk.common.hw,
+ [CLK_R_APB0] = &r_apb0_clk.common.hw,
+ [CLK_R_APB1] = &r_apb1_clk.common.hw,
+ [CLK_R_TIMER0] = &r_cpu_timer0.common.hw,
+ [CLK_R_TIMER1] = &r_cpu_timer1.common.hw,
+ [CLK_R_TIMER2] = &r_cpu_timer2.common.hw,
+ [CLK_R_TIMER3] = &r_cpu_timer3.common.hw,
+ [CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
+ [CLK_R_PWM] = &r_pwm_clk.common.hw,
+ [CLK_BUS_R_PWM] = &bus_r_pwm_clk.common.hw,
+ [CLK_R_SPI] = &r_spi_clk.common.hw,
+ [CLK_BUS_R_SPI] = &bus_r_spi_clk.common.hw,
+ [CLK_BUS_R_MSGBOX] = &bus_r_msgbox_clk.common.hw,
+ [CLK_BUS_R_UART0] = &bus_r_uart0_clk.common.hw,
+ [CLK_BUS_R_UART1] = &bus_r_uart1_clk.common.hw,
+ [CLK_BUS_R_I2C0] = &bus_r_i2c0_clk.common.hw,
+ [CLK_BUS_R_I2C1] = &bus_r_i2c1_clk.common.hw,
+ [CLK_BUS_R_I2C2] = &bus_r_i2c2_clk.common.hw,
+ [CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
+ [CLK_BUS_R_TZMA] = &bus_r_tzma_clk.common.hw,
+ [CLK_BUS_R_CPU_BIST] = &bus_r_cpu_bist_clk.common.hw,
+ [CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
+ [CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
+ [CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
+ [CLK_R_RISCV] = &r_riscv_clk.common.hw,
+ [CLK_BUS_R_RISCV] = &bus_r_riscv_clk.common.hw,
+ [CLK_BUS_R_RISCV_CFG] = &bus_r_riscv_cfg_clk.common.hw,
+ [CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
+ },
+ .num = CLK_BUS_R_CPUCFG + 1,
+};
+
+static const struct ccu_reset_map sun60i_a733_r_ccu_resets[] = {
+ [RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
+ [RST_BUS_R_PWM] = { 0x13c, BIT(16) },
+ [RST_BUS_R_SPI] = { 0x15c, BIT(16) },
+ [RST_BUS_R_MSGBOX] = { 0x17c, BIT(16) },
+ [RST_BUS_R_UART0] = { 0x18c, BIT(16) },
+ [RST_BUS_R_UART1] = { 0x18c, BIT(17) },
+ [RST_BUS_R_I2C0] = { 0x19c, BIT(16) },
+ [RST_BUS_R_I2C1] = { 0x19c, BIT(17) },
+ [RST_BUS_R_I2C2] = { 0x19c, BIT(18) },
+ [RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
+ [RST_BUS_R_RTC] = { 0x20c, BIT(16) },
+ [RST_BUS_R_RISCV_CFG] = { 0x21c, BIT(16) },
+ [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
+};
+
+static const struct sunxi_ccu_desc sun60i_a733_r_ccu_desc = {
+ .ccu_clks = sun60i_a733_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun60i_a733_r_ccu_clks),
+
+ .hw_clks = &sun60i_a733_r_hw_clks,
+
+ .resets = sun60i_a733_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun60i_a733_r_ccu_resets),
+};
+
+static int sun60i_a733_r_ccu_probe(struct platform_device *pdev)
+{
+ void __iomem *reg;
+
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
+
+ return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun60i_a733_r_ccu_desc);
+}
+
+static const struct of_device_id sun60i_a733_r_ccu_ids[] = {
+ { .compatible = "allwinner,sun60i-a733-r-ccu" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sun60i_a733_r_ccu_ids);
+
+static struct platform_driver sun60i_a733_r_ccu_driver = {
+ .probe = sun60i_a733_r_ccu_probe,
+ .driver = {
+ .name = "sun60i-a733-r-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun60i_a733_r_ccu_ids,
+ },
+};
+module_platform_driver(sun60i_a733_r_ccu_driver);
+
+MODULE_IMPORT_NS("SUNXI_CCU");
+MODULE_DESCRIPTION("Support for the Allwinner A733 PRCM CCU");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
new file mode 100644
index 0000000000000..cc2b229e2e6a6
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
@@ -0,0 +1,2422 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 rengaomin@allwinnertech.com
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ * Based on the A523 CCU driver:
+ * Copyright (C) 2023-2024 Arm Ltd.
+ *
+ * When secure boot is enabled, firmware must configure CCMU_SEC_SWITCH_REG
+ * to make the PLL, bus and MBUS clock registers accessible to the
+ * non-secure world.
+ *
+ * CPU_PERI_CLK_REG has no documented consumer, while NSI_CLK_REG has no
+ * known kernel consumer, so they are not modelled here.
+ *
+ * TODO: The real parents of some bus gates, including its-pcie0-aclk,
+ * msi-lite, npu, sgpio, lpc and i2spcm, are not documented in the
+ * manual. For now, follow the vendor BSP, which keeps them on hosc.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/allwinner,sun60i-a733-ccu.h>
+#include <dt-bindings/reset/allwinner,sun60i-a733-ccu.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_mux.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+
+/*
+ * The DCXO oscillator, the root of most of the clock tree, which may be
+ * 19.2MHz, 24MHz, or 26MHz.
+ */
+static const struct clk_parent_data hosc[] = {
+ { .fw_name = "hosc" }
+};
+
+/**************************************************************************
+ * PLLs *
+ **************************************************************************/
+
+/*
+ * Undocumented, taken from the vendor kernel.
+ * PLL_REF normalizes the DCXO frequency to a 24MHz reference for downstream
+ * PLLs.
+ */
+#define SUN60I_A733_PLL_REF_REG 0x000
+static struct ccu_nkmp pll_ref_clk = {
+ .enable = BIT(27),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT(8, 8),
+ .m = _SUNXI_CCU_DIV(16, 7), /* output divider */
+ .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_REF_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ref", hosc,
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+/*
+ * Most clock-defining macros expect an *array* of parent clocks, even if
+ * they do not contain a muxer to select between different parents.
+ * The macros ending in just _HW take a simple clock pointer, but then create
+ * a single-entry array out of that. The macros using _HWS take such an
+ * array (even when it is a single entry one), this avoids having those
+ * helper arrays created inside *every* clock definition.
+ * This means for every clock that is referenced more than once it is
+ * useful to create such a dummy array and use _HWS.
+ */
+static const struct clk_hw *pll_ref_hws[] = {
+ &pll_ref_clk.common.hw
+};
+
+/*
+ * There is a non-software-configurable mux selecting between the DCXO and the
+ * PLL_REF in hardware, whose output is fed to the sys-24M clock. Although both
+ * sys-24M and pll-ref are fixed at 24 MHz, define a 1:1 fixed factor clock to
+ * provide logical separation:
+ * - pll-ref is dedicated to feeding other PLLs
+ * - sys-24M serves as reference clock for downstream functional modules
+ */
+static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0);
+static const struct clk_hw *sys_24M_hws[] = {
+ &sys_24M_clk.hw
+};
+
+#define SUN60I_A733_PLL_DDR_REG 0x020
+static struct ccu_nkmp pll_ddr_clk = {
+ .enable = BIT(27),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(20, 3), /* output divider */
+ .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_DDR_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-ddr", pll_ref_hws,
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_GATE |
+ CLK_IS_CRITICAL),
+ },
+};
+
+/*
+ * There is no actual clock output with that frequency (2.4 GHz), instead it
+ * has multiple outputs with adjustable dividers from that base frequency.
+ * Model them separately as divider clocks based on that parent here.
+ */
+#define SUN60I_A733_PLL_PERIPH0_REG 0x0a0
+static struct ccu_nm pll_periph0_4x_clk = {
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_PERIPH0_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-periph0-4x",
+ pll_ref_hws, &ccu_nm_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+static const struct clk_hw *pll_periph0_4x_hws[] = {
+ &pll_periph0_4x_clk.common.hw
+};
+
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_2x_clk, "pll-periph0-2x",
+ pll_periph0_4x_hws,
+ SUN60I_A733_PLL_PERIPH0_REG,
+ 20, 3, BIT(27), 0);
+static const struct clk_hw *pll_periph0_2x_hws[] = {
+ &pll_periph0_2x_clk.common.hw
+};
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_800M_clk, "pll-periph0-800M",
+ pll_periph0_4x_hws,
+ SUN60I_A733_PLL_PERIPH0_REG,
+ 16, 3, BIT(26), 0);
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_480M_clk, "pll-periph0-480M",
+ pll_periph0_4x_hws,
+ SUN60I_A733_PLL_PERIPH0_REG,
+ 2, 3, BIT(25), 0);
+static const struct clk_hw *pll_periph0_480M_hws[] = {
+ &pll_periph0_480M_clk.common.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M",
+ pll_periph0_2x_hws, 2, 1, 0);
+static const struct clk_hw *pll_periph0_600M_hws[] = {
+ &pll_periph0_600M_clk.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M",
+ pll_periph0_2x_hws, 3, 1, 0);
+static const struct clk_hw *pll_periph0_400M_hws[] = {
+ &pll_periph0_400M_clk.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M",
+ pll_periph0_600M_hws, 2, 1, 0);
+static const struct clk_hw *pll_periph0_300M_hws[] = {
+ &pll_periph0_300M_clk.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M",
+ pll_periph0_400M_hws, 2, 1, 0);
+static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M",
+ pll_periph0_300M_hws, 2, 1, 0);
+static const struct clk_hw *pll_periph0_150M_hws[] = {
+ &pll_periph0_150M_clk.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M",
+ pll_periph0_480M_hws, 3, 1, 0);
+
+#define SUN60I_A733_PLL_PERIPH1_REG 0x0c0
+static struct ccu_nm pll_periph1_4x_clk = {
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_PERIPH1_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-periph1-4x",
+ pll_ref_hws, &ccu_nm_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+static const struct clk_hw *pll_periph1_4x_hws[] = {
+ &pll_periph1_4x_clk.common.hw
+};
+
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_2x_clk, "pll-periph1-2x",
+ pll_periph1_4x_hws,
+ SUN60I_A733_PLL_PERIPH1_REG,
+ 20, 3, BIT(27), 0);
+static const struct clk_hw *pll_periph1_2x_hws[] = {
+ &pll_periph1_2x_clk.common.hw
+};
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_800M_clk, "pll-periph1-800M",
+ pll_periph1_4x_hws,
+ SUN60I_A733_PLL_PERIPH1_REG,
+ 16, 3, BIT(26), 0);
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_480M_clk, "pll-periph1-480M",
+ pll_periph1_4x_hws,
+ SUN60I_A733_PLL_PERIPH1_REG,
+ 2, 3, BIT(25), 0);
+static const struct clk_hw *pll_periph1_480M_hws[] = {
+ &pll_periph1_480M_clk.common.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M",
+ pll_periph1_2x_hws, 2, 1, 0);
+static const struct clk_hw *pll_periph1_600M_hws[] = {
+ &pll_periph1_600M_clk.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M",
+ pll_periph1_2x_hws, 3, 1, 0);
+static const struct clk_hw *pll_periph1_400M_hws[] = {
+ &pll_periph1_400M_clk.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M",
+ pll_periph1_600M_hws, 2, 1, 0);
+static const struct clk_hw *pll_periph1_300M_hws[] = {
+ &pll_periph1_300M_clk.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M",
+ pll_periph1_400M_hws, 2, 1, 0);
+static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M",
+ pll_periph1_300M_hws, 2, 1, 0);
+static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M",
+ pll_periph1_480M_hws, 3, 1, 0);
+
+#define SUN60I_A733_PLL_GPU_REG 0x0e0
+static struct ccu_nkmp pll_gpu0_clk = {
+ .enable = BIT(27),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(20, 3), /* output divider */
+ .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_GPU_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-gpu0", pll_ref_hws,
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+#define SUN60I_A733_PLL_VIDEO0_REG 0x120
+static struct ccu_nm pll_video0_clk = {
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_VIDEO0_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-video0", pll_ref_hws,
+ &ccu_nm_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+static const struct clk_hw *pll_video0_hws[] = {
+ &pll_video0_clk.common.hw
+};
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video0_4x_clk, "pll-video0-4x",
+ pll_video0_hws, SUN60I_A733_PLL_VIDEO0_REG,
+ 20, 3, BIT(27), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video0_3x_clk, "pll-video0-3x",
+ pll_video0_hws, SUN60I_A733_PLL_VIDEO0_REG,
+ 16, 3, BIT(26), CLK_SET_RATE_PARENT);
+
+#define SUN60I_A733_PLL_VIDEO1_REG 0x140
+static struct ccu_nm pll_video1_clk = {
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_VIDEO1_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-video1", pll_ref_hws,
+ &ccu_nm_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+static const struct clk_hw *pll_video1_hws[] = {
+ &pll_video1_clk.common.hw
+};
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video1_4x_clk, "pll-video1-4x",
+ pll_video1_hws, SUN60I_A733_PLL_VIDEO1_REG,
+ 20, 3, BIT(27), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video1_3x_clk, "pll-video1-3x",
+ pll_video1_hws, SUN60I_A733_PLL_VIDEO1_REG,
+ 16, 3, BIT(26), CLK_SET_RATE_PARENT);
+
+#define SUN60I_A733_PLL_VIDEO2_REG 0x160
+static struct ccu_nm pll_video2_clk = {
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_VIDEO2_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-video2", pll_ref_hws,
+ &ccu_nm_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+static const struct clk_hw *pll_video2_hws[] = {
+ &pll_video2_clk.common.hw
+};
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video2_4x_clk, "pll-video2-4x",
+ pll_video2_hws, SUN60I_A733_PLL_VIDEO2_REG,
+ 20, 3, BIT(27), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_video2_3x_clk, "pll-video2-3x",
+ pll_video2_hws, SUN60I_A733_PLL_VIDEO2_REG,
+ 16, 3, BIT(26), CLK_SET_RATE_PARENT);
+
+#define SUN60I_A733_PLL_VE0_REG 0x220
+static struct ccu_nkmp pll_ve0_clk = {
+ .enable = BIT(27),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(20, 3), /* output divider */
+ .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_VE0_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-ve0", pll_ref_hws,
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+#define SUN60I_A733_PLL_VE1_REG 0x240
+static struct ccu_nkmp pll_ve1_clk = {
+ .enable = BIT(27),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(20, 3), /* output divider */
+ .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_VE1_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-ve1", pll_ref_hws,
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+/*
+ * PLL_AUDIO0 has a m1 divider in addition to the usual N, M factors.
+ * Since we only need some fixed frequency from this PLL (22.5792MHz x 4),
+ * ignore the divider and force it to 1 (encoded as 0), in the probe function
+ * below.
+ * The M factor must be an even number to produce a 50% duty cycle output.
+ */
+#define SUN60I_A733_PLL_AUDIO0_REG 0x260
+static struct ccu_sdm_setting pll_audio0_sdm_table[] = {
+ { .rate = 90316800, .pattern = 0xa002872b, .m = 20, .n = 75 }, /* 22.5792 * 4 */
+};
+
+static struct ccu_nm pll_audio0_4x_clk = {
+ .enable = BIT(27),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(16, 7),
+ .sdm = _SUNXI_CCU_SDM_DUAL_PAT(pll_audio0_sdm_table, 0,
+ 0x268, BIT(31),
+ 0x26c, BIT(27) | BIT(31)),
+ .common = {
+ .reg = SUN60I_A733_PLL_AUDIO0_REG,
+ .features = CCU_FEATURE_SIGMA_DELTA_MOD,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-audio0-4x", pll_ref_hws,
+ &ccu_nm_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+#define SUN60I_A733_PLL_AUDIO1_REG 0x280
+static struct ccu_nm pll_audio1_clk = {
+ .enable = BIT(27),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .sdm = {
+ /* PLL_AUDIO1 does not use fractional rates. */
+ .pat0_enable = BIT(31),
+ .pat0_reg = 0x288,
+ .pat1_enable = BIT(27) | BIT(31),
+ .pat1_reg = 0x28c,
+ },
+ .common = {
+ .reg = SUN60I_A733_PLL_AUDIO1_REG,
+ .features = CCU_FEATURE_SIGMA_DELTA_MOD,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-audio1", pll_ref_hws,
+ &ccu_nm_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+static const struct clk_hw *pll_audio1_hws[] = {
+ &pll_audio1_clk.common.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_audio1_div2_clk, "pll-audio1-div2",
+ pll_audio1_hws, 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio1_div5_clk, "pll-audio1-div5",
+ pll_audio1_hws, 5, 1, CLK_SET_RATE_PARENT);
+
+#define SUN60I_A733_PLL_NPU_REG 0x2a0
+static struct ccu_nkmp pll_npu_clk = {
+ .enable = BIT(27),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(20, 3), /* output divider */
+ .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_NPU_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-npu", pll_ref_hws,
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+#define SUN60I_A733_PLL_DE_REG 0x2e0
+static struct ccu_nm pll_de_clk = {
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .common = {
+ .reg = SUN60I_A733_PLL_DE_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-de", pll_ref_hws,
+ &ccu_nm_ops,
+ CLK_SET_RATE_GATE),
+ },
+};
+
+static const struct clk_hw *pll_de_hws[] = {
+ &pll_de_clk.common.hw
+};
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_de_4x_clk, "pll-de-4x", pll_de_hws,
+ SUN60I_A733_PLL_DE_REG,
+ 20, 3, BIT(27), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_HWS_WITH_GATE(pll_de_3x_clk, "pll-de-3x", pll_de_hws,
+ SUN60I_A733_PLL_DE_REG,
+ 16, 3, BIT(26), CLK_SET_RATE_PARENT);
+
+/**************************************************************************
+ * bus clocks *
+ **************************************************************************/
+
+static const struct clk_parent_data ahb_apb_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+ { .hw = &pll_periph0_600M_clk.hw },
+};
+
+static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb_parents, 0x500,
+ 0, 5, /* M */
+ 24, 2, /* mux */
+ 0);
+static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw };
+
+static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510,
+ 0, 5, /* M */
+ 24, 2, /* mux */
+ 0);
+static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
+
+static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518,
+ 0, 5, /* M */
+ 24, 2, /* mux */
+ 0);
+static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
+
+static const struct clk_parent_data apb_uart_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+ { .hw = &pll_periph0_600M_clk.hw },
+ { .hw = &pll_periph0_480M_clk.common.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uart", apb_uart_parents, 0x538,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ 0);
+static const struct clk_hw *apb_uart_hws[] = {
+ &apb_uart_clk.common.hw
+};
+
+static const struct clk_parent_data trace_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+ { .hw = &pll_periph0_300M_clk.hw },
+ { .hw = &pll_periph0_400M_clk.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0x540,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data gic_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "losc" },
+ { .hw = &pll_periph0_600M_clk.hw },
+ { .hw = &pll_periph0_480M_clk.common.hw },
+ { .hw = &pll_periph0_400M_clk.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gic_clk, "gic", gic_parents, 0x560,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_IS_CRITICAL);
+
+static SUNXI_CCU_GATE_DATA(bus_its_pcie0_aclk_clk, "bus-its-pcie0-aclk", hosc, 0x574, BIT(1), 0);
+
+static const struct clk_parent_data mbus_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_periph1_600M_clk.hw },
+ { .hw = &pll_ddr_clk.common.hw },
+ { .hw = &pll_periph1_480M_clk.common.hw },
+ { .hw = &pll_periph1_400M_clk.hw },
+ { .hw = &pll_npu_clk.common.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_IS_CRITICAL,
+ CCU_FEATURE_UPDATE_BIT);
+static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw };
+
+static SUNXI_CCU_GATE_HWS(mbus_iommu0_sys_clk, "mbus-iommu0-sys", mbus_hws, 0x58c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(apb_iommu0_sys_clk, "apb-iommu0-sys", apb0_hws, 0x58c, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(ahb_iommu0_sys_clk, "ahb-iommu0-sys", ahb_hws, 0x58c, BIT(2), 0);
+
+static SUNXI_CCU_GATE_DATA(bus_msi_lite0_clk, "bus-msi-lite0", hosc, 0x594, BIT(0), 0);
+static SUNXI_CCU_GATE_DATA(bus_msi_lite1_clk, "bus-msi-lite1", hosc, 0x59c, BIT(0), 0);
+static SUNXI_CCU_GATE_DATA(bus_msi_lite2_clk, "bus-msi-lite2", hosc, 0x5a4, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(mbus_iommu1_sys_clk, "mbus-iommu1-sys", mbus_hws, 0x5b4, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(apb_iommu1_sys_clk, "apb-iommu1-sys", apb0_hws, 0x5b4, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(ahb_iommu1_sys_clk, "ahb-iommu1-sys", ahb_hws, 0x5b4, BIT(2), 0);
+
+static SUNXI_CCU_GATE_HWS(ahb_ve_dec_clk, "ahb-ve-dec", ahb_hws,
+ 0x5c0, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(ahb_ve_enc_clk, "ahb-ve-enc", ahb_hws,
+ 0x5c0, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(ahb_vid_in_clk, "ahb-vid-in", ahb_hws,
+ 0x5c0, BIT(2), 0);
+static SUNXI_CCU_GATE_HWS(ahb_vid_cout0_clk, "ahb-vid-cout0", ahb_hws,
+ 0x5c0, BIT(3), 0);
+static SUNXI_CCU_GATE_HWS(ahb_vid_cout1_clk, "ahb-vid-cout1", ahb_hws,
+ 0x5c0, BIT(4), 0);
+static SUNXI_CCU_GATE_HWS(ahb_de_clk, "ahb-de", ahb_hws,
+ 0x5c0, BIT(5), 0);
+static SUNXI_CCU_GATE_HWS(ahb_npu_clk, "ahb-npu", ahb_hws,
+ 0x5c0, BIT(6), 0);
+static SUNXI_CCU_GATE_HWS(ahb_gpu0_clk, "ahb-gpu0", ahb_hws,
+ 0x5c0, BIT(7), 0);
+static SUNXI_CCU_GATE_HWS(ahb_serdes_clk, "ahb-serdes", ahb_hws,
+ 0x5c0, BIT(8), 0);
+static SUNXI_CCU_GATE_HWS(ahb_usb_sys_clk, "ahb-usb-sys", ahb_hws,
+ 0x5c0, BIT(9), 0);
+static SUNXI_CCU_GATE_HWS(ahb_msi_lite0_clk, "ahb-msi-lite0", ahb_hws,
+ 0x5c0, BIT(16), 0);
+
+/* This gate controls access to the storage controller MMIO registers. */
+static SUNXI_CCU_GATE_HWS(ahb_store_clk, "ahb-store", ahb_hws,
+ 0x5c0, BIT(24), 0);
+static const struct clk_hw *ahb_store_hws[] = { &ahb_store_clk.common.hw };
+
+/* Keep enabled for access to the CPUS domain registers. */
+static SUNXI_CCU_GATE_HWS(ahb_cpus_clk, "ahb-cpus", ahb_hws,
+ 0x5c0, BIT(28), CLK_IS_CRITICAL);
+
+static SUNXI_CCU_GATE_HWS(mbus_iommu0_clk, "mbus-iommu0", mbus_hws,
+ 0x5e0, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(mbus_iommu1_clk, "mbus-iommu1", mbus_hws,
+ 0x5e0, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(mbus_desys_clk, "mbus-desys", mbus_hws,
+ 0x5e0, BIT(11), 0);
+static SUNXI_CCU_GATE_HWS(mbus_ve_enc0_gate_clk, "mbus-ve-enc0-gate", mbus_hws,
+ 0x5e0, BIT(12), 0);
+static SUNXI_CCU_GATE_HWS(mbus_ve_dec0_gate_clk, "mbus-ve-dec0-gate", mbus_hws,
+ 0x5e0, BIT(14), 0);
+static SUNXI_CCU_GATE_HWS(mbus_gpu0_clk, "mbus-gpu0", mbus_hws,
+ 0x5e0, BIT(16), 0);
+static SUNXI_CCU_GATE_HWS(mbus_npu_clk, "mbus-npu", mbus_hws,
+ 0x5e0, BIT(18), 0);
+static SUNXI_CCU_GATE_HWS(mbus_vid_in_clk, "mbus-vid-in", mbus_hws,
+ 0x5e0, BIT(24), 0);
+static SUNXI_CCU_GATE_HWS(mbus_serdes_clk, "mbus-serdes", mbus_hws,
+ 0x5e0, BIT(28), 0);
+static SUNXI_CCU_GATE_HWS(mbus_msi_lite0_clk, "mbus-msi-lite0", mbus_hws,
+ 0x5e0, BIT(29), 0);
+
+/* Keep enabled for the storage controller DMA paths. */
+static SUNXI_CCU_GATE_HWS(mbus_store_clk, "mbus-store", mbus_hws,
+ 0x5e0, BIT(30), CLK_IS_CRITICAL);
+static const struct clk_hw *mbus_store_hws[] = { &mbus_store_clk.common.hw };
+
+static SUNXI_CCU_GATE_HWS(mbus_msi_lite2_clk, "mbus-msi-lite2", mbus_hws,
+ 0x5e0, BIT(31), 0);
+
+static SUNXI_CCU_GATE_HWS(mbus_dma0_clk, "mbus-dma0", mbus_hws,
+ 0x5e4, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(mbus_ve_enc0_clk, "mbus-ve-enc0", mbus_hws,
+ 0x5e4, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
+ 0x5e4, BIT(2), 0);
+static SUNXI_CCU_GATE_HWS(mbus_dma1_clk, "mbus-dma1", mbus_hws,
+ 0x5e4, BIT(3), 0);
+static SUNXI_CCU_GATE_HWS(mbus_nand0_clk, "mbus-nand0", mbus_store_hws,
+ 0x5e4, BIT(5), 0);
+static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
+ 0x5e4, BIT(8), 0);
+static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws,
+ 0x5e4, BIT(9), 0);
+static SUNXI_CCU_GATE_HWS(mbus_gmac0_clk, "mbus-gmac0", mbus_hws,
+ 0x5e4, BIT(11), 0);
+/* Undocumented, taken from the vendor kernel. */
+static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, "mbus-gmac1", mbus_hws,
+ 0x5e4, BIT(12), 0);
+static SUNXI_CCU_GATE_HWS(mbus_ve_dec0_clk, "mbus-ve-dec0", mbus_hws,
+ 0x5e4, BIT(18), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dma0_clk, "bus-dma0", ahb_hws,
+ 0x704, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_dma1_clk, "bus-dma1", ahb_hws,
+ 0x70c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws,
+ 0x724, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", ahb_hws,
+ 0x744, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb0_hws,
+ 0x784, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, "bus-pwm1", apb0_hws,
+ 0x78c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", sys_24M_hws,
+ 0x7a4, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws,
+ 0x7ac, BIT(0), 0);
+
+/**************************************************************************
+ * mod clocks with gates *
+ **************************************************************************/
+
+static const struct clk_parent_data timer_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "iosc" },
+ { .fw_name = "losc" },
+ { .hw = &pll_periph0_200M_clk.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer0_clk, "timer0", timer_parents, 0x800,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer1_clk, "timer1", timer_parents, 0x804,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer2_clk, "timer2", timer_parents, 0x808,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer3_clk, "timer3", timer_parents, 0x80c,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer4_clk, "timer4", timer_parents, 0x810,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer5_clk, "timer5", timer_parents, 0x814,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer6_clk, "timer6", timer_parents, 0x818,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer7_clk, "timer7", timer_parents, 0x81c,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer8_clk, "timer8", timer_parents, 0x820,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer9_clk, "timer9", timer_parents, 0x824,
+ 0, 3, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_timer_clk, "bus-timer", ahb_hws, 0x850, BIT(0), 0);
+
+/* Undocumented, taken from the vendor kernel. */
+static const struct clk_parent_data avs_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_MUX_DATA_WITH_GATE(avs_clk, "avs-clk", avs_parents, 0x880,
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_hw *de_parents[] = {
+ &pll_de_3x_clk.common.hw,
+ &pll_de_4x_clk.common.hw,
+ &pll_periph0_480M_clk.common.hw,
+ &pll_periph0_400M_clk.hw,
+ &pll_periph0_300M_clk.hw,
+ &pll_video0_4x_clk.common.hw,
+ &pll_video2_4x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(de0_clk, "de0", de_parents, 0xa00,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE_HWS(bus_de0_clk, "bus-de0", ahb_hws, 0xa04, BIT(0), 0);
+
+static const struct clk_hw *di_parents[] = {
+ &pll_periph0_600M_clk.hw,
+ &pll_periph0_480M_clk.common.hw,
+ &pll_periph0_400M_clk.hw,
+ &pll_video0_4x_clk.common.hw,
+ &pll_video2_4x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0xa20,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", ahb_hws, 0xa24, BIT(0), 0);
+
+static const struct clk_hw *g2d_parents[] = {
+ &pll_periph0_400M_clk.hw,
+ &pll_periph0_300M_clk.hw,
+ &pll_video0_4x_clk.common.hw,
+ &pll_video1_4x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0xa40,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws, 0xa44, BIT(0), 0);
+
+static const struct clk_hw *eink_parents[] = {
+ &pll_periph0_480M_clk.common.hw,
+ &pll_periph0_400M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_clk, "eink", eink_parents, 0xa60,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+
+static const struct clk_hw *eink_panel_parents[] = {
+ &pll_video0_4x_clk.common.hw,
+ &pll_video0_3x_clk.common.hw,
+ &pll_video1_4x_clk.common.hw,
+ &pll_video1_3x_clk.common.hw,
+ &pll_periph0_300M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, "eink-panel", eink_panel_parents, 0xa64,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE_HWS(bus_eink_clk, "bus-eink", ahb_hws, 0xa6c, BIT(0), 0);
+
+static const struct clk_hw *ve_enc_parents[] = {
+ &pll_ve0_clk.common.hw,
+ &pll_ve1_clk.common.hw,
+ &pll_periph0_800M_clk.common.hw,
+ &pll_periph0_600M_clk.hw,
+ &pll_periph0_480M_clk.common.hw,
+ &pll_de_3x_clk.common.hw,
+ &pll_npu_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_enc0_clk, "ve-enc0", ve_enc_parents, 0xa80,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+
+static const struct clk_hw *ve_dec_parents[] = {
+ &pll_ve1_clk.common.hw,
+ &pll_ve0_clk.common.hw,
+ &pll_periph0_800M_clk.common.hw,
+ &pll_periph0_600M_clk.hw,
+ &pll_periph0_480M_clk.common.hw,
+ &pll_de_3x_clk.common.hw,
+ &pll_npu_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec0_clk, "ve-dec0", ve_dec_parents, 0xa88,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_ve_enc0_clk, "bus-ve-enc0", ahb_hws, 0xa8c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_ve_dec0_clk, "bus-ve-dec0", ahb_hws, 0xa8c, BIT(2), 0);
+
+static const struct clk_hw *ce_parents[] = {
+ &sys_24M_clk.hw,
+ &pll_periph0_400M_clk.hw,
+ &pll_periph0_600M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0xac0,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws, 0xac4, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, "bus-ce-sys", ahb_hws, 0xac4, BIT(1), 0);
+
+static const struct clk_hw *npu_parents[] = {
+ &pll_npu_clk.common.hw,
+ &pll_periph0_800M_clk.common.hw,
+ &pll_periph0_600M_clk.hw,
+ &pll_periph0_480M_clk.common.hw,
+ &pll_ve0_clk.common.hw,
+ &pll_ve1_clk.common.hw,
+ &pll_de_3x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0xb00,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_DATA(bus_npu_clk, "bus-npu", hosc, 0xb04, BIT(0), 0);
+
+/*
+ * GPU_CLK = ClockSource * ((16 - M) / 16)
+ * Here we use a div_table to select M values that result in integer divisors.
+ */
+static struct clk_div_table gpu_div_table[] = {
+ { .val = 0, .div = 1 },
+ { .val = 8, .div = 2 },
+ { .val = 12, .div = 4 },
+ { .val = 14, .div = 8 },
+ { .val = 15, .div = 16 },
+ { /* sentinel */ },
+};
+static const struct clk_parent_data gpu_parents[] = {
+ { .hw = &pll_gpu0_clk.common.hw, },
+ { .hw = &pll_periph0_800M_clk.common.hw, },
+ { .hw = &pll_periph0_600M_clk.hw, },
+ { .hw = &pll_periph0_400M_clk.hw, },
+ { .hw = &pll_periph0_300M_clk.hw, },
+ { .hw = &pll_periph0_200M_clk.hw, },
+};
+static struct ccu_div gpu0_clk = {
+ .enable = BIT(31),
+ .div = _SUNXI_CCU_DIV_TABLE(0, 4, gpu_div_table),
+ .mux = _SUNXI_CCU_MUX(24, 3),
+ .common = {
+ .reg = 0xb20,
+ .features = CCU_FEATURE_UPDATE_BIT,
+ .hw.init = CLK_HW_INIT_PARENTS_DATA("gpu0", gpu_parents,
+ &ccu_div_ops, 0),
+ }
+};
+static SUNXI_CCU_GATE_HWS(bus_gpu0_clk, "bus-gpu0", ahb_hws, 0xb24, BIT(0), 0);
+
+static const struct clk_parent_data dram_parents[] = {
+ { .hw = &pll_ddr_clk.common.hw, },
+ { .hw = &pll_periph0_800M_clk.common.hw, },
+ { .hw = &pll_periph0_600M_clk.hw, },
+ { .hw = &pll_de_clk.common.hw, },
+ { .hw = &pll_npu_clk.common.hw, },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram0_clk, "dram0", dram_parents, 0xc00,
+ 0, 4, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_IS_CRITICAL,
+ CCU_FEATURE_UPDATE_BIT);
+static SUNXI_CCU_GATE_HWS(bus_dram0_clk, "bus-dram0", ahb_hws, 0xc0c,
+ BIT(0), CLK_IS_CRITICAL);
+
+static const struct clk_parent_data nand_mmc_parents[] = {
+ { .hw = &sys_24M_clk.hw, },
+ { .hw = &pll_periph0_400M_clk.hw, },
+ { .hw = &pll_periph0_300M_clk.hw, },
+ { .hw = &pll_periph1_400M_clk.hw, },
+ { .hw = &pll_periph1_300M_clk.hw, },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk0_clk, "nand0-clk0", nand_mmc_parents, 0xc80,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk1_clk, "nand0-clk1", nand_mmc_parents, 0xc84,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_nand0_clk, "bus-nand0", ahb_store_hws, 0xc8c, BIT(0), 0);
+
+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents, 0xd00,
+ 0, 5, /* M */
+ 8, 5, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 2, /* post div */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_store_hws, 0xd0c, BIT(0), 0);
+
+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents, 0xd10,
+ 0, 5, /* M */
+ 8, 5, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 2, /* post div */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_store_hws, 0xd1c, BIT(0), 0);
+
+static const struct clk_parent_data mmc2_mmc3_parents[] = {
+ { .hw = &sys_24M_clk.hw, },
+ { .hw = &pll_periph0_800M_clk.common.hw },
+ { .hw = &pll_periph0_600M_clk.hw },
+ { .hw = &pll_periph1_800M_clk.common.hw },
+ { .hw = &pll_periph1_600M_clk.hw },
+};
+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_mmc3_parents, 0xd20,
+ 0, 5, /* M */
+ 8, 5, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 2, /* post div */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_store_hws, 0xd2c, BIT(0), 0);
+
+static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_parents, 0xd30,
+ 0, 5, /* M */
+ 8, 5, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 2, /* post div */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_mmc3_clk, "bus-mmc3", ahb_store_hws, 0xd3c, BIT(0), 0);
+
+static const struct clk_hw *ufs_axi_parents[] = {
+ &pll_periph0_300M_clk.hw,
+ &pll_periph0_200M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ufs_axi_clk, "ufs-axi", ufs_axi_parents, 0xd80,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data ufs_cfg_parents[] = {
+ { .hw = &pll_periph0_480M_clk.common.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, "ufs-cfg", ufs_cfg_parents, 0xd84,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_ufs_clk, "bus-ufs", ahb_store_hws, 0xd8c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb_uart_hws, 0xe00, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb_uart_hws, 0xe04, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb_uart_hws, 0xe08, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb_uart_hws, 0xe0c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb_uart_hws, 0xe10, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb_uart_hws, 0xe14, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart6_clk, "bus-uart6", apb_uart_hws, 0xe18, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0xe80, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0xe84, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 0xe88, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0xe8c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws, 0xe90, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, "bus-i2c5", apb1_hws, 0xe94, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c6_clk, "bus-i2c6", apb1_hws, 0xe98, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c7_clk, "bus-i2c7", apb1_hws, 0xe9c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c8_clk, "bus-i2c8", apb1_hws, 0xea0, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c9_clk, "bus-i2c9", apb1_hws, 0xea4, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c10_clk, "bus-i2c10", apb1_hws, 0xea8, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c11_clk, "bus-i2c11", apb1_hws, 0xeac, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c12_clk, "bus-i2c12", apb1_hws, 0xeb0, BIT(0), 0);
+
+static const struct clk_parent_data spi_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_periph0_300M_clk.hw },
+ { .hw = &pll_periph0_200M_clk.hw },
+ { .hw = &pll_periph1_300M_clk.hw },
+ { .hw = &pll_periph1_200M_clk.hw },
+ { .hw = &pll_periph0_480M_clk.common.hw },
+ { .hw = &pll_periph1_480M_clk.common.hw },
+ { .fw_name = "hosc"},
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0xf00,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_store_hws, 0xf04, BIT(0), 0);
+
+static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0xf08,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_store_hws, 0xf0c, BIT(0), 0);
+
+static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0xf10,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_store_hws, 0xf14, BIT(0), 0);
+
+static const struct clk_parent_data spif_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_periph0_400M_clk.hw },
+ { .hw = &pll_periph0_300M_clk.hw },
+ { .hw = &pll_periph1_400M_clk.hw },
+ { .hw = &pll_periph1_300M_clk.hw },
+ { .hw = &pll_periph0_160M_clk.hw },
+ { .hw = &pll_periph1_160M_clk.hw },
+ { .fw_name = "hosc"},
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, "spif", spif_parents, 0xf18,
+ 0, 5, /* M */
+ 8, 5, /* P */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_spif_clk, "bus-spif", ahb_store_hws, 0xf1c, BIT(0), 0);
+
+static SUNXI_CCU_DUALDIV_MUX_GATE(spi3_clk, "spi3", spi_parents, 0xf20,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_spi3_clk, "bus-spi3", ahb_store_hws, 0xf24, BIT(0), 0);
+
+/* Undocumented, taken from the vendor kernel. */
+static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_spi4_clk, "bus-spi4", ahb_store_hws, 0xf2c, BIT(0), 0);
+
+static const struct clk_parent_data gpadc0_24m_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "hosc"},
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc0_24m_clk, "gpadc0-24m", gpadc0_24m_parents, 0xfc0,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_gpadc0_clk, "bus-gpadc0", ahb_hws, 0xfc4, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_ths0_clk, "bus-ths0", apb0_hws, 0xfe4, BIT(0), 0);
+
+static const struct clk_parent_data irrx_parents[] = {
+ { .fw_name = "losc"},
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "hosc"},
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, "irrx", irrx_parents, 0x1000,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_irrx_clk, "bus-irrx", apb0_hws, 0x1004, BIT(0), 0);
+
+static const struct clk_parent_data irtx_parents[] = {
+ { .fw_name = "losc"},
+ { .hw = &pll_periph1_600M_clk.hw },
+ { .fw_name = "hosc"},
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, "irtx", irtx_parents, 0x1008,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_irtx_clk, "bus-irtx", apb0_hws, 0x100c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0x1024, BIT(0), 0);
+
+/* Undocumented, taken from the vendor kernel. */
+static const struct clk_parent_data sgpio_parents[] = {
+ { .fw_name = "losc"},
+ { .hw = &sys_24M_clk.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, "sgpio", sgpio_parents, 0x1060,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_DATA(bus_sgpio_clk, "bus-sgpio", hosc, 0x1064, BIT(0), 0);
+
+/* Undocumented, taken from the vendor kernel. */
+static const struct clk_hw *lpc_parents[] = {
+ &pll_video0_3x_clk.common.hw,
+ &pll_video1_3x_clk.common.hw,
+ &pll_video2_3x_clk.common.hw,
+ &pll_periph0_300M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, "lpc", lpc_parents, 0x1080,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_DATA(bus_lpc_clk, "bus-lpc", hosc, 0x1084, BIT(0), 0);
+
+static const struct clk_hw *i2spcm_parents[] = {
+ &pll_audio0_4x_clk.common.hw,
+ &pll_audio1_div2_clk.hw,
+ &pll_audio1_div5_clk.hw,
+ &pll_periph0_200M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm0_clk, "i2spcm0", i2spcm_parents, 0x1200,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_DATA(bus_i2spcm0_clk, "bus-i2spcm0", hosc, 0x120c, BIT(0), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm1_clk, "i2spcm1", i2spcm_parents, 0x1210,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_DATA(bus_i2spcm1_clk, "bus-i2spcm1", hosc, 0x121c, BIT(0), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_clk, "i2spcm2", i2spcm_parents, 0x1220,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_hw *i2spcm2_asrc_parents[] = {
+ &pll_audio0_4x_clk.common.hw,
+ &pll_audio1_div2_clk.hw,
+ &pll_audio1_div5_clk.hw,
+ &pll_periph0_300M_clk.hw,
+ &pll_periph1_300M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_asrc_clk, "i2spcm2_asrc", i2spcm2_asrc_parents, 0x1224,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE_DATA(bus_i2spcm2_clk, "bus-i2spcm2", hosc, 0x122c, BIT(0), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm3_clk, "i2spcm3", i2spcm_parents, 0x1230,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_DATA(bus_i2spcm3_clk, "bus-i2spcm3", hosc, 0x123c, BIT(0), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, "i2spcm4", i2spcm_parents, 0x1240,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_DATA(bus_i2spcm4_clk, "bus-i2spcm4", hosc, 0x124c, BIT(0), 0);
+
+static const struct clk_hw *spdif_tx_parents[] = {
+ &pll_audio0_4x_clk.common.hw,
+ &pll_audio1_div2_clk.hw,
+ &pll_audio1_div5_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", spdif_tx_parents, 0x1280,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_hw *spdif_rx_parents[] = {
+ &pll_periph0_200M_clk.hw,
+ &pll_periph0_300M_clk.hw,
+ &pll_periph0_400M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0x1284,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb1_hws, 0x128c, BIT(0), 0);
+
+static const struct clk_hw *dmic_parents[] = {
+ &pll_audio0_4x_clk.common.hw,
+ &pll_audio1_div2_clk.hw,
+ &pll_audio1_div5_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_parents, 0x12c0,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb1_hws, 0x12cc, BIT(0), 0);
+
+/*
+ * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is
+ * a 2x multiplier from pll-ref synchronized by pll-periph0, and is also used by
+ * the OHCI module.
+ */
+static const struct clk_parent_data usb_ohci_parents[] = {
+ { .hw = &pll_periph0_4x_clk.common.hw },
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+};
+static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = {
+ { .index = 0, .div = 200 },
+ { .index = 1, .div = 2 },
+};
+
+static struct ccu_mux usb_ohci0_clk = {
+ .enable = BIT(31),
+ .mux = {
+ .shift = 24,
+ .width = 2,
+ .fixed_predivs = usb_ohci_predivs,
+ .n_predivs = ARRAY_SIZE(usb_ohci_predivs),
+ },
+ .common = {
+ .reg = 0x1300,
+ .features = CCU_FEATURE_FIXED_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0", usb_ohci_parents,
+ &ccu_mux_ops, 0),
+ },
+};
+static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0x1304, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", ahb_hws, 0x1304, BIT(4), 0);
+static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0x1304, BIT(8), 0);
+
+static struct ccu_mux usb_ohci1_clk = {
+ .enable = BIT(31),
+ .mux = {
+ .shift = 24,
+ .width = 2,
+ .fixed_predivs = usb_ohci_predivs,
+ .n_predivs = ARRAY_SIZE(usb_ohci_predivs),
+ },
+ .common = {
+ .reg = 0x1308,
+ .features = CCU_FEATURE_FIXED_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1", usb_ohci_parents,
+ &ccu_mux_ops, 0),
+ },
+};
+static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0x130c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", ahb_hws, 0x130c, BIT(4), 0);
+
+static const struct clk_parent_data usb01_ref_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_MUX_DATA(usb01_ref_clk, "usb01-ref", usb01_ref_parents, 0x1340, 24, 3, 0);
+
+static SUNXI_CCU_MUX_DATA(usb2_u2_ref_clk, "usb2-u2-ref", usb01_ref_parents, 0x1348, 24, 3, 0);
+
+static const struct clk_parent_data usb2_suspend_parents[] = {
+ { .fw_name = "losc" },
+ { .hw = &sys_24M_clk.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_suspend_clk, "usb2-suspend", usb2_suspend_parents,
+ 0x1350,
+ 0, 5, /* M */
+ 24, 1, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data usb2_mf_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_periph0_300M_clk.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_mf_clk, "usb2-mf", usb2_mf_parents,
+ 0x1354,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data usb2_u3_utmi_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_periph0_300M_clk.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u3_utmi_clk, "usb2-u3-utmi", usb2_u3_utmi_parents,
+ 0x1360,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data usb2_u2_pipe_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_periph0_480M_clk.common.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u2_pipe_clk, "usb2-u2-pipe", usb2_u2_pipe_parents,
+ 0x1364,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data pcie_aux_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "losc" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux", pcie_aux_parents, 0x1380,
+ 0, 5, /* M */
+ 24, 1, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_hw *pcie_axi_slv_parents[] = {
+ &pll_periph0_600M_clk.hw,
+ &pll_periph0_480M_clk.common.hw,
+ &pll_periph0_400M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(pcie_axi_slv_clk, "pcie-axi-slv", pcie_axi_slv_parents, 0x1384,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_hw *serdes_phy_parents[] = {
+ &sys_24M_clk.hw,
+ &pll_periph0_600M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(serdes_phy_clk, "serdes-phy", serdes_phy_parents, 0x13c0,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data gmac_ptp_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_periph0_200M_clk.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gmac_ptp_clk, "gmac-ptp", gmac_ptp_parents, 0x1400,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_M_HWS_WITH_GATE(gmac0_phy_clk, "gmac0-phy", pll_periph0_150M_hws, 0x1410,
+ 0, 5, /* M */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_gmac0_clk, "bus-gmac0", ahb_hws, 0x141c, BIT(0), 0);
+
+/* Undocumented, taken from the vendor kernel. */
+static SUNXI_CCU_M_HWS_WITH_GATE(gmac1_phy_clk, "gmac1-phy", pll_periph0_150M_hws, 0x1420,
+ 0, 5, /* M */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_gmac1_clk, "bus-gmac1", ahb_hws, 0x142c, BIT(0), 0);
+
+static const struct clk_hw *tcon_lcd_parents[] = {
+ &pll_video0_4x_clk.common.hw,
+ &pll_video1_4x_clk.common.hw,
+ &pll_video2_4x_clk.common.hw,
+ &pll_periph0_2x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_lcd_parents, 0x1500,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", ahb_hws, 0x1504, BIT(0), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_lcd_parents, 0x1508,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, "bus-tcon-lcd1", ahb_hws, 0x150c, BIT(0), 0);
+
+/* Undocumented, taken from the vendor kernel. */
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2", tcon_lcd_parents, 0x1510,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, "bus-tcon-lcd2", ahb_hws, 0x1514, BIT(0), 0);
+
+static const struct clk_hw *dsi_parents[] = {
+ &sys_24M_clk.hw,
+ &pll_periph0_200M_clk.hw,
+ &pll_periph0_150M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi0_clk, "dsi0", dsi_parents, 0x1580,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_dsi0_clk, "bus-dsi0", ahb_hws, 0x1584, BIT(0), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, "dsi1", dsi_parents, 0x1588,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_dsi1_clk, "bus-dsi1", ahb_hws, 0x158c, BIT(0), 0);
+
+static const struct clk_hw *combphy_parents[] = {
+ &pll_video0_4x_clk.common.hw,
+ &pll_video1_4x_clk.common.hw,
+ &pll_video2_4x_clk.common.hw,
+ &pll_periph0_2x_clk.common.hw,
+ &pll_video0_3x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy0_clk, "combphy0", combphy_parents, 0x15c0,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, "combphy1", combphy_parents, 0x15c4,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, "bus-tcon-tv0", ahb_hws, 0x1604, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, "bus-tcon-tv1", ahb_hws, 0x160c, BIT(0), 0);
+
+static const struct clk_hw *edp_tv_parents[] = {
+ &pll_video0_4x_clk.common.hw,
+ &pll_video1_4x_clk.common.hw,
+ &pll_video2_4x_clk.common.hw,
+ &pll_periph0_2x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, "edp-tv", edp_tv_parents, 0x1640,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_edp_tv_clk, "bus-edp-tv", ahb_hws, 0x164c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pll_periph0_2x_hws, 0x1680,
+ BIT(30), /* gate */
+ 36621, /* pre div */
+ 0);
+
+static const struct clk_parent_data hdmi_cec_parents[] = {
+ { .fw_name = "losc" },
+ { .hw = &hdmi_cec_32k_clk.common.hw },
+};
+static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0x1680,
+ 24, 1, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data hdmi_tv_parents[] = {
+ { .hw = &pll_video0_4x_clk.common.hw },
+ { .hw = &pll_video1_4x_clk.common.hw },
+ { .hw = &pll_video2_4x_clk.common.hw },
+ { .hw = &pll_periph0_2x_clk.common.hw },
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, "hdmi-tv", hdmi_tv_parents, 0x1684,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_hdmi_tv_clk, "bus-hdmi-tv", ahb_hws, 0x168c, BIT(0), 0);
+
+static const struct clk_parent_data hdmi_sfr_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, "hdmi-sfr", hdmi_sfr_parents, 0x1690,
+ 24, 1, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE_HWS(hdcp_esm_clk, "hdcp-esm", pll_periph0_300M_hws, 0x1694, BIT(31), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dpss_top0_clk, "bus-dpss-top0", ahb_hws, 0x16c4, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_dpss_top1_clk, "bus-dpss-top1", ahb_hws, 0x16cc, BIT(0), 0);
+
+static const struct clk_parent_data ledc_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_periph0_600M_clk.hw },
+ { .fw_name = "hosc" },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ledc_parents, 0x1700,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", apb0_hws, 0x1704, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dsc_clk, "bus-dsc", ahb_hws, 0x1744, BIT(0), 0);
+
+static const struct clk_parent_data csi_master_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .hw = &pll_video0_4x_clk.common.hw },
+ { .hw = &pll_video0_3x_clk.common.hw },
+ { .hw = &pll_video1_4x_clk.common.hw },
+ { .hw = &pll_video1_3x_clk.common.hw },
+ { .hw = &pll_video2_4x_clk.common.hw },
+ { .hw = &pll_video2_3x_clk.common.hw },
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master0_clk, "csi_master0", csi_master_parents, 0x1800,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master1_clk, "csi_master1", csi_master_parents, 0x1804,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master2_clk, "csi_master2", csi_master_parents, 0x1808,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_hw *csi_parents[] = {
+ &pll_video2_4x_clk.common.hw,
+ &pll_de_4x_clk.common.hw,
+ &pll_periph0_480M_clk.common.hw,
+ &pll_periph0_400M_clk.hw,
+ &pll_periph0_600M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, "csi", csi_parents, 0x1840,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws, 0x1844, BIT(0), 0);
+
+static const struct clk_hw *isp_parents[] = {
+ &pll_video2_4x_clk.common.hw,
+ &pll_periph0_480M_clk.common.hw,
+ &pll_periph0_400M_clk.hw,
+ &pll_periph0_600M_clk.hw,
+ &pll_video0_4x_clk.common.hw,
+ &pll_video1_4x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0x1860,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE_DATA(res_dcap_24m_clk, "res-dcap-24m", hosc, 0x1a00, BIT(3), 0);
+
+static const struct clk_parent_data apb2jtag_parents[] = {
+ { .hw = &sys_24M_clk.hw },
+ { .fw_name = "losc" },
+ { .fw_name = "iosc" },
+ { .hw = &pll_periph0_480M_clk.common.hw },
+ { .hw = &pll_periph1_480M_clk.common.hw },
+ { .hw = &pll_periph0_200M_clk.hw },
+ { .hw = &pll_periph1_200M_clk.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(apb2jtag_clk, "apb2jtag", apb2jtag_parents, 0x1c00,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE_HWS(fanout_24M_clk, "fanout-24M", sys_24M_hws, 0x1f30, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_12M_clk, "fanout-12M", sys_24M_hws, 0x1f30,
+ BIT(1), 2, 0);
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_480M_hws, 0x1f30,
+ BIT(2), 30, 0);
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_2x_hws, 0x1f30,
+ BIT(3), 48, 0);
+
+static const struct clk_parent_data fanout_27M_parents[] = {
+ { .hw = &pll_video0_4x_clk.common.hw },
+ { .hw = &pll_video1_4x_clk.common.hw },
+ { .hw = &pll_video2_4x_clk.common.hw },
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0x1f34,
+ 0, 5, /* M */
+ 8, 5, /* N */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data fanout_pclk_parents[] = {
+ { .hw = &apb0_clk.common.hw }
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk", fanout_pclk_parents, 0x1f38,
+ 0, 5, /* M */
+ 5, 5, /* N */
+ 0, 0, /* no mux */
+ BIT(31), /* gate */
+ 0);
+
+static const struct clk_parent_data fanout_parents[] = {
+ { .fw_name = "losc-fanout" },
+ { .hw = &fanout_12M_clk.common.hw, },
+ { .hw = &fanout_16M_clk.common.hw, },
+ { .hw = &fanout_24M_clk.common.hw, },
+ { .hw = &fanout_25M_clk.common.hw, },
+ { .hw = &fanout_27M_clk.common.hw, },
+ { .hw = &fanout_pclk_clk.common.hw, },
+};
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0x1f3c,
+ 0, 3, /* mux */
+ BIT(21), /* gate */
+ 0);
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0x1f3c,
+ 3, 3, /* mux */
+ BIT(22), /* gate */
+ 0);
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0x1f3c,
+ 6, 3, /* mux */
+ BIT(23), /* gate */
+ 0);
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout3_clk, "fanout3", fanout_parents, 0x1f3c,
+ 9, 3, /* mux */
+ BIT(24), /* gate */
+ 0);
+
+/*
+ * Contains all clocks that are controlled by a hardware register. They
+ * have a (sunxi) .common member, which needs to be initialised by the common
+ * sunxi CCU code, to be filled with the MMIO base address and the shared lock.
+ */
+static struct ccu_common *sun60i_a733_ccu_clks[] = {
+ &pll_ref_clk.common,
+ &pll_ddr_clk.common,
+ &pll_periph0_4x_clk.common,
+ &pll_periph0_2x_clk.common,
+ &pll_periph0_800M_clk.common,
+ &pll_periph0_480M_clk.common,
+ &pll_periph1_4x_clk.common,
+ &pll_periph1_2x_clk.common,
+ &pll_periph1_800M_clk.common,
+ &pll_periph1_480M_clk.common,
+ &pll_gpu0_clk.common,
+ &pll_video0_clk.common,
+ &pll_video0_4x_clk.common,
+ &pll_video0_3x_clk.common,
+ &pll_video1_clk.common,
+ &pll_video1_4x_clk.common,
+ &pll_video1_3x_clk.common,
+ &pll_video2_clk.common,
+ &pll_video2_4x_clk.common,
+ &pll_video2_3x_clk.common,
+ &pll_ve0_clk.common,
+ &pll_ve1_clk.common,
+ &pll_audio0_4x_clk.common,
+ &pll_audio1_clk.common,
+ &pll_npu_clk.common,
+ &pll_de_clk.common,
+ &pll_de_4x_clk.common,
+ &pll_de_3x_clk.common,
+ &ahb_clk.common,
+ &apb0_clk.common,
+ &apb1_clk.common,
+ &apb_uart_clk.common,
+ &trace_clk.common,
+ &gic_clk.common,
+ &bus_its_pcie0_aclk_clk.common,
+ &mbus_clk.common,
+ &mbus_iommu0_sys_clk.common,
+ &apb_iommu0_sys_clk.common,
+ &ahb_iommu0_sys_clk.common,
+ &bus_msi_lite0_clk.common,
+ &bus_msi_lite1_clk.common,
+ &bus_msi_lite2_clk.common,
+ &mbus_iommu1_sys_clk.common,
+ &apb_iommu1_sys_clk.common,
+ &ahb_iommu1_sys_clk.common,
+ &ahb_ve_dec_clk.common,
+ &ahb_ve_enc_clk.common,
+ &ahb_vid_in_clk.common,
+ &ahb_vid_cout0_clk.common,
+ &ahb_vid_cout1_clk.common,
+ &ahb_de_clk.common,
+ &ahb_npu_clk.common,
+ &ahb_gpu0_clk.common,
+ &ahb_serdes_clk.common,
+ &ahb_usb_sys_clk.common,
+ &ahb_msi_lite0_clk.common,
+ &ahb_store_clk.common,
+ &ahb_cpus_clk.common,
+ &mbus_iommu0_clk.common,
+ &mbus_iommu1_clk.common,
+ &mbus_desys_clk.common,
+ &mbus_ve_enc0_gate_clk.common,
+ &mbus_ve_dec0_gate_clk.common,
+ &mbus_gpu0_clk.common,
+ &mbus_npu_clk.common,
+ &mbus_vid_in_clk.common,
+ &mbus_serdes_clk.common,
+ &mbus_msi_lite0_clk.common,
+ &mbus_store_clk.common,
+ &mbus_msi_lite2_clk.common,
+ &mbus_dma0_clk.common,
+ &mbus_ve_enc0_clk.common,
+ &mbus_ce_clk.common,
+ &mbus_dma1_clk.common,
+ &mbus_nand0_clk.common,
+ &mbus_csi_clk.common,
+ &mbus_isp_clk.common,
+ &mbus_gmac0_clk.common,
+ &mbus_gmac1_clk.common,
+ &mbus_ve_dec0_clk.common,
+ &bus_dma0_clk.common,
+ &bus_dma1_clk.common,
+ &bus_spinlock_clk.common,
+ &bus_msgbox0_clk.common,
+ &bus_pwm0_clk.common,
+ &bus_pwm1_clk.common,
+ &bus_dbg_clk.common,
+ &bus_sysdap_clk.common,
+ &timer0_clk.common,
+ &timer1_clk.common,
+ &timer2_clk.common,
+ &timer3_clk.common,
+ &timer4_clk.common,
+ &timer5_clk.common,
+ &timer6_clk.common,
+ &timer7_clk.common,
+ &timer8_clk.common,
+ &timer9_clk.common,
+ &bus_timer_clk.common,
+ &avs_clk.common,
+ &de0_clk.common,
+ &bus_de0_clk.common,
+ &di_clk.common,
+ &bus_di_clk.common,
+ &g2d_clk.common,
+ &bus_g2d_clk.common,
+ &eink_clk.common,
+ &eink_panel_clk.common,
+ &bus_eink_clk.common,
+ &ve_enc0_clk.common,
+ &ve_dec0_clk.common,
+ &bus_ve_enc0_clk.common,
+ &bus_ve_dec0_clk.common,
+ &ce_clk.common,
+ &bus_ce_clk.common,
+ &bus_ce_sys_clk.common,
+ &npu_clk.common,
+ &bus_npu_clk.common,
+ &gpu0_clk.common,
+ &bus_gpu0_clk.common,
+ &dram0_clk.common,
+ &bus_dram0_clk.common,
+ &nand0_clk0_clk.common,
+ &nand0_clk1_clk.common,
+ &bus_nand0_clk.common,
+ &mmc0_clk.common,
+ &bus_mmc0_clk.common,
+ &mmc1_clk.common,
+ &bus_mmc1_clk.common,
+ &mmc2_clk.common,
+ &bus_mmc2_clk.common,
+ &mmc3_clk.common,
+ &bus_mmc3_clk.common,
+ &ufs_axi_clk.common,
+ &ufs_cfg_clk.common,
+ &bus_ufs_clk.common,
+ &bus_uart0_clk.common,
+ &bus_uart1_clk.common,
+ &bus_uart2_clk.common,
+ &bus_uart3_clk.common,
+ &bus_uart4_clk.common,
+ &bus_uart5_clk.common,
+ &bus_uart6_clk.common,
+ &bus_i2c0_clk.common,
+ &bus_i2c1_clk.common,
+ &bus_i2c2_clk.common,
+ &bus_i2c3_clk.common,
+ &bus_i2c4_clk.common,
+ &bus_i2c5_clk.common,
+ &bus_i2c6_clk.common,
+ &bus_i2c7_clk.common,
+ &bus_i2c8_clk.common,
+ &bus_i2c9_clk.common,
+ &bus_i2c10_clk.common,
+ &bus_i2c11_clk.common,
+ &bus_i2c12_clk.common,
+ &spi0_clk.common,
+ &bus_spi0_clk.common,
+ &spi1_clk.common,
+ &bus_spi1_clk.common,
+ &spi2_clk.common,
+ &bus_spi2_clk.common,
+ &spif_clk.common,
+ &bus_spif_clk.common,
+ &spi3_clk.common,
+ &bus_spi3_clk.common,
+ &spi4_clk.common,
+ &bus_spi4_clk.common,
+ &gpadc0_24m_clk.common,
+ &bus_gpadc0_clk.common,
+ &bus_ths0_clk.common,
+ &irrx_clk.common,
+ &bus_irrx_clk.common,
+ &irtx_clk.common,
+ &bus_irtx_clk.common,
+ &bus_lradc_clk.common,
+ &sgpio_clk.common,
+ &bus_sgpio_clk.common,
+ &lpc_clk.common,
+ &bus_lpc_clk.common,
+ &i2spcm0_clk.common,
+ &bus_i2spcm0_clk.common,
+ &i2spcm1_clk.common,
+ &bus_i2spcm1_clk.common,
+ &i2spcm2_clk.common,
+ &i2spcm2_asrc_clk.common,
+ &bus_i2spcm2_clk.common,
+ &i2spcm3_clk.common,
+ &bus_i2spcm3_clk.common,
+ &i2spcm4_clk.common,
+ &bus_i2spcm4_clk.common,
+ &spdif_tx_clk.common,
+ &spdif_rx_clk.common,
+ &bus_spdif_clk.common,
+ &dmic_clk.common,
+ &bus_dmic_clk.common,
+ &usb_ohci0_clk.common,
+ &bus_ohci0_clk.common,
+ &bus_ehci0_clk.common,
+ &bus_otg_clk.common,
+ &usb_ohci1_clk.common,
+ &bus_ohci1_clk.common,
+ &bus_ehci1_clk.common,
+ &usb01_ref_clk.common,
+ &usb2_u2_ref_clk.common,
+ &usb2_suspend_clk.common,
+ &usb2_mf_clk.common,
+ &usb2_u3_utmi_clk.common,
+ &usb2_u2_pipe_clk.common,
+ &pcie_aux_clk.common,
+ &pcie_axi_slv_clk.common,
+ &serdes_phy_clk.common,
+ &gmac_ptp_clk.common,
+ &gmac0_phy_clk.common,
+ &bus_gmac0_clk.common,
+ &gmac1_phy_clk.common,
+ &bus_gmac1_clk.common,
+ &tcon_lcd0_clk.common,
+ &bus_tcon_lcd0_clk.common,
+ &tcon_lcd1_clk.common,
+ &bus_tcon_lcd1_clk.common,
+ &tcon_lcd2_clk.common,
+ &bus_tcon_lcd2_clk.common,
+ &dsi0_clk.common,
+ &bus_dsi0_clk.common,
+ &dsi1_clk.common,
+ &bus_dsi1_clk.common,
+ &combphy0_clk.common,
+ &combphy1_clk.common,
+ &bus_tcon_tv0_clk.common,
+ &bus_tcon_tv1_clk.common,
+ &edp_tv_clk.common,
+ &bus_edp_tv_clk.common,
+ &hdmi_cec_32k_clk.common,
+ &hdmi_cec_clk.common,
+ &hdmi_tv_clk.common,
+ &bus_hdmi_tv_clk.common,
+ &hdmi_sfr_clk.common,
+ &hdcp_esm_clk.common,
+ &bus_dpss_top0_clk.common,
+ &bus_dpss_top1_clk.common,
+ &ledc_clk.common,
+ &bus_ledc_clk.common,
+ &bus_dsc_clk.common,
+ &csi_master0_clk.common,
+ &csi_master1_clk.common,
+ &csi_master2_clk.common,
+ &csi_clk.common,
+ &bus_csi_clk.common,
+ &isp_clk.common,
+ &res_dcap_24m_clk.common,
+ &apb2jtag_clk.common,
+ &fanout_24M_clk.common,
+ &fanout_12M_clk.common,
+ &fanout_16M_clk.common,
+ &fanout_25M_clk.common,
+ &fanout_27M_clk.common,
+ &fanout_pclk_clk.common,
+ &fanout0_clk.common,
+ &fanout1_clk.common,
+ &fanout2_clk.common,
+ &fanout3_clk.common,
+};
+
+static struct clk_hw_onecell_data sun60i_a733_hw_clks = {
+ .hws = {
+ [CLK_PLL_REF] = &pll_ref_clk.common.hw,
+ [CLK_SYS_24M] = &sys_24M_clk.hw,
+ [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
+ [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw,
+ [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw,
+ [CLK_PLL_PERIPH0_800M] = &pll_periph0_800M_clk.common.hw,
+ [CLK_PLL_PERIPH0_480M] = &pll_periph0_480M_clk.common.hw,
+ [CLK_PLL_PERIPH0_600M] = &pll_periph0_600M_clk.hw,
+ [CLK_PLL_PERIPH0_400M] = &pll_periph0_400M_clk.hw,
+ [CLK_PLL_PERIPH0_300M] = &pll_periph0_300M_clk.hw,
+ [CLK_PLL_PERIPH0_200M] = &pll_periph0_200M_clk.hw,
+ [CLK_PLL_PERIPH0_160M] = &pll_periph0_160M_clk.hw,
+ [CLK_PLL_PERIPH0_150M] = &pll_periph0_150M_clk.hw,
+ [CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.common.hw,
+ [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.common.hw,
+ [CLK_PLL_PERIPH1_800M] = &pll_periph1_800M_clk.common.hw,
+ [CLK_PLL_PERIPH1_480M] = &pll_periph1_480M_clk.common.hw,
+ [CLK_PLL_PERIPH1_600M] = &pll_periph1_600M_clk.hw,
+ [CLK_PLL_PERIPH1_400M] = &pll_periph1_400M_clk.hw,
+ [CLK_PLL_PERIPH1_300M] = &pll_periph1_300M_clk.hw,
+ [CLK_PLL_PERIPH1_200M] = &pll_periph1_200M_clk.hw,
+ [CLK_PLL_PERIPH1_160M] = &pll_periph1_160M_clk.hw,
+ [CLK_PLL_PERIPH1_150M] = &pll_periph1_150M_clk.hw,
+ [CLK_PLL_GPU0] = &pll_gpu0_clk.common.hw,
+ [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
+ [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw,
+ [CLK_PLL_VIDEO0_3X] = &pll_video0_3x_clk.common.hw,
+ [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
+ [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw,
+ [CLK_PLL_VIDEO1_3X] = &pll_video1_3x_clk.common.hw,
+ [CLK_PLL_VIDEO2] = &pll_video2_clk.common.hw,
+ [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.common.hw,
+ [CLK_PLL_VIDEO2_3X] = &pll_video2_3x_clk.common.hw,
+ [CLK_PLL_VE0] = &pll_ve0_clk.common.hw,
+ [CLK_PLL_VE1] = &pll_ve1_clk.common.hw,
+ [CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw,
+ [CLK_PLL_AUDIO1] = &pll_audio1_clk.common.hw,
+ [CLK_PLL_AUDIO1_DIV2] = &pll_audio1_div2_clk.hw,
+ [CLK_PLL_AUDIO1_DIV5] = &pll_audio1_div5_clk.hw,
+ [CLK_PLL_NPU] = &pll_npu_clk.common.hw,
+ [CLK_PLL_DE] = &pll_de_clk.common.hw,
+ [CLK_PLL_DE_4X] = &pll_de_4x_clk.common.hw,
+ [CLK_PLL_DE_3X] = &pll_de_3x_clk.common.hw,
+ [CLK_AHB] = &ahb_clk.common.hw,
+ [CLK_APB0] = &apb0_clk.common.hw,
+ [CLK_APB1] = &apb1_clk.common.hw,
+ [CLK_APB_UART] = &apb_uart_clk.common.hw,
+ [CLK_TRACE] = &trace_clk.common.hw,
+ [CLK_GIC] = &gic_clk.common.hw,
+ [CLK_BUS_ITS_PCIE0_ACLK] = &bus_its_pcie0_aclk_clk.common.hw,
+ [CLK_MBUS] = &mbus_clk.common.hw,
+ [CLK_MBUS_IOMMU0_SYS] = &mbus_iommu0_sys_clk.common.hw,
+ [CLK_APB_IOMMU0_SYS] = &apb_iommu0_sys_clk.common.hw,
+ [CLK_AHB_IOMMU0_SYS] = &ahb_iommu0_sys_clk.common.hw,
+ [CLK_BUS_MSI_LITE0] = &bus_msi_lite0_clk.common.hw,
+ [CLK_BUS_MSI_LITE1] = &bus_msi_lite1_clk.common.hw,
+ [CLK_BUS_MSI_LITE2] = &bus_msi_lite2_clk.common.hw,
+ [CLK_MBUS_IOMMU1_SYS] = &mbus_iommu1_sys_clk.common.hw,
+ [CLK_APB_IOMMU1_SYS] = &apb_iommu1_sys_clk.common.hw,
+ [CLK_AHB_IOMMU1_SYS] = &ahb_iommu1_sys_clk.common.hw,
+ [CLK_AHB_VE_DEC] = &ahb_ve_dec_clk.common.hw,
+ [CLK_AHB_VE_ENC] = &ahb_ve_enc_clk.common.hw,
+ [CLK_AHB_VID_IN] = &ahb_vid_in_clk.common.hw,
+ [CLK_AHB_VID_COUT0] = &ahb_vid_cout0_clk.common.hw,
+ [CLK_AHB_VID_COUT1] = &ahb_vid_cout1_clk.common.hw,
+ [CLK_AHB_DE] = &ahb_de_clk.common.hw,
+ [CLK_AHB_NPU] = &ahb_npu_clk.common.hw,
+ [CLK_AHB_GPU0] = &ahb_gpu0_clk.common.hw,
+ [CLK_AHB_SERDES] = &ahb_serdes_clk.common.hw,
+ [CLK_AHB_USB_SYS] = &ahb_usb_sys_clk.common.hw,
+ [CLK_AHB_MSI_LITE0] = &ahb_msi_lite0_clk.common.hw,
+ [CLK_AHB_STORE] = &ahb_store_clk.common.hw,
+ [CLK_AHB_CPUS] = &ahb_cpus_clk.common.hw,
+ [CLK_MBUS_IOMMU0] = &mbus_iommu0_clk.common.hw,
+ [CLK_MBUS_IOMMU1] = &mbus_iommu1_clk.common.hw,
+ [CLK_MBUS_DESYS] = &mbus_desys_clk.common.hw,
+ [CLK_MBUS_VE_ENC0_GATE] = &mbus_ve_enc0_gate_clk.common.hw,
+ [CLK_MBUS_VE_DEC0_GATE] = &mbus_ve_dec0_gate_clk.common.hw,
+ [CLK_MBUS_GPU0] = &mbus_gpu0_clk.common.hw,
+ [CLK_MBUS_NPU] = &mbus_npu_clk.common.hw,
+ [CLK_MBUS_VID_IN] = &mbus_vid_in_clk.common.hw,
+ [CLK_MBUS_SERDES] = &mbus_serdes_clk.common.hw,
+ [CLK_MBUS_MSI_LITE0] = &mbus_msi_lite0_clk.common.hw,
+ [CLK_MBUS_STORE] = &mbus_store_clk.common.hw,
+ [CLK_MBUS_MSI_LITE2] = &mbus_msi_lite2_clk.common.hw,
+ [CLK_MBUS_DMA0] = &mbus_dma0_clk.common.hw,
+ [CLK_MBUS_VE_ENC0] = &mbus_ve_enc0_clk.common.hw,
+ [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
+ [CLK_MBUS_DMA1] = &mbus_dma1_clk.common.hw,
+ [CLK_MBUS_NAND0] = &mbus_nand0_clk.common.hw,
+ [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
+ [CLK_MBUS_ISP] = &mbus_isp_clk.common.hw,
+ [CLK_MBUS_GMAC0] = &mbus_gmac0_clk.common.hw,
+ [CLK_MBUS_GMAC1] = &mbus_gmac1_clk.common.hw,
+ [CLK_MBUS_VE_DEC0] = &mbus_ve_dec0_clk.common.hw,
+ [CLK_BUS_DMA0] = &bus_dma0_clk.common.hw,
+ [CLK_BUS_DMA1] = &bus_dma1_clk.common.hw,
+ [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
+ [CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw,
+ [CLK_BUS_PWM0] = &bus_pwm0_clk.common.hw,
+ [CLK_BUS_PWM1] = &bus_pwm1_clk.common.hw,
+ [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
+ [CLK_BUS_SYSDAP] = &bus_sysdap_clk.common.hw,
+ [CLK_TIMER0] = &timer0_clk.common.hw,
+ [CLK_TIMER1] = &timer1_clk.common.hw,
+ [CLK_TIMER2] = &timer2_clk.common.hw,
+ [CLK_TIMER3] = &timer3_clk.common.hw,
+ [CLK_TIMER4] = &timer4_clk.common.hw,
+ [CLK_TIMER5] = &timer5_clk.common.hw,
+ [CLK_TIMER6] = &timer6_clk.common.hw,
+ [CLK_TIMER7] = &timer7_clk.common.hw,
+ [CLK_TIMER8] = &timer8_clk.common.hw,
+ [CLK_TIMER9] = &timer9_clk.common.hw,
+ [CLK_BUS_TIMER] = &bus_timer_clk.common.hw,
+ [CLK_AVS] = &avs_clk.common.hw,
+ [CLK_DE0] = &de0_clk.common.hw,
+ [CLK_BUS_DE0] = &bus_de0_clk.common.hw,
+ [CLK_DI] = &di_clk.common.hw,
+ [CLK_BUS_DI] = &bus_di_clk.common.hw,
+ [CLK_G2D] = &g2d_clk.common.hw,
+ [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
+ [CLK_EINK] = &eink_clk.common.hw,
+ [CLK_EINK_PANEL] = &eink_panel_clk.common.hw,
+ [CLK_BUS_EINK] = &bus_eink_clk.common.hw,
+ [CLK_VE_ENC0] = &ve_enc0_clk.common.hw,
+ [CLK_VE_DEC0] = &ve_dec0_clk.common.hw,
+ [CLK_BUS_VE_ENC0] = &bus_ve_enc0_clk.common.hw,
+ [CLK_BUS_VE_DEC0] = &bus_ve_dec0_clk.common.hw,
+ [CLK_CE] = &ce_clk.common.hw,
+ [CLK_BUS_CE] = &bus_ce_clk.common.hw,
+ [CLK_BUS_CE_SYS] = &bus_ce_sys_clk.common.hw,
+ [CLK_NPU] = &npu_clk.common.hw,
+ [CLK_BUS_NPU] = &bus_npu_clk.common.hw,
+ [CLK_GPU0] = &gpu0_clk.common.hw,
+ [CLK_BUS_GPU0] = &bus_gpu0_clk.common.hw,
+ [CLK_DRAM0] = &dram0_clk.common.hw,
+ [CLK_BUS_DRAM0] = &bus_dram0_clk.common.hw,
+ [CLK_NAND0_CLK0] = &nand0_clk0_clk.common.hw,
+ [CLK_NAND0_CLK1] = &nand0_clk1_clk.common.hw,
+ [CLK_BUS_NAND0] = &bus_nand0_clk.common.hw,
+ [CLK_MMC0] = &mmc0_clk.common.hw,
+ [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
+ [CLK_MMC1] = &mmc1_clk.common.hw,
+ [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
+ [CLK_MMC2] = &mmc2_clk.common.hw,
+ [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
+ [CLK_MMC3] = &mmc3_clk.common.hw,
+ [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw,
+ [CLK_UFS_AXI] = &ufs_axi_clk.common.hw,
+ [CLK_UFS_CFG] = &ufs_cfg_clk.common.hw,
+ [CLK_BUS_UFS] = &bus_ufs_clk.common.hw,
+ [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
+ [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
+ [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
+ [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
+ [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
+ [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
+ [CLK_BUS_UART6] = &bus_uart6_clk.common.hw,
+ [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
+ [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
+ [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
+ [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
+ [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
+ [CLK_BUS_I2C5] = &bus_i2c5_clk.common.hw,
+ [CLK_BUS_I2C6] = &bus_i2c6_clk.common.hw,
+ [CLK_BUS_I2C7] = &bus_i2c7_clk.common.hw,
+ [CLK_BUS_I2C8] = &bus_i2c8_clk.common.hw,
+ [CLK_BUS_I2C9] = &bus_i2c9_clk.common.hw,
+ [CLK_BUS_I2C10] = &bus_i2c10_clk.common.hw,
+ [CLK_BUS_I2C11] = &bus_i2c11_clk.common.hw,
+ [CLK_BUS_I2C12] = &bus_i2c12_clk.common.hw,
+ [CLK_SPI0] = &spi0_clk.common.hw,
+ [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
+ [CLK_SPI1] = &spi1_clk.common.hw,
+ [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
+ [CLK_SPI2] = &spi2_clk.common.hw,
+ [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
+ [CLK_SPIF] = &spif_clk.common.hw,
+ [CLK_BUS_SPIF] = &bus_spif_clk.common.hw,
+ [CLK_SPI3] = &spi3_clk.common.hw,
+ [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
+ [CLK_SPI4] = &spi4_clk.common.hw,
+ [CLK_BUS_SPI4] = &bus_spi4_clk.common.hw,
+ [CLK_GPADC0_24M] = &gpadc0_24m_clk.common.hw,
+ [CLK_BUS_GPADC0] = &bus_gpadc0_clk.common.hw,
+ [CLK_BUS_THS0] = &bus_ths0_clk.common.hw,
+ [CLK_IRRX] = &irrx_clk.common.hw,
+ [CLK_BUS_IRRX] = &bus_irrx_clk.common.hw,
+ [CLK_IRTX] = &irtx_clk.common.hw,
+ [CLK_BUS_IRTX] = &bus_irtx_clk.common.hw,
+ [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
+ [CLK_SGPIO] = &sgpio_clk.common.hw,
+ [CLK_BUS_SGPIO] = &bus_sgpio_clk.common.hw,
+ [CLK_LPC] = &lpc_clk.common.hw,
+ [CLK_BUS_LPC] = &bus_lpc_clk.common.hw,
+ [CLK_I2SPCM0] = &i2spcm0_clk.common.hw,
+ [CLK_BUS_I2SPCM0] = &bus_i2spcm0_clk.common.hw,
+ [CLK_I2SPCM1] = &i2spcm1_clk.common.hw,
+ [CLK_BUS_I2SPCM1] = &bus_i2spcm1_clk.common.hw,
+ [CLK_I2SPCM2] = &i2spcm2_clk.common.hw,
+ [CLK_I2SPCM2_ASRC] = &i2spcm2_asrc_clk.common.hw,
+ [CLK_BUS_I2SPCM2] = &bus_i2spcm2_clk.common.hw,
+ [CLK_I2SPCM3] = &i2spcm3_clk.common.hw,
+ [CLK_BUS_I2SPCM3] = &bus_i2spcm3_clk.common.hw,
+ [CLK_I2SPCM4] = &i2spcm4_clk.common.hw,
+ [CLK_BUS_I2SPCM4] = &bus_i2spcm4_clk.common.hw,
+ [CLK_SPDIF_TX] = &spdif_tx_clk.common.hw,
+ [CLK_SPDIF_RX] = &spdif_rx_clk.common.hw,
+ [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
+ [CLK_DMIC] = &dmic_clk.common.hw,
+ [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
+ [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
+ [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
+ [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
+ [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
+ [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
+ [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
+ [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
+ [CLK_USB01_REF] = &usb01_ref_clk.common.hw,
+ [CLK_USB2_U2_REF] = &usb2_u2_ref_clk.common.hw,
+ [CLK_USB2_SUSPEND] = &usb2_suspend_clk.common.hw,
+ [CLK_USB2_MF] = &usb2_mf_clk.common.hw,
+ [CLK_USB2_U3_UTMI] = &usb2_u3_utmi_clk.common.hw,
+ [CLK_USB2_U2_PIPE] = &usb2_u2_pipe_clk.common.hw,
+ [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw,
+ [CLK_PCIE_AXI_SLV] = &pcie_axi_slv_clk.common.hw,
+ [CLK_SERDES_PHY] = &serdes_phy_clk.common.hw,
+ [CLK_GMAC_PTP] = &gmac_ptp_clk.common.hw,
+ [CLK_GMAC0_PHY] = &gmac0_phy_clk.common.hw,
+ [CLK_BUS_GMAC0] = &bus_gmac0_clk.common.hw,
+ [CLK_GMAC1_PHY] = &gmac1_phy_clk.common.hw,
+ [CLK_BUS_GMAC1] = &bus_gmac1_clk.common.hw,
+ [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
+ [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
+ [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
+ [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
+ [CLK_TCON_LCD2] = &tcon_lcd2_clk.common.hw,
+ [CLK_BUS_TCON_LCD2] = &bus_tcon_lcd2_clk.common.hw,
+ [CLK_DSI0] = &dsi0_clk.common.hw,
+ [CLK_BUS_DSI0] = &bus_dsi0_clk.common.hw,
+ [CLK_DSI1] = &dsi1_clk.common.hw,
+ [CLK_BUS_DSI1] = &bus_dsi1_clk.common.hw,
+ [CLK_COMBPHY0] = &combphy0_clk.common.hw,
+ [CLK_COMBPHY1] = &combphy1_clk.common.hw,
+ [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
+ [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
+ [CLK_EDP_TV] = &edp_tv_clk.common.hw,
+ [CLK_BUS_EDP_TV] = &bus_edp_tv_clk.common.hw,
+ [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw,
+ [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
+ [CLK_HDMI_TV] = &hdmi_tv_clk.common.hw,
+ [CLK_BUS_HDMI_TV] = &bus_hdmi_tv_clk.common.hw,
+ [CLK_HDMI_SFR] = &hdmi_sfr_clk.common.hw,
+ [CLK_HDCP_ESM] = &hdcp_esm_clk.common.hw,
+ [CLK_BUS_DPSS_TOP0] = &bus_dpss_top0_clk.common.hw,
+ [CLK_BUS_DPSS_TOP1] = &bus_dpss_top1_clk.common.hw,
+ [CLK_LEDC] = &ledc_clk.common.hw,
+ [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw,
+ [CLK_BUS_DSC] = &bus_dsc_clk.common.hw,
+ [CLK_CSI_MASTER0] = &csi_master0_clk.common.hw,
+ [CLK_CSI_MASTER1] = &csi_master1_clk.common.hw,
+ [CLK_CSI_MASTER2] = &csi_master2_clk.common.hw,
+ [CLK_CSI] = &csi_clk.common.hw,
+ [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
+ [CLK_ISP] = &isp_clk.common.hw,
+ [CLK_RES_DCAP_24M] = &res_dcap_24m_clk.common.hw,
+ [CLK_APB2JTAG] = &apb2jtag_clk.common.hw,
+ [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw,
+ [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw,
+ [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw,
+ [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw,
+ [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw,
+ [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw,
+ [CLK_FANOUT0] = &fanout0_clk.common.hw,
+ [CLK_FANOUT1] = &fanout1_clk.common.hw,
+ [CLK_FANOUT2] = &fanout2_clk.common.hw,
+ [CLK_FANOUT3] = &fanout3_clk.common.hw,
+ },
+ .num = CLK_FANOUT3 + 1,
+};
+
+static const struct ccu_reset_map sun60i_a733_ccu_resets[] = {
+ [RST_BUS_ITS_PCIE0] = { 0x574, BIT(16) },
+ [RST_BUS_IOMMU0_SYS] = { 0x58c, BIT(16) },
+ [RST_BUS_MSI_LITE0_AHB] = { 0x594, BIT(16) },
+ [RST_BUS_MSI_LITE0_MBUS] = { 0x594, BIT(17) },
+ [RST_BUS_MSI_LITE1_AHB] = { 0x59c, BIT(16) },
+ [RST_BUS_MSI_LITE1_MBUS] = { 0x59c, BIT(17) },
+ [RST_BUS_MSI_LITE2_AHB] = { 0x5a4, BIT(16) },
+ [RST_BUS_MSI_LITE2_MBUS] = { 0x5a4, BIT(17) },
+ [RST_BUS_IOMMU1_SYS] = { 0x5b4, BIT(16) },
+ [RST_BUS_DMA0] = { 0x704, BIT(16) },
+ [RST_BUS_DMA1] = { 0x70c, BIT(16) },
+ [RST_BUS_SPINLOCK] = { 0x724, BIT(16) },
+ [RST_BUS_MSGBOX] = { 0x744, BIT(16) },
+ [RST_BUS_PWM0] = { 0x784, BIT(16) },
+ [RST_BUS_PWM1] = { 0x78c, BIT(16) },
+ [RST_BUS_DBG] = { 0x7a4, BIT(16) },
+ [RST_BUS_SYSDAP] = { 0x7ac, BIT(16) },
+ [RST_BUS_TIMER0] = { 0x850, BIT(16) },
+ [RST_BUS_DE0] = { 0xa04, BIT(16) },
+ [RST_BUS_DI] = { 0xa24, BIT(16) },
+ [RST_BUS_G2D] = { 0xa44, BIT(16) },
+ [RST_BUS_EINK] = { 0xa6c, BIT(16) },
+ [RST_BUS_DE_SYS] = { 0xa74, BIT(16) },
+ [RST_BUS_VE_ENC0] = { 0xa8c, BIT(16) },
+ [RST_BUS_VE_DEC0] = { 0xa8c, BIT(18) },
+ [RST_BUS_CE] = { 0xac4, BIT(16) },
+ [RST_BUS_CE_SYS] = { 0xac4, BIT(17) },
+ [RST_BUS_NPU_CORE] = { 0xb04, BIT(16) },
+ [RST_BUS_NPU_AXI] = { 0xb04, BIT(17) },
+ [RST_BUS_NPU_AHB] = { 0xb04, BIT(18) },
+ [RST_BUS_NPU_SRAM] = { 0xb04, BIT(19) },
+ [RST_BUS_GPU0] = { 0xb24, BIT(16) },
+ [RST_BUS_DRAM0] = { 0xc0c, BIT(16) },
+ [RST_BUS_NAND0] = { 0xc8c, BIT(16) },
+ [RST_BUS_MMC0] = { 0xd0c, BIT(16) },
+ [RST_BUS_MMC1] = { 0xd1c, BIT(16) },
+ [RST_BUS_MMC2] = { 0xd2c, BIT(16) },
+ [RST_BUS_MMC3] = { 0xd3c, BIT(16) },
+ [RST_BUS_UFS_AHB] = { 0xd8c, BIT(16) },
+ [RST_BUS_UFS_AXI] = { 0xd8c, BIT(17) },
+ [RST_BUS_UFS_PHY] = { 0xd8c, BIT(18) },
+ [RST_BUS_UFS_CORE] = { 0xd8c, BIT(19) },
+ [RST_BUS_UART0] = { 0xe00, BIT(16) },
+ [RST_BUS_UART1] = { 0xe04, BIT(16) },
+ [RST_BUS_UART2] = { 0xe08, BIT(16) },
+ [RST_BUS_UART3] = { 0xe0c, BIT(16) },
+ [RST_BUS_UART4] = { 0xe10, BIT(16) },
+ [RST_BUS_UART5] = { 0xe14, BIT(16) },
+ [RST_BUS_UART6] = { 0xe18, BIT(16) },
+ [RST_BUS_I2C0] = { 0xe80, BIT(16) },
+ [RST_BUS_I2C1] = { 0xe84, BIT(16) },
+ [RST_BUS_I2C2] = { 0xe88, BIT(16) },
+ [RST_BUS_I2C3] = { 0xe8c, BIT(16) },
+ [RST_BUS_I2C4] = { 0xe90, BIT(16) },
+ [RST_BUS_I2C5] = { 0xe94, BIT(16) },
+ [RST_BUS_I2C6] = { 0xe98, BIT(16) },
+ [RST_BUS_I2C7] = { 0xe9c, BIT(16) },
+ [RST_BUS_I2C8] = { 0xea0, BIT(16) },
+ [RST_BUS_I2C9] = { 0xea4, BIT(16) },
+ [RST_BUS_I2C10] = { 0xea8, BIT(16) },
+ [RST_BUS_I2C11] = { 0xeac, BIT(16) },
+ [RST_BUS_I2C12] = { 0xeb0, BIT(16) },
+ [RST_BUS_SPI0] = { 0xf04, BIT(16) },
+ [RST_BUS_SPI1] = { 0xf0c, BIT(16) },
+ [RST_BUS_SPI2] = { 0xf14, BIT(16) },
+ [RST_BUS_SPIF] = { 0xf1c, BIT(16) },
+ [RST_BUS_SPI3] = { 0xf24, BIT(16) },
+ [RST_BUS_SPI4] = { 0xf2c, BIT(16) }, /* From the vendor kernel. */
+ [RST_BUS_GPADC0] = { 0xfc4, BIT(16) },
+ [RST_BUS_THS0] = { 0xfe4, BIT(16) },
+ [RST_BUS_IRRX] = { 0x1004, BIT(16) },
+ [RST_BUS_IRTX] = { 0x100c, BIT(16) },
+ [RST_BUS_LRADC] = { 0x1024, BIT(16) },
+ [RST_BUS_SGPIO] = { 0x1064, BIT(16) }, /* From the vendor kernel. */
+ [RST_BUS_LPC] = { 0x1084, BIT(16) }, /* From the vendor kernel. */
+ [RST_BUS_I2SPCM0] = { 0x120c, BIT(16) },
+ [RST_BUS_I2SPCM1] = { 0x121c, BIT(16) },
+ [RST_BUS_I2SPCM2] = { 0x122c, BIT(16) },
+ [RST_BUS_I2SPCM3] = { 0x123c, BIT(16) },
+ [RST_BUS_I2SPCM4] = { 0x124c, BIT(16) },
+ [RST_BUS_SPDIF] = { 0x128c, BIT(16) },
+ [RST_BUS_DMIC] = { 0x12cc, BIT(16) },
+ [RST_USB_PHY0] = { 0x1300, BIT(30) },
+ [RST_BUS_OHCI0] = { 0x1304, BIT(16) },
+ [RST_BUS_EHCI0] = { 0x1304, BIT(20) },
+ [RST_BUS_OTG] = { 0x1304, BIT(24) },
+ [RST_USB_PHY1] = { 0x1308, BIT(30) },
+ [RST_BUS_OHCI1] = { 0x130c, BIT(16) },
+ [RST_BUS_EHCI1] = { 0x130c, BIT(20) },
+ [RST_BUS_USB2] = { 0x135c, BIT(16) },
+ [RST_BUS_PCIE_PWRUP] = { 0x138c, BIT(16) },
+ [RST_BUS_PCIE] = { 0x138c, BIT(17) },
+ [RST_BUS_SERDES] = { 0x13c4, BIT(16) },
+ [RST_BUS_GMAC0] = { 0x141c, BIT(16) },
+ [RST_BUS_GMAC0_AXI] = { 0x141c, BIT(17) },
+ [RST_BUS_GMAC1] = { 0x142c, BIT(16) }, /* From the vendor kernel. */
+ [RST_BUS_GMAC1_AXI] = { 0x142c, BIT(17) }, /* From the vendor kernel. */
+ [RST_BUS_TCON_LCD0] = { 0x1504, BIT(16) },
+ [RST_BUS_TCON_LCD1] = { 0x150c, BIT(16) },
+ [RST_BUS_TCON_LCD2] = { 0x1514, BIT(16) }, /* From the vendor kernel. */
+ [RST_BUS_LVDS0] = { 0x1544, BIT(16) },
+ [RST_BUS_LVDS1] = { 0x154c, BIT(16) },
+ [RST_BUS_DSI0] = { 0x1584, BIT(16) },
+ [RST_BUS_DSI1] = { 0x158c, BIT(16) },
+ [RST_BUS_TCON_TV0] = { 0x1604, BIT(16) },
+ [RST_BUS_TCON_TV1] = { 0x160c, BIT(16) },
+ [RST_BUS_EDP] = { 0x164c, BIT(16) },
+ [RST_BUS_HDMI_MAIN] = { 0x168c, BIT(16) },
+ [RST_BUS_HDMI_SUB] = { 0x168c, BIT(17) },
+ [RST_BUS_HDMI_HDCP] = { 0x168c, BIT(18) },
+ [RST_BUS_DPSS_TOP0] = { 0x16c4, BIT(16) },
+ [RST_BUS_DPSS_TOP1] = { 0x16cc, BIT(16) },
+ [RST_BUS_VIDEO_OUT0] = { 0x16e4, BIT(16) },
+ [RST_BUS_VIDEO_OUT1] = { 0x16ec, BIT(16) },
+ [RST_BUS_LEDC] = { 0x1704, BIT(16) },
+ [RST_BUS_DSC] = { 0x1744, BIT(16) },
+ [RST_BUS_CSI] = { 0x1844, BIT(16) },
+ [RST_BUS_VIDEO_IN] = { 0x1884, BIT(16) },
+ [RST_BUS_APB2JTAG] = { 0x1c04, BIT(16) },
+};
+
+static const struct sunxi_ccu_desc sun60i_a733_ccu_desc = {
+ .ccu_clks = sun60i_a733_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun60i_a733_ccu_clks),
+
+ .hw_clks = &sun60i_a733_hw_clks,
+
+ .resets = sun60i_a733_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun60i_a733_ccu_resets),
+};
+
+static const u32 pll_regs[] = {
+ SUN60I_A733_PLL_REF_REG,
+ SUN60I_A733_PLL_DDR_REG,
+ SUN60I_A733_PLL_PERIPH0_REG,
+ SUN60I_A733_PLL_PERIPH1_REG,
+ SUN60I_A733_PLL_GPU_REG,
+ SUN60I_A733_PLL_VIDEO0_REG,
+ SUN60I_A733_PLL_VIDEO1_REG,
+ SUN60I_A733_PLL_VIDEO2_REG,
+ SUN60I_A733_PLL_VE0_REG,
+ SUN60I_A733_PLL_VE1_REG,
+ SUN60I_A733_PLL_AUDIO0_REG,
+ SUN60I_A733_PLL_AUDIO1_REG,
+ SUN60I_A733_PLL_NPU_REG,
+ SUN60I_A733_PLL_DE_REG,
+};
+
+static int sun60i_a733_ccu_probe(struct platform_device *pdev)
+{
+ void __iomem *reg;
+ u32 val;
+ int i, ret;
+
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
+
+ /*
+ * The CCU framework only models one enable bit per PLL, while the
+ * hardware has separate PLL, LDO, lock, and output gate controls.
+ * Enable the common PLL, LDO, and lock controls here.
+ */
+ for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
+ val = readl(reg + pll_regs[i]);
+ val |= BIT(31) | BIT(30) | BIT(29);
+ writel(val, reg + pll_regs[i]);
+ }
+
+ /* Enforce m1 = 0 for PLL_AUDIO0. */
+ val = readl(reg + SUN60I_A733_PLL_AUDIO0_REG);
+ val &= ~BIT(1);
+ writel(val, reg + SUN60I_A733_PLL_AUDIO0_REG);
+
+ /* Enforce the named /2 and /5 outputs for PLL_AUDIO1. */
+ val = readl(reg + SUN60I_A733_PLL_AUDIO1_REG);
+ val &= ~(GENMASK(22, 20) | GENMASK(18, 16));
+ val |= (1 << 20) | (4 << 16);
+ writel(val, reg + SUN60I_A733_PLL_AUDIO1_REG);
+
+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun60i_a733_ccu_desc);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct of_device_id sun60i_a733_ccu_ids[] = {
+ { .compatible = "allwinner,sun60i-a733-ccu" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sun60i_a733_ccu_ids);
+
+static struct platform_driver sun60i_a733_ccu_driver = {
+ .probe = sun60i_a733_ccu_probe,
+ .driver = {
+ .name = "sun60i-a733-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun60i_a733_ccu_ids,
+ },
+};
+module_platform_driver(sun60i_a733_ccu_driver);
+
+MODULE_IMPORT_NS("SUNXI_CCU");
+MODULE_DESCRIPTION("Support for the Allwinner A733 CCU");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu_sdm.c b/drivers/clk/sunxi-ng/ccu_sdm.c
index c564e5f9e6104..7e13ffd246d36 100644
--- a/drivers/clk/sunxi-ng/ccu_sdm.c
+++ b/drivers/clk/sunxi-ng/ccu_sdm.c
@@ -18,7 +18,11 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable))
return false;
- return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable);
+ if (sdm->pat1_enable &&
+ (readl(common->base + sdm->pat1_reg) & sdm->pat1_enable) != sdm->pat1_enable)
+ return false;
+
+ return !!(readl(common->base + sdm->pat0_reg) & sdm->pat0_enable);
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, "SUNXI_CCU");
@@ -37,18 +41,27 @@ void ccu_sdm_helper_enable(struct ccu_common *common,
for (i = 0; i < sdm->table_size; i++)
if (sdm->table[i].rate == rate)
writel(sdm->table[i].pattern,
- common->base + sdm->tuning_reg);
+ common->base + sdm->pat0_reg);
/* Make sure SDM is enabled */
spin_lock_irqsave(common->lock, flags);
- reg = readl(common->base + sdm->tuning_reg);
- writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg);
+ reg = readl(common->base + sdm->pat0_reg);
+ writel(reg | sdm->pat0_enable, common->base + sdm->pat0_reg);
spin_unlock_irqrestore(common->lock, flags);
- spin_lock_irqsave(common->lock, flags);
- reg = readl(common->base + common->reg);
- writel(reg | sdm->enable, common->base + common->reg);
- spin_unlock_irqrestore(common->lock, flags);
+ if (sdm->enable) {
+ spin_lock_irqsave(common->lock, flags);
+ reg = readl(common->base + common->reg);
+ writel(reg | sdm->enable, common->base + common->reg);
+ spin_unlock_irqrestore(common->lock, flags);
+ }
+
+ if (sdm->pat1_enable) {
+ spin_lock_irqsave(common->lock, flags);
+ reg = readl(common->base + sdm->pat1_reg);
+ writel(reg | sdm->pat1_enable, common->base + sdm->pat1_reg);
+ spin_unlock_irqrestore(common->lock, flags);
+ }
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, "SUNXI_CCU");
@@ -61,14 +74,23 @@ void ccu_sdm_helper_disable(struct ccu_common *common,
if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
return;
- spin_lock_irqsave(common->lock, flags);
- reg = readl(common->base + common->reg);
- writel(reg & ~sdm->enable, common->base + common->reg);
- spin_unlock_irqrestore(common->lock, flags);
+ if (sdm->enable) {
+ spin_lock_irqsave(common->lock, flags);
+ reg = readl(common->base + common->reg);
+ writel(reg & ~sdm->enable, common->base + common->reg);
+ spin_unlock_irqrestore(common->lock, flags);
+ }
+
+ if (sdm->pat1_enable) {
+ spin_lock_irqsave(common->lock, flags);
+ reg = readl(common->base + sdm->pat1_reg);
+ writel(reg & ~sdm->pat1_enable, common->base + sdm->pat1_reg);
+ spin_unlock_irqrestore(common->lock, flags);
+ }
spin_lock_irqsave(common->lock, flags);
- reg = readl(common->base + sdm->tuning_reg);
- writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg);
+ reg = readl(common->base + sdm->pat0_reg);
+ writel(reg & ~sdm->pat0_enable, common->base + sdm->pat0_reg);
spin_unlock_irqrestore(common->lock, flags);
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, "SUNXI_CCU");
@@ -123,7 +145,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
pr_debug("%s: clock is sigma-delta modulated\n",
clk_hw_get_name(&common->hw));
- reg = readl(common->base + sdm->tuning_reg);
+ reg = readl(common->base + sdm->pat0_reg);
pr_debug("%s: pattern reg is 0x%x",
clk_hw_get_name(&common->hw), reg);
diff --git a/drivers/clk/sunxi-ng/ccu_sdm.h b/drivers/clk/sunxi-ng/ccu_sdm.h
index c1a7159b89c31..e94cef141c7de 100644
--- a/drivers/clk/sunxi-ng/ccu_sdm.h
+++ b/drivers/clk/sunxi-ng/ccu_sdm.h
@@ -33,21 +33,28 @@ struct ccu_sdm_internal {
u32 table_size;
/* early SoCs don't have the SDM enable bit in the PLL register */
u32 enable;
- /* second enable bit in tuning register */
- u32 tuning_enable;
- u16 tuning_reg;
+ /* second enable bit in pattern0 register */
+ u32 pat0_enable;
+ u16 pat0_reg;
+ /* on some platforms, the sdm enable bit in pattern1 register */
+ u32 pat1_enable;
+ u16 pat1_reg;
};
-#define _SUNXI_CCU_SDM(_table, _enable, \
- _reg, _reg_enable) \
- { \
- .table = _table, \
- .table_size = ARRAY_SIZE(_table), \
- .enable = _enable, \
- .tuning_enable = _reg_enable, \
- .tuning_reg = _reg, \
+#define _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, _pat1, _pat1_enable) \
+ { \
+ .table = _table, \
+ .table_size = ARRAY_SIZE(_table), \
+ .enable = _enable, \
+ .pat0_enable = _pat0_enable, \
+ .pat0_reg = _pat0, \
+ .pat1_enable = _pat1_enable, \
+ .pat1_reg = _pat1, \
}
+#define _SUNXI_CCU_SDM(_table, _enable, _pat0, _pat0_enable) \
+ _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, 0, 0)
+
bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
struct ccu_sdm_internal *sdm);
void ccu_sdm_helper_enable(struct ccu_common *common,
diff --git a/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h b/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h
new file mode 100644
index 0000000000000..81924cba58ec6
--- /dev/null
+++ b/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ *
+ * The user manual uses PCLK, HCLK, and MCLK suffixes for some bus clocks.
+ * These are represented here as APB, AHB, and MBUS prefixes respectively,
+ * with the bus type moved to the front of the clock name.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_
+#define _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_
+
+#define CLK_PLL_REF 0
+#define CLK_SYS_24M 1
+#define CLK_PLL_DDR 2
+#define CLK_PLL_PERIPH0_4X 3
+#define CLK_PLL_PERIPH0_2X 4
+#define CLK_PLL_PERIPH0_800M 5
+#define CLK_PLL_PERIPH0_480M 6
+#define CLK_PLL_PERIPH0_600M 7
+#define CLK_PLL_PERIPH0_400M 8
+#define CLK_PLL_PERIPH0_300M 9
+#define CLK_PLL_PERIPH0_200M 10
+#define CLK_PLL_PERIPH0_160M 11
+#define CLK_PLL_PERIPH0_150M 12
+#define CLK_PLL_PERIPH1_4X 13
+#define CLK_PLL_PERIPH1_2X 14
+#define CLK_PLL_PERIPH1_800M 15
+#define CLK_PLL_PERIPH1_480M 16
+#define CLK_PLL_PERIPH1_600M 17
+#define CLK_PLL_PERIPH1_400M 18
+#define CLK_PLL_PERIPH1_300M 19
+#define CLK_PLL_PERIPH1_200M 20
+#define CLK_PLL_PERIPH1_160M 21
+#define CLK_PLL_PERIPH1_150M 22
+#define CLK_PLL_GPU0 23
+#define CLK_PLL_VIDEO0 24
+#define CLK_PLL_VIDEO0_4X 25
+#define CLK_PLL_VIDEO0_3X 26
+#define CLK_PLL_VIDEO1 27
+#define CLK_PLL_VIDEO1_4X 28
+#define CLK_PLL_VIDEO1_3X 29
+#define CLK_PLL_VIDEO2 30
+#define CLK_PLL_VIDEO2_4X 31
+#define CLK_PLL_VIDEO2_3X 32
+#define CLK_PLL_VE0 33
+#define CLK_PLL_VE1 34
+#define CLK_PLL_AUDIO0_4X 35
+#define CLK_PLL_AUDIO1 36
+#define CLK_PLL_AUDIO1_DIV2 37
+#define CLK_PLL_AUDIO1_DIV5 38
+#define CLK_PLL_NPU 39
+#define CLK_PLL_DE 40
+#define CLK_PLL_DE_4X 41
+#define CLK_PLL_DE_3X 42
+#define CLK_AHB 43
+#define CLK_APB0 44
+#define CLK_APB1 45
+#define CLK_APB_UART 46
+#define CLK_TRACE 47
+#define CLK_GIC 48
+#define CLK_BUS_ITS_PCIE0_ACLK 49
+#define CLK_MBUS 50
+#define CLK_MBUS_IOMMU0_SYS 51
+#define CLK_APB_IOMMU0_SYS 52
+#define CLK_AHB_IOMMU0_SYS 53
+#define CLK_BUS_MSI_LITE0 54
+#define CLK_BUS_MSI_LITE1 55
+#define CLK_BUS_MSI_LITE2 56
+#define CLK_MBUS_IOMMU1_SYS 57
+#define CLK_APB_IOMMU1_SYS 58
+#define CLK_AHB_IOMMU1_SYS 59
+#define CLK_AHB_VE_DEC 60
+#define CLK_AHB_VE_ENC 61
+#define CLK_AHB_VID_IN 62
+#define CLK_AHB_VID_COUT0 63
+#define CLK_AHB_VID_COUT1 64
+#define CLK_AHB_DE 65
+#define CLK_AHB_NPU 66
+#define CLK_AHB_GPU0 67
+#define CLK_AHB_SERDES 68
+#define CLK_AHB_USB_SYS 69
+#define CLK_AHB_MSI_LITE0 70
+#define CLK_AHB_STORE 71
+#define CLK_AHB_CPUS 72
+#define CLK_MBUS_IOMMU0 73
+#define CLK_MBUS_IOMMU1 74
+#define CLK_MBUS_DESYS 75
+#define CLK_MBUS_VE_ENC0_GATE 76
+#define CLK_MBUS_VE_DEC0_GATE 77
+#define CLK_MBUS_GPU0 78
+#define CLK_MBUS_NPU 79
+#define CLK_MBUS_VID_IN 80
+#define CLK_MBUS_SERDES 81
+#define CLK_MBUS_MSI_LITE0 82
+#define CLK_MBUS_STORE 83
+#define CLK_MBUS_MSI_LITE2 84
+#define CLK_MBUS_DMA0 85
+#define CLK_MBUS_VE_ENC0 86
+#define CLK_MBUS_CE 87
+#define CLK_MBUS_DMA1 88
+#define CLK_MBUS_NAND0 89
+#define CLK_MBUS_CSI 90
+#define CLK_MBUS_ISP 91
+#define CLK_MBUS_GMAC0 92
+#define CLK_MBUS_GMAC1 93
+#define CLK_MBUS_VE_DEC0 94
+#define CLK_BUS_DMA0 95
+#define CLK_BUS_DMA1 96
+#define CLK_BUS_SPINLOCK 97
+#define CLK_BUS_MSGBOX0 98
+#define CLK_BUS_PWM0 99
+#define CLK_BUS_PWM1 100
+#define CLK_BUS_DBG 101
+#define CLK_BUS_SYSDAP 102
+#define CLK_TIMER0 103
+#define CLK_TIMER1 104
+#define CLK_TIMER2 105
+#define CLK_TIMER3 106
+#define CLK_TIMER4 107
+#define CLK_TIMER5 108
+#define CLK_TIMER6 109
+#define CLK_TIMER7 110
+#define CLK_TIMER8 111
+#define CLK_TIMER9 112
+#define CLK_BUS_TIMER 113
+#define CLK_AVS 114
+#define CLK_DE0 115
+#define CLK_BUS_DE0 116
+#define CLK_DI 117
+#define CLK_BUS_DI 118
+#define CLK_G2D 119
+#define CLK_BUS_G2D 120
+#define CLK_EINK 121
+#define CLK_EINK_PANEL 122
+#define CLK_BUS_EINK 123
+#define CLK_VE_ENC0 124
+#define CLK_VE_DEC0 125
+#define CLK_BUS_VE_ENC0 126
+#define CLK_BUS_VE_DEC0 127
+#define CLK_CE 128
+#define CLK_BUS_CE 129
+#define CLK_BUS_CE_SYS 130
+#define CLK_NPU 131
+#define CLK_BUS_NPU 132
+#define CLK_GPU0 133
+#define CLK_BUS_GPU0 134
+#define CLK_DRAM0 135
+#define CLK_BUS_DRAM0 136
+#define CLK_NAND0_CLK0 137
+#define CLK_NAND0_CLK1 138
+#define CLK_BUS_NAND0 139
+#define CLK_MMC0 140
+#define CLK_BUS_MMC0 141
+#define CLK_MMC1 142
+#define CLK_BUS_MMC1 143
+#define CLK_MMC2 144
+#define CLK_BUS_MMC2 145
+#define CLK_MMC3 146
+#define CLK_BUS_MMC3 147
+#define CLK_UFS_AXI 148
+#define CLK_UFS_CFG 149
+#define CLK_BUS_UFS 150
+#define CLK_BUS_UART0 151
+#define CLK_BUS_UART1 152
+#define CLK_BUS_UART2 153
+#define CLK_BUS_UART3 154
+#define CLK_BUS_UART4 155
+#define CLK_BUS_UART5 156
+#define CLK_BUS_UART6 157
+#define CLK_BUS_I2C0 158
+#define CLK_BUS_I2C1 159
+#define CLK_BUS_I2C2 160
+#define CLK_BUS_I2C3 161
+#define CLK_BUS_I2C4 162
+#define CLK_BUS_I2C5 163
+#define CLK_BUS_I2C6 164
+#define CLK_BUS_I2C7 165
+#define CLK_BUS_I2C8 166
+#define CLK_BUS_I2C9 167
+#define CLK_BUS_I2C10 168
+#define CLK_BUS_I2C11 169
+#define CLK_BUS_I2C12 170
+#define CLK_SPI0 171
+#define CLK_BUS_SPI0 172
+#define CLK_SPI1 173
+#define CLK_BUS_SPI1 174
+#define CLK_SPI2 175
+#define CLK_BUS_SPI2 176
+#define CLK_SPIF 177
+#define CLK_BUS_SPIF 178
+#define CLK_SPI3 179
+#define CLK_BUS_SPI3 180
+#define CLK_SPI4 181
+#define CLK_BUS_SPI4 182
+#define CLK_GPADC0_24M 183
+#define CLK_BUS_GPADC0 184
+#define CLK_BUS_THS0 185
+#define CLK_IRRX 186
+#define CLK_BUS_IRRX 187
+#define CLK_IRTX 188
+#define CLK_BUS_IRTX 189
+#define CLK_BUS_LRADC 190
+#define CLK_SGPIO 191
+#define CLK_BUS_SGPIO 192
+#define CLK_LPC 193
+#define CLK_BUS_LPC 194
+#define CLK_I2SPCM0 195
+#define CLK_BUS_I2SPCM0 196
+#define CLK_I2SPCM1 197
+#define CLK_BUS_I2SPCM1 198
+#define CLK_I2SPCM2 199
+#define CLK_I2SPCM2_ASRC 200
+#define CLK_BUS_I2SPCM2 201
+#define CLK_I2SPCM3 202
+#define CLK_BUS_I2SPCM3 203
+#define CLK_I2SPCM4 204
+#define CLK_BUS_I2SPCM4 205
+#define CLK_SPDIF_TX 206
+#define CLK_SPDIF_RX 207
+#define CLK_BUS_SPDIF 208
+#define CLK_DMIC 209
+#define CLK_BUS_DMIC 210
+#define CLK_USB_OHCI0 211
+#define CLK_BUS_OHCI0 212
+#define CLK_BUS_EHCI0 213
+#define CLK_BUS_OTG 214
+#define CLK_USB_OHCI1 215
+#define CLK_BUS_OHCI1 216
+#define CLK_BUS_EHCI1 217
+#define CLK_USB01_REF 218
+#define CLK_USB2_U2_REF 219
+#define CLK_USB2_SUSPEND 220
+#define CLK_USB2_MF 221
+#define CLK_USB2_U3_UTMI 222
+#define CLK_USB2_U2_PIPE 223
+#define CLK_PCIE_AUX 224
+#define CLK_PCIE_AXI_SLV 225
+#define CLK_SERDES_PHY 226
+#define CLK_GMAC_PTP 227
+#define CLK_GMAC0_PHY 228
+#define CLK_BUS_GMAC0 229
+#define CLK_GMAC1_PHY 230
+#define CLK_BUS_GMAC1 231
+#define CLK_TCON_LCD0 232
+#define CLK_BUS_TCON_LCD0 233
+#define CLK_TCON_LCD1 234
+#define CLK_BUS_TCON_LCD1 235
+#define CLK_TCON_LCD2 236
+#define CLK_BUS_TCON_LCD2 237
+#define CLK_DSI0 238
+#define CLK_BUS_DSI0 239
+#define CLK_DSI1 240
+#define CLK_BUS_DSI1 241
+#define CLK_COMBPHY0 242
+#define CLK_COMBPHY1 243
+#define CLK_BUS_TCON_TV0 244
+#define CLK_BUS_TCON_TV1 245
+#define CLK_EDP_TV 246
+#define CLK_BUS_EDP_TV 247
+#define CLK_HDMI_CEC_32K 248
+#define CLK_HDMI_CEC 249
+#define CLK_HDMI_TV 250
+#define CLK_BUS_HDMI_TV 251
+#define CLK_HDMI_SFR 252
+#define CLK_HDCP_ESM 253
+#define CLK_BUS_DPSS_TOP0 254
+#define CLK_BUS_DPSS_TOP1 255
+#define CLK_LEDC 256
+#define CLK_BUS_LEDC 257
+#define CLK_BUS_DSC 258
+#define CLK_CSI_MASTER0 259
+#define CLK_CSI_MASTER1 260
+#define CLK_CSI_MASTER2 261
+#define CLK_CSI 262
+#define CLK_BUS_CSI 263
+#define CLK_ISP 264
+#define CLK_RES_DCAP_24M 265
+#define CLK_APB2JTAG 266
+#define CLK_FANOUT_24M 267
+#define CLK_FANOUT_12M 268
+#define CLK_FANOUT_16M 269
+#define CLK_FANOUT_25M 270
+#define CLK_FANOUT_27M 271
+#define CLK_FANOUT_PCLK 272
+#define CLK_FANOUT0 273
+#define CLK_FANOUT1 274
+#define CLK_FANOUT2 275
+#define CLK_FANOUT3 276
+
+#endif /* _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_ */
diff --git a/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h b/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h
new file mode 100644
index 0000000000000..401a1e66e8047
--- /dev/null
+++ b/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_
+#define _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_
+
+#define CLK_R_AHB 0
+#define CLK_R_APB0 1
+#define CLK_R_APB1 2
+#define CLK_R_TIMER0 3
+#define CLK_R_TIMER1 4
+#define CLK_R_TIMER2 5
+#define CLK_R_TIMER3 6
+#define CLK_BUS_R_TIMER 7
+#define CLK_R_PWM 8
+#define CLK_BUS_R_PWM 9
+#define CLK_R_SPI 10
+#define CLK_BUS_R_SPI 11
+#define CLK_BUS_R_MSGBOX 12
+#define CLK_BUS_R_UART0 13
+#define CLK_BUS_R_UART1 14
+#define CLK_BUS_R_I2C0 15
+#define CLK_BUS_R_I2C1 16
+#define CLK_BUS_R_I2C2 17
+#define CLK_BUS_R_PPU 18
+#define CLK_BUS_R_TZMA 19
+#define CLK_BUS_R_CPU_BIST 20
+#define CLK_R_IR_RX 21
+#define CLK_BUS_R_IR_RX 22
+#define CLK_BUS_R_RTC 23
+#define CLK_R_RISCV 24
+#define CLK_BUS_R_RISCV 25
+#define CLK_BUS_R_RISCV_CFG 26
+#define CLK_BUS_R_CPUCFG 27
+
+#endif /* _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h b/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h
new file mode 100644
index 0000000000000..a4db2f673bd03
--- /dev/null
+++ b/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_
+#define _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_
+
+#define RST_BUS_ITS_PCIE0 0
+#define RST_BUS_IOMMU0_SYS 1
+#define RST_BUS_MSI_LITE0_AHB 2
+#define RST_BUS_MSI_LITE0_MBUS 3
+#define RST_BUS_MSI_LITE1_AHB 4
+#define RST_BUS_MSI_LITE1_MBUS 5
+#define RST_BUS_MSI_LITE2_AHB 6
+#define RST_BUS_MSI_LITE2_MBUS 7
+#define RST_BUS_IOMMU1_SYS 8
+#define RST_BUS_DMA0 9
+#define RST_BUS_DMA1 10
+#define RST_BUS_SPINLOCK 11
+#define RST_BUS_MSGBOX 12
+#define RST_BUS_PWM0 13
+#define RST_BUS_PWM1 14
+#define RST_BUS_DBG 15
+#define RST_BUS_SYSDAP 16
+#define RST_BUS_TIMER0 17
+#define RST_BUS_DE0 18
+#define RST_BUS_DI 19
+#define RST_BUS_G2D 20
+#define RST_BUS_EINK 21
+#define RST_BUS_DE_SYS 22
+#define RST_BUS_VE_ENC0 23
+#define RST_BUS_VE_DEC0 24
+#define RST_BUS_CE 25
+#define RST_BUS_CE_SYS 26
+#define RST_BUS_NPU_CORE 27
+#define RST_BUS_NPU_AXI 28
+#define RST_BUS_NPU_AHB 29
+#define RST_BUS_NPU_SRAM 30
+#define RST_BUS_GPU0 31
+#define RST_BUS_DRAM0 32
+#define RST_BUS_NAND0 33
+#define RST_BUS_MMC0 34
+#define RST_BUS_MMC1 35
+#define RST_BUS_MMC2 36
+#define RST_BUS_MMC3 37
+#define RST_BUS_UFS_AHB 38
+#define RST_BUS_UFS_AXI 39
+#define RST_BUS_UFS_PHY 40
+#define RST_BUS_UFS_CORE 41
+#define RST_BUS_UART0 42
+#define RST_BUS_UART1 43
+#define RST_BUS_UART2 44
+#define RST_BUS_UART3 45
+#define RST_BUS_UART4 46
+#define RST_BUS_UART5 47
+#define RST_BUS_UART6 48
+#define RST_BUS_I2C0 49
+#define RST_BUS_I2C1 50
+#define RST_BUS_I2C2 51
+#define RST_BUS_I2C3 52
+#define RST_BUS_I2C4 53
+#define RST_BUS_I2C5 54
+#define RST_BUS_I2C6 55
+#define RST_BUS_I2C7 56
+#define RST_BUS_I2C8 57
+#define RST_BUS_I2C9 58
+#define RST_BUS_I2C10 59
+#define RST_BUS_I2C11 60
+#define RST_BUS_I2C12 61
+#define RST_BUS_SPI0 62
+#define RST_BUS_SPI1 63
+#define RST_BUS_SPI2 64
+#define RST_BUS_SPIF 65
+#define RST_BUS_SPI3 66
+#define RST_BUS_SPI4 67
+#define RST_BUS_GPADC0 68
+#define RST_BUS_THS0 69
+#define RST_BUS_IRRX 70
+#define RST_BUS_IRTX 71
+#define RST_BUS_LRADC 72
+#define RST_BUS_SGPIO 73
+#define RST_BUS_LPC 74
+#define RST_BUS_I2SPCM0 75
+#define RST_BUS_I2SPCM1 76
+#define RST_BUS_I2SPCM2 77
+#define RST_BUS_I2SPCM3 78
+#define RST_BUS_I2SPCM4 79
+#define RST_BUS_SPDIF 80
+#define RST_BUS_DMIC 81
+#define RST_USB_PHY0 82
+#define RST_BUS_OHCI0 83
+#define RST_BUS_EHCI0 84
+#define RST_BUS_OTG 85
+#define RST_USB_PHY1 86
+#define RST_BUS_OHCI1 87
+#define RST_BUS_EHCI1 88
+#define RST_BUS_USB2 89
+#define RST_BUS_PCIE_PWRUP 90
+#define RST_BUS_PCIE 91
+#define RST_BUS_SERDES 92
+#define RST_BUS_GMAC0 93
+#define RST_BUS_GMAC0_AXI 94
+#define RST_BUS_GMAC1 95
+#define RST_BUS_GMAC1_AXI 96
+#define RST_BUS_TCON_LCD0 97
+#define RST_BUS_TCON_LCD1 98
+#define RST_BUS_TCON_LCD2 99
+#define RST_BUS_LVDS0 100
+#define RST_BUS_LVDS1 101
+#define RST_BUS_DSI0 102
+#define RST_BUS_DSI1 103
+#define RST_BUS_TCON_TV0 104
+#define RST_BUS_TCON_TV1 105
+#define RST_BUS_EDP 106
+#define RST_BUS_HDMI_MAIN 107
+#define RST_BUS_HDMI_SUB 108
+#define RST_BUS_HDMI_HDCP 109
+#define RST_BUS_DPSS_TOP0 110
+#define RST_BUS_DPSS_TOP1 111
+#define RST_BUS_VIDEO_OUT0 112
+#define RST_BUS_VIDEO_OUT1 113
+#define RST_BUS_LEDC 114
+#define RST_BUS_DSC 115
+#define RST_BUS_CSI 116
+#define RST_BUS_VIDEO_IN 117
+#define RST_BUS_APB2JTAG 118
+
+#endif /* _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_ */
diff --git a/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h b/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h
new file mode 100644
index 0000000000000..69fc7d405e1d1
--- /dev/null
+++ b/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_
+#define _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_
+
+#define RST_BUS_R_TIMER 0
+#define RST_BUS_R_PWM 1
+#define RST_BUS_R_SPI 2
+#define RST_BUS_R_MSGBOX 3
+#define RST_BUS_R_UART0 4
+#define RST_BUS_R_UART1 5
+#define RST_BUS_R_I2C0 6
+#define RST_BUS_R_I2C1 7
+#define RST_BUS_R_I2C2 8
+#define RST_BUS_R_IR_RX 9
+#define RST_BUS_R_RTC 10
+#define RST_BUS_R_RISCV_CFG 11
+#define RST_BUS_R_CPUCFG 12
+
+#endif /* _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_ */
|
| 3/2 | 2026/10/09 19:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 67482 output: 19 thoughts: 597 Thoughts: **Analyzing the Allwinner A733 CCU Patch for amd64** Okay, so this patch is adding support for the Allwinner A733 CCU and R_CCU clock controllers. It looks like it's touching `drivers/clk/sunxi-ng/ccu_sdm.c`, `drivers/clk/sunxi-ng/ccu_sdm.h`, and adding `drivers/clk/sunxi-ng/ccu-sun60i-a733.c` and `drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c`, plus some Device Tree bindings. My initial thought is to analyze the reachability, especially given the target architecture is `amd64`. First, the architecture is amd64, which is a key consideration. I need to check the relevant `Kconfig` files. Looking at `drivers/clk/sunxi-ng/Kconfig`, I see the configurations `SUN60I_A733_CCU` and `SUN60I_A733_R_CCU`. They both depend on `ARM64 || COMPILE_TEST`. Alright, so it's clearly designed for ARM64 SoCs, specifically Allwinner (sunxi) SoCs. Now, the crucial question: can this *actually* run on amd64 in something like QEMU? In a standard virtualized environment (think GCE or QEMU), with software-emulated devices (USB, netdev, tun/tap), I have to ask: does QEMU x86_64 *even* emulate or provide hardware or platform devices specifically for the Allwinner A733? This is a SoC platform driver, identified by the compatible strings `allwinner,sun60i-a733-ccu` and `allwinner,sun60i-a733-r-ccu` in the code, so it is tightly coupled to the hardware. The answer, I suspect, is no. There's almost certainly no DT node or emulated Allwinner A733 SoC hardware exposed in an amd64 QEMU environment. This strongly indicates this patch won't be directly applicable or testable on the target architecture. But just to be sure, what about `ccu_sdm.c`? It's a key part of the codebase being changed. I should grep the entire kernel source to understand what's using it, to be sure I am not missing any cross-architecture implications. |
| 4/2 | 2026/10/09 19:37 | tool | grepper |
0mArgs:{
"Expression": "ccu_sdm"
}Results: {
"Output": "\nFull output is too long, showing 200 out of 244 lines.\nUse more precise expression or PathPrefixes if possible.\n\nNumber of matching lines per file (22 files in total):\ndrivers/clk/sunxi-ng/Makefile:1\ndrivers/clk/sunxi-ng/ccu-sun20i-d1.c:1\ndrivers/clk/sunxi-ng/ccu-sun4i-a10.c:2\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c:2\ndrivers/clk/sunxi-ng/ccu-sun50i-a64.c:1\ndrivers/clk/sunxi-ng/ccu-sun50i-h6.c:1\ndrivers/clk/sunxi-ng/ccu-sun50i-h616.c:1\ndrivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c:1\ndrivers/clk/sunxi-ng/ccu-sun55i-a523.c:1\ndrivers/clk/sunxi-ng/ccu-sun5i.c:2\ndrivers/clk/sunxi-ng/ccu-sun60i-a733.c:1\ndrivers/clk/sunxi-ng/ccu-sun6i-a31.c:2\ndrivers/clk/sunxi-ng/ccu-sun8i-a23.c:2\ndrivers/clk/sunxi-ng/ccu-sun8i-a33.c:1\ndrivers/clk/sunxi-ng/ccu-sun8i-a83t.c:1\ndrivers/clk/sunxi-ng/ccu-sun8i-h3.c:2\ndrivers/clk/sunxi-ng/ccu-sun8i-r40.c:1\ndrivers/clk/sunxi-ng/ccu-sun8i-v3s.c:1\ndrivers/clk/sunxi-ng/ccu_nm.c:7\ndrivers/clk/sunxi-ng/ccu_nm.h:2\ndrivers/clk/sunxi-ng/ccu_sdm.c:19\ndrivers/clk/sunxi-ng/ccu_sdm.h:15\n\ndrivers/clk/sunxi-ng/Makefile=16=sunxi-ccu-y\t\t\t+= ccu_phase.o\ndrivers/clk/sunxi-ng/Makefile:17:sunxi-ccu-y\t\t\t+= ccu_sdm.o\ndrivers/clk/sunxi-ng/Makefile-18-\n--\ndrivers/clk/sunxi-ng/ccu-sun20i-d1.c=150=static struct ccu_nkmp pll_ve_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun20i-d1.c-170-#define SUN20I_D1_PLL_AUDIO0_REG\t\t0x078\ndrivers/clk/sunxi-ng/ccu-sun20i-d1.c:171:static struct ccu_sdm_setting pll_audio0_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun20i-d1.c-172-\t{ .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },\n--\ndrivers/clk/sunxi-ng/ccu-sun4i-a10.c-25-#include \"ccu_phase.h\"\ndrivers/clk/sunxi-ng/ccu-sun4i-a10.c:26:#include \"ccu_sdm.h\"\ndrivers/clk/sunxi-ng/ccu-sun4i-a10.c-27-\n--\ndrivers/clk/sunxi-ng/ccu-sun4i-a10.c=30=static struct ccu_nkmp pll_core_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun4i-a10.c-58-\ndrivers/clk/sunxi-ng/ccu-sun4i-a10.c:59:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun4i-a10.c-60-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c=176=static struct ccu_nkmp pll_ve_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c-195-#define SUN50I_A100_PLL_COM_REG\t\t0x060\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c:196:static struct ccu_sdm_setting pll_com_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c-197-\t{ .rate = 451584000, .pattern = 0xc0014396, .m = 2, .n = 37 },\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c=217=static struct ccu_nm pll_video3_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c-238-#define SUN50I_A100_PLL_AUDIO_REG\t\t0x078\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c:239:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun50i-a100.c-240-\t{ .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-a64.c=26=static struct ccu_nkmp pll_cpux_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-a64.c-55-\ndrivers/clk/sunxi-ng/ccu-sun50i-a64.c:56:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun50i-a64.c-57-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-h6.c=184=static struct ccu_nkmp pll_hsic_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-h6.c-206-\ndrivers/clk/sunxi-ng/ccu-sun50i-h6.c:207:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun50i-h6.c-208-\t{ .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-h616.c=204=static struct ccu_nkmp pll_de_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun50i-h616.c-224- */\ndrivers/clk/sunxi-ng/ccu-sun50i-h616.c:225:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun50i-h616.c-226-\t{ .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 },\n--\ndrivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c=34=static const struct clk_parent_data apb[] = {\n--\ndrivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c-38-#define SUN55I_A523_PLL_AUDIO1_REG\t0x00c\ndrivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c:39:static struct ccu_sdm_setting pll_audio1_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c-40-\t{ .rate = 2167603200, .pattern = 0xa000a234, .m = 1, .n = 90 }, /* div2-\u003e22.5792 */\n--\ndrivers/clk/sunxi-ng/ccu-sun55i-a523.c=279=static CLK_FIXED_FACTOR_HWS(pll_video3_3x_clk, \"pll-video3-3x\",\n--\ndrivers/clk/sunxi-ng/ccu-sun55i-a523.c-289-#define SUN55I_A523_PLL_AUDIO0_REG\t\t0x078\ndrivers/clk/sunxi-ng/ccu-sun55i-a523.c:290:static struct ccu_sdm_setting pll_audio0_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun55i-a523.c-291-\t{ .rate = 90316800, .pattern = 0xc000872b, .m = 20, .n = 75 },\n--\ndrivers/clk/sunxi-ng/ccu-sun5i.c-21-#include \"ccu_phase.h\"\ndrivers/clk/sunxi-ng/ccu-sun5i.c:22:#include \"ccu_sdm.h\"\ndrivers/clk/sunxi-ng/ccu-sun5i.c-23-\n--\ndrivers/clk/sunxi-ng/ccu-sun5i.c=26=static struct ccu_nkmp pll_core_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun5i.c-54-\ndrivers/clk/sunxi-ng/ccu-sun5i.c:55:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun5i.c-56-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu-sun60i-a733.c=336=static struct ccu_nkmp pll_ve1_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun60i-a733.c-357-#define SUN60I_A733_PLL_AUDIO0_REG\t0x260\ndrivers/clk/sunxi-ng/ccu-sun60i-a733.c:358:static struct ccu_sdm_setting pll_audio0_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun60i-a733.c-359-\t{ .rate = 90316800, .pattern = 0xa002872b, .m = 20, .n = 75 }, /* 22.5792 * 4 */\n--\ndrivers/clk/sunxi-ng/ccu-sun6i-a31.c-27-#include \"ccu_phase.h\"\ndrivers/clk/sunxi-ng/ccu-sun6i-a31.c:28:#include \"ccu_sdm.h\"\ndrivers/clk/sunxi-ng/ccu-sun6i-a31.c-29-\n--\ndrivers/clk/sunxi-ng/ccu-sun6i-a31.c=32=static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, \"pll-cpu\",\n--\ndrivers/clk/sunxi-ng/ccu-sun6i-a31.c-54-\ndrivers/clk/sunxi-ng/ccu-sun6i-a31.c:55:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun6i-a31.c-56-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-a23.c-22-#include \"ccu_phase.h\"\ndrivers/clk/sunxi-ng/ccu-sun8i-a23.c:23:#include \"ccu_sdm.h\"\ndrivers/clk/sunxi-ng/ccu-sun8i-a23.c-24-\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-a23.c=28=static struct ccu_nkmp pll_cpux_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-a23.c-58-\ndrivers/clk/sunxi-ng/ccu-sun8i-a23.c:59:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun8i-a23.c-60-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-a33.c=26=static struct ccu_nkmp pll_cpux_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-a33.c-56-\ndrivers/clk/sunxi-ng/ccu-sun8i-a33.c:57:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun8i-a33.c-58-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-a83t.c=50=static struct ccu_mult pll_c1cpux_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-a83t.c-72-/* clock rates doubled for post divider */\ndrivers/clk/sunxi-ng/ccu-sun8i-a83t.c:73:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun8i-a83t.c-74-\t{ .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-h3.c-23-#include \"ccu_phase.h\"\ndrivers/clk/sunxi-ng/ccu-sun8i-h3.c:24:#include \"ccu_sdm.h\"\ndrivers/clk/sunxi-ng/ccu-sun8i-h3.c-25-\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-h3.c=28=static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, \"pll-cpux\",\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-h3.c-51-\ndrivers/clk/sunxi-ng/ccu-sun8i-h3.c:52:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun8i-h3.c-53-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-r40.c=28=static struct ccu_nkmp pll_cpu_clk = {\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-r40.c-57-\ndrivers/clk/sunxi-ng/ccu-sun8i-r40.c:58:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun8i-r40.c-59-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-v3s.c=30=static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, \"pll-cpu\",\n--\ndrivers/clk/sunxi-ng/ccu-sun8i-v3s.c-53-\ndrivers/clk/sunxi-ng/ccu-sun8i-v3s.c:54:static struct ccu_sdm_setting pll_audio_sdm_table[] = {\ndrivers/clk/sunxi-ng/ccu-sun8i-v3s.c-55-\t{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },\n--\ndrivers/clk/sunxi-ng/ccu_nm.c=77=static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,\n--\ndrivers/clk/sunxi-ng/ccu_nm.c-107-\ndrivers/clk/sunxi-ng/ccu_nm.c:108:\tif (ccu_sdm_helper_is_enabled(\u0026nm-\u003ecommon, \u0026nm-\u003esdm))\ndrivers/clk/sunxi-ng/ccu_nm.c:109:\t\trate = ccu_sdm_helper_read_rate(\u0026nm-\u003ecommon, \u0026nm-\u003esdm, m, n);\ndrivers/clk/sunxi-ng/ccu_nm.c-110-\telse\n--\ndrivers/clk/sunxi-ng/ccu_nm.c=119=static int ccu_nm_determine_rate(struct clk_hw *hw,\n--\ndrivers/clk/sunxi-ng/ccu_nm.c-147-\ndrivers/clk/sunxi-ng/ccu_nm.c:148:\tif (ccu_sdm_helper_has_rate(\u0026nm-\u003ecommon, \u0026nm-\u003esdm, req-\u003erate)) {\ndrivers/clk/sunxi-ng/ccu_nm.c-149-\t\tif (nm-\u003ecommon.features \u0026 CCU_FEATURE_FIXED_POSTDIV)\n--\ndrivers/clk/sunxi-ng/ccu_nm.c=168=static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,\n--\ndrivers/clk/sunxi-ng/ccu_nm.c-202-\ndrivers/clk/sunxi-ng/ccu_nm.c:203:\tif (ccu_sdm_helper_has_rate(\u0026nm-\u003ecommon, \u0026nm-\u003esdm, rate)) {\ndrivers/clk/sunxi-ng/ccu_nm.c:204:\t\tccu_sdm_helper_enable(\u0026nm-\u003ecommon, \u0026nm-\u003esdm, rate);\ndrivers/clk/sunxi-ng/ccu_nm.c-205-\ndrivers/clk/sunxi-ng/ccu_nm.c-206-\t\t/* Sigma delta modulation requires specific N and M factors */\ndrivers/clk/sunxi-ng/ccu_nm.c:207:\t\tccu_sdm_helper_get_factors(\u0026nm-\u003ecommon, \u0026nm-\u003esdm, rate,\ndrivers/clk/sunxi-ng/ccu_nm.c-208-\t\t\t\t\t \u0026_nm.m, \u0026_nm.n);\ndrivers/clk/sunxi-ng/ccu_nm.c-209-\t} else {\ndrivers/clk/sunxi-ng/ccu_nm.c:210:\t\tccu_sdm_helper_disable(\u0026nm-\u003ecommon, \u0026nm-\u003esdm);\ndrivers/clk/sunxi-ng/ccu_nm.c-211-\t\tccu_nm_find_best(\u0026nm-\u003ecommon, parent_rate, rate, \u0026_nm);\n--\ndrivers/clk/sunxi-ng/ccu_nm.h-14-#include \"ccu_mult.h\"\ndrivers/clk/sunxi-ng/ccu_nm.h:15:#include \"ccu_sdm.h\"\ndrivers/clk/sunxi-ng/ccu_nm.h-16-\n--\ndrivers/clk/sunxi-ng/ccu_nm.h=22=struct ccu_nm {\n--\ndrivers/clk/sunxi-ng/ccu_nm.h-28-\tstruct ccu_frac_internal\tfrac;\ndrivers/clk/sunxi-ng/ccu_nm.h:29:\tstruct ccu_sdm_internal\t\tsdm;\ndrivers/clk/sunxi-ng/ccu_nm.h-30-\n--\ndrivers/clk/sunxi-ng/ccu_sdm.c-9-\ndrivers/clk/sunxi-ng/ccu_sdm.c:10:#include \"ccu_sdm.h\"\ndrivers/clk/sunxi-ng/ccu_sdm.c-11-\ndrivers/clk/sunxi-ng/ccu_sdm.c:12:bool ccu_sdm_helper_is_enabled(struct ccu_common *common,\ndrivers/clk/sunxi-ng/ccu_sdm.c:13:\t\t\t struct ccu_sdm_internal *sdm)\ndrivers/clk/sunxi-ng/ccu_sdm.c-14-{\n--\ndrivers/clk/sunxi-ng/ccu_sdm.c-26-}\ndrivers/clk/sunxi-ng/ccu_sdm.c:27:EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, \"SUNXI_CCU\");\ndrivers/clk/sunxi-ng/ccu_sdm.c-28-\ndrivers/clk/sunxi-ng/ccu_sdm.c:29:void ccu_sdm_helper_enable(struct ccu_common *common,\ndrivers/clk/sunxi-ng/ccu_sdm.c:30:\t\t\t struct ccu_sdm_internal *sdm,\ndrivers/clk/sunxi-ng/ccu_sdm.c-31-\t\t\t unsigned long rate)\n--\ndrivers/clk/sunxi-ng/ccu_sdm.c-65-}\ndrivers/clk/sunxi-ng/ccu_sdm.c:66:EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, \"SUNXI_CCU\");\ndrivers/clk/sunxi-ng/ccu_sdm.c-67-\ndrivers/clk/sunxi-ng/ccu_sdm.c:68:void ccu_sdm_helper_disable(struct ccu_common *common,\ndrivers/clk/sunxi-ng/ccu_sdm.c:69:\t\t\t struct ccu_sdm_internal *sdm)\ndrivers/clk/sunxi-ng/ccu_sdm.c-70-{\n--\ndrivers/clk/sunxi-ng/ccu_sdm.c-95-}\ndrivers/clk/sunxi-ng/ccu_sdm.c:96:EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, \"SUNXI_CCU\");\ndrivers/clk/sunxi-ng/ccu_sdm.c-97-\n--\ndrivers/clk/sunxi-ng/ccu_sdm.c-114- */\ndrivers/clk/sunxi-ng/ccu_sdm.c:115:bool ccu_sdm_helper_has_rate(struct ccu_common *common,\ndrivers/clk/sunxi-ng/ccu_sdm.c:116:\t\t\t struct ccu_sdm_internal *sdm,\ndrivers/clk/sunxi-ng/ccu_sdm.c-117-\t\t\t unsigned long rate)\n--\ndrivers/clk/sunxi-ng/ccu_sdm.c-129-}\ndrivers/clk/sunxi-ng/ccu_sdm.c:130:EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_has_rate, \"SUNXI_CCU\");\n\n"
} |
| 5/2 | 2026/10/09 19:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 75232 output: 36 thoughts: 88 Thoughts: Here's my thought process, as if I were analyzing this code: **Clock Driver Investigation** Okay, so I'm looking at `drivers/clk/sunxi-ng/ccu_sdm.c`. From its location, I can see it's part of the sunxi-ccu clock driver framework. The `Makefile` confirms this: `drivers/clk/sunxi-ng/Makefile` links it in as `ccu_sdm.o` to `sunxi-ccu-y`. Now, the important question to get answered is: what creates `sunxi-ccu`? I need to understand the build process here, so I'll next check `drivers/clk/sunxi-ng/Makefile` to see how that object gets built. I need to understand the dependencies and how this clock driver fits into the larger system. |
| 6/2 | 2026/10/09 19:37 | tool | read-file |
0mArgs:{
"File": "drivers/clk/sunxi-ng/Makefile",
"FirstLine": 1,
"LineCount": 50
}Results: {
"Contents": " 1:\t# SPDX-License-Identifier: GPL-2.0\n 2:\t\n 3:\tobj-$(CONFIG_SUNXI_CCU)\t\t+= sunxi-ccu.o\n 4:\t\n 5:\t# Common objects\n 6:\tsunxi-ccu-y\t\t\t+= ccu_common.o\n 7:\tsunxi-ccu-y\t\t\t+= ccu_mmc_timing.o\n 8:\tsunxi-ccu-y\t\t\t+= ccu_reset.o\n 9:\t\n 10:\t# Base clock types\n 11:\tsunxi-ccu-y\t\t\t+= ccu_div.o\n 12:\tsunxi-ccu-y\t\t\t+= ccu_frac.o\n 13:\tsunxi-ccu-y\t\t\t+= ccu_gate.o\n 14:\tsunxi-ccu-y\t\t\t+= ccu_mux.o\n 15:\tsunxi-ccu-y\t\t\t+= ccu_mult.o\n 16:\tsunxi-ccu-y\t\t\t+= ccu_phase.o\n 17:\tsunxi-ccu-y\t\t\t+= ccu_sdm.o\n 18:\t\n 19:\t# Multi-factor clocks\n 20:\tsunxi-ccu-y\t\t\t+= ccu_nk.o\n 21:\tsunxi-ccu-y\t\t\t+= ccu_nkm.o\n 22:\tsunxi-ccu-y\t\t\t+= ccu_nkmp.o\n 23:\tsunxi-ccu-y\t\t\t+= ccu_nm.o\n 24:\tsunxi-ccu-y\t\t\t+= ccu_mp.o\n 25:\t\n 26:\t# SoC support\n 27:\tobj-$(CONFIG_SUNIV_F1C100S_CCU)\t+= suniv-f1c100s-ccu.o\n 28:\tobj-$(CONFIG_SUN20I_D1_CCU)\t+= sun20i-d1-ccu.o\n 29:\tobj-$(CONFIG_SUN20I_D1_R_CCU)\t+= sun20i-d1-r-ccu.o\n 30:\tobj-$(CONFIG_SUN50I_A64_CCU)\t+= sun50i-a64-ccu.o\n 31:\tobj-$(CONFIG_SUN50I_A100_CCU)\t+= sun50i-a100-ccu.o\n 32:\tobj-$(CONFIG_SUN50I_A100_R_CCU)\t+= sun50i-a100-r-ccu.o\n 33:\tobj-$(CONFIG_SUN50I_H6_CCU)\t+= sun50i-h6-ccu.o\n 34:\tobj-$(CONFIG_SUN50I_H6_R_CCU)\t+= sun50i-h6-r-ccu.o\n 35:\tobj-$(CONFIG_SUN50I_H616_CCU)\t+= sun50i-h616-ccu.o\n 36:\tobj-$(CONFIG_SUN55I_A523_CCU)\t+= sun55i-a523-ccu.o\n 37:\tobj-$(CONFIG_SUN55I_A523_MCU_CCU)\t+= sun55i-a523-mcu-ccu.o\n 38:\tobj-$(CONFIG_SUN55I_A523_R_CCU)\t+= sun55i-a523-r-ccu.o\n 39:\tobj-$(CONFIG_SUN60I_A733_CCU)\t+= sun60i-a733-ccu.o\n 40:\tobj-$(CONFIG_SUN60I_A733_R_CCU)\t+= sun60i-a733-r-ccu.o\n 41:\tobj-$(CONFIG_SUN4I_A10_CCU)\t+= sun4i-a10-ccu.o\n 42:\tobj-$(CONFIG_SUN5I_CCU)\t\t+= sun5i-ccu.o\n 43:\tobj-$(CONFIG_SUN6I_A31_CCU)\t+= sun6i-a31-ccu.o\n 44:\tobj-$(CONFIG_SUN6I_RTC_CCU)\t+= sun6i-rtc-ccu.o\n 45:\tobj-$(CONFIG_SUN8I_A23_CCU)\t+= sun8i-a23-ccu.o\n 46:\tobj-$(CONFIG_SUN8I_A33_CCU)\t+= sun8i-a33-ccu.o\n 47:\tobj-$(CONFIG_SUN8I_A83T_CCU)\t+= sun8i-a83t-ccu.o\n 48:\tobj-$(CONFIG_SUN8I_H3_CCU)\t+= sun8i-h3-ccu.o\n 49:\tobj-$(CONFIG_SUN8I_R40_CCU)\t+= sun8i-r40-ccu.o\n 50:\tobj-$(CONFIG_SUN8I_V3S_CCU)\t+= sun8i-v3s-ccu.o\n"
} |
| 7/2 | 2026/10/09 19:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 76896 output: 37 thoughts: 17 Thoughts: Here's my take on those thoughts: **Clock Driver Configuration Review** Alright, let's dive in. My immediate thought is to check the `drivers/clk/sunxi-ng/Kconfig` file. This is where I'd expect to find the configuration options for the Sunxi-NG clock drivers. I need to understand what's been defined, what's available for enabling/disabling various clock sources and controllers, and any dependencies between them. I'm looking for the core options related to clock tree configuration for these Allwinner SoCs. Specifically, I need to understand how the build process handles the clock drivers, and what configurability is provided. Let's see what we can find. |
| 8/2 | 2026/10/09 19:37 | tool | read-file |
0mArgs:{
"File": "drivers/clk/sunxi-ng/Kconfig",
"FirstLine": 1,
"LineCount": 80
}Results: {
"Contents": " 1:\t# SPDX-License-Identifier: GPL-2.0-only\n 2:\tconfig SUNXI_CCU\n 3:\t\ttristate \"Clock support for Allwinner SoCs\"\n 4:\t\tdepends on ARCH_SUNXI || COMPILE_TEST\n 5:\t\tselect RESET_CONTROLLER\n 6:\t\tdefault ARCH_SUNXI\n 7:\t\n 8:\tif SUNXI_CCU\n 9:\t\n 10:\tconfig SUNIV_F1C100S_CCU\n 11:\t\ttristate \"Support for the Allwinner newer F1C100s CCU\"\n 12:\t\tdefault ARCH_SUNXI\n 13:\t\tdepends on MACH_SUNIV || COMPILE_TEST\n 14:\t\n 15:\tconfig SUN20I_D1_CCU\n 16:\t\ttristate \"Support for the Allwinner D1/R528/T113 CCU\"\n 17:\t\tdefault ARCH_SUNXI\n 18:\t\tdepends on MACH_SUN8I || RISCV || COMPILE_TEST\n 19:\t\n 20:\tconfig SUN20I_D1_R_CCU\n 21:\t\ttristate \"Support for the Allwinner D1/R528/T113 PRCM CCU\"\n 22:\t\tdefault ARCH_SUNXI\n 23:\t\tdepends on MACH_SUN8I || RISCV || COMPILE_TEST\n 24:\t\n 25:\tconfig SUN50I_A64_CCU\n 26:\t\ttristate \"Support for the Allwinner A64 CCU\"\n 27:\t\tdefault ARCH_SUNXI\n 28:\t\tdepends on ARM64 || COMPILE_TEST\n 29:\t\n 30:\tconfig SUN50I_A100_CCU\n 31:\t\ttristate \"Support for the Allwinner A100 CCU\"\n 32:\t\tdefault ARCH_SUNXI\n 33:\t\tdepends on ARM64 || COMPILE_TEST\n 34:\t\n 35:\tconfig SUN50I_A100_R_CCU\n 36:\t\ttristate \"Support for the Allwinner A100 PRCM CCU\"\n 37:\t\tdefault ARCH_SUNXI\n 38:\t\tdepends on ARM64 || COMPILE_TEST\n 39:\t\n 40:\tconfig SUN50I_H6_CCU\n 41:\t\ttristate \"Support for the Allwinner H6 CCU\"\n 42:\t\tdefault ARCH_SUNXI\n 43:\t\tdepends on ARM64 || COMPILE_TEST\n 44:\t\n 45:\tconfig SUN50I_H616_CCU\n 46:\t\ttristate \"Support for the Allwinner H616 CCU\"\n 47:\t\tdefault ARCH_SUNXI\n 48:\t\tdepends on ARM64 || COMPILE_TEST\n 49:\t\n 50:\tconfig SUN50I_H6_R_CCU\n 51:\t\ttristate \"Support for the Allwinner H6 and H616 PRCM CCU\"\n 52:\t\tdefault ARCH_SUNXI\n 53:\t\tdepends on ARM64 || COMPILE_TEST\n 54:\t\n 55:\tconfig SUN55I_A523_CCU\n 56:\t\ttristate \"Support for the Allwinner A523/T527 CCU\"\n 57:\t\tdefault ARCH_SUNXI\n 58:\t\tdepends on ARM64 || COMPILE_TEST\n 59:\t\n 60:\tconfig SUN55I_A523_MCU_CCU\n 61:\t\ttristate \"Support for the Allwinner A523/T527 MCU CCU\"\n 62:\t\tdefault ARCH_SUNXI\n 63:\t\tdepends on ARM64 || COMPILE_TEST\n 64:\t\n 65:\tconfig SUN55I_A523_R_CCU\n 66:\t\ttristate \"Support for the Allwinner A523/T527 PRCM CCU\"\n 67:\t\tdefault ARCH_SUNXI\n 68:\t\tdepends on ARM64 || COMPILE_TEST\n 69:\t\n 70:\tconfig SUN60I_A733_CCU\n 71:\t\ttristate \"Support for the Allwinner A733 CCU\"\n 72:\t\tdefault ARCH_SUNXI\n 73:\t\tdepends on ARM64 || COMPILE_TEST\n 74:\t\n 75:\tconfig SUN60I_A733_R_CCU\n 76:\t\ttristate \"Support for the Allwinner A733 PRCM CCU\"\n 77:\t\tdefault ARCH_SUNXI\n 78:\t\tdepends on ARM64 || COMPILE_TEST\n 79:\t\n 80:\tconfig SUN4I_A10_CCU\n"
} |
| 9/2 | 2026/10/09 19:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 78332 output: 133 thoughts: 1608 Thoughts: **Analysis of Sunxi-ng CCU Driver Reachability on amd64** Okay, so `SUNXI_CCU` depends on `ARCH_SUNXI` or `COMPILE_TEST`. The question is: can *any* Allwinner CCU driver be reached in an amd64 QEMU or GCE environment? Let's dig into this. First, are any of these drivers capable of probing without a device tree? I need to check how the `sunxi_ccu` or its drivers are actually instantiated. It looks like all the sunxi-ng CCU drivers are platform drivers that rely on Device Tree nodes, like the `sun60i_a733_ccu_driver`, which uses a compatible string: `"allwinner,sun60i-a733-ccu"`. The important thing is, look at the driver's definition, `suppress_bind_attrs = true`! That's a huge red flag. This means even manual sysfs bind/unbind is disabled. And on amd64, there *won't be* a Device Tree with that `allwinner,sun60i-a733-ccu` node, or any sunxi CCU node for that matter. But wait, can we instantiate an OF platform device from userspace on x86? Could we use configfs for an OF overlay? OF overlay requires `CONFIG_OF_CONFIGFS`. Even if that were enabled, does anyone even *use* DT overlays on x86? Typically, OF is disabled or empty on x86 unless `COMPILE_TEST`. I need to remember what's important: *reachability* is key. Fuzzing only works on code that can actually execute in standard virtualized environments. If it's structurally unreachable, it MUST NOT be fuzzed, no matter what assertions or complex logic is in the code. The instructions say: * Code paths exclusive to architectures other than the target architecture... * Structurally unreachable hardware... like vendor-specific PCIe switches, or drivers that need physical ASICs that aren't emulated. And the target architecture *is* amd64. So, can `ccu_sdm.c`, `ccu-sun60i-a733.c`, or `ccu-sun60i-a733-r.c` be executed on amd64? No. Allwinner SoCs are ARM/ARM64 and RISC-V (D1). They are embedded SoCs. The CCU (Clock Control Unit) is the on-chip clock controller. On `amd64` (x86_64), `ARCH_SUNXI` is *not* enabled; it's only defined on ARM/ARM64/RISCV. Even with `COMPILE_TEST`, the driver would only be compile-tested. At runtime on amd64 QEMU/GCE, there won't be any Allwinner SoC devices, no matching DT nodes, and that `.suppress_bind_attrs = true` prevents driver binding via sysfs. This hardware is physically part of the Allwinner SoC silicon memory map. Let's double check by inspecting all the changes in this commit. Looks like it affects: 1. `Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml` 2. `drivers/clk/sunxi-ng/Kconfig` 3. `drivers/clk/sunxi-ng/Makefile` 4. `drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c` 5. `drivers/clk/sunxi-ng/ccu-sun60i-a733.c` 6. `drivers/clk/sunxi-ng/ccu_sdm.c` 7. `drivers/clk/sunxi-ng/ccu_sdm.h` 8. `include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h` 9. `include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h` 10. `include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h` 11. `include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h` All files are exclusively about the Allwinner sunxi-ng |
| 10/2 | 2026/10/09 19:38 | tool | set-results |
0mArgs:{
"EnableConfigs": [],
"FocusSymbols": [],
"Reasoning": "The patch adds clock control unit (CCU) drivers for the Allwinner A733 SoC (sun60i) and updates the internal sunxi-ng sigma-delta modulation helpers. All modified code is exclusive to Allwinner ARM/ARM64 SoCs (ARCH_SUNXI) and requires hardware/Device Tree nodes not present or emulated in standard amd64 QEMU/GCE environments. Because the target architecture is amd64, the modified code is structurally unreachable.",
"WorthFuzzing": false
}Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch adds clock control unit (CCU) drivers for the Allwinner A733 SoC (sun60i) and updates the internal sunxi-ng sigma-delta modulation helpers. All modified code is exclusive to Allwinner ARM/ARM64 SoCs (ARCH_SUNXI) and requires hardware/Device Tree nodes not present or emulated in standard amd64 QEMU/GCE environments. Because the target architecture is amd64, the modified code is structurally unreachable.",
"WorthFuzzing": false
} |
| 11/1 | 2026/10/09 19:38 | action | If |
0mArgs:{
"WorthFuzzing": false
}Results: null |
| Total Calls | Total Tokens | Avg Tokens | Total Duration (Seconds) | Avg Duration (Seconds) |
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| Total Calls | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|