AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/09/10 04:37	flow	patch-triage	0m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The patch adds MMIO read memory barriers (rmb) in gem_tsu_get_time() within the Cadence MACB/GEM Ethernet driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver requires vendor-specific Cadence MACB/GEM hardware (primarily found on Atmel/Xilinx SoCs) that is not available or emulated in standard amd64 virtualized fuzzing environments (QEMU/GCE), making the modified code structurally unreachable.", "WorthFuzzing": false }
1/1	2026/09/10 04:37	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit b4f7b57de5c0c01edc9e885a25ae1fd10cfec5ac\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Thu Sep 10 04:37:38 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c\nindex e5195d7dac1d5..4fb287608dc48 100644\n--- a/drivers/net/ethernet/cadence/macb_ptp.c\n+++ b/drivers/net/ethernet/cadence/macb_ptp.c\n@@ -50,7 +50,15 @@ static int gem_tsu_get_time(struct ptp_clock_info ptp, struct timespec64 ts,\n \n \tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\n \tptp_read_system_prets(sts);\n+\t/* ptp_read_system_prets() uses smp_rmb() internally,\n+\t * which does not guarantee ordering against MMIO reads.\n+\t /\n+\trmb();\n \tfirst = gem_readl(bp, TN);\n+\t/ Ensure the PHC read completes before taking\n+\t * the post timestamp.\n+\t /\n+\trmb();\n \tptp_read_system_postts(sts);\n \tsecl = gem_readl(bp, TSL);\n \tsech = gem_readl(bp, TSH);\n@@ -62,7 +70,15 @@ static int gem_tsu_get_time(struct ptp_clock_info ptp, struct timespec64 ts,\n \t\t (assume all done within 1s)\n \t\t /\n \t\tptp_read_system_prets(sts);\n+\t\t/ ptp_read_system_prets() uses smp_rmb() internally,\n+\t\t * which does not guarantee ordering against MMIO reads.\n+\t\t /\n+\t\trmb();\n \t\tts-\u003etv_nsec = gem_readl(bp, TN);\n+\t\t/ Ensure the PHC read completes before taking\n+\t\t * the post timestamp.\n+\t\t */\n+\t\trmb();\n \t\tptp_read_system_postts(sts);\n \t\tsecl = gem_readl(bp, TSL);\n \t\tsech = gem_readl(bp, TSH);\n" }
2/1	2026/09/10 04:37	agent	patch-evaluator	0m Model: core Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch adds MMIO read memory barriers (rmb) in gem_tsu_get_time() within the Cadence MACB/GEM Ethernet driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver requires vendor-specific Cadence MACB/GEM hardware (primarily found on Atmel/Xilinx SoCs) that is not available or emulated in standard amd64 virtualized fuzzing environments (QEMU/GCE), making the modified code structurally unreachable.", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer and security engineer. Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on internal assumptions. You must actively use your code access tools to inspect the actual source code, callers, and surrounding context. ================================================================================ 1. CORE TRIAGE PHILOSOPHY ================================================================================ The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs, and newly triggered assertions introduced by the patch series. - REACHABILITY IS THE PRIMARY GATE: Fuzzing can only discover bugs in code that can actually execute in standard virtualized environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap). If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed, regardless of whether it adds assertions or complex logic. - DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS: Patch authors routinely label changes as "cleanups", "refactorings", or state "No functional change intended". Do NOT take these claims at face value. Code refactorings that rearrange logic, introduce helper functions, or alter state management in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs. If reachable executable code is modified or refactored, it MUST be fuzzed. - NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED: When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON, VM_WARN_ON, BUG_ON, lockdep_assert) in reachable code paths, it enforces new or stricter invariants. Even if the author believes the invariant always holds, fuzzing is essential to verify whether an unusual sequence of operations can violate it. ================================================================================ 2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA) ================================================================================ Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories: - Non-kernel and non-executable changes: * Modifications to Documentation/, comments, or spelling fixes. * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/) that do not affect the compiled kernel image (vmlinux) or kernel modules. * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints that do not alter control flow or data structures. * Build system or Kconfig changes that do not alter compiled C logic. - Structurally unreachable hardware: * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU. - Unreachable execution paths: * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during physical PCI hot-unplug or manual sysfs driver unbinding. * Code paths exclusive to architectures other than the target architecture. ================================================================================ 3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA) ================================================================================ Return WorthFuzzing=true whenever the patch touches reachable executable code, including: - Core Subsystems: * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/), BPF, scheduler, core networking, VFS, or syscall handling. - Refactorings and Code Cleanups: * Any restructuring of reachable data structures, helper abstractions, or algorithm flows. - Runtime Assertions and Defensive Checks: * Any introduction or alteration of assertions (WARN_ON, VM_WARN_ON, BUG_ON, etc.) in reachable paths. - Reachable Drivers and Protocols: Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.). ================================================================================ 4. EXTRACTING FocusSymbols (PREVENTING DILUTION) ================================================================================ When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer: - AVOID UBIQUITOUS LIFECYCLE HOT-PATHS: Do NOT list generic, ubiquitous functions called by almost every program in the corpus (including, but not limited to: general memory allocators and deallocators, page fault and trap handlers, or core synchronization primitives; this is not an exhaustive list). Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused", which severely dilutes fuzzing effort away from the actual changes. - TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS: List functions that specifically implement the logic being added or altered, or direct API entrypoints for the subsystem feature under review. - HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h): Compiler-inlined static functions (such as static inlines in mm/.h or include/linux/.h) lack distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters. If the changes are primarily in static inline helpers, identify non-static, feature-specific caller functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers). ================================================================================ 5. IDENTIFYING EnableConfigs ================================================================================ Identify any specific CONFIG_ options required to properly compile and reach the modified code: - Inspect Kconfig files and #ifdef guards; do not make assumptions. - Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed. - Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: Target architecture: amd64 For your convenience, here is the diff of the changes: commit b4f7b57de5c0c01edc9e885a25ae1fd10cfec5ac Author: syz-cluster <triage@syzkaller.com> Date: Thu Sep 10 04:37:38 2026 +0000 syz-cluster: applied patch under review diff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c index e5195d7dac1d5..4fb287608dc48 100644 --- a/drivers/net/ethernet/cadence/macb_ptp.c +++ b/drivers/net/ethernet/cadence/macb_ptp.c @@ -50,7 +50,15 @@ static int gem_tsu_get_time(struct ptp_clock_info ptp, struct timespec64 ts, spin_lock_irqsave(&bp->tsu_clk_lock, flags); ptp_read_system_prets(sts); + /* ptp_read_system_prets() uses smp_rmb() internally, + * which does not guarantee ordering against MMIO reads. + / + rmb(); first = gem_readl(bp, TN); + / Ensure the PHC read completes before taking + * the post timestamp. + / + rmb(); ptp_read_system_postts(sts); secl = gem_readl(bp, TSL); sech = gem_readl(bp, TSH); @@ -62,7 +70,15 @@ static int gem_tsu_get_time(struct ptp_clock_info ptp, struct timespec64 ts, (assume all done within 1s) / ptp_read_system_prets(sts); + / ptp_read_system_prets() uses smp_rmb() internally, + * which does not guarantee ordering against MMIO reads. + / + rmb(); ts->tv_nsec = gem_readl(bp, TN); + / Ensure the PHC read completes before taking + * the post timestamp. + */ + rmb(); ptp_read_system_postts(sts); secl = gem_readl(bp, TSL); sech = gem_readl(bp, TSH);
3/2	2026/09/10 04:37	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 3213 output: 32 thoughts: 75 Thoughts: Initial Assessment of the Code Change Okay, so the patch is touching `drivers/net/ethernet/cadence/macb_ptp.c`. My first move is to dive into that driver code and understand its connection to the hardware and its overall functionality, especially the PTP aspect. Given the context of a fuzzing setup, my immediate concern is whether this specific Cadence MACB controller is even reachable within a standard QEMU amd64 fuzzing environment. That's a crucial first step; if it's not present, then this whole thing is a dead end for fuzzing purposes. I need to quickly establish its presence or absence within that specific test environment. I'll need to check the Kconfig, see if there's any specific hardware configuration needed, or if it's dependent on a particular machine model. I'll be looking for clues in the Kconfig to see what kind of hardware dependency we are talking about here.
4/2	2026/09/10 04:37	tool	grepper	0m Args: { "Expression": "MACB", "PathPrefix": "drivers/net/ethernet/cadence/" } Results: { "Output": "\nFull output is too long, showing 500 out of 1713 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/cadence/Kconfig=20=if NET_VENDOR_CADENCE\ndrivers/net/ethernet/cadence/Kconfig-21-\ndrivers/net/ethernet/cadence/Kconfig:22:config MACB\ndrivers/net/ethernet/cadence/Kconfig:23:\ttristate \"Cadence MACB/GEM support\"\ndrivers/net/ethernet/cadence/Kconfig-24-\tdepends on HAS_DMA \u0026\u0026 COMMON_CLK\n--\ndrivers/net/ethernet/cadence/Kconfig-28-\thelp\ndrivers/net/ethernet/cadence/Kconfig:29:\t The Cadence MACB ethernet interface is found on many Atmel AT32 and\ndrivers/net/ethernet/cadence/Kconfig-30-\t AT91 parts. This driver also supports the Cadence GEM (Gigabit\ndrivers/net/ethernet/cadence/Kconfig-31-\t Ethernet MAC found in some ARM SoC devices). Say Y to include\ndrivers/net/ethernet/cadence/Kconfig:32:\t support for the MACB/GEM chip.\ndrivers/net/ethernet/cadence/Kconfig-33-\n--\ndrivers/net/ethernet/cadence/Kconfig-36-\ndrivers/net/ethernet/cadence/Kconfig:37:config MACB_USE_HWSTAMP\ndrivers/net/ethernet/cadence/Kconfig-38-\tbool \"Use IEEE 1588 hwstamp\"\ndrivers/net/ethernet/cadence/Kconfig:39:\tdepends on MACB\ndrivers/net/ethernet/cadence/Kconfig-40-\tdepends on PTP_1588_CLOCK\n--\ndrivers/net/ethernet/cadence/Kconfig-42-\thelp\ndrivers/net/ethernet/cadence/Kconfig:43:\t Enable IEEE 1588 Precision Time Protocol (PTP) support for MACB.\ndrivers/net/ethernet/cadence/Kconfig-44-\ndrivers/net/ethernet/cadence/Kconfig:45:config MACB_PCI\ndrivers/net/ethernet/cadence/Kconfig:46:\ttristate \"Cadence PCI MACB/GEM support\"\ndrivers/net/ethernet/cadence/Kconfig:47:\tdepends on MACB \u0026\u0026 PCI\ndrivers/net/ethernet/cadence/Kconfig-48-\thelp\ndrivers/net/ethernet/cadence/Kconfig:49:\t This is PCI wrapper for MACB driver.\ndrivers/net/ethernet/cadence/Kconfig-50-\n--\ndrivers/net/ethernet/cadence/Makefile=5=macb-y\t:= macb_main.o\ndrivers/net/ethernet/cadence/Makefile-6-\ndrivers/net/ethernet/cadence/Makefile:7:ifeq ($(CONFIG_MACB_USE_HWSTAMP),y)\ndrivers/net/ethernet/cadence/Makefile-8-macb-y\t+= macb_ptp.o\ndrivers/net/ethernet/cadence/Makefile=9=endif\ndrivers/net/ethernet/cadence/Makefile-10-\ndrivers/net/ethernet/cadence/Makefile:11:obj-$(CONFIG_MACB) += macb.o\ndrivers/net/ethernet/cadence/Makefile:12:obj-$(CONFIG_MACB_PCI) += macb_pci.o\n--\ndrivers/net/ethernet/cadence/macb.h-2-/\ndrivers/net/ethernet/cadence/macb.h:3: Atmel MACB Ethernet Controller driver\ndrivers/net/ethernet/cadence/macb.h-4- \n--\ndrivers/net/ethernet/cadence/macb.h-6- /\ndrivers/net/ethernet/cadence/macb.h:7:#ifndef _MACB_H\ndrivers/net/ethernet/cadence/macb.h:8:#define _MACB_H\ndrivers/net/ethernet/cadence/macb.h-9-\n--\ndrivers/net/ethernet/cadence/macb.h-17-\ndrivers/net/ethernet/cadence/macb.h:18:#define MACB_GREGS_NBR 16\ndrivers/net/ethernet/cadence/macb.h:19:#define MACB_GREGS_VERSION 2\ndrivers/net/ethernet/cadence/macb.h:20:#define MACB_MAX_QUEUES 8\ndrivers/net/ethernet/cadence/macb.h-21-\ndrivers/net/ethernet/cadence/macb.h:22:/* MACB register offsets /\ndrivers/net/ethernet/cadence/macb.h:23:#define MACB_NCR\t\t0x0000 / Network Control /\ndrivers/net/ethernet/cadence/macb.h:24:#define MACB_NCFGR\t\t0x0004 / Network Config /\ndrivers/net/ethernet/cadence/macb.h:25:#define MACB_NSR\t\t0x0008 / Network Status /\ndrivers/net/ethernet/cadence/macb.h:26:#define MACB_TAR\t\t0x000c / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:27:#define MACB_TCR\t\t0x0010 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:28:#define MACB_TSR\t\t0x0014 / Transmit Status /\ndrivers/net/ethernet/cadence/macb.h:29:#define MACB_RBQP\t\t0x0018 / RX Q Base Address /\ndrivers/net/ethernet/cadence/macb.h:30:#define MACB_TBQP\t\t0x001c / TX Q Base Address /\ndrivers/net/ethernet/cadence/macb.h:31:#define MACB_RSR\t\t0x0020 / Receive Status /\ndrivers/net/ethernet/cadence/macb.h:32:#define MACB_ISR\t\t0x0024 / Interrupt Status /\ndrivers/net/ethernet/cadence/macb.h:33:#define MACB_IER\t\t0x0028 / Interrupt Enable /\ndrivers/net/ethernet/cadence/macb.h:34:#define MACB_IDR\t\t0x002c / Interrupt Disable /\ndrivers/net/ethernet/cadence/macb.h:35:#define MACB_IMR\t\t0x0030 / Interrupt Mask /\ndrivers/net/ethernet/cadence/macb.h:36:#define MACB_MAN\t\t0x0034 / PHY Maintenance /\ndrivers/net/ethernet/cadence/macb.h:37:#define MACB_PTR\t\t0x0038\ndrivers/net/ethernet/cadence/macb.h:38:#define MACB_PFR\t\t0x003c\ndrivers/net/ethernet/cadence/macb.h:39:#define MACB_FTO\t\t0x0040\ndrivers/net/ethernet/cadence/macb.h:40:#define MACB_SCF\t\t0x0044\ndrivers/net/ethernet/cadence/macb.h:41:#define MACB_MCF\t\t0x0048\ndrivers/net/ethernet/cadence/macb.h:42:#define MACB_FRO\t\t0x004c\ndrivers/net/ethernet/cadence/macb.h:43:#define MACB_FCSE\t\t0x0050\ndrivers/net/ethernet/cadence/macb.h:44:#define MACB_ALE\t\t0x0054\ndrivers/net/ethernet/cadence/macb.h:45:#define MACB_DTF\t\t0x0058\ndrivers/net/ethernet/cadence/macb.h:46:#define MACB_LCOL\t\t0x005c\ndrivers/net/ethernet/cadence/macb.h:47:#define MACB_EXCOL\t\t0x0060\ndrivers/net/ethernet/cadence/macb.h:48:#define MACB_TUND\t\t0x0064\ndrivers/net/ethernet/cadence/macb.h:49:#define MACB_CSE\t\t0x0068\ndrivers/net/ethernet/cadence/macb.h:50:#define MACB_RRE\t\t0x006c\ndrivers/net/ethernet/cadence/macb.h:51:#define MACB_ROVR\t\t0x0070\ndrivers/net/ethernet/cadence/macb.h:52:#define MACB_RSE\t\t0x0074\ndrivers/net/ethernet/cadence/macb.h:53:#define MACB_ELE\t\t0x0078\ndrivers/net/ethernet/cadence/macb.h:54:#define MACB_RJA\t\t0x007c\ndrivers/net/ethernet/cadence/macb.h:55:#define MACB_USF\t\t0x0080\ndrivers/net/ethernet/cadence/macb.h:56:#define MACB_STE\t\t0x0084\ndrivers/net/ethernet/cadence/macb.h:57:#define MACB_RLE\t\t0x0088\ndrivers/net/ethernet/cadence/macb.h:58:#define MACB_TPF\t\t0x008c\ndrivers/net/ethernet/cadence/macb.h:59:#define MACB_HRB\t\t0x0090\ndrivers/net/ethernet/cadence/macb.h:60:#define MACB_HRT\t\t0x0094\ndrivers/net/ethernet/cadence/macb.h:61:#define MACB_SA1B\t\t0x0098\ndrivers/net/ethernet/cadence/macb.h:62:#define MACB_SA1T\t\t0x009c\ndrivers/net/ethernet/cadence/macb.h:63:#define MACB_SA2B\t\t0x00a0\ndrivers/net/ethernet/cadence/macb.h:64:#define MACB_SA2T\t\t0x00a4\ndrivers/net/ethernet/cadence/macb.h:65:#define MACB_SA3B\t\t0x00a8\ndrivers/net/ethernet/cadence/macb.h:66:#define MACB_SA3T\t\t0x00ac\ndrivers/net/ethernet/cadence/macb.h:67:#define MACB_SA4B\t\t0x00b0\ndrivers/net/ethernet/cadence/macb.h:68:#define MACB_SA4T\t\t0x00b4\ndrivers/net/ethernet/cadence/macb.h:69:#define MACB_TID\t\t0x00b8\ndrivers/net/ethernet/cadence/macb.h:70:#define MACB_TPQ\t\t0x00bc\ndrivers/net/ethernet/cadence/macb.h:71:#define MACB_USRIO\t\t0x00c0\ndrivers/net/ethernet/cadence/macb.h:72:#define MACB_WOL\t\t0x00c4\ndrivers/net/ethernet/cadence/macb.h:73:#define MACB_MID\t\t0x00fc\ndrivers/net/ethernet/cadence/macb.h:74:#define MACB_TBQPH\t\t0x04C8\ndrivers/net/ethernet/cadence/macb.h:75:#define MACB_RBQPH\t\t0x04D4\ndrivers/net/ethernet/cadence/macb.h-76-\n--\ndrivers/net/ethernet/cadence/macb.h-230-/ Bitfields in NCR /\ndrivers/net/ethernet/cadence/macb.h:231:#define MACB_LB_OFFSET\t\t0 / reserved /\ndrivers/net/ethernet/cadence/macb.h:232:#define MACB_LB_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:233:#define MACB_LLB_OFFSET\t\t1 / Loop back local /\ndrivers/net/ethernet/cadence/macb.h:234:#define MACB_LLB_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:235:#define MACB_RE_OFFSET\t\t2 / Receive enable /\ndrivers/net/ethernet/cadence/macb.h:236:#define MACB_RE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:237:#define MACB_TE_OFFSET\t\t3 / Transmit enable /\ndrivers/net/ethernet/cadence/macb.h:238:#define MACB_TE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:239:#define MACB_MPE_OFFSET\t\t4 / Management port enable /\ndrivers/net/ethernet/cadence/macb.h:240:#define MACB_MPE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:241:#define MACB_CLRSTAT_OFFSET\t5 / Clear stats regs /\ndrivers/net/ethernet/cadence/macb.h:242:#define MACB_CLRSTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:243:#define MACB_INCSTAT_OFFSET\t6 / Incremental stats regs /\ndrivers/net/ethernet/cadence/macb.h:244:#define MACB_INCSTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:245:#define MACB_WESTAT_OFFSET\t7 / Write enable stats regs /\ndrivers/net/ethernet/cadence/macb.h:246:#define MACB_WESTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:247:#define MACB_BP_OFFSET\t\t8 / Back pressure /\ndrivers/net/ethernet/cadence/macb.h:248:#define MACB_BP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:249:#define MACB_TSTART_OFFSET\t9 / Start transmission /\ndrivers/net/ethernet/cadence/macb.h:250:#define MACB_TSTART_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:251:#define MACB_THALT_OFFSET\t10 / Transmit halt /\ndrivers/net/ethernet/cadence/macb.h:252:#define MACB_THALT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:253:#define MACB_NCR_TPF_OFFSET\t11 / Transmit pause frame /\ndrivers/net/ethernet/cadence/macb.h:254:#define MACB_NCR_TPF_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:255:#define MACB_TZQ_OFFSET\t\t12 / Transmit zero quantum pause frame /\ndrivers/net/ethernet/cadence/macb.h:256:#define MACB_TZQ_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:257:#define MACB_SRTSM_OFFSET\t15 / Store Receive Timestamp to Memory /\ndrivers/net/ethernet/cadence/macb.h:258:#define MACB_PTPUNI_OFFSET\t20 / PTP Unicast packet enable /\ndrivers/net/ethernet/cadence/macb.h:259:#define MACB_PTPUNI_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:260:#define MACB_OSSMODE_OFFSET\t24 / Enable One Step Synchro Mode /\ndrivers/net/ethernet/cadence/macb.h:261:#define MACB_OSSMODE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:262:#define MACB_MIIONRGMII_OFFSET\t28 / MII Usage on RGMII Interface /\ndrivers/net/ethernet/cadence/macb.h:263:#define MACB_MIIONRGMII_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h-264-\ndrivers/net/ethernet/cadence/macb.h-265-/ Bitfields in NCFGR /\ndrivers/net/ethernet/cadence/macb.h:266:#define MACB_SPD_OFFSET\t\t0 / Speed /\ndrivers/net/ethernet/cadence/macb.h:267:#define MACB_SPD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:268:#define MACB_FD_OFFSET\t\t1 / Full duplex /\ndrivers/net/ethernet/cadence/macb.h:269:#define MACB_FD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:270:#define MACB_BIT_RATE_OFFSET\t2 / Discard non-VLAN frames /\ndrivers/net/ethernet/cadence/macb.h:271:#define MACB_BIT_RATE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:272:#define MACB_JFRAME_OFFSET\t3 / reserved /\ndrivers/net/ethernet/cadence/macb.h:273:#define MACB_JFRAME_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:274:#define MACB_CAF_OFFSET\t\t4 / Copy all frames /\ndrivers/net/ethernet/cadence/macb.h:275:#define MACB_CAF_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:276:#define MACB_NBC_OFFSET\t\t5 / No broadcast /\ndrivers/net/ethernet/cadence/macb.h:277:#define MACB_NBC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:278:#define MACB_NCFGR_MTI_OFFSET\t6 / Multicast hash enable /\ndrivers/net/ethernet/cadence/macb.h:279:#define MACB_NCFGR_MTI_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:280:#define MACB_UNI_OFFSET\t\t7 / Unicast hash enable /\ndrivers/net/ethernet/cadence/macb.h:281:#define MACB_UNI_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:282:#define MACB_BIG_OFFSET\t\t8 / Receive 1536 byte frames /\ndrivers/net/ethernet/cadence/macb.h:283:#define MACB_BIG_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:284:#define MACB_EAE_OFFSET\t\t9 / External address match enable /\ndrivers/net/ethernet/cadence/macb.h:285:#define MACB_EAE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:286:#define MACB_CLK_OFFSET\t\t10\ndrivers/net/ethernet/cadence/macb.h:287:#define MACB_CLK_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:288:#define MACB_RTY_OFFSET\t\t12 / Retry test /\ndrivers/net/ethernet/cadence/macb.h:289:#define MACB_RTY_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:290:#define MACB_PAE_OFFSET\t\t13 / Pause enable /\ndrivers/net/ethernet/cadence/macb.h:291:#define MACB_PAE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:292:#define MACB_RM9200_RMII_OFFSET\t13 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:293:#define MACB_RM9200_RMII_SIZE\t1 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:294:#define MACB_RBOF_OFFSET\t14 / Receive buffer offset /\ndrivers/net/ethernet/cadence/macb.h:295:#define MACB_RBOF_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:296:#define MACB_RLCE_OFFSET\t16 / Length field error frame discard /\ndrivers/net/ethernet/cadence/macb.h:297:#define MACB_RLCE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:298:#define MACB_DRFCS_OFFSET\t17 / FCS remove /\ndrivers/net/ethernet/cadence/macb.h:299:#define MACB_DRFCS_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:300:#define MACB_EFRHD_OFFSET\t18\ndrivers/net/ethernet/cadence/macb.h:301:#define MACB_EFRHD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:302:#define MACB_IRXFCS_OFFSET\t19\ndrivers/net/ethernet/cadence/macb.h:303:#define MACB_IRXFCS_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h-304-\n--\ndrivers/net/ethernet/cadence/macb.h-364-/ Bitfields in NSR /\ndrivers/net/ethernet/cadence/macb.h:365:#define MACB_NSR_LINK_OFFSET\t0 / pcs_link_state /\ndrivers/net/ethernet/cadence/macb.h:366:#define MACB_NSR_LINK_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:367:#define MACB_MDIO_OFFSET\t1 / status of the mdio_in pin /\ndrivers/net/ethernet/cadence/macb.h:368:#define MACB_MDIO_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:369:#define MACB_IDLE_OFFSET\t2 / The PHY management logic is idle /\ndrivers/net/ethernet/cadence/macb.h:370:#define MACB_IDLE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-371-\ndrivers/net/ethernet/cadence/macb.h-372-/ Bitfields in TSR /\ndrivers/net/ethernet/cadence/macb.h:373:#define MACB_UBR_OFFSET\t\t0 / Used bit read /\ndrivers/net/ethernet/cadence/macb.h:374:#define MACB_UBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:375:#define MACB_COL_OFFSET\t\t1 / Collision occurred /\ndrivers/net/ethernet/cadence/macb.h:376:#define MACB_COL_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:377:#define MACB_TSR_RLE_OFFSET\t2 / Retry limit exceeded /\ndrivers/net/ethernet/cadence/macb.h:378:#define MACB_TSR_RLE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:379:#define MACB_TGO_OFFSET\t\t3 / Transmit go /\ndrivers/net/ethernet/cadence/macb.h:380:#define MACB_TGO_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:381:#define MACB_BEX_OFFSET\t\t4 / TX frame corruption due to AHB error /\ndrivers/net/ethernet/cadence/macb.h:382:#define MACB_BEX_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:383:#define MACB_RM9200_BNQ_OFFSET\t4 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:384:#define MACB_RM9200_BNQ_SIZE\t1 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:385:#define MACB_COMP_OFFSET\t5 / Trnasmit complete /\ndrivers/net/ethernet/cadence/macb.h:386:#define MACB_COMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:387:#define MACB_UND_OFFSET\t\t6 / Trnasmit under run /\ndrivers/net/ethernet/cadence/macb.h:388:#define MACB_UND_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-389-\ndrivers/net/ethernet/cadence/macb.h-390-/ Bitfields in RSR /\ndrivers/net/ethernet/cadence/macb.h:391:#define MACB_BNA_OFFSET\t\t0 / Buffer not available /\ndrivers/net/ethernet/cadence/macb.h:392:#define MACB_BNA_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:393:#define MACB_REC_OFFSET\t\t1 / Frame received /\ndrivers/net/ethernet/cadence/macb.h:394:#define MACB_REC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:395:#define MACB_OVR_OFFSET\t\t2 / Receive overrun /\ndrivers/net/ethernet/cadence/macb.h:396:#define MACB_OVR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-397-\ndrivers/net/ethernet/cadence/macb.h-398-/ Bitfields in ISR/IER/IDR/IMR /\ndrivers/net/ethernet/cadence/macb.h:399:#define MACB_MFD_OFFSET\t\t0 / Management frame sent /\ndrivers/net/ethernet/cadence/macb.h:400:#define MACB_MFD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:401:#define MACB_RCOMP_OFFSET\t1 / Receive complete /\ndrivers/net/ethernet/cadence/macb.h:402:#define MACB_RCOMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:403:#define MACB_RXUBR_OFFSET\t2 / RX used bit read /\ndrivers/net/ethernet/cadence/macb.h:404:#define MACB_RXUBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:405:#define MACB_TXUBR_OFFSET\t3 / TX used bit read /\ndrivers/net/ethernet/cadence/macb.h:406:#define MACB_TXUBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:407:#define MACB_ISR_TUND_OFFSET\t4 / Enable TX buffer under run interrupt /\ndrivers/net/ethernet/cadence/macb.h:408:#define MACB_ISR_TUND_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:409:#define MACB_ISR_RLE_OFFSET\t5 / EN retry exceeded/late coll interrupt /\ndrivers/net/ethernet/cadence/macb.h:410:#define MACB_ISR_RLE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:411:#define MACB_TXERR_OFFSET\t6 / EN TX frame corrupt from error interrupt /\ndrivers/net/ethernet/cadence/macb.h:412:#define MACB_TXERR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:413:#define MACB_RM9200_TBRE_OFFSET\t6 / EN may send new frame interrupt (RM9200) /\ndrivers/net/ethernet/cadence/macb.h:414:#define MACB_RM9200_TBRE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:415:#define MACB_TCOMP_OFFSET\t7 / Enable transmit complete interrupt /\ndrivers/net/ethernet/cadence/macb.h:416:#define MACB_TCOMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:417:#define MACB_ISR_LINK_OFFSET\t9 / Enable link change interrupt /\ndrivers/net/ethernet/cadence/macb.h:418:#define MACB_ISR_LINK_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:419:#define MACB_ISR_ROVR_OFFSET\t10 / Enable receive overrun interrupt /\ndrivers/net/ethernet/cadence/macb.h:420:#define MACB_ISR_ROVR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:421:#define MACB_HRESP_OFFSET\t11 / Enable hrsep not OK interrupt /\ndrivers/net/ethernet/cadence/macb.h:422:#define MACB_HRESP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:423:#define MACB_PFR_OFFSET\t\t12 / Enable pause frame w/ quantum interrupt /\ndrivers/net/ethernet/cadence/macb.h:424:#define MACB_PFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:425:#define MACB_PTZ_OFFSET\t\t13 / Enable pause time zero interrupt /\ndrivers/net/ethernet/cadence/macb.h:426:#define MACB_PTZ_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:427:#define MACB_WOL_OFFSET\t\t14 / Enable wake-on-lan interrupt /\ndrivers/net/ethernet/cadence/macb.h:428:#define MACB_WOL_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:429:#define MACB_DRQFR_OFFSET\t18 / PTP Delay Request Frame Received /\ndrivers/net/ethernet/cadence/macb.h:430:#define MACB_DRQFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:431:#define MACB_SFR_OFFSET\t\t19 / PTP Sync Frame Received /\ndrivers/net/ethernet/cadence/macb.h:432:#define MACB_SFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:433:#define MACB_DRQFT_OFFSET\t20 / PTP Delay Request Frame Transmitted /\ndrivers/net/ethernet/cadence/macb.h:434:#define MACB_DRQFT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:435:#define MACB_SFT_OFFSET\t\t21 / PTP Sync Frame Transmitted /\ndrivers/net/ethernet/cadence/macb.h:436:#define MACB_SFT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:437:#define MACB_PDRQFR_OFFSET\t22 / PDelay Request Frame Received /\ndrivers/net/ethernet/cadence/macb.h:438:#define MACB_PDRQFR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:439:#define MACB_PDRSFR_OFFSET\t23 / PDelay Response Frame Received /\ndrivers/net/ethernet/cadence/macb.h:440:#define MACB_PDRSFR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:441:#define MACB_PDRQFT_OFFSET\t24 / PDelay Request Frame Transmitted /\ndrivers/net/ethernet/cadence/macb.h:442:#define MACB_PDRQFT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:443:#define MACB_PDRSFT_OFFSET\t25 / PDelay Response Frame Transmitted /\ndrivers/net/ethernet/cadence/macb.h:444:#define MACB_PDRSFT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:445:#define MACB_SRI_OFFSET\t\t26 / TSU Seconds Register Increment /\ndrivers/net/ethernet/cadence/macb.h:446:#define MACB_SRI_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-447-#define GEM_WOL_OFFSET\t\t28 / Enable wake-on-lan interrupt /\n--\ndrivers/net/ethernet/cadence/macb.h-450-/ Timer increment fields /\ndrivers/net/ethernet/cadence/macb.h:451:#define MACB_TI_CNS_OFFSET\t0\ndrivers/net/ethernet/cadence/macb.h:452:#define MACB_TI_CNS_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h:453:#define MACB_TI_ACNS_OFFSET\t8\ndrivers/net/ethernet/cadence/macb.h:454:#define MACB_TI_ACNS_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h:455:#define MACB_TI_NIT_OFFSET\t16\ndrivers/net/ethernet/cadence/macb.h:456:#define MACB_TI_NIT_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h-457-\ndrivers/net/ethernet/cadence/macb.h-458-/ Bitfields in MAN /\ndrivers/net/ethernet/cadence/macb.h:459:#define MACB_DATA_OFFSET\t0 / data /\ndrivers/net/ethernet/cadence/macb.h:460:#define MACB_DATA_SIZE\t\t16\ndrivers/net/ethernet/cadence/macb.h:461:#define MACB_CODE_OFFSET\t16 / Must be written to 10 /\ndrivers/net/ethernet/cadence/macb.h:462:#define MACB_CODE_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:463:#define MACB_REGA_OFFSET\t18 / Register address /\ndrivers/net/ethernet/cadence/macb.h:464:#define MACB_REGA_SIZE\t\t5\ndrivers/net/ethernet/cadence/macb.h:465:#define MACB_PHYA_OFFSET\t23 / PHY address /\ndrivers/net/ethernet/cadence/macb.h:466:#define MACB_PHYA_SIZE\t\t5\ndrivers/net/ethernet/cadence/macb.h:467:#define MACB_RW_OFFSET\t\t28 / Operation. 10 is read. 01 is write. /\ndrivers/net/ethernet/cadence/macb.h:468:#define MACB_RW_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:469:#define MACB_SOF_OFFSET\t\t30 / Must be written to 1 for Clause 22 /\ndrivers/net/ethernet/cadence/macb.h:470:#define MACB_SOF_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h-471-\ndrivers/net/ethernet/cadence/macb.h-472-/ Bitfields in USRIO (AVR32) /\ndrivers/net/ethernet/cadence/macb.h:473:#define MACB_MII_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:474:#define MACB_MII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:475:#define MACB_EAM_OFFSET\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:476:#define MACB_EAM_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:477:#define MACB_TX_PAUSE_OFFSET\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:478:#define MACB_TX_PAUSE_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:479:#define MACB_TX_PAUSE_ZERO_OFFSET\t\t3\ndrivers/net/ethernet/cadence/macb.h:480:#define MACB_TX_PAUSE_ZERO_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-481-\ndrivers/net/ethernet/cadence/macb.h-482-/ Bitfields in USRIO (AT91) /\ndrivers/net/ethernet/cadence/macb.h:483:#define MACB_RMII_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:484:#define MACB_RMII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-485-#define GEM_RGMII_OFFSET\t\t\t0 / GEM gigabit mode /\ndrivers/net/ethernet/cadence/macb.h-486-#define GEM_RGMII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:487:#define MACB_CLKEN_OFFSET\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:488:#define MACB_CLKEN_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-489-\ndrivers/net/ethernet/cadence/macb.h-490-/ Bitfields in WOL /\ndrivers/net/ethernet/cadence/macb.h:491:#define MACB_IP_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:492:#define MACB_IP_SIZE\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:493:#define MACB_MAG_OFFSET\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:494:#define MACB_MAG_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:495:#define MACB_ARP_OFFSET\t\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:496:#define MACB_ARP_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:497:#define MACB_SA1_OFFSET\t\t\t\t18\ndrivers/net/ethernet/cadence/macb.h:498:#define MACB_SA1_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:499:#define MACB_WOL_MTI_OFFSET\t\t\t19\ndrivers/net/ethernet/cadence/macb.h:500:#define MACB_WOL_MTI_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-501-\ndrivers/net/ethernet/cadence/macb.h-502-/ Bitfields in MID /\ndrivers/net/ethernet/cadence/macb.h:503:#define MACB_IDNUM_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:504:#define MACB_IDNUM_SIZE\t\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:505:#define MACB_REV_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:506:#define MACB_REV_SIZE\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h-507-\n--\ndrivers/net/ethernet/cadence/macb.h-678-/ Bitfields in queue pointer registers /\ndrivers/net/ethernet/cadence/macb.h:679:#define MACB_QUEUE_DISABLE_OFFSET\t\t0 / disable queue /\ndrivers/net/ethernet/cadence/macb.h:680:#define MACB_QUEUE_DISABLE_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-681-\n--\ndrivers/net/ethernet/cadence/macb.h-729-/ Constants for CLK /\ndrivers/net/ethernet/cadence/macb.h:730:#define MACB_CLK_DIV8\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:731:#define MACB_CLK_DIV16\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:732:#define MACB_CLK_DIV32\t\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:733:#define MACB_CLK_DIV64\t\t\t\t3\ndrivers/net/ethernet/cadence/macb.h-734-\n--\ndrivers/net/ethernet/cadence/macb.h-745-/ Constants for MAN register /\ndrivers/net/ethernet/cadence/macb.h:746:#define MACB_MAN_C22_SOF\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:747:#define MACB_MAN_C22_WRITE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:748:#define MACB_MAN_C22_READ\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:749:#define MACB_MAN_C22_CODE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h-750-\ndrivers/net/ethernet/cadence/macb.h:751:#define MACB_MAN_C45_SOF\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:752:#define MACB_MAN_C45_ADDR\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:753:#define MACB_MAN_C45_WRITE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:754:#define MACB_MAN_C45_POST_READ_INCR\t\t2\ndrivers/net/ethernet/cadence/macb.h:755:#define MACB_MAN_C45_READ\t\t\t3\ndrivers/net/ethernet/cadence/macb.h:756:#define MACB_MAN_C45_CODE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h-757-\ndrivers/net/ethernet/cadence/macb.h-758-/ Capability mask bits /\ndrivers/net/ethernet/cadence/macb.h:759:#define MACB_CAPS_ISR_CLEAR_ON_WRITE\t\tBIT(0)\ndrivers/net/ethernet/cadence/macb.h:760:#define MACB_CAPS_USRIO_HAS_CLKEN\t\tBIT(1)\ndrivers/net/ethernet/cadence/macb.h:761:#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII\tBIT(2)\ndrivers/net/ethernet/cadence/macb.h:762:#define MACB_CAPS_NO_GIGABIT_HALF\t\tBIT(3)\ndrivers/net/ethernet/cadence/macb.h:763:#define MACB_CAPS_USRIO_DISABLED\t\tBIT(4)\ndrivers/net/ethernet/cadence/macb.h:764:#define MACB_CAPS_JUMBO\t\t\t\tBIT(5)\ndrivers/net/ethernet/cadence/macb.h:765:#define MACB_CAPS_GEM_HAS_PTP\t\t\tBIT(6)\ndrivers/net/ethernet/cadence/macb.h:766:#define MACB_CAPS_BD_RD_PREFETCH\t\tBIT(7)\ndrivers/net/ethernet/cadence/macb.h:767:#define MACB_CAPS_NEEDS_RSTONUBR\t\tBIT(8)\ndrivers/net/ethernet/cadence/macb.h:768:#define MACB_CAPS_MIIONRGMII\t\t\tBIT(9)\ndrivers/net/ethernet/cadence/macb.h:769:#define MACB_CAPS_NEED_TSUCLK\t\t\tBIT(10)\ndrivers/net/ethernet/cadence/macb.h:770:#define MACB_CAPS_QUEUE_DISABLE\t\t\tBIT(11)\ndrivers/net/ethernet/cadence/macb.h:771:#define MACB_CAPS_QBV\t\t\t\tBIT(12)\ndrivers/net/ethernet/cadence/macb.h:772:#define MACB_CAPS_PCS\t\t\t\tBIT(13)\ndrivers/net/ethernet/cadence/macb.h:773:#define MACB_CAPS_HIGH_SPEED\t\t\tBIT(14)\ndrivers/net/ethernet/cadence/macb.h:774:#define MACB_CAPS_CLK_HW_CHG\t\t\tBIT(15)\ndrivers/net/ethernet/cadence/macb.h:775:#define MACB_CAPS_MACB_IS_EMAC\t\t\tBIT(16)\ndrivers/net/ethernet/cadence/macb.h:776:#define MACB_CAPS_FIFO_MODE\t\t\tBIT(17)\ndrivers/net/ethernet/cadence/macb.h:777:#define MACB_CAPS_GIGABIT_MODE_AVAILABLE\tBIT(18)\ndrivers/net/ethernet/cadence/macb.h:778:#define MACB_CAPS_SG_DISABLED\t\t\tBIT(19)\ndrivers/net/ethernet/cadence/macb.h:779:#define MACB_CAPS_MACB_IS_GEM\t\t\tBIT(20)\ndrivers/net/ethernet/cadence/macb.h:780:#define MACB_CAPS_DMA_64B\t\t\tBIT(21)\ndrivers/net/ethernet/cadence/macb.h:781:#define MACB_CAPS_DMA_PTP\t\t\tBIT(22)\ndrivers/net/ethernet/cadence/macb.h:782:#define MACB_CAPS_RSC\t\t\t\tBIT(23)\ndrivers/net/ethernet/cadence/macb.h:783:#define MACB_CAPS_NO_LSO\t\t\tBIT(24)\ndrivers/net/ethernet/cadence/macb.h:784:#define MACB_CAPS_EEE\t\t\t\tBIT(25)\ndrivers/net/ethernet/cadence/macb.h:785:#define MACB_CAPS_USRIO_HAS_MII\t\t\tBIT(26)\ndrivers/net/ethernet/cadence/macb.h:786:#define MACB_CAPS_USRIO_HAS_REFCLK_SOURCE\tBIT(27)\ndrivers/net/ethernet/cadence/macb.h:787:#define MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE\tBIT(28)\ndrivers/net/ethernet/cadence/macb.h-788-\ndrivers/net/ethernet/cadence/macb.h-789-/ LSO settings /\ndrivers/net/ethernet/cadence/macb.h:790:#define MACB_LSO_UFO_ENABLE\t\t\t0x01\ndrivers/net/ethernet/cadence/macb.h:791:#define MACB_LSO_TSO_ENABLE\t\t\t0x02\ndrivers/net/ethernet/cadence/macb.h-792-\ndrivers/net/ethernet/cadence/macb.h-793-/ Bit manipulation macros /\ndrivers/net/ethernet/cadence/macb.h:794:#define MACB_BIT(name)\t\t\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:795:\t(1 \u003c\u003c MACB_##name##_OFFSET)\ndrivers/net/ethernet/cadence/macb.h:796:#define MACB_BF(name,value)\t\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:797:\t(((value) \u0026 ((1 \u003c\u003c MACB_##name##_SIZE) - 1))\t\\\ndrivers/net/ethernet/cadence/macb.h:798:\t \u003c\u003c MACB_##name##_OFFSET)\ndrivers/net/ethernet/cadence/macb.h:799:#define MACB_BFEXT(name,value)\\\ndrivers/net/ethernet/cadence/macb.h:800:\t(((value) \u003e\u003e MACB_##name##_OFFSET)\t\t\\\ndrivers/net/ethernet/cadence/macb.h:801:\t \u0026 ((1 \u003c\u003c MACB_##name##_SIZE) - 1))\ndrivers/net/ethernet/cadence/macb.h:802:#define MACB_BFINS(name,value,old)\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:803:\t(((old) \u0026 ~(((1 \u003c\u003c MACB_##name##_SIZE) - 1)\t\\\ndrivers/net/ethernet/cadence/macb.h:804:\t\t \u003c\u003c MACB_##name##_OFFSET))\t\t\\\ndrivers/net/ethernet/cadence/macb.h:805:\t \| MACB_BF(name,value))\ndrivers/net/ethernet/cadence/macb.h-806-\n--\ndrivers/net/ethernet/cadence/macb.h-820-/ Register access macros /\ndrivers/net/ethernet/cadence/macb.h:821:#define macb_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), MACB_##reg)\ndrivers/net/ethernet/cadence/macb.h:822:#define macb_writel(port, reg, value)\t(port)-\u003emacb_reg_writel((port), MACB_##reg, (value))\ndrivers/net/ethernet/cadence/macb.h-823-#define gem_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), GEM_##reg)\n--\ndrivers/net/ethernet/cadence/macb.h-829-\ndrivers/net/ethernet/cadence/macb.h:830:/ Conditional GEM/MACB macros. These perform the operation to the correct\ndrivers/net/ethernet/cadence/macb.h:831: * register dependent on whether the device is a GEM or a MACB. For registers\ndrivers/net/ethernet/cadence/macb.h-832- * and bitfields that are common across both devices, use macb_{read,write}l\n--\ndrivers/net/ethernet/cadence/macb.h-852-\ndrivers/net/ethernet/cadence/macb.h:853:#define MACB_READ_NSR(bp)\tmacb_readl(bp, NSR)\ndrivers/net/ethernet/cadence/macb.h-854-\n--\ndrivers/net/ethernet/cadence/macb.h=869=struct macb_dma_desc_ptp {\n--\ndrivers/net/ethernet/cadence/macb.h-874-/* DMA descriptor bitfields /\ndrivers/net/ethernet/cadence/macb.h:875:#define MACB_RX_USED_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:876:#define MACB_RX_USED_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:877:#define MACB_RX_WRAP_OFFSET\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:878:#define MACB_RX_WRAP_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:879:#define MACB_RX_WADDR_OFFSET\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:880:#define MACB_RX_WADDR_SIZE\t\t\t30\ndrivers/net/ethernet/cadence/macb.h-881-\ndrivers/net/ethernet/cadence/macb.h:882:#define MACB_RX_FRMLEN_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:883:#define MACB_RX_FRMLEN_SIZE\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:884:#define MACB_RX_OFFSET_OFFSET\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:885:#define MACB_RX_OFFSET_SIZE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:886:#define MACB_RX_SOF_OFFSET\t\t\t14\ndrivers/net/ethernet/cadence/macb.h:887:#define MACB_RX_SOF_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:888:#define MACB_RX_EOF_OFFSET\t\t\t15\ndrivers/net/ethernet/cadence/macb.h:889:#define MACB_RX_EOF_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:890:#define MACB_RX_CFI_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:891:#define MACB_RX_CFI_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:892:#define MACB_RX_VLAN_PRI_OFFSET\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:893:#define MACB_RX_VLAN_PRI_SIZE\t\t\t3\ndrivers/net/ethernet/cadence/macb.h:894:#define MACB_RX_PRI_TAG_OFFSET\t\t\t20\ndrivers/net/ethernet/cadence/macb.h:895:#define MACB_RX_PRI_TAG_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:896:#define MACB_RX_VLAN_TAG_OFFSET\t\t\t21\ndrivers/net/ethernet/cadence/macb.h:897:#define MACB_RX_VLAN_TAG_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:898:#define MACB_RX_TYPEID_MATCH_OFFSET\t\t22\ndrivers/net/ethernet/cadence/macb.h:899:#define MACB_RX_TYPEID_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:900:#define MACB_RX_SA4_MATCH_OFFSET\t\t23\ndrivers/net/ethernet/cadence/macb.h:901:#define MACB_RX_SA4_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:902:#define MACB_RX_SA3_MATCH_OFFSET\t\t24\ndrivers/net/ethernet/cadence/macb.h:903:#define MACB_RX_SA3_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:904:#define MACB_RX_SA2_MATCH_OFFSET\t\t25\ndrivers/net/ethernet/cadence/macb.h:905:#define MACB_RX_SA2_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:906:#define MACB_RX_SA1_MATCH_OFFSET\t\t26\ndrivers/net/ethernet/cadence/macb.h:907:#define MACB_RX_SA1_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:908:#define MACB_RX_EXT_MATCH_OFFSET\t\t28\ndrivers/net/ethernet/cadence/macb.h:909:#define MACB_RX_EXT_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:910:#define MACB_RX_UHASH_MATCH_OFFSET\t\t29\ndrivers/net/ethernet/cadence/macb.h:911:#define MACB_RX_UHASH_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:912:#define MACB_RX_MHASH_MATCH_OFFSET\t\t30\ndrivers/net/ethernet/cadence/macb.h:913:#define MACB_RX_MHASH_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:914:#define MACB_RX_BROADCAST_OFFSET\t\t31\ndrivers/net/ethernet/cadence/macb.h:915:#define MACB_RX_BROADCAST_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-916-\ndrivers/net/ethernet/cadence/macb.h:917:#define MACB_RX_FRMLEN_MASK\t\t\t0xFFF\ndrivers/net/ethernet/cadence/macb.h:918:#define MACB_RX_JFRMLEN_MASK\t\t\t0x3FFF\ndrivers/net/ethernet/cadence/macb.h-919-\n--\ndrivers/net/ethernet/cadence/macb.h-927-\ndrivers/net/ethernet/cadence/macb.h:928:#define MACB_TX_FRMLEN_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:929:#define MACB_TX_FRMLEN_SIZE\t\t\t11\ndrivers/net/ethernet/cadence/macb.h:930:#define MACB_TX_LAST_OFFSET\t\t\t15\ndrivers/net/ethernet/cadence/macb.h:931:#define MACB_TX_LAST_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:932:#define MACB_TX_NOCRC_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:933:#define MACB_TX_NOCRC_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:934:#define MACB_MSS_MFS_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:935:#define MACB_MSS_MFS_SIZE\t\t\t14\ndrivers/net/ethernet/cadence/macb.h:936:#define MACB_TX_LSO_OFFSET\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:937:#define MACB_TX_LSO_SIZE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:938:#define MACB_TX_TCP_SEQ_SRC_OFFSET\t\t19\ndrivers/net/ethernet/cadence/macb.h:939:#define MACB_TX_TCP_SEQ_SRC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:940:#define MACB_TX_BUF_EXHAUSTED_OFFSET\t\t27\ndrivers/net/ethernet/cadence/macb.h:941:#define MACB_TX_BUF_EXHAUSTED_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:942:#define MACB_TX_UNDERRUN_OFFSET\t\t\t28\ndrivers/net/ethernet/cadence/macb.h:943:#define MACB_TX_UNDERRUN_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:944:#define MACB_TX_ERROR_OFFSET\t\t\t29\ndrivers/net/ethernet/cadence/macb.h:945:#define MACB_TX_ERROR_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:946:#define MACB_TX_WRAP_OFFSET\t\t\t30\ndrivers/net/ethernet/cadence/macb.h:947:#define MACB_TX_WRAP_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:948:#define MACB_TX_USED_OFFSET\t\t\t31\ndrivers/net/ethernet/cadence/macb.h:949:#define MACB_TX_USED_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-950-\n--\ndrivers/net/ethernet/cadence/macb.h=1197=struct macb_or_gem_ops {\n--\ndrivers/net/ethernet/cadence/macb.h-1204-\ndrivers/net/ethernet/cadence/macb.h:1205:/ MACB-PTP interface: adapt to platform needs. */\ndrivers/net/ethernet/cadence/macb.h-1206-struct macb_ptp_info {\n--\ndrivers/net/ethernet/cadence/macb.h=1301=struct macb {\n--\ndrivers/net/ethernet/cadence/macb.h-1316-\tunsigned int\t\tnum_queues;\n\n" }
5/2	2026/09/10 04:37	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 18853 output: 36 thoughts: 160 Thoughts: My QEMU / Cadence MACB PCI Investigation Okay, so I'm looking into the Cadence MACB / GEM ethernet controller, specifically the PCI implementation. I know `macb_pci.c` and `macb_main.c` are the relevant source files. The question is, does QEMU emulate the Cadence MACB in a PCI configuration, and if so, how? My initial thought is that it might be emulated, but I need to confirm. Ah, yes! I remember QEMU having `cadence_gem` emulation! But does that apply to the PCI implementation? A quick search reminds me that QEMU utilizes `cadence_gem` for Xilinx Zynq, ZynqMP, and Versal platforms, which all use ARM/AArch64 or MicroBlaze architectures. So, where does this fit in with PCI? Does QEMU use `macb_pci` directly, or does it somehow map that to `cadence_gem` on PCI devices? To be sure, I'll check `macb_pci.c`. I need to figure out which PCI devices it's designed to match. That will give me a clear idea of what the QEMU emulation targets. Let's dig in.
6/2	2026/09/10 04:37	tool	grepper	0m Args: { "Expression": "pci_device_id", "PathPrefix": "drivers/net/ethernet/cadence/" } Results: { "Output": "drivers/net/ethernet/cadence/macb_pci.c-26-\ndrivers/net/ethernet/cadence/macb_pci.c:27:static int macb_probe(struct pci_dev pci, const struct pci_device_id id)\ndrivers/net/ethernet/cadence/macb_pci.c-28-{\n--\ndrivers/net/ethernet/cadence/macb_pci.c=108=static void macb_remove(struct pci_dev *pci)\n--\ndrivers/net/ethernet/cadence/macb_pci.c-119-\ndrivers/net/ethernet/cadence/macb_pci.c:120:static const struct pci_device_id dev_id_table[] = {\ndrivers/net/ethernet/cadence/macb_pci.c-121-\t{ PCI_VDEVICE(CDNS, PCI_DEVICE_ID_CDNS_MACB) },\n" }
7/2	2026/09/10 04:37	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 19587 output: 44 thoughts: 29 Thoughts: Okay, here's my take on those thoughts, framed as if they're mine: Diving into the MACB Driver Right, time to get my hands dirty. Let's see... the issue we're tackling likely involves how the device is identified and probed, so my first instinct is to zero in on `macb_pci.c`. Specifically, I want to refresh my memory about how the `dev_id_table` is structured – that's the crucial mapping between PCI device IDs and the MACB driver. I need to understand how the driver knows which devices it should attach to. Then, I'll jump over to the `macb_probe` function. That's the function that gets called when a matching device is found. I need to reconstruct the execution flow here - how it verifies device compatibility, initializes the hardware, and ultimately makes the device ready for use by the system. Understanding this control flow should clarify the root of the problem.
8/2	2026/09/10 04:37	tool	read-file	0m Args: { "File": "drivers/net/ethernet/cadence/macb_pci.c", "FirstLine": 1, "LineCount": 130 } Results: { "Contents": " 1:\t// SPDX-License-Identifier: GPL-2.0-only\n 2:\t/\n 3:\t DOC: Cadence GEM PCI wrapper.\n 4:\t \n 5:\t Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com\n 6:\t \n 7:\t Authors: Rafal Ozieblo \u003crafalo@cadence.com\u003e\n 8:\t \t Bartosz Folta \u003cbfolta@cadence.com\u003e\n 9:\t /\n 10:\t\n 11:\t#include \u003clinux/clk.h\u003e\n 12:\t#include \u003clinux/clk-provider.h\u003e\n 13:\t#include \u003clinux/etherdevice.h\u003e\n 14:\t#include \u003clinux/module.h\u003e\n 15:\t#include \u003clinux/pci.h\u003e\n 16:\t#include \u003clinux/platform_device.h\u003e\n 17:\t#include \"macb.h\"\n 18:\t\n 19:\t#define PCI_DRIVER_NAME \"macb_pci\"\n 20:\t#define PLAT_DRIVER_NAME \"macb\"\n 21:\t\n 22:\t#define PCI_DEVICE_ID_CDNS_MACB 0xe007\n 23:\t\n 24:\t#define GEM_PCLK_RATE 50000000\n 25:\t#define GEM_HCLK_RATE 50000000\n 26:\t\n 27:\tstatic int macb_probe(struct pci_dev pci, const struct pci_device_id id)\n 28:\t{\n 29:\t\tint err;\n 30:\t\tstruct platform_device pdev;\n 31:\t\tstruct platform_device_info plat_info;\n 32:\t\tstruct macb_platform_data plat_data;\n 33:\t\tstruct resource res[2];\n 34:\t\n 35:\t\t/ enable pci device /\n 36:\t\terr = pcim_enable_device(pci);\n 37:\t\tif (err \u003c 0) {\n 38:\t\t\tdev_err(\u0026pci-\u003edev, \"Enabling PCI device has failed: %d\", err);\n 39:\t\t\treturn err;\n 40:\t\t}\n 41:\t\n 42:\t\tpci_set_master(pci);\n 43:\t\n 44:\t\t/ set up resources /\n 45:\t\tmemset(res, 0x00, sizeof(struct resource) ARRAY_SIZE(res));\n 46:\t\tres[0].start = pci_resource_start(pci, 0);\n 47:\t\tres[0].end = pci_resource_end(pci, 0);\n 48:\t\tres[0].name = PCI_DRIVER_NAME;\n 49:\t\tres[0].flags = IORESOURCE_MEM;\n 50:\t\tres[1].start = pci_irq_vector(pci, 0);\n 51:\t\tres[1].name = PCI_DRIVER_NAME;\n 52:\t\tres[1].flags = IORESOURCE_IRQ;\n 53:\t\n 54:\t\tdev_info(\u0026pci-\u003edev, \"EMAC physical base addr: %pa\\n\",\n 55:\t\t\t \u0026res[0].start);\n 56:\t\n 57:\t\t/* set up macb platform data /\n 58:\t\tmemset(\u0026plat_data, 0, sizeof(plat_data));\n 59:\t\n 60:\t\t/ initialize clocks /\n 61:\t\tplat_data.pclk = clk_register_fixed_rate(\u0026pci-\u003edev, \"pclk\", NULL, 0,\n 62:\t\t\t\t\t\t\t GEM_PCLK_RATE);\n 63:\t\tif (IS_ERR(plat_data.pclk)) {\n 64:\t\t\terr = PTR_ERR(plat_data.pclk);\n 65:\t\t\tgoto err_pclk_register;\n 66:\t\t}\n 67:\t\n 68:\t\tplat_data.hclk = clk_register_fixed_rate(\u0026pci-\u003edev, \"hclk\", NULL, 0,\n 69:\t\t\t\t\t\t\t GEM_HCLK_RATE);\n 70:\t\tif (IS_ERR(plat_data.hclk)) {\n 71:\t\t\terr = PTR_ERR(plat_data.hclk);\n 72:\t\t\tgoto err_hclk_register;\n 73:\t\t}\n 74:\t\n 75:\t\t/ set up platform device info /\n 76:\t\tmemset(\u0026plat_info, 0, sizeof(plat_info));\n 77:\t\tplat_info.parent = \u0026pci-\u003edev;\n 78:\t\tplat_info.fwnode = pci-\u003edev.fwnode;\n 79:\t\tplat_info.name = PLAT_DRIVER_NAME;\n 80:\t\tplat_info.id = pci-\u003edevfn;\n 81:\t\tplat_info.res = res;\n 82:\t\tplat_info.num_res = ARRAY_SIZE(res);\n 83:\t\tplat_info.data = \u0026plat_data;\n 84:\t\tplat_info.size_data = sizeof(plat_data);\n 85:\t\tplat_info.dma_mask = pci-\u003edma_mask;\n 86:\t\n 87:\t\t/ register platform device */\n 88:\t\tpdev = platform_device_register_full(\u0026plat_info);\n 89:\t\tif (IS_ERR(pdev)) {\n 90:\t\t\terr = PTR_ERR(pdev);\n 91:\t\t\tgoto err_plat_dev_register;\n 92:\t\t}\n 93:\t\n 94:\t\tpci_set_drvdata(pci, pdev);\n 95:\t\n 96:\t\treturn 0;\n 97:\t\n 98:\terr_plat_dev_register:\n 99:\t\tclk_unregister_fixed_rate(plat_data.hclk);\n 100:\t\n" }
9/2	2026/09/10 04:37	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 21394 output: 43 thoughts: 333 Thoughts: My Assessment of the Cadence MACB / GEM Ethernet Controller for Fuzzing Okay, let's break this down. I'm looking at this Cadence MACB/GEM ethernet controller – it's a vendor-specific hardware MAC, like you'd find on Atmel, AT32, or potentially Cadence's GEM IP in Xilinx Zynq ARM systems, FPGAs, or even a PCI prototype card. The immediate question in my mind is, on a standard amd64 system, running in a virtualized environment like GCE or QEMU, can I actually reach and execute this code, specifically with `CONFIG_MACB` enabled? I need to refer to the fuzzing guidelines. The key takeaway, the primary gatekeeper, is reachability. The guidelines state clearly that fuzzing is only valid for code that executes within standard virtualized setups, using software-emulated devices. If the code is, in a word, unreachable, then fuzzing is out of the question, regardless of its internal complexity or if there are additional assertion statements. Now, according to the guidelines, I can mark something as `WorthFuzzing=false` only if the modified code falls into certain categories. The crucial one for me here is structurally unreachable hardware, such as vendor-specific PCIe switches, or drivers that need specific physical hardware not emulated in standard QEMU. Unreachable execution paths are also not suitable. Now, let's shift focus to `macb_ptp.c`. I need to dig into that file and see what it does. Its role in the overall picture, and its relation to the hardware, needs to be inspected. So, let me open that up and investigate.
10/2	2026/09/10 04:38	tool	read-file	0m Args: { "File": "drivers/net/ethernet/cadence/macb_ptp.c", "FirstLine": 1, "LineCount": 80 } Results: { "Contents": " 1:\t// SPDX-License-Identifier: GPL-2.0-only\n 2:\t/\n 3:\t 1588 PTP support for Cadence GEM device.\n 4:\t \n 5:\t Copyright (C) 2017 Cadence Design Systems - https://www.cadence.com\n 6:\t \n 7:\t Authors: Rafal Ozieblo \u003crafalo@cadence.com\u003e\n 8:\t * Bartosz Folta \u003cbfolta@cadence.com\u003e\n 9:\t /\n 10:\t#include \u003clinux/kernel.h\u003e\n 11:\t#include \u003clinux/types.h\u003e\n 12:\t#include \u003clinux/clk.h\u003e\n 13:\t#include \u003clinux/device.h\u003e\n 14:\t#include \u003clinux/etherdevice.h\u003e\n 15:\t#include \u003clinux/platform_device.h\u003e\n 16:\t#include \u003clinux/time64.h\u003e\n 17:\t#include \u003clinux/ptp_classify.h\u003e\n 18:\t#include \u003clinux/if_ether.h\u003e\n 19:\t#include \u003clinux/if_vlan.h\u003e\n 20:\t#include \u003clinux/net_tstamp.h\u003e\n 21:\t#include \u003clinux/circ_buf.h\u003e\n 22:\t#include \u003clinux/spinlock.h\u003e\n 23:\t\n 24:\t#include \"macb.h\"\n 25:\t\n 26:\t#define GEM_PTP_TIMER_NAME \"gem-ptp-timer\"\n 27:\t\n 28:\tstatic struct macb_dma_desc_ptp macb_ptp_desc(struct macb bp,\n 29:\t\t\t\t\t\t struct macb_dma_desc desc)\n 30:\t{\n 31:\t\tif (!macb_dma_ptp(bp))\n 32:\t\t\treturn NULL;\n 33:\t\n 34:\t\tif (macb_dma64(bp))\n 35:\t\t\treturn (struct macb_dma_desc_ptp )\n 36:\t\t\t\t\t((u8 )desc + sizeof(struct macb_dma_desc)\n 37:\t\t\t\t\t+ sizeof(struct macb_dma_desc_64));\n 38:\t\telse\n 39:\t\t\treturn (struct macb_dma_desc_ptp )\n 40:\t\t\t\t\t((u8 )desc + sizeof(struct macb_dma_desc));\n 41:\t}\n 42:\t\n 43:\tstatic int gem_tsu_get_time(struct ptp_clock_info ptp, struct timespec64 ts,\n 44:\t\t\t\t struct ptp_system_timestamp sts)\n 45:\t{\n 46:\t\tstruct macb bp = container_of(ptp, struct macb, ptp_clock_info);\n 47:\t\tunsigned long flags;\n 48:\t\tlong first, second;\n 49:\t\tu32 secl, sech;\n 50:\t\n 51:\t\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\n 52:\t\tptp_read_system_prets(sts);\n 53:\t\t/* ptp_read_system_prets() uses smp_rmb() internally,\n 54:\t\t * which does not guarantee ordering against MMIO reads.\n 55:\t\t /\n 56:\t\trmb();\n 57:\t\tfirst = gem_readl(bp, TN);\n 58:\t\t/ Ensure the PHC read completes before taking\n 59:\t\t * the post timestamp.\n 60:\t\t /\n 61:\t\trmb();\n 62:\t\tptp_read_system_postts(sts);\n 63:\t\tsecl = gem_readl(bp, TSL);\n 64:\t\tsech = gem_readl(bp, TSH);\n 65:\t\tsecond = gem_readl(bp, TN);\n 66:\t\n 67:\t\t/ test for nsec rollover /\n 68:\t\tif (first \u003e second) {\n 69:\t\t\t/ if so, use later read \u0026 re-read seconds\n 70:\t\t\t * (assume all done within 1s)\n 71:\t\t\t /\n 72:\t\t\tptp_read_system_prets(sts);\n 73:\t\t\t/ ptp_read_system_prets() uses smp_rmb() internally,\n 74:\t\t\t * which does not guarantee ordering against MMIO reads.\n 75:\t\t\t /\n 76:\t\t\trmb();\n 77:\t\t\tts-\u003etv_nsec = gem_readl(bp, TN);\n 78:\t\t\t/ Ensure the PHC read completes before taking\n 79:\t\t\t * the post timestamp.\n 80:\t\t\t */\n" }
11/2	2026/09/10 04:38	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 23364 output: 38 thoughts: 76 Thoughts: Here's my thought process, distilled: Finding the Source of a PTP Time Callback Okay, so `gem_tsu_get_time()`… right, that's a PTP clock callback, specifically the one defined as `ptp_clock_info.gettimex64` within the `macb_ptp.c` module. The function's purpose is clear, but I need to figure out where it's being registered, which device or driver is actually using it. I need to trace its usage. I'll search the codebase directly for instances of `gem_tsu_get_time` and see what comes up. That should point me to the relevant initialization or registration code.
12/2	2026/09/10 04:38	tool	grepper	0m Args: { "Expression": "gem_tsu_get_time", "PathPrefix": "drivers/net/ethernet/cadence/" } Results: { "Output": "drivers/net/ethernet/cadence/macb_ptp.c=28=static struct macb_dma_desc_ptp macb_ptp_desc(struct macb bp,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-42-\ndrivers/net/ethernet/cadence/macb_ptp.c:43:static int gem_tsu_get_time(struct ptp_clock_info ptp, struct timespec64 ts,\ndrivers/net/ethernet/cadence/macb_ptp.c-44-\t\t\t struct ptp_system_timestamp sts)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=175=static int gem_ptp_adjtime(struct ptp_clock_info ptp, s64 delta)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-186-\tif (delta \u003e TSU_NSEC_MAX_VAL) {\ndrivers/net/ethernet/cadence/macb_ptp.c:187:\t\tgem_tsu_get_time(\u0026bp-\u003eptp_clock_info, \u0026now, NULL);\ndrivers/net/ethernet/cadence/macb_ptp.c-188-\t\tnow = timespec64_add(now, then);\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=207=static const struct ptp_clock_info gem_ptp_caps_template = {\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-217-\t.adjtime\t= gem_ptp_adjtime,\ndrivers/net/ethernet/cadence/macb_ptp.c:218:\t.gettimex64\t= gem_tsu_get_time,\ndrivers/net/ethernet/cadence/macb_ptp.c-219-\t.settime64\t= gem_tsu_set_time,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=264=static int gem_hw_timestamp(struct macb bp, u32 dma_desc_ts_1,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-276-\t /\ndrivers/net/ethernet/cadence/macb_ptp.c:277:\tgem_tsu_get_time(\u0026bp-\u003eptp_clock_info, \u0026tsu, NULL);\ndrivers/net/ethernet/cadence/macb_ptp.c-278-\n" }
13/2	2026/09/10 04:38	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 24295 output: 140 thoughts: 913 Thoughts: Fuzzing Verdict: Structurally Unreachable Code Okay, let's break this down. First, I need to figure out if the Cadence MACB device, specifically the `macb_ptp.c` driver, is even accessible in a standard QEMU x86_64 fuzzing environment. The initial check reveals that standard QEMU primarily emulates a set of network devices, but none of them are Cadence GEM. We're talking about e1000, virtio, rtl8139, and similar common NICs – nothing that involves a Cadence GEM controller, especially not on a PCI bus within the x86_64 architecture. My QEMU source dive confirmed this. The `cadence_gem.c` driver does exist, but it's instantiated as a sysbus device, and specifically within the context of ARM SoCs like the Xilinx Zynq and Versal platforms. QEMU's x86_64 PC/Q35 emulation doesn't probe or instantiate this device. Alright, what about clever tricks with virtual buses or syzkaller? Can syzkaller somehow force the device to come into existence, either as a platform device or a PCI device? I'm familiar with those capabilities, but in this case, the answer is a firm no. Syzkaller relies on the standard QEMU environment, and it's not going to conjure up physical or specialized Cadence hardware. Furthermore, looking at the syzkaller documentation, this situation falls squarely into the "Structurally unreachable hardware" category. Let's nail down this point. The core function in question is `gem_tsu_get_time`. This function is only called if the Cadence GEM device is successfully probed and initialized – a process that involves the `gem_ptp_init` function, creating a PTP clock for the network interface. Without that hardware probe, `gem_tsu_get_time` cannot be executed. We're chasing ghosts here. So, let's clarify the patch's purpose. It's adding `rmb()` barriers before and after `gem_readl(bp, TN)` within `gem_tsu_get_time`. These barriers are meant to enforce memory ordering for MMIO register reads, synchronizing them with system timestamps as part of the PTP (Precision Time Protocol) functionality. So, it's about hardware memory-barrier ordering for MMIO reads, but for specific Cadence GEM hardware. Therefore, this patch directly modifies the code for the Cadence MACB/GEM Ethernet controller, which is vendor-specific hardware, and is absent from standard x86_64 (amd64) environments. It can't be reached because of the architecture of the simulated machine. Here's the finalized output format: * `WorthFuzzing`: false * `FocusSymbols`: \[ ] * `EnableConfigs`: \[ ] * `Reasoning`: The patch modifies driver code for the Cadence MACB/GEM Ethernet controller (`drivers/net/ethernet/cadence/macb_ptp.c`). This hardware is not present or emulated in standard x86_64 (amd64) fuzzing environments, making the modified code structurally unreachable and not warranting fuzzing.
14/2	2026/09/10 04:38	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The patch adds MMIO read memory barriers (rmb) in gem_tsu_get_time() within the Cadence MACB/GEM Ethernet driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver requires vendor-specific Cadence MACB/GEM hardware (primarily found on Atmel/Xilinx SoCs) that is not available or emulated in standard amd64 virtualized fuzzing environments (QEMU/GCE), making the modified code structurally unreachable.", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch adds MMIO read memory barriers (rmb) in gem_tsu_get_time() within the Cadence MACB/GEM Ethernet driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver requires vendor-specific Cadence MACB/GEM hardware (primarily found on Atmel/Xilinx SoCs) that is not available or emulated in standard amd64 virtualized fuzzing environments (QEMU/GCE), making the modified code structurally unreachable.", "WorthFuzzing": false }
15/1	2026/09/10 04:38	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch adds MMIO read memory barriers (rmb) in gem_tsu_get_time() within the Cadence MACB/GEM Ethernet driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver requires vendor-specific Cadence MACB/GEM hardware (primarily found on Atmel/Xilinx SoCs) that is not available or emulated in standard amd64 virtualized fuzzing environments (QEMU/GCE), making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

{
  "PatchDiff": "commit b4f7b57de5c0c01edc9e885a25ae1fd10cfec5ac\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Thu Sep 10 04:37:38 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c\nindex e5195d7dac1d5..4fb287608dc48 100644\n--- a/drivers/net/ethernet/cadence/macb_ptp.c\n+++ b/drivers/net/ethernet/cadence/macb_ptp.c\n@@ -50,7 +50,15 @@ static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts,\n \n \tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\n \tptp_read_system_prets(sts);\n+\t/* ptp_read_system_prets() uses smp_rmb() internally,\n+\t * which does not guarantee ordering against MMIO reads.\n+\t */\n+\trmb();\n \tfirst = gem_readl(bp, TN);\n+\t/* Ensure the PHC read completes before taking\n+\t * the post timestamp.\n+\t */\n+\trmb();\n \tptp_read_system_postts(sts);\n \tsecl = gem_readl(bp, TSL);\n \tsech = gem_readl(bp, TSH);\n@@ -62,7 +70,15 @@ static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts,\n \t\t * (assume all done within 1s)\n \t\t */\n \t\tptp_read_system_prets(sts);\n+\t\t/* ptp_read_system_prets() uses smp_rmb() internally,\n+\t\t * which does not guarantee ordering against MMIO reads.\n+\t\t */\n+\t\trmb();\n \t\tts-\u003etv_nsec = gem_readl(bp, TN);\n+\t\t/* Ensure the PHC read completes before taking\n+\t\t * the post timestamp.\n+\t\t */\n+\t\trmb();\n \t\tptp_read_system_postts(sts);\n \t\tsecl = gem_readl(bp, TSL);\n \t\tsech = gem_readl(bp, TSH);\n"
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch adds MMIO read memory barriers (rmb) in gem_tsu_get_time() within the Cadence MACB/GEM Ethernet driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver requires vendor-specific Cadence MACB/GEM hardware (primarily found on Atmel/Xilinx SoCs) that is not available or emulated in standard amd64 virtualized fuzzing environments (QEMU/GCE), making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit b4f7b57de5c0c01edc9e885a25ae1fd10cfec5ac
Author: syz-cluster <triage@syzkaller.com>
Date:   Thu Sep 10 04:37:38 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c
index e5195d7dac1d5..4fb287608dc48 100644
--- a/drivers/net/ethernet/cadence/macb_ptp.c
+++ b/drivers/net/ethernet/cadence/macb_ptp.c
@@ -50,7 +50,15 @@ static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts,
 
 	spin_lock_irqsave(&bp->tsu_clk_lock, flags);
 	ptp_read_system_prets(sts);
+	/* ptp_read_system_prets() uses smp_rmb() internally,
+	 * which does not guarantee ordering against MMIO reads.
+	 */
+	rmb();
 	first = gem_readl(bp, TN);
+	/* Ensure the PHC read completes before taking
+	 * the post timestamp.
+	 */
+	rmb();
 	ptp_read_system_postts(sts);
 	secl = gem_readl(bp, TSL);
 	sech = gem_readl(bp, TSH);
@@ -62,7 +70,15 @@ static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts,
 		 * (assume all done within 1s)
 		 */
 		ptp_read_system_prets(sts);
+		/* ptp_read_system_prets() uses smp_rmb() internally,
+		 * which does not guarantee ordering against MMIO reads.
+		 */
+		rmb();
 		ts->tv_nsec = gem_readl(bp, TN);
+		/* Ensure the PHC read completes before taking
+		 * the post timestamp.
+		 */
+		rmb();
 		ptp_read_system_postts(sts);
 		secl = gem_readl(bp, TSL);
 		sech = gem_readl(bp, TSH);

							input: 3213
							output: 32
							thoughts: 75

**Initial Assessment of the Code Change**

Okay, so the patch is touching `drivers/net/ethernet/cadence/macb_ptp.c`. My first move is to dive into that driver code and understand its connection to the hardware and its overall functionality, especially the PTP aspect. Given the context of a fuzzing setup, my immediate concern is whether this specific Cadence MACB controller is even reachable within a standard QEMU amd64 fuzzing environment. That's a crucial first step; if it's not present, then this whole thing is a dead end for fuzzing purposes. I need to quickly establish its presence or absence within that specific test environment. I'll need to check the Kconfig, see if there's any specific hardware configuration needed, or if it's dependent on a particular machine model. I'll be looking for clues in the Kconfig to see what kind of hardware dependency we are talking about here.

{
  "Expression": "MACB",
  "PathPrefix": "drivers/net/ethernet/cadence/"
}

{
  "Output": "\nFull output is too long, showing 500 out of 1713 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/cadence/Kconfig=20=if NET_VENDOR_CADENCE\ndrivers/net/ethernet/cadence/Kconfig-21-\ndrivers/net/ethernet/cadence/Kconfig:22:config MACB\ndrivers/net/ethernet/cadence/Kconfig:23:\ttristate \"Cadence MACB/GEM support\"\ndrivers/net/ethernet/cadence/Kconfig-24-\tdepends on HAS_DMA \u0026\u0026 COMMON_CLK\n--\ndrivers/net/ethernet/cadence/Kconfig-28-\thelp\ndrivers/net/ethernet/cadence/Kconfig:29:\t  The Cadence MACB ethernet interface is found on many Atmel AT32 and\ndrivers/net/ethernet/cadence/Kconfig-30-\t  AT91 parts.  This driver also supports the Cadence GEM (Gigabit\ndrivers/net/ethernet/cadence/Kconfig-31-\t  Ethernet MAC found in some ARM SoC devices).  Say Y to include\ndrivers/net/ethernet/cadence/Kconfig:32:\t  support for the MACB/GEM chip.\ndrivers/net/ethernet/cadence/Kconfig-33-\n--\ndrivers/net/ethernet/cadence/Kconfig-36-\ndrivers/net/ethernet/cadence/Kconfig:37:config MACB_USE_HWSTAMP\ndrivers/net/ethernet/cadence/Kconfig-38-\tbool \"Use IEEE 1588 hwstamp\"\ndrivers/net/ethernet/cadence/Kconfig:39:\tdepends on MACB\ndrivers/net/ethernet/cadence/Kconfig-40-\tdepends on PTP_1588_CLOCK\n--\ndrivers/net/ethernet/cadence/Kconfig-42-\thelp\ndrivers/net/ethernet/cadence/Kconfig:43:\t  Enable IEEE 1588 Precision Time Protocol (PTP) support for MACB.\ndrivers/net/ethernet/cadence/Kconfig-44-\ndrivers/net/ethernet/cadence/Kconfig:45:config MACB_PCI\ndrivers/net/ethernet/cadence/Kconfig:46:\ttristate \"Cadence PCI MACB/GEM support\"\ndrivers/net/ethernet/cadence/Kconfig:47:\tdepends on MACB \u0026\u0026 PCI\ndrivers/net/ethernet/cadence/Kconfig-48-\thelp\ndrivers/net/ethernet/cadence/Kconfig:49:\t  This is PCI wrapper for MACB driver.\ndrivers/net/ethernet/cadence/Kconfig-50-\n--\ndrivers/net/ethernet/cadence/Makefile=5=macb-y\t:= macb_main.o\ndrivers/net/ethernet/cadence/Makefile-6-\ndrivers/net/ethernet/cadence/Makefile:7:ifeq ($(CONFIG_MACB_USE_HWSTAMP),y)\ndrivers/net/ethernet/cadence/Makefile-8-macb-y\t+= macb_ptp.o\ndrivers/net/ethernet/cadence/Makefile=9=endif\ndrivers/net/ethernet/cadence/Makefile-10-\ndrivers/net/ethernet/cadence/Makefile:11:obj-$(CONFIG_MACB) += macb.o\ndrivers/net/ethernet/cadence/Makefile:12:obj-$(CONFIG_MACB_PCI) += macb_pci.o\n--\ndrivers/net/ethernet/cadence/macb.h-2-/*\ndrivers/net/ethernet/cadence/macb.h:3: * Atmel MACB Ethernet Controller driver\ndrivers/net/ethernet/cadence/macb.h-4- *\n--\ndrivers/net/ethernet/cadence/macb.h-6- */\ndrivers/net/ethernet/cadence/macb.h:7:#ifndef _MACB_H\ndrivers/net/ethernet/cadence/macb.h:8:#define _MACB_H\ndrivers/net/ethernet/cadence/macb.h-9-\n--\ndrivers/net/ethernet/cadence/macb.h-17-\ndrivers/net/ethernet/cadence/macb.h:18:#define MACB_GREGS_NBR 16\ndrivers/net/ethernet/cadence/macb.h:19:#define MACB_GREGS_VERSION 2\ndrivers/net/ethernet/cadence/macb.h:20:#define MACB_MAX_QUEUES 8\ndrivers/net/ethernet/cadence/macb.h-21-\ndrivers/net/ethernet/cadence/macb.h:22:/* MACB register offsets */\ndrivers/net/ethernet/cadence/macb.h:23:#define MACB_NCR\t\t0x0000 /* Network Control */\ndrivers/net/ethernet/cadence/macb.h:24:#define MACB_NCFGR\t\t0x0004 /* Network Config */\ndrivers/net/ethernet/cadence/macb.h:25:#define MACB_NSR\t\t0x0008 /* Network Status */\ndrivers/net/ethernet/cadence/macb.h:26:#define MACB_TAR\t\t0x000c /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:27:#define MACB_TCR\t\t0x0010 /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:28:#define MACB_TSR\t\t0x0014 /* Transmit Status */\ndrivers/net/ethernet/cadence/macb.h:29:#define MACB_RBQP\t\t0x0018 /* RX Q Base Address */\ndrivers/net/ethernet/cadence/macb.h:30:#define MACB_TBQP\t\t0x001c /* TX Q Base Address */\ndrivers/net/ethernet/cadence/macb.h:31:#define MACB_RSR\t\t0x0020 /* Receive Status */\ndrivers/net/ethernet/cadence/macb.h:32:#define MACB_ISR\t\t0x0024 /* Interrupt Status */\ndrivers/net/ethernet/cadence/macb.h:33:#define MACB_IER\t\t0x0028 /* Interrupt Enable */\ndrivers/net/ethernet/cadence/macb.h:34:#define MACB_IDR\t\t0x002c /* Interrupt Disable */\ndrivers/net/ethernet/cadence/macb.h:35:#define MACB_IMR\t\t0x0030 /* Interrupt Mask */\ndrivers/net/ethernet/cadence/macb.h:36:#define MACB_MAN\t\t0x0034 /* PHY Maintenance */\ndrivers/net/ethernet/cadence/macb.h:37:#define MACB_PTR\t\t0x0038\ndrivers/net/ethernet/cadence/macb.h:38:#define MACB_PFR\t\t0x003c\ndrivers/net/ethernet/cadence/macb.h:39:#define MACB_FTO\t\t0x0040\ndrivers/net/ethernet/cadence/macb.h:40:#define MACB_SCF\t\t0x0044\ndrivers/net/ethernet/cadence/macb.h:41:#define MACB_MCF\t\t0x0048\ndrivers/net/ethernet/cadence/macb.h:42:#define MACB_FRO\t\t0x004c\ndrivers/net/ethernet/cadence/macb.h:43:#define MACB_FCSE\t\t0x0050\ndrivers/net/ethernet/cadence/macb.h:44:#define MACB_ALE\t\t0x0054\ndrivers/net/ethernet/cadence/macb.h:45:#define MACB_DTF\t\t0x0058\ndrivers/net/ethernet/cadence/macb.h:46:#define MACB_LCOL\t\t0x005c\ndrivers/net/ethernet/cadence/macb.h:47:#define MACB_EXCOL\t\t0x0060\ndrivers/net/ethernet/cadence/macb.h:48:#define MACB_TUND\t\t0x0064\ndrivers/net/ethernet/cadence/macb.h:49:#define MACB_CSE\t\t0x0068\ndrivers/net/ethernet/cadence/macb.h:50:#define MACB_RRE\t\t0x006c\ndrivers/net/ethernet/cadence/macb.h:51:#define MACB_ROVR\t\t0x0070\ndrivers/net/ethernet/cadence/macb.h:52:#define MACB_RSE\t\t0x0074\ndrivers/net/ethernet/cadence/macb.h:53:#define MACB_ELE\t\t0x0078\ndrivers/net/ethernet/cadence/macb.h:54:#define MACB_RJA\t\t0x007c\ndrivers/net/ethernet/cadence/macb.h:55:#define MACB_USF\t\t0x0080\ndrivers/net/ethernet/cadence/macb.h:56:#define MACB_STE\t\t0x0084\ndrivers/net/ethernet/cadence/macb.h:57:#define MACB_RLE\t\t0x0088\ndrivers/net/ethernet/cadence/macb.h:58:#define MACB_TPF\t\t0x008c\ndrivers/net/ethernet/cadence/macb.h:59:#define MACB_HRB\t\t0x0090\ndrivers/net/ethernet/cadence/macb.h:60:#define MACB_HRT\t\t0x0094\ndrivers/net/ethernet/cadence/macb.h:61:#define MACB_SA1B\t\t0x0098\ndrivers/net/ethernet/cadence/macb.h:62:#define MACB_SA1T\t\t0x009c\ndrivers/net/ethernet/cadence/macb.h:63:#define MACB_SA2B\t\t0x00a0\ndrivers/net/ethernet/cadence/macb.h:64:#define MACB_SA2T\t\t0x00a4\ndrivers/net/ethernet/cadence/macb.h:65:#define MACB_SA3B\t\t0x00a8\ndrivers/net/ethernet/cadence/macb.h:66:#define MACB_SA3T\t\t0x00ac\ndrivers/net/ethernet/cadence/macb.h:67:#define MACB_SA4B\t\t0x00b0\ndrivers/net/ethernet/cadence/macb.h:68:#define MACB_SA4T\t\t0x00b4\ndrivers/net/ethernet/cadence/macb.h:69:#define MACB_TID\t\t0x00b8\ndrivers/net/ethernet/cadence/macb.h:70:#define MACB_TPQ\t\t0x00bc\ndrivers/net/ethernet/cadence/macb.h:71:#define MACB_USRIO\t\t0x00c0\ndrivers/net/ethernet/cadence/macb.h:72:#define MACB_WOL\t\t0x00c4\ndrivers/net/ethernet/cadence/macb.h:73:#define MACB_MID\t\t0x00fc\ndrivers/net/ethernet/cadence/macb.h:74:#define MACB_TBQPH\t\t0x04C8\ndrivers/net/ethernet/cadence/macb.h:75:#define MACB_RBQPH\t\t0x04D4\ndrivers/net/ethernet/cadence/macb.h-76-\n--\ndrivers/net/ethernet/cadence/macb.h-230-/* Bitfields in NCR */\ndrivers/net/ethernet/cadence/macb.h:231:#define MACB_LB_OFFSET\t\t0 /* reserved */\ndrivers/net/ethernet/cadence/macb.h:232:#define MACB_LB_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:233:#define MACB_LLB_OFFSET\t\t1 /* Loop back local */\ndrivers/net/ethernet/cadence/macb.h:234:#define MACB_LLB_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:235:#define MACB_RE_OFFSET\t\t2 /* Receive enable */\ndrivers/net/ethernet/cadence/macb.h:236:#define MACB_RE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:237:#define MACB_TE_OFFSET\t\t3 /* Transmit enable */\ndrivers/net/ethernet/cadence/macb.h:238:#define MACB_TE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:239:#define MACB_MPE_OFFSET\t\t4 /* Management port enable */\ndrivers/net/ethernet/cadence/macb.h:240:#define MACB_MPE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:241:#define MACB_CLRSTAT_OFFSET\t5 /* Clear stats regs */\ndrivers/net/ethernet/cadence/macb.h:242:#define MACB_CLRSTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:243:#define MACB_INCSTAT_OFFSET\t6 /* Incremental stats regs */\ndrivers/net/ethernet/cadence/macb.h:244:#define MACB_INCSTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:245:#define MACB_WESTAT_OFFSET\t7 /* Write enable stats regs */\ndrivers/net/ethernet/cadence/macb.h:246:#define MACB_WESTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:247:#define MACB_BP_OFFSET\t\t8 /* Back pressure */\ndrivers/net/ethernet/cadence/macb.h:248:#define MACB_BP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:249:#define MACB_TSTART_OFFSET\t9 /* Start transmission */\ndrivers/net/ethernet/cadence/macb.h:250:#define MACB_TSTART_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:251:#define MACB_THALT_OFFSET\t10 /* Transmit halt */\ndrivers/net/ethernet/cadence/macb.h:252:#define MACB_THALT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:253:#define MACB_NCR_TPF_OFFSET\t11 /* Transmit pause frame */\ndrivers/net/ethernet/cadence/macb.h:254:#define MACB_NCR_TPF_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:255:#define MACB_TZQ_OFFSET\t\t12 /* Transmit zero quantum pause frame */\ndrivers/net/ethernet/cadence/macb.h:256:#define MACB_TZQ_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:257:#define MACB_SRTSM_OFFSET\t15 /* Store Receive Timestamp to Memory */\ndrivers/net/ethernet/cadence/macb.h:258:#define MACB_PTPUNI_OFFSET\t20 /* PTP Unicast packet enable */\ndrivers/net/ethernet/cadence/macb.h:259:#define MACB_PTPUNI_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:260:#define MACB_OSSMODE_OFFSET\t24 /* Enable One Step Synchro Mode */\ndrivers/net/ethernet/cadence/macb.h:261:#define MACB_OSSMODE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:262:#define MACB_MIIONRGMII_OFFSET\t28 /* MII Usage on RGMII Interface */\ndrivers/net/ethernet/cadence/macb.h:263:#define MACB_MIIONRGMII_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h-264-\ndrivers/net/ethernet/cadence/macb.h-265-/* Bitfields in NCFGR */\ndrivers/net/ethernet/cadence/macb.h:266:#define MACB_SPD_OFFSET\t\t0 /* Speed */\ndrivers/net/ethernet/cadence/macb.h:267:#define MACB_SPD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:268:#define MACB_FD_OFFSET\t\t1 /* Full duplex */\ndrivers/net/ethernet/cadence/macb.h:269:#define MACB_FD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:270:#define MACB_BIT_RATE_OFFSET\t2 /* Discard non-VLAN frames */\ndrivers/net/ethernet/cadence/macb.h:271:#define MACB_BIT_RATE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:272:#define MACB_JFRAME_OFFSET\t3 /* reserved */\ndrivers/net/ethernet/cadence/macb.h:273:#define MACB_JFRAME_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:274:#define MACB_CAF_OFFSET\t\t4 /* Copy all frames */\ndrivers/net/ethernet/cadence/macb.h:275:#define MACB_CAF_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:276:#define MACB_NBC_OFFSET\t\t5 /* No broadcast */\ndrivers/net/ethernet/cadence/macb.h:277:#define MACB_NBC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:278:#define MACB_NCFGR_MTI_OFFSET\t6 /* Multicast hash enable */\ndrivers/net/ethernet/cadence/macb.h:279:#define MACB_NCFGR_MTI_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:280:#define MACB_UNI_OFFSET\t\t7 /* Unicast hash enable */\ndrivers/net/ethernet/cadence/macb.h:281:#define MACB_UNI_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:282:#define MACB_BIG_OFFSET\t\t8 /* Receive 1536 byte frames */\ndrivers/net/ethernet/cadence/macb.h:283:#define MACB_BIG_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:284:#define MACB_EAE_OFFSET\t\t9 /* External address match enable */\ndrivers/net/ethernet/cadence/macb.h:285:#define MACB_EAE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:286:#define MACB_CLK_OFFSET\t\t10\ndrivers/net/ethernet/cadence/macb.h:287:#define MACB_CLK_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:288:#define MACB_RTY_OFFSET\t\t12 /* Retry test */\ndrivers/net/ethernet/cadence/macb.h:289:#define MACB_RTY_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:290:#define MACB_PAE_OFFSET\t\t13 /* Pause enable */\ndrivers/net/ethernet/cadence/macb.h:291:#define MACB_PAE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:292:#define MACB_RM9200_RMII_OFFSET\t13 /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:293:#define MACB_RM9200_RMII_SIZE\t1  /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:294:#define MACB_RBOF_OFFSET\t14 /* Receive buffer offset */\ndrivers/net/ethernet/cadence/macb.h:295:#define MACB_RBOF_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:296:#define MACB_RLCE_OFFSET\t16 /* Length field error frame discard */\ndrivers/net/ethernet/cadence/macb.h:297:#define MACB_RLCE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:298:#define MACB_DRFCS_OFFSET\t17 /* FCS remove */\ndrivers/net/ethernet/cadence/macb.h:299:#define MACB_DRFCS_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:300:#define MACB_EFRHD_OFFSET\t18\ndrivers/net/ethernet/cadence/macb.h:301:#define MACB_EFRHD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:302:#define MACB_IRXFCS_OFFSET\t19\ndrivers/net/ethernet/cadence/macb.h:303:#define MACB_IRXFCS_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h-304-\n--\ndrivers/net/ethernet/cadence/macb.h-364-/* Bitfields in NSR */\ndrivers/net/ethernet/cadence/macb.h:365:#define MACB_NSR_LINK_OFFSET\t0 /* pcs_link_state */\ndrivers/net/ethernet/cadence/macb.h:366:#define MACB_NSR_LINK_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:367:#define MACB_MDIO_OFFSET\t1 /* status of the mdio_in pin */\ndrivers/net/ethernet/cadence/macb.h:368:#define MACB_MDIO_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:369:#define MACB_IDLE_OFFSET\t2 /* The PHY management logic is idle */\ndrivers/net/ethernet/cadence/macb.h:370:#define MACB_IDLE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-371-\ndrivers/net/ethernet/cadence/macb.h-372-/* Bitfields in TSR */\ndrivers/net/ethernet/cadence/macb.h:373:#define MACB_UBR_OFFSET\t\t0 /* Used bit read */\ndrivers/net/ethernet/cadence/macb.h:374:#define MACB_UBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:375:#define MACB_COL_OFFSET\t\t1 /* Collision occurred */\ndrivers/net/ethernet/cadence/macb.h:376:#define MACB_COL_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:377:#define MACB_TSR_RLE_OFFSET\t2 /* Retry limit exceeded */\ndrivers/net/ethernet/cadence/macb.h:378:#define MACB_TSR_RLE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:379:#define MACB_TGO_OFFSET\t\t3 /* Transmit go */\ndrivers/net/ethernet/cadence/macb.h:380:#define MACB_TGO_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:381:#define MACB_BEX_OFFSET\t\t4 /* TX frame corruption due to AHB error */\ndrivers/net/ethernet/cadence/macb.h:382:#define MACB_BEX_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:383:#define MACB_RM9200_BNQ_OFFSET\t4 /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:384:#define MACB_RM9200_BNQ_SIZE\t1 /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:385:#define MACB_COMP_OFFSET\t5 /* Trnasmit complete */\ndrivers/net/ethernet/cadence/macb.h:386:#define MACB_COMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:387:#define MACB_UND_OFFSET\t\t6 /* Trnasmit under run */\ndrivers/net/ethernet/cadence/macb.h:388:#define MACB_UND_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-389-\ndrivers/net/ethernet/cadence/macb.h-390-/* Bitfields in RSR */\ndrivers/net/ethernet/cadence/macb.h:391:#define MACB_BNA_OFFSET\t\t0 /* Buffer not available */\ndrivers/net/ethernet/cadence/macb.h:392:#define MACB_BNA_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:393:#define MACB_REC_OFFSET\t\t1 /* Frame received */\ndrivers/net/ethernet/cadence/macb.h:394:#define MACB_REC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:395:#define MACB_OVR_OFFSET\t\t2 /* Receive overrun */\ndrivers/net/ethernet/cadence/macb.h:396:#define MACB_OVR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-397-\ndrivers/net/ethernet/cadence/macb.h-398-/* Bitfields in ISR/IER/IDR/IMR */\ndrivers/net/ethernet/cadence/macb.h:399:#define MACB_MFD_OFFSET\t\t0 /* Management frame sent */\ndrivers/net/ethernet/cadence/macb.h:400:#define MACB_MFD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:401:#define MACB_RCOMP_OFFSET\t1 /* Receive complete */\ndrivers/net/ethernet/cadence/macb.h:402:#define MACB_RCOMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:403:#define MACB_RXUBR_OFFSET\t2 /* RX used bit read */\ndrivers/net/ethernet/cadence/macb.h:404:#define MACB_RXUBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:405:#define MACB_TXUBR_OFFSET\t3 /* TX used bit read */\ndrivers/net/ethernet/cadence/macb.h:406:#define MACB_TXUBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:407:#define MACB_ISR_TUND_OFFSET\t4 /* Enable TX buffer under run interrupt */\ndrivers/net/ethernet/cadence/macb.h:408:#define MACB_ISR_TUND_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:409:#define MACB_ISR_RLE_OFFSET\t5 /* EN retry exceeded/late coll interrupt */\ndrivers/net/ethernet/cadence/macb.h:410:#define MACB_ISR_RLE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:411:#define MACB_TXERR_OFFSET\t6 /* EN TX frame corrupt from error interrupt */\ndrivers/net/ethernet/cadence/macb.h:412:#define MACB_TXERR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:413:#define MACB_RM9200_TBRE_OFFSET\t6 /* EN may send new frame interrupt (RM9200) */\ndrivers/net/ethernet/cadence/macb.h:414:#define MACB_RM9200_TBRE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:415:#define MACB_TCOMP_OFFSET\t7 /* Enable transmit complete interrupt */\ndrivers/net/ethernet/cadence/macb.h:416:#define MACB_TCOMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:417:#define MACB_ISR_LINK_OFFSET\t9 /* Enable link change interrupt */\ndrivers/net/ethernet/cadence/macb.h:418:#define MACB_ISR_LINK_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:419:#define MACB_ISR_ROVR_OFFSET\t10 /* Enable receive overrun interrupt */\ndrivers/net/ethernet/cadence/macb.h:420:#define MACB_ISR_ROVR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:421:#define MACB_HRESP_OFFSET\t11 /* Enable hrsep not OK interrupt */\ndrivers/net/ethernet/cadence/macb.h:422:#define MACB_HRESP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:423:#define MACB_PFR_OFFSET\t\t12 /* Enable pause frame w/ quantum interrupt */\ndrivers/net/ethernet/cadence/macb.h:424:#define MACB_PFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:425:#define MACB_PTZ_OFFSET\t\t13 /* Enable pause time zero interrupt */\ndrivers/net/ethernet/cadence/macb.h:426:#define MACB_PTZ_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:427:#define MACB_WOL_OFFSET\t\t14 /* Enable wake-on-lan interrupt */\ndrivers/net/ethernet/cadence/macb.h:428:#define MACB_WOL_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:429:#define MACB_DRQFR_OFFSET\t18 /* PTP Delay Request Frame Received */\ndrivers/net/ethernet/cadence/macb.h:430:#define MACB_DRQFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:431:#define MACB_SFR_OFFSET\t\t19 /* PTP Sync Frame Received */\ndrivers/net/ethernet/cadence/macb.h:432:#define MACB_SFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:433:#define MACB_DRQFT_OFFSET\t20 /* PTP Delay Request Frame Transmitted */\ndrivers/net/ethernet/cadence/macb.h:434:#define MACB_DRQFT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:435:#define MACB_SFT_OFFSET\t\t21 /* PTP Sync Frame Transmitted */\ndrivers/net/ethernet/cadence/macb.h:436:#define MACB_SFT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:437:#define MACB_PDRQFR_OFFSET\t22 /* PDelay Request Frame Received */\ndrivers/net/ethernet/cadence/macb.h:438:#define MACB_PDRQFR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:439:#define MACB_PDRSFR_OFFSET\t23 /* PDelay Response Frame Received */\ndrivers/net/ethernet/cadence/macb.h:440:#define MACB_PDRSFR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:441:#define MACB_PDRQFT_OFFSET\t24 /* PDelay Request Frame Transmitted */\ndrivers/net/ethernet/cadence/macb.h:442:#define MACB_PDRQFT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:443:#define MACB_PDRSFT_OFFSET\t25 /* PDelay Response Frame Transmitted */\ndrivers/net/ethernet/cadence/macb.h:444:#define MACB_PDRSFT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:445:#define MACB_SRI_OFFSET\t\t26 /* TSU Seconds Register Increment */\ndrivers/net/ethernet/cadence/macb.h:446:#define MACB_SRI_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-447-#define GEM_WOL_OFFSET\t\t28 /* Enable wake-on-lan interrupt */\n--\ndrivers/net/ethernet/cadence/macb.h-450-/* Timer increment fields */\ndrivers/net/ethernet/cadence/macb.h:451:#define MACB_TI_CNS_OFFSET\t0\ndrivers/net/ethernet/cadence/macb.h:452:#define MACB_TI_CNS_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h:453:#define MACB_TI_ACNS_OFFSET\t8\ndrivers/net/ethernet/cadence/macb.h:454:#define MACB_TI_ACNS_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h:455:#define MACB_TI_NIT_OFFSET\t16\ndrivers/net/ethernet/cadence/macb.h:456:#define MACB_TI_NIT_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h-457-\ndrivers/net/ethernet/cadence/macb.h-458-/* Bitfields in MAN */\ndrivers/net/ethernet/cadence/macb.h:459:#define MACB_DATA_OFFSET\t0 /* data */\ndrivers/net/ethernet/cadence/macb.h:460:#define MACB_DATA_SIZE\t\t16\ndrivers/net/ethernet/cadence/macb.h:461:#define MACB_CODE_OFFSET\t16 /* Must be written to 10 */\ndrivers/net/ethernet/cadence/macb.h:462:#define MACB_CODE_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:463:#define MACB_REGA_OFFSET\t18 /* Register address */\ndrivers/net/ethernet/cadence/macb.h:464:#define MACB_REGA_SIZE\t\t5\ndrivers/net/ethernet/cadence/macb.h:465:#define MACB_PHYA_OFFSET\t23 /* PHY address */\ndrivers/net/ethernet/cadence/macb.h:466:#define MACB_PHYA_SIZE\t\t5\ndrivers/net/ethernet/cadence/macb.h:467:#define MACB_RW_OFFSET\t\t28 /* Operation. 10 is read. 01 is write. */\ndrivers/net/ethernet/cadence/macb.h:468:#define MACB_RW_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:469:#define MACB_SOF_OFFSET\t\t30 /* Must be written to 1 for Clause 22 */\ndrivers/net/ethernet/cadence/macb.h:470:#define MACB_SOF_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h-471-\ndrivers/net/ethernet/cadence/macb.h-472-/* Bitfields in USRIO (AVR32) */\ndrivers/net/ethernet/cadence/macb.h:473:#define MACB_MII_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:474:#define MACB_MII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:475:#define MACB_EAM_OFFSET\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:476:#define MACB_EAM_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:477:#define MACB_TX_PAUSE_OFFSET\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:478:#define MACB_TX_PAUSE_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:479:#define MACB_TX_PAUSE_ZERO_OFFSET\t\t3\ndrivers/net/ethernet/cadence/macb.h:480:#define MACB_TX_PAUSE_ZERO_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-481-\ndrivers/net/ethernet/cadence/macb.h-482-/* Bitfields in USRIO (AT91) */\ndrivers/net/ethernet/cadence/macb.h:483:#define MACB_RMII_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:484:#define MACB_RMII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-485-#define GEM_RGMII_OFFSET\t\t\t0 /* GEM gigabit mode */\ndrivers/net/ethernet/cadence/macb.h-486-#define GEM_RGMII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:487:#define MACB_CLKEN_OFFSET\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:488:#define MACB_CLKEN_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-489-\ndrivers/net/ethernet/cadence/macb.h-490-/* Bitfields in WOL */\ndrivers/net/ethernet/cadence/macb.h:491:#define MACB_IP_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:492:#define MACB_IP_SIZE\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:493:#define MACB_MAG_OFFSET\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:494:#define MACB_MAG_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:495:#define MACB_ARP_OFFSET\t\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:496:#define MACB_ARP_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:497:#define MACB_SA1_OFFSET\t\t\t\t18\ndrivers/net/ethernet/cadence/macb.h:498:#define MACB_SA1_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:499:#define MACB_WOL_MTI_OFFSET\t\t\t19\ndrivers/net/ethernet/cadence/macb.h:500:#define MACB_WOL_MTI_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-501-\ndrivers/net/ethernet/cadence/macb.h-502-/* Bitfields in MID */\ndrivers/net/ethernet/cadence/macb.h:503:#define MACB_IDNUM_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:504:#define MACB_IDNUM_SIZE\t\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:505:#define MACB_REV_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:506:#define MACB_REV_SIZE\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h-507-\n--\ndrivers/net/ethernet/cadence/macb.h-678-/* Bitfields in queue pointer registers */\ndrivers/net/ethernet/cadence/macb.h:679:#define MACB_QUEUE_DISABLE_OFFSET\t\t0 /* disable queue */\ndrivers/net/ethernet/cadence/macb.h:680:#define MACB_QUEUE_DISABLE_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-681-\n--\ndrivers/net/ethernet/cadence/macb.h-729-/* Constants for CLK */\ndrivers/net/ethernet/cadence/macb.h:730:#define MACB_CLK_DIV8\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:731:#define MACB_CLK_DIV16\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:732:#define MACB_CLK_DIV32\t\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:733:#define MACB_CLK_DIV64\t\t\t\t3\ndrivers/net/ethernet/cadence/macb.h-734-\n--\ndrivers/net/ethernet/cadence/macb.h-745-/* Constants for MAN register */\ndrivers/net/ethernet/cadence/macb.h:746:#define MACB_MAN_C22_SOF\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:747:#define MACB_MAN_C22_WRITE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:748:#define MACB_MAN_C22_READ\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:749:#define MACB_MAN_C22_CODE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h-750-\ndrivers/net/ethernet/cadence/macb.h:751:#define MACB_MAN_C45_SOF\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:752:#define MACB_MAN_C45_ADDR\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:753:#define MACB_MAN_C45_WRITE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:754:#define MACB_MAN_C45_POST_READ_INCR\t\t2\ndrivers/net/ethernet/cadence/macb.h:755:#define MACB_MAN_C45_READ\t\t\t3\ndrivers/net/ethernet/cadence/macb.h:756:#define MACB_MAN_C45_CODE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h-757-\ndrivers/net/ethernet/cadence/macb.h-758-/* Capability mask bits */\ndrivers/net/ethernet/cadence/macb.h:759:#define MACB_CAPS_ISR_CLEAR_ON_WRITE\t\tBIT(0)\ndrivers/net/ethernet/cadence/macb.h:760:#define MACB_CAPS_USRIO_HAS_CLKEN\t\tBIT(1)\ndrivers/net/ethernet/cadence/macb.h:761:#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII\tBIT(2)\ndrivers/net/ethernet/cadence/macb.h:762:#define MACB_CAPS_NO_GIGABIT_HALF\t\tBIT(3)\ndrivers/net/ethernet/cadence/macb.h:763:#define MACB_CAPS_USRIO_DISABLED\t\tBIT(4)\ndrivers/net/ethernet/cadence/macb.h:764:#define MACB_CAPS_JUMBO\t\t\t\tBIT(5)\ndrivers/net/ethernet/cadence/macb.h:765:#define MACB_CAPS_GEM_HAS_PTP\t\t\tBIT(6)\ndrivers/net/ethernet/cadence/macb.h:766:#define MACB_CAPS_BD_RD_PREFETCH\t\tBIT(7)\ndrivers/net/ethernet/cadence/macb.h:767:#define MACB_CAPS_NEEDS_RSTONUBR\t\tBIT(8)\ndrivers/net/ethernet/cadence/macb.h:768:#define MACB_CAPS_MIIONRGMII\t\t\tBIT(9)\ndrivers/net/ethernet/cadence/macb.h:769:#define MACB_CAPS_NEED_TSUCLK\t\t\tBIT(10)\ndrivers/net/ethernet/cadence/macb.h:770:#define MACB_CAPS_QUEUE_DISABLE\t\t\tBIT(11)\ndrivers/net/ethernet/cadence/macb.h:771:#define MACB_CAPS_QBV\t\t\t\tBIT(12)\ndrivers/net/ethernet/cadence/macb.h:772:#define MACB_CAPS_PCS\t\t\t\tBIT(13)\ndrivers/net/ethernet/cadence/macb.h:773:#define MACB_CAPS_HIGH_SPEED\t\t\tBIT(14)\ndrivers/net/ethernet/cadence/macb.h:774:#define MACB_CAPS_CLK_HW_CHG\t\t\tBIT(15)\ndrivers/net/ethernet/cadence/macb.h:775:#define MACB_CAPS_MACB_IS_EMAC\t\t\tBIT(16)\ndrivers/net/ethernet/cadence/macb.h:776:#define MACB_CAPS_FIFO_MODE\t\t\tBIT(17)\ndrivers/net/ethernet/cadence/macb.h:777:#define MACB_CAPS_GIGABIT_MODE_AVAILABLE\tBIT(18)\ndrivers/net/ethernet/cadence/macb.h:778:#define MACB_CAPS_SG_DISABLED\t\t\tBIT(19)\ndrivers/net/ethernet/cadence/macb.h:779:#define MACB_CAPS_MACB_IS_GEM\t\t\tBIT(20)\ndrivers/net/ethernet/cadence/macb.h:780:#define MACB_CAPS_DMA_64B\t\t\tBIT(21)\ndrivers/net/ethernet/cadence/macb.h:781:#define MACB_CAPS_DMA_PTP\t\t\tBIT(22)\ndrivers/net/ethernet/cadence/macb.h:782:#define MACB_CAPS_RSC\t\t\t\tBIT(23)\ndrivers/net/ethernet/cadence/macb.h:783:#define MACB_CAPS_NO_LSO\t\t\tBIT(24)\ndrivers/net/ethernet/cadence/macb.h:784:#define MACB_CAPS_EEE\t\t\t\tBIT(25)\ndrivers/net/ethernet/cadence/macb.h:785:#define MACB_CAPS_USRIO_HAS_MII\t\t\tBIT(26)\ndrivers/net/ethernet/cadence/macb.h:786:#define MACB_CAPS_USRIO_HAS_REFCLK_SOURCE\tBIT(27)\ndrivers/net/ethernet/cadence/macb.h:787:#define MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE\tBIT(28)\ndrivers/net/ethernet/cadence/macb.h-788-\ndrivers/net/ethernet/cadence/macb.h-789-/* LSO settings */\ndrivers/net/ethernet/cadence/macb.h:790:#define MACB_LSO_UFO_ENABLE\t\t\t0x01\ndrivers/net/ethernet/cadence/macb.h:791:#define MACB_LSO_TSO_ENABLE\t\t\t0x02\ndrivers/net/ethernet/cadence/macb.h-792-\ndrivers/net/ethernet/cadence/macb.h-793-/* Bit manipulation macros */\ndrivers/net/ethernet/cadence/macb.h:794:#define MACB_BIT(name)\t\t\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:795:\t(1 \u003c\u003c MACB_##name##_OFFSET)\ndrivers/net/ethernet/cadence/macb.h:796:#define MACB_BF(name,value)\t\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:797:\t(((value) \u0026 ((1 \u003c\u003c MACB_##name##_SIZE) - 1))\t\\\ndrivers/net/ethernet/cadence/macb.h:798:\t \u003c\u003c MACB_##name##_OFFSET)\ndrivers/net/ethernet/cadence/macb.h:799:#define MACB_BFEXT(name,value)\\\ndrivers/net/ethernet/cadence/macb.h:800:\t(((value) \u003e\u003e MACB_##name##_OFFSET)\t\t\\\ndrivers/net/ethernet/cadence/macb.h:801:\t \u0026 ((1 \u003c\u003c MACB_##name##_SIZE) - 1))\ndrivers/net/ethernet/cadence/macb.h:802:#define MACB_BFINS(name,value,old)\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:803:\t(((old) \u0026 ~(((1 \u003c\u003c MACB_##name##_SIZE) - 1)\t\\\ndrivers/net/ethernet/cadence/macb.h:804:\t\t    \u003c\u003c MACB_##name##_OFFSET))\t\t\\\ndrivers/net/ethernet/cadence/macb.h:805:\t | MACB_BF(name,value))\ndrivers/net/ethernet/cadence/macb.h-806-\n--\ndrivers/net/ethernet/cadence/macb.h-820-/* Register access macros */\ndrivers/net/ethernet/cadence/macb.h:821:#define macb_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), MACB_##reg)\ndrivers/net/ethernet/cadence/macb.h:822:#define macb_writel(port, reg, value)\t(port)-\u003emacb_reg_writel((port), MACB_##reg, (value))\ndrivers/net/ethernet/cadence/macb.h-823-#define gem_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), GEM_##reg)\n--\ndrivers/net/ethernet/cadence/macb.h-829-\ndrivers/net/ethernet/cadence/macb.h:830:/* Conditional GEM/MACB macros.  These perform the operation to the correct\ndrivers/net/ethernet/cadence/macb.h:831: * register dependent on whether the device is a GEM or a MACB.  For registers\ndrivers/net/ethernet/cadence/macb.h-832- * and bitfields that are common across both devices, use macb_{read,write}l\n--\ndrivers/net/ethernet/cadence/macb.h-852-\ndrivers/net/ethernet/cadence/macb.h:853:#define MACB_READ_NSR(bp)\tmacb_readl(bp, NSR)\ndrivers/net/ethernet/cadence/macb.h-854-\n--\ndrivers/net/ethernet/cadence/macb.h=869=struct macb_dma_desc_ptp {\n--\ndrivers/net/ethernet/cadence/macb.h-874-/* DMA descriptor bitfields */\ndrivers/net/ethernet/cadence/macb.h:875:#define MACB_RX_USED_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:876:#define MACB_RX_USED_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:877:#define MACB_RX_WRAP_OFFSET\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:878:#define MACB_RX_WRAP_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:879:#define MACB_RX_WADDR_OFFSET\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:880:#define MACB_RX_WADDR_SIZE\t\t\t30\ndrivers/net/ethernet/cadence/macb.h-881-\ndrivers/net/ethernet/cadence/macb.h:882:#define MACB_RX_FRMLEN_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:883:#define MACB_RX_FRMLEN_SIZE\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:884:#define MACB_RX_OFFSET_OFFSET\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:885:#define MACB_RX_OFFSET_SIZE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:886:#define MACB_RX_SOF_OFFSET\t\t\t14\ndrivers/net/ethernet/cadence/macb.h:887:#define MACB_RX_SOF_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:888:#define MACB_RX_EOF_OFFSET\t\t\t15\ndrivers/net/ethernet/cadence/macb.h:889:#define MACB_RX_EOF_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:890:#define MACB_RX_CFI_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:891:#define MACB_RX_CFI_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:892:#define MACB_RX_VLAN_PRI_OFFSET\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:893:#define MACB_RX_VLAN_PRI_SIZE\t\t\t3\ndrivers/net/ethernet/cadence/macb.h:894:#define MACB_RX_PRI_TAG_OFFSET\t\t\t20\ndrivers/net/ethernet/cadence/macb.h:895:#define MACB_RX_PRI_TAG_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:896:#define MACB_RX_VLAN_TAG_OFFSET\t\t\t21\ndrivers/net/ethernet/cadence/macb.h:897:#define MACB_RX_VLAN_TAG_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:898:#define MACB_RX_TYPEID_MATCH_OFFSET\t\t22\ndrivers/net/ethernet/cadence/macb.h:899:#define MACB_RX_TYPEID_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:900:#define MACB_RX_SA4_MATCH_OFFSET\t\t23\ndrivers/net/ethernet/cadence/macb.h:901:#define MACB_RX_SA4_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:902:#define MACB_RX_SA3_MATCH_OFFSET\t\t24\ndrivers/net/ethernet/cadence/macb.h:903:#define MACB_RX_SA3_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:904:#define MACB_RX_SA2_MATCH_OFFSET\t\t25\ndrivers/net/ethernet/cadence/macb.h:905:#define MACB_RX_SA2_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:906:#define MACB_RX_SA1_MATCH_OFFSET\t\t26\ndrivers/net/ethernet/cadence/macb.h:907:#define MACB_RX_SA1_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:908:#define MACB_RX_EXT_MATCH_OFFSET\t\t28\ndrivers/net/ethernet/cadence/macb.h:909:#define MACB_RX_EXT_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:910:#define MACB_RX_UHASH_MATCH_OFFSET\t\t29\ndrivers/net/ethernet/cadence/macb.h:911:#define MACB_RX_UHASH_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:912:#define MACB_RX_MHASH_MATCH_OFFSET\t\t30\ndrivers/net/ethernet/cadence/macb.h:913:#define MACB_RX_MHASH_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:914:#define MACB_RX_BROADCAST_OFFSET\t\t31\ndrivers/net/ethernet/cadence/macb.h:915:#define MACB_RX_BROADCAST_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-916-\ndrivers/net/ethernet/cadence/macb.h:917:#define MACB_RX_FRMLEN_MASK\t\t\t0xFFF\ndrivers/net/ethernet/cadence/macb.h:918:#define MACB_RX_JFRMLEN_MASK\t\t\t0x3FFF\ndrivers/net/ethernet/cadence/macb.h-919-\n--\ndrivers/net/ethernet/cadence/macb.h-927-\ndrivers/net/ethernet/cadence/macb.h:928:#define MACB_TX_FRMLEN_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:929:#define MACB_TX_FRMLEN_SIZE\t\t\t11\ndrivers/net/ethernet/cadence/macb.h:930:#define MACB_TX_LAST_OFFSET\t\t\t15\ndrivers/net/ethernet/cadence/macb.h:931:#define MACB_TX_LAST_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:932:#define MACB_TX_NOCRC_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:933:#define MACB_TX_NOCRC_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:934:#define MACB_MSS_MFS_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:935:#define MACB_MSS_MFS_SIZE\t\t\t14\ndrivers/net/ethernet/cadence/macb.h:936:#define MACB_TX_LSO_OFFSET\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:937:#define MACB_TX_LSO_SIZE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:938:#define MACB_TX_TCP_SEQ_SRC_OFFSET\t\t19\ndrivers/net/ethernet/cadence/macb.h:939:#define MACB_TX_TCP_SEQ_SRC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:940:#define MACB_TX_BUF_EXHAUSTED_OFFSET\t\t27\ndrivers/net/ethernet/cadence/macb.h:941:#define MACB_TX_BUF_EXHAUSTED_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:942:#define MACB_TX_UNDERRUN_OFFSET\t\t\t28\ndrivers/net/ethernet/cadence/macb.h:943:#define MACB_TX_UNDERRUN_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:944:#define MACB_TX_ERROR_OFFSET\t\t\t29\ndrivers/net/ethernet/cadence/macb.h:945:#define MACB_TX_ERROR_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:946:#define MACB_TX_WRAP_OFFSET\t\t\t30\ndrivers/net/ethernet/cadence/macb.h:947:#define MACB_TX_WRAP_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:948:#define MACB_TX_USED_OFFSET\t\t\t31\ndrivers/net/ethernet/cadence/macb.h:949:#define MACB_TX_USED_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-950-\n--\ndrivers/net/ethernet/cadence/macb.h=1197=struct macb_or_gem_ops {\n--\ndrivers/net/ethernet/cadence/macb.h-1204-\ndrivers/net/ethernet/cadence/macb.h:1205:/* MACB-PTP interface: adapt to platform needs. */\ndrivers/net/ethernet/cadence/macb.h-1206-struct macb_ptp_info {\n--\ndrivers/net/ethernet/cadence/macb.h=1301=struct macb {\n--\ndrivers/net/ethernet/cadence/macb.h-1316-\tunsigned int\t\tnum_queues;\n\n"
}

							input: 18853
							output: 36
							thoughts: 160

**My QEMU / Cadence MACB PCI Investigation**

Okay, so I'm looking into the Cadence MACB / GEM ethernet controller, specifically the PCI implementation. I know `macb_pci.c` and `macb_main.c` are the relevant source files. The question is, does QEMU emulate the Cadence MACB in a PCI configuration, and if so, how? My initial thought is that it might be emulated, but I need to confirm.

Ah, yes! I remember QEMU having `cadence_gem` emulation! But does that apply to the PCI implementation? A quick search reminds me that QEMU utilizes `cadence_gem` for Xilinx Zynq, ZynqMP, and Versal platforms, which all use ARM/AArch64 or MicroBlaze architectures. So, *where* does this fit in with PCI? Does QEMU use `macb_pci` directly, or does it somehow map that to `cadence_gem` on PCI devices?

To be sure, I'll check `macb_pci.c`. I need to figure out which PCI devices it's designed to match. That will give me a clear idea of what the QEMU emulation targets. Let's dig in.

{
  "Expression": "pci_device_id",
  "PathPrefix": "drivers/net/ethernet/cadence/"
}

{
  "Output": "drivers/net/ethernet/cadence/macb_pci.c-26-\ndrivers/net/ethernet/cadence/macb_pci.c:27:static int macb_probe(struct pci_dev *pci, const struct pci_device_id *id)\ndrivers/net/ethernet/cadence/macb_pci.c-28-{\n--\ndrivers/net/ethernet/cadence/macb_pci.c=108=static void macb_remove(struct pci_dev *pci)\n--\ndrivers/net/ethernet/cadence/macb_pci.c-119-\ndrivers/net/ethernet/cadence/macb_pci.c:120:static const struct pci_device_id dev_id_table[] = {\ndrivers/net/ethernet/cadence/macb_pci.c-121-\t{ PCI_VDEVICE(CDNS, PCI_DEVICE_ID_CDNS_MACB) },\n"
}

							input: 19587
							output: 44
							thoughts: 29

Okay, here's my take on those thoughts, framed as if they're mine:

**Diving into the MACB Driver**

Right, time to get my hands dirty. Let's see... the issue we're tackling likely involves how the device is identified and probed, so my first instinct is to zero in on `macb_pci.c`. Specifically, I want to refresh my memory about how the `dev_id_table` is structured – that's the crucial mapping between PCI device IDs and the MACB driver. I need to understand how the driver knows *which* devices it should attach to. Then, I'll jump over to the `macb_probe` function. That's the function that gets called when a matching device is found. I need to reconstruct the execution flow here - how it verifies device compatibility, initializes the hardware, and ultimately makes the device ready for use by the system. Understanding this control flow should clarify the root of the problem.

{
  "File": "drivers/net/ethernet/cadence/macb_pci.c",
  "FirstLine": 1,
  "LineCount": 130
}

{
  "Contents": "   1:\t// SPDX-License-Identifier: GPL-2.0-only\n   2:\t/*\n   3:\t * DOC: Cadence GEM PCI wrapper.\n   4:\t *\n   5:\t * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com\n   6:\t *\n   7:\t * Authors: Rafal Ozieblo \u003crafalo@cadence.com\u003e\n   8:\t *\t    Bartosz Folta \u003cbfolta@cadence.com\u003e\n   9:\t */\n  10:\t\n  11:\t#include \u003clinux/clk.h\u003e\n  12:\t#include \u003clinux/clk-provider.h\u003e\n  13:\t#include \u003clinux/etherdevice.h\u003e\n  14:\t#include \u003clinux/module.h\u003e\n  15:\t#include \u003clinux/pci.h\u003e\n  16:\t#include \u003clinux/platform_device.h\u003e\n  17:\t#include \"macb.h\"\n  18:\t\n  19:\t#define PCI_DRIVER_NAME \"macb_pci\"\n  20:\t#define PLAT_DRIVER_NAME \"macb\"\n  21:\t\n  22:\t#define PCI_DEVICE_ID_CDNS_MACB 0xe007\n  23:\t\n  24:\t#define GEM_PCLK_RATE 50000000\n  25:\t#define GEM_HCLK_RATE 50000000\n  26:\t\n  27:\tstatic int macb_probe(struct pci_dev *pci, const struct pci_device_id *id)\n  28:\t{\n  29:\t\tint err;\n  30:\t\tstruct platform_device *pdev;\n  31:\t\tstruct platform_device_info plat_info;\n  32:\t\tstruct macb_platform_data plat_data;\n  33:\t\tstruct resource res[2];\n  34:\t\n  35:\t\t/* enable pci device */\n  36:\t\terr = pcim_enable_device(pci);\n  37:\t\tif (err \u003c 0) {\n  38:\t\t\tdev_err(\u0026pci-\u003edev, \"Enabling PCI device has failed: %d\", err);\n  39:\t\t\treturn err;\n  40:\t\t}\n  41:\t\n  42:\t\tpci_set_master(pci);\n  43:\t\n  44:\t\t/* set up resources */\n  45:\t\tmemset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));\n  46:\t\tres[0].start = pci_resource_start(pci, 0);\n  47:\t\tres[0].end = pci_resource_end(pci, 0);\n  48:\t\tres[0].name = PCI_DRIVER_NAME;\n  49:\t\tres[0].flags = IORESOURCE_MEM;\n  50:\t\tres[1].start = pci_irq_vector(pci, 0);\n  51:\t\tres[1].name = PCI_DRIVER_NAME;\n  52:\t\tres[1].flags = IORESOURCE_IRQ;\n  53:\t\n  54:\t\tdev_info(\u0026pci-\u003edev, \"EMAC physical base addr: %pa\\n\",\n  55:\t\t\t \u0026res[0].start);\n  56:\t\n  57:\t\t/* set up macb platform data */\n  58:\t\tmemset(\u0026plat_data, 0, sizeof(plat_data));\n  59:\t\n  60:\t\t/* initialize clocks */\n  61:\t\tplat_data.pclk = clk_register_fixed_rate(\u0026pci-\u003edev, \"pclk\", NULL, 0,\n  62:\t\t\t\t\t\t\t GEM_PCLK_RATE);\n  63:\t\tif (IS_ERR(plat_data.pclk)) {\n  64:\t\t\terr = PTR_ERR(plat_data.pclk);\n  65:\t\t\tgoto err_pclk_register;\n  66:\t\t}\n  67:\t\n  68:\t\tplat_data.hclk = clk_register_fixed_rate(\u0026pci-\u003edev, \"hclk\", NULL, 0,\n  69:\t\t\t\t\t\t\t GEM_HCLK_RATE);\n  70:\t\tif (IS_ERR(plat_data.hclk)) {\n  71:\t\t\terr = PTR_ERR(plat_data.hclk);\n  72:\t\t\tgoto err_hclk_register;\n  73:\t\t}\n  74:\t\n  75:\t\t/* set up platform device info */\n  76:\t\tmemset(\u0026plat_info, 0, sizeof(plat_info));\n  77:\t\tplat_info.parent = \u0026pci-\u003edev;\n  78:\t\tplat_info.fwnode = pci-\u003edev.fwnode;\n  79:\t\tplat_info.name = PLAT_DRIVER_NAME;\n  80:\t\tplat_info.id = pci-\u003edevfn;\n  81:\t\tplat_info.res = res;\n  82:\t\tplat_info.num_res = ARRAY_SIZE(res);\n  83:\t\tplat_info.data = \u0026plat_data;\n  84:\t\tplat_info.size_data = sizeof(plat_data);\n  85:\t\tplat_info.dma_mask = pci-\u003edma_mask;\n  86:\t\n  87:\t\t/* register platform device */\n  88:\t\tpdev = platform_device_register_full(\u0026plat_info);\n  89:\t\tif (IS_ERR(pdev)) {\n  90:\t\t\terr = PTR_ERR(pdev);\n  91:\t\t\tgoto err_plat_dev_register;\n  92:\t\t}\n  93:\t\n  94:\t\tpci_set_drvdata(pci, pdev);\n  95:\t\n  96:\t\treturn 0;\n  97:\t\n  98:\terr_plat_dev_register:\n  99:\t\tclk_unregister_fixed_rate(plat_data.hclk);\n 100:\t\n"
}

							input: 21394
							output: 43
							thoughts: 333

**My Assessment of the Cadence MACB / GEM Ethernet Controller for Fuzzing**

Okay, let's break this down. I'm looking at this Cadence MACB/GEM ethernet controller – it's a vendor-specific hardware MAC, like you'd find on Atmel, AT32, or potentially Cadence's GEM IP in Xilinx Zynq ARM systems, FPGAs, or even a PCI prototype card. The immediate question in my mind is, on a standard amd64 system, running in a virtualized environment like GCE or QEMU, can I *actually* reach and execute this code, specifically with `CONFIG_MACB` enabled?

I need to refer to the fuzzing guidelines. The key takeaway, the *primary* gatekeeper, is reachability. The guidelines state clearly that fuzzing is only valid for code that *executes* within standard virtualized setups, using software-emulated devices. If the code is, in a word, unreachable, then fuzzing is out of the question, regardless of its internal complexity or if there are additional assertion statements.

Now, according to the guidelines, I can mark something as `WorthFuzzing=false` only if the modified code falls into certain categories. The crucial one for me here is structurally unreachable hardware, such as vendor-specific PCIe switches, or drivers that need specific physical hardware not emulated in standard QEMU. Unreachable execution paths are also not suitable.

Now, let's shift focus to `macb_ptp.c`. I need to dig into that file and see what it does. Its role in the overall picture, and its relation to the hardware, needs to be inspected. So, let me open that up and investigate.

{
  "File": "drivers/net/ethernet/cadence/macb_ptp.c",
  "FirstLine": 1,
  "LineCount": 80
}

{
  "Contents": "   1:\t// SPDX-License-Identifier: GPL-2.0-only\n   2:\t/*\n   3:\t * 1588 PTP support for Cadence GEM device.\n   4:\t *\n   5:\t * Copyright (C) 2017 Cadence Design Systems - https://www.cadence.com\n   6:\t *\n   7:\t * Authors: Rafal Ozieblo \u003crafalo@cadence.com\u003e\n   8:\t *          Bartosz Folta \u003cbfolta@cadence.com\u003e\n   9:\t */\n  10:\t#include \u003clinux/kernel.h\u003e\n  11:\t#include \u003clinux/types.h\u003e\n  12:\t#include \u003clinux/clk.h\u003e\n  13:\t#include \u003clinux/device.h\u003e\n  14:\t#include \u003clinux/etherdevice.h\u003e\n  15:\t#include \u003clinux/platform_device.h\u003e\n  16:\t#include \u003clinux/time64.h\u003e\n  17:\t#include \u003clinux/ptp_classify.h\u003e\n  18:\t#include \u003clinux/if_ether.h\u003e\n  19:\t#include \u003clinux/if_vlan.h\u003e\n  20:\t#include \u003clinux/net_tstamp.h\u003e\n  21:\t#include \u003clinux/circ_buf.h\u003e\n  22:\t#include \u003clinux/spinlock.h\u003e\n  23:\t\n  24:\t#include \"macb.h\"\n  25:\t\n  26:\t#define  GEM_PTP_TIMER_NAME \"gem-ptp-timer\"\n  27:\t\n  28:\tstatic struct macb_dma_desc_ptp *macb_ptp_desc(struct macb *bp,\n  29:\t\t\t\t\t\t       struct macb_dma_desc *desc)\n  30:\t{\n  31:\t\tif (!macb_dma_ptp(bp))\n  32:\t\t\treturn NULL;\n  33:\t\n  34:\t\tif (macb_dma64(bp))\n  35:\t\t\treturn (struct macb_dma_desc_ptp *)\n  36:\t\t\t\t\t((u8 *)desc + sizeof(struct macb_dma_desc)\n  37:\t\t\t\t\t+ sizeof(struct macb_dma_desc_64));\n  38:\t\telse\n  39:\t\t\treturn (struct macb_dma_desc_ptp *)\n  40:\t\t\t\t\t((u8 *)desc + sizeof(struct macb_dma_desc));\n  41:\t}\n  42:\t\n  43:\tstatic int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts,\n  44:\t\t\t\t    struct ptp_system_timestamp *sts)\n  45:\t{\n  46:\t\tstruct macb *bp = container_of(ptp, struct macb, ptp_clock_info);\n  47:\t\tunsigned long flags;\n  48:\t\tlong first, second;\n  49:\t\tu32 secl, sech;\n  50:\t\n  51:\t\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\n  52:\t\tptp_read_system_prets(sts);\n  53:\t\t/* ptp_read_system_prets() uses smp_rmb() internally,\n  54:\t\t * which does not guarantee ordering against MMIO reads.\n  55:\t\t */\n  56:\t\trmb();\n  57:\t\tfirst = gem_readl(bp, TN);\n  58:\t\t/* Ensure the PHC read completes before taking\n  59:\t\t * the post timestamp.\n  60:\t\t */\n  61:\t\trmb();\n  62:\t\tptp_read_system_postts(sts);\n  63:\t\tsecl = gem_readl(bp, TSL);\n  64:\t\tsech = gem_readl(bp, TSH);\n  65:\t\tsecond = gem_readl(bp, TN);\n  66:\t\n  67:\t\t/* test for nsec rollover */\n  68:\t\tif (first \u003e second) {\n  69:\t\t\t/* if so, use later read \u0026 re-read seconds\n  70:\t\t\t * (assume all done within 1s)\n  71:\t\t\t */\n  72:\t\t\tptp_read_system_prets(sts);\n  73:\t\t\t/* ptp_read_system_prets() uses smp_rmb() internally,\n  74:\t\t\t * which does not guarantee ordering against MMIO reads.\n  75:\t\t\t */\n  76:\t\t\trmb();\n  77:\t\t\tts-\u003etv_nsec = gem_readl(bp, TN);\n  78:\t\t\t/* Ensure the PHC read completes before taking\n  79:\t\t\t * the post timestamp.\n  80:\t\t\t */\n"
}

							input: 23364
							output: 38
							thoughts: 76

Here's my thought process, distilled:

**Finding the Source of a PTP Time Callback**

Okay, so `gem_tsu_get_time()`… right, that's a PTP clock callback, specifically the one defined as `ptp_clock_info.gettimex64` within the `macb_ptp.c` module. The function's purpose is clear, but I need to figure out *where* it's being registered, which device or driver is actually using it. I need to trace its usage. I'll search the codebase directly for instances of `gem_tsu_get_time` and see what comes up. That should point me to the relevant initialization or registration code.

{
  "Expression": "gem_tsu_get_time",
  "PathPrefix": "drivers/net/ethernet/cadence/"
}

{
  "Output": "drivers/net/ethernet/cadence/macb_ptp.c=28=static struct macb_dma_desc_ptp *macb_ptp_desc(struct macb *bp,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-42-\ndrivers/net/ethernet/cadence/macb_ptp.c:43:static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts,\ndrivers/net/ethernet/cadence/macb_ptp.c-44-\t\t\t    struct ptp_system_timestamp *sts)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=175=static int gem_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-186-\tif (delta \u003e TSU_NSEC_MAX_VAL) {\ndrivers/net/ethernet/cadence/macb_ptp.c:187:\t\tgem_tsu_get_time(\u0026bp-\u003eptp_clock_info, \u0026now, NULL);\ndrivers/net/ethernet/cadence/macb_ptp.c-188-\t\tnow = timespec64_add(now, then);\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=207=static const struct ptp_clock_info gem_ptp_caps_template = {\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-217-\t.adjtime\t= gem_ptp_adjtime,\ndrivers/net/ethernet/cadence/macb_ptp.c:218:\t.gettimex64\t= gem_tsu_get_time,\ndrivers/net/ethernet/cadence/macb_ptp.c-219-\t.settime64\t= gem_tsu_set_time,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=264=static int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-276-\t */\ndrivers/net/ethernet/cadence/macb_ptp.c:277:\tgem_tsu_get_time(\u0026bp-\u003eptp_clock_info, \u0026tsu, NULL);\ndrivers/net/ethernet/cadence/macb_ptp.c-278-\n"
}

							input: 24295
							output: 140
							thoughts: 913

**Fuzzing Verdict: Structurally Unreachable Code**

Okay, let's break this down. First, I need to figure out if the Cadence MACB device, specifically the `macb_ptp.c` driver, is even accessible in a standard QEMU x86_64 fuzzing environment. The initial check reveals that standard QEMU primarily emulates a set of network devices, but none of them are Cadence GEM. We're talking about e1000, virtio, rtl8139, and similar common NICs – nothing that involves a Cadence GEM controller, especially not on a PCI bus within the x86_64 architecture.

My QEMU source dive confirmed this. The `cadence_gem.c` driver *does* exist, but it's instantiated as a sysbus device, and specifically within the context of ARM SoCs like the Xilinx Zynq and Versal platforms. QEMU's x86_64 PC/Q35 emulation doesn't probe or instantiate this device.

Alright, what about clever tricks with virtual buses or syzkaller? Can syzkaller somehow force the device to come into existence, either as a platform device or a PCI device? I'm familiar with those capabilities, but in this case, the answer is a firm no. Syzkaller relies on the standard QEMU environment, and it's not going to conjure up physical or specialized Cadence hardware. Furthermore, looking at the syzkaller documentation, this situation falls squarely into the "Structurally unreachable hardware" category.

Let's nail down this point. The core function in question is `gem_tsu_get_time`. This function is only called if the Cadence GEM device is successfully probed and initialized – a process that involves the `gem_ptp_init` function, creating a PTP clock for the network interface. Without that hardware probe, `gem_tsu_get_time` *cannot* be executed. We're chasing ghosts here.

So, let's clarify the patch's purpose. It's adding `rmb()` barriers before and after `gem_readl(bp, TN)` within `gem_tsu_get_time`. These barriers are meant to enforce memory ordering for MMIO register reads, synchronizing them with system timestamps as part of the PTP (Precision Time Protocol) functionality. So, it's about hardware memory-barrier ordering for MMIO reads, but for specific Cadence GEM hardware.

Therefore, this patch directly modifies the code for the Cadence MACB/GEM Ethernet controller, which is vendor-specific hardware, and is absent from standard x86_64 (amd64) environments. It can't be reached because of the architecture of the simulated machine.

Here's the finalized output format:

* `WorthFuzzing`: false
* `FocusSymbols`: \[ ]
* `EnableConfigs`: \[ ]
* `Reasoning`: The patch modifies driver code for the Cadence MACB/GEM Ethernet controller (`drivers/net/ethernet/cadence/macb_ptp.c`). This hardware is not present or emulated in standard x86_64 (amd64) fuzzing environments, making the modified code structurally unreachable and not warranting fuzzing.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch adds MMIO read memory barriers (rmb) in gem_tsu_get_time() within the Cadence MACB/GEM Ethernet driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver requires vendor-specific Cadence MACB/GEM hardware (primarily found on Atmel/Xilinx SoCs) that is not available or emulated in standard amd64 virtualized fuzzing environments (QEMU/GCE), making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch adds MMIO read memory barriers (rmb) in gem_tsu_get_time() within the Cadence MACB/GEM Ethernet driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver requires vendor-specific Cadence MACB/GEM hardware (primarily found on Atmel/Xilinx SoCs) that is not available or emulated in standard amd64 virtualized fuzzing environments (QEMU/GCE), making the modified code structurally unreachable.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

LLM Calls Summary:
Total Calls	Total Tokens	Avg Tokens	Total Duration (Seconds)	Avg Duration (Seconds)

Tool Calls Summary:
Total Calls	Total Duration (Seconds)	Avg Duration (Seconds)