AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/08/14 12:06	flow	patch-triage	1m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The patch modifies the Airoha NPU driver, which is a hardware-specific SoC driver for Airoha EN7581/AN7583 routers. This driver requires physical hardware that is not emulated in standard QEMU environments, making the code paths impossible to reach and test during fuzzing.", "WorthFuzzing": false }
1/1	2026/08/14 12:06	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit 481cb8faffd51e9feb916f0ca2663fdca11d7924\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Fri Aug 14 12:06:43 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c\nindex b679bed952de3..2ba78bf0e97b4 100644\n--- a/drivers/net/ethernet/airoha/airoha_npu.c\n+++ b/drivers/net/ethernet/airoha/airoha_npu.c\n@@ -5,6 +5,7 @@\n /\n \n #include \u003clinux/devcoredump.h\u003e\n+#include \u003clinux/dma-mapping.h\u003e\n #include \u003clinux/firmware.h\u003e\n #include \u003clinux/platform_device.h\u003e\n #include \u003clinux/of_net.h\u003e\n@@ -23,6 +24,8 @@\n #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE\t0x200000\n #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE\t0x10000\n #define NPU_DUMP_SIZE\t\t\t\t512\n+/ Maximum mailbox DMA payload (PPE ~28 bytes, WLAN TLV up to 24). /\n+#define AIROHA_NPU_MBOX_SIZE\t\t\t256\n \n #define REG_NPU_LOCAL_SRAM\t\t0x0\n \n@@ -160,23 +163,33 @@ struct wlan_mbox_data {\n \tDECLARE_FLEX_ARRAY(u8, d);\n };\n \n-static int airoha_npu_send_msg(struct airoha_npu npu, int func_id,\n-\t\t\t void p, int size)\n+static int __airoha_npu_send_msg(struct airoha_npu npu, int func_id,\n+\t\t\t\t const void data, int len, void reply,\n+\t\t\t\t u16 reply_len)\n {\n-\tu16 core = 0; /* FIXME /\n-\tu32 val, offset = core \u003c\u003c 4;\n+\tstruct airoha_npu_core core = \u0026npu-\u003ecores[0]; /* FIXME: core /\n \tdma_addr_t dma_addr;\n+\tunsigned int map_len = ALIGN(len, SMP_CACHE_BYTES);\n+\tu32 val, offset = 0;\n \tint ret;\n \n-\tdma_addr = dma_map_single(npu-\u003edev, p, size, DMA_BIDIRECTIONAL);\n+\tif (len \u003c= 0 \|\| len \u003e AIROHA_NPU_MBOX_SIZE)\n+\t\treturn -EINVAL;\n+\n+\tif (reply \u0026\u0026 reply_len \u003e len)\n+\t\treturn -EINVAL;\n+\n+\tspin_lock_bh(\u0026core-\u003elock);\n+\n+\tmemcpy(core-\u003ebuf, data, len);\n+\n+\tdma_addr = dma_map_single(npu-\u003edev, core-\u003ebuf, map_len, DMA_BIDIRECTIONAL);\n \tret = dma_mapping_error(npu-\u003edev, dma_addr);\n \tif (ret)\n-\t\treturn ret;\n-\n-\tspin_lock_bh(\u0026npu-\u003ecores[core].lock);\n+\t\tgoto unlock;\n \n \tregmap_write(npu-\u003eregmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr);\n-\tregmap_write(npu-\u003eregmap, REG_CR_MBQ0_CTRL(1) + offset, size);\n+\tregmap_write(npu-\u003eregmap, REG_CR_MBQ0_CTRL(1) + offset, len);\n \tregmap_read(npu-\u003eregmap, REG_CR_MBQ0_CTRL(2) + offset, \u0026val);\n \tregmap_write(npu-\u003eregmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1);\n \tval = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) \| MBOX_MSG_WAIT_RSP;\n@@ -189,13 +202,23 @@ static int airoha_npu_send_msg(struct airoha_npu npu, int func_id,\n \tif (!ret \u0026\u0026 FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS)\n \t\tret = -EINVAL;\n \n-\tspin_unlock_bh(\u0026npu-\u003ecores[core].lock);\n+\tdma_unmap_single(npu-\u003edev, dma_addr, map_len, DMA_BIDIRECTIONAL);\n \n-\tdma_unmap_single(npu-\u003edev, dma_addr, size, DMA_BIDIRECTIONAL);\n+\t/* Copy the trailing reply_len bytes of the response. /\n+\tif (!ret \u0026\u0026 reply)\n+\t\tmemcpy(reply, core-\u003ebuf + len - reply_len, reply_len);\n+unlock:\n+\tspin_unlock_bh(\u0026core-\u003elock);\n \n \treturn ret;\n }\n \n+static int airoha_npu_send_msg(struct airoha_npu npu, int func_id,\n+\t\t\t void data, int len)\n+{\n+\treturn __airoha_npu_send_msg(npu, func_id, data, len, data, len);\n+}\n+\n static int airoha_npu_load_firmware(struct device dev, void __iomem addr,\n \t\t\t\t const char fw_name, int fw_max_size)\n {\n@@ -497,9 +520,8 @@ static int airoha_npu_wlan_msg_get(struct airoha_npu npu, int ifindex,\n \twlan_data-\u003efunc_type = NPU_OP_GET;\n \twlan_data-\u003efunc_id = func_id;\n \n-\terr = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);\n-\tif (!err)\n-\t\tmemcpy(data, wlan_data-\u003ed, data_len);\n+\terr = __airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len,\n+\t\t\t\t data, data_len);\n \tkfree(wlan_data);\n \n \treturn err;\n@@ -770,6 +792,18 @@ static int airoha_npu_probe(struct platform_device pdev)\n \tif (err)\n \t\treturn err;\n \n+\tfor (i = 0; i \u003c ARRAY_SIZE(npu-\u003ecores); i++) {\n+\t\tstruct airoha_npu_core core = \u0026npu-\u003ecores[i];\n+\t\tvoid raw;\n+\n+\t\traw = devm_kmalloc(dev, AIROHA_NPU_MBOX_SIZE + SMP_CACHE_BYTES,\n+\t\t\t\t GFP_KERNEL);\n+\t\tif (!raw)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tcore-\u003ebuf = PTR_ALIGN(raw, SMP_CACHE_BYTES);\n+\t}\n+\n \terr = airoha_npu_run_firmware(dev, base, \u0026res);\n \tif (err)\n \t\treturn dev_err_probe(dev, err, \"failed to run npu firmware\\n\");\ndiff --git a/include/linux/soc/airoha/airoha_offload.h b/include/linux/soc/airoha/airoha_offload.h\nindex 7589fccfeef6d..f635766e3dba2 100644\n--- a/include/linux/soc/airoha/airoha_offload.h\n+++ b/include/linux/soc/airoha/airoha_offload.h\n@@ -173,6 +173,7 @@ struct airoha_npu {\n \t\t/* protect concurrent npu memory accesses /\n \t\tspinlock_t lock;\n \t\tstruct work_struct wdt_work;\n+\t\tvoid buf; /* mailbox DMA bounce buffer */\n \t} cores[NPU_NUM_CORES];\n \n \tint irqs[NPU_NUM_IRQ];\n" }
2/1	2026/08/14 12:06	agent	patch-evaluator	1m Model: best-expensive Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch modifies the Airoha NPU driver, which is a hardware-specific SoC driver for Airoha EN7581/AN7583 routers. This driver requires physical hardware that is not emulated in standard QEMU environments, making the code paths impossible to reach and test during fuzzing.", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). - Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU. - Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove) that are executed only during PCI hot-unplug or sysfs driver unbind operations. If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. Prefer non-static, non-inlined API entrypoint functions over internal static helper functions (which are inlined by the compiler and do not have distinct symbol addresses). 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes: commit 481cb8faffd51e9feb916f0ca2663fdca11d7924 Author: syz-cluster <triage@syzkaller.com> Date: Fri Aug 14 12:06:43 2026 +0000 syz-cluster: applied patch under review diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c index b679bed952de3..2ba78bf0e97b4 100644 --- a/drivers/net/ethernet/airoha/airoha_npu.c +++ b/drivers/net/ethernet/airoha/airoha_npu.c @@ -5,6 +5,7 @@ / #include <linux/devcoredump.h> +#include <linux/dma-mapping.h> #include <linux/firmware.h> #include <linux/platform_device.h> #include <linux/of_net.h> @@ -23,6 +24,8 @@ #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE 0x200000 #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE 0x10000 #define NPU_DUMP_SIZE 512 +/ Maximum mailbox DMA payload (PPE ~28 bytes, WLAN TLV up to 24). / +#define AIROHA_NPU_MBOX_SIZE 256 #define REG_NPU_LOCAL_SRAM 0x0 @@ -160,23 +163,33 @@ struct wlan_mbox_data { DECLARE_FLEX_ARRAY(u8, d); }; -static int airoha_npu_send_msg(struct airoha_npu npu, int func_id, - void p, int size) +static int __airoha_npu_send_msg(struct airoha_npu npu, int func_id, + const void data, int len, void reply, + u16 reply_len) { - u16 core = 0; /* FIXME / - u32 val, offset = core << 4; + struct airoha_npu_core core = &npu->cores[0]; /* FIXME: core / dma_addr_t dma_addr; + unsigned int map_len = ALIGN(len, SMP_CACHE_BYTES); + u32 val, offset = 0; int ret; - dma_addr = dma_map_single(npu->dev, p, size, DMA_BIDIRECTIONAL); + if (len <= 0 \|\| len > AIROHA_NPU_MBOX_SIZE) + return -EINVAL; + + if (reply && reply_len > len) + return -EINVAL; + + spin_lock_bh(&core->lock); + + memcpy(core->buf, data, len); + + dma_addr = dma_map_single(npu->dev, core->buf, map_len, DMA_BIDIRECTIONAL); ret = dma_mapping_error(npu->dev, dma_addr); if (ret) - return ret; - - spin_lock_bh(&npu->cores[core].lock); + goto unlock; regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr); - regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, size); + regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, len); regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val); regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1); val = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) \| MBOX_MSG_WAIT_RSP; @@ -189,13 +202,23 @@ static int airoha_npu_send_msg(struct airoha_npu npu, int func_id, if (!ret && FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS) ret = -EINVAL; - spin_unlock_bh(&npu->cores[core].lock); + dma_unmap_single(npu->dev, dma_addr, map_len, DMA_BIDIRECTIONAL); - dma_unmap_single(npu->dev, dma_addr, size, DMA_BIDIRECTIONAL); + /* Copy the trailing reply_len bytes of the response. / + if (!ret && reply) + memcpy(reply, core->buf + len - reply_len, reply_len); +unlock: + spin_unlock_bh(&core->lock); return ret; } +static int airoha_npu_send_msg(struct airoha_npu npu, int func_id, + void data, int len) +{ + return __airoha_npu_send_msg(npu, func_id, data, len, data, len); +} + static int airoha_npu_load_firmware(struct device dev, void __iomem addr, const char fw_name, int fw_max_size) { @@ -497,9 +520,8 @@ static int airoha_npu_wlan_msg_get(struct airoha_npu npu, int ifindex, wlan_data->func_type = NPU_OP_GET; wlan_data->func_id = func_id; - err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len); - if (!err) - memcpy(data, wlan_data->d, data_len); + err = __airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len, + data, data_len); kfree(wlan_data); return err; @@ -770,6 +792,18 @@ static int airoha_npu_probe(struct platform_device pdev) if (err) return err; + for (i = 0; i < ARRAY_SIZE(npu->cores); i++) { + struct airoha_npu_core core = &npu->cores[i]; + void raw; + + raw = devm_kmalloc(dev, AIROHA_NPU_MBOX_SIZE + SMP_CACHE_BYTES, + GFP_KERNEL); + if (!raw) + return -ENOMEM; + + core->buf = PTR_ALIGN(raw, SMP_CACHE_BYTES); + } + err = airoha_npu_run_firmware(dev, base, &res); if (err) return dev_err_probe(dev, err, "failed to run npu firmware\n"); diff --git a/include/linux/soc/airoha/airoha_offload.h b/include/linux/soc/airoha/airoha_offload.h index 7589fccfeef6d..f635766e3dba2 100644 --- a/include/linux/soc/airoha/airoha_offload.h +++ b/include/linux/soc/airoha/airoha_offload.h @@ -173,6 +173,7 @@ struct airoha_npu { /* protect concurrent npu memory accesses / spinlock_t lock; struct work_struct wdt_work; + void buf; /* mailbox DMA bounce buffer */ } cores[NPU_NUM_CORES]; int irqs[NPU_NUM_IRQ];
3/2	2026/08/14 12:06	llm	patch-evaluator	0m Model: gemini-3.1-pro-preview Args: null Results: null Tokens: input: 3811 output: 35 thoughts: 294 Thoughts: Analyzing a Patch: Airoha NPU Driver Okay, so I'm looking at this patch that's touching `drivers/net/ethernet/airoha/airoha_npu.c` and `include/linux/soc/airoha/airoha_offload.h`. It seems to be modifying how messages are sent to the NPU on Airoha SoCs. The key change is the introduction of a DMA bounce buffer (`core->buf`) and renaming `airoha_npu_send_msg` to `__airoha_npu_send_msg` to use it. The intent here is clearly to resolve potential DMA mapping problems, which makes sense; dealing with stack memory or unaligned memory in DMA operations is always a pain. But hold on, there's a specific question I need to answer. The prompt says I need to set `WorthFuzzing=false` if the patch concerns a vendor-specific driver that requires physical hardware that's not emulated in QEMU. That's a critical point. Is this Airoha NPU driver one of those? I need to quickly assess if `airoha_npu` fits this criteria. I know it's under `drivers/net/ethernet/airoha/`, so at least it's a network driver and vendor-specific to Airoha. But is the hardware dependent on a PCIe device, or something else that QEMU might not handle? Time to do a quick search within the kernel tree to get a broader understanding of this `airoha_npu`. I need to figure out if this driver is tied to a specific physical hardware implementation or if it's potentially emulatable.
4/2	2026/08/14 12:06	tool	grepper	0m Args: { "Expression": "airoha_npu", "PathPrefix": "drivers/net/ethernet/airoha/" } Results: { "Output": "drivers/net/ethernet/airoha/Makefile=8=airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/ethernet/airoha/airoha_eth.h=645=struct airoha_eth {\n--\ndrivers/net/ethernet/airoha/airoha_eth.h-652-\ndrivers/net/ethernet/airoha/airoha_eth.h:653:\tstruct airoha_npu __rcu npu;\ndrivers/net/ethernet/airoha/airoha_eth.h-654-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=108=enum {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-112-\ndrivers/net/ethernet/airoha/airoha_npu.c:113:struct airoha_npu_fw {\ndrivers/net/ethernet/airoha/airoha_npu.c-114-\tconst char name;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-117-\ndrivers/net/ethernet/airoha/airoha_npu.c:118:struct airoha_npu_soc_data {\ndrivers/net/ethernet/airoha/airoha_npu.c:119:\tstruct airoha_npu_fw fw_rv32;\ndrivers/net/ethernet/airoha/airoha_npu.c:120:\tstruct airoha_npu_fw fw_data;\ndrivers/net/ethernet/airoha/airoha_npu.c-121-};\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=159=struct wlan_mbox_data {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-165-\ndrivers/net/ethernet/airoha/airoha_npu.c:166:static int __airoha_npu_send_msg(struct airoha_npu npu, int func_id,\ndrivers/net/ethernet/airoha/airoha_npu.c-167-\t\t\t\t const void data, int len, void reply,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-169-{\ndrivers/net/ethernet/airoha/airoha_npu.c:170:\tstruct airoha_npu_core core = \u0026npu-\u003ecores[0]; /* FIXME: core /\ndrivers/net/ethernet/airoha/airoha_npu.c-171-\tdma_addr_t dma_addr;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-215-\ndrivers/net/ethernet/airoha/airoha_npu.c:216:static int airoha_npu_send_msg(struct airoha_npu npu, int func_id,\ndrivers/net/ethernet/airoha/airoha_npu.c-217-\t\t\t void data, int len)\ndrivers/net/ethernet/airoha/airoha_npu.c-218-{\ndrivers/net/ethernet/airoha/airoha_npu.c:219:\treturn __airoha_npu_send_msg(npu, func_id, data, len, data, len);\ndrivers/net/ethernet/airoha/airoha_npu.c-220-}\ndrivers/net/ethernet/airoha/airoha_npu.c-221-\ndrivers/net/ethernet/airoha/airoha_npu.c:222:static int airoha_npu_load_firmware(struct device dev, void __iomem addr,\ndrivers/net/ethernet/airoha/airoha_npu.c-223-\t\t\t\t const char fw_name, int fw_max_size)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=246=static int\ndrivers/net/ethernet/airoha/airoha_npu.c:247:airoha_npu_load_firmware_from_dts(struct device dev, void __iomem addr,\ndrivers/net/ethernet/airoha/airoha_npu.c-248-\t\t\t\t void __iomem base)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-257-\ndrivers/net/ethernet/airoha/airoha_npu.c:258:\tret = airoha_npu_load_firmware(dev, addr, fw_names[0],\ndrivers/net/ethernet/airoha/airoha_npu.c-259-\t\t\t\t NPU_EN7581_FIRMWARE_RV32_MAX_SIZE);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-262-\ndrivers/net/ethernet/airoha/airoha_npu.c:263:\treturn airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM,\ndrivers/net/ethernet/airoha/airoha_npu.c-264-\t\t\t\t\tfw_names[1],\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-267-\ndrivers/net/ethernet/airoha/airoha_npu.c:268:static int airoha_npu_run_firmware(struct device dev, void __iomem base,\ndrivers/net/ethernet/airoha/airoha_npu.c-269-\t\t\t\t struct resource res)\ndrivers/net/ethernet/airoha/airoha_npu.c-270-{\ndrivers/net/ethernet/airoha/airoha_npu.c:271:\tconst struct airoha_npu_soc_data soc;\ndrivers/net/ethernet/airoha/airoha_npu.c-272-\tvoid __iomem addr;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-286-\tif (of_find_property(dev-\u003eof_node, \"firmware-name\", NULL))\ndrivers/net/ethernet/airoha/airoha_npu.c:287:\t\treturn airoha_npu_load_firmware_from_dts(dev, addr, base);\ndrivers/net/ethernet/airoha/airoha_npu.c-288-\ndrivers/net/ethernet/airoha/airoha_npu.c-289-\t/* Load rv32 npu firmware /\ndrivers/net/ethernet/airoha/airoha_npu.c:290:\tret = airoha_npu_load_firmware(dev, addr, soc-\u003efw_rv32.name,\ndrivers/net/ethernet/airoha/airoha_npu.c-291-\t\t\t\t soc-\u003efw_rv32.max_size);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-295-\t/ Load data npu firmware /\ndrivers/net/ethernet/airoha/airoha_npu.c:296:\treturn airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM,\ndrivers/net/ethernet/airoha/airoha_npu.c-297-\t\t\t\t\tsoc-\u003efw_data.name,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-300-\ndrivers/net/ethernet/airoha/airoha_npu.c:301:static irqreturn_t airoha_npu_mbox_handler(int irq, void npu_instance)\ndrivers/net/ethernet/airoha/airoha_npu.c-302-{\ndrivers/net/ethernet/airoha/airoha_npu.c:303:\tstruct airoha_npu npu = npu_instance;\ndrivers/net/ethernet/airoha/airoha_npu.c-304-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-315-\ndrivers/net/ethernet/airoha/airoha_npu.c:316:static void airoha_npu_wdt_work(struct work_struct work)\ndrivers/net/ethernet/airoha/airoha_npu.c-317-{\ndrivers/net/ethernet/airoha/airoha_npu.c:318:\tstruct airoha_npu_core core;\ndrivers/net/ethernet/airoha/airoha_npu.c:319:\tstruct airoha_npu npu;\ndrivers/net/ethernet/airoha/airoha_npu.c-320-\tvoid dump;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-323-\ndrivers/net/ethernet/airoha/airoha_npu.c:324:\tcore = container_of(work, struct airoha_npu_core, wdt_work);\ndrivers/net/ethernet/airoha/airoha_npu.c-325-\tnpu = core-\u003enpu;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-338-\ndrivers/net/ethernet/airoha/airoha_npu.c:339:static irqreturn_t airoha_npu_wdt_handler(int irq, void core_instance)\ndrivers/net/ethernet/airoha/airoha_npu.c-340-{\ndrivers/net/ethernet/airoha/airoha_npu.c:341:\tstruct airoha_npu_core core = core_instance;\ndrivers/net/ethernet/airoha/airoha_npu.c:342:\tstruct airoha_npu npu = core-\u003enpu;\ndrivers/net/ethernet/airoha/airoha_npu.c-343-\tint c = core - \u0026npu-\u003ecores[0];\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-353-\ndrivers/net/ethernet/airoha/airoha_npu.c:354:static int airoha_npu_ppe_init(struct airoha_npu npu)\ndrivers/net/ethernet/airoha/airoha_npu.c-355-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-367-\ndrivers/net/ethernet/airoha/airoha_npu.c:368:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-369-\t\t\t\t sizeof(ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-374-\ndrivers/net/ethernet/airoha/airoha_npu.c:375:static int airoha_npu_ppe_deinit(struct airoha_npu npu)\ndrivers/net/ethernet/airoha/airoha_npu.c-376-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-386-\ndrivers/net/ethernet/airoha/airoha_npu.c:387:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-388-\t\t\t\t sizeof(ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-393-\ndrivers/net/ethernet/airoha/airoha_npu.c:394:static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu npu,\ndrivers/net/ethernet/airoha/airoha_npu.c-395-\t\t\t\t\t dma_addr_t foe_addr,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-410-\ndrivers/net/ethernet/airoha/airoha_npu.c:411:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-412-\t\t\t\t sizeof(ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-417-\ndrivers/net/ethernet/airoha/airoha_npu.c:418:static int airoha_npu_foe_commit_entry(struct airoha_npu npu,\ndrivers/net/ethernet/airoha/airoha_npu.c-419-\t\t\t\t dma_addr_t foe_addr,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-435-\ndrivers/net/ethernet/airoha/airoha_npu.c:436:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-437-\t\t\t\t sizeof(ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-444-\ndrivers/net/ethernet/airoha/airoha_npu.c:445:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-446-\t\t\t\t sizeof(ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-452-\ndrivers/net/ethernet/airoha/airoha_npu.c:453:static int airoha_npu_ppe_stats_setup(struct airoha_npu npu,\ndrivers/net/ethernet/airoha/airoha_npu.c-454-\t\t\t\t dma_addr_t foe_stats_addr,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-467-\ndrivers/net/ethernet/airoha/airoha_npu.c:468:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-469-\t\t\t\t sizeof(ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-483-\ndrivers/net/ethernet/airoha/airoha_npu.c:484:static int airoha_npu_wlan_msg_send(struct airoha_npu npu, int ifindex,\ndrivers/net/ethernet/airoha/airoha_npu.c:485:\t\t\t\t enum airoha_npu_wlan_set_cmd func_id,\ndrivers/net/ethernet/airoha/airoha_npu.c-486-\t\t\t\t void data, int data_len, gfp_t gfp)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-500-\ndrivers/net/ethernet/airoha/airoha_npu.c:501:\terr = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);\ndrivers/net/ethernet/airoha/airoha_npu.c-502-\tkfree(wlan_data);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-506-\ndrivers/net/ethernet/airoha/airoha_npu.c:507:static int airoha_npu_wlan_msg_get(struct airoha_npu npu, int ifindex,\ndrivers/net/ethernet/airoha/airoha_npu.c:508:\t\t\t\t enum airoha_npu_wlan_get_cmd func_id,\ndrivers/net/ethernet/airoha/airoha_npu.c-509-\t\t\t\t void data, int data_len, gfp_t gfp)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-522-\ndrivers/net/ethernet/airoha/airoha_npu.c:523:\terr = __airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len,\ndrivers/net/ethernet/airoha/airoha_npu.c-524-\t\t\t\t data, data_len);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=530=static int\ndrivers/net/ethernet/airoha/airoha_npu.c:531:airoha_npu_wlan_set_reserved_memory(struct airoha_npu npu,\ndrivers/net/ethernet/airoha/airoha_npu.c-532-\t\t\t\t int ifindex, const char name,\ndrivers/net/ethernet/airoha/airoha_npu.c:533:\t\t\t\t enum airoha_npu_wlan_set_cmd func_id)\ndrivers/net/ethernet/airoha/airoha_npu.c-534-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-545-\tval = res.start;\ndrivers/net/ethernet/airoha/airoha_npu.c:546:\treturn airoha_npu_wlan_msg_send(npu, ifindex, func_id, \u0026val,\ndrivers/net/ethernet/airoha/airoha_npu.c-547-\t\t\t\t\tsizeof(val), GFP_KERNEL);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-549-\ndrivers/net/ethernet/airoha/airoha_npu.c:550:static int airoha_npu_wlan_init_memory(struct airoha_npu npu)\ndrivers/net/ethernet/airoha/airoha_npu.c-551-{\ndrivers/net/ethernet/airoha/airoha_npu.c:552:\tenum airoha_npu_wlan_set_cmd cmd = WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU;\ndrivers/net/ethernet/airoha/airoha_npu.c-553-\tu32 val = 0;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-555-\ndrivers/net/ethernet/airoha/airoha_npu.c:556:\terr = airoha_npu_wlan_msg_send(npu, 1, cmd, \u0026val, sizeof(val),\ndrivers/net/ethernet/airoha/airoha_npu.c-557-\t\t\t\t GFP_KERNEL);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-561-\tcmd = WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR;\ndrivers/net/ethernet/airoha/airoha_npu.c:562:\terr = airoha_npu_wlan_set_reserved_memory(npu, 0, \"tx-bufid\", cmd);\ndrivers/net/ethernet/airoha/airoha_npu.c-563-\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-566-\tcmd = WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR;\ndrivers/net/ethernet/airoha/airoha_npu.c:567:\terr = airoha_npu_wlan_set_reserved_memory(npu, 0, \"pkt\", cmd);\ndrivers/net/ethernet/airoha/airoha_npu.c-568-\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-571-\tcmd = WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR;\ndrivers/net/ethernet/airoha/airoha_npu.c:572:\terr = airoha_npu_wlan_set_reserved_memory(npu, 0, \"tx-pkt\", cmd);\ndrivers/net/ethernet/airoha/airoha_npu.c-573-\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-578-\t\tcmd = WLAN_FUNC_SET_WAIT_DRAM_BA_NODE_ADDR;\ndrivers/net/ethernet/airoha/airoha_npu.c:579:\t\terr = airoha_npu_wlan_set_reserved_memory(npu, 0, \"ba\", cmd);\ndrivers/net/ethernet/airoha/airoha_npu.c-580-\t\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-584-\tcmd = WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU;\ndrivers/net/ethernet/airoha/airoha_npu.c:585:\treturn airoha_npu_wlan_msg_send(npu, 0, cmd, \u0026val, sizeof(val),\ndrivers/net/ethernet/airoha/airoha_npu.c-586-\t\t\t\t\tGFP_KERNEL);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-588-\ndrivers/net/ethernet/airoha/airoha_npu.c:589:static u32 airoha_npu_wlan_queue_addr_get(struct airoha_npu npu, int qid,\ndrivers/net/ethernet/airoha/airoha_npu.c-590-\t\t\t\t\t bool xmit)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-597-\ndrivers/net/ethernet/airoha/airoha_npu.c:598:static void airoha_npu_wlan_irq_status_set(struct airoha_npu npu, u32 val)\ndrivers/net/ethernet/airoha/airoha_npu.c-599-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-602-\ndrivers/net/ethernet/airoha/airoha_npu.c:603:static u32 airoha_npu_wlan_irq_status_get(struct airoha_npu npu, int q)\ndrivers/net/ethernet/airoha/airoha_npu.c-604-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-610-\ndrivers/net/ethernet/airoha/airoha_npu.c:611:static void airoha_npu_wlan_irq_enable(struct airoha_npu npu, int q)\ndrivers/net/ethernet/airoha/airoha_npu.c-612-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-615-\ndrivers/net/ethernet/airoha/airoha_npu.c:616:static void airoha_npu_wlan_irq_disable(struct airoha_npu npu, int q)\ndrivers/net/ethernet/airoha/airoha_npu.c-617-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-620-\ndrivers/net/ethernet/airoha/airoha_npu.c:621:struct airoha_npu airoha_npu_get(struct device dev)\ndrivers/net/ethernet/airoha/airoha_npu.c-622-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-624-\tstruct device_node np;\ndrivers/net/ethernet/airoha/airoha_npu.c:625:\tstruct airoha_npu npu;\ndrivers/net/ethernet/airoha/airoha_npu.c-626-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-668-}\ndrivers/net/ethernet/airoha/airoha_npu.c:669:EXPORT_SYMBOL_GPL(airoha_npu_get);\ndrivers/net/ethernet/airoha/airoha_npu.c-670-\ndrivers/net/ethernet/airoha/airoha_npu.c:671:void airoha_npu_put(struct airoha_npu npu)\ndrivers/net/ethernet/airoha/airoha_npu.c-672-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-675-}\ndrivers/net/ethernet/airoha/airoha_npu.c:676:EXPORT_SYMBOL_GPL(airoha_npu_put);\ndrivers/net/ethernet/airoha/airoha_npu.c-677-\ndrivers/net/ethernet/airoha/airoha_npu.c:678:static const struct airoha_npu_soc_data en7581_npu_soc_data = {\ndrivers/net/ethernet/airoha/airoha_npu.c-679-\t.fw_rv32 = {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-688-\ndrivers/net/ethernet/airoha/airoha_npu.c:689:static const struct airoha_npu_soc_data an7583_npu_soc_data = {\ndrivers/net/ethernet/airoha/airoha_npu.c-690-\t.fw_rv32 = {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-699-\ndrivers/net/ethernet/airoha/airoha_npu.c:700:static const struct of_device_id of_airoha_npu_match[] = {\ndrivers/net/ethernet/airoha/airoha_npu.c-701-\t{ .compatible = \"airoha,en7581-npu\", .data = \u0026en7581_npu_soc_data },\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-704-};\ndrivers/net/ethernet/airoha/airoha_npu.c:705:MODULE_DEVICE_TABLE(of, of_airoha_npu_match);\ndrivers/net/ethernet/airoha/airoha_npu.c-706-\ndrivers/net/ethernet/airoha/airoha_npu.c=707=static const struct regmap_config regmap_config = {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-714-\ndrivers/net/ethernet/airoha/airoha_npu.c:715:static int airoha_npu_probe(struct platform_device pdev)\ndrivers/net/ethernet/airoha/airoha_npu.c-716-{\ndrivers/net/ethernet/airoha/airoha_npu.c-717-\tstruct device dev = \u0026pdev-\u003edev;\ndrivers/net/ethernet/airoha/airoha_npu.c:718:\tstruct airoha_npu npu;\ndrivers/net/ethernet/airoha/airoha_npu.c-719-\tstruct resource res;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-732-\tnpu-\u003edev = dev;\ndrivers/net/ethernet/airoha/airoha_npu.c:733:\tnpu-\u003eops.ppe_init = airoha_npu_ppe_init;\ndrivers/net/ethernet/airoha/airoha_npu.c:734:\tnpu-\u003eops.ppe_deinit = airoha_npu_ppe_deinit;\ndrivers/net/ethernet/airoha/airoha_npu.c:735:\tnpu-\u003eops.ppe_init_stats = airoha_npu_ppe_stats_setup;\ndrivers/net/ethernet/airoha/airoha_npu.c:736:\tnpu-\u003eops.ppe_flush_sram_entries = airoha_npu_ppe_flush_sram_entries;\ndrivers/net/ethernet/airoha/airoha_npu.c:737:\tnpu-\u003eops.ppe_foe_commit_entry = airoha_npu_foe_commit_entry;\ndrivers/net/ethernet/airoha/airoha_npu.c:738:\tnpu-\u003eops.wlan_init_reserved_memory = airoha_npu_wlan_init_memory;\ndrivers/net/ethernet/airoha/airoha_npu.c:739:\tnpu-\u003eops.wlan_send_msg = airoha_npu_wlan_msg_send;\ndrivers/net/ethernet/airoha/airoha_npu.c:740:\tnpu-\u003eops.wlan_get_msg = airoha_npu_wlan_msg_get;\ndrivers/net/ethernet/airoha/airoha_npu.c:741:\tnpu-\u003eops.wlan_get_queue_addr = airoha_npu_wlan_queue_addr_get;\ndrivers/net/ethernet/airoha/airoha_npu.c:742:\tnpu-\u003eops.wlan_set_irq_status = airoha_npu_wlan_irq_status_set;\ndrivers/net/ethernet/airoha/airoha_npu.c:743:\tnpu-\u003eops.wlan_get_irq_status = airoha_npu_wlan_irq_status_get;\ndrivers/net/ethernet/airoha/airoha_npu.c:744:\tnpu-\u003eops.wlan_enable_irq = airoha_npu_wlan_irq_enable;\ndrivers/net/ethernet/airoha/airoha_npu.c:745:\tnpu-\u003eops.wlan_disable_irq = airoha_npu_wlan_irq_disable;\ndrivers/net/ethernet/airoha/airoha_npu.c-746-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-758-\ndrivers/net/ethernet/airoha/airoha_npu.c:759:\terr = devm_request_irq(dev, irq, airoha_npu_mbox_handler,\ndrivers/net/ethernet/airoha/airoha_npu.c-760-\t\t\t IRQF_SHARED, \"airoha-npu-mbox\", npu);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-764-\tfor (i = 0; i \u003c ARRAY_SIZE(npu-\u003ecores); i++) {\ndrivers/net/ethernet/airoha/airoha_npu.c:765:\t\tstruct airoha_npu_core core = \u0026npu-\u003ecores[i];\ndrivers/net/ethernet/airoha/airoha_npu.c-766-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-773-\ndrivers/net/ethernet/airoha/airoha_npu.c:774:\t\terr = devm_request_irq(dev, irq, airoha_npu_wdt_handler,\ndrivers/net/ethernet/airoha/airoha_npu.c-775-\t\t\t\t IRQF_SHARED, \"airoha-npu-wdt\", core);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-778-\ndrivers/net/ethernet/airoha/airoha_npu.c:779:\t\tINIT_WORK(\u0026core-\u003ewdt_work, airoha_npu_wdt_work);\ndrivers/net/ethernet/airoha/airoha_npu.c-780-\t}\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-795-\tfor (i = 0; i \u003c ARRAY_SIZE(npu-\u003ecores); i++) {\ndrivers/net/ethernet/airoha/airoha_npu.c:796:\t\tstruct airoha_npu_core core = \u0026npu-\u003ecores[i];\ndrivers/net/ethernet/airoha/airoha_npu.c-797-\t\tvoid raw;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-806-\ndrivers/net/ethernet/airoha/airoha_npu.c:807:\terr = airoha_npu_run_firmware(dev, base, \u0026res);\ndrivers/net/ethernet/airoha/airoha_npu.c-808-\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-827-\ndrivers/net/ethernet/airoha/airoha_npu.c:828:\tif (!airoha_npu_wlan_msg_get(npu, 0, WLAN_FUNC_GET_WAIT_NPU_VERSION,\ndrivers/net/ethernet/airoha/airoha_npu.c-829-\t\t\t\t \u0026val, sizeof(val), GFP_KERNEL))\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-837-\ndrivers/net/ethernet/airoha/airoha_npu.c:838:static void airoha_npu_remove(struct platform_device pdev)\ndrivers/net/ethernet/airoha/airoha_npu.c-839-{\ndrivers/net/ethernet/airoha/airoha_npu.c:840:\tstruct airoha_npu npu = platform_get_drvdata(pdev);\ndrivers/net/ethernet/airoha/airoha_npu.c-841-\tint i;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-846-\ndrivers/net/ethernet/airoha/airoha_npu.c:847:static struct platform_driver airoha_npu_driver = {\ndrivers/net/ethernet/airoha/airoha_npu.c:848:\t.probe = airoha_npu_probe,\ndrivers/net/ethernet/airoha/airoha_npu.c:849:\t.remove = airoha_npu_remove,\ndrivers/net/ethernet/airoha/airoha_npu.c-850-\t.driver = {\ndrivers/net/ethernet/airoha/airoha_npu.c-851-\t\t.name = \"airoha-npu\",\ndrivers/net/ethernet/airoha/airoha_npu.c:852:\t\t.of_match_table = of_airoha_npu_match,\ndrivers/net/ethernet/airoha/airoha_npu.c-853-\t},\ndrivers/net/ethernet/airoha/airoha_npu.c-854-};\ndrivers/net/ethernet/airoha/airoha_npu.c:855:module_platform_driver(airoha_npu_driver);\ndrivers/net/ethernet/airoha/airoha_npu.c-856-\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=607=static void airoha_ppe_foe_flow_stat_entry_reset(struct airoha_ppe ppe,\ndrivers/net/ethernet/airoha/airoha_ppe.c:608:\t\t\t\t\t\t struct airoha_npu npu,\ndrivers/net/ethernet/airoha/airoha_ppe.c-609-\t\t\t\t\t\t int index)\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=615=static void airoha_ppe_foe_flow_stats_reset(struct airoha_ppe ppe,\ndrivers/net/ethernet/airoha/airoha_ppe.c:616:\t\t\t\t\t struct airoha_npu npu)\ndrivers/net/ethernet/airoha/airoha_ppe.c-617-{\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=628=static void airoha_ppe_foe_flow_stats_update(struct airoha_ppe ppe,\ndrivers/net/ethernet/airoha/airoha_ppe.c:629:\t\t\t\t\t struct airoha_npu npu,\ndrivers/net/ethernet/airoha/airoha_ppe.c-630-\t\t\t\t\t struct airoha_foe_entry hwe,\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=765=static int airoha_ppe_foe_commit_entry(struct airoha_ppe ppe,\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-772-\tstruct airoha_eth eth = ppe-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_ppe.c:773:\tstruct airoha_npu npu;\ndrivers/net/ethernet/airoha/airoha_ppe.c-774-\tint err = 0;\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=1301=void airoha_ppe_foe_entry_get_stats(struct airoha_ppe ppe, u32 hash,\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1305-\tint ppe_num_stats_entries;\ndrivers/net/ethernet/airoha/airoha_ppe.c:1306:\tstruct airoha_npu npu;\ndrivers/net/ethernet/airoha/airoha_ppe.c-1307-\tu32 index;\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=1379=static int airoha_ppe_flush_sram_entries(struct airoha_ppe ppe)\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1396-\ndrivers/net/ethernet/airoha/airoha_ppe.c:1397:static struct airoha_npu airoha_ppe_npu_get(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_ppe.c-1398-{\ndrivers/net/ethernet/airoha/airoha_ppe.c:1399:\tstruct airoha_npu npu = airoha_npu_get(eth-\u003edev);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1400-\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1402-\t\trequest_module(\"airoha-npu\");\ndrivers/net/ethernet/airoha/airoha_ppe.c:1403:\t\tnpu = airoha_npu_get(eth-\u003edev);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1404-\t}\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=1432=static int airoha_ppe_offload_setup(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_ppe.c-1433-{\ndrivers/net/ethernet/airoha/airoha_ppe.c:1434:\tstruct airoha_npu npu = airoha_ppe_npu_get(eth);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1435-\tstruct airoha_ppe ppe = eth-\u003eppe;\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1466-error_npu_put:\ndrivers/net/ethernet/airoha/airoha_ppe.c:1467:\tairoha_npu_put(npu);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1468-\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=1662=void airoha_ppe_deinit(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_ppe.c-1663-{\ndrivers/net/ethernet/airoha/airoha_ppe.c:1664:\tstruct airoha_npu *npu;\ndrivers/net/ethernet/airoha/airoha_ppe.c-1665-\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1672-\t\tnpu-\u003eops.ppe_deinit(npu);\ndrivers/net/ethernet/airoha/airoha_ppe.c:1673:\t\tairoha_npu_put(npu);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1674-\t}\n" }
5/2	2026/08/14 12:06	llm	patch-evaluator	0m Model: gemini-3.1-pro-preview Args: null Results: null Tokens: input: 15083 output: 32 thoughts: 617 Thoughts: My Assessment of the Airoha NPU Driver and WorthFuzzing Okay, so I'm looking at this `airoha_npu` driver, part of the Airoha Ethernet driver suite. It seems to be an NPU driver specifically for Airoha's EN7581 SoCs. The question is, is this something that requires real hardware and is therefore a no-go for standard QEMU emulation? The EN7581 is a router/gateway SoC, confirming that it's probably vendor-specific silicon. The code's in `drivers/net/ethernet/airoha/airoha_npu.c`. The prompt specifically mentions skipping vendor-specific PCIe switch, SmartNIC, or GPU drivers that need real PCIe hardware. I need to figure out if this fits that description. A quick check of the source reveals it's registered as a `platform_driver`. That means it's an IP block within the SoC, and not a PCIe device, which changes things a bit! Platform drivers are often SoC-specific, relying on specific device tree nodes and memory-mapped I/O regions. The likelihood of standard QEMU perfectly emulating the EN7581's platform specifics is vanishingly small, unless there's some obscure machine type for it. However, Syzkaller can sometimes get at platform drivers. It can inject device tree nodes, use `syz_mount_image`, or fake platform devices. But here's the kicker: `airoha_npu_probe` does `devm_platform_ioremap_resource(pdev, 0)`, which means it's directly accessing hardware registers through MMIO. If the hardware isn't emulated, that's just going to crash or fail the probe. Now, while Syzkaller can sometimes poke around via `/dev/` nodes or pseudo-device frameworks, direct MMIO on a platform driver without emulation is a dead end. Unless, of course, there's some way Syzkaller can instantiate this driver, but in this case, I'd need an emulator of the hardware. The key question is whether there's existing Syzkaller support for Airoha's NPU. I need to research this before I make a final call, but my gut tells me it's likely not fuzzable without that.
6/2	2026/08/14 12:07	tool	grepper	0m Args: { "Expression": "airoha", "PathPrefix": "drivers/net/ethernet/airoha/" } Results: { "Output": "\nFull output is too long, showing 500 out of 3689 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/airoha/Makefile-5-\ndrivers/net/ethernet/airoha/Makefile:6:obj-$(CONFIG_NET_AIROHA) += airoha-eth.o\ndrivers/net/ethernet/airoha/Makefile:7:airoha-eth-y := airoha_eth.o airoha_ppe.o\ndrivers/net/ethernet/airoha/Makefile:8:airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-16-\ndrivers/net/ethernet/airoha/airoha_eth.c:17:#include \"airoha_regs.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c:18:#include \"airoha_eth.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c-19-\ndrivers/net/ethernet/airoha/airoha_eth.c:20:u32 airoha_rr(void __iomem base, u32 offset)\ndrivers/net/ethernet/airoha/airoha_eth.c-21-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-24-\ndrivers/net/ethernet/airoha/airoha_eth.c:25:void airoha_wr(void __iomem base, u32 offset, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-26-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-29-\ndrivers/net/ethernet/airoha/airoha_eth.c:30:u32 airoha_rmw(void __iomem base, u32 offset, u32 mask, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-31-{\ndrivers/net/ethernet/airoha/airoha_eth.c:32:\tval \|= (airoha_rr(base, offset) \u0026 ~mask);\ndrivers/net/ethernet/airoha/airoha_eth.c:33:\tairoha_wr(base, offset, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-34-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-37-\ndrivers/net/ethernet/airoha/airoha_eth.c:38:static void airoha_qdma_set_irqmask(struct airoha_irq_bank irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-39-\t\t\t\t int index, u32 clear, u32 set)\ndrivers/net/ethernet/airoha/airoha_eth.c-40-{\ndrivers/net/ethernet/airoha/airoha_eth.c:41:\tstruct airoha_qdma qdma = irq_bank-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-42-\tint bank = irq_bank - \u0026qdma-\u003eirq_banks[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-51-\tirq_bank-\u003eirqmask[index] \|= set;\ndrivers/net/ethernet/airoha/airoha_eth.c:52:\tairoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),\ndrivers/net/ethernet/airoha/airoha_eth.c-53-\t\t irq_bank-\u003eirqmask[index]);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-56-\t /\ndrivers/net/ethernet/airoha/airoha_eth.c:57:\tairoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));\ndrivers/net/ethernet/airoha/airoha_eth.c-58-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-61-\ndrivers/net/ethernet/airoha/airoha_eth.c:62:static void airoha_qdma_irq_enable(struct airoha_irq_bank irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-63-\t\t\t\t int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-64-{\ndrivers/net/ethernet/airoha/airoha_eth.c:65:\tairoha_qdma_set_irqmask(irq_bank, index, 0, mask);\ndrivers/net/ethernet/airoha/airoha_eth.c-66-}\ndrivers/net/ethernet/airoha/airoha_eth.c-67-\ndrivers/net/ethernet/airoha/airoha_eth.c:68:static void airoha_qdma_irq_disable(struct airoha_irq_bank irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-69-\t\t\t\t int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-70-{\ndrivers/net/ethernet/airoha/airoha_eth.c:71:\tairoha_qdma_set_irqmask(irq_bank, index, mask, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-72-}\ndrivers/net/ethernet/airoha/airoha_eth.c-73-\ndrivers/net/ethernet/airoha/airoha_eth.c:74:static int airoha_set_macaddr(struct airoha_gdm_dev dev, const u8 addr)\ndrivers/net/ethernet/airoha/airoha_eth.c-75-{\ndrivers/net/ethernet/airoha/airoha_eth.c-76-\tu8 ref_addr[ETH_ALEN] __aligned(2);\ndrivers/net/ethernet/airoha/airoha_eth.c:77:\tstruct airoha_eth eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-78-\tu32 reg, val, lmin, lmax;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-85-\tfor (i = 0; i \u003c ARRAY_SIZE(eth-\u003eports); i++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:86:\t\tstruct airoha_gdm_port port = eth-\u003eports[i];\ndrivers/net/ethernet/airoha/airoha_eth.c-87-\t\tint j;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-92-\t\tfor (j = 0; j \u003c ARRAY_SIZE(port-\u003edevs); j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:93:\t\t\tstruct airoha_gdm_dev iter_dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-94-\t\t\tstruct net_device netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-99-\ndrivers/net/ethernet/airoha/airoha_eth.c:100:\t\t\tif (airoha_is_lan_gdm_dev(iter_dev) !=\ndrivers/net/ethernet/airoha/airoha_eth.c:101:\t\t\t airoha_is_lan_gdm_dev(dev))\ndrivers/net/ethernet/airoha/airoha_eth.c-102-\t\t\t\tcontinue;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-133-\ndrivers/net/ethernet/airoha/airoha_eth.c:134:\treg = airoha_is_lan_gdm_dev(dev) ? REG_FE_LAN_MAC_H : REG_FE_WAN_MAC_H;\ndrivers/net/ethernet/airoha/airoha_eth.c-135-\tval = (addr[0] \u003c\u003c 16) \| (addr[1] \u003c\u003c 8) \| addr[2];\ndrivers/net/ethernet/airoha/airoha_eth.c:136:\tairoha_fe_wr(eth, reg, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-137-\ndrivers/net/ethernet/airoha/airoha_eth.c:138:\tairoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), lmin);\ndrivers/net/ethernet/airoha/airoha_eth.c:139:\tairoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), lmax);\ndrivers/net/ethernet/airoha/airoha_eth.c-140-\ndrivers/net/ethernet/airoha/airoha_eth.c:141:\tairoha_ppe_init_upd_mem(dev, addr);\ndrivers/net/ethernet/airoha/airoha_eth.c-142-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-145-\ndrivers/net/ethernet/airoha/airoha_eth.c:146:static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth eth, u32 addr,\ndrivers/net/ethernet/airoha/airoha_eth.c-147-\t\t\t\t\tu32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-148-{\ndrivers/net/ethernet/airoha/airoha_eth.c:149:\tairoha_fe_rmw(eth, addr, GDM_OCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-150-\t\t FIELD_PREP(GDM_OCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:151:\tairoha_fe_rmw(eth, addr, GDM_MCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-152-\t\t FIELD_PREP(GDM_MCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:153:\tairoha_fe_rmw(eth, addr, GDM_BCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-154-\t\t FIELD_PREP(GDM_BCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:155:\tairoha_fe_rmw(eth, addr, GDM_UCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-156-\t\t FIELD_PREP(GDM_UCFQ_MASK, val));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-158-\ndrivers/net/ethernet/airoha/airoha_eth.c:159:static int airoha_set_vip_for_gdm_port(struct airoha_gdm_dev dev, bool enable)\ndrivers/net/ethernet/airoha/airoha_eth.c-160-{\ndrivers/net/ethernet/airoha/airoha_eth.c:161:\tstruct airoha_gdm_port port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c:162:\tstruct airoha_eth eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-163-\tu32 vip_port;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-166-\tif (enable) {\ndrivers/net/ethernet/airoha/airoha_eth.c:167:\t\tairoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:168:\t\tairoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-169-\t} else {\ndrivers/net/ethernet/airoha/airoha_eth.c:170:\t\tairoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:171:\t\tairoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-172-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-176-\ndrivers/net/ethernet/airoha/airoha_eth.c:177:static void airoha_fe_maccr_init(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-178-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-181-\tfor (p = 1; p \u003c= ARRAY_SIZE(eth-\u003eports); p++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:182:\t\tairoha_fe_set(eth, REG_GDM_FWD_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-183-\t\t\t GDM_TCP_CKSUM_MASK \| GDM_UDP_CKSUM_MASK \|\ndrivers/net/ethernet/airoha/airoha_eth.c-184-\t\t\t GDM_IP4_CKSUM_MASK \| GDM_DROP_CRC_ERR_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:185:\t\tairoha_fe_rmw(eth, REG_GDM_LEN_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-186-\t\t\t GDM_SHORT_LEN_MASK \| GDM_LONG_LEN_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-190-\ndrivers/net/ethernet/airoha/airoha_eth.c:191:\tairoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-192-\t\t FIELD_PREP(CDM_VLAN_MASK, 0x8100));\ndrivers/net/ethernet/airoha/airoha_eth.c-193-\ndrivers/net/ethernet/airoha/airoha_eth.c:194:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD);\ndrivers/net/ethernet/airoha/airoha_eth.c-195-}\ndrivers/net/ethernet/airoha/airoha_eth.c-196-\ndrivers/net/ethernet/airoha/airoha_eth.c:197:static void airoha_fe_vip_setup(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-198-{\ndrivers/net/ethernet/airoha/airoha_eth.c:199:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC);\ndrivers/net/ethernet/airoha/airoha_eth.c:200:\tairoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK \| PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-201-\ndrivers/net/ethernet/airoha/airoha_eth.c:202:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:203:\tairoha_fe_wr(eth, REG_FE_VIP_EN(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-204-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-206-\ndrivers/net/ethernet/airoha/airoha_eth.c:207:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:208:\tairoha_fe_wr(eth, REG_FE_VIP_EN(6),\ndrivers/net/ethernet/airoha/airoha_eth.c-209-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-211-\ndrivers/net/ethernet/airoha/airoha_eth.c:212:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:213:\tairoha_fe_wr(eth, REG_FE_VIP_EN(7),\ndrivers/net/ethernet/airoha/airoha_eth.c-214-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-217-\t/* BOOTP (0x43) /\ndrivers/net/ethernet/airoha/airoha_eth.c:218:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43);\ndrivers/net/ethernet/airoha/airoha_eth.c:219:\tairoha_fe_wr(eth, REG_FE_VIP_EN(8),\ndrivers/net/ethernet/airoha/airoha_eth.c-220-\t\t PATN_FCPU_EN_MASK \| PATN_SP_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-223-\t/ BOOTP (0x44) /\ndrivers/net/ethernet/airoha/airoha_eth.c:224:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44);\ndrivers/net/ethernet/airoha/airoha_eth.c:225:\tairoha_fe_wr(eth, REG_FE_VIP_EN(9),\ndrivers/net/ethernet/airoha/airoha_eth.c-226-\t\t PATN_FCPU_EN_MASK \| PATN_SP_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-229-\t/ ISAKMP /\ndrivers/net/ethernet/airoha/airoha_eth.c:230:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4);\ndrivers/net/ethernet/airoha/airoha_eth.c:231:\tairoha_fe_wr(eth, REG_FE_VIP_EN(10),\ndrivers/net/ethernet/airoha/airoha_eth.c-232-\t\t PATN_FCPU_EN_MASK \| PATN_DP_EN_MASK \| PATN_SP_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-234-\ndrivers/net/ethernet/airoha/airoha_eth.c:235:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP);\ndrivers/net/ethernet/airoha/airoha_eth.c:236:\tairoha_fe_wr(eth, REG_FE_VIP_EN(11),\ndrivers/net/ethernet/airoha/airoha_eth.c-237-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-240-\t/ DHCPv6 /\ndrivers/net/ethernet/airoha/airoha_eth.c:241:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223);\ndrivers/net/ethernet/airoha/airoha_eth.c:242:\tairoha_fe_wr(eth, REG_FE_VIP_EN(12),\ndrivers/net/ethernet/airoha/airoha_eth.c-243-\t\t PATN_FCPU_EN_MASK \| PATN_DP_EN_MASK \| PATN_SP_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-245-\ndrivers/net/ethernet/airoha/airoha_eth.c:246:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:247:\tairoha_fe_wr(eth, REG_FE_VIP_EN(19),\ndrivers/net/ethernet/airoha/airoha_eth.c-248-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-251-\t/ ETH-\u003eETH_P_1905 (0x893a) /\ndrivers/net/ethernet/airoha/airoha_eth.c:252:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a);\ndrivers/net/ethernet/airoha/airoha_eth.c:253:\tairoha_fe_wr(eth, REG_FE_VIP_EN(20),\ndrivers/net/ethernet/airoha/airoha_eth.c-254-\t\t PATN_FCPU_EN_MASK \| PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-255-\ndrivers/net/ethernet/airoha/airoha_eth.c:256:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP);\ndrivers/net/ethernet/airoha/airoha_eth.c:257:\tairoha_fe_wr(eth, REG_FE_VIP_EN(21),\ndrivers/net/ethernet/airoha/airoha_eth.c-258-\t\t PATN_FCPU_EN_MASK \| PATN_EN_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-260-\ndrivers/net/ethernet/airoha/airoha_eth.c:261:static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-262-\t\t\t\t\t u32 port, u32 queue)\ndrivers/net/ethernet/airoha/airoha_eth.c-263-{\ndrivers/net/ethernet/airoha/airoha_eth.c:264:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-265-\t\t PSE_CFG_PORT_ID_MASK \| PSE_CFG_QUEUE_ID_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-268-\ndrivers/net/ethernet/airoha/airoha_eth.c:269:\treturn airoha_fe_get(eth, REG_FE_PSE_QUEUE_CFG_VAL,\ndrivers/net/ethernet/airoha/airoha_eth.c-270-\t\t\t PSE_CFG_OQ_RSV_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-272-\ndrivers/net/ethernet/airoha/airoha_eth.c:273:static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-274-\t\t\t\t\t u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-275-{\ndrivers/net/ethernet/airoha/airoha_eth.c:276:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-277-\t\t FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:278:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-279-\t\t PSE_CFG_PORT_ID_MASK \| PSE_CFG_QUEUE_ID_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-285-\ndrivers/net/ethernet/airoha/airoha_eth.c:286:static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-287-{\ndrivers/net/ethernet/airoha/airoha_eth.c:288:\treturn airoha_fe_get(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-289-}\ndrivers/net/ethernet/airoha/airoha_eth.c-290-\ndrivers/net/ethernet/airoha/airoha_eth.c:291:static int airoha_fe_set_pse_oq_rsv(struct airoha_eth eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-292-\t\t\t\t u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-293-{\ndrivers/net/ethernet/airoha/airoha_eth.c:294:\tu32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);\ndrivers/net/ethernet/airoha/airoha_eth.c-295-\tu32 tmp, all_rsv, fq_limit;\ndrivers/net/ethernet/airoha/airoha_eth.c-296-\ndrivers/net/ethernet/airoha/airoha_eth.c:297:\tairoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-298-\ndrivers/net/ethernet/airoha/airoha_eth.c-299-\t/ modify all rsv /\ndrivers/net/ethernet/airoha/airoha_eth.c:300:\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-301-\tall_rsv += (val - orig_val);\ndrivers/net/ethernet/airoha/airoha_eth.c:302:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-303-\t\t FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-305-\t/ modify hthd /\ndrivers/net/ethernet/airoha/airoha_eth.c:306:\tfq_limit = airoha_fe_get(eth, PSE_FQ_CFG, PSE_FQ_LIMIT_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-307-\ttmp = fq_limit - all_rsv - 0x20;\ndrivers/net/ethernet/airoha/airoha_eth.c:308:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-309-\t\t PSE_SHARE_USED_HTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-312-\ttmp = fq_limit - all_rsv - 0x100;\ndrivers/net/ethernet/airoha/airoha_eth.c:313:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-314-\t\t PSE_SHARE_USED_MTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-316-\ttmp = (3 tmp) \u003e\u003e 2;\ndrivers/net/ethernet/airoha/airoha_eth.c:317:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET,\ndrivers/net/ethernet/airoha/airoha_eth.c-318-\t\t PSE_SHARE_USED_LTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-323-\ndrivers/net/ethernet/airoha/airoha_eth.c:324:static void airoha_fe_pse_ports_init(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-325-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-340-\ndrivers/net/ethernet/airoha/airoha_eth.c:341:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-342-\t\tu32 all_rsv;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-344-\t\t/ hw misses PPE2 oq rsv /\ndrivers/net/ethernet/airoha/airoha_eth.c:345:\t\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-346-\t\tall_rsv += PSE_RSV_PAGES \ndrivers/net/ethernet/airoha/airoha_eth.c-347-\t\t\t pse_port_num_queues[FE_PSE_PORT_PPE2];\ndrivers/net/ethernet/airoha/airoha_eth.c:348:\t\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-349-\t\t\t FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-353-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:354:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-355-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-357-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:358:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-359-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-361-\tfor (q = 6; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:362:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-363-\t/* GDM3 /\ndrivers/net/ethernet/airoha/airoha_eth.c-364-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM3]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:365:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-366-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-369-\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE1] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:370:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-371-\t\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c-372-\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:373:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-374-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-376-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:377:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-378-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-380-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:381:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-382-\t/ CDM4 /\ndrivers/net/ethernet/airoha/airoha_eth.c-383-\tfor (q = 4; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:384:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-385-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c:386:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-387-\t\t/ PPE2 /\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-389-\t\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE2] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:390:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-391-\t\t\t\t\t\t\t q,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-393-\t\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:394:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-395-\t\t\t\t\t\t\t q, 0);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-399-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:400:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-401-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-403-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM5]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:404:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-405-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-407-\ndrivers/net/ethernet/airoha/airoha_eth.c:408:static int airoha_fe_mc_vlan_clear(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-409-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-415-\ndrivers/net/ethernet/airoha/airoha_eth.c:416:\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-417-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-419-\t\t MC_VLAN_CFG_TABLE_SEL_MASK \| MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:420:\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:421:\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-422-\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-428-\t\tfor (j = 0; j \u003c AIROHA_FE_MC_MAX_VLAN_PORT; j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:429:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-430-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-433-\t\t\t MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:434:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:435:\t\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-436-\t\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-447-\ndrivers/net/ethernet/airoha/airoha_eth.c:448:static void airoha_fe_crsn_qsel_init(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-449-{\ndrivers/net/ethernet/airoha/airoha_eth.c-450-\t/ CDM1_CRSN_QSEL /\ndrivers/net/ethernet/airoha/airoha_eth.c:451:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-452-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-454-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:455:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-456-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-458-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:459:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-460-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-462-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:463:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-464-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-466-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:467:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-468-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-471-\t/ CDM2_CRSN_QSEL /\ndrivers/net/ethernet/airoha/airoha_eth.c:472:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-473-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-475-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:476:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-477-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-479-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:480:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-481-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-483-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:484:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-485-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-487-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:488:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-489-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-493-\ndrivers/net/ethernet/airoha/airoha_eth.c:494:static int airoha_fe_init(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-495-{\ndrivers/net/ethernet/airoha/airoha_eth.c:496:\tairoha_fe_maccr_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-497-\ndrivers/net/ethernet/airoha/airoha_eth.c-498-\t/* PSE IQ reserve /\ndrivers/net/ethernet/airoha/airoha_eth.c:499:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-500-\t\t FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10));\ndrivers/net/ethernet/airoha/airoha_eth.c:501:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV2,\ndrivers/net/ethernet/airoha/airoha_eth.c-502-\t\t PSE_IQ_RES2_P5_MASK \| PSE_IQ_RES2_P4_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-506-\t/ enable FE copy engine for KA/DPI /\ndrivers/net/ethernet/airoha/airoha_eth.c:507:\tairoha_fe_wr(eth, REG_FE_PCE_CFG, PCE_DPI_EN_MASK \| PCE_KA_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-508-\t/ set vip queue selection to ring 1 /\ndrivers/net/ethernet/airoha/airoha_eth.c:509:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-510-\t\t FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c:511:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-512-\t\t FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c-513-\t/ set GDM4 source interface offset to 8 /\ndrivers/net/ethernet/airoha/airoha_eth.c:514:\tairoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-515-\t\t GDM_SPORT_OFF2_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-522-\t/ set PSE Page as 128B /\ndrivers/net/ethernet/airoha/airoha_eth.c:523:\tairoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-524-\t\t FE_DMA_GLO_L2_SPACE_MASK \| FE_DMA_GLO_PG_SZ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-526-\t\t FE_DMA_GLO_PG_SZ_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:527:\tairoha_fe_wr(eth, REG_FE_RST_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-528-\t\t FE_RST_CORE_MASK \| FE_RST_GDM3_MBI_ARB_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-534-\t /\ndrivers/net/ethernet/airoha/airoha_eth.c:535:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:536:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c:537:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:538:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c-539-\ndrivers/net/ethernet/airoha/airoha_eth.c:540:\tairoha_fe_vip_setup(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c:541:\tairoha_fe_pse_ports_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-542-\ndrivers/net/ethernet/airoha/airoha_eth.c:543:\tairoha_fe_set(eth, REG_GDM_MISC_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-544-\t\t GDM2_RDM_ACK_WAIT_PREF_MASK \|\ndrivers/net/ethernet/airoha/airoha_eth.c-545-\t\t GDM2_CHN_VLD_MODE_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:546:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-547-\t\t FIELD_PREP(CDM_OAM_QSEL_MASK, 15));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-550-\t/* NPU Core-3, NPU Bridge Channel-3 /\ndrivers/net/ethernet/airoha/airoha_eth.c:551:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-552-\t\t IP_FRAGMENT_PORT_MASK \| IP_FRAGMENT_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-555-\t/ QDMA LAN, RX Ring-22 /\ndrivers/net/ethernet/airoha/airoha_eth.c:556:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-557-\t\t IP_ASSEMBLE_PORT_MASK \| IP_ASSEMBLE_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-560-\ndrivers/net/ethernet/airoha/airoha_eth.c:561:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:562:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-563-\ndrivers/net/ethernet/airoha/airoha_eth.c-564-\t/ Enable split for MIB counters for GDM3 and GDM4 /\ndrivers/net/ethernet/airoha/airoha_eth.c:565:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM3_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-566-\t\t FE_GDM_TX_MIB_SPLIT_EN_MASK \|\ndrivers/net/ethernet/airoha/airoha_eth.c-567-\t\t FE_GDM_RX_MIB_SPLIT_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:568:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM4_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-569-\t\t FE_GDM_TX_MIB_SPLIT_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-571-\ndrivers/net/ethernet/airoha/airoha_eth.c:572:\tairoha_fe_crsn_qsel_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-573-\ndrivers/net/ethernet/airoha/airoha_eth.c:574:\tairoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:575:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-576-\ndrivers/net/ethernet/airoha/airoha_eth.c-577-\t/ default aging mode for mbi unlock issue /\ndrivers/net/ethernet/airoha/airoha_eth.c:578:\tairoha_fe_rmw(eth, REG_GDM_CHN_RLS(2),\ndrivers/net/ethernet/airoha/airoha_eth.c-579-\t\t MBI_RX_AGE_SEL_MASK \| MBI_TX_AGE_SEL_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-583-\t/ disable IFC by default /\ndrivers/net/ethernet/airoha/airoha_eth.c:584:\tairoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-585-\ndrivers/net/ethernet/airoha/airoha_eth.c-586-\t/ enable 1:N vlan action, init vlan table /\ndrivers/net/ethernet/airoha/airoha_eth.c:587:\tairoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-588-\ndrivers/net/ethernet/airoha/airoha_eth.c:589:\treturn airoha_fe_mc_vlan_clear(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-590-}\ndrivers/net/ethernet/airoha/airoha_eth.c-591-\ndrivers/net/ethernet/airoha/airoha_eth.c:592:static int airoha_qdma_fill_rx_queue(struct airoha_queue q)\ndrivers/net/ethernet/airoha/airoha_eth.c-593-{\ndrivers/net/ethernet/airoha/airoha_eth.c:594:\tstruct airoha_qdma qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-595-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-598-\twhile (q-\u003equeued \u003c q-\u003endesc - 1) {\ndrivers/net/ethernet/airoha/airoha_eth.c:599:\t\tstruct airoha_queue_entry e = \u0026q-\u003eentry[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c:600:\t\tstruct airoha_qdma_desc desc = \u0026q-\u003edesc[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c-601-\t\tstruct page page;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-630-\tif (nframes)\ndrivers/net/ethernet/airoha/airoha_eth.c:631:\t\tairoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid),\ndrivers/net/ethernet/airoha/airoha_eth.c-632-\t\t\t\tRX_RING_CPU_IDX_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-637-\ndrivers/net/ethernet/airoha/airoha_eth.c:638:static struct airoha_gdm_dev \ndrivers/net/ethernet/airoha/airoha_eth.c:639:airoha_qdma_get_gdm_dev(struct airoha_eth eth, struct airoha_qdma_desc desc)\ndrivers/net/ethernet/airoha/airoha_eth.c-640-{\ndrivers/net/ethernet/airoha/airoha_eth.c:641:\tstruct airoha_gdm_port port;\ndrivers/net/ethernet/airoha/airoha_eth.c-642-\tu16 p, d;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-659-\ndrivers/net/ethernet/airoha/airoha_eth.c:660:static int airoha_qdma_rx_process(struct airoha_queue q, int budget)\ndrivers/net/ethernet/airoha/airoha_eth.c-661-{\ndrivers/net/ethernet/airoha/airoha_eth.c-662-\tenum dma_data_direction dir = page_pool_get_dma_dir(q-\u003epage_pool);\ndrivers/net/ethernet/airoha/airoha_eth.c:663:\tstruct airoha_qdma qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c:664:\tstruct airoha_eth eth = qdma-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-665-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-668-\twhile (done \u003c budget) {\ndrivers/net/ethernet/airoha/airoha_eth.c:669:\t\tstruct airoha_queue_entry e = \u0026q-\u003eentry[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c:670:\t\tstruct airoha_qdma_desc desc = \u0026q-\u003edesc[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c-671-\t\tu32 hash, reason, msg1, desc_ctrl;\ndrivers/net/ethernet/airoha/airoha_eth.c:672:\t\tstruct airoha_gdm_dev dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-673-\t\tstruct net_device netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-694-\ndrivers/net/ethernet/airoha/airoha_eth.c:695:\t\tdev = airoha_qdma_get_gdm_dev(eth, desc);\ndrivers/net/ethernet/airoha/airoha_eth.c-696-\t\tif (IS_ERR(dev))\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-728-\t\tif (netdev_uses_dsa(netdev)) {\ndrivers/net/ethernet/airoha/airoha_eth.c:729:\t\t\tstruct airoha_gdm_port port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c-730-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-752-\t\tif (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)\ndrivers/net/ethernet/airoha/airoha_eth.c:753:\t\t\tairoha_ppe_check_skb(\u0026eth-\u003eppe-\u003edev, q-\u003eskb, hash,\n\n" }
7/2	2026/08/14 12:07	llm	patch-evaluator	0m Model: gemini-3.1-pro-preview Args: null Results: null Tokens: input: 32528 output: 32 thoughts: 1744 Thoughts: Analysis of the Airoha NPU Driver for Fuzzing Suitability Okay, so I'm looking at the `airoha_npu` code, specifically within the `drivers/net/ethernet/airoha/airoha_eth.c` driver. I see that `airoha_npu` is initialized via `airoha_ppe_npu_get()`, which is called from `airoha_ppe_offload_setup()`. And, `airoha_ppe_offload_setup()` itself is called by functions in `airoha_eth.c`. My first instinct is to check if `airoha_eth.c` is a standard Ethernet driver. Yes, it seems to be an Ethernet driver specifically for Airoha SoCs. Now, the crucial question is whether this is some special-purpose hardware, like a PCIe switch, SmartNIC, or GPU driver, because if so, it's immediately excluded from fuzzing. But no, it's just an SoC-integrated Ethernet driver. That's key. The prompt specifically says to return `WorthFuzzing=false` if the code falls under several categories, including code that requires specific hardware not emulated in standard QEMU. Is Airoha Ethernet a PCIe card? No, it's built into the SoC. Can Syzkaller fuzz this? Syzkaller can fuzz platform drivers if they can be instantiated. Sometimes this happens through device tree overlays or pseudo-devices. The prompt is clear, though: I need to verify that this code can be executed in a virtualized environment. That is, code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware, mean I return `WorthFuzzing=false`. Here's the problem: SoC-specific Ethernet drivers, like Airoha (along with MediaTek and Qualcomm IPQ), are not typically emulated in standard QEMU. They usually require very specific SoC emulation, which isn't present in standard syzkaller QEMU images that use `q35` or `virt` machine types. I know Syzkaller has been evolving, and I'm aware that it's added support for platform drivers through mechanisms like `syz_devres` or similar, but the core issue remains MMIO. If the hardware isn't there, any attempt to read or write to MMIO addresses will result in a crash, a probe failure, or just garbage data. I remember the `syz_platform_device_add` pseudo-syscall, but that doesn't exist. Syzkaller uses `syz_mount_image` and crafted filesystems to load things, maybe including device tree overlays. The latest additions to fuzzing platform drivers depend on what those overlays do. If a DT overlay is used to register this hardware, the driver will try to `devm_platform_ioremap_resource(pdev, 0)`. The overlay will specify some physical address. If that address is not backed by RAM or a real MMIO device in QEMU, `ioremap` might succeed, but actually reading or writing to it will cause a synchronous external abort or page fault if the address is not mapped. Or, I might just get all 0xFFs, which will likely cause a probe failure. Let's look closely at `airoha_npu_probe`: it calls `devm_platform_ioremap_resource()` to map the MMIO region. Then it uses `devm_regmap_init_mmio` to initialize a `regmap`. Crucially, it then calls `airoha_npu_run_firmware()`, which, in turn, calls `airoha_npu_load_firmware()`. This function requests firmware, and if that firmware isn't found, it fails. If the probe fails, everything after it, like `airoha_npu_send_msg`, is never reached. The reachability of `airoha_npu_send_msg` depends on successfully probing the driver. `airoha_npu_send_msg` is called by `airoha_npu_ppe_init`, `airoha_npu_wlan_msg_send`, etc., which are reached through function pointers via `npu->ops.ppe_init` etc. This is called from `airoha_ppe_offload_setup()` in `airoha_ppe.c`, which is ultimately called from `airoha_eth_probe`. Therefore, it requires the `airoha_eth` driver to probe successfully. `airoha_eth` is also a platform driver. If there is no Airoha hardware, this probe will fail. I have to consider the fact
8/2	2026/08/14 12:07	tool	grepper	0m Args: { "Expression": "airoha", "PathPrefix": "drivers/net/ethernet/airoha/" } Results: { "Output": "\nFull output is too long, showing 500 out of 3689 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/airoha/Makefile-5-\ndrivers/net/ethernet/airoha/Makefile:6:obj-$(CONFIG_NET_AIROHA) += airoha-eth.o\ndrivers/net/ethernet/airoha/Makefile:7:airoha-eth-y := airoha_eth.o airoha_ppe.o\ndrivers/net/ethernet/airoha/Makefile:8:airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-16-\ndrivers/net/ethernet/airoha/airoha_eth.c:17:#include \"airoha_regs.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c:18:#include \"airoha_eth.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c-19-\ndrivers/net/ethernet/airoha/airoha_eth.c:20:u32 airoha_rr(void __iomem base, u32 offset)\ndrivers/net/ethernet/airoha/airoha_eth.c-21-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-24-\ndrivers/net/ethernet/airoha/airoha_eth.c:25:void airoha_wr(void __iomem base, u32 offset, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-26-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-29-\ndrivers/net/ethernet/airoha/airoha_eth.c:30:u32 airoha_rmw(void __iomem base, u32 offset, u32 mask, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-31-{\ndrivers/net/ethernet/airoha/airoha_eth.c:32:\tval \|= (airoha_rr(base, offset) \u0026 ~mask);\ndrivers/net/ethernet/airoha/airoha_eth.c:33:\tairoha_wr(base, offset, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-34-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-37-\ndrivers/net/ethernet/airoha/airoha_eth.c:38:static void airoha_qdma_set_irqmask(struct airoha_irq_bank irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-39-\t\t\t\t int index, u32 clear, u32 set)\ndrivers/net/ethernet/airoha/airoha_eth.c-40-{\ndrivers/net/ethernet/airoha/airoha_eth.c:41:\tstruct airoha_qdma qdma = irq_bank-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-42-\tint bank = irq_bank - \u0026qdma-\u003eirq_banks[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-51-\tirq_bank-\u003eirqmask[index] \|= set;\ndrivers/net/ethernet/airoha/airoha_eth.c:52:\tairoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),\ndrivers/net/ethernet/airoha/airoha_eth.c-53-\t\t irq_bank-\u003eirqmask[index]);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-56-\t /\ndrivers/net/ethernet/airoha/airoha_eth.c:57:\tairoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));\ndrivers/net/ethernet/airoha/airoha_eth.c-58-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-61-\ndrivers/net/ethernet/airoha/airoha_eth.c:62:static void airoha_qdma_irq_enable(struct airoha_irq_bank irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-63-\t\t\t\t int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-64-{\ndrivers/net/ethernet/airoha/airoha_eth.c:65:\tairoha_qdma_set_irqmask(irq_bank, index, 0, mask);\ndrivers/net/ethernet/airoha/airoha_eth.c-66-}\ndrivers/net/ethernet/airoha/airoha_eth.c-67-\ndrivers/net/ethernet/airoha/airoha_eth.c:68:static void airoha_qdma_irq_disable(struct airoha_irq_bank irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-69-\t\t\t\t int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-70-{\ndrivers/net/ethernet/airoha/airoha_eth.c:71:\tairoha_qdma_set_irqmask(irq_bank, index, mask, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-72-}\ndrivers/net/ethernet/airoha/airoha_eth.c-73-\ndrivers/net/ethernet/airoha/airoha_eth.c:74:static int airoha_set_macaddr(struct airoha_gdm_dev dev, const u8 addr)\ndrivers/net/ethernet/airoha/airoha_eth.c-75-{\ndrivers/net/ethernet/airoha/airoha_eth.c-76-\tu8 ref_addr[ETH_ALEN] __aligned(2);\ndrivers/net/ethernet/airoha/airoha_eth.c:77:\tstruct airoha_eth eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-78-\tu32 reg, val, lmin, lmax;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-85-\tfor (i = 0; i \u003c ARRAY_SIZE(eth-\u003eports); i++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:86:\t\tstruct airoha_gdm_port port = eth-\u003eports[i];\ndrivers/net/ethernet/airoha/airoha_eth.c-87-\t\tint j;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-92-\t\tfor (j = 0; j \u003c ARRAY_SIZE(port-\u003edevs); j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:93:\t\t\tstruct airoha_gdm_dev iter_dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-94-\t\t\tstruct net_device netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-99-\ndrivers/net/ethernet/airoha/airoha_eth.c:100:\t\t\tif (airoha_is_lan_gdm_dev(iter_dev) !=\ndrivers/net/ethernet/airoha/airoha_eth.c:101:\t\t\t airoha_is_lan_gdm_dev(dev))\ndrivers/net/ethernet/airoha/airoha_eth.c-102-\t\t\t\tcontinue;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-133-\ndrivers/net/ethernet/airoha/airoha_eth.c:134:\treg = airoha_is_lan_gdm_dev(dev) ? REG_FE_LAN_MAC_H : REG_FE_WAN_MAC_H;\ndrivers/net/ethernet/airoha/airoha_eth.c-135-\tval = (addr[0] \u003c\u003c 16) \| (addr[1] \u003c\u003c 8) \| addr[2];\ndrivers/net/ethernet/airoha/airoha_eth.c:136:\tairoha_fe_wr(eth, reg, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-137-\ndrivers/net/ethernet/airoha/airoha_eth.c:138:\tairoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), lmin);\ndrivers/net/ethernet/airoha/airoha_eth.c:139:\tairoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), lmax);\ndrivers/net/ethernet/airoha/airoha_eth.c-140-\ndrivers/net/ethernet/airoha/airoha_eth.c:141:\tairoha_ppe_init_upd_mem(dev, addr);\ndrivers/net/ethernet/airoha/airoha_eth.c-142-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-145-\ndrivers/net/ethernet/airoha/airoha_eth.c:146:static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth eth, u32 addr,\ndrivers/net/ethernet/airoha/airoha_eth.c-147-\t\t\t\t\tu32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-148-{\ndrivers/net/ethernet/airoha/airoha_eth.c:149:\tairoha_fe_rmw(eth, addr, GDM_OCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-150-\t\t FIELD_PREP(GDM_OCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:151:\tairoha_fe_rmw(eth, addr, GDM_MCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-152-\t\t FIELD_PREP(GDM_MCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:153:\tairoha_fe_rmw(eth, addr, GDM_BCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-154-\t\t FIELD_PREP(GDM_BCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:155:\tairoha_fe_rmw(eth, addr, GDM_UCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-156-\t\t FIELD_PREP(GDM_UCFQ_MASK, val));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-158-\ndrivers/net/ethernet/airoha/airoha_eth.c:159:static int airoha_set_vip_for_gdm_port(struct airoha_gdm_dev dev, bool enable)\ndrivers/net/ethernet/airoha/airoha_eth.c-160-{\ndrivers/net/ethernet/airoha/airoha_eth.c:161:\tstruct airoha_gdm_port port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c:162:\tstruct airoha_eth eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-163-\tu32 vip_port;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-166-\tif (enable) {\ndrivers/net/ethernet/airoha/airoha_eth.c:167:\t\tairoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:168:\t\tairoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-169-\t} else {\ndrivers/net/ethernet/airoha/airoha_eth.c:170:\t\tairoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:171:\t\tairoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-172-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-176-\ndrivers/net/ethernet/airoha/airoha_eth.c:177:static void airoha_fe_maccr_init(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-178-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-181-\tfor (p = 1; p \u003c= ARRAY_SIZE(eth-\u003eports); p++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:182:\t\tairoha_fe_set(eth, REG_GDM_FWD_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-183-\t\t\t GDM_TCP_CKSUM_MASK \| GDM_UDP_CKSUM_MASK \|\ndrivers/net/ethernet/airoha/airoha_eth.c-184-\t\t\t GDM_IP4_CKSUM_MASK \| GDM_DROP_CRC_ERR_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:185:\t\tairoha_fe_rmw(eth, REG_GDM_LEN_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-186-\t\t\t GDM_SHORT_LEN_MASK \| GDM_LONG_LEN_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-190-\ndrivers/net/ethernet/airoha/airoha_eth.c:191:\tairoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-192-\t\t FIELD_PREP(CDM_VLAN_MASK, 0x8100));\ndrivers/net/ethernet/airoha/airoha_eth.c-193-\ndrivers/net/ethernet/airoha/airoha_eth.c:194:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD);\ndrivers/net/ethernet/airoha/airoha_eth.c-195-}\ndrivers/net/ethernet/airoha/airoha_eth.c-196-\ndrivers/net/ethernet/airoha/airoha_eth.c:197:static void airoha_fe_vip_setup(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-198-{\ndrivers/net/ethernet/airoha/airoha_eth.c:199:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC);\ndrivers/net/ethernet/airoha/airoha_eth.c:200:\tairoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK \| PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-201-\ndrivers/net/ethernet/airoha/airoha_eth.c:202:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:203:\tairoha_fe_wr(eth, REG_FE_VIP_EN(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-204-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-206-\ndrivers/net/ethernet/airoha/airoha_eth.c:207:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:208:\tairoha_fe_wr(eth, REG_FE_VIP_EN(6),\ndrivers/net/ethernet/airoha/airoha_eth.c-209-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-211-\ndrivers/net/ethernet/airoha/airoha_eth.c:212:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:213:\tairoha_fe_wr(eth, REG_FE_VIP_EN(7),\ndrivers/net/ethernet/airoha/airoha_eth.c-214-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-217-\t/* BOOTP (0x43) /\ndrivers/net/ethernet/airoha/airoha_eth.c:218:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43);\ndrivers/net/ethernet/airoha/airoha_eth.c:219:\tairoha_fe_wr(eth, REG_FE_VIP_EN(8),\ndrivers/net/ethernet/airoha/airoha_eth.c-220-\t\t PATN_FCPU_EN_MASK \| PATN_SP_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-223-\t/ BOOTP (0x44) /\ndrivers/net/ethernet/airoha/airoha_eth.c:224:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44);\ndrivers/net/ethernet/airoha/airoha_eth.c:225:\tairoha_fe_wr(eth, REG_FE_VIP_EN(9),\ndrivers/net/ethernet/airoha/airoha_eth.c-226-\t\t PATN_FCPU_EN_MASK \| PATN_SP_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-229-\t/ ISAKMP /\ndrivers/net/ethernet/airoha/airoha_eth.c:230:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4);\ndrivers/net/ethernet/airoha/airoha_eth.c:231:\tairoha_fe_wr(eth, REG_FE_VIP_EN(10),\ndrivers/net/ethernet/airoha/airoha_eth.c-232-\t\t PATN_FCPU_EN_MASK \| PATN_DP_EN_MASK \| PATN_SP_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-234-\ndrivers/net/ethernet/airoha/airoha_eth.c:235:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP);\ndrivers/net/ethernet/airoha/airoha_eth.c:236:\tairoha_fe_wr(eth, REG_FE_VIP_EN(11),\ndrivers/net/ethernet/airoha/airoha_eth.c-237-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-240-\t/ DHCPv6 /\ndrivers/net/ethernet/airoha/airoha_eth.c:241:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223);\ndrivers/net/ethernet/airoha/airoha_eth.c:242:\tairoha_fe_wr(eth, REG_FE_VIP_EN(12),\ndrivers/net/ethernet/airoha/airoha_eth.c-243-\t\t PATN_FCPU_EN_MASK \| PATN_DP_EN_MASK \| PATN_SP_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-245-\ndrivers/net/ethernet/airoha/airoha_eth.c:246:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:247:\tairoha_fe_wr(eth, REG_FE_VIP_EN(19),\ndrivers/net/ethernet/airoha/airoha_eth.c-248-\t\t PATN_FCPU_EN_MASK \| FIELD_PREP(PATN_TYPE_MASK, 1) \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-251-\t/ ETH-\u003eETH_P_1905 (0x893a) /\ndrivers/net/ethernet/airoha/airoha_eth.c:252:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a);\ndrivers/net/ethernet/airoha/airoha_eth.c:253:\tairoha_fe_wr(eth, REG_FE_VIP_EN(20),\ndrivers/net/ethernet/airoha/airoha_eth.c-254-\t\t PATN_FCPU_EN_MASK \| PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-255-\ndrivers/net/ethernet/airoha/airoha_eth.c:256:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP);\ndrivers/net/ethernet/airoha/airoha_eth.c:257:\tairoha_fe_wr(eth, REG_FE_VIP_EN(21),\ndrivers/net/ethernet/airoha/airoha_eth.c-258-\t\t PATN_FCPU_EN_MASK \| PATN_EN_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-260-\ndrivers/net/ethernet/airoha/airoha_eth.c:261:static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-262-\t\t\t\t\t u32 port, u32 queue)\ndrivers/net/ethernet/airoha/airoha_eth.c-263-{\ndrivers/net/ethernet/airoha/airoha_eth.c:264:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-265-\t\t PSE_CFG_PORT_ID_MASK \| PSE_CFG_QUEUE_ID_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-268-\ndrivers/net/ethernet/airoha/airoha_eth.c:269:\treturn airoha_fe_get(eth, REG_FE_PSE_QUEUE_CFG_VAL,\ndrivers/net/ethernet/airoha/airoha_eth.c-270-\t\t\t PSE_CFG_OQ_RSV_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-272-\ndrivers/net/ethernet/airoha/airoha_eth.c:273:static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-274-\t\t\t\t\t u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-275-{\ndrivers/net/ethernet/airoha/airoha_eth.c:276:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-277-\t\t FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:278:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-279-\t\t PSE_CFG_PORT_ID_MASK \| PSE_CFG_QUEUE_ID_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-285-\ndrivers/net/ethernet/airoha/airoha_eth.c:286:static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-287-{\ndrivers/net/ethernet/airoha/airoha_eth.c:288:\treturn airoha_fe_get(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-289-}\ndrivers/net/ethernet/airoha/airoha_eth.c-290-\ndrivers/net/ethernet/airoha/airoha_eth.c:291:static int airoha_fe_set_pse_oq_rsv(struct airoha_eth eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-292-\t\t\t\t u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-293-{\ndrivers/net/ethernet/airoha/airoha_eth.c:294:\tu32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);\ndrivers/net/ethernet/airoha/airoha_eth.c-295-\tu32 tmp, all_rsv, fq_limit;\ndrivers/net/ethernet/airoha/airoha_eth.c-296-\ndrivers/net/ethernet/airoha/airoha_eth.c:297:\tairoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-298-\ndrivers/net/ethernet/airoha/airoha_eth.c-299-\t/ modify all rsv /\ndrivers/net/ethernet/airoha/airoha_eth.c:300:\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-301-\tall_rsv += (val - orig_val);\ndrivers/net/ethernet/airoha/airoha_eth.c:302:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-303-\t\t FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-305-\t/ modify hthd /\ndrivers/net/ethernet/airoha/airoha_eth.c:306:\tfq_limit = airoha_fe_get(eth, PSE_FQ_CFG, PSE_FQ_LIMIT_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-307-\ttmp = fq_limit - all_rsv - 0x20;\ndrivers/net/ethernet/airoha/airoha_eth.c:308:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-309-\t\t PSE_SHARE_USED_HTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-312-\ttmp = fq_limit - all_rsv - 0x100;\ndrivers/net/ethernet/airoha/airoha_eth.c:313:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-314-\t\t PSE_SHARE_USED_MTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-316-\ttmp = (3 tmp) \u003e\u003e 2;\ndrivers/net/ethernet/airoha/airoha_eth.c:317:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET,\ndrivers/net/ethernet/airoha/airoha_eth.c-318-\t\t PSE_SHARE_USED_LTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-323-\ndrivers/net/ethernet/airoha/airoha_eth.c:324:static void airoha_fe_pse_ports_init(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-325-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-340-\ndrivers/net/ethernet/airoha/airoha_eth.c:341:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-342-\t\tu32 all_rsv;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-344-\t\t/ hw misses PPE2 oq rsv /\ndrivers/net/ethernet/airoha/airoha_eth.c:345:\t\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-346-\t\tall_rsv += PSE_RSV_PAGES \ndrivers/net/ethernet/airoha/airoha_eth.c-347-\t\t\t pse_port_num_queues[FE_PSE_PORT_PPE2];\ndrivers/net/ethernet/airoha/airoha_eth.c:348:\t\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-349-\t\t\t FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-353-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:354:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-355-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-357-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:358:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-359-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-361-\tfor (q = 6; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:362:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-363-\t/* GDM3 /\ndrivers/net/ethernet/airoha/airoha_eth.c-364-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM3]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:365:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-366-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-369-\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE1] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:370:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-371-\t\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c-372-\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:373:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-374-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-376-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:377:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-378-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-380-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:381:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-382-\t/ CDM4 /\ndrivers/net/ethernet/airoha/airoha_eth.c-383-\tfor (q = 4; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:384:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-385-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c:386:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-387-\t\t/ PPE2 /\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-389-\t\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE2] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:390:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-391-\t\t\t\t\t\t\t q,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-393-\t\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:394:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-395-\t\t\t\t\t\t\t q, 0);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-399-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:400:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-401-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-403-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM5]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:404:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-405-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-407-\ndrivers/net/ethernet/airoha/airoha_eth.c:408:static int airoha_fe_mc_vlan_clear(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-409-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-415-\ndrivers/net/ethernet/airoha/airoha_eth.c:416:\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-417-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-419-\t\t MC_VLAN_CFG_TABLE_SEL_MASK \| MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:420:\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:421:\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-422-\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-428-\t\tfor (j = 0; j \u003c AIROHA_FE_MC_MAX_VLAN_PORT; j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:429:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-430-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-433-\t\t\t MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:434:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:435:\t\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-436-\t\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-447-\ndrivers/net/ethernet/airoha/airoha_eth.c:448:static void airoha_fe_crsn_qsel_init(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-449-{\ndrivers/net/ethernet/airoha/airoha_eth.c-450-\t/ CDM1_CRSN_QSEL /\ndrivers/net/ethernet/airoha/airoha_eth.c:451:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-452-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-454-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:455:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-456-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-458-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:459:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-460-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-462-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:463:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-464-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-466-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:467:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-468-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-471-\t/ CDM2_CRSN_QSEL /\ndrivers/net/ethernet/airoha/airoha_eth.c:472:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-473-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-475-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:476:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-477-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-479-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:480:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-481-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-483-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:484:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-485-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-487-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:488:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-489-\t\t CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-493-\ndrivers/net/ethernet/airoha/airoha_eth.c:494:static int airoha_fe_init(struct airoha_eth eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-495-{\ndrivers/net/ethernet/airoha/airoha_eth.c:496:\tairoha_fe_maccr_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-497-\ndrivers/net/ethernet/airoha/airoha_eth.c-498-\t/* PSE IQ reserve /\ndrivers/net/ethernet/airoha/airoha_eth.c:499:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-500-\t\t FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10));\ndrivers/net/ethernet/airoha/airoha_eth.c:501:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV2,\ndrivers/net/ethernet/airoha/airoha_eth.c-502-\t\t PSE_IQ_RES2_P5_MASK \| PSE_IQ_RES2_P4_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-506-\t/ enable FE copy engine for KA/DPI /\ndrivers/net/ethernet/airoha/airoha_eth.c:507:\tairoha_fe_wr(eth, REG_FE_PCE_CFG, PCE_DPI_EN_MASK \| PCE_KA_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-508-\t/ set vip queue selection to ring 1 /\ndrivers/net/ethernet/airoha/airoha_eth.c:509:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-510-\t\t FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c:511:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-512-\t\t FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c-513-\t/ set GDM4 source interface offset to 8 /\ndrivers/net/ethernet/airoha/airoha_eth.c:514:\tairoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-515-\t\t GDM_SPORT_OFF2_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-522-\t/ set PSE Page as 128B /\ndrivers/net/ethernet/airoha/airoha_eth.c:523:\tairoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-524-\t\t FE_DMA_GLO_L2_SPACE_MASK \| FE_DMA_GLO_PG_SZ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-526-\t\t FE_DMA_GLO_PG_SZ_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:527:\tairoha_fe_wr(eth, REG_FE_RST_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-528-\t\t FE_RST_CORE_MASK \| FE_RST_GDM3_MBI_ARB_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-534-\t /\ndrivers/net/ethernet/airoha/airoha_eth.c:535:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:536:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c:537:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:538:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c-539-\ndrivers/net/ethernet/airoha/airoha_eth.c:540:\tairoha_fe_vip_setup(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c:541:\tairoha_fe_pse_ports_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-542-\ndrivers/net/ethernet/airoha/airoha_eth.c:543:\tairoha_fe_set(eth, REG_GDM_MISC_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-544-\t\t GDM2_RDM_ACK_WAIT_PREF_MASK \|\ndrivers/net/ethernet/airoha/airoha_eth.c-545-\t\t GDM2_CHN_VLD_MODE_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:546:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-547-\t\t FIELD_PREP(CDM_OAM_QSEL_MASK, 15));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-550-\t/* NPU Core-3, NPU Bridge Channel-3 /\ndrivers/net/ethernet/airoha/airoha_eth.c:551:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-552-\t\t IP_FRAGMENT_PORT_MASK \| IP_FRAGMENT_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-555-\t/ QDMA LAN, RX Ring-22 /\ndrivers/net/ethernet/airoha/airoha_eth.c:556:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-557-\t\t IP_ASSEMBLE_PORT_MASK \| IP_ASSEMBLE_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-560-\ndrivers/net/ethernet/airoha/airoha_eth.c:561:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:562:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-563-\ndrivers/net/ethernet/airoha/airoha_eth.c-564-\t/ Enable split for MIB counters for GDM3 and GDM4 /\ndrivers/net/ethernet/airoha/airoha_eth.c:565:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM3_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-566-\t\t FE_GDM_TX_MIB_SPLIT_EN_MASK \|\ndrivers/net/ethernet/airoha/airoha_eth.c-567-\t\t FE_GDM_RX_MIB_SPLIT_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:568:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM4_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-569-\t\t FE_GDM_TX_MIB_SPLIT_EN_MASK \|\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-571-\ndrivers/net/ethernet/airoha/airoha_eth.c:572:\tairoha_fe_crsn_qsel_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-573-\ndrivers/net/ethernet/airoha/airoha_eth.c:574:\tairoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:575:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-576-\ndrivers/net/ethernet/airoha/airoha_eth.c-577-\t/ default aging mode for mbi unlock issue /\ndrivers/net/ethernet/airoha/airoha_eth.c:578:\tairoha_fe_rmw(eth, REG_GDM_CHN_RLS(2),\ndrivers/net/ethernet/airoha/airoha_eth.c-579-\t\t MBI_RX_AGE_SEL_MASK \| MBI_TX_AGE_SEL_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-583-\t/ disable IFC by default /\ndrivers/net/ethernet/airoha/airoha_eth.c:584:\tairoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-585-\ndrivers/net/ethernet/airoha/airoha_eth.c-586-\t/ enable 1:N vlan action, init vlan table /\ndrivers/net/ethernet/airoha/airoha_eth.c:587:\tairoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-588-\ndrivers/net/ethernet/airoha/airoha_eth.c:589:\treturn airoha_fe_mc_vlan_clear(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-590-}\ndrivers/net/ethernet/airoha/airoha_eth.c-591-\ndrivers/net/ethernet/airoha/airoha_eth.c:592:static int airoha_qdma_fill_rx_queue(struct airoha_queue q)\ndrivers/net/ethernet/airoha/airoha_eth.c-593-{\ndrivers/net/ethernet/airoha/airoha_eth.c:594:\tstruct airoha_qdma qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-595-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-598-\twhile (q-\u003equeued \u003c q-\u003endesc - 1) {\ndrivers/net/ethernet/airoha/airoha_eth.c:599:\t\tstruct airoha_queue_entry e = \u0026q-\u003eentry[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c:600:\t\tstruct airoha_qdma_desc desc = \u0026q-\u003edesc[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c-601-\t\tstruct page page;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-630-\tif (nframes)\ndrivers/net/ethernet/airoha/airoha_eth.c:631:\t\tairoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid),\ndrivers/net/ethernet/airoha/airoha_eth.c-632-\t\t\t\tRX_RING_CPU_IDX_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-637-\ndrivers/net/ethernet/airoha/airoha_eth.c:638:static struct airoha_gdm_dev \ndrivers/net/ethernet/airoha/airoha_eth.c:639:airoha_qdma_get_gdm_dev(struct airoha_eth eth, struct airoha_qdma_desc desc)\ndrivers/net/ethernet/airoha/airoha_eth.c-640-{\ndrivers/net/ethernet/airoha/airoha_eth.c:641:\tstruct airoha_gdm_port port;\ndrivers/net/ethernet/airoha/airoha_eth.c-642-\tu16 p, d;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-659-\ndrivers/net/ethernet/airoha/airoha_eth.c:660:static int airoha_qdma_rx_process(struct airoha_queue q, int budget)\ndrivers/net/ethernet/airoha/airoha_eth.c-661-{\ndrivers/net/ethernet/airoha/airoha_eth.c-662-\tenum dma_data_direction dir = page_pool_get_dma_dir(q-\u003epage_pool);\ndrivers/net/ethernet/airoha/airoha_eth.c:663:\tstruct airoha_qdma qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c:664:\tstruct airoha_eth eth = qdma-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-665-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-668-\twhile (done \u003c budget) {\ndrivers/net/ethernet/airoha/airoha_eth.c:669:\t\tstruct airoha_queue_entry e = \u0026q-\u003eentry[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c:670:\t\tstruct airoha_qdma_desc desc = \u0026q-\u003edesc[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c-671-\t\tu32 hash, reason, msg1, desc_ctrl;\ndrivers/net/ethernet/airoha/airoha_eth.c:672:\t\tstruct airoha_gdm_dev dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-673-\t\tstruct net_device netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-694-\ndrivers/net/ethernet/airoha/airoha_eth.c:695:\t\tdev = airoha_qdma_get_gdm_dev(eth, desc);\ndrivers/net/ethernet/airoha/airoha_eth.c-696-\t\tif (IS_ERR(dev))\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-728-\t\tif (netdev_uses_dsa(netdev)) {\ndrivers/net/ethernet/airoha/airoha_eth.c:729:\t\t\tstruct airoha_gdm_port port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c-730-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-752-\t\tif (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)\ndrivers/net/ethernet/airoha/airoha_eth.c:753:\t\t\tairoha_ppe_check_skb(\u0026eth-\u003eppe-\u003edev, q-\u003eskb, hash,\n\n" }
9/2	2026/08/14 12:07	llm	patch-evaluator	0m Model: gemini-3.1-pro-preview Args: null Results: null Tokens: input: 51618 output: 31 thoughts: 370 Thoughts: Analyzing the WorthFuzzing Criteria Okay, first things first, I've spotted `airoha_eth.c`, `airoha_ppe.c`, and `airoha_npu.c` in the patch. Now, I need to evaluate this against the "WorthFuzzing" criteria. The prompt specifically mentions returning `WorthFuzzing=false` if the patch only contains code paths inaccessible in virtualized environments like QEMU. The key question is: Is `airoha_npu.c` reachable within a QEMU environment? Considering my understanding, no, it's a platform driver tailored for a particular System-on-a-Chip (SoC). This driver necessitates the underlying hardware or at least its accurate emulation, which, I'm pretty sure, QEMU doesn't offer for this specific SoC. I recall Syzkaller has mechanisms for evaluating patches even if they can't be fully fuzzed. It'll attempt to apply the patch, check compilation, or try a fuzzing run to determine if it can find anything. But that's not the primary concern here. The prompt is crystal clear: if it modifies core kernel logic, drivers, or architectures that are reachable, it's worth fuzzing. If it's inaccessible, then it's not. Given my assessment that `airoha_npu.c` is inaccessible in QEMU because it's hardware-specific, it looks like a `WorthFuzzing=false` is the correct determination. However, I should double-check. I'll search the `tools/` and `drivers/net/ethernet/airoha/` directories for any mock or software emulation support for Airoha hardware. This is a crucial step to avoid making any assumptions. If I find something, my assessment might change.
10/2	2026/08/14 12:07	tool	grepper	0m Error: no matches Args: { "Expression": "mock", "PathPrefix": "drivers/net/ethernet/airoha/" } Results: { "error": "no matches" }
11/2	2026/08/14 12:07	llm	patch-evaluator	0m Model: gemini-3.1-pro-preview Args: null Results: null Tokens: input: 52429 output: 97 thoughts: 1547 Thoughts: Unreachable Code in Virtualized Environments Okay, let's break this down. First, no mockups are needed. I'm focusing on reachability in a fuzzing context, and that means virtualized environments like QEMU are the key consideration. Is `CONFIG_NET_AIROHA_NPU` even enabled in syzkaller? Even if it is, this driver, a `platform_driver`, is going to need a corresponding `platform_device` to trigger the `probe` function. Syzkaller might try to create a platform device using `syz_devres` or similar, but even then the `probe` function is going to try to `ioremap` the physical address. And if that hardware isn't actually there, that's just going to crash or fail. Hold on, I thought maybe syzkaller has some kind of pseudo-syscall like `syz_platform_device_add`? No, that doesn't exist. Now, what if it was a PCI driver? No, it's a platform driver, so that's irrelevant. Alright, back to the code, specifically `airoha_npu.c`. ```c static const struct of_device_id of_airoha_npu_match[] = { { .compatible = "airoha,en7581-npu", .data = &en7581_npu_soc_data }, { .compatible = "airoha,an7583-npu", .data = &an7583_npu_soc_data }, { /* sentinel / } }; MODULE_DEVICE_TABLE(of, of_airoha_npu_match); static struct platform_driver airoha_npu_driver = { .probe = airoha_npu_probe, .remove = airoha_npu_remove, .driver = { .name = "airoha-npu", .of_match_table = of_airoha_npu_match, }, }; module_platform_driver(airoha_npu_driver); ``` Okay, it's a standard Device Tree based platform driver. In QEMU, the device tree is provided by the machine type, e.g., 'virt'. And the 'virt' machine type doesn't* include something like "airoha,en7581-npu". Boom. The device won't be instantiated, and `probe` won't be called. It's just not going to happen in these virtualized environments. Could syzkaller use device tree overlays? Even if it did, that `devm_platform_ioremap_resource` call will map a physical address. QEMU isn't emulating Airoha NPU registers at that address. Reading from that address will probably cause a bus error, or return garbage. Either way, it's a dead end. Specifically in `airoha_npu_probe`: ```c err = airoha_npu_run_firmware(dev, base, &res); ``` Inside `airoha_npu_run_firmware`: ```c /* Load rv32 npu firmware / ret = airoha_npu_load_firmware(dev, addr, soc->fw_rv32.name, soc->fw_rv32.max_size); ``` If the firmware isn't in the rootfs, it's going to fail there*, but even if it's there it is writing registers and waiting: ```c if (!airoha_npu_wlan_msg_get(npu, 0, WLAN_FUNC_GET_WAIT_NPU_VERSION, &val, sizeof(val), GFP_KERNEL)) dev_info(dev, "NPU version: %d\n", val); ``` `airoha_npu_wlan_msg_get` then calls `__airoha_npu_send_msg`, where we see: ```c regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr); regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, len); regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val); regmap_
12/2	2026/08/14 12:08	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The patch modifies the Airoha NPU driver, which is a hardware-specific SoC driver for Airoha EN7581/AN7583 routers. This driver requires physical hardware that is not emulated in standard QEMU environments, making the code paths impossible to reach and test during fuzzing.", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch modifies the Airoha NPU driver, which is a hardware-specific SoC driver for Airoha EN7581/AN7583 routers. This driver requires physical hardware that is not emulated in standard QEMU environments, making the code paths impossible to reach and test during fuzzing.", "WorthFuzzing": false }
13/1	2026/08/14 12:08	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies the Airoha NPU driver, which is a hardware-specific SoC driver for Airoha EN7581/AN7583 routers. This driver requires physical hardware that is not emulated in standard QEMU environments, making the code paths impossible to reach and test during fuzzing.",
  "WorthFuzzing": false
}

{
  "PatchDiff": "commit 481cb8faffd51e9feb916f0ca2663fdca11d7924\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Fri Aug 14 12:06:43 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c\nindex b679bed952de3..2ba78bf0e97b4 100644\n--- a/drivers/net/ethernet/airoha/airoha_npu.c\n+++ b/drivers/net/ethernet/airoha/airoha_npu.c\n@@ -5,6 +5,7 @@\n  */\n \n #include \u003clinux/devcoredump.h\u003e\n+#include \u003clinux/dma-mapping.h\u003e\n #include \u003clinux/firmware.h\u003e\n #include \u003clinux/platform_device.h\u003e\n #include \u003clinux/of_net.h\u003e\n@@ -23,6 +24,8 @@\n #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE\t0x200000\n #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE\t0x10000\n #define NPU_DUMP_SIZE\t\t\t\t512\n+/* Maximum mailbox DMA payload (PPE ~28 bytes, WLAN TLV up to 24). */\n+#define AIROHA_NPU_MBOX_SIZE\t\t\t256\n \n #define REG_NPU_LOCAL_SRAM\t\t0x0\n \n@@ -160,23 +163,33 @@ struct wlan_mbox_data {\n \tDECLARE_FLEX_ARRAY(u8, d);\n };\n \n-static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,\n-\t\t\t       void *p, int size)\n+static int __airoha_npu_send_msg(struct airoha_npu *npu, int func_id,\n+\t\t\t\t const void *data, int len, void *reply,\n+\t\t\t\t u16 reply_len)\n {\n-\tu16 core = 0; /* FIXME */\n-\tu32 val, offset = core \u003c\u003c 4;\n+\tstruct airoha_npu_core *core = \u0026npu-\u003ecores[0]; /* FIXME: core */\n \tdma_addr_t dma_addr;\n+\tunsigned int map_len = ALIGN(len, SMP_CACHE_BYTES);\n+\tu32 val, offset = 0;\n \tint ret;\n \n-\tdma_addr = dma_map_single(npu-\u003edev, p, size, DMA_BIDIRECTIONAL);\n+\tif (len \u003c= 0 || len \u003e AIROHA_NPU_MBOX_SIZE)\n+\t\treturn -EINVAL;\n+\n+\tif (reply \u0026\u0026 reply_len \u003e len)\n+\t\treturn -EINVAL;\n+\n+\tspin_lock_bh(\u0026core-\u003elock);\n+\n+\tmemcpy(core-\u003ebuf, data, len);\n+\n+\tdma_addr = dma_map_single(npu-\u003edev, core-\u003ebuf, map_len, DMA_BIDIRECTIONAL);\n \tret = dma_mapping_error(npu-\u003edev, dma_addr);\n \tif (ret)\n-\t\treturn ret;\n-\n-\tspin_lock_bh(\u0026npu-\u003ecores[core].lock);\n+\t\tgoto unlock;\n \n \tregmap_write(npu-\u003eregmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr);\n-\tregmap_write(npu-\u003eregmap, REG_CR_MBQ0_CTRL(1) + offset, size);\n+\tregmap_write(npu-\u003eregmap, REG_CR_MBQ0_CTRL(1) + offset, len);\n \tregmap_read(npu-\u003eregmap, REG_CR_MBQ0_CTRL(2) + offset, \u0026val);\n \tregmap_write(npu-\u003eregmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1);\n \tval = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) | MBOX_MSG_WAIT_RSP;\n@@ -189,13 +202,23 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,\n \tif (!ret \u0026\u0026 FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS)\n \t\tret = -EINVAL;\n \n-\tspin_unlock_bh(\u0026npu-\u003ecores[core].lock);\n+\tdma_unmap_single(npu-\u003edev, dma_addr, map_len, DMA_BIDIRECTIONAL);\n \n-\tdma_unmap_single(npu-\u003edev, dma_addr, size, DMA_BIDIRECTIONAL);\n+\t/* Copy the trailing reply_len bytes of the response. */\n+\tif (!ret \u0026\u0026 reply)\n+\t\tmemcpy(reply, core-\u003ebuf + len - reply_len, reply_len);\n+unlock:\n+\tspin_unlock_bh(\u0026core-\u003elock);\n \n \treturn ret;\n }\n \n+static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,\n+\t\t\t       void *data, int len)\n+{\n+\treturn __airoha_npu_send_msg(npu, func_id, data, len, data, len);\n+}\n+\n static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr,\n \t\t\t\t    const char *fw_name, int fw_max_size)\n {\n@@ -497,9 +520,8 @@ static int airoha_npu_wlan_msg_get(struct airoha_npu *npu, int ifindex,\n \twlan_data-\u003efunc_type = NPU_OP_GET;\n \twlan_data-\u003efunc_id = func_id;\n \n-\terr = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);\n-\tif (!err)\n-\t\tmemcpy(data, wlan_data-\u003ed, data_len);\n+\terr = __airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len,\n+\t\t\t\t    data, data_len);\n \tkfree(wlan_data);\n \n \treturn err;\n@@ -770,6 +792,18 @@ static int airoha_npu_probe(struct platform_device *pdev)\n \tif (err)\n \t\treturn err;\n \n+\tfor (i = 0; i \u003c ARRAY_SIZE(npu-\u003ecores); i++) {\n+\t\tstruct airoha_npu_core *core = \u0026npu-\u003ecores[i];\n+\t\tvoid *raw;\n+\n+\t\traw = devm_kmalloc(dev, AIROHA_NPU_MBOX_SIZE + SMP_CACHE_BYTES,\n+\t\t\t\t   GFP_KERNEL);\n+\t\tif (!raw)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tcore-\u003ebuf = PTR_ALIGN(raw, SMP_CACHE_BYTES);\n+\t}\n+\n \terr = airoha_npu_run_firmware(dev, base, \u0026res);\n \tif (err)\n \t\treturn dev_err_probe(dev, err, \"failed to run npu firmware\\n\");\ndiff --git a/include/linux/soc/airoha/airoha_offload.h b/include/linux/soc/airoha/airoha_offload.h\nindex 7589fccfeef6d..f635766e3dba2 100644\n--- a/include/linux/soc/airoha/airoha_offload.h\n+++ b/include/linux/soc/airoha/airoha_offload.h\n@@ -173,6 +173,7 @@ struct airoha_npu {\n \t\t/* protect concurrent npu memory accesses */\n \t\tspinlock_t lock;\n \t\tstruct work_struct wdt_work;\n+\t\tvoid *buf; /* mailbox DMA bounce buffer */\n \t} cores[NPU_NUM_CORES];\n \n \tint irqs[NPU_NUM_IRQ];\n"
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Airoha NPU driver, which is a hardware-specific SoC driver for Airoha EN7581/AN7583 routers. This driver requires physical hardware that is not emulated in standard QEMU environments, making the code paths impossible to reach and test during fuzzing.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer.
Your job is to review a provided patch series and determine
if it makes functional changes to the kernel that should be fuzzed.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively
use your code access tools to examine the actual source code and confirm any assumptions.

Return WorthFuzzing=false if the patch only contains:
- Modifications to Documentation/, Kconfig files, or code comments.
- Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints.
- Changes to numeric constants or macros that do not functionally alter execution flow.
- Code paths that are impossible to reach in virtualized environments like GCE or QEMU,
  even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim).
- Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed,
  ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU.
- Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove)
  that are executed only during PCI hot-unplug or sysfs driver unbind operations.

If it modifies reachable core kernel logic, drivers, or architectures, use your code search
tools to verify the code can be executed, then return WorthFuzzing=true.

When returning WorthFuzzing=true, you MUST ALSO:
1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols.
   Avoid listing generic hot-path functions to prevent skewed test distributions.
   Prefer non-static, non-inlined API entrypoint functions over internal static helper functions
   (which are inlined by the compiler and do not have distinct symbol addresses).
2. Identify any specific CONFIG_ options required to properly test this new/modified feature.
   Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions.
   Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs
   needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs
   output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

For your convenience, here is the diff of the changes:
commit 481cb8faffd51e9feb916f0ca2663fdca11d7924
Author: syz-cluster <triage@syzkaller.com>
Date:   Fri Aug 14 12:06:43 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c
index b679bed952de3..2ba78bf0e97b4 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.c
+++ b/drivers/net/ethernet/airoha/airoha_npu.c
@@ -5,6 +5,7 @@
  */
 
 #include <linux/devcoredump.h>
+#include <linux/dma-mapping.h>
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
 #include <linux/of_net.h>
@@ -23,6 +24,8 @@
 #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE	0x200000
 #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE	0x10000
 #define NPU_DUMP_SIZE				512
+/* Maximum mailbox DMA payload (PPE ~28 bytes, WLAN TLV up to 24). */
+#define AIROHA_NPU_MBOX_SIZE			256
 
 #define REG_NPU_LOCAL_SRAM		0x0
 
@@ -160,23 +163,33 @@ struct wlan_mbox_data {
 	DECLARE_FLEX_ARRAY(u8, d);
 };
 
-static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
-			       void *p, int size)
+static int __airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
+				 const void *data, int len, void *reply,
+				 u16 reply_len)
 {
-	u16 core = 0; /* FIXME */
-	u32 val, offset = core << 4;
+	struct airoha_npu_core *core = &npu->cores[0]; /* FIXME: core */
 	dma_addr_t dma_addr;
+	unsigned int map_len = ALIGN(len, SMP_CACHE_BYTES);
+	u32 val, offset = 0;
 	int ret;
 
-	dma_addr = dma_map_single(npu->dev, p, size, DMA_BIDIRECTIONAL);
+	if (len <= 0 || len > AIROHA_NPU_MBOX_SIZE)
+		return -EINVAL;
+
+	if (reply && reply_len > len)
+		return -EINVAL;
+
+	spin_lock_bh(&core->lock);
+
+	memcpy(core->buf, data, len);
+
+	dma_addr = dma_map_single(npu->dev, core->buf, map_len, DMA_BIDIRECTIONAL);
 	ret = dma_mapping_error(npu->dev, dma_addr);
 	if (ret)
-		return ret;
-
-	spin_lock_bh(&npu->cores[core].lock);
+		goto unlock;
 
 	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr);
-	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, size);
+	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, len);
 	regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val);
 	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1);
 	val = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) | MBOX_MSG_WAIT_RSP;
@@ -189,13 +202,23 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
 	if (!ret && FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS)
 		ret = -EINVAL;
 
-	spin_unlock_bh(&npu->cores[core].lock);
+	dma_unmap_single(npu->dev, dma_addr, map_len, DMA_BIDIRECTIONAL);
 
-	dma_unmap_single(npu->dev, dma_addr, size, DMA_BIDIRECTIONAL);
+	/* Copy the trailing reply_len bytes of the response. */
+	if (!ret && reply)
+		memcpy(reply, core->buf + len - reply_len, reply_len);
+unlock:
+	spin_unlock_bh(&core->lock);
 
 	return ret;
 }
 
+static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
+			       void *data, int len)
+{
+	return __airoha_npu_send_msg(npu, func_id, data, len, data, len);
+}
+
 static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr,
 				    const char *fw_name, int fw_max_size)
 {
@@ -497,9 +520,8 @@ static int airoha_npu_wlan_msg_get(struct airoha_npu *npu, int ifindex,
 	wlan_data->func_type = NPU_OP_GET;
 	wlan_data->func_id = func_id;
 
-	err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);
-	if (!err)
-		memcpy(data, wlan_data->d, data_len);
+	err = __airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len,
+				    data, data_len);
 	kfree(wlan_data);
 
 	return err;
@@ -770,6 +792,18 @@ static int airoha_npu_probe(struct platform_device *pdev)
 	if (err)
 		return err;
 
+	for (i = 0; i < ARRAY_SIZE(npu->cores); i++) {
+		struct airoha_npu_core *core = &npu->cores[i];
+		void *raw;
+
+		raw = devm_kmalloc(dev, AIROHA_NPU_MBOX_SIZE + SMP_CACHE_BYTES,
+				   GFP_KERNEL);
+		if (!raw)
+			return -ENOMEM;
+
+		core->buf = PTR_ALIGN(raw, SMP_CACHE_BYTES);
+	}
+
 	err = airoha_npu_run_firmware(dev, base, &res);
 	if (err)
 		return dev_err_probe(dev, err, "failed to run npu firmware\n");
diff --git a/include/linux/soc/airoha/airoha_offload.h b/include/linux/soc/airoha/airoha_offload.h
index 7589fccfeef6d..f635766e3dba2 100644
--- a/include/linux/soc/airoha/airoha_offload.h
+++ b/include/linux/soc/airoha/airoha_offload.h
@@ -173,6 +173,7 @@ struct airoha_npu {
 		/* protect concurrent npu memory accesses */
 		spinlock_t lock;
 		struct work_struct wdt_work;
+		void *buf; /* mailbox DMA bounce buffer */
 	} cores[NPU_NUM_CORES];
 
 	int irqs[NPU_NUM_IRQ];

gemini-3.1-pro-preview

							input: 3811
							output: 35
							thoughts: 294

**Analyzing a Patch: Airoha NPU Driver**

Okay, so I'm looking at this patch that's touching `drivers/net/ethernet/airoha/airoha_npu.c` and `include/linux/soc/airoha/airoha_offload.h`. It seems to be modifying how messages are sent to the NPU on Airoha SoCs. The key change is the introduction of a DMA bounce buffer (`core->buf`) and renaming `airoha_npu_send_msg` to `__airoha_npu_send_msg` to use it. The intent here is clearly to resolve potential DMA mapping problems, which makes sense; dealing with stack memory or unaligned memory in DMA operations is always a pain.

But hold on, there's a specific question I need to answer. The prompt says I need to set `WorthFuzzing=false` if the patch concerns a vendor-specific driver that *requires* physical hardware that's *not* emulated in QEMU. That's a critical point. Is this Airoha NPU driver one of *those*?

I need to quickly assess if `airoha_npu` fits this criteria. I know it's under `drivers/net/ethernet/airoha/`, so at least it's a network driver and vendor-specific to Airoha. But is the hardware dependent on a PCIe device, or something else that QEMU might not handle? Time to do a quick search within the kernel tree to get a broader understanding of this `airoha_npu`. I need to figure out if this driver is tied to a specific physical hardware implementation or if it's potentially emulatable.

{
  "Expression": "airoha_npu",
  "PathPrefix": "drivers/net/ethernet/airoha/"
}

{
  "Output": "drivers/net/ethernet/airoha/Makefile=8=airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/ethernet/airoha/airoha_eth.h=645=struct airoha_eth {\n--\ndrivers/net/ethernet/airoha/airoha_eth.h-652-\ndrivers/net/ethernet/airoha/airoha_eth.h:653:\tstruct airoha_npu __rcu *npu;\ndrivers/net/ethernet/airoha/airoha_eth.h-654-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=108=enum {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-112-\ndrivers/net/ethernet/airoha/airoha_npu.c:113:struct airoha_npu_fw {\ndrivers/net/ethernet/airoha/airoha_npu.c-114-\tconst char *name;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-117-\ndrivers/net/ethernet/airoha/airoha_npu.c:118:struct airoha_npu_soc_data {\ndrivers/net/ethernet/airoha/airoha_npu.c:119:\tstruct airoha_npu_fw fw_rv32;\ndrivers/net/ethernet/airoha/airoha_npu.c:120:\tstruct airoha_npu_fw fw_data;\ndrivers/net/ethernet/airoha/airoha_npu.c-121-};\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=159=struct wlan_mbox_data {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-165-\ndrivers/net/ethernet/airoha/airoha_npu.c:166:static int __airoha_npu_send_msg(struct airoha_npu *npu, int func_id,\ndrivers/net/ethernet/airoha/airoha_npu.c-167-\t\t\t\t const void *data, int len, void *reply,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-169-{\ndrivers/net/ethernet/airoha/airoha_npu.c:170:\tstruct airoha_npu_core *core = \u0026npu-\u003ecores[0]; /* FIXME: core */\ndrivers/net/ethernet/airoha/airoha_npu.c-171-\tdma_addr_t dma_addr;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-215-\ndrivers/net/ethernet/airoha/airoha_npu.c:216:static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,\ndrivers/net/ethernet/airoha/airoha_npu.c-217-\t\t\t       void *data, int len)\ndrivers/net/ethernet/airoha/airoha_npu.c-218-{\ndrivers/net/ethernet/airoha/airoha_npu.c:219:\treturn __airoha_npu_send_msg(npu, func_id, data, len, data, len);\ndrivers/net/ethernet/airoha/airoha_npu.c-220-}\ndrivers/net/ethernet/airoha/airoha_npu.c-221-\ndrivers/net/ethernet/airoha/airoha_npu.c:222:static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr,\ndrivers/net/ethernet/airoha/airoha_npu.c-223-\t\t\t\t    const char *fw_name, int fw_max_size)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=246=static int\ndrivers/net/ethernet/airoha/airoha_npu.c:247:airoha_npu_load_firmware_from_dts(struct device *dev, void __iomem *addr,\ndrivers/net/ethernet/airoha/airoha_npu.c-248-\t\t\t\t  void __iomem *base)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-257-\ndrivers/net/ethernet/airoha/airoha_npu.c:258:\tret = airoha_npu_load_firmware(dev, addr, fw_names[0],\ndrivers/net/ethernet/airoha/airoha_npu.c-259-\t\t\t\t       NPU_EN7581_FIRMWARE_RV32_MAX_SIZE);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-262-\ndrivers/net/ethernet/airoha/airoha_npu.c:263:\treturn airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM,\ndrivers/net/ethernet/airoha/airoha_npu.c-264-\t\t\t\t\tfw_names[1],\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-267-\ndrivers/net/ethernet/airoha/airoha_npu.c:268:static int airoha_npu_run_firmware(struct device *dev, void __iomem *base,\ndrivers/net/ethernet/airoha/airoha_npu.c-269-\t\t\t\t   struct resource *res)\ndrivers/net/ethernet/airoha/airoha_npu.c-270-{\ndrivers/net/ethernet/airoha/airoha_npu.c:271:\tconst struct airoha_npu_soc_data *soc;\ndrivers/net/ethernet/airoha/airoha_npu.c-272-\tvoid __iomem *addr;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-286-\tif (of_find_property(dev-\u003eof_node, \"firmware-name\", NULL))\ndrivers/net/ethernet/airoha/airoha_npu.c:287:\t\treturn airoha_npu_load_firmware_from_dts(dev, addr, base);\ndrivers/net/ethernet/airoha/airoha_npu.c-288-\ndrivers/net/ethernet/airoha/airoha_npu.c-289-\t/* Load rv32 npu firmware */\ndrivers/net/ethernet/airoha/airoha_npu.c:290:\tret = airoha_npu_load_firmware(dev, addr, soc-\u003efw_rv32.name,\ndrivers/net/ethernet/airoha/airoha_npu.c-291-\t\t\t\t       soc-\u003efw_rv32.max_size);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-295-\t/* Load data npu firmware */\ndrivers/net/ethernet/airoha/airoha_npu.c:296:\treturn airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM,\ndrivers/net/ethernet/airoha/airoha_npu.c-297-\t\t\t\t\tsoc-\u003efw_data.name,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-300-\ndrivers/net/ethernet/airoha/airoha_npu.c:301:static irqreturn_t airoha_npu_mbox_handler(int irq, void *npu_instance)\ndrivers/net/ethernet/airoha/airoha_npu.c-302-{\ndrivers/net/ethernet/airoha/airoha_npu.c:303:\tstruct airoha_npu *npu = npu_instance;\ndrivers/net/ethernet/airoha/airoha_npu.c-304-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-315-\ndrivers/net/ethernet/airoha/airoha_npu.c:316:static void airoha_npu_wdt_work(struct work_struct *work)\ndrivers/net/ethernet/airoha/airoha_npu.c-317-{\ndrivers/net/ethernet/airoha/airoha_npu.c:318:\tstruct airoha_npu_core *core;\ndrivers/net/ethernet/airoha/airoha_npu.c:319:\tstruct airoha_npu *npu;\ndrivers/net/ethernet/airoha/airoha_npu.c-320-\tvoid *dump;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-323-\ndrivers/net/ethernet/airoha/airoha_npu.c:324:\tcore = container_of(work, struct airoha_npu_core, wdt_work);\ndrivers/net/ethernet/airoha/airoha_npu.c-325-\tnpu = core-\u003enpu;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-338-\ndrivers/net/ethernet/airoha/airoha_npu.c:339:static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance)\ndrivers/net/ethernet/airoha/airoha_npu.c-340-{\ndrivers/net/ethernet/airoha/airoha_npu.c:341:\tstruct airoha_npu_core *core = core_instance;\ndrivers/net/ethernet/airoha/airoha_npu.c:342:\tstruct airoha_npu *npu = core-\u003enpu;\ndrivers/net/ethernet/airoha/airoha_npu.c-343-\tint c = core - \u0026npu-\u003ecores[0];\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-353-\ndrivers/net/ethernet/airoha/airoha_npu.c:354:static int airoha_npu_ppe_init(struct airoha_npu *npu)\ndrivers/net/ethernet/airoha/airoha_npu.c-355-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-367-\ndrivers/net/ethernet/airoha/airoha_npu.c:368:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-369-\t\t\t\t  sizeof(*ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-374-\ndrivers/net/ethernet/airoha/airoha_npu.c:375:static int airoha_npu_ppe_deinit(struct airoha_npu *npu)\ndrivers/net/ethernet/airoha/airoha_npu.c-376-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-386-\ndrivers/net/ethernet/airoha/airoha_npu.c:387:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-388-\t\t\t\t  sizeof(*ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-393-\ndrivers/net/ethernet/airoha/airoha_npu.c:394:static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu *npu,\ndrivers/net/ethernet/airoha/airoha_npu.c-395-\t\t\t\t\t     dma_addr_t foe_addr,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-410-\ndrivers/net/ethernet/airoha/airoha_npu.c:411:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-412-\t\t\t\t  sizeof(*ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-417-\ndrivers/net/ethernet/airoha/airoha_npu.c:418:static int airoha_npu_foe_commit_entry(struct airoha_npu *npu,\ndrivers/net/ethernet/airoha/airoha_npu.c-419-\t\t\t\t       dma_addr_t foe_addr,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-435-\ndrivers/net/ethernet/airoha/airoha_npu.c:436:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-437-\t\t\t\t  sizeof(*ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-444-\ndrivers/net/ethernet/airoha/airoha_npu.c:445:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-446-\t\t\t\t  sizeof(*ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-452-\ndrivers/net/ethernet/airoha/airoha_npu.c:453:static int airoha_npu_ppe_stats_setup(struct airoha_npu *npu,\ndrivers/net/ethernet/airoha/airoha_npu.c-454-\t\t\t\t      dma_addr_t foe_stats_addr,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-467-\ndrivers/net/ethernet/airoha/airoha_npu.c:468:\terr = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,\ndrivers/net/ethernet/airoha/airoha_npu.c-469-\t\t\t\t  sizeof(*ppe_data));\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-483-\ndrivers/net/ethernet/airoha/airoha_npu.c:484:static int airoha_npu_wlan_msg_send(struct airoha_npu *npu, int ifindex,\ndrivers/net/ethernet/airoha/airoha_npu.c:485:\t\t\t\t    enum airoha_npu_wlan_set_cmd func_id,\ndrivers/net/ethernet/airoha/airoha_npu.c-486-\t\t\t\t    void *data, int data_len, gfp_t gfp)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-500-\ndrivers/net/ethernet/airoha/airoha_npu.c:501:\terr = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);\ndrivers/net/ethernet/airoha/airoha_npu.c-502-\tkfree(wlan_data);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-506-\ndrivers/net/ethernet/airoha/airoha_npu.c:507:static int airoha_npu_wlan_msg_get(struct airoha_npu *npu, int ifindex,\ndrivers/net/ethernet/airoha/airoha_npu.c:508:\t\t\t\t   enum airoha_npu_wlan_get_cmd func_id,\ndrivers/net/ethernet/airoha/airoha_npu.c-509-\t\t\t\t   void *data, int data_len, gfp_t gfp)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-522-\ndrivers/net/ethernet/airoha/airoha_npu.c:523:\terr = __airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len,\ndrivers/net/ethernet/airoha/airoha_npu.c-524-\t\t\t\t    data, data_len);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=530=static int\ndrivers/net/ethernet/airoha/airoha_npu.c:531:airoha_npu_wlan_set_reserved_memory(struct airoha_npu *npu,\ndrivers/net/ethernet/airoha/airoha_npu.c-532-\t\t\t\t    int ifindex, const char *name,\ndrivers/net/ethernet/airoha/airoha_npu.c:533:\t\t\t\t    enum airoha_npu_wlan_set_cmd func_id)\ndrivers/net/ethernet/airoha/airoha_npu.c-534-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-545-\tval = res.start;\ndrivers/net/ethernet/airoha/airoha_npu.c:546:\treturn airoha_npu_wlan_msg_send(npu, ifindex, func_id, \u0026val,\ndrivers/net/ethernet/airoha/airoha_npu.c-547-\t\t\t\t\tsizeof(val), GFP_KERNEL);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-549-\ndrivers/net/ethernet/airoha/airoha_npu.c:550:static int airoha_npu_wlan_init_memory(struct airoha_npu *npu)\ndrivers/net/ethernet/airoha/airoha_npu.c-551-{\ndrivers/net/ethernet/airoha/airoha_npu.c:552:\tenum airoha_npu_wlan_set_cmd cmd = WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU;\ndrivers/net/ethernet/airoha/airoha_npu.c-553-\tu32 val = 0;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-555-\ndrivers/net/ethernet/airoha/airoha_npu.c:556:\terr = airoha_npu_wlan_msg_send(npu, 1, cmd, \u0026val, sizeof(val),\ndrivers/net/ethernet/airoha/airoha_npu.c-557-\t\t\t\t       GFP_KERNEL);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-561-\tcmd = WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR;\ndrivers/net/ethernet/airoha/airoha_npu.c:562:\terr = airoha_npu_wlan_set_reserved_memory(npu, 0, \"tx-bufid\", cmd);\ndrivers/net/ethernet/airoha/airoha_npu.c-563-\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-566-\tcmd = WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR;\ndrivers/net/ethernet/airoha/airoha_npu.c:567:\terr = airoha_npu_wlan_set_reserved_memory(npu, 0, \"pkt\", cmd);\ndrivers/net/ethernet/airoha/airoha_npu.c-568-\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-571-\tcmd = WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR;\ndrivers/net/ethernet/airoha/airoha_npu.c:572:\terr = airoha_npu_wlan_set_reserved_memory(npu, 0, \"tx-pkt\", cmd);\ndrivers/net/ethernet/airoha/airoha_npu.c-573-\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-578-\t\tcmd = WLAN_FUNC_SET_WAIT_DRAM_BA_NODE_ADDR;\ndrivers/net/ethernet/airoha/airoha_npu.c:579:\t\terr = airoha_npu_wlan_set_reserved_memory(npu, 0, \"ba\", cmd);\ndrivers/net/ethernet/airoha/airoha_npu.c-580-\t\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-584-\tcmd = WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU;\ndrivers/net/ethernet/airoha/airoha_npu.c:585:\treturn airoha_npu_wlan_msg_send(npu, 0, cmd, \u0026val, sizeof(val),\ndrivers/net/ethernet/airoha/airoha_npu.c-586-\t\t\t\t\tGFP_KERNEL);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-588-\ndrivers/net/ethernet/airoha/airoha_npu.c:589:static u32 airoha_npu_wlan_queue_addr_get(struct airoha_npu *npu, int qid,\ndrivers/net/ethernet/airoha/airoha_npu.c-590-\t\t\t\t\t  bool xmit)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-597-\ndrivers/net/ethernet/airoha/airoha_npu.c:598:static void airoha_npu_wlan_irq_status_set(struct airoha_npu *npu, u32 val)\ndrivers/net/ethernet/airoha/airoha_npu.c-599-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-602-\ndrivers/net/ethernet/airoha/airoha_npu.c:603:static u32 airoha_npu_wlan_irq_status_get(struct airoha_npu *npu, int q)\ndrivers/net/ethernet/airoha/airoha_npu.c-604-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-610-\ndrivers/net/ethernet/airoha/airoha_npu.c:611:static void airoha_npu_wlan_irq_enable(struct airoha_npu *npu, int q)\ndrivers/net/ethernet/airoha/airoha_npu.c-612-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-615-\ndrivers/net/ethernet/airoha/airoha_npu.c:616:static void airoha_npu_wlan_irq_disable(struct airoha_npu *npu, int q)\ndrivers/net/ethernet/airoha/airoha_npu.c-617-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-620-\ndrivers/net/ethernet/airoha/airoha_npu.c:621:struct airoha_npu *airoha_npu_get(struct device *dev)\ndrivers/net/ethernet/airoha/airoha_npu.c-622-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-624-\tstruct device_node *np;\ndrivers/net/ethernet/airoha/airoha_npu.c:625:\tstruct airoha_npu *npu;\ndrivers/net/ethernet/airoha/airoha_npu.c-626-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-668-}\ndrivers/net/ethernet/airoha/airoha_npu.c:669:EXPORT_SYMBOL_GPL(airoha_npu_get);\ndrivers/net/ethernet/airoha/airoha_npu.c-670-\ndrivers/net/ethernet/airoha/airoha_npu.c:671:void airoha_npu_put(struct airoha_npu *npu)\ndrivers/net/ethernet/airoha/airoha_npu.c-672-{\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-675-}\ndrivers/net/ethernet/airoha/airoha_npu.c:676:EXPORT_SYMBOL_GPL(airoha_npu_put);\ndrivers/net/ethernet/airoha/airoha_npu.c-677-\ndrivers/net/ethernet/airoha/airoha_npu.c:678:static const struct airoha_npu_soc_data en7581_npu_soc_data = {\ndrivers/net/ethernet/airoha/airoha_npu.c-679-\t.fw_rv32 = {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-688-\ndrivers/net/ethernet/airoha/airoha_npu.c:689:static const struct airoha_npu_soc_data an7583_npu_soc_data = {\ndrivers/net/ethernet/airoha/airoha_npu.c-690-\t.fw_rv32 = {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-699-\ndrivers/net/ethernet/airoha/airoha_npu.c:700:static const struct of_device_id of_airoha_npu_match[] = {\ndrivers/net/ethernet/airoha/airoha_npu.c-701-\t{ .compatible = \"airoha,en7581-npu\", .data = \u0026en7581_npu_soc_data },\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-704-};\ndrivers/net/ethernet/airoha/airoha_npu.c:705:MODULE_DEVICE_TABLE(of, of_airoha_npu_match);\ndrivers/net/ethernet/airoha/airoha_npu.c-706-\ndrivers/net/ethernet/airoha/airoha_npu.c=707=static const struct regmap_config regmap_config = {\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-714-\ndrivers/net/ethernet/airoha/airoha_npu.c:715:static int airoha_npu_probe(struct platform_device *pdev)\ndrivers/net/ethernet/airoha/airoha_npu.c-716-{\ndrivers/net/ethernet/airoha/airoha_npu.c-717-\tstruct device *dev = \u0026pdev-\u003edev;\ndrivers/net/ethernet/airoha/airoha_npu.c:718:\tstruct airoha_npu *npu;\ndrivers/net/ethernet/airoha/airoha_npu.c-719-\tstruct resource res;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-732-\tnpu-\u003edev = dev;\ndrivers/net/ethernet/airoha/airoha_npu.c:733:\tnpu-\u003eops.ppe_init = airoha_npu_ppe_init;\ndrivers/net/ethernet/airoha/airoha_npu.c:734:\tnpu-\u003eops.ppe_deinit = airoha_npu_ppe_deinit;\ndrivers/net/ethernet/airoha/airoha_npu.c:735:\tnpu-\u003eops.ppe_init_stats = airoha_npu_ppe_stats_setup;\ndrivers/net/ethernet/airoha/airoha_npu.c:736:\tnpu-\u003eops.ppe_flush_sram_entries = airoha_npu_ppe_flush_sram_entries;\ndrivers/net/ethernet/airoha/airoha_npu.c:737:\tnpu-\u003eops.ppe_foe_commit_entry = airoha_npu_foe_commit_entry;\ndrivers/net/ethernet/airoha/airoha_npu.c:738:\tnpu-\u003eops.wlan_init_reserved_memory = airoha_npu_wlan_init_memory;\ndrivers/net/ethernet/airoha/airoha_npu.c:739:\tnpu-\u003eops.wlan_send_msg = airoha_npu_wlan_msg_send;\ndrivers/net/ethernet/airoha/airoha_npu.c:740:\tnpu-\u003eops.wlan_get_msg = airoha_npu_wlan_msg_get;\ndrivers/net/ethernet/airoha/airoha_npu.c:741:\tnpu-\u003eops.wlan_get_queue_addr = airoha_npu_wlan_queue_addr_get;\ndrivers/net/ethernet/airoha/airoha_npu.c:742:\tnpu-\u003eops.wlan_set_irq_status = airoha_npu_wlan_irq_status_set;\ndrivers/net/ethernet/airoha/airoha_npu.c:743:\tnpu-\u003eops.wlan_get_irq_status = airoha_npu_wlan_irq_status_get;\ndrivers/net/ethernet/airoha/airoha_npu.c:744:\tnpu-\u003eops.wlan_enable_irq = airoha_npu_wlan_irq_enable;\ndrivers/net/ethernet/airoha/airoha_npu.c:745:\tnpu-\u003eops.wlan_disable_irq = airoha_npu_wlan_irq_disable;\ndrivers/net/ethernet/airoha/airoha_npu.c-746-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-758-\ndrivers/net/ethernet/airoha/airoha_npu.c:759:\terr = devm_request_irq(dev, irq, airoha_npu_mbox_handler,\ndrivers/net/ethernet/airoha/airoha_npu.c-760-\t\t\t       IRQF_SHARED, \"airoha-npu-mbox\", npu);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-764-\tfor (i = 0; i \u003c ARRAY_SIZE(npu-\u003ecores); i++) {\ndrivers/net/ethernet/airoha/airoha_npu.c:765:\t\tstruct airoha_npu_core *core = \u0026npu-\u003ecores[i];\ndrivers/net/ethernet/airoha/airoha_npu.c-766-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-773-\ndrivers/net/ethernet/airoha/airoha_npu.c:774:\t\terr = devm_request_irq(dev, irq, airoha_npu_wdt_handler,\ndrivers/net/ethernet/airoha/airoha_npu.c-775-\t\t\t\t       IRQF_SHARED, \"airoha-npu-wdt\", core);\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-778-\ndrivers/net/ethernet/airoha/airoha_npu.c:779:\t\tINIT_WORK(\u0026core-\u003ewdt_work, airoha_npu_wdt_work);\ndrivers/net/ethernet/airoha/airoha_npu.c-780-\t}\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-795-\tfor (i = 0; i \u003c ARRAY_SIZE(npu-\u003ecores); i++) {\ndrivers/net/ethernet/airoha/airoha_npu.c:796:\t\tstruct airoha_npu_core *core = \u0026npu-\u003ecores[i];\ndrivers/net/ethernet/airoha/airoha_npu.c-797-\t\tvoid *raw;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-806-\ndrivers/net/ethernet/airoha/airoha_npu.c:807:\terr = airoha_npu_run_firmware(dev, base, \u0026res);\ndrivers/net/ethernet/airoha/airoha_npu.c-808-\tif (err)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-827-\ndrivers/net/ethernet/airoha/airoha_npu.c:828:\tif (!airoha_npu_wlan_msg_get(npu, 0, WLAN_FUNC_GET_WAIT_NPU_VERSION,\ndrivers/net/ethernet/airoha/airoha_npu.c-829-\t\t\t\t     \u0026val, sizeof(val), GFP_KERNEL))\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-837-\ndrivers/net/ethernet/airoha/airoha_npu.c:838:static void airoha_npu_remove(struct platform_device *pdev)\ndrivers/net/ethernet/airoha/airoha_npu.c-839-{\ndrivers/net/ethernet/airoha/airoha_npu.c:840:\tstruct airoha_npu *npu = platform_get_drvdata(pdev);\ndrivers/net/ethernet/airoha/airoha_npu.c-841-\tint i;\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-846-\ndrivers/net/ethernet/airoha/airoha_npu.c:847:static struct platform_driver airoha_npu_driver = {\ndrivers/net/ethernet/airoha/airoha_npu.c:848:\t.probe = airoha_npu_probe,\ndrivers/net/ethernet/airoha/airoha_npu.c:849:\t.remove = airoha_npu_remove,\ndrivers/net/ethernet/airoha/airoha_npu.c-850-\t.driver = {\ndrivers/net/ethernet/airoha/airoha_npu.c-851-\t\t.name = \"airoha-npu\",\ndrivers/net/ethernet/airoha/airoha_npu.c:852:\t\t.of_match_table = of_airoha_npu_match,\ndrivers/net/ethernet/airoha/airoha_npu.c-853-\t},\ndrivers/net/ethernet/airoha/airoha_npu.c-854-};\ndrivers/net/ethernet/airoha/airoha_npu.c:855:module_platform_driver(airoha_npu_driver);\ndrivers/net/ethernet/airoha/airoha_npu.c-856-\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=607=static void airoha_ppe_foe_flow_stat_entry_reset(struct airoha_ppe *ppe,\ndrivers/net/ethernet/airoha/airoha_ppe.c:608:\t\t\t\t\t\t struct airoha_npu *npu,\ndrivers/net/ethernet/airoha/airoha_ppe.c-609-\t\t\t\t\t\t int index)\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=615=static void airoha_ppe_foe_flow_stats_reset(struct airoha_ppe *ppe,\ndrivers/net/ethernet/airoha/airoha_ppe.c:616:\t\t\t\t\t    struct airoha_npu *npu)\ndrivers/net/ethernet/airoha/airoha_ppe.c-617-{\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=628=static void airoha_ppe_foe_flow_stats_update(struct airoha_ppe *ppe,\ndrivers/net/ethernet/airoha/airoha_ppe.c:629:\t\t\t\t\t     struct airoha_npu *npu,\ndrivers/net/ethernet/airoha/airoha_ppe.c-630-\t\t\t\t\t     struct airoha_foe_entry *hwe,\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=765=static int airoha_ppe_foe_commit_entry(struct airoha_ppe *ppe,\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-772-\tstruct airoha_eth *eth = ppe-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_ppe.c:773:\tstruct airoha_npu *npu;\ndrivers/net/ethernet/airoha/airoha_ppe.c-774-\tint err = 0;\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=1301=void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1305-\tint ppe_num_stats_entries;\ndrivers/net/ethernet/airoha/airoha_ppe.c:1306:\tstruct airoha_npu *npu;\ndrivers/net/ethernet/airoha/airoha_ppe.c-1307-\tu32 index;\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=1379=static int airoha_ppe_flush_sram_entries(struct airoha_ppe *ppe)\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1396-\ndrivers/net/ethernet/airoha/airoha_ppe.c:1397:static struct airoha_npu *airoha_ppe_npu_get(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_ppe.c-1398-{\ndrivers/net/ethernet/airoha/airoha_ppe.c:1399:\tstruct airoha_npu *npu = airoha_npu_get(eth-\u003edev);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1400-\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1402-\t\trequest_module(\"airoha-npu\");\ndrivers/net/ethernet/airoha/airoha_ppe.c:1403:\t\tnpu = airoha_npu_get(eth-\u003edev);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1404-\t}\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=1432=static int airoha_ppe_offload_setup(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_ppe.c-1433-{\ndrivers/net/ethernet/airoha/airoha_ppe.c:1434:\tstruct airoha_npu *npu = airoha_ppe_npu_get(eth);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1435-\tstruct airoha_ppe *ppe = eth-\u003eppe;\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1466-error_npu_put:\ndrivers/net/ethernet/airoha/airoha_ppe.c:1467:\tairoha_npu_put(npu);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1468-\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=1662=void airoha_ppe_deinit(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_ppe.c-1663-{\ndrivers/net/ethernet/airoha/airoha_ppe.c:1664:\tstruct airoha_npu *npu;\ndrivers/net/ethernet/airoha/airoha_ppe.c-1665-\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c-1672-\t\tnpu-\u003eops.ppe_deinit(npu);\ndrivers/net/ethernet/airoha/airoha_ppe.c:1673:\t\tairoha_npu_put(npu);\ndrivers/net/ethernet/airoha/airoha_ppe.c-1674-\t}\n"
}

gemini-3.1-pro-preview

							input: 15083
							output: 32
							thoughts: 617

**My Assessment of the Airoha NPU Driver and WorthFuzzing**

Okay, so I'm looking at this `airoha_npu` driver, part of the Airoha Ethernet driver suite. It seems to be an NPU driver specifically for Airoha's EN7581 SoCs. The question is, is this something that requires real hardware and is therefore a no-go for standard QEMU emulation?

The EN7581 *is* a router/gateway SoC, confirming that it's probably vendor-specific silicon. The code's in `drivers/net/ethernet/airoha/airoha_npu.c`. The prompt specifically mentions skipping vendor-specific PCIe switch, SmartNIC, or GPU drivers that need real PCIe hardware. I need to figure out if this fits that description.

A quick check of the source reveals it's registered as a `platform_driver`. That means it's an IP block *within* the SoC, and not a PCIe device, which changes things a bit! Platform drivers are often SoC-specific, relying on specific device tree nodes and memory-mapped I/O regions. The likelihood of standard QEMU perfectly emulating the EN7581's platform specifics is vanishingly small, unless there's some obscure machine type for it.

However, Syzkaller *can* sometimes get at platform drivers. It can inject device tree nodes, use `syz_mount_image`, or fake platform devices. But here's the kicker: `airoha_npu_probe` does `devm_platform_ioremap_resource(pdev, 0)`, which means it's directly accessing hardware registers through MMIO. If the hardware isn't emulated, that's just going to crash or fail the probe.

Now, while Syzkaller can sometimes poke around via `/dev/` nodes or pseudo-device frameworks, direct MMIO on a platform driver without emulation is a dead end. Unless, of course, there's some way Syzkaller can instantiate this driver, but in this case, I'd need an emulator of the hardware. The key question is whether there's existing Syzkaller support for Airoha's NPU. I need to research this before I make a final call, but my gut tells me it's likely not fuzzable without that.

{
  "Expression": "airoha",
  "PathPrefix": "drivers/net/ethernet/airoha/"
}

{
  "Output": "\nFull output is too long, showing 500 out of 3689 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/airoha/Makefile-5-\ndrivers/net/ethernet/airoha/Makefile:6:obj-$(CONFIG_NET_AIROHA) += airoha-eth.o\ndrivers/net/ethernet/airoha/Makefile:7:airoha-eth-y := airoha_eth.o airoha_ppe.o\ndrivers/net/ethernet/airoha/Makefile:8:airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-16-\ndrivers/net/ethernet/airoha/airoha_eth.c:17:#include \"airoha_regs.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c:18:#include \"airoha_eth.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c-19-\ndrivers/net/ethernet/airoha/airoha_eth.c:20:u32 airoha_rr(void __iomem *base, u32 offset)\ndrivers/net/ethernet/airoha/airoha_eth.c-21-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-24-\ndrivers/net/ethernet/airoha/airoha_eth.c:25:void airoha_wr(void __iomem *base, u32 offset, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-26-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-29-\ndrivers/net/ethernet/airoha/airoha_eth.c:30:u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-31-{\ndrivers/net/ethernet/airoha/airoha_eth.c:32:\tval |= (airoha_rr(base, offset) \u0026 ~mask);\ndrivers/net/ethernet/airoha/airoha_eth.c:33:\tairoha_wr(base, offset, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-34-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-37-\ndrivers/net/ethernet/airoha/airoha_eth.c:38:static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-39-\t\t\t\t    int index, u32 clear, u32 set)\ndrivers/net/ethernet/airoha/airoha_eth.c-40-{\ndrivers/net/ethernet/airoha/airoha_eth.c:41:\tstruct airoha_qdma *qdma = irq_bank-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-42-\tint bank = irq_bank - \u0026qdma-\u003eirq_banks[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-51-\tirq_bank-\u003eirqmask[index] |= set;\ndrivers/net/ethernet/airoha/airoha_eth.c:52:\tairoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),\ndrivers/net/ethernet/airoha/airoha_eth.c-53-\t\t       irq_bank-\u003eirqmask[index]);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-56-\t */\ndrivers/net/ethernet/airoha/airoha_eth.c:57:\tairoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));\ndrivers/net/ethernet/airoha/airoha_eth.c-58-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-61-\ndrivers/net/ethernet/airoha/airoha_eth.c:62:static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-63-\t\t\t\t   int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-64-{\ndrivers/net/ethernet/airoha/airoha_eth.c:65:\tairoha_qdma_set_irqmask(irq_bank, index, 0, mask);\ndrivers/net/ethernet/airoha/airoha_eth.c-66-}\ndrivers/net/ethernet/airoha/airoha_eth.c-67-\ndrivers/net/ethernet/airoha/airoha_eth.c:68:static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-69-\t\t\t\t    int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-70-{\ndrivers/net/ethernet/airoha/airoha_eth.c:71:\tairoha_qdma_set_irqmask(irq_bank, index, mask, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-72-}\ndrivers/net/ethernet/airoha/airoha_eth.c-73-\ndrivers/net/ethernet/airoha/airoha_eth.c:74:static int airoha_set_macaddr(struct airoha_gdm_dev *dev, const u8 *addr)\ndrivers/net/ethernet/airoha/airoha_eth.c-75-{\ndrivers/net/ethernet/airoha/airoha_eth.c-76-\tu8 ref_addr[ETH_ALEN] __aligned(2);\ndrivers/net/ethernet/airoha/airoha_eth.c:77:\tstruct airoha_eth *eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-78-\tu32 reg, val, lmin, lmax;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-85-\tfor (i = 0; i \u003c ARRAY_SIZE(eth-\u003eports); i++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:86:\t\tstruct airoha_gdm_port *port = eth-\u003eports[i];\ndrivers/net/ethernet/airoha/airoha_eth.c-87-\t\tint j;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-92-\t\tfor (j = 0; j \u003c ARRAY_SIZE(port-\u003edevs); j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:93:\t\t\tstruct airoha_gdm_dev *iter_dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-94-\t\t\tstruct net_device *netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-99-\ndrivers/net/ethernet/airoha/airoha_eth.c:100:\t\t\tif (airoha_is_lan_gdm_dev(iter_dev) !=\ndrivers/net/ethernet/airoha/airoha_eth.c:101:\t\t\t    airoha_is_lan_gdm_dev(dev))\ndrivers/net/ethernet/airoha/airoha_eth.c-102-\t\t\t\tcontinue;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-133-\ndrivers/net/ethernet/airoha/airoha_eth.c:134:\treg = airoha_is_lan_gdm_dev(dev) ? REG_FE_LAN_MAC_H : REG_FE_WAN_MAC_H;\ndrivers/net/ethernet/airoha/airoha_eth.c-135-\tval = (addr[0] \u003c\u003c 16) | (addr[1] \u003c\u003c 8) | addr[2];\ndrivers/net/ethernet/airoha/airoha_eth.c:136:\tairoha_fe_wr(eth, reg, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-137-\ndrivers/net/ethernet/airoha/airoha_eth.c:138:\tairoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), lmin);\ndrivers/net/ethernet/airoha/airoha_eth.c:139:\tairoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), lmax);\ndrivers/net/ethernet/airoha/airoha_eth.c-140-\ndrivers/net/ethernet/airoha/airoha_eth.c:141:\tairoha_ppe_init_upd_mem(dev, addr);\ndrivers/net/ethernet/airoha/airoha_eth.c-142-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-145-\ndrivers/net/ethernet/airoha/airoha_eth.c:146:static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,\ndrivers/net/ethernet/airoha/airoha_eth.c-147-\t\t\t\t\tu32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-148-{\ndrivers/net/ethernet/airoha/airoha_eth.c:149:\tairoha_fe_rmw(eth, addr, GDM_OCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-150-\t\t      FIELD_PREP(GDM_OCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:151:\tairoha_fe_rmw(eth, addr, GDM_MCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-152-\t\t      FIELD_PREP(GDM_MCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:153:\tairoha_fe_rmw(eth, addr, GDM_BCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-154-\t\t      FIELD_PREP(GDM_BCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:155:\tairoha_fe_rmw(eth, addr, GDM_UCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-156-\t\t      FIELD_PREP(GDM_UCFQ_MASK, val));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-158-\ndrivers/net/ethernet/airoha/airoha_eth.c:159:static int airoha_set_vip_for_gdm_port(struct airoha_gdm_dev *dev, bool enable)\ndrivers/net/ethernet/airoha/airoha_eth.c-160-{\ndrivers/net/ethernet/airoha/airoha_eth.c:161:\tstruct airoha_gdm_port *port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c:162:\tstruct airoha_eth *eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-163-\tu32 vip_port;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-166-\tif (enable) {\ndrivers/net/ethernet/airoha/airoha_eth.c:167:\t\tairoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:168:\t\tairoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-169-\t} else {\ndrivers/net/ethernet/airoha/airoha_eth.c:170:\t\tairoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:171:\t\tairoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-172-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-176-\ndrivers/net/ethernet/airoha/airoha_eth.c:177:static void airoha_fe_maccr_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-178-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-181-\tfor (p = 1; p \u003c= ARRAY_SIZE(eth-\u003eports); p++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:182:\t\tairoha_fe_set(eth, REG_GDM_FWD_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-183-\t\t\t      GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-184-\t\t\t      GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:185:\t\tairoha_fe_rmw(eth, REG_GDM_LEN_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-186-\t\t\t      GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-190-\ndrivers/net/ethernet/airoha/airoha_eth.c:191:\tairoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-192-\t\t      FIELD_PREP(CDM_VLAN_MASK, 0x8100));\ndrivers/net/ethernet/airoha/airoha_eth.c-193-\ndrivers/net/ethernet/airoha/airoha_eth.c:194:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD);\ndrivers/net/ethernet/airoha/airoha_eth.c-195-}\ndrivers/net/ethernet/airoha/airoha_eth.c-196-\ndrivers/net/ethernet/airoha/airoha_eth.c:197:static void airoha_fe_vip_setup(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-198-{\ndrivers/net/ethernet/airoha/airoha_eth.c:199:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC);\ndrivers/net/ethernet/airoha/airoha_eth.c:200:\tairoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-201-\ndrivers/net/ethernet/airoha/airoha_eth.c:202:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:203:\tairoha_fe_wr(eth, REG_FE_VIP_EN(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-204-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-206-\ndrivers/net/ethernet/airoha/airoha_eth.c:207:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:208:\tairoha_fe_wr(eth, REG_FE_VIP_EN(6),\ndrivers/net/ethernet/airoha/airoha_eth.c-209-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-211-\ndrivers/net/ethernet/airoha/airoha_eth.c:212:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:213:\tairoha_fe_wr(eth, REG_FE_VIP_EN(7),\ndrivers/net/ethernet/airoha/airoha_eth.c-214-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-217-\t/* BOOTP (0x43) */\ndrivers/net/ethernet/airoha/airoha_eth.c:218:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43);\ndrivers/net/ethernet/airoha/airoha_eth.c:219:\tairoha_fe_wr(eth, REG_FE_VIP_EN(8),\ndrivers/net/ethernet/airoha/airoha_eth.c-220-\t\t     PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-223-\t/* BOOTP (0x44) */\ndrivers/net/ethernet/airoha/airoha_eth.c:224:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44);\ndrivers/net/ethernet/airoha/airoha_eth.c:225:\tairoha_fe_wr(eth, REG_FE_VIP_EN(9),\ndrivers/net/ethernet/airoha/airoha_eth.c-226-\t\t     PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-229-\t/* ISAKMP */\ndrivers/net/ethernet/airoha/airoha_eth.c:230:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4);\ndrivers/net/ethernet/airoha/airoha_eth.c:231:\tairoha_fe_wr(eth, REG_FE_VIP_EN(10),\ndrivers/net/ethernet/airoha/airoha_eth.c-232-\t\t     PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-234-\ndrivers/net/ethernet/airoha/airoha_eth.c:235:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP);\ndrivers/net/ethernet/airoha/airoha_eth.c:236:\tairoha_fe_wr(eth, REG_FE_VIP_EN(11),\ndrivers/net/ethernet/airoha/airoha_eth.c-237-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-240-\t/* DHCPv6 */\ndrivers/net/ethernet/airoha/airoha_eth.c:241:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223);\ndrivers/net/ethernet/airoha/airoha_eth.c:242:\tairoha_fe_wr(eth, REG_FE_VIP_EN(12),\ndrivers/net/ethernet/airoha/airoha_eth.c-243-\t\t     PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-245-\ndrivers/net/ethernet/airoha/airoha_eth.c:246:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:247:\tairoha_fe_wr(eth, REG_FE_VIP_EN(19),\ndrivers/net/ethernet/airoha/airoha_eth.c-248-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-251-\t/* ETH-\u003eETH_P_1905 (0x893a) */\ndrivers/net/ethernet/airoha/airoha_eth.c:252:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a);\ndrivers/net/ethernet/airoha/airoha_eth.c:253:\tairoha_fe_wr(eth, REG_FE_VIP_EN(20),\ndrivers/net/ethernet/airoha/airoha_eth.c-254-\t\t     PATN_FCPU_EN_MASK | PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-255-\ndrivers/net/ethernet/airoha/airoha_eth.c:256:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP);\ndrivers/net/ethernet/airoha/airoha_eth.c:257:\tairoha_fe_wr(eth, REG_FE_VIP_EN(21),\ndrivers/net/ethernet/airoha/airoha_eth.c-258-\t\t     PATN_FCPU_EN_MASK | PATN_EN_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-260-\ndrivers/net/ethernet/airoha/airoha_eth.c:261:static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-262-\t\t\t\t\t     u32 port, u32 queue)\ndrivers/net/ethernet/airoha/airoha_eth.c-263-{\ndrivers/net/ethernet/airoha/airoha_eth.c:264:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-265-\t\t      PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-268-\ndrivers/net/ethernet/airoha/airoha_eth.c:269:\treturn airoha_fe_get(eth, REG_FE_PSE_QUEUE_CFG_VAL,\ndrivers/net/ethernet/airoha/airoha_eth.c-270-\t\t\t     PSE_CFG_OQ_RSV_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-272-\ndrivers/net/ethernet/airoha/airoha_eth.c:273:static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-274-\t\t\t\t\t      u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-275-{\ndrivers/net/ethernet/airoha/airoha_eth.c:276:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-277-\t\t      FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:278:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-279-\t\t      PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-285-\ndrivers/net/ethernet/airoha/airoha_eth.c:286:static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-287-{\ndrivers/net/ethernet/airoha/airoha_eth.c:288:\treturn airoha_fe_get(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-289-}\ndrivers/net/ethernet/airoha/airoha_eth.c-290-\ndrivers/net/ethernet/airoha/airoha_eth.c:291:static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-292-\t\t\t\t    u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-293-{\ndrivers/net/ethernet/airoha/airoha_eth.c:294:\tu32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);\ndrivers/net/ethernet/airoha/airoha_eth.c-295-\tu32 tmp, all_rsv, fq_limit;\ndrivers/net/ethernet/airoha/airoha_eth.c-296-\ndrivers/net/ethernet/airoha/airoha_eth.c:297:\tairoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-298-\ndrivers/net/ethernet/airoha/airoha_eth.c-299-\t/* modify all rsv */\ndrivers/net/ethernet/airoha/airoha_eth.c:300:\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-301-\tall_rsv += (val - orig_val);\ndrivers/net/ethernet/airoha/airoha_eth.c:302:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-303-\t\t      FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-305-\t/* modify hthd */\ndrivers/net/ethernet/airoha/airoha_eth.c:306:\tfq_limit = airoha_fe_get(eth, PSE_FQ_CFG, PSE_FQ_LIMIT_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-307-\ttmp = fq_limit - all_rsv - 0x20;\ndrivers/net/ethernet/airoha/airoha_eth.c:308:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-309-\t\t      PSE_SHARE_USED_HTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-312-\ttmp = fq_limit - all_rsv - 0x100;\ndrivers/net/ethernet/airoha/airoha_eth.c:313:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-314-\t\t      PSE_SHARE_USED_MTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-316-\ttmp = (3 * tmp) \u003e\u003e 2;\ndrivers/net/ethernet/airoha/airoha_eth.c:317:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET,\ndrivers/net/ethernet/airoha/airoha_eth.c-318-\t\t      PSE_SHARE_USED_LTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-323-\ndrivers/net/ethernet/airoha/airoha_eth.c:324:static void airoha_fe_pse_ports_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-325-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-340-\ndrivers/net/ethernet/airoha/airoha_eth.c:341:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-342-\t\tu32 all_rsv;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-344-\t\t/* hw misses PPE2 oq rsv */\ndrivers/net/ethernet/airoha/airoha_eth.c:345:\t\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-346-\t\tall_rsv += PSE_RSV_PAGES *\ndrivers/net/ethernet/airoha/airoha_eth.c-347-\t\t\t   pse_port_num_queues[FE_PSE_PORT_PPE2];\ndrivers/net/ethernet/airoha/airoha_eth.c:348:\t\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-349-\t\t\t      FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-353-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:354:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-355-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-357-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:358:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-359-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-361-\tfor (q = 6; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:362:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-363-\t/* GDM3 */\ndrivers/net/ethernet/airoha/airoha_eth.c-364-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM3]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:365:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-366-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-369-\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE1] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:370:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-371-\t\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c-372-\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:373:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-374-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-376-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:377:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-378-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-380-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:381:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-382-\t/* CDM4 */\ndrivers/net/ethernet/airoha/airoha_eth.c-383-\tfor (q = 4; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:384:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-385-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c:386:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-387-\t\t/* PPE2 */\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-389-\t\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE2] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:390:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-391-\t\t\t\t\t\t\t q,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-393-\t\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:394:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-395-\t\t\t\t\t\t\t q, 0);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-399-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:400:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-401-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-403-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM5]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:404:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-405-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-407-\ndrivers/net/ethernet/airoha/airoha_eth.c:408:static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-409-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-415-\ndrivers/net/ethernet/airoha/airoha_eth.c:416:\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-417-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-419-\t\t      MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:420:\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:421:\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-422-\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-428-\t\tfor (j = 0; j \u003c AIROHA_FE_MC_MAX_VLAN_PORT; j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:429:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-430-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-433-\t\t\t      MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:434:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:435:\t\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-436-\t\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-447-\ndrivers/net/ethernet/airoha/airoha_eth.c:448:static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-449-{\ndrivers/net/ethernet/airoha/airoha_eth.c-450-\t/* CDM1_CRSN_QSEL */\ndrivers/net/ethernet/airoha/airoha_eth.c:451:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-452-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-454-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:455:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-456-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-458-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:459:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-460-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-462-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:463:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-464-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-466-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:467:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-468-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-471-\t/* CDM2_CRSN_QSEL */\ndrivers/net/ethernet/airoha/airoha_eth.c:472:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-473-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-475-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:476:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-477-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-479-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:480:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-481-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-483-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:484:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-485-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-487-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:488:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-489-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-493-\ndrivers/net/ethernet/airoha/airoha_eth.c:494:static int airoha_fe_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-495-{\ndrivers/net/ethernet/airoha/airoha_eth.c:496:\tairoha_fe_maccr_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-497-\ndrivers/net/ethernet/airoha/airoha_eth.c-498-\t/* PSE IQ reserve */\ndrivers/net/ethernet/airoha/airoha_eth.c:499:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-500-\t\t      FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10));\ndrivers/net/ethernet/airoha/airoha_eth.c:501:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV2,\ndrivers/net/ethernet/airoha/airoha_eth.c-502-\t\t      PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-506-\t/* enable FE copy engine for KA/DPI */\ndrivers/net/ethernet/airoha/airoha_eth.c:507:\tairoha_fe_wr(eth, REG_FE_PCE_CFG, PCE_DPI_EN_MASK | PCE_KA_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-508-\t/* set vip queue selection to ring 1 */\ndrivers/net/ethernet/airoha/airoha_eth.c:509:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-510-\t\t      FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c:511:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-512-\t\t      FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c-513-\t/* set GDM4 source interface offset to 8 */\ndrivers/net/ethernet/airoha/airoha_eth.c:514:\tairoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-515-\t\t      GDM_SPORT_OFF2_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-522-\t/* set PSE Page as 128B */\ndrivers/net/ethernet/airoha/airoha_eth.c:523:\tairoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-524-\t\t      FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-526-\t\t      FE_DMA_GLO_PG_SZ_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:527:\tairoha_fe_wr(eth, REG_FE_RST_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-528-\t\t     FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-534-\t */\ndrivers/net/ethernet/airoha/airoha_eth.c:535:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:536:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c:537:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:538:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c-539-\ndrivers/net/ethernet/airoha/airoha_eth.c:540:\tairoha_fe_vip_setup(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c:541:\tairoha_fe_pse_ports_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-542-\ndrivers/net/ethernet/airoha/airoha_eth.c:543:\tairoha_fe_set(eth, REG_GDM_MISC_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-544-\t\t      GDM2_RDM_ACK_WAIT_PREF_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-545-\t\t      GDM2_CHN_VLD_MODE_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:546:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-547-\t\t      FIELD_PREP(CDM_OAM_QSEL_MASK, 15));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-550-\t/* NPU Core-3, NPU Bridge Channel-3 */\ndrivers/net/ethernet/airoha/airoha_eth.c:551:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-552-\t\t      IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-555-\t/* QDMA LAN, RX Ring-22 */\ndrivers/net/ethernet/airoha/airoha_eth.c:556:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-557-\t\t      IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-560-\ndrivers/net/ethernet/airoha/airoha_eth.c:561:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:562:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-563-\ndrivers/net/ethernet/airoha/airoha_eth.c-564-\t/* Enable split for MIB counters for GDM3 and GDM4 */\ndrivers/net/ethernet/airoha/airoha_eth.c:565:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM3_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-566-\t\t      FE_GDM_TX_MIB_SPLIT_EN_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-567-\t\t      FE_GDM_RX_MIB_SPLIT_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:568:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM4_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-569-\t\t      FE_GDM_TX_MIB_SPLIT_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-571-\ndrivers/net/ethernet/airoha/airoha_eth.c:572:\tairoha_fe_crsn_qsel_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-573-\ndrivers/net/ethernet/airoha/airoha_eth.c:574:\tairoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:575:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-576-\ndrivers/net/ethernet/airoha/airoha_eth.c-577-\t/* default aging mode for mbi unlock issue */\ndrivers/net/ethernet/airoha/airoha_eth.c:578:\tairoha_fe_rmw(eth, REG_GDM_CHN_RLS(2),\ndrivers/net/ethernet/airoha/airoha_eth.c-579-\t\t      MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-583-\t/* disable IFC by default */\ndrivers/net/ethernet/airoha/airoha_eth.c:584:\tairoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-585-\ndrivers/net/ethernet/airoha/airoha_eth.c-586-\t/* enable 1:N vlan action, init vlan table */\ndrivers/net/ethernet/airoha/airoha_eth.c:587:\tairoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-588-\ndrivers/net/ethernet/airoha/airoha_eth.c:589:\treturn airoha_fe_mc_vlan_clear(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-590-}\ndrivers/net/ethernet/airoha/airoha_eth.c-591-\ndrivers/net/ethernet/airoha/airoha_eth.c:592:static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)\ndrivers/net/ethernet/airoha/airoha_eth.c-593-{\ndrivers/net/ethernet/airoha/airoha_eth.c:594:\tstruct airoha_qdma *qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-595-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-598-\twhile (q-\u003equeued \u003c q-\u003endesc - 1) {\ndrivers/net/ethernet/airoha/airoha_eth.c:599:\t\tstruct airoha_queue_entry *e = \u0026q-\u003eentry[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c:600:\t\tstruct airoha_qdma_desc *desc = \u0026q-\u003edesc[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c-601-\t\tstruct page *page;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-630-\tif (nframes)\ndrivers/net/ethernet/airoha/airoha_eth.c:631:\t\tairoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid),\ndrivers/net/ethernet/airoha/airoha_eth.c-632-\t\t\t\tRX_RING_CPU_IDX_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-637-\ndrivers/net/ethernet/airoha/airoha_eth.c:638:static struct airoha_gdm_dev *\ndrivers/net/ethernet/airoha/airoha_eth.c:639:airoha_qdma_get_gdm_dev(struct airoha_eth *eth, struct airoha_qdma_desc *desc)\ndrivers/net/ethernet/airoha/airoha_eth.c-640-{\ndrivers/net/ethernet/airoha/airoha_eth.c:641:\tstruct airoha_gdm_port *port;\ndrivers/net/ethernet/airoha/airoha_eth.c-642-\tu16 p, d;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-659-\ndrivers/net/ethernet/airoha/airoha_eth.c:660:static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)\ndrivers/net/ethernet/airoha/airoha_eth.c-661-{\ndrivers/net/ethernet/airoha/airoha_eth.c-662-\tenum dma_data_direction dir = page_pool_get_dma_dir(q-\u003epage_pool);\ndrivers/net/ethernet/airoha/airoha_eth.c:663:\tstruct airoha_qdma *qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c:664:\tstruct airoha_eth *eth = qdma-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-665-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-668-\twhile (done \u003c budget) {\ndrivers/net/ethernet/airoha/airoha_eth.c:669:\t\tstruct airoha_queue_entry *e = \u0026q-\u003eentry[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c:670:\t\tstruct airoha_qdma_desc *desc = \u0026q-\u003edesc[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c-671-\t\tu32 hash, reason, msg1, desc_ctrl;\ndrivers/net/ethernet/airoha/airoha_eth.c:672:\t\tstruct airoha_gdm_dev *dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-673-\t\tstruct net_device *netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-694-\ndrivers/net/ethernet/airoha/airoha_eth.c:695:\t\tdev = airoha_qdma_get_gdm_dev(eth, desc);\ndrivers/net/ethernet/airoha/airoha_eth.c-696-\t\tif (IS_ERR(dev))\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-728-\t\tif (netdev_uses_dsa(netdev)) {\ndrivers/net/ethernet/airoha/airoha_eth.c:729:\t\t\tstruct airoha_gdm_port *port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c-730-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-752-\t\tif (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)\ndrivers/net/ethernet/airoha/airoha_eth.c:753:\t\t\tairoha_ppe_check_skb(\u0026eth-\u003eppe-\u003edev, q-\u003eskb, hash,\n\n"
}

gemini-3.1-pro-preview

							input: 32528
							output: 32
							thoughts: 1744

**Analysis of the Airoha NPU Driver for Fuzzing Suitability**

Okay, so I'm looking at the `airoha_npu` code, specifically within the `drivers/net/ethernet/airoha/airoha_eth.c` driver. I see that `airoha_npu` is initialized via `airoha_ppe_npu_get()`, which is called from `airoha_ppe_offload_setup()`. And, `airoha_ppe_offload_setup()` itself is called by functions in `airoha_eth.c`. My first instinct is to check if `airoha_eth.c` is a standard Ethernet driver. Yes, it seems to be an Ethernet driver specifically for Airoha SoCs.

Now, the crucial question is whether this is some special-purpose hardware, like a PCIe switch, SmartNIC, or GPU driver, because if so, it's immediately excluded from fuzzing. But no, it's just an SoC-integrated Ethernet driver. That's key.

The prompt specifically says to return `WorthFuzzing=false` if the code falls under several categories, including code that requires specific hardware not emulated in standard QEMU. Is Airoha Ethernet a PCIe card? No, it's built into the SoC.

Can Syzkaller fuzz this? Syzkaller *can* fuzz platform drivers if they can be instantiated. Sometimes this happens through device tree overlays or pseudo-devices. The prompt is clear, though: I need to verify that this code *can* be executed in a virtualized environment. That is, code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware, mean I return `WorthFuzzing=false`.

Here's the problem: SoC-specific Ethernet drivers, like Airoha (along with MediaTek and Qualcomm IPQ), are *not* typically emulated in standard QEMU. They usually require very specific SoC emulation, which isn't present in standard syzkaller QEMU images that use `q35` or `virt` machine types.

I know Syzkaller has been evolving, and I'm aware that it's added support for platform drivers through mechanisms like `syz_devres` or similar, but the core issue remains MMIO. If the hardware isn't there, any attempt to read or write to MMIO addresses will result in a crash, a probe failure, or just garbage data. I remember the `syz_platform_device_add` pseudo-syscall, but that doesn't exist. Syzkaller uses `syz_mount_image` and crafted filesystems to load things, maybe including device tree overlays. The latest additions to fuzzing platform drivers depend on what those overlays do.

If a DT overlay is used to register this hardware, the driver will try to `devm_platform_ioremap_resource(pdev, 0)`. The overlay will specify some physical address. If that address is not backed by RAM or a real MMIO device in QEMU, `ioremap` *might* succeed, but actually reading or writing to it will cause a synchronous external abort or page fault if the address is not mapped. Or, I might just get all 0xFFs, which will likely cause a probe failure.

Let's look closely at `airoha_npu_probe`: it calls `devm_platform_ioremap_resource()` to map the MMIO region. Then it uses `devm_regmap_init_mmio` to initialize a `regmap`. Crucially, it then calls `airoha_npu_run_firmware()`, which, in turn, calls `airoha_npu_load_firmware()`. This function requests firmware, and if that firmware isn't found, it fails. If the probe fails, everything after it, like `airoha_npu_send_msg`, is never reached.

The reachability of `airoha_npu_send_msg` depends on successfully probing the driver. `airoha_npu_send_msg` is called by `airoha_npu_ppe_init`, `airoha_npu_wlan_msg_send`, etc., which are reached through function pointers via `npu->ops.ppe_init` etc. This is called from `airoha_ppe_offload_setup()` in `airoha_ppe.c`, which is ultimately called from `airoha_eth_probe`. Therefore, it requires the `airoha_eth` driver to probe successfully. `airoha_eth` is also a platform driver. If there is no Airoha hardware, this probe will fail.

I have to consider the fact

{
  "Expression": "airoha",
  "PathPrefix": "drivers/net/ethernet/airoha/"
}

{
  "Output": "\nFull output is too long, showing 500 out of 3689 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/airoha/Makefile-5-\ndrivers/net/ethernet/airoha/Makefile:6:obj-$(CONFIG_NET_AIROHA) += airoha-eth.o\ndrivers/net/ethernet/airoha/Makefile:7:airoha-eth-y := airoha_eth.o airoha_ppe.o\ndrivers/net/ethernet/airoha/Makefile:8:airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-16-\ndrivers/net/ethernet/airoha/airoha_eth.c:17:#include \"airoha_regs.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c:18:#include \"airoha_eth.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c-19-\ndrivers/net/ethernet/airoha/airoha_eth.c:20:u32 airoha_rr(void __iomem *base, u32 offset)\ndrivers/net/ethernet/airoha/airoha_eth.c-21-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-24-\ndrivers/net/ethernet/airoha/airoha_eth.c:25:void airoha_wr(void __iomem *base, u32 offset, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-26-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-29-\ndrivers/net/ethernet/airoha/airoha_eth.c:30:u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-31-{\ndrivers/net/ethernet/airoha/airoha_eth.c:32:\tval |= (airoha_rr(base, offset) \u0026 ~mask);\ndrivers/net/ethernet/airoha/airoha_eth.c:33:\tairoha_wr(base, offset, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-34-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-37-\ndrivers/net/ethernet/airoha/airoha_eth.c:38:static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-39-\t\t\t\t    int index, u32 clear, u32 set)\ndrivers/net/ethernet/airoha/airoha_eth.c-40-{\ndrivers/net/ethernet/airoha/airoha_eth.c:41:\tstruct airoha_qdma *qdma = irq_bank-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-42-\tint bank = irq_bank - \u0026qdma-\u003eirq_banks[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-51-\tirq_bank-\u003eirqmask[index] |= set;\ndrivers/net/ethernet/airoha/airoha_eth.c:52:\tairoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),\ndrivers/net/ethernet/airoha/airoha_eth.c-53-\t\t       irq_bank-\u003eirqmask[index]);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-56-\t */\ndrivers/net/ethernet/airoha/airoha_eth.c:57:\tairoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));\ndrivers/net/ethernet/airoha/airoha_eth.c-58-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-61-\ndrivers/net/ethernet/airoha/airoha_eth.c:62:static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-63-\t\t\t\t   int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-64-{\ndrivers/net/ethernet/airoha/airoha_eth.c:65:\tairoha_qdma_set_irqmask(irq_bank, index, 0, mask);\ndrivers/net/ethernet/airoha/airoha_eth.c-66-}\ndrivers/net/ethernet/airoha/airoha_eth.c-67-\ndrivers/net/ethernet/airoha/airoha_eth.c:68:static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-69-\t\t\t\t    int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-70-{\ndrivers/net/ethernet/airoha/airoha_eth.c:71:\tairoha_qdma_set_irqmask(irq_bank, index, mask, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-72-}\ndrivers/net/ethernet/airoha/airoha_eth.c-73-\ndrivers/net/ethernet/airoha/airoha_eth.c:74:static int airoha_set_macaddr(struct airoha_gdm_dev *dev, const u8 *addr)\ndrivers/net/ethernet/airoha/airoha_eth.c-75-{\ndrivers/net/ethernet/airoha/airoha_eth.c-76-\tu8 ref_addr[ETH_ALEN] __aligned(2);\ndrivers/net/ethernet/airoha/airoha_eth.c:77:\tstruct airoha_eth *eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-78-\tu32 reg, val, lmin, lmax;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-85-\tfor (i = 0; i \u003c ARRAY_SIZE(eth-\u003eports); i++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:86:\t\tstruct airoha_gdm_port *port = eth-\u003eports[i];\ndrivers/net/ethernet/airoha/airoha_eth.c-87-\t\tint j;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-92-\t\tfor (j = 0; j \u003c ARRAY_SIZE(port-\u003edevs); j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:93:\t\t\tstruct airoha_gdm_dev *iter_dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-94-\t\t\tstruct net_device *netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-99-\ndrivers/net/ethernet/airoha/airoha_eth.c:100:\t\t\tif (airoha_is_lan_gdm_dev(iter_dev) !=\ndrivers/net/ethernet/airoha/airoha_eth.c:101:\t\t\t    airoha_is_lan_gdm_dev(dev))\ndrivers/net/ethernet/airoha/airoha_eth.c-102-\t\t\t\tcontinue;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-133-\ndrivers/net/ethernet/airoha/airoha_eth.c:134:\treg = airoha_is_lan_gdm_dev(dev) ? REG_FE_LAN_MAC_H : REG_FE_WAN_MAC_H;\ndrivers/net/ethernet/airoha/airoha_eth.c-135-\tval = (addr[0] \u003c\u003c 16) | (addr[1] \u003c\u003c 8) | addr[2];\ndrivers/net/ethernet/airoha/airoha_eth.c:136:\tairoha_fe_wr(eth, reg, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-137-\ndrivers/net/ethernet/airoha/airoha_eth.c:138:\tairoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), lmin);\ndrivers/net/ethernet/airoha/airoha_eth.c:139:\tairoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), lmax);\ndrivers/net/ethernet/airoha/airoha_eth.c-140-\ndrivers/net/ethernet/airoha/airoha_eth.c:141:\tairoha_ppe_init_upd_mem(dev, addr);\ndrivers/net/ethernet/airoha/airoha_eth.c-142-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-145-\ndrivers/net/ethernet/airoha/airoha_eth.c:146:static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,\ndrivers/net/ethernet/airoha/airoha_eth.c-147-\t\t\t\t\tu32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-148-{\ndrivers/net/ethernet/airoha/airoha_eth.c:149:\tairoha_fe_rmw(eth, addr, GDM_OCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-150-\t\t      FIELD_PREP(GDM_OCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:151:\tairoha_fe_rmw(eth, addr, GDM_MCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-152-\t\t      FIELD_PREP(GDM_MCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:153:\tairoha_fe_rmw(eth, addr, GDM_BCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-154-\t\t      FIELD_PREP(GDM_BCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:155:\tairoha_fe_rmw(eth, addr, GDM_UCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-156-\t\t      FIELD_PREP(GDM_UCFQ_MASK, val));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-158-\ndrivers/net/ethernet/airoha/airoha_eth.c:159:static int airoha_set_vip_for_gdm_port(struct airoha_gdm_dev *dev, bool enable)\ndrivers/net/ethernet/airoha/airoha_eth.c-160-{\ndrivers/net/ethernet/airoha/airoha_eth.c:161:\tstruct airoha_gdm_port *port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c:162:\tstruct airoha_eth *eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-163-\tu32 vip_port;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-166-\tif (enable) {\ndrivers/net/ethernet/airoha/airoha_eth.c:167:\t\tairoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:168:\t\tairoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-169-\t} else {\ndrivers/net/ethernet/airoha/airoha_eth.c:170:\t\tairoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:171:\t\tairoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-172-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-176-\ndrivers/net/ethernet/airoha/airoha_eth.c:177:static void airoha_fe_maccr_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-178-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-181-\tfor (p = 1; p \u003c= ARRAY_SIZE(eth-\u003eports); p++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:182:\t\tairoha_fe_set(eth, REG_GDM_FWD_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-183-\t\t\t      GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-184-\t\t\t      GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:185:\t\tairoha_fe_rmw(eth, REG_GDM_LEN_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-186-\t\t\t      GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-190-\ndrivers/net/ethernet/airoha/airoha_eth.c:191:\tairoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-192-\t\t      FIELD_PREP(CDM_VLAN_MASK, 0x8100));\ndrivers/net/ethernet/airoha/airoha_eth.c-193-\ndrivers/net/ethernet/airoha/airoha_eth.c:194:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD);\ndrivers/net/ethernet/airoha/airoha_eth.c-195-}\ndrivers/net/ethernet/airoha/airoha_eth.c-196-\ndrivers/net/ethernet/airoha/airoha_eth.c:197:static void airoha_fe_vip_setup(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-198-{\ndrivers/net/ethernet/airoha/airoha_eth.c:199:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC);\ndrivers/net/ethernet/airoha/airoha_eth.c:200:\tairoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-201-\ndrivers/net/ethernet/airoha/airoha_eth.c:202:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:203:\tairoha_fe_wr(eth, REG_FE_VIP_EN(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-204-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-206-\ndrivers/net/ethernet/airoha/airoha_eth.c:207:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:208:\tairoha_fe_wr(eth, REG_FE_VIP_EN(6),\ndrivers/net/ethernet/airoha/airoha_eth.c-209-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-211-\ndrivers/net/ethernet/airoha/airoha_eth.c:212:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:213:\tairoha_fe_wr(eth, REG_FE_VIP_EN(7),\ndrivers/net/ethernet/airoha/airoha_eth.c-214-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-217-\t/* BOOTP (0x43) */\ndrivers/net/ethernet/airoha/airoha_eth.c:218:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43);\ndrivers/net/ethernet/airoha/airoha_eth.c:219:\tairoha_fe_wr(eth, REG_FE_VIP_EN(8),\ndrivers/net/ethernet/airoha/airoha_eth.c-220-\t\t     PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-223-\t/* BOOTP (0x44) */\ndrivers/net/ethernet/airoha/airoha_eth.c:224:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44);\ndrivers/net/ethernet/airoha/airoha_eth.c:225:\tairoha_fe_wr(eth, REG_FE_VIP_EN(9),\ndrivers/net/ethernet/airoha/airoha_eth.c-226-\t\t     PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-229-\t/* ISAKMP */\ndrivers/net/ethernet/airoha/airoha_eth.c:230:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4);\ndrivers/net/ethernet/airoha/airoha_eth.c:231:\tairoha_fe_wr(eth, REG_FE_VIP_EN(10),\ndrivers/net/ethernet/airoha/airoha_eth.c-232-\t\t     PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-234-\ndrivers/net/ethernet/airoha/airoha_eth.c:235:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP);\ndrivers/net/ethernet/airoha/airoha_eth.c:236:\tairoha_fe_wr(eth, REG_FE_VIP_EN(11),\ndrivers/net/ethernet/airoha/airoha_eth.c-237-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-240-\t/* DHCPv6 */\ndrivers/net/ethernet/airoha/airoha_eth.c:241:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223);\ndrivers/net/ethernet/airoha/airoha_eth.c:242:\tairoha_fe_wr(eth, REG_FE_VIP_EN(12),\ndrivers/net/ethernet/airoha/airoha_eth.c-243-\t\t     PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-245-\ndrivers/net/ethernet/airoha/airoha_eth.c:246:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:247:\tairoha_fe_wr(eth, REG_FE_VIP_EN(19),\ndrivers/net/ethernet/airoha/airoha_eth.c-248-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-251-\t/* ETH-\u003eETH_P_1905 (0x893a) */\ndrivers/net/ethernet/airoha/airoha_eth.c:252:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a);\ndrivers/net/ethernet/airoha/airoha_eth.c:253:\tairoha_fe_wr(eth, REG_FE_VIP_EN(20),\ndrivers/net/ethernet/airoha/airoha_eth.c-254-\t\t     PATN_FCPU_EN_MASK | PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-255-\ndrivers/net/ethernet/airoha/airoha_eth.c:256:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP);\ndrivers/net/ethernet/airoha/airoha_eth.c:257:\tairoha_fe_wr(eth, REG_FE_VIP_EN(21),\ndrivers/net/ethernet/airoha/airoha_eth.c-258-\t\t     PATN_FCPU_EN_MASK | PATN_EN_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-260-\ndrivers/net/ethernet/airoha/airoha_eth.c:261:static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-262-\t\t\t\t\t     u32 port, u32 queue)\ndrivers/net/ethernet/airoha/airoha_eth.c-263-{\ndrivers/net/ethernet/airoha/airoha_eth.c:264:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-265-\t\t      PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-268-\ndrivers/net/ethernet/airoha/airoha_eth.c:269:\treturn airoha_fe_get(eth, REG_FE_PSE_QUEUE_CFG_VAL,\ndrivers/net/ethernet/airoha/airoha_eth.c-270-\t\t\t     PSE_CFG_OQ_RSV_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-272-\ndrivers/net/ethernet/airoha/airoha_eth.c:273:static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-274-\t\t\t\t\t      u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-275-{\ndrivers/net/ethernet/airoha/airoha_eth.c:276:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-277-\t\t      FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:278:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-279-\t\t      PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-285-\ndrivers/net/ethernet/airoha/airoha_eth.c:286:static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-287-{\ndrivers/net/ethernet/airoha/airoha_eth.c:288:\treturn airoha_fe_get(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-289-}\ndrivers/net/ethernet/airoha/airoha_eth.c-290-\ndrivers/net/ethernet/airoha/airoha_eth.c:291:static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-292-\t\t\t\t    u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-293-{\ndrivers/net/ethernet/airoha/airoha_eth.c:294:\tu32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);\ndrivers/net/ethernet/airoha/airoha_eth.c-295-\tu32 tmp, all_rsv, fq_limit;\ndrivers/net/ethernet/airoha/airoha_eth.c-296-\ndrivers/net/ethernet/airoha/airoha_eth.c:297:\tairoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-298-\ndrivers/net/ethernet/airoha/airoha_eth.c-299-\t/* modify all rsv */\ndrivers/net/ethernet/airoha/airoha_eth.c:300:\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-301-\tall_rsv += (val - orig_val);\ndrivers/net/ethernet/airoha/airoha_eth.c:302:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-303-\t\t      FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-305-\t/* modify hthd */\ndrivers/net/ethernet/airoha/airoha_eth.c:306:\tfq_limit = airoha_fe_get(eth, PSE_FQ_CFG, PSE_FQ_LIMIT_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-307-\ttmp = fq_limit - all_rsv - 0x20;\ndrivers/net/ethernet/airoha/airoha_eth.c:308:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-309-\t\t      PSE_SHARE_USED_HTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-312-\ttmp = fq_limit - all_rsv - 0x100;\ndrivers/net/ethernet/airoha/airoha_eth.c:313:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-314-\t\t      PSE_SHARE_USED_MTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-316-\ttmp = (3 * tmp) \u003e\u003e 2;\ndrivers/net/ethernet/airoha/airoha_eth.c:317:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET,\ndrivers/net/ethernet/airoha/airoha_eth.c-318-\t\t      PSE_SHARE_USED_LTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-323-\ndrivers/net/ethernet/airoha/airoha_eth.c:324:static void airoha_fe_pse_ports_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-325-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-340-\ndrivers/net/ethernet/airoha/airoha_eth.c:341:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-342-\t\tu32 all_rsv;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-344-\t\t/* hw misses PPE2 oq rsv */\ndrivers/net/ethernet/airoha/airoha_eth.c:345:\t\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-346-\t\tall_rsv += PSE_RSV_PAGES *\ndrivers/net/ethernet/airoha/airoha_eth.c-347-\t\t\t   pse_port_num_queues[FE_PSE_PORT_PPE2];\ndrivers/net/ethernet/airoha/airoha_eth.c:348:\t\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-349-\t\t\t      FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-353-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:354:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-355-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-357-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:358:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-359-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-361-\tfor (q = 6; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:362:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-363-\t/* GDM3 */\ndrivers/net/ethernet/airoha/airoha_eth.c-364-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM3]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:365:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-366-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-369-\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE1] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:370:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-371-\t\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c-372-\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:373:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-374-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-376-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:377:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-378-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-380-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:381:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-382-\t/* CDM4 */\ndrivers/net/ethernet/airoha/airoha_eth.c-383-\tfor (q = 4; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:384:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-385-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c:386:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-387-\t\t/* PPE2 */\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-389-\t\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE2] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:390:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-391-\t\t\t\t\t\t\t q,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-393-\t\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:394:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-395-\t\t\t\t\t\t\t q, 0);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-399-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:400:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-401-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-403-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM5]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:404:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-405-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-407-\ndrivers/net/ethernet/airoha/airoha_eth.c:408:static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-409-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-415-\ndrivers/net/ethernet/airoha/airoha_eth.c:416:\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-417-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-419-\t\t      MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:420:\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:421:\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-422-\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-428-\t\tfor (j = 0; j \u003c AIROHA_FE_MC_MAX_VLAN_PORT; j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:429:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-430-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-433-\t\t\t      MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:434:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:435:\t\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-436-\t\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-447-\ndrivers/net/ethernet/airoha/airoha_eth.c:448:static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-449-{\ndrivers/net/ethernet/airoha/airoha_eth.c-450-\t/* CDM1_CRSN_QSEL */\ndrivers/net/ethernet/airoha/airoha_eth.c:451:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-452-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-454-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:455:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-456-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-458-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:459:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-460-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-462-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:463:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-464-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-466-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:467:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-468-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-471-\t/* CDM2_CRSN_QSEL */\ndrivers/net/ethernet/airoha/airoha_eth.c:472:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-473-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-475-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:476:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-477-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-479-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:480:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-481-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-483-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:484:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-485-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-487-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:488:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-489-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-493-\ndrivers/net/ethernet/airoha/airoha_eth.c:494:static int airoha_fe_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-495-{\ndrivers/net/ethernet/airoha/airoha_eth.c:496:\tairoha_fe_maccr_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-497-\ndrivers/net/ethernet/airoha/airoha_eth.c-498-\t/* PSE IQ reserve */\ndrivers/net/ethernet/airoha/airoha_eth.c:499:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-500-\t\t      FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10));\ndrivers/net/ethernet/airoha/airoha_eth.c:501:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV2,\ndrivers/net/ethernet/airoha/airoha_eth.c-502-\t\t      PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-506-\t/* enable FE copy engine for KA/DPI */\ndrivers/net/ethernet/airoha/airoha_eth.c:507:\tairoha_fe_wr(eth, REG_FE_PCE_CFG, PCE_DPI_EN_MASK | PCE_KA_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-508-\t/* set vip queue selection to ring 1 */\ndrivers/net/ethernet/airoha/airoha_eth.c:509:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-510-\t\t      FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c:511:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-512-\t\t      FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c-513-\t/* set GDM4 source interface offset to 8 */\ndrivers/net/ethernet/airoha/airoha_eth.c:514:\tairoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-515-\t\t      GDM_SPORT_OFF2_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-522-\t/* set PSE Page as 128B */\ndrivers/net/ethernet/airoha/airoha_eth.c:523:\tairoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-524-\t\t      FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-526-\t\t      FE_DMA_GLO_PG_SZ_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:527:\tairoha_fe_wr(eth, REG_FE_RST_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-528-\t\t     FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-534-\t */\ndrivers/net/ethernet/airoha/airoha_eth.c:535:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:536:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c:537:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:538:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c-539-\ndrivers/net/ethernet/airoha/airoha_eth.c:540:\tairoha_fe_vip_setup(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c:541:\tairoha_fe_pse_ports_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-542-\ndrivers/net/ethernet/airoha/airoha_eth.c:543:\tairoha_fe_set(eth, REG_GDM_MISC_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-544-\t\t      GDM2_RDM_ACK_WAIT_PREF_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-545-\t\t      GDM2_CHN_VLD_MODE_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:546:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-547-\t\t      FIELD_PREP(CDM_OAM_QSEL_MASK, 15));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-550-\t/* NPU Core-3, NPU Bridge Channel-3 */\ndrivers/net/ethernet/airoha/airoha_eth.c:551:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-552-\t\t      IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-555-\t/* QDMA LAN, RX Ring-22 */\ndrivers/net/ethernet/airoha/airoha_eth.c:556:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-557-\t\t      IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-560-\ndrivers/net/ethernet/airoha/airoha_eth.c:561:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:562:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-563-\ndrivers/net/ethernet/airoha/airoha_eth.c-564-\t/* Enable split for MIB counters for GDM3 and GDM4 */\ndrivers/net/ethernet/airoha/airoha_eth.c:565:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM3_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-566-\t\t      FE_GDM_TX_MIB_SPLIT_EN_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-567-\t\t      FE_GDM_RX_MIB_SPLIT_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:568:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM4_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-569-\t\t      FE_GDM_TX_MIB_SPLIT_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-571-\ndrivers/net/ethernet/airoha/airoha_eth.c:572:\tairoha_fe_crsn_qsel_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-573-\ndrivers/net/ethernet/airoha/airoha_eth.c:574:\tairoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:575:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-576-\ndrivers/net/ethernet/airoha/airoha_eth.c-577-\t/* default aging mode for mbi unlock issue */\ndrivers/net/ethernet/airoha/airoha_eth.c:578:\tairoha_fe_rmw(eth, REG_GDM_CHN_RLS(2),\ndrivers/net/ethernet/airoha/airoha_eth.c-579-\t\t      MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-583-\t/* disable IFC by default */\ndrivers/net/ethernet/airoha/airoha_eth.c:584:\tairoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-585-\ndrivers/net/ethernet/airoha/airoha_eth.c-586-\t/* enable 1:N vlan action, init vlan table */\ndrivers/net/ethernet/airoha/airoha_eth.c:587:\tairoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-588-\ndrivers/net/ethernet/airoha/airoha_eth.c:589:\treturn airoha_fe_mc_vlan_clear(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-590-}\ndrivers/net/ethernet/airoha/airoha_eth.c-591-\ndrivers/net/ethernet/airoha/airoha_eth.c:592:static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)\ndrivers/net/ethernet/airoha/airoha_eth.c-593-{\ndrivers/net/ethernet/airoha/airoha_eth.c:594:\tstruct airoha_qdma *qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-595-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-598-\twhile (q-\u003equeued \u003c q-\u003endesc - 1) {\ndrivers/net/ethernet/airoha/airoha_eth.c:599:\t\tstruct airoha_queue_entry *e = \u0026q-\u003eentry[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c:600:\t\tstruct airoha_qdma_desc *desc = \u0026q-\u003edesc[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c-601-\t\tstruct page *page;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-630-\tif (nframes)\ndrivers/net/ethernet/airoha/airoha_eth.c:631:\t\tairoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid),\ndrivers/net/ethernet/airoha/airoha_eth.c-632-\t\t\t\tRX_RING_CPU_IDX_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-637-\ndrivers/net/ethernet/airoha/airoha_eth.c:638:static struct airoha_gdm_dev *\ndrivers/net/ethernet/airoha/airoha_eth.c:639:airoha_qdma_get_gdm_dev(struct airoha_eth *eth, struct airoha_qdma_desc *desc)\ndrivers/net/ethernet/airoha/airoha_eth.c-640-{\ndrivers/net/ethernet/airoha/airoha_eth.c:641:\tstruct airoha_gdm_port *port;\ndrivers/net/ethernet/airoha/airoha_eth.c-642-\tu16 p, d;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-659-\ndrivers/net/ethernet/airoha/airoha_eth.c:660:static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)\ndrivers/net/ethernet/airoha/airoha_eth.c-661-{\ndrivers/net/ethernet/airoha/airoha_eth.c-662-\tenum dma_data_direction dir = page_pool_get_dma_dir(q-\u003epage_pool);\ndrivers/net/ethernet/airoha/airoha_eth.c:663:\tstruct airoha_qdma *qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c:664:\tstruct airoha_eth *eth = qdma-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-665-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-668-\twhile (done \u003c budget) {\ndrivers/net/ethernet/airoha/airoha_eth.c:669:\t\tstruct airoha_queue_entry *e = \u0026q-\u003eentry[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c:670:\t\tstruct airoha_qdma_desc *desc = \u0026q-\u003edesc[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c-671-\t\tu32 hash, reason, msg1, desc_ctrl;\ndrivers/net/ethernet/airoha/airoha_eth.c:672:\t\tstruct airoha_gdm_dev *dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-673-\t\tstruct net_device *netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-694-\ndrivers/net/ethernet/airoha/airoha_eth.c:695:\t\tdev = airoha_qdma_get_gdm_dev(eth, desc);\ndrivers/net/ethernet/airoha/airoha_eth.c-696-\t\tif (IS_ERR(dev))\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-728-\t\tif (netdev_uses_dsa(netdev)) {\ndrivers/net/ethernet/airoha/airoha_eth.c:729:\t\t\tstruct airoha_gdm_port *port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c-730-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-752-\t\tif (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)\ndrivers/net/ethernet/airoha/airoha_eth.c:753:\t\t\tairoha_ppe_check_skb(\u0026eth-\u003eppe-\u003edev, q-\u003eskb, hash,\n\n"
}

gemini-3.1-pro-preview

							input: 51618
							output: 31
							thoughts: 370

**Analyzing the WorthFuzzing Criteria**

Okay, first things first, I've spotted `airoha_eth.c`, `airoha_ppe.c`, and `airoha_npu.c` in the patch. Now, I need to evaluate this against the "WorthFuzzing" criteria. The prompt specifically mentions returning `WorthFuzzing=false` if the patch *only* contains code paths inaccessible in virtualized environments like QEMU.

The key question is: Is `airoha_npu.c` reachable within a QEMU environment? Considering my understanding, no, it's a platform driver tailored for a particular System-on-a-Chip (SoC). This driver necessitates the underlying hardware or at least its accurate emulation, which, I'm pretty sure, QEMU doesn't offer for this specific SoC.

I recall Syzkaller has mechanisms for evaluating patches even if they can't be fully fuzzed. It'll attempt to apply the patch, check compilation, or try a fuzzing run to determine if it can find anything. But that's not the primary concern here.

The prompt is crystal clear: if it modifies core kernel logic, drivers, or architectures that are reachable, it's worth fuzzing. If it's inaccessible, then it's not. Given my assessment that `airoha_npu.c` *is* inaccessible in QEMU because it's hardware-specific, it looks like a `WorthFuzzing=false` is the correct determination.

However, I should double-check. I'll search the `tools/` and `drivers/net/ethernet/airoha/` directories for any mock or software emulation support for Airoha hardware. This is a crucial step to avoid making any assumptions. If I find something, my assessment might change.

{
  "Expression": "mock",
  "PathPrefix": "drivers/net/ethernet/airoha/"
}

{
  "error": "no matches"
}

gemini-3.1-pro-preview

							input: 52429
							output: 97
							thoughts: 1547

**Unreachable Code in Virtualized Environments**

Okay, let's break this down. First, no mockups are needed. I'm focusing on reachability in a fuzzing context, and that means virtualized environments like QEMU are the key consideration.  Is `CONFIG_NET_AIROHA_NPU` even enabled in syzkaller?  Even if it *is*, this driver, a `platform_driver`, is going to need a corresponding `platform_device` to trigger the `probe` function.  Syzkaller might *try* to create a platform device using `syz_devres` or similar, but even then the `probe` function is going to try to `ioremap` the physical address. And if that hardware isn't *actually* there, that's just going to crash or fail.

Hold on, I thought maybe syzkaller has some kind of pseudo-syscall like `syz_platform_device_add`? No, that doesn't exist. Now, what if it was a PCI driver? No, it's a platform driver, so that's irrelevant.

Alright, back to the code, specifically `airoha_npu.c`.

```c
static const struct of_device_id of_airoha_npu_match[] = {
	{ .compatible = "airoha,en7581-npu", .data = &en7581_npu_soc_data },
	{ .compatible = "airoha,an7583-npu", .data = &an7583_npu_soc_data },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_airoha_npu_match);

static struct platform_driver airoha_npu_driver = {
	.probe = airoha_npu_probe,
	.remove = airoha_npu_remove,
	.driver = {
		.name = "airoha-npu",
		.of_match_table = of_airoha_npu_match,
	},
};
module_platform_driver(airoha_npu_driver);
```

Okay, it's a standard Device Tree based platform driver. In QEMU, the device tree is provided by the machine type, e.g., 'virt'. And the 'virt' machine type **doesn't** include something like "airoha,en7581-npu". Boom.  The device won't be instantiated, and `probe` won't be called.  It's just not going to happen in these virtualized environments.

Could syzkaller use device tree overlays? Even if it did, that `devm_platform_ioremap_resource` call will map a physical address.  QEMU isn't emulating Airoha NPU registers at that address.  Reading from that address will probably cause a bus error, or return garbage. Either way, it's a dead end.

Specifically in `airoha_npu_probe`:

```c
	err = airoha_npu_run_firmware(dev, base, &res);
```

Inside `airoha_npu_run_firmware`:

```c
	/* Load rv32 npu firmware */
	ret = airoha_npu_load_firmware(dev, addr, soc->fw_rv32.name,
				       soc->fw_rv32.max_size);
```

If the firmware isn't in the rootfs, it's going to fail *there*, but even if it's there it is writing registers and waiting:

```c
	if (!airoha_npu_wlan_msg_get(npu, 0, WLAN_FUNC_GET_WAIT_NPU_VERSION,
				     &val, sizeof(val), GFP_KERNEL))
		dev_info(dev, "NPU version: %d\n", val);
```

`airoha_npu_wlan_msg_get` then calls `__airoha_npu_send_msg`, where we see:

```c
	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr);
	regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, len);
	regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val);
	regmap_

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Airoha NPU driver, which is a hardware-specific SoC driver for Airoha EN7581/AN7583 routers. This driver requires physical hardware that is not emulated in standard QEMU environments, making the code paths impossible to reach and test during fuzzing.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Airoha NPU driver, which is a hardware-specific SoC driver for Airoha EN7581/AN7583 routers. This driver requires physical hardware that is not emulated in standard QEMU environments, making the code paths impossible to reach and test during fuzzing.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

LLM Calls Summary:
Total Calls	Total Tokens	Avg Tokens	Total Duration (Seconds)	Avg Duration (Seconds)

Tool Calls Summary:
Total Calls	Total Duration (Seconds)	Avg Duration (Seconds)