| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/10/09 21:55 | flow | patch-triage |
8mArgs:null Results: {
"EnableConfigs": [
"PHYLINK",
"FWNODE_PCS"
],
"FocusSymbols": [
"phylink_create",
"phylink_destroy",
"phylink_pcs_change",
"phylink_update_mac_pause_capabilities",
"phylink_ethtool_ksettings_set",
"fwnode_phylink_pcs_parse",
"fwnode_phylink_pcs_count",
"fwnode_pcs_add_provider",
"fwnode_pcs_del_provider",
"fwnode_pcs_matches_provider",
"register_fwnode_pcs_notifier",
"unregister_fwnode_pcs_notifier"
],
"KMSANReasoning": "The patch series introduces a new firmware-node (fwnode) PCS subsystem framework, adds support for Airoha PCS hardware (common and AN7581-specific drivers), and updates the phylink core and the Airoha Ethernet driver to support dynamic PCS discovery and hotplug notifications.\n\nAn audit of the changes shows no uninitialized memory risks:\n1. All newly allocated kernel heap objects and arrays are zero-initialized at allocation time:\n - `struct fwnode_pcs_provider` uses `kzalloc_obj`.\n - Device resources use `devres_alloc` and `devm_kzalloc` / `devm_kcalloc` (e.g., `struct airoha_pcs_priv`, port arrays, regmap field arrays).\n - Temporary arrays such as `pcss` in `phylink_fill_available_pcs()` are allocated via `kzalloc_objs`.\n - `struct phylink` is allocated with `kzalloc_obj`.\n2. All local stack variables across new and modified functions (such as register read values, status flags, and temporary pointers) are explicitly initialized at declaration or safely populated before read.\n3. No data is copied to user space via `copy_to_user`, `put_user`, Netlink attributes, ioctls, or socket buffers. The addition of `.get_link_ksettings` in `airoha_eth.c` delegates to `phylink_ethtool_ksettings_get()`, which operates on an `ethtool_link_ksettings` structure already zeroed by the ethtool core.\n4. Any potential risks introduced by the patch involve list operations, reference counting (`fwnode_handle_get`/`put`), locking under `state_mutex`/`rtnl_lock`, or lifecycle management. These classes of bugs are already covered by standard KASAN, LOCKDEP, and general kernel debuggers.\n\nTherefore, there is no risk of uninitialized memory reads or information leaks that would justify a dedicated KMSAN session.",
"NeedsKMSAN": false,
"Reasoning": "The patch series introduces a new generic Ethernet PCS firmware node framework (drivers/net/pcs/pcs.c) and makes significant modifications to the core phylink subsystem (drivers/net/phy/phylink.c) to handle multiple PCS devices, dynamic interface mask updates, and hotplug PCS provider notifications. Phylink is reachable via standard virtualized netdevices (including USB Ethernet devices like asix and lan78xx, DSA, and PCIe drivers like r8169). Furthermore, the locking modifications introduce mutex acquisition of pl-\u003estate_mutex in phylink_validate_mac_and_pcs(), which creates a recursive deadlock hazard in reachable call paths like phylink_update_mac_pause_capabilities(). Therefore, the changes affect reachable code and warrant fuzzing.",
"WorthFuzzing": true
} |
| 1/1 | 2026/10/09 21:55 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit fa50ce9901b4f80b61fb05d00ca168060d135a73\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Fri Oct 9 21:55:49 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml\nnew file mode 100644\nindex 0000000000000..9c1d116c1b016\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml\n@@ -0,0 +1,261 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Airoha Ethernet PCS and Serdes\n+\n+maintainers:\n+ - Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+\n+description:\n+ Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for\n+ the various Serdes port supporting different Media Independent Interface\n+ (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).\n+\n+properties:\n+ compatible:\n+ enum:\n+ - airoha,an7581-pcs-eth\n+ - airoha,an7581-pcs-pon\n+ - airoha,an7581-pcs-pcie\n+ - airoha,an7581-pcs-usb\n+\n+ reg:\n+ minItems: 6\n+ maxItems: 15\n+\n+ reg-names:\n+ minItems: 6\n+ maxItems: 15\n+\n+ airoha,scu:\n+ $ref: /schemas/types.yaml#/definitions/phandle\n+ description: phandle to the SCU node required to configure\n+ the serdes line to the correct interface mode.\n+\n+ phys:\n+ maxItems: 1\n+\n+ \"#pcs-cells\": true\n+\n+required:\n+ - compatible\n+ - reg\n+ - reg-names\n+ - \"#pcs-cells\"\n+\n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - airoha,an7581-pcs-eth\n+ - airoha,an7581-pcs-pon\n+\n+ then:\n+ properties:\n+ reg:\n+ items:\n+ - description: PCS MAC reg\n+ - description: HSGMII AN reg\n+ - description: HSGMII PCS reg\n+ - description: MULTI SGMII reg\n+ - description: USXGMII reg\n+ - description: HSGMII rate adaption reg\n+ - description: PCS Analog register\n+ - description: PCS PMA (Physical Medium Attachment) register\n+\n+ reg-names:\n+ items:\n+ - const: pcs_mac\n+ - const: hsgmii_an\n+ - const: hsgmii_pcs\n+ - const: multi_sgmii\n+ - const: usxgmii\n+ - const: hsgmii_rate_adp\n+ - const: pcs_ana\n+ - const: pcs_pma\n+\n+ phys: false\n+\n+ \"#pcs-cells\":\n+ const: 0\n+\n+ required:\n+ - airoha,scu\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ const: airoha,an7581-pcs-pcie\n+\n+ then:\n+ properties:\n+ reg:\n+ items:\n+ - description: PCS MAC 0 reg\n+ - description: HSGMII AN 0 reg\n+ - description: HSGMII PCS 0 reg\n+ - description: MULTI SGMII 0 reg\n+ - description: USXGMII 0 reg\n+ - description: HSGMII rate adaption 0 reg\n+ - description: PCS MAC 1 reg\n+ - description: HSGMII AN 1 reg\n+ - description: HSGMII PCS 1 reg\n+ - description: MULTI SGMII 1 reg\n+ - description: USXGMII 1 reg\n+ - description: HSGMII rate adaption 1 reg\n+ - description: PCS Analog register\n+ - description: PCS PMA (Physical Medium Attachment) 0 register\n+ - description: PCS PMA (Physical Medium Attachment) 1 register\n+\n+ reg-names:\n+ items:\n+ - const: pcs_mac0\n+ - const: hsgmii_an0\n+ - const: hsgmii_pcs0\n+ - const: multi_sgmii0\n+ - const: usxgmii0\n+ - const: hsgmii_rate_adp0\n+ - const: pcs_mac1\n+ - const: hsgmii_an1\n+ - const: hsgmii_pcs1\n+ - const: multi_sgmii1\n+ - const: usxgmii1\n+ - const: hsgmii_rate_adp1\n+ - const: pcs_ana\n+ - const: pcs_pma0\n+ - const: pcs_pma1\n+\n+ phys: false\n+\n+ \"#pcs-cells\":\n+ const: 1\n+\n+ required:\n+ - airoha,scu\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ const: airoha,an7581-pcs-usb\n+\n+ then:\n+ properties:\n+ reg:\n+ items:\n+ - description: PCS MAC reg\n+ - description: HSGMII AN reg\n+ - description: HSGMII PCS reg\n+ - description: MULTI SGMII reg\n+ - description: HSGMII rate adaption reg\n+ - description: PCS Analog register\n+\n+ reg-names:\n+ items:\n+ - const: pcs_mac\n+ - const: hsgmii_an\n+ - const: hsgmii_pcs\n+ - const: multi_sgmii\n+ - const: hsgmii_rate_adp\n+ - const: pcs_ana\n+\n+ airoha,scu: false\n+\n+ \"#pcs-cells\":\n+ const: 0\n+\n+ required:\n+ - phys\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include \u003cdt-bindings/phy/phy.h\u003e\n+\n+ pcs@1fa08000 {\n+ compatible = \"airoha,an7581-pcs-pon\";\n+ reg = \u003c0x1fa08000 0x1000\u003e,\n+ \u003c0x1fa80000 0x60\u003e,\n+ \u003c0x1fa80a00 0x164\u003e,\n+ \u003c0x1fa84000 0x450\u003e,\n+ \u003c0x1fa85900 0x338\u003e,\n+ \u003c0x1fa86000 0x300\u003e,\n+ \u003c0x1fa8a000 0x1000\u003e,\n+ \u003c0x1fa8b000 0x1000\u003e;\n+ reg-names = \"pcs_mac\", \"hsgmii_an\", \"hsgmii_pcs\",\n+ \"multi_sgmii\", \"usxgmii\",\n+ \"hsgmii_rate_adp\", \"pcs_ana\", \"pcs_pma\";\n+\n+ airoha,scu = \u003c\u0026scuclk\u003e;\n+ #pcs-cells = \u003c0\u003e;\n+ };\n+\n+ pcs@1fa09000 {\n+ compatible = \"airoha,an7581-pcs-eth\";\n+ reg = \u003c0x1fa09000 0x1000\u003e,\n+ \u003c0x1fa70000 0x60\u003e,\n+ \u003c0x1fa70a00 0x164\u003e,\n+ \u003c0x1fa74000 0x450\u003e,\n+ \u003c0x1fa75900 0x338\u003e,\n+ \u003c0x1fa76000 0x300\u003e,\n+ \u003c0x1fa7a000 0x1000\u003e,\n+ \u003c0x1fa7b000 0x1000\u003e;\n+ reg-names = \"pcs_mac\", \"hsgmii_an\", \"hsgmii_pcs\",\n+ \"multi_sgmii\", \"usxgmii\",\n+ \"hsgmii_rate_adp\", \"pcs_ana\", \"pcs_pma\";\n+\n+ airoha,scu = \u003c\u0026scuclk\u003e;\n+ #pcs-cells = \u003c0\u003e;\n+ };\n+\n+ pcs@1fa04000 {\n+ compatible = \"airoha,an7581-pcs-pcie\";\n+ reg = \u003c0x1fa04000 0x1000\u003e,\n+ \u003c0x1fa50000 0x60\u003e,\n+ \u003c0x1fa50a00 0x164\u003e,\n+ \u003c0x1fa54000 0x450\u003e,\n+ \u003c0x1fa55900 0x338\u003e,\n+ \u003c0x1fa56000 0x300\u003e,\n+ \u003c0x1fa05000 0x1000\u003e,\n+ \u003c0x1fa60000 0x60\u003e,\n+ \u003c0x1fa60a00 0x164\u003e,\n+ \u003c0x1fa64000 0x450\u003e,\n+ \u003c0x1fa65900 0x338\u003e,\n+ \u003c0x1fa66000 0x300\u003e,\n+ \u003c0x1fa5a000 0x1000\u003e,\n+ \u003c0x1fa5b000 0x1000\u003e,\n+ \u003c0x1fa5c000 0x1000\u003e;\n+ reg-names = \"pcs_mac0\", \"hsgmii_an0\", \"hsgmii_pcs0\",\n+ \"multi_sgmii0\", \"usxgmii0\",\n+ \"hsgmii_rate_adp0\",\n+ \"pcs_mac1\", \"hsgmii_an1\", \"hsgmii_pcs1\",\n+ \"multi_sgmii1\", \"usxgmii1\",\n+ \"hsgmii_rate_adp1\",\n+ \"pcs_ana\", \"pcs_pma0\", \"pcs_pma1\";\n+\n+ airoha,scu = \u003c\u0026scuclk\u003e;\n+ #pcs-cells = \u003c1\u003e;\n+ };\n+\n+ pcs@1fa07000 {\n+ compatible = \"airoha,an7581-pcs-usb\";\n+ reg = \u003c0x1fa07000 0x1000\u003e,\n+ \u003c0x1fa90000 0x60\u003e,\n+ \u003c0x1fa90a00 0x164\u003e,\n+ \u003c0x1fa94000 0x450\u003e,\n+ \u003c0x1fa96000 0x300\u003e,\n+ \u003c0x1fa9a000 0x600\u003e;\n+ reg-names = \"pcs_mac\", \"hsgmii_an\", \"hsgmii_pcs\",\n+ \"multi_sgmii\", \"hsgmii_rate_adp\",\"pcs_ana\";\n+\n+ phys = \u003c\u0026usb0_phy PHY_TYPE_USB3\u003e;\n+\n+ #pcs-cells = \u003c0\u003e;\n+ };\ndiff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst\nindex 44a422ad3b055..3fce8f6ac089e 100644\n--- a/Documentation/networking/index.rst\n+++ b/Documentation/networking/index.rst\n@@ -28,6 +28,7 @@ Contents:\n net_failover\n page_pool\n phy\n+ pcs\n sfp-phylink\n alias\n bridge\ndiff --git a/Documentation/networking/pcs.rst b/Documentation/networking/pcs.rst\nnew file mode 100644\nindex 0000000000000..2cae702319484\n--- /dev/null\n+++ b/Documentation/networking/pcs.rst\n@@ -0,0 +1,234 @@\n+.. SPDX-License-Identifier: GPL-2.0\n+\n+=============\n+PCS Subsystem\n+=============\n+\n+The PCS (Physical Coding Sublayer) subsystem handles the registration and lookup\n+of PCS devices. These devices contain the upper sublayers of the Ethernet\n+physical layer, generally handling framing, scrambling, and encoding tasks. PCS\n+devices may also include PMA (Physical Medium Attachment) components. PCS\n+devices transfer data between the Link-layer MAC device, and the rest of the\n+physical layer, typically via a serdes. The output of the serdes may be\n+connected more-or-less directly to the medium when using fiber-optic or\n+backplane connections (1000BASE-SX, 1000BASE-KX, etc). It may also communicate\n+with a separate PHY (such as over SGMII) which handles the connection to the\n+medium (such as 1000BASE-T).\n+\n+Remark on usage of .mac_select_pcs and fw_node PCS\n+--------------------------------------------------\n+\n+There are generally two ways to look up a PCS device.\n+\n+1. MAC OP struct .mac_select_pcs (considered deprecated)\n+2. Internal PCS handling with ``num_possible_pcs`` and ``fill_available_pcs``\n+\n+Implementation 1 leaves the entire handling of the PCS to the MAC\n+driver with the selection of the PCS driven by .mac_select_pcs.\n+Custom implementations are required if the PCS is external to the MAC\n+and needs to be handled by a separate driver.\n+\n+Implementation 2 makes the phylink core code to select the PCS\n+provided by ``num_possible_pcs`` and ``fill_available_pcs`` either\n+via internal MAC handling or firmware node (fwnode)\n+\n+Implementation 1 is considered deprecated and it's suggested to\n+switch to implementation 2 and where possible switch to firmware\n+node design.\n+\n+.. _pcs_fwnode:\n+\n+Looking up PCS Devices (fwnode implementation)\n+-----------------------------------------------\n+\n+The lookup of a PCS device follows the common producer/consumer implementation\n+used by similar subsystems with a ``#pcs-cells`` on the producer and a\n+``pcs-handle`` property on the consumer::\n+\n+ pcs: pcs {\n+ // ...\n+ #pcs-cells = \u003c0\u003e;\n+ };\n+\n+ ethernet-controller {\n+ // ...\n+ pcs-handle = \u003c\u0026pcs\u003e;\n+ };\n+\n+On :c:func:`phylink_create`, phylink will use the ``num_possible_pcs``\n+value and ``fill_available_pcs`` helper function in\n+:c:struct:`phylink_config` to compose the list of available PCS that can be\n+used for the phylink instance.\n+\n+Phylink will then internally handle the selection of the correct PCS for\n+the requested interface mode based on the interface modes configured in\n+``pcs_interfaces`` in :c:struct:`phylink_config` struct and\n+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.\n+\n+A PCS is considered eligible when the requested interface mode is present\n+in both ``pcs_interfaces`` in :c:struct:`phylink_config` struct and\n+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.\n+\n+``supported_interfaces`` describes all interface modes supported by the MAC,\n+whereas ``pcs_interfaces`` identifies the subset that require PCS selection.\n+\n+For the special implementation where the PCS is internal or part of the MAC\n+and a dedicated driver is not needed, it's possible to leave the implementation\n+of the PCS to the MAC driver and just implement the ``num_possible_pcs``\n+value and ``fill_available_pcs`` helper function in\n+:c:struct:`phylink_config` referencing the local :c:struct:`phylink_pcs`\n+struct allocated from the MAC driver.\n+\n+.. _pcs_consumer:\n+\n+Using PCS Devices\n+-----------------\n+\n+It's mandatory to either implement the ``mac_select_pcs`` callback\n+of :c:struct:`phylink_mac_ops` or ``num_possible_pcs`` and ``fill_available_pcs``\n+of :c:struct:`phylink_config` to use a PCS for a MAC.\n+\n+The fwnode implementation exposes simple helpers to parse the PCS from\n+the fwnode :c:func:`fwnode_phylink_pcs_count` and\n+:c:func:`fwnode_phylink_pcs_parse`. The :c:func:`fwnode_phylink_pcs_count` helper\n+takes the fwnode where the ``pcs-handle`` should be parsed and return the\n+number of PCS entries described in the fwnode.\n+The :c:func:`fwnode_phylink_pcs_parse` helper takes three arguments,\n+the fwnode where the ``pcs-handle`` should be parsed, an allocated array\n+of :c:struct:`phylink_pcs` pointer where to put the parsed PCS from the fwnode\n+and the maximum number of PCS to parse.\n+Contrary to :c:func:`fwnode_phylink_pcs_count`, :c:func:`fwnode_phylink_pcs_parse`\n+helper fills the allocated array with ONLY the available PCS and return the\n+number of available PCS found. PCS that returns -ENODEV will be skipped and\n+won't be inserted in the allocated array.\n+\n+A phylink instance may use multiple PCS devices. The maximum number is reported\n+through ``num_possible_pcs``.\n+\n+It's mandatory to specify for what interface a PCS is needed. This can be done\n+by filling the ``pcs_interfaces`` in :c:struct:`phylink_config` struct.\n+If the requested interface mode is not present in this bitmask, phylink does\n+not search for a PCS for that specific mode. (example MAC doesn't need a PCS\n+for SGMII but require one for USXGMII)\n+\n+With the use of the :c:func:`fwnode_phylink_pcs_parse` a common implementation\n+is the following::\n+\n+ static int mac_fill_available_pcs(struct phylink_config *config,\n+ \t\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t\t\t unsigned int num_possible_pcs)\n+ {\n+ \tstruct device *dev = config-\u003edev;\n+\n+ \treturn fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,\n+\t\t\t\t\t\t num_possible_pcs);\n+ }\n+\n+ static int mac_setup_phylink(struct net_device *netdev)\n+ {\n+ struct phylink_config *config;\n+\n+ // ...\n+\n+ config-\u003edev = \u0026netdev-\u003edev;\n+\n+ // ...\n+\n+ // Parse possible PCS and fill num_possible_pcs.\n+ config-\u003enum_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(\u0026netdev-\u003edev));\n+ config-\u003efill_available_pcs = mac_fill_available_pcs;\n+\n+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config-\u003esupported_interfaces);\n+ __set_bit(PHY_INTERFACE_MODE_SGMII, config-\u003esupported_interfaces);\n+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, config-\u003esupported_interfaces);\n+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config-\u003esupported_interfaces);\n+\n+ // PCS required only for USXGMII\n+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config-\u003epcs_interfaces);\n+\n+ phylink = phylink_create(config, //...\n+\n+It's worth to mention that it's phylink code that takes care of allocating\n+the array of :c:struct:`phylink_pcs` pointer for ``fill_available_pcs``\n+callback based on the value set in ``num_possible_pcs`` for\n+:c:struct:`phylink_config` struct.\n+\n+The ``fill_available_pcs`` callback must not write more than\n+``num_possible_pcs`` entries. The third argument may be used to validate\n+that there is enough space to fill all the available PCS in the passed array\n+of :c:struct:`phylink_pcs` pointer.\n+\n+The ``fill_available_pcs`` callback is called only on :c:func:`phylink_create`\n+and is used only to compose the initial available PCS list. Ownership of PCS\n+is held by phylink.\n+\n+.. _pcs_producer:\n+\n+Writing PCS Drivers\n+-------------------\n+\n+To write a PCS driver, first implement :c:struct:`phylink_pcs_ops`. Then,\n+register your PCS in your probe function using :c:func:`fwnode_pcs_add_provider`.\n+The :c:func:`fwnode_pcs_add_provider` takes three arguments, the fwnode where\n+the PCS provider should be registered to, a xlate function to return the requested\n+PCS based on ``#pcs-cells`` and a pointer to reference private data for the xlate\n+function.\n+\n+The PCS will then be registered to a global list of PCS provider that the\n+PCS fwnode implementation will use to parse it.\n+\n+For the simple case where the PCS driver expose a single PCS,\n+:c:func:`fwnode_pcs_simple_xlate` can be used as the xlate function.\n+\n+You must call :c:func:`fwnode_pcs_del_provider` from your remove function\n+on driver detach.\n+\n+A devm variant, :c:func:`devm_fwnode_pcs_add_provider`, is available to\n+automatically release the PCS provider on driver detach.\n+\n+It's worth to mention that xlate function MUST reference already allocated\n+:c:struct:`phylink_pcs` pointer and MUST NOT dynamically allocate new PCS.\n+The returned pointer is used to identify the PCS across provider lookup and\n+removal notifications.\n+\n+Late PCS registration handling\n+------------------------------\n+\n+It's possible that a PCS becomes available after the MAC finished probing.\n+Contrary to the usual producer/consumer implementation, when a PCS is not\n+registered and can't be found, the fwnode parser helper returns ``-ENODEV``\n+instead of ``-EPROBE_DEFER``.\n+\n+This is to prevent race condition with particular devices that register\n+MAC and PCS with USB or PCIe and require the MAC to be registered before\n+the PCS.\n+\n+The phylink logic correctly handle this special case and keep the phylink\n+instance in a fail condition.\n+\n+The PCS fwnode implementation provides a notifier to which each phylink\n+instance with a non-empty ``pcs_interfaces`` in :c:type:`phylink_config`\n+registers. When a new PCS provider is registered, the notifier is called\n+triggering the :c:func:`pcs_provider_notify` function.\n+\n+Function :c:func:`pcs_provider_notify` will check if the just added PCS\n+should be used by the phylink instance. If it should be used then,\n+it's added to the internal list of available PCS and a phylink major\n+config is forced.\n+\n+If a phylink instance was in a failure state, with the just added PCS\n+now part of the available PCS internal phylink list, provided all other\n+conditions are satisfied, the configuration is retried and the failure\n+condition is cleared.\n+\n+API Reference\n+-------------\n+\n+.. kernel-doc:: include/linux/phylink.h\n+ :identifiers: phylink_pcs\n+\n+.. kernel-doc:: include/linux/pcs/pcs.h\n+ :internal:\n+\n+.. kernel-doc:: include/linux/pcs/pcs-provider.h\n+ :internal:\ndiff --git a/Documentation/networking/sfp-phylink.rst b/Documentation/networking/sfp-phylink.rst\nindex 5bf285d73e8a1..306505118eba9 100644\n--- a/Documentation/networking/sfp-phylink.rst\n+++ b/Documentation/networking/sfp-phylink.rst\n@@ -311,33 +311,20 @@ this documentation.\n \n priv-\u003epcs = lynx_pcs_create_mdiodev(bus, 0);\n \n- Some PCS can be recovered based on firmware information:\n+ PCS that should be recovered based on firmware information should implement\n+ the external PCS as a :ref:`PCS provider \u003cpcs_producer\u003e` and reference it\n+ with the use of PCS fwnode helper :ref:`PCS fwnode helper \u003cpcs_fwnode\u003e`.\n \n- .. code-block:: c\n-\n- priv-\u003epcs = lynx_pcs_create_fwnode(of_fwnode_handle(node));\n-\n-12. Populate the :c:func:`mac_select_pcs` callback and add it to your\n- :c:type:`struct phylink_mac_ops \u003cphylink_mac_ops\u003e` set of ops. This function\n- must return a pointer to the relevant :c:type:`struct phylink_pcs \u003cphylink_pcs\u003e`\n- that will be used for the requested link configuration:\n-\n- .. code-block:: c\n-\n- static struct phylink_pcs *foo_select_pcs(struct phylink_config *config,\n- phy_interface_t interface)\n- {\n- struct foo_priv *priv = container_of(config, struct foo_priv,\n- phylink_config);\n-\n- if ( /* 'interface' needs a PCS to function */ )\n- return priv-\u003epcs;\n+12. Populate the :c:var:`num_possible_pcs` value and\n+ :c:func:`fill_available_pcs` callback and add it to your\n+ :c:type:`struct phylink_config \u003cphylink_config\u003e`.\n \n- return NULL;\n- }\n+ Refer to :ref:`Documentation/networking/pcs.rst \u003cpcs_consumer\u003e` for\n+ further details and examples.\n \n- See :c:func:`mvpp2_select_pcs` for an example of a driver that has multiple\n- internal PCS.\n+ Notice that the previous implementation of populating\n+ :c:func:`mac_select_pcs` is considered deprecated in favor of the new\n+ described above.\n \n 13. Fill-in all the :c:type:`phy_interface_t \u003cphy_interface_t\u003e` (i.e. all MAC to\n PHY link modes) that your MAC can output. The following example shows a\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex 509b35b5a0e7a..d8533e36941c7 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -9759,6 +9759,15 @@ F:\tinclude/uapi/linux/if_bridge.h\n F:\tinclude/linux/netfilter_bridge/\n F:\tnet/bridge/\n \n+ETHERNET PCS SUBSYSTEM\n+M:\tChristian Marangi \u003cansuelsmth@gmail.com\u003e\n+L:\tnetdev@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/networking/pcs.rst\n+F:\tdrivers/net/pcs/pcs.c\n+F:\tinclude/linux/pcs/pcs-provider.h\n+F:\tinclude/linux/pcs/pcs.h\n+\n ETHERNET PHY LIBRARY\n M:\tAndrew Lunn \u003candrew@lunn.ch\u003e\n M:\tHeiner Kallweit \u003chkallweit1@gmail.com\u003e\ndiff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig\nindex 1f6640a15fc94..5c54a07d2a768 100644\n--- a/drivers/net/ethernet/airoha/Kconfig\n+++ b/drivers/net/ethernet/airoha/Kconfig\n@@ -20,6 +20,8 @@ config NET_AIROHA\n \tdepends on NET_DSA || !NET_DSA\n \tselect NET_AIROHA_NPU\n \tselect PAGE_POOL\n+\tselect PCS_AIROHA\n+\tselect PHYLINK\n \thelp\n \t This driver supports the gigabit ethernet MACs in the\n \t Airoha SoC family.\ndiff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c\nindex b164a78ddac9d..81a8da721c13a 100644\n--- a/drivers/net/ethernet/airoha/airoha_eth.c\n+++ b/drivers/net/ethernet/airoha/airoha_eth.c\n@@ -6,6 +6,7 @@\n #include \u003clinux/of.h\u003e\n #include \u003clinux/of_net.h\u003e\n #include \u003clinux/of_reserved_mem.h\u003e\n+#include \u003clinux/pcs/pcs.h\u003e\n #include \u003clinux/platform_device.h\u003e\n #include \u003clinux/tcp.h\u003e\n #include \u003clinux/u64_stats_sync.h\u003e\n@@ -2194,10 +2195,18 @@ static int airoha_dev_open(struct net_device *netdev)\n \t\treturn -EBUSY;\n \t}\n \n+\terr = phylink_of_phy_connect(dev-\u003ephylink, netdev-\u003edev.of_node, 0);\n+\tif (err) {\n+\t\tnetdev_err(netdev, \"could not attach PHY: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\tphylink_start(dev-\u003ephylink);\n+\n \tnetif_tx_start_all_queues(netdev);\n \terr = airoha_set_vip_for_gdm_port(dev, true);\n \tif (err)\n-\t\treturn err;\n+\t\tgoto err_phy_stop;\n \n \tif (netdev_uses_dsa(netdev))\n \t\tairoha_fe_set(qdma-\u003eeth, REG_GDM_INGRESS_CFG(port-\u003eid),\n@@ -2219,6 +2228,12 @@ static int airoha_dev_open(struct net_device *netdev)\n \t\tairoha_dev_lro_enable(dev);\n \n \treturn 0;\n+\n+err_phy_stop:\n+\tphylink_stop(dev-\u003ephylink);\n+\tphylink_disconnect_phy(dev-\u003ephylink);\n+\n+\treturn err;\n }\n \n static int airoha_dev_stop(struct net_device *netdev)\n@@ -2226,6 +2241,8 @@ static int airoha_dev_stop(struct net_device *netdev)\n \tstruct airoha_gdm_dev *dev = netdev_priv(netdev);\n \tstruct airoha_gdm_port *port = dev-\u003eport;\n \n+\tphylink_stop(dev-\u003ephylink);\n+\n \tnetif_tx_disable(netdev);\n \tairoha_set_vip_for_gdm_port(dev, false);\n \n@@ -2239,6 +2256,8 @@ static int airoha_dev_stop(struct net_device *netdev)\n \tif (netdev-\u003efeatures \u0026 NETIF_F_LRO)\n \t\tairoha_dev_lro_disable(dev);\n \n+\tphylink_disconnect_phy(dev-\u003ephylink);\n+\n \treturn 0;\n }\n \n@@ -2829,6 +2848,24 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,\n \t} while (u64_stats_fetch_retry(\u0026dev-\u003estats.syncp, start));\n }\n \n+static int\n+airoha_ethtool_get_link_ksettings(struct net_device *netdev,\n+\t\t\t\t struct ethtool_link_ksettings *cmd)\n+{\n+\tstruct airoha_gdm_dev *dev = netdev_priv(netdev);\n+\n+\treturn phylink_ethtool_ksettings_get(dev-\u003ephylink, cmd);\n+}\n+\n+static int\n+airoha_ethtool_set_link_ksettings(struct net_device *netdev,\n+\t\t\t\t const struct ethtool_link_ksettings *cmd)\n+{\n+\tstruct airoha_gdm_dev *dev = netdev_priv(netdev);\n+\n+\treturn phylink_ethtool_ksettings_set(dev-\u003ephylink, cmd);\n+}\n+\n static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev,\n \t\t\t\t\t int channel, enum tx_sched_mode mode,\n \t\t\t\t\t const u16 *weights, u8 n_weights)\n@@ -3696,7 +3733,8 @@ static const struct ethtool_ops airoha_ethtool_ops = {\n \t.get_drvinfo\t\t= airoha_ethtool_get_drvinfo,\n \t.get_eth_mac_stats = airoha_ethtool_get_mac_stats,\n \t.get_rmon_stats\t\t= airoha_ethtool_get_rmon_stats,\n-\t.get_link_ksettings\t= phy_ethtool_get_link_ksettings,\n+\t.get_link_ksettings\t= airoha_ethtool_get_link_ksettings,\n+\t.set_link_ksettings\t= airoha_ethtool_set_link_ksettings,\n \t.get_link\t\t= ethtool_op_get_link,\n };\n \n@@ -3752,6 +3790,155 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,\n \treturn false;\n }\n \n+/* Nothing to do in MAC, everything is handled in PCS */\n+static void airoha_mac_config(struct phylink_config *config, unsigned int mode,\n+\t\t\t const struct phylink_link_state *state)\n+{\n+}\n+\n+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,\n+\t\t\t unsigned int mode, phy_interface_t interface,\n+\t\t\t int speed, int duplex, bool tx_pause, bool rx_pause)\n+{\n+\tstruct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev,\n+\t\t\t\t\t\t phylink_config);\n+\tstruct airoha_gdm_port *port = dev-\u003eport;\n+\tstruct airoha_eth *eth = dev-\u003eeth;\n+\tu32 frag_size_tx, frag_size_rx;\n+\n+\t/* TX/RX frag is configured only for GDM4 */\n+\tif (port-\u003eid != AIROHA_GDM4_IDX)\n+\t\treturn;\n+\n+\tswitch (speed) {\n+\tcase SPEED_10000:\n+\tcase SPEED_5000:\n+\t\tfrag_size_tx = 8;\n+\t\tfrag_size_rx = 8;\n+\t\tbreak;\n+\tcase SPEED_2500:\n+\t\tfrag_size_tx = 2;\n+\t\tfrag_size_rx = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tfrag_size_tx = 1;\n+\t\tfrag_size_rx = 0;\n+\t\tbreak;\n+\t}\n+\n+\tmutex_lock(\u0026port-\u003elink_lock);\n+\n+\t/* Configure TX/RX frag based on speed */\n+\tif (dev-\u003enbq == 1) {\n+\t\tairoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG,\n+\t\t\t GDM4_SGMII1_TX_FRAG_SIZE_MASK,\n+\t\t\t FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK,\n+\t\t\t\t\t frag_size_tx));\n+\n+\t\tairoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG,\n+\t\t\t GDM4_SGMII1_RX_FRAG_SIZE_MASK,\n+\t\t\t FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK,\n+\t\t\t\t\t frag_size_rx));\n+\t} else {\n+\t\tairoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG,\n+\t\t\t GDM4_SGMII0_TX_FRAG_SIZE_MASK,\n+\t\t\t FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK,\n+\t\t\t\t\t frag_size_tx));\n+\n+\t\tairoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG,\n+\t\t\t GDM4_SGMII0_RX_FRAG_SIZE_MASK,\n+\t\t\t FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK,\n+\t\t\t\t\t frag_size_rx));\n+\t}\n+\n+\tmutex_unlock(\u0026port-\u003elink_lock);\n+}\n+\n+/* Nothing to do in MAC, everything is handled in PCS */\n+static void airoha_mac_link_down(struct phylink_config *config, unsigned int mode,\n+\t\t\t\t phy_interface_t interface)\n+{\n+}\n+\n+static const struct phylink_mac_ops airoha_phylink_ops = {\n+\t.mac_config = airoha_mac_config,\n+\t.mac_link_up = airoha_mac_link_up,\n+\t.mac_link_down = airoha_mac_link_down,\n+};\n+\n+static int airoha_fill_available_pcs(struct phylink_config *config,\n+\t\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t\t unsigned int num_possible_pcs)\n+{\n+\tstruct device *dev = config-\u003edev;\n+\n+\treturn fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,\n+\t\t\t\t\tnum_possible_pcs);\n+}\n+\n+static int airoha_setup_phylink(struct net_device *netdev)\n+{\n+\tstruct airoha_gdm_dev *dev = netdev_priv(netdev);\n+\tstruct device_node *np = netdev-\u003edev.of_node;\n+\tstruct airoha_gdm_port *port = dev-\u003eport;\n+\tstruct phylink_config *config;\n+\tphy_interface_t phy_mode;\n+\tstruct phylink *phylink;\n+\tint err;\n+\n+\terr = of_get_phy_mode(np, \u0026phy_mode);\n+\tif (err) {\n+\t\tdev_err(\u0026netdev-\u003edev, \"incorrect phy-mode\\n\");\n+\t\treturn err;\n+\t}\n+\n+\tconfig = \u0026dev-\u003ephylink_config;\n+\tconfig-\u003edev = \u0026netdev-\u003edev;\n+\tconfig-\u003etype = PHYLINK_NETDEV;\n+\n+\t/*\n+\t * GDM1 only supports internal for Embedded Switch\n+\t * and doesn't require a PCS.\n+\t */\n+\tif (port-\u003eid == AIROHA_GDM1_IDX) {\n+\t\tconfig-\u003emac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |\n+\t\t\t\t\t MAC_10000FD;\n+\n+\t\t__set_bit(PHY_INTERFACE_MODE_INTERNAL,\n+\t\t\t config-\u003esupported_interfaces);\n+\t} else {\n+\t\tconfig-\u003emac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |\n+\t\t\t\t\t MAC_10 | MAC_100 | MAC_1000 |\n+\t\t\t\t\t MAC_2500FD | MAC_5000FD | MAC_10000FD;\n+\n+\t\tconfig-\u003enum_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config-\u003edev));\n+\t\tconfig-\u003efill_available_pcs = airoha_fill_available_pcs;\n+\n+\t\t__set_bit(PHY_INTERFACE_MODE_SGMII,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_1000BASEX,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_2500BASEX,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_10GBASER,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_USXGMII,\n+\t\t\t config-\u003esupported_interfaces);\n+\n+\t\tphy_interface_copy(config-\u003epcs_interfaces,\n+\t\t\t\t config-\u003esupported_interfaces);\n+\t}\n+\n+\tphylink = phylink_create(config, of_fwnode_handle(np),\n+\t\t\t\t phy_mode, \u0026airoha_phylink_ops);\n+\tif (IS_ERR(phylink))\n+\t\treturn PTR_ERR(phylink);\n+\n+\tdev-\u003ephylink = phylink;\n+\n+\treturn 0;\n+}\n+\n static int airoha_alloc_gdm_device(struct airoha_eth *eth,\n \t\t\t\t struct airoha_gdm_port *port,\n \t\t\t\t int nbq, struct device_node *np)\n@@ -3815,7 +4002,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,\n \tdev-\u003enbq = nbq;\n \tport-\u003edevs[index] = dev;\n \n-\treturn 0;\n+\treturn airoha_setup_phylink(netdev);\n }\n \n static int airoha_alloc_gdm_port(struct airoha_eth *eth,\n@@ -3851,6 +4038,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,\n \n \tport-\u003eid = id;\n \tspin_lock_init(\u0026port-\u003estats_lock);\n+\tmutex_init(\u0026port-\u003elink_lock);\n \teth-\u003eports[p] = port;\n \n \terr = airoha_metadata_dst_alloc(port);\n@@ -4047,6 +4235,8 @@ static int airoha_probe(struct platform_device *pdev)\n \t\t\tnetdev = netdev_from_priv(dev);\n \t\t\tif (netdev-\u003ereg_state == NETREG_REGISTERED)\n \t\t\t\tunregister_netdev(netdev);\n+\t\t\tif (dev-\u003ephylink)\n+\t\t\t\tphylink_destroy(dev-\u003ephylink);\n \t\t\tof_node_put(netdev-\u003edev.of_node);\n \t\t}\n \t\tairoha_metadata_dst_free(port);\n@@ -4085,6 +4275,7 @@ static void airoha_remove(struct platform_device *pdev)\n \n \t\t\tnetdev = netdev_from_priv(dev);\n \t\t\tunregister_netdev(netdev);\n+\t\t\tphylink_destroy(dev-\u003ephylink);\n \t\t\tof_node_put(netdev-\u003edev.of_node);\n \t\t}\n \t\tairoha_metadata_dst_free(port);\ndiff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h\nindex d270729e22ff9..909e75fec2797 100644\n--- a/drivers/net/ethernet/airoha/airoha_eth.h\n+++ b/drivers/net/ethernet/airoha/airoha_eth.h\n@@ -612,6 +612,9 @@ struct airoha_gdm_dev {\n \t * QDMA migration.\n \t */\n \tspinlock_t txq_lock[AIROHA_NUM_NETDEV_TX_RINGS];\n+\n+\tstruct phylink *phylink;\n+\tstruct phylink_config phylink_config;\n };\n \n struct airoha_gdm_port {\n@@ -621,6 +624,8 @@ struct airoha_gdm_port {\n \n \t/* protect concurrent hw_stats accesses */\n \tspinlock_t stats_lock;\n+\t/* protect concurrent GDM4 register access */\n+\tstruct mutex link_lock;\n \n \tstruct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];\n };\ndiff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h\nindex 07dd04859fde8..94d53d4c3ab70 100644\n--- a/drivers/net/ethernet/airoha/airoha_regs.h\n+++ b/drivers/net/ethernet/airoha/airoha_regs.h\n@@ -371,6 +371,18 @@\n #define IP_FRAGMENT_PORT_MASK\t\tGENMASK(8, 5)\n #define IP_FRAGMENT_NBQ_MASK\t\tGENMASK(4, 0)\n \n+#define REG_FE_GDM4_TMBI_FRAG\t\t0x2028\n+#define GDM4_SGMII1_TX_WEIGHT_MASK\tGENMASK(31, 26)\n+#define GDM4_SGMII1_TX_FRAG_SIZE_MASK\tGENMASK(25, 16)\n+#define GDM4_SGMII0_TX_WEIGHT_MASK\tGENMASK(15, 10)\n+#define GDM4_SGMII0_TX_FRAG_SIZE_MASK\tGENMASK(9, 0)\n+\n+#define REG_FE_GDM4_RMBI_FRAG\t\t0x202c\n+#define GDM4_SGMII1_RX_WEIGHT_MASK\tGENMASK(31, 26)\n+#define GDM4_SGMII1_RX_FRAG_SIZE_MASK\tGENMASK(25, 16)\n+#define GDM4_SGMII0_RX_WEIGHT_MASK\tGENMASK(15, 10)\n+#define GDM4_SGMII0_RX_FRAG_SIZE_MASK\tGENMASK(9, 0)\n+\n #define REG_MC_VLAN_EN\t\t\t0x2100\n #define MC_VLAN_EN_MASK\t\t\tBIT(0)\n \ndiff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig\nindex e417fd66f660a..8fae619f24322 100644\n--- a/drivers/net/pcs/Kconfig\n+++ b/drivers/net/pcs/Kconfig\n@@ -5,6 +5,12 @@\n \n menu \"PCS device drivers\"\n \n+config FWNODE_PCS\n+\tbool \"PCS Firmware Node\"\n+\tdepends on ACPI || OF || COMPILE_TEST\n+\thelp\n+\t Firmware node PCS accessors\n+\n config PCS_XPCS\n \ttristate \"Synopsys DesignWare Ethernet XPCS\"\n \tselect PHYLINK\n@@ -35,4 +41,6 @@ config PCS_RZN1_MIIC\n \t Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to\n \t RMII/RGMII, or can be set in pass-through mode for MII.\n \n+source \"drivers/net/pcs/airoha/Kconfig\"\n+\n endmenu\ndiff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile\nindex 4f7920618b900..91593aa8d9266 100644\n--- a/drivers/net/pcs/Makefile\n+++ b/drivers/net/pcs/Makefile\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0\n # Makefile for Linux PCS drivers\n \n+obj-$(CONFIG_FWNODE_PCS)\t+= pcs.o\n pcs_xpcs-$(CONFIG_PCS_XPCS)\t:= pcs-xpcs.o pcs-xpcs-plat.o \\\n \t\t\t\t pcs-xpcs-nxp.o pcs-xpcs-wx.o\n \n@@ -8,3 +9,5 @@ obj-$(CONFIG_PCS_XPCS)\t\t+= pcs_xpcs.o\n obj-$(CONFIG_PCS_LYNX)\t\t+= pcs-lynx.o\n obj-$(CONFIG_PCS_MTK_LYNXI)\t+= pcs-mtk-lynxi.o\n obj-$(CONFIG_PCS_RZN1_MIIC)\t+= pcs-rzn1-miic.o\n+\n+obj-$(CONFIG_PCS_AIROHA)\t+= airoha/\ndiff --git a/drivers/net/pcs/airoha/Kconfig b/drivers/net/pcs/airoha/Kconfig\nnew file mode 100644\nindex 0000000000000..1aa4c0d33b87d\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/Kconfig\n@@ -0,0 +1,13 @@\n+# SPDX-License-Identifier: GPL-2.0-only\n+\n+config PCS_AIROHA\n+\ttristate\n+\tselect FWNODE_PCS\n+\n+config PCS_AIROHA_AN7581\n+\ttristate \"Airoha AN7581 PCS driver\"\n+\tdepends on ARCH_AIROHA || COMPILE_TEST\n+\tselect PCS_AIROHA\n+\thelp\n+\t This module provides helper to phylink for managing the Airoha\n+\t AN7581 PCS for SoC Ethernet and PON SERDES.\ndiff --git a/drivers/net/pcs/airoha/Makefile b/drivers/net/pcs/airoha/Makefile\nnew file mode 100644\nindex 0000000000000..c5201d5cc3569\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/Makefile\n@@ -0,0 +1,7 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+obj-$(CONFIG_PCS_AIROHA)\t:= pcs-airoha.o\n+pcs-airoha-objs\t\t\t:= pcs-airoha-common.o\n+ifdef CONFIG_PCS_AIROHA_AN7581\n+pcs-airoha-objs\t\t\t+= pcs-an7581.o\n+endif\ndiff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c\nnew file mode 100644\nindex 0000000000000..d9ec0e97b746a\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c\n@@ -0,0 +1,1303 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+\n+#include \u003clinux/device.h\u003e\n+#include \u003clinux/mfd/syscon.h\u003e\n+#include \u003clinux/of.h\u003e\n+#include \u003clinux/of_platform.h\u003e\n+#include \u003clinux/pcs/pcs-provider.h\u003e\n+#include \u003clinux/phy/phy.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/platform_device.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+#include \u003clinux/reset.h\u003e\n+#include \u003clinux/rtnetlink.h\u003e\n+\n+#include \"pcs-airoha.h\"\n+\n+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,\n+\t\t\t\t phy_interface_t interface)\n+{\n+\tu32 xsi_sel;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\txsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\tdefault:\n+\t\txsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;\n+\t}\n+\n+\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_SSR3,\n+\t\t\t AIROHA_SCU_ETH_XSI_SEL,\n+\t\t\t xsi_sel);\n+}\n+\n+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,\n+\t\t\t\t phy_interface_t interface)\n+{\n+\tu32 xsi_sel, wan_sel;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_SGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_HSGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\tdefault:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_USXGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_USXGMII;\n+\t}\n+\n+\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_SSTR,\n+\t\t\t AIROHA_SCU_PON_XSI_SEL,\n+\t\t\t xsi_sel);\n+\n+\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_WAN_CONF,\n+\t\t\t AIROHA_SCU_WAN_SEL,\n+\t\t\t wan_sel);\n+}\n+\n+static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tu32 xsi_sel;\n+\n+\tif (index == 0) {\n+\t\tswitch (interface) {\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\t\txsi_sel = AIROHA_SCU_PCIE_XSI0_HSGMII;\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tdefault:\n+\t\t\txsi_sel = AIROHA_SCU_PCIE_XSI0_USXGMII;\n+\t\t}\n+\n+\t\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_SSTR,\n+\t\t\t\t AIROHA_SCU_PCIE_XSI0_SEL,\n+\t\t\t\t xsi_sel);\n+\t} else {\n+\t\tswitch (interface) {\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\t\txsi_sel = AIROHA_SCU_PCIE_XSI1_HSGMII;\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tdefault:\n+\t\t\txsi_sel = AIROHA_SCU_PCIE_XSI1_USXGMII;\n+\t\t}\n+\n+\t\tregmap_update_bits(priv-\u003escu, AIROHA_SCU_SSTR,\n+\t\t\t\t AIROHA_SCU_PCIE_XSI1_SEL,\n+\t\t\t\t xsi_sel);\n+\t}\n+}\n+\n+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,\n+\t\t\t\tint index, phy_interface_t interface)\n+{\n+\tconst struct airoha_pcs_match_data *data = priv-\u003edata;\n+\tint ret;\n+\n+\tswitch (data-\u003eport_type) {\n+\tcase AIROHA_PCS_ETH:\n+\t\tairoha_pcs_setup_scu_eth(priv, interface);\n+\t\tbreak;\n+\tcase AIROHA_PCS_PON:\n+\t\tairoha_pcs_setup_scu_pon(priv, interface);\n+\t\tbreak;\n+\tcase AIROHA_PCS_PCIE:\n+\t\tairoha_pcs_setup_scu_pcie(priv, index, interface);\n+\t\tbreak;\n+\tcase AIROHA_PCS_USB:\n+\t\tbreak;\n+\t}\n+\n+\tret = reset_control_bulk_assert(ARRAY_SIZE(priv-\u003ersts),\n+\t\t\t\t\tpriv-\u003ersts);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = reset_control_bulk_deassert(ARRAY_SIZE(priv-\u003ersts),\n+\t\t\t\t\t priv-\u003ersts);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\tregmap_set_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\tAIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\t/* Disable Hibernation */\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,\n+\t\t\t AIROHA_PCS_USXGMII_SPEED_SEL_H);\n+\n+\t/* FIXME: wait Airoha */\n+\t/* Avoid PCS sending garbage to MAC in some HW revision (E0) */\n+\tregmap_write(maps-\u003eusxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);\n+}\n+\n+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\tregmap_clear_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\t AIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\tregmap_update_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\t AIROHA_PCS_TBI_10B_MODE,\n+\t\t\t priv-\u003ephy ? 0 : AIROHA_PCS_TBI_10B_MODE);\n+}\n+\n+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\tregmap_clear_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\t AIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\tAIROHA_PCS_TBI_10B_MODE);\n+\n+\tregmap_update_bits(maps-\u003ehsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,\n+\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));\n+\n+\tregmap_update_bits(maps-\u003ehsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,\n+\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));\n+}\n+\n+static void airoha_pcs_init(struct airoha_pcs_priv *priv,\n+\t\t\t int index, phy_interface_t interface)\n+{\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tairoha_pcs_init_sgmii(priv, index);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tairoha_pcs_init_hsgmii(priv, index);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tairoha_pcs_init_usxgmii(priv, index);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\t/* Disable every interrupt */\n+\tregmap_clear_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);\n+\n+\t/* Clear interrupt */\n+\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);\n+\n+\tregmap_clear_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |\n+\t\t\t AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);\n+}\n+\n+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\n+\t/* Disable every Interrupt */\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);\n+\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);\n+\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,\n+\t\t\t AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);\n+\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,\n+\t\t\t AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |\n+\t\t\t AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);\n+\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,\n+\t\t\t AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);\n+\n+\t/* Clear any pending interrupt */\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,\n+\t\t\tAIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_E_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_T_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_D_INT);\n+\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,\n+\t\t\tAIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_LINK_UP_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_HI_BER_ST_INT);\n+\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,\n+\t\t\tAIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);\n+\n+\t/* Interrupt saddly seems to be not weel supported for Link Down.\n+\t * PCS Poll is a must to correctly read and react on Cable Deatch\n+\t * as only cable attach interrupt are fired and Link Down interrupt\n+\t * are fired only in special case like AN restart.\n+\t */\n+}\n+\n+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\treturn airoha_pcs_interrupt_init_sgmii(priv, index);\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\treturn airoha_pcs_interrupt_init_usxgmii(priv, index);\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,\n+\t\t\t\t unsigned int neg_mode, int index,\n+\t\t\t\t struct phylink_link_state *state)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 bmsr = 0, lpa = 0;\n+\n+\tregmap_read(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,\n+\t\t \u0026bmsr);\n+\tregmap_read(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,\n+\t\t \u0026lpa);\n+\n+\tbmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) \u0026 bmsr;\n+\tlpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY \u0026 lpa;\n+\n+\tphylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);\n+}\n+\n+static void airoha_pcs_get_state_hsgmii(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\tstruct phylink_link_state *state)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 bmsr = 0;\n+\n+\tregmap_read(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,\n+\t\t \u0026bmsr);\n+\n+\tbmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |\n+\t\tAIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) \u0026 bmsr;\n+\n+\tstate-\u003elink = !!(bmsr \u0026 BMSR_LSTATUS);\n+\tstate-\u003ean_complete = !!(bmsr \u0026 BMSR_ANEGCOMPLETE);\n+\tstate-\u003espeed = SPEED_2500;\n+\tstate-\u003eduplex = DUPLEX_FULL;\n+}\n+\n+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\t struct phylink_link_state *state)\n+{\n+\tconst struct airoha_pcs_match_data *data = priv-\u003edata;\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 an_done = 0, lpa = 0;\n+\n+\t/* Trigger HW workaround if needed. If an error is reported,\n+\t * consider link down and test again later.\n+\t */\n+\tif (data-\u003erxlock_workaround \u0026\u0026 data-\u003erxlock_workaround(priv, index)) {\n+\t\tstate-\u003elink = false;\n+\t\treturn;\n+\t}\n+\n+\t/* Toggle AN Status */\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,\n+\t\t\tAIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,\n+\t\t\t AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);\n+\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, \u0026lpa);\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_2, \u0026an_done);\n+\n+\tstate-\u003elink = !!(lpa \u0026 MDIO_USXGMII_LINK);\n+\tstate-\u003ean_complete = !!(an_done \u0026 AIROHA_PCS_USXGMII_PCS_AN_COMPLETE);\n+\n+\tphylink_decode_usxgmii_word(state, lpa);\n+}\n+\n+static void airoha_pcs_get_state_10gbaser(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\t struct phylink_link_state *state)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 status = 0, curr_mode = 0;\n+\n+\t/* Toggle AN Status */\n+\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,\n+\t\t\tAIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);\n+\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,\n+\t\t\t AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);\n+\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1,\n+\t\t \u0026status);\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, \u0026curr_mode);\n+\n+\tstate-\u003elink = !!(status \u0026 AIROHA_PCS_USXGMII_RX_LINK_STUS);\n+\n+\tswitch (curr_mode \u0026 AIROHA_PCS_USXGMII_CUR_USXGMII_MODE) {\n+\tcase AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G:\n+\t\tstate-\u003espeed = SPEED_10000;\n+\t\tbreak;\n+\tcase AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G:\n+\t\tstate-\u003espeed = SPEED_5000;\n+\t\tbreak;\n+\tcase AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G:\n+\t\tstate-\u003espeed = SPEED_2500;\n+\t\tbreak;\n+\tdefault:\n+\t\tstate-\u003espeed = SPEED_UNKNOWN;\n+\t\treturn;\n+\t}\n+\n+\tstate-\u003eduplex = DUPLEX_FULL;\n+}\n+\n+static void airoha_pcs_get_state(struct phylink_pcs *pcs,\n+\t\t\t\t unsigned int neg_mode,\n+\t\t\t\t struct phylink_link_state *state)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\n+\tswitch (state-\u003einterface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tairoha_pcs_get_state_sgmii(priv, neg_mode, port-\u003eindex, state);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tairoha_pcs_get_state_hsgmii(priv, port-\u003eindex, state);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\tairoha_pcs_get_state_usxgmii(priv, port-\u003eindex, state);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tairoha_pcs_get_state_10gbaser(priv, port-\u003eindex, state);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,\n+\t\t\t phy_interface_t interface,\n+\t\t\t const unsigned long *advertising,\n+\t\t\t bool permit_pause_to_mac)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tconst struct airoha_pcs_match_data *data;\n+\tstruct airoha_pcs_maps *maps;\n+\tint index = port-\u003eindex;\n+\tu32 rate_adapt;\n+\tint ret;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\tport-\u003einterface = interface;\n+\tdata = priv-\u003edata;\n+\n+\t/* Apply Analog and Digital configuration for PCS */\n+\tif (data-\u003ebringup) {\n+\t\tret = data-\u003ebringup(priv, index, interface);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Set final configuration for various modes */\n+\tairoha_pcs_init(priv, index, interface);\n+\n+\t/* Configure Interrupt for various modes */\n+\tairoha_pcs_interrupt_init(priv, index, interface);\n+\n+\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |\n+\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;\n+\n+\tif (interface == PHY_INTERFACE_MODE_SGMII)\n+\t\trate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS;\n+\n+\t/* AN Auto Settings (Rate Adaptation) */\n+\tregmap_update_bits(maps-\u003ehsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |\n+\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);\n+\n+\tif (interface == PHY_INTERFACE_MODE_USXGMII ||\n+\t interface == PHY_INTERFACE_MODE_10GBASER) {\n+\t\tif (interface == PHY_INTERFACE_MODE_USXGMII) {\n+\t\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)\n+\t\t\t\tregmap_set_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\t\tAIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t\t\tAIROHA_PCS_USXGMII_AN_ENABLE);\n+\t\t\telse\n+\t\t\t\tregmap_clear_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\t\t AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t\t\t AIROHA_PCS_USXGMII_AN_ENABLE);\n+\n+\t\t\tregmap_clear_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);\n+\t\t} else {\n+\t\t\tregmap_clear_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_AN_ENABLE);\n+\n+\t\t\tregmap_set_bits(maps-\u003eusxgmii_pcs,\n+\t\t\t\t\tAIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,\n+\t\t\t\t\tAIROHA_PCS_USXGMII_RATE_UPDATE_MODE);\n+\t\t}\n+\t}\n+\n+\t/* Clear any force bit that my be set by bootloader */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t interface == PHY_INTERFACE_MODE_1000BASEX ||\n+\t interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_clear_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,\n+\t\t\t\t AIROHA_PCS_LINK_MODE_P0 |\n+\t\t\t\t AIROHA_PCS_FORCE_SPD_MODE_P0 |\n+\t\t\t\t AIROHA_PCS_FORCE_LINKDOWN_P0 |\n+\t\t\t\t AIROHA_PCS_FORCE_LINKUP_P0);\n+\t}\n+\n+\t/* Toggle Rate Adaption for SGMII/HSGMII mode */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t interface == PHY_INTERFACE_MODE_1000BASEX ||\n+\t interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)\n+\t\t\tregmap_clear_bits(maps-\u003ehsgmii_rate_adp,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);\n+\t\telse\n+\t\t\tregmap_set_bits(maps-\u003ehsgmii_rate_adp,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_P0_DIS_MII_MODE);\n+\t}\n+\n+\t/* Setup AN Link Timer */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t interface == PHY_INTERFACE_MODE_1000BASEX) {\n+\t\tu32 an_timer;\n+\n+\t\tan_timer = phylink_get_link_timer_ns(interface);\n+\n+\t\t/* Value needs to be shifted by 4, seems value is internally * 16 */\n+\t\tregmap_update_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,\n+\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,\n+\t\t\t\t\t an_timer \u003e\u003e 4));\n+\n+\t\tregmap_update_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,\n+\t\t\t\t AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,\n+\t\t\t\t\t an_timer \u003e\u003e 4));\n+\t}\n+\n+\t/* Setup SGMII AN and advertisement in DEV_ABILITY */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\t\tint advertise = phylink_mii_c22_pcs_encode_advertisement(interface,\n+\t\t\t\t\t\t\t\t\t\t advertising);\n+\t\t\tif (advertise \u003c 0)\n+\t\t\t\treturn advertise;\n+\n+\t\t\tregmap_update_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,\n+\t\t\t\t\t\t advertise));\n+\n+\t\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\t\t} else {\n+\t\t\tregmap_clear_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\t\t}\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_clear_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\n+\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_TX_ENABLE);\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t interface == PHY_INTERFACE_MODE_1000BASEX) {\n+\t\tu32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;\n+\n+\t\t/* Toggle SGMII or 1000base-x mode */\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII)\n+\t\t\tif_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN;\n+\n+\t\tif (neg_mode \u0026 PHYLINK_PCS_NEG_INBAND)\n+\t\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);\n+\t\telse\n+\t\t\tregmap_clear_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);\n+\n+\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\t\t/* Clear force speed bits and MAC mode */\n+\t\t\tregmap_clear_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_MAC_MODE |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);\n+\t\t} else {\n+\t\t\t/* Enable compatibility with MAC PCS Layer */\n+\t\t\tif_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;\n+\n+\t\t\t/* AN off force rate adaption, speed is set later in Link Up */\n+\t\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_PCS_MAC_MODE |\n+\t\t\t\t\tAIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);\n+\t\t}\n+\n+\t\tregmap_update_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);\n+\n+\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_TX_ENABLE |\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_MODE2_EN);\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_1000BASEX \u0026\u0026\n+\t neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\tregmap_set_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\t\tAIROHA_PCS_SGMII_SEND_AN_ERR_EN);\n+\n+\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,\n+\t\t\t\tAIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY);\n+\t}\n+\n+\t/* Configure Flow Control on XFI */\n+\tregmap_update_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,\n+\t\t\t permit_pause_to_mac ?\n+\t\t\t\tAIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :\n+\t\t\t\t0);\n+\n+\treturn 0;\n+}\n+\n+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\n+\tswitch (port-\u003einterface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tregmap_set_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);\n+\t\tudelay(3);\n+\t\tregmap_clear_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\tregmap_set_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\tAIROHA_PCS_USXGMII_AN_RESTART);\n+\t\tudelay(3);\n+\t\tregmap_clear_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t AIROHA_PCS_USXGMII_AN_RESTART);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,\n+\t\t\t phy_interface_t interface, int speed, int duplex)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tconst struct airoha_pcs_match_data *data;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\tdata = priv-\u003edata;\n+\n+\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\t\tregmap_update_bits(maps-\u003ehsgmii_rate_adp,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));\n+\t\t\tudelay(1);\n+\t\t\tregmap_update_bits(maps-\u003ehsgmii_rate_adp,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |\n+\t\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));\n+\t\t}\n+\t} else {\n+\t\tif (interface == PHY_INTERFACE_MODE_USXGMII ||\n+\t\t interface == PHY_INTERFACE_MODE_10GBASER) {\n+\t\t\tu32 mode;\n+\t\t\tu32 rate_adapt;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_10000:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_10000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_5000:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_5000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_2500:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_2500;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_1000:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_100;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\t/* Not supported */\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\t/* Force USXGMII to selected speed */\n+\t\t\tregmap_update_bits(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,\n+\t\t\t\t\t AIROHA_PCS_USXGMII_MODE, mode);\n+\n+\t\t\tif (interface == PHY_INTERFACE_MODE_10GBASER)\n+\t\t\t\tregmap_update_bits(maps-\u003ehsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |\n+\t\t\t\t\t\t rate_adapt);\n+\t\t}\n+\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t\t interface == PHY_INTERFACE_MODE_1000BASEX) {\n+\t\t\tu32 force_speed;\n+\t\t\tu32 rate_adapt;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_1000:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_10:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\t/* Not supported */\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tregmap_update_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |\n+\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,\n+\t\t\t\t\t force_speed | rate_adapt);\n+\t\t}\n+\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t\t interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\t\tu32 ck_gen_mode;\n+\t\t\tu32 speed_reg;\n+\t\t\tu32 if_mode;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_2500:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_1000:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_1G;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_100M;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_10:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_10M;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\t\t\tregmap_update_bits(maps-\u003ehsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,\n+\t\t\t\t\t\t if_mode);\n+\n+\t\t\t\tregmap_update_bits(maps-\u003ehsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,\n+\t\t\t\t\t\t ck_gen_mode |\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);\n+\t\t\t}\n+\n+\t\t\tregmap_update_bits(maps-\u003emulti_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,\n+\t\t\t\t\t AIROHA_PCS_LINK_MODE_P0 |\n+\t\t\t\t\t AIROHA_PCS_FORCE_SPD_MODE_P0,\n+\t\t\t\t\t speed_reg |\n+\t\t\t\t\t AIROHA_PCS_FORCE_SPD_MODE_P0);\n+\t\t}\n+\t}\n+\n+\tif (data-\u003elink_up)\n+\t\tdata-\u003elink_up(priv, port-\u003eindex);\n+\n+\t/* BPI BMI enable */\n+\tregmap_clear_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\t AIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\t AIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\t AIROHA_PCS_XFI_TXMBI_STOP);\n+}\n+\n+static void airoha_pcs_link_down(struct phylink_pcs *pcs)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\n+\t/* MPI MBI disable */\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMBI_STOP);\n+}\n+\n+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,\n+\t\t\t\t phy_interface_t interface)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\n+\t/* Select HSGMII or USXGMII in SCU regs */\n+\tairoha_pcs_setup_scu(priv, port-\u003eindex, interface);\n+\n+\t/* MPI MBI disable */\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMBI_STOP);\n+\n+\t/* Write 1 to trigger reset and clear */\n+\tregmap_clear_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,\n+\t\t\t AIROHA_PCS_XFI_MAC_LOGIC_RST);\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,\n+\t\t\tAIROHA_PCS_XFI_MAC_LOGIC_RST);\n+\n+\tusleep_range(1000, 2000);\n+\n+\t/* Clear XFI MAC counter */\n+\tregmap_set_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,\n+\t\t\tAIROHA_PCS_XFI_GLB_CNT_CLR);\n+}\n+\n+static int airoha_pcs_post_config(struct phylink_pcs *pcs,\n+\t\t\t\t phy_interface_t interface)\n+{\n+\tstruct airoha_pcs_port *port = to_airoha_pcs_port(pcs);\n+\tstruct airoha_pcs_priv *priv = port-\u003epriv;\n+\tstruct airoha_pcs_maps *maps;\n+\n+\tmaps = \u0026priv-\u003emaps[port-\u003eindex];\n+\n+\t/* Frag disable */\n+\tregmap_update_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_RX_FRAG_LEN,\n+\t\t\t FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31));\n+\tregmap_update_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_TX_FRAG_LEN,\n+\t\t\t FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31));\n+\n+\t/* IPG NUM */\n+\tregmap_update_bits(maps-\u003epcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t AIROHA_PCS_XFI_IPG_NUM,\n+\t\t\t FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10));\n+\n+\treturn 0;\n+}\n+\n+static unsigned int airoha_pcs_inband_caps(struct phylink_pcs *pcs,\n+\t\t\t\t\t phy_interface_t interface)\n+{\n+\treturn LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;\n+}\n+\n+static const struct phylink_pcs_ops airoha_pcs_ops = {\n+\t.pcs_inband_caps = airoha_pcs_inband_caps,\n+\t.pcs_pre_config = airoha_pcs_pre_config,\n+\t.pcs_post_config = airoha_pcs_post_config,\n+\t.pcs_get_state = airoha_pcs_get_state,\n+\t.pcs_config = airoha_pcs_config,\n+\t.pcs_an_restart = airoha_pcs_an_restart,\n+\t.pcs_link_up = airoha_pcs_link_up,\n+\t.pcs_link_down = airoha_pcs_link_down,\n+};\n+\n+static int airoha_pcs_init_named_regmap(struct platform_device *pdev,\n+\t\t\t\t\tconst char *name, struct regmap **regmap)\n+{\n+\tstruct regmap_config config = {\n+\t\t.reg_bits = 32,\n+\t\t.val_bits = 32,\n+\t\t.reg_stride = 4,\n+\t};\n+\tvoid __iomem *base;\n+\n+\tbase = devm_platform_ioremap_resource_byname(pdev, name);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tconfig.name = name;\n+\t*regmap = devm_regmap_init_mmio(\u0026pdev-\u003edev, base, \u0026config);\n+\n+\treturn PTR_ERR_OR_ZERO(*regmap);\n+}\n+\n+static int airoha_pcs_alloc_maps(struct platform_device *pdev,\n+\t\t\t\t struct airoha_pcs_priv *priv)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[0];\n+\tint ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_mac\", \u0026maps-\u003epcs_mac);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_an\", \u0026maps-\u003ehsgmii_an);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_pcs\", \u0026maps-\u003ehsgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_rate_adp\", \u0026maps-\u003ehsgmii_rate_adp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"multi_sgmii\", \u0026maps-\u003emulti_sgmii);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"usxgmii\", \u0026maps-\u003eusxgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_pma\", \u0026priv-\u003epcs_pma[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn airoha_pcs_init_named_regmap(pdev, \"pcs_ana\", \u0026priv-\u003epcs_ana);\n+}\n+\n+static int airoha_pcs_usb_alloc_maps(struct platform_device *pdev,\n+\t\t\t\t struct airoha_pcs_priv *priv)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[0];\n+\tint ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_mac\", \u0026maps-\u003epcs_mac);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_an\", \u0026maps-\u003ehsgmii_an);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_pcs\", \u0026maps-\u003ehsgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_rate_adp\", \u0026maps-\u003ehsgmii_rate_adp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"multi_sgmii\", \u0026maps-\u003emulti_sgmii);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn airoha_pcs_init_named_regmap(pdev, \"pcs_ana\", \u0026priv-\u003epcs_ana);\n+}\n+\n+static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev,\n+\t\t\t\t struct airoha_pcs_priv *priv)\n+{\n+\tstruct airoha_pcs_maps *maps = priv-\u003emaps;\n+\tint ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_mac0\", \u0026maps[0].pcs_mac);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_an0\", \u0026maps[0].hsgmii_an);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_pcs0\", \u0026maps[0].hsgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_rate_adp0\", \u0026maps[0].hsgmii_rate_adp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"multi_sgmii0\", \u0026maps[0].multi_sgmii);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"usxgmii0\", \u0026maps[0].usxgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_mac1\", \u0026maps[1].pcs_mac);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_an1\", \u0026maps[1].hsgmii_an);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_pcs1\", \u0026maps[1].hsgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"hsgmii_rate_adp1\", \u0026maps[1].hsgmii_rate_adp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"multi_sgmii1\", \u0026maps[1].multi_sgmii);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"usxgmii1\", \u0026maps[1].usxgmii_pcs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_pma0\", \u0026priv-\u003epcs_pma[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = airoha_pcs_init_named_regmap(pdev, \"pcs_pma1\", \u0026priv-\u003epcs_pma[1]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn airoha_pcs_init_named_regmap(pdev, \"pcs_ana\", \u0026priv-\u003epcs_ana);\n+}\n+\n+static struct phylink_pcs *airoha_pcs_xlate(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t void *data)\n+{\n+\tstruct airoha_pcs_priv *priv = data;\n+\tstruct device *dev = priv-\u003edev;\n+\tu64 index = 0;\n+\n+\tswitch (priv-\u003edata-\u003eport_type) {\n+\tcase AIROHA_PCS_ETH:\n+\tcase AIROHA_PCS_PON:\n+\tcase AIROHA_PCS_USB:\n+\t\tif (pcsspec-\u003enargs) {\n+\t\t\tdev_err(dev, \"invalid number of cells in 'pcs-handle' property\\n\");\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\n+\t\tbreak;\n+\tcase AIROHA_PCS_PCIE:\n+\t\tif (pcsspec-\u003enargs != 1) {\n+\t\t\tdev_err(dev, \"invalid number of cells in 'pcs-handle' property\\n\");\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\n+\t\tbreak;\n+\t}\n+\n+\tif (pcsspec-\u003enargs)\n+\t\tindex = pcsspec-\u003eargs[0];\n+\n+\tif (index \u003e= priv-\u003edata-\u003enum_port) {\n+\t\tdev_err(dev, \"invalid index cell in 'pcs-handle' property\\n\");\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\n+\treturn \u0026priv-\u003eports[index].pcs;\n+}\n+\n+static int airoha_pcs_probe(struct platform_device *pdev)\n+{\n+\tconst struct airoha_pcs_match_data *data;\n+\tstruct fwnode_pcs_provider *pcs_provider;\n+\tstruct device *dev = \u0026pdev-\u003edev;\n+\tstruct airoha_pcs_priv *priv;\n+\tint index, ret;\n+\n+\tdata = of_device_get_match_data(dev);\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv-\u003eports = devm_kcalloc(dev, data-\u003enum_port,\n+\t\t\t\t sizeof(*priv-\u003eports), GFP_KERNEL);\n+\tif (!priv-\u003eports)\n+\t\treturn -ENOMEM;\n+\n+\tpriv-\u003edev = dev;\n+\tpriv-\u003edata = data;\n+\n+\tif (data-\u003eport_type == AIROHA_PCS_USB) {\n+\t\tstruct phy *phy;\n+\n+\t\tphy = devm_phy_get(dev, NULL);\n+\t\tif (IS_ERR(phy))\n+\t\t\treturn dev_err_probe(dev, PTR_ERR(phy), \"failed to get phy\\n\");\n+\n+\t\tpriv-\u003ephy = phy;\n+\t}\n+\n+\tswitch (data-\u003eport_type) {\n+\tcase AIROHA_PCS_ETH:\n+\tcase AIROHA_PCS_PON:\n+\t\tret = airoha_pcs_alloc_maps(pdev, priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tbreak;\n+\tcase AIROHA_PCS_PCIE:\n+\t\tret = airoha_pcs_pcie_alloc_maps(pdev, priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tbreak;\n+\tcase AIROHA_PCS_USB:\n+\t\tret = airoha_pcs_usb_alloc_maps(pdev, priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tbreak;\n+\t}\n+\n+\tif (data-\u003ealloc_regmap_fields) {\n+\t\tret = data-\u003ealloc_regmap_fields(priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* SCU is used to toggle XFI or HSGMII in global SoC registers */\n+\tif (!priv-\u003ephy) {\n+\t\tpriv-\u003escu = syscon_regmap_lookup_by_phandle(dev-\u003eof_node, \"airoha,scu\");\n+\t\tif (IS_ERR(priv-\u003escu))\n+\t\t\treturn PTR_ERR(priv-\u003escu);\n+\t}\n+\n+\tpriv-\u003ersts[0].id = \"mac\";\n+\tpriv-\u003ersts[1].id = \"phy\";\n+\tret = devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(priv-\u003ersts),\n+\t\t\t\t\t\t\t priv-\u003ersts);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"failed to get bulk reset lines\\n\");\n+\n+\t/* For Ethernet PCS, read the AN7581 SoC revision to check if\n+\t * manual rx calibration is needed. This is only limited to\n+\t * any SoC revision before E2.\n+\t */\n+\tif (device_is_compatible(dev, \"airoha,an7581-pcs-eth\")) {\n+\t\tu32 val;\n+\n+\t\tret = regmap_read(priv-\u003escu, AIROHA_SCU_PDIDR, \u0026val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tif (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) \u003c 0x2)\n+\t\t\tpriv-\u003emanual_rx_calib = true;\n+\t}\n+\n+\tfor (index = 0; index \u003c data-\u003enum_port; index++) {\n+\t\tstruct airoha_pcs_port *port = \u0026priv-\u003eports[index];\n+\n+\t\tport-\u003epriv = priv;\n+\t\tport-\u003eindex = index;\n+\t\tport-\u003epcs.poll = true;\n+\t\tport-\u003epcs.ops = \u0026airoha_pcs_ops;\n+\n+\t\tswitch (data-\u003eport_type) {\n+\t\tcase AIROHA_PCS_ETH:\n+\t\tcase AIROHA_PCS_PON:\n+\t\tcase AIROHA_PCS_PCIE:\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_10GBASER,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_USXGMII,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\tfallthrough;\n+\t\tcase AIROHA_PCS_USB:\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_SGMII,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_1000BASEX,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_2500BASEX,\n+\t\t\t\t port-\u003epcs.supported_interfaces);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\tpcs_provider = devm_fwnode_pcs_add_provider(dev, dev_fwnode(dev),\n+\t\t\t\t\t\t airoha_pcs_xlate, priv);\n+\tif (IS_ERR(pcs_provider))\n+\t\treturn PTR_ERR(pcs_provider);\n+\n+\treturn 0;\n+}\n+\n+static const struct airoha_pcs_match_data an7581_pcs_eth = {\n+\t.num_port = 1,\n+\t.port_type = AIROHA_PCS_ETH,\n+\t.alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,\n+\t.bringup = an7581_pcs_bringup,\n+\t.link_up = an7581_pcs_phya_link_up,\n+\t.rxlock_workaround = an7581_pcs_rxlock_workaround,\n+};\n+\n+static const struct airoha_pcs_match_data an7581_pcs_pon = {\n+\t.num_port = 1,\n+\t.port_type = AIROHA_PCS_PON,\n+\t.alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,\n+\t.bringup = an7581_pcs_bringup,\n+\t.link_up = an7581_pcs_phya_link_up,\n+};\n+\n+static const struct airoha_pcs_match_data an7581_pcs_pcie = {\n+\t.num_port = 2,\n+\t.port_type = AIROHA_PCS_PCIE,\n+\t.alloc_regmap_fields = an7581_pcs_pcie_alloc_regmap_fields,\n+\t.bringup = an7581_pcs_bringup,\n+\t.link_up = an7581_pcs_phya_link_up,\n+};\n+\n+static const struct airoha_pcs_match_data an7581_pcs_usb = {\n+\t.num_port = 1,\n+\t.port_type = AIROHA_PCS_USB,\n+\t.bringup = an7581_pcs_usb_bringup,\n+};\n+\n+static const struct of_device_id airoha_pcs_of_table[] = {\n+\t{ .compatible = \"airoha,an7581-pcs-eth\", .data = \u0026an7581_pcs_eth },\n+\t{ .compatible = \"airoha,an7581-pcs-pon\", .data = \u0026an7581_pcs_pon },\n+\t{ .compatible = \"airoha,an7581-pcs-pcie\", .data = \u0026an7581_pcs_pcie },\n+\t{ .compatible = \"airoha,an7581-pcs-usb\", .data = \u0026an7581_pcs_usb },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);\n+\n+static struct platform_driver airoha_pcs_driver = {\n+\t.driver = {\n+\t\t.name\t = \"airoha-pcs\",\n+\t\t.of_match_table = airoha_pcs_of_table,\n+\t},\n+\t.probe = airoha_pcs_probe,\n+};\n+module_platform_driver(airoha_pcs_driver);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"Airoha PCS driver\");\n+MODULE_AUTHOR(\"Christian Marangi \u003cansuelsmth@gmail.com\u003e\");\ndiff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h\nnew file mode 100644\nindex 0000000000000..8a76d51b5d2c8\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/pcs-airoha.h\n@@ -0,0 +1,1311 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+\n+#include \u003clinux/bitfield.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/platform_device.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+#include \u003clinux/reset.h\u003e\n+\n+/* SCU*/\n+#define AIROHA_SCU_PDIDR\t\t\t0x5c\n+#define AIROHA_SCU_PRODUCT_ID\t\t\tGENMASK(15, 0)\n+#define AIROHA_SCU_WAN_CONF\t\t\t0x70\n+#define AIROHA_SCU_WAN_SEL\t\t\tGENMASK(7, 0)\n+#define AIROHA_SCU_WAN_SEL_SGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)\n+#define AIROHA_SCU_WAN_SEL_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)\n+#define AIROHA_SCU_WAN_SEL_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)\n+#define AIROHA_SCU_SSR3\t\t\t\t0x94\n+#define AIROHA_SCU_ETH_XSI_SEL\t\tGENMASK(14, 13)\n+#define AIROHA_SCU_ETH_XSI_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)\n+#define AIROHA_SCU_ETH_XSI_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)\n+#define AIROHA_SCU_SSTR\t\t\t\t0x9c\n+#define AIROHA_SCU_PCIE_XSI0_SEL\t\tGENMASK(14, 13)\n+#define AIROHA_SCU_PCIE_XSI0_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x1)\n+#define AIROHA_SCU_PCIE_XSI0_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x2)\n+#define AIROHA_SCU_PCIE_XSI1_SEL\t\tGENMASK(12, 11)\n+#define AIROHA_SCU_PCIE_XSI1_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x1)\n+#define AIROHA_SCU_PCIE_XSI1_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x2)\n+#define AIROHA_SCU_PON_XSI_SEL\t\tGENMASK(10, 9)\n+#define AIROHA_SCU_PON_XSI_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)\n+#define AIROHA_SCU_PON_XSI_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)\n+\n+/* XFI_MAC */\n+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG\t\t0x0\n+#define AIROHA_PCS_XFI_RX_FRAG_LEN\t\tGENMASK(26, 22)\n+#define AIROHA_PCS_XFI_TX_FRAG_LEN\t\tGENMASK(21, 17)\n+#define AIROHA_PCS_XFI_IPG_NUM\t\tGENMASK(15, 10)\n+#define AIROHA_PCS_XFI_TX_FC_EN\t\tBIT(5)\n+#define AIROHA_PCS_XFI_RX_FC_EN\t\tBIT(4)\n+#define AIROHA_PCS_XFI_RXMPI_STOP\t\tBIT(3)\n+#define AIROHA_PCS_XFI_RXMBI_STOP\t\tBIT(2)\n+#define AIROHA_PCS_XFI_TXMPI_STOP\t\tBIT(1)\n+#define AIROHA_PCS_XFI_TXMBI_STOP\t\tBIT(0)\n+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST\t0x10\n+#define AIROHA_PCS_XFI_MAC_LOGIC_RST\t\tBIT(0)\n+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH\t\t0x60\n+#define AIROHA_PCS_XFI_MAC_MACADDRH\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL\t\t0x64\n+#define AIROHA_PCS_XFI_MAC_MACADDRL\t\tGENMASK(31, 0)\n+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR\t\t0x100\n+#define AIROHA_PCS_XFI_GLB_CNT_CLR\t\tBIT(0)\n+\n+/* HSGMII_AN */\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0\t0x0\n+#define AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY\tBIT(15)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE\tBIT(12)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART\tBIT(9)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1\t0x4 /* BMSR */\n+#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4\t0x10\n+#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5\t0x14 /* LPA */\n+#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11\t0x2c\n+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER\tGENMASK(19, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13\t0x34\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)\n+#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)\n+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)\n+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)\n+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)\n+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)\n+#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN\tBIT(1)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60\n+#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE\tBIT(0)\n+\n+/* HSGMII_PCS */\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_1\t\t0x0\n+#define AIROHA_PCS_TBI_10B_MODE\t\tBIT(30)\n+#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN\tBIT(24)\n+#define AIROHA_PCS_REMOTE_FAULT_DIS\t\tBIT(12)\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_3\t\t0x8\n+#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME\tGENMASK(19, 0)\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_6\t\t0x14\n+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)\n+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)\n+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)\n+#define AIROHA_PCS_HSGMII_PCS_MAC_MODE\tBIT(8)\n+#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE\tBIT(4)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT\tBIT(1)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20\n+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)\n+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT\tBIT(4)\n+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)\n+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)\n+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)\n+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)\n+#define ARIOHA_PCS_HSGMII_PCS_STATE_2\t\t0x104\n+#define AIROHA_PCS_HSGMII_PCS_RX_SYNC\t\tBIT(5)\n+#define AIROHA_PCS_HSGMII_PCS_AN_DONE\t\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_INT_STATE\t\t0x15c\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS\tBIT(3)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC\tBIT(1)\n+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE\tBIT(0)\n+\n+/* HSGMII_ANA */\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6\t0x18\n+#define AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC\tBIT(20)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8\t0x20\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR GENMASK(11, 8)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 GENMASK(7, 4)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0 GENMASK(3, 0)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11\t0x2c\n+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED\tGENMASK(3, 2)\n+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x0)\n+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x1)\n+#define AIROHA_PCS_HSGMII_ANA_TPHY_MODE\tGENMASK(1, 0)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18\t0x48\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV\tGENMASK(28, 27)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19\t0x4c\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV GENMASK(15, 8)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_LV GENMASK(7, 0)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG GENMASK(2, 0)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_GND FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x0)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONFBK_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x1)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x2)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONREF_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x3)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_CKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x4)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_FBCKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x5)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_TX2500M_A FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x6)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_CDR_250M_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x7)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24\t0x60\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE GENMASK(31, 24)\n+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26\t0x68\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY GENMASK(7, 6)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x0)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x1)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x2)\n+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x3)\n+\n+/* MULTI_SGMII */\n+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0\t0x14\n+#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18\n+#define AIROHA_PCS_LINK_MODE_P0\t\tGENMASK(5, 4)\n+#define AIROHA_PCS_LINK_MODE_P0_2_5G\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)\n+#define AIROHA_PCS_LINK_MODE_P0_1G\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)\n+#define AIROHA_PCS_LINK_MODE_P0_100M\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)\n+#define AIROHA_PCS_LINK_MODE_P0_10M\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)\n+#define AIROHA_PCS_FORCE_SPD_MODE_P0\t\tBIT(2)\n+#define AIROHA_PCS_FORCE_LINKDOWN_P0\t\tBIT(1)\n+#define AIROHA_PCS_FORCE_LINKUP_P0\t\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0\t0x100\n+#define AIROHA_PCS_HSGMII_XFI_SEL\t\tBIT(28)\n+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL\t0x14c\n+#define AIROHA_PCS_HSGMII_PCS_INT\t\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15\t0x43c\n+#define AIROHA_PCS_LINK_STS_P0\t\tBIT(3)\n+#define AIROHA_PCS_SPEED_STS_P0\t\tGENMASK(2, 0)\n+#define AIROHA_PCS_SPEED_STS_P0_1G\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)\n+#define AIROHA_PCS_SPEED_STS_P0_100M\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)\n+#define AIROHA_PCS_SPEED_STS_P0_10M\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18\t0x448\n+#define AIROHA_PCS_P0_SGMII_IS_10\t\tBIT(2)\n+#define AIROHA_PCS_P0_SGMII_IS_100\t\tBIT(1)\n+#define AIROHA_PCS_P0_SGMII_IS_1000\t\tBIT(0)\n+\n+/* HSGMII_RATE_ADP */\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0\t0x0\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN\tBIT(4)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1\t0x4\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6\t0x18\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8\t0x20\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11\t0x2c\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)\n+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)\n+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0\t0x100\n+#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE\tBIT(31)\n+\n+/* USXGMII */\n+#define AIROHA_PCS_USXGMII_PCS_CTROL_1\t\t0x0\n+#define AIROHA_PCS_USXGMII_SPEED_SEL_H\tBIT(13)\n+#define AIROHA_PCS_USXGMII_PCS_STUS_1\t\t0x4\n+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS\tBIT(2)\n+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x1)\n+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_DOWN \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x0)\n+#define AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1 0x30\n+#define AIROHA_PCS_USXGMII_RX_LINK_STUS\tBIT(12)\n+#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)\n+#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)\n+#define AIROHA_PCS_USXGMII_PCS_BLK_LK\t\tBIT(0)\n+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116\t0x22c\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_0\t\t0x2c0\n+#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN\tBIT(24)\n+#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN\tBIT(16)\n+#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN\tBIT(8)\n+#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_1\t\t0x2c4\n+#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN\tBIT(24)\n+#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN\tBIT(16)\n+#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)\n+#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_2\t\t0x2c8\n+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)\n+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN\tBIT(16)\n+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN\tBIT(8)\n+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_3\t\t0x2cc\n+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)\n+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)\n+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN\tBIT(8)\n+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2\t0x2d8\n+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)\n+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT\tBIT(16)\n+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT\tBIT(8)\n+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3\t0x2dc\n+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)\n+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)\n+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT\tBIT(8)\n+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_4\t\t0x2e0\n+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4\t0x2e4\n+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0\t0x2f8\n+#define AIROHA_PCS_USXGMII_AN_RESTART\t\tBIT(8)\n+#define AIROHA_PCS_USXGMII_AN_ENABLE\t\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0\t0x310\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE\tGENMASK(30, 28)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)\n+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)\n+#define AIROHA_PCS_USXGMII_PARTNER_ABILITY\tGENMASK(15, 0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2\t0x318\n+#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE\tBIT(24)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6\t0x31c\n+#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7\t0x320\n+#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE\tBIT(12)\n+#define AIROHA_PCS_USXGMII_MODE\t\tGENMASK(10, 8)\n+#define AIROHA_PCS_USXGMII_MODE_10000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)\n+#define AIROHA_PCS_USXGMII_MODE_5000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1)\n+#define AIROHA_PCS_USXGMII_MODE_2500\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)\n+#define AIROHA_PCS_USXGMII_MODE_1000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)\n+#define AIROHA_PCS_USXGMII_MODE_100\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)\n+\n+/* PMA_PHYA */\n+#define AIROHA_PCS_ANA_PXP_CMN_EN\t\t0x0\n+#define AIROHA_PCS_ANA_CMN_EN\t\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN\t0x4\n+#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST\tGENMASK(29, 24)\n+#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS\tGENMASK(21, 16)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR\t\t0x8\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BWR\t\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BP\t\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BC\t\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BR\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC\t0xc\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE\tGENMASK(23, 16)\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION\tBIT(8)\n+#define AIROHA_PCS_ANA_JCPLL_LPF_BWC\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC\t0x10\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_KS\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_KF\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14\n+#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5\tBIT(24)\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 0x0\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 0x1\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 0x2\n+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 0x3\n+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY\t0x1c\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB\t\tBIT(8)\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY\t\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 0x4\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 0x5\n+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 0x6\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM\t0x20\n+#define AIROHA_PCS_ANA_JCPLL_SDM_OUT\t\tBIT(24)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_SDM_MODE\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_IFM\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN\t0x24\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 0x4\n+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_JCPLL_SDM_HREN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN\t0x28\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1\t0x1\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2\t0x2\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4\t0x3\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8\t0x4\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16\t0x6\n+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV\t\t0x2c\n+#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_JCPLL_VCODIV\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_JCPLL_VCODIV_1\t0x0\n+#define AIROHA_PCS_ANA_JCPLL_VCODIV_2\t0x1\n+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR\t0x30\n+#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI\tBIT(17)\n+#define AIROHA_PCS_ANA_JCPLL_SSC_EN\t\tBIT(16)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)\n+#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN\t0x34\n+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1\tGENMASK(23, 8)\n+#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA\t0x38\n+#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H\t0x48\n+#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_JCPLL_SPARE_L\t\tGENMASK(15, 8)\n+#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO\tBIT(5)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS\t0x50\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BC\t\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BR\t\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST\tGENMASK(13, 8)\n+#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS\tGENMASK(5, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP\t\t0x54\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION\tBIT(24)\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BWC\t\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BWR\t\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_TXPLL_LPF_BP\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE\t0x58\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_KF\t\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS\t0x5c\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 0x0\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 0x1\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 0x2\n+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 0x3\n+#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_TXPLL_KBAND_KS\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL\t0x64\n+#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB\t\tBIT(24)\n+#define AIROHA_PCS_ANA_TXPLL_RST_DLY\t\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4\t0x3\n+#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN\t0x68\n+#define AIROHA_PCS_ANA_TXPLL_SDM_MODE\t\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_IFM\t\tBIT(16)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15\t0x3\n+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD\t0x6c\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_HREN\t\tBIT(16)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_OUT\t\tBIT(8)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM\t0x3\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN\t0x70\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 0x1\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4\t0x3\n+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6\t0x4\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN\t0x74\n+#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX\t\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_TXPLL_VCODIV\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_TXPLL_VCODIV_1\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_VCODIV_2\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5\t0x0\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1\t0x1\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2\t0x2\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4\t0x3\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8\t0x4\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16\t0x6\n+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN\t0x78\n+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)\n+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN\t\t0x7c\n+#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI\tBIT(8)\n+#define AIROHA_PCS_ANA_TXPLL_SSC_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1\t0x80\n+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD\t0x84\n+#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_TXPLL_LDO_OUT\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF\t0x94\n+#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN\t\t0xc4\n+#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_TX_CKLDO_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL\t0xcc\n+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE\tBIT(24)\n+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL\t\tBIT(16)\n+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR 0x0\n+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES 0x1\n+#define AIROHA_PCS_ANA_PXP_RX_REV_0\t\t0xd4\n+#define AIROHA_PCS_ANA_RX_REV_1\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)\n+#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)\n+#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK\tGENMASK(19, 18)\n+#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB\tBIT(16)\n+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV\t\t0xd8\n+#define AIROHA_PCS_ANA_RX_TDC_CK_SEL\t\tBIT(24)\n+#define AIROHA_PCS_ANA_RX_PHYCK_RSTB\t\tBIT(16)\n+#define AIROHA_PCS_ANA_RX_PHYCK_SEL\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_RX_PHYCK_DIV\t\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc\n+#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS\tBIT(8)\n+#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO\t0xe8\n+#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM\tGENMASK(26, 8)\n+#define AIROHA_PCS_ANA_CDR_LPF_RATIO\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE\t0xf4\n+#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC\t0xf8\n+#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL\tGENMASK(19, 16)\n+#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS\tGENMASK(11, 8)\n+#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC\tGENMASK(6, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc\n+#define AIROHA_PCS_ANA_CDR_PR_FBKSEL\t\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN\t0x10c\n+#define AIROHA_PCS_ANA_RX_DAC_MON\t\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_CDR_PR_CAP_EN\t\tBIT(19)\n+#define AIROHA_PCS_ANA_CDR_BUF_IN_SR\t\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN\tBIT(2)\n+#define AIROHA_PCS_ANA_CDR_PR_MONPI_EN\tBIT(1)\n+#define AIROHA_PCS_ANA_CDR_PR_MONPR_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE\t\t0x110\n+#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH\t0x114\n+#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_RX_SIGDET_PEAK\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN\t0x118\n+#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB\t0x11c\n+#define AIROHA_PCS_ANA_RX_FE_VCM_GEN_PWDB\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW\t0x120\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE\t\tGENMASK(17, 8)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS BIT(0)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS BIT(1)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS BIT(2)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS BIT(3)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS BIT(4)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS BIT(5)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS BIT(6)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS BIT(7)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH\tBIT(8)\n+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS BIT(9)\n+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE\t\t0x13c\n+#define AIROHA_PCS_ANA_AEQ_OFORCE\t\tGENMASK(19, 8)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS\tBIT(0)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1\tBIT(1)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2\tBIT(2)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3\tBIT(3)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4\tBIT(4)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5\tBIT(5)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6\tBIT(6)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7\tBIT(7)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA\tBIT(8)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE\tBIT(9)\n+#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT\tBIT(10)\n+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144\n+#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ\t0x148\n+#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ\tBIT(24)\n+#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ\tBIT(16)\n+#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ\tBIT(8)\n+#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ\tBIT(0)\n+\n+/* PMA_PHYA 2L */\n+#define AIROHA_PCS_ANA_PXP_2L_CMN_EN\t\t0x0\n+#define AIROHA_PCS_ANA_2L_CMN_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN\t0x4\n+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IOFST\tGENMASK(29, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IBIAS\tGENMASK(21, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_SHCK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR\t0x8\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWR\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BP\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BC\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BR\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC\t0xc\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_CODE\tGENMASK(23, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_OPTION\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWC\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC\t0x10\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KS\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KF\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KFC\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE 0x14\n+#define AIROHA_PCS_ANA_2L_JCPLL_POSTDIV_D5\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_2 0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_3 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_4 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_1 0x3\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY\t0x1c\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_23 0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_21 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_19 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_15 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_PLL_RSTB\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_20_25 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_40_50 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_80_100 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_150_200 0x4\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_300_400 0x5\n+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_600_800 0x6\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM\t0x20\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_OUT\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_INT\t0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_1SDM 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_2SDM 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_3SDM 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_MODE\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_IFM\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN\t0x24\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_VREF\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_2 0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_4 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_6 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_8 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_10 0x4\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_HREN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN\t0x28\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_0_5 0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_1 0x1\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_2 0x2\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_4 0x3\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_8 0x4\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_16 0x6\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV\t0x2c\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_SCAPWR\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_HALFLSB_EN BIT(16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_CFIX\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_1\t0x0\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_2\t0x1\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR\t0x30\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(18, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_TCLVAR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN\t0x38\n+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_TRI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1\t0x3c\n+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA1\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD\t0x40\n+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_PERIOD\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN\t0x4c\n+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L\tGENMASK(31, 24)\n+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L_LDO\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))\n+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF 0x50\n+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_KBAND_VREF GENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN\t0x54\n+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IBIAS\tGENMASK(29, 24)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST\t0x58\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BP\tGENMASK(28, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BC\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BR\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IOFST\tGENMASK(5, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR\t0x5c\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_CODE\tGENMASK(31, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_OPTION\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWC\tGENMASK(12, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWR\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV\t0x60\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KS\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KF\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KFC\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_DIV\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN\t0x64\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE GENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_2 0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_3 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_4 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_1 0x3\n+#define AIROHA_PCS_ANA_2L_TXPLL_POSTDIV_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN\t0x68\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_INTERNAL BIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV\t0x6c\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_PLL_RSTB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_RST_DLY\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_1\t0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_2\t0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_3\t0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_4\t0x3\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS\t0x70\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_INT\t0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_1SDM 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_2SDM 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_3SDM 0x3\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_MODE\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_IFM\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_23 0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_21 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_19 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_15 0x3\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT\t0x74\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2 0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2_5 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_3 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_4 0x3\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_6 0x4\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_HREN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_OUT\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF 0x78\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_VREF\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW\t0x7c\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_HALFLSB_EN BIT(24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_CFIX\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_1\t0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_2\t0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_0_5 0x0\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_1 0x1\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_2 0x2\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_4 0x3\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_8 0x4\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_16 0x6\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR\t0x80\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(18, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_TCLVAR\tGENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_SCAPWR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN\t0x84\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_TRI_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PHASE_INI\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1\t0x88\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA1\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD\t0x8c\n+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_VCO_OUT\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_OUT\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PERIOD\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF 0x9c\n+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN\t0xcc\n+#define AIROHA_PCS_ANA_2L_TX0_DMEDGEGEN_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_TX0_CKLDO_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN\t0xe8\n+#define AIROHA_PCS_ANA_2L_TX1_DMEDGEGEN_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_TX1_CKLDO_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL\t0xf4\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FORCE BIT(24)\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_REV_0\t\t0xfc\n+#define AIROHA_PCS_ANA_2L_RX0_REV_1\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)\n+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)\n+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_REV_0\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)\n+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)\n+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV\tGENMASK(3, 2)\n+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4\tBIT(1)\n+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV\t0x100\n+#define AIROHA_PCS_ANA_2L_RX0_TDC_CK_SEL\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_RSTB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_SEL\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_DIV\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV 0x104\n+#define AIROHA_PCS_ANA_2L_CDR0_PD_EDGE_DIS\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PD_PICAL_CKD8_INV BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO\t0x110\n+#define AIROHA_PCS_ANA_2L_CDR0_LPF_TOP_LIM\tGENMASK(26, 8)\n+#define AIROHA_PCS_ANA_2L_CDR0_LPF_RATIO\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE\t0x11c\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_INJ_FORCE_OFF BIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC\t0x120\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_SEL\tGENMASK(19, 16)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_VCOADC_OS\tGENMASK(11, 8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_DAC\tGENMASK(6, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL 0x124\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_FBKSEL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_DAC_BAND\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_CKBUF_VAL GENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_IBAND_VAL GENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN 0x130\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPR_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN\t0x134\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_XFICK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR\t0x138\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_CAP_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR0_PR_BUF_IN_SR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON\t0x13c\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_MON\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN 0x140\n+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_PEAK\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_LPF_CTRL\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL 0x144\n+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ1_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_RX0_FE_EQ_HZEN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_VTH_SEL\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN\t0x148\n+#define AIROHA_PCS_ANA_2L_RX0_FE_VCM_GEN_PWDB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ3_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ2_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE\t0x150\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE\tGENMASK(17, 8)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2VOS BIT(0)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2IOS BIT(1)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1VOS BIT(2)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1IOS BIT(3)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2VOS BIT(4)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2IOS BIT(5)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1VOS BIT(6)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1IOS BIT(7)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_LVSH BIT(8)\n+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_COMPOS BIT(9)\n+#define AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE\t0x170\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE\t\tGENMASK(19, 8)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_SAOS\tBIT(0)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP1 BIT(1)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP2 BIT(2)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP3 BIT(3)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP4 BIT(4)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP5 BIT(5)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP6 BIT(6)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP7 BIT(7)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_VGA\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_CTLE\tBIT(9)\n+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_ATT\tBIT(10)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ 0x17c\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_E1_BYPASS_AEQ BIT(24)\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_E0_BYPASS_AEQ BIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_D1_BYPASS_AEQ BIT(8)\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_D0_BYPASS_AEQ BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ 0x180\n+#define AIROHA_PCS_ANA_2L_RX0_DAC_EYE_BYPASS_AEQ BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB 0x234\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_D0_BYPASS_AEQ BIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL\t0x1ac\n+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL_FORCE BIT(24)\n+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0\n+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_REV_0\t\t0x1b4\n+#define AIROHA_PCS_ANA_2L_RX1_REV_1\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)\n+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)\n+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX1_REV_0\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)\n+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)\n+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)\n+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV\tGENMASK(3, 2)\n+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4\tBIT(1)\n+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV\t0x1b8\n+#define AIROHA_PCS_ANA_2L_RX1_TDC_CK_SEL\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_RSTB\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_SEL\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_DIV\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV 0x1bc\n+#define AIROHA_PCS_ANA_2L_CDR1_PD_EDGE_DIS\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PD_PICAL_CKD8_INV BIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO\t0x1c8\n+#define AIROHA_PCS_ANA_2L_CDR1_LPF_TOP_LIM\tGENMASK(26, 8)\n+#define AIROHA_PCS_ANA_2L_CDR1_LPF_RATIO\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE\t0x1d4\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_INJ_FORCE_OFF BIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC\t0x1d8\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_KBAND_DIV\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_SEL\tGENMASK(19, 16)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_VCOADC_OS\tGENMASK(11, 8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_DAC\tGENMASK(6, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL 0x1dc\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_FBKSEL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_DAC_BAND\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_CKBUF_VAL GENMASK(10, 8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_IBAND_VAL GENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN 0x1e8\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPR_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN\t0x1ec\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_XFICK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR\t0x1f0\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_MON\t\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_CAP_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_CDR1_PR_BUF_IN_SR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE\t0x1f4\n+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_LPF_CTRL\tGENMASK(25, 24)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH\t0x1f8\n+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_VTH_SEL\tGENMASK(20, 16)\n+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_PEAK\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL\t0x1fc\n+#define AIROHA_PCS_ANA_2L_RX1_FE_EQ_HZEN\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN\t0x200\n+#define AIROHA_PCS_ANA_2L_RX1_FE_VCM_GEN_PWDB\tBIT(24)\n+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ3_EN\tBIT(16)\n+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ2_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ1_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW 0x208\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE\tGENMASK(25, 16)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2VOS BIT(0)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2IOS BIT(1)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1VOS BIT(2)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1IOS BIT(3)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2VOS BIT(4)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2IOS BIT(5)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1VOS BIT(6)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1IOS BIT(7)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_LVSH BIT(8)\n+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_COMPOS BIT(9)\n+#define AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE\t0x228\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE\t\tGENMASK(27, 16)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_SAOS\tBIT(0)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP1 BIT(1)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP2 BIT(2)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP3 BIT(3)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP4 BIT(4)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP5 BIT(5)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP6 BIT(6)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP7 BIT(7)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_VGA\tBIT(8)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_CTLE\tBIT(9)\n+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_ATT\tBIT(10)\n+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ 0x238\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_EYE_BYPASS_AEQ BIT(24)\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_E1_BYPASS_AEQ BIT(16)\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_E0_BYPASS_AEQ BIT(8)\n+#define AIROHA_PCS_ANA_2L_RX1_DAC_D1_BYPASS_AEQ BIT(0)\n+\n+/* PMA_PHYD */\n+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0\t0x0\n+#define AIROHA_PCS_PMA_SW_LCPLL_EN\t\tBIT(24)\n+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1\t0x4\n+#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2\t0x88\n+#define AIROHA_PCS_PMA_DATA_SHIFT\t\tBIT(8)\n+#define AIROHA_PCS_PMA_EYECNT_FAST\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0\t0x8c\n+#define AIROHA_PCS_PMA_RX_OS_START\t\tGENMASK(23, 8)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT\t\tGENMASK(2, 0)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)\n+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1\t0x90\n+#define AIROHA_PCS_PMA_RX_PICAL_END\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_PICAL_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2\t0x94\n+#define AIROHA_PCS_PMA_RX_PDOS_END\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_PDOS_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3\t0x98\n+#define AIROHA_PCS_PMA_RX_FEOS_END\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_FEOS_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4\t0x9c\n+#define AIROHA_PCS_PMA_RX_SDCAL_END\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_SDCAL_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5\t0x100\n+#define AIROHA_PCS_PMA_RX_RDY\t\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6\t0x104\n+#define AIROHA_PCS_PMA_RX_OS_END\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c\n+#define AIROHA_PCS_PMA_DISB_RX_RDY\t\tBIT(24)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114\n+#define AIROHA_PCS_PMA_FORCE_RX_RDY\t\tBIT(24)\n+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2\t\t0x120\n+#define AIROHA_PCS_PMA_EQ_DEBUG_SEL\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_PMA_FOM_NUM_ORDER\t\tGENMASK(12, 8)\n+#define AIROHA_PCS_PMA_A_SEL\t\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1\t\t0x14c\n+#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_LOCK_CYCLECNT\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2\t\t0x150\n+#define AIROHA_PCS_PMA_LOCK_TARGET_END\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_LOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3\t\t0x154\n+#define AIROHA_PCS_PMA_UNLOCK_TARGET_END\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4\t\t0x158\n+#define AIROHA_PCS_PMA_LOCK_UNLOCKTH\t\tGENMASK(15, 12)\n+#define AIROHA_PCS_PMA_LOCK_LOCKTH\t\tGENMASK(11, 8)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN\tGENMASK(2, 0)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT\tFIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL\tFIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)\n+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)\n+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1\t\t0x16c\n+#define AIROHA_PCS_PMA_SIGDET_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FLL_1\t\t\t0x174\n+#define AIROHA_PCS_PMA_LPATH_IDAC\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_RX_FLL_2\t\t\t0x178\n+#define AIROHA_PCS_PMA_CK_RATE\t\tGENMASK(18, 16)\n+#define AIROHA_PCS_PMA_CK_RATE_20\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)\n+#define AIROHA_PCS_PMA_CK_RATE_10\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)\n+#define AIROHA_PCS_PMA_CK_RATE_5\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)\n+#define AIROHA_PCS_PMA_RX_FLL_5\t\t\t0x184\n+#define AIROHA_PCS_PMA_FLL_IDAC_MIN\t\tGENMASK(26, 16)\n+#define AIROHA_PCS_PMA_FLL_IDAC_MAX\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_RX_FLL_B\t\t\t0x19c\n+#define AIROHA_PCS_PMA_LOAD_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_RESET_1\t\t0x208\n+#define AIROHA_PCS_PMA_SIGDET_RST_B\t\tBIT(8)\n+#define AIROHA_PCS_PMA_TX_RST_B\t\t\t0x260\n+#define AIROHA_PCS_PMA_TXCALIB_RST_B\t\tBIT(8)\n+#define AIROHA_PCS_PMA_TX_TOP_RST_B\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_4\t\t0x320\n+#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET\tBIT(24)\n+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9\t\t0x330\n+#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_8\t\t0x33c\n+#define AIROHA_PCS_PMA_DISB_FBCK_LOCK\t\tBIT(0)\n+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0\t0x34c\n+#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB\tBIT(24)\n+#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB\tBIT(16)\n+#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB\tBIT(8)\n+#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB\tBIT(0)\n+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1\t0x350\n+#define AIROHA_PCS_PMA_RX_SIDGET_PWDB\t\tBIT(0)\n+#define AIROHA_PCS_PMA_DIG_RESERVE_0\t\t0x360\n+#define AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN\tGENMASK(17, 16)\n+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1\t0x374\n+#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2\t\t0x380\n+#define AIROHA_PCS_RX_SIGDET\t\t\tBIT(8)\n+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0\t\t0x38c\n+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0\t0x390\n+#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1\t0x394\n+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3\t0x39c\n+#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH\tGENMASK(11, 8)\n+#define AIROHA_PCS_PMA_ADD_XPON_MODE_1\t\t0x414\n+#define AIROHA_PCS_PMA_XFI_RX_MODE\t\tGENMASK(11, 9)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_10G3\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x0)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_5G15\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x1)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_6G25\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x2)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_2G57\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x3)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_3G12\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x4)\n+#define AIROHA_PCS_PMA_XFI_RX_MODE_1G25\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x5)\n+#define AIROHA_PCS_PMA_R2T_MODE\t\tBIT(8)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE\t\tGENMASK(5, 3)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_10G3\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x0)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_5G15\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x1)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_6G25\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x2)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_2G57\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x3)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_3G12\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x4)\n+#define AIROHA_PCS_PMA_XFI_TX_MODE_1G25\tFIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x5)\n+#define AIROHA_PCS_PMA_SW_RST_SET\t\t0x460\n+#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N\tBIT(11)\n+#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N\tBIT(10)\n+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)\n+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N\tBIT(8)\n+#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N\tBIT(7)\n+#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N\tBIT(6)\n+#define AIROHA_PCS_PMA_SW_REF_RST_N\t\tBIT(5)\n+#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N\tBIT(4)\n+#define AIROHA_PCS_PMA_SW_PMA_RST_N\t\tBIT(3)\n+#define AIROHA_PCS_PMA_SW_TX_RST_N\t\tBIT(2)\n+#define AIROHA_PCS_PMA_SW_RX_RST_N\t\tBIT(1)\n+#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N\tBIT(0)\n+#define AIROHA_PCS_PMA_XPON_INT_EN_3\t\t0x474\n+#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_XPON_INT_STA_3\t\t0x47c\n+#define AIROHA_PCS_PMA_RX_SIGDET_INT\t\tBIT(16)\n+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL\t\t0x48c\n+#define AIROHA_PCS_PMA_DISB_LEQ\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FREQDET\t\t0x530\n+#define AIROHA_PCS_PMA_FL_OUT\t\t\tGENMASK(31, 16)\n+#define AIROHA_PCS_PMA_FBCK_LOCK\t\tBIT(0)\n+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL\t0x580\n+#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN\t0x768\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)\n+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED\t\t0x76c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL\tBIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL\tGENMASK(17, 16)\n+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B\t\t0x778\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1\tGENMASK(20, 16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL\t\t0x77c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL\tGENMASK(2, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1\t\t0x780\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2\tGENMASK(20, 16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL\t\t0x784\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC\t\t0x794\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)\n+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW\t0x798\n+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW\tGENMASK(30, 0)\n+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS\t\t0x79c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS\tBIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW\t0x800\n+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW\tGENMASK(30, 0)\n+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS\t\t0x80c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON\tBIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB\t\t0x814\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA\t0x818\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB\t\t0x81c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN\t0x820\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB\t0x824\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN\t0x828\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN\tBIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B\t0x84c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B\t BIT(0)\n+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN\t0x854\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN\tBIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN\t\t0x874\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL\t\t0x88c\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB\t\t0x894\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)\n+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB\t BIT(0)\n+#define AIROHA_PCS_PMA_DIG_RESERVE_29\t\t0x910\n+#define AIROHA_PCS_PMA_2L_TX_RATE_CTRL\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_2L_RX_RATE_CTRL\tGENMASK(5, 4)\n+\n+#define AIROHA_PCS_MAX_CALIBRATION_TRY\t\t50\n+#define AIROHA_PCS_MAX_RX_SIGDET_TRY\t\t6\n+#define AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT\t4\n+#define AIROHA_PCS_MAX_NUM_RSTS\t\t\t2\n+\n+enum xfi_port_type {\n+\tAIROHA_PCS_ETH,\n+\tAIROHA_PCS_PON,\n+\tAIROHA_PCS_USB,\n+\tAIROHA_PCS_PCIE,\n+};\n+\n+struct airoha_pcs_maps {\n+\tstruct regmap *pcs_mac;\n+\tstruct regmap *hsgmii_an;\n+\tstruct regmap *hsgmii_pcs;\n+\tstruct regmap *hsgmii_rate_adp;\n+\tstruct regmap *multi_sgmii;\n+\tstruct regmap *usxgmii_pcs;\n+};\n+\n+struct airoha_pcs_priv {\n+\tstruct device *dev;\n+\tconst struct airoha_pcs_match_data *data;\n+\n+\tstruct airoha_pcs_port *ports;\n+\n+\tstruct regmap *scu;\n+\n+\tstruct airoha_pcs_maps maps[2];\n+\n+\tstruct regmap *pcs_pma[2];\n+\tstruct regmap *pcs_ana;\n+\tstruct regmap_field **pcs_ana_fields[2];\n+\n+\tstruct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];\n+\n+\tstruct phy *phy;\n+\n+\tbool manual_rx_calib;\n+};\n+\n+struct airoha_pcs_port {\n+\tstruct airoha_pcs_priv *priv;\n+\tphy_interface_t interface;\n+\tint index;\n+\n+\tstruct phylink_pcs pcs;\n+};\n+\n+struct airoha_pcs_match_data {\n+\tint num_port;\n+\tenum xfi_port_type port_type;\n+\n+\tint (*alloc_regmap_fields)(struct airoha_pcs_priv *priv);\n+\tint (*bringup)(struct airoha_pcs_priv *priv,\n+\t\t int index, phy_interface_t interface);\n+\tvoid (*link_up)(struct airoha_pcs_priv *priv, int index);\n+\tint (*rxlock_workaround)(struct airoha_pcs_priv *priv, int index);\n+};\n+\n+#define to_airoha_pcs_port(n) container_of(n, struct airoha_pcs_port, pcs)\n+\n+#if IS_ENABLED(CONFIG_PCS_AIROHA_AN7581)\n+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv);\n+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv);\n+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,\n+\t\t int index, phy_interface_t interface);\n+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t int index, phy_interface_t interface);\n+\n+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index);\n+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index);\n+#else\n+static inline int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index, phy_interface_t interface)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index)\n+{\n+}\n+\n+static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index)\n+{\n+\treturn 0;\n+}\n+#endif\ndiff --git a/drivers/net/pcs/airoha/pcs-an7581.c b/drivers/net/pcs/airoha/pcs-an7581.c\nnew file mode 100644\nindex 0000000000000..95e155a7fa621\n--- /dev/null\n+++ b/drivers/net/pcs/airoha/pcs-an7581.c\n@@ -0,0 +1,2100 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+#include \u003clinux/math.h\u003e\n+#include \u003clinux/phy/phy.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+\n+#include \"pcs-airoha.h\"\n+\n+#include \u003clinux/of.h\u003e\n+\n+enum {\n+\tAN7581_PCS_CMN_EN,\n+\n+\tAN7581_PCS_JCPLL_SPARE_L,\n+\tAN7581_PCS_JCPLL_RST_DLY,\n+\tAN7581_PCS_JCPLL_PLL_RSTB,\n+\tAN7581_PCS_JCPLL_SDM_DI_EN,\n+\tAN7581_PCS_JCPLL_SDM_DI_LS,\n+\n+\tAN7581_PCS_JCPLL_SDM_OUT,\n+\tAN7581_PCS_JCPLL_SDM_ORD,\n+\tAN7581_PCS_JCPLL_SDM_MODE,\n+\tAN7581_PCS_JCPLL_SDM_IFM,\n+\tAN7581_PCS_JCPLL_SDM_HREN,\n+\n+\tAN7581_PCS_JCPLL_CHP_IOFST,\n+\tAN7581_PCS_JCPLL_CHP_IBIAS,\n+\tAN7581_PCS_JCPLL_LPF_SHCK_EN,\n+\n+\tAN7581_PCS_JCPLL_LPF_BWR,\n+\tAN7581_PCS_JCPLL_LPF_BP,\n+\tAN7581_PCS_JCPLL_LPF_BC,\n+\tAN7581_PCS_JCPLL_LPF_BR,\n+\tAN7581_PCS_JCPLL_LPF_BWC,\n+\n+\tAN7581_PCS_JCPLL_VCO_SCAPWR,\n+\tAN7581_PCS_JCPLL_VCO_HALFLSB_EN,\n+\tAN7581_PCS_JCPLL_VCO_CFIX,\n+\tAN7581_PCS_JCPLL_VCODIV,\n+\tAN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L,\n+\tAN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H,\n+\tAN7581_PCS_JCPLL_VCO_TCLVAR,\n+\n+\tAN7581_PCS_JCPLL_POSTDIV_D5,\n+\tAN7581_PCS_JCPLL_MMD_PREDIV_MODE,\n+\n+\tAN7581_PCS_JCPLL_KBAND_KS,\n+\tAN7581_PCS_JCPLL_KBAND_KF,\n+\tAN7581_PCS_JCPLL_KBAND_KFC,\n+\tAN7581_PCS_JCPLL_KBAND_DIV,\n+\tAN7581_PCS_JCPLL_KBAND_CODE,\n+\tAN7581_PCS_JCPLL_KBAND_OPTION,\n+\n+\tAN7581_PCS_JCPLL_TCL_AMP_VREF,\n+\tAN7581_PCS_JCPLL_TCL_AMP_GAIN,\n+\tAN7581_PCS_JCPLL_TCL_AMP_EN,\n+\n+\tAN7581_PCS_JCPLL_TCL_LPF_BW,\n+\tAN7581_PCS_JCPLL_TCL_LPF_EN,\n+\n+\tAN7581_PCS_JCPLL_SSC_DELTA,\n+\tAN7581_PCS_JCPLL_SSC_DELTA1,\n+\tAN7581_PCS_JCPLL_SSC_PERIOD,\n+\tAN7581_PCS_JCPLL_SSC_TRI_EN,\n+\tAN7581_PCS_JCPLL_SSC_EN,\n+\tAN7581_PCS_JCPLL_SSC_PHASE_INI,\n+\tAN7581_PCS_JCPLL_TCL_KBAND_VREF,\n+\n+\tAN7581_PCS_TXPLL_LDO_VCO_OUT,\n+\tAN7581_PCS_TXPLL_LDO_OUT,\n+\tAN7581_PCS_TXPLL_PLL_RSTB,\n+\tAN7581_PCS_TXPLL_RST_DLY,\n+\tAN7581_PCS_TXPLL_REFIN_DIV,\n+\tAN7581_PCS_TXPLL_REFIN_INTERNAL,\n+\tAN7581_PCS_TXPLL_SDM_MODE,\n+\tAN7581_PCS_TXPLL_SDM_IFM,\n+\tAN7581_PCS_TXPLL_SDM_DI_LS,\n+\tAN7581_PCS_TXPLL_SDM_DI_EN,\n+\tAN7581_PCS_TXPLL_SDM_HREN,\n+\tAN7581_PCS_TXPLL_SDM_ORD,\n+\tAN7581_PCS_TXPLL_SDM_OUT,\n+\tAN7581_PCS_TXPLL_SSC_DELTA1,\n+\tAN7581_PCS_TXPLL_SSC_DELTA,\n+\tAN7581_PCS_TXPLL_SSC_TRI_EN,\n+\tAN7581_PCS_TXPLL_SSC_PHASE_INI,\n+\tAN7581_PCS_TXPLL_SSC_EN,\n+\tAN7581_PCS_TXPLL_SSC_PERIOD,\n+\tAN7581_PCS_TXPLL_LPF_BC,\n+\tAN7581_PCS_TXPLL_LPF_BR,\n+\tAN7581_PCS_TXPLL_LPF_BP,\n+\tAN7581_PCS_TXPLL_LPF_BWC,\n+\tAN7581_PCS_TXPLL_LPF_BWR,\n+\tAN7581_PCS_TXPLL_CHP_IOFST,\n+\tAN7581_PCS_TXPLL_CHP_IBIAS,\n+\tAN7581_PCS_TXPLL_VCO_CFIX,\n+\tAN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L,\n+\tAN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H,\n+\tAN7581_PCS_TXPLL_VCO_TCLVAR,\n+\tAN7581_PCS_TXPLL_VCO_SCAPWR,\n+\tAN7581_PCS_TXPLL_VCO_HALFLSB_EN,\n+\tAN7581_PCS_TXPLL_KBAND_CODE,\n+\tAN7581_PCS_TXPLL_KBAND_OPTION,\n+\tAN7581_PCS_TXPLL_KBAND_KS,\n+\tAN7581_PCS_TXPLL_KBAND_KF,\n+\tAN7581_PCS_TXPLL_KBAND_KFC,\n+\tAN7581_PCS_TXPLL_KBAND_DIV,\n+\tAN7581_PCS_TXPLL_MMD_PREDIV_MODE,\n+\tAN7581_PCS_TXPLL_POSTDIV_EN,\n+\tAN7581_PCS_TXPLL_VCODIV,\n+\tAN7581_PCS_TXPLL_TCL_KBAND_VREF,\n+\tAN7581_PCS_TXPLL_TCL_AMP_GAIN,\n+\tAN7581_PCS_TXPLL_TCL_AMP_VREF,\n+\tAN7581_PCS_TXPLL_TCL_LPF_BW,\n+\tAN7581_PCS_TXPLL_TCL_LPF_EN,\n+\tAN7581_PCS_TXPLL_TCL_AMP_EN,\n+\n+\tAN7581_PCS_TX_DMEDGEGEN_EN,\n+\tAN7581_PCS_TX_CKLDO_EN,\n+\n+\tAN7581_PCS_RX_DAC_EYE_BYPASS_AEQ,\n+\tAN7581_PCS_RX_DAC_E1_BYPASS_AEQ,\n+\tAN7581_PCS_RX_DAC_E0_BYPASS_AEQ,\n+\tAN7581_PCS_RX_DAC_D1_BYPASS_AEQ,\n+\tAN7581_PCS_RX_DAC_D0_BYPASS_AEQ,\n+\tAN7581_PCS_RX_FE_VCM_GEN_PWDB,\n+\tAN7581_PCS_RX_OSCAL_FORCE,\n+\tAN7581_PCS_RX_DAC_MON,\n+\tAN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL,\n+\tAN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL,\n+\tAN7581_PCS_RX_REV_1_SIGDET_ILEAK,\n+\tAN7581_PCS_RX_FE_VB_EQ3_EN,\n+\tAN7581_PCS_RX_FE_VB_EQ2_EN,\n+\tAN7581_PCS_RX_FE_VB_EQ1_EN,\n+\tAN7581_PCS_RX_FE_EQ_HZEN,\n+\tAN7581_PCS_RX_SIGDET_VTH_SEL,\n+\tAN7581_PCS_RX_SIGDET_PEAK,\n+\tAN7581_PCS_RX_SIGDET_LPF_CTRL,\n+\tAN7581_PCS_RX_TDC_CK_SEL,\n+\tAN7581_PCS_RX_PHYCK_RSTB,\n+\tAN7581_PCS_RX_PHYCK_SEL,\n+\tAN7581_PCS_RX_PHYCK_DIV,\n+\tAN7581_PCS_RX_PHY_CK_SEL_FORCE,\n+\tAN7581_PCS_RX_PHY_CK_SEL,\n+\n+\tAN7581_PCS_AEQ_OFORCE,\n+\n+\tAN7581_PCS_CDR_PD_EDGE_DIS,\n+\tAN7581_PCS_CDR_PD_PICAL_CKD8_INV,\n+\n+\tAN7581_PCS_CDR_PR_XFICK_EN,\n+\tAN7581_PCS_CDR_PR_MONPI_EN,\n+\tAN7581_PCS_CDR_PR_MONPR_EN,\n+\tAN7581_PCS_CDR_PR_KBAND_DIV,\n+\tAN7581_PCS_CDR_PR_BETA_SEL,\n+\tAN7581_PCS_CDR_PR_VCOADC_OS,\n+\tAN7581_PCS_CDR_PR_BETA_DAC,\n+\tAN7581_PCS_CDR_PR_FBKSEL,\n+\tAN7581_PCS_CDR_PR_DAC_BAND,\n+\tAN7581_PCS_CDR_PR_VREG_CKBUF_VAL,\n+\tAN7581_PCS_CDR_PR_VREG_IBAND_VAL,\n+\tAN7581_PCS_CDR_PR_CAP_EN,\n+\tAN7581_PCS_CDR_PR_INJ_FORCE_OFF,\n+\n+\tAN7581_PCS_CDR_BUF_IN_SR,\n+\n+\tAN7581_PCS_CDR_LPF_TOP_LIM,\n+\tAN7581_PCS_CDR_LPF_RATIO,\n+\n+\tAN7581_PCS_FIELDS_MAX,\n+};\n+\n+static const struct reg_field an7581_pcs_fields[AN7581_PCS_FIELDS_MAX] = {\n+\t[AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CMN_EN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 8, 15),\n+\n+\t[AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 0, 2),\n+\t[AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 8, 8),\n+\t[AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 16, 16),\n+\t[AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 24, 25),\n+\n+\t[AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 24, 24),\n+\t[AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 16, 17),\n+\t[AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 8, 9),\n+\t[AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 0, 0),\n+\t[AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 16, 31),\n+\t[AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 8, 23),\n+\t[AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 0, 0),\n+\t[AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 17, 17),\n+\t[AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 16, 16),\n+\t[AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 16, 20),\n+\n+\t[AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 24, 29),\n+\t[AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 16, 21),\n+\t[AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 24, 28),\n+\t[AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 16, 20),\n+\t[AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 8, 12),\n+\t[AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 0, 4),\n+\t[AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 24, 26),\n+\t[AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 16, 16),\n+\t[AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 8, 9),\n+\t[AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 0, 1),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 8, 10),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 3, 5),\n+\t[AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 0, 2),\n+\n+\t[AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 24, 24),\n+\t[AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 0, 1),\n+\n+\t[AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 16, 17),\n+\t[AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 8, 9),\n+\t[AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 0, 1),\n+\t[AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 24, 26),\n+\t[AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 16, 23),\n+\t[AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 24, 28),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 16, 18),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 24, 26),\n+\t[AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 16, 16),\n+\n+\t[AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 24, 25),\n+\t[AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 16, 17),\n+\t[AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 24, 24),\n+\t[AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 16, 18),\n+\t[AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 8, 9),\n+\t[AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 0, 0),\n+\t[AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 24, 25),\n+\t[AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 16, 16),\n+\t[AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 8, 9),\n+\t[AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 16, 16),\n+\t[AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 0, 1),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 24, 28),\n+\t[AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 16, 20),\n+\t[AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 8, 13),\n+\t[AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 0, 5),\n+\t[AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 16, 20),\n+\t[AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 8, 12),\n+\t[AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 0, 4),\n+\t[AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 24, 25),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 27, 29),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 24, 26),\n+\t[AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 16, 18),\n+\t[AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 8, 10),\n+\t[AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 0, 7),\n+\t[AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 24, 24),\n+\t[AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 0, 1),\n+\t[AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 24, 25),\n+\t[AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 16, 17),\n+\t[AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 8, 10),\n+\t[AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 16, 17),\n+\t[AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 8, 8),\n+\t[AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 16, 17),\n+\t[AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 0, 2),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 8, 12),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 8, 10),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 24, 24),\n+\n+\t[AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 24, 24),\n+\t[AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 24, 24),\n+\t[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 16, 16),\n+\t[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 8, 8),\n+\t[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 0, 0),\n+\t[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB, 24, 24),\n+\t[AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB, 0, 0),\n+\n+\t[AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_AEQ_CFORCE, 8, 19),\n+\t[AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW, 8, 17),\n+\n+\t[AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 8, 8),\n+\t[AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 24, 28),\n+\t[AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 2, 2),\n+\t[AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 1, 1),\n+\t[AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 0, 0),\n+\n+\t[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 24, 26),\n+\t[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 20, 22),\n+\t[AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 18, 19),\n+\n+\t[AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 8, 26),\n+\t[AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 0, 1),\n+\n+\t[AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 24, 26),\n+\t[AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 16, 19),\n+\t[AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 8, 11),\n+\t[AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 0, 6),\n+\t[AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 24, 25),\n+\t[AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 16, 20),\n+\t[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 8, 10),\n+\t[AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 0, 2),\n+\n+\t[AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 24, 24),\n+\t[AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 16, 16),\n+\t[AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 8, 8),\n+\t[AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 0, 0),\n+\n+\t[AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 19, 19),\n+\t[AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 16, 18),\n+\n+\t[AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 16, 20),\n+\t[AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 8, 9),\n+\t[AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_RANGE, 24, 25),\n+\n+\t[AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 24, 24),\n+\t[AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 16, 16),\n+\t[AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 8, 9),\n+\t[AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 0, 7),\n+\t[AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 24, 24),\n+\t[AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 16, 16),\n+\n+\t[AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, 24, 24),\n+};\n+\n+static const struct reg_field an7581_pcs_pcie0_fields[AN7581_PCS_FIELDS_MAX] = {\n+\t[AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),\n+\n+\t[AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),\n+\t[AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),\n+\t[AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),\n+\t[AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),\n+\n+\t[AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),\n+\t[AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),\n+\t[AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),\n+\t[AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),\n+\t[AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),\n+\t[AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),\n+\t[AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),\n+\t[AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),\n+\t[AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),\n+\t[AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),\n+\t[AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),\n+\t[AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),\n+\t[AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),\n+\t[AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),\n+\t[AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),\n+\n+\t[AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),\n+\t[AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),\n+\n+\t[AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),\n+\t[AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),\n+\t[AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),\n+\t[AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),\n+\t[AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),\n+\t[AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),\n+\t[AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),\n+\n+\t[AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),\n+\t[AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),\n+\t[AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),\n+\t[AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),\n+\t[AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),\n+\t[AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),\n+\t[AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),\n+\t[AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),\n+\t[AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),\n+\t[AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),\n+\t[AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),\n+\t[AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),\n+\t[AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),\n+\t[AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),\n+\t[AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),\n+\t[AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),\n+\t[AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),\n+\t[AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),\n+\t[AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),\n+\t[AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),\n+\t[AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),\n+\t[AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),\n+\t[AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),\n+\t[AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),\n+\t[AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),\n+\t[AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),\n+\t[AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),\n+\t[AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),\n+\t[AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),\n+\t[AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 16, 16),\n+\n+\t[AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 24, 24),\n+\t[AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ, 0, 0),\n+\t[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 24, 24),\n+\t[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 16, 16),\n+\t[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 8, 8),\n+\t[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 0, 0),\n+\t[AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 16, 16),\n+\n+\t[AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE, 8, 19),\n+\t[AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE, 8, 17),\n+\n+\t[AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 8, 8),\n+\t[AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON, 0, 4),\n+\t[AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 8, 8),\n+\t[AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 0, 0),\n+\t[AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN, 24, 24),\n+\n+\t[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 24, 26),\n+\t[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 20, 22),\n+\t[AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 18, 19),\n+\n+\t[AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 8, 26),\n+\t[AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 0, 1),\n+\n+\t[AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 24, 26),\n+\t[AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 16, 19),\n+\t[AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 8, 11),\n+\t[AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 0, 6),\n+\t[AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 24, 25),\n+\t[AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 16, 20),\n+\t[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 8, 10),\n+\t[AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 0, 2),\n+\n+\t[AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 8, 8),\n+\t[AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 0, 0),\n+\t[AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 24, 24),\n+\t[AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 16, 16),\n+\n+\t[AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 8, 8),\n+\t[AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 0, 2),\n+\n+\t[AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 0, 4),\n+\t[AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 24, 25),\n+\t[AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 8, 9),\n+\n+\t[AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 24, 24),\n+\t[AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 16, 16),\n+\t[AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 8, 9),\n+\t[AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 0, 7),\n+\t[AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 24, 24),\n+\t[AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 16, 16),\n+\n+\t[AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE, 24, 24),\n+};\n+\n+static const struct reg_field an7581_pcs_pcie1_fields[AN7581_PCS_FIELDS_MAX] = {\n+\t[AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),\n+\n+\t[AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),\n+\t[AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),\n+\t[AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),\n+\t[AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),\n+\n+\t[AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),\n+\t[AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),\n+\t[AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),\n+\t[AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),\n+\t[AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),\n+\n+\t[AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),\n+\t[AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),\n+\t[AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),\n+\t[AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),\n+\t[AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),\n+\t[AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),\n+\t[AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),\n+\t[AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),\n+\t[AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),\n+\t[AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),\n+\t[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),\n+\t[AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),\n+\n+\t[AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),\n+\n+\t[AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),\n+\t[AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),\n+\n+\t[AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),\n+\t[AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),\n+\t[AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),\n+\t[AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),\n+\t[AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),\n+\t[AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),\n+\t[AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),\n+\n+\t[AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),\n+\t[AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),\n+\n+\t[AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),\n+\t[AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),\n+\t[AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),\n+\t[AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),\n+\t[AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),\n+\t[AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),\n+\t[AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),\n+\t[AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),\n+\t[AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),\n+\t[AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),\n+\t[AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),\n+\t[AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),\n+\t[AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),\n+\t[AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),\n+\t[AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),\n+\t[AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),\n+\t[AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),\n+\t[AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),\n+\t[AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),\n+\t[AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),\n+\t[AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),\n+\t[AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),\n+\t[AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),\n+\t[AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),\n+\t[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),\n+\t[AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),\n+\t[AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),\n+\t[AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),\n+\t[AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),\n+\t[AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),\n+\t[AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),\n+\t[AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),\n+\t[AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),\n+\t[AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),\n+\t[AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),\n+\t[AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),\n+\t[AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),\n+\t[AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),\n+\t[AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),\n+\t[AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 16, 16),\n+\n+\t[AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 24, 24),\n+\t[AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 24, 24),\n+\t[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 16, 16),\n+\t[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 8, 8),\n+\t[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 0, 0),\n+\t[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB, 24, 24),\n+\t[AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 24, 24),\n+\n+\t[AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE, 16, 27),\n+\t[AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW, 16, 25),\n+\n+\t[AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 8, 8),\n+\t[AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 0, 0),\n+\n+\t[AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 16, 20),\n+\t[AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 8, 8),\n+\t[AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 0, 0),\n+\t[AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN, 24, 24),\n+\n+\t[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 24, 26),\n+\t[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 20, 22),\n+\t[AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 18, 19),\n+\n+\t[AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 8, 26),\n+\t[AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 0, 1),\n+\n+\t[AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 24, 26),\n+\t[AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 16, 19),\n+\t[AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 8, 11),\n+\t[AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 0, 6),\n+\t[AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 24, 25),\n+\t[AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 16, 20),\n+\t[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 8, 10),\n+\t[AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 0, 2),\n+\n+\t[AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 16, 16),\n+\t[AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 8, 8),\n+\t[AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 0, 0),\n+\t[AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL, 24, 24),\n+\n+\t[AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 8, 8),\n+\t[AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 0, 2),\n+\n+\t[AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 16, 20),\n+\t[AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 8, 9),\n+\t[AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE, 24, 25),\n+\n+\t[AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 24, 24),\n+\t[AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 16, 16),\n+\t[AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 8, 9),\n+\t[AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 0, 7),\n+\t[AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 24, 24),\n+\t[AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 16, 16),\n+\n+\t[AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE, 24, 24),\n+};\n+\n+static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tstruct regmap *pcs_pma;\n+\tu32 kband_vref;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tkband_vref = 0x10;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tkband_vref = 0xf;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* This comment only apply to Serdes PCIe that expose\n+\t * 2 PCS.\n+\t *\n+\t * The Serdes PCIe expose 2 PCS but always require\n+\t * the PMA for the first PCS to be configured\n+\t * for correct functionality for JCPLL.\n+\t */\n+\tpcs_pma = priv-\u003epcs_pma[0];\n+\n+\t/* Setup LDO */\n+\tusleep_range(200, 300);\n+\n+\tregmap_field_set_bits(pcs_ana_fields[AN7581_PCS_JCPLL_SPARE_L],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);\n+\n+\t/* Setup RSTB */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_RST_DLY],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_PLL_RSTB], 0x1);\n+\n+\t/* Enable PLL force selection and Force Disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);\n+\n+\t/* Setup SDM */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_LS],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_EN], 0x0);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_OUT], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_ORD],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_MODE], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_IFM], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_HREN], 0x0);\n+\n+\t/* Setup SSC */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA1], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PERIOD], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_TRI_EN], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_EN], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PHASE_INI], 0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0);\n+\n+\t/* Setup LPF */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IOFST], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IBIAS], 0x18);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_SHCK_EN], 0);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWR], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BP], 0x10);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BC], 0x1f);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BR], BIT(3) | BIT(1));\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWC], 0x0);\n+\n+\t/* Setup VCO */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_SCAPWR], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_HALFLSB_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_CFIX], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H], 0x3);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x3);\n+\n+\t/* Setup PCW */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);\n+\n+\t/* Setup DIV */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_POSTDIV_D5], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_MMD_PREDIV_MODE],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCODIV],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_VCODIV_1);\n+\n+\t/* Setup KBand */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KS], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KF], 0x3);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KFC], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_DIV], 0x2);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_CODE], 0xe4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_OPTION], 0x0);\n+\n+\t/* Setup TCL */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_KBAND_VREF],\n+\t\t\t kband_vref);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_VREF], 0x5);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_GAIN],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_EN], 0x1);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_BW],\n+\t\t\t AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_EN], 0x1);\n+\n+\t/* Enable PLL */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);\n+\n+\t/* Enale PLL Output */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);\n+}\n+\n+static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tu32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;\n+\tstruct regmap *pcs_pma;\n+\tu32 tcl_amp_vref;\n+\tbool sdm_hren;\n+\tu32 vco_cfix;\n+\tbool vcodiv;\n+\tu32 pcw;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tlpf_chp_ibias = 0xf;\n+\t\tlpf_bp = BIT(1);\n+\t\tlpf_bwr = BIT(3) | BIT(1) | BIT(0);\n+\t\tlpf_bwc = BIT(4) | BIT(3);\n+\t\tvco_cfix = BIT(1) | BIT(0);\n+\t\tpcw = BIT(27);\n+\t\ttcl_amp_vref = BIT(3) | BIT(1) | BIT(0);\n+\t\tvcodiv = false;\n+\t\tsdm_hren = false;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tlpf_chp_ibias = 0xa;\n+\t\tlpf_bp = BIT(2) | BIT(0);\n+\t\tlpf_bwr = 0;\n+\t\tlpf_bwc = 0;\n+\t\tvco_cfix = 0;\n+\t\tpcw = BIT(27) | BIT(25);\n+\t\ttcl_amp_vref = BIT(3) | BIT(2) | BIT(0);\n+\t\tvcodiv = true;\n+\t\tsdm_hren = false;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tlpf_chp_ibias = 0xf;\n+\t\tlpf_bp = BIT(1);\n+\t\tlpf_bwr = BIT(3) | BIT(1) | BIT(0);\n+\t\tlpf_bwc = BIT(4) | BIT(3);\n+\t\tvco_cfix = BIT(0);\n+\t\tpcw = BIT(27) | BIT(22);\n+\t\ttcl_amp_vref = BIT(3) | BIT(1) | BIT(0);\n+\t\tvcodiv = false;\n+\t\tsdm_hren = true;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* This comment only apply to Serdes PCIe that expose\n+\t * 2 PCS.\n+\t *\n+\t * The Serdes PCIe expose 2 PCS but always require\n+\t * the PMA for the first PCS to be configured\n+\t * for correct functionality for TXPLL.\n+\t */\n+\tpcs_pma = priv-\u003epcs_pma[0];\n+\n+\t/* Setup VCO LDO Output */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_VCO_OUT], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_OUT], 0x1);\n+\n+\t/* Setup RSTB */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_PLL_RSTB], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_RST_DLY], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_DIV],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_INTERNAL], 0x1);\n+\n+\t/* Enable PLL force selection and Force Disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);\n+\n+\t/* Setup SDM */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_MODE], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_IFM], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_LS],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_HREN], sdm_hren);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_OUT], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_ORD],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);\n+\n+\t/* Setup SSC */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA1], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_TRI_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PHASE_INI], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PERIOD], 0x0);\n+\n+\t/* Setup LPF */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IBIAS],\n+\t\t\t lpf_chp_ibias);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IOFST], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BC], 0x1f);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BR], 0x5);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWC], lpf_bwc);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWR], lpf_bwr);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BP], lpf_bp);\n+\n+\t/* Setup VCO */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_CFIX], vco_cfix);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_TCLVAR], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_SCAPWR], 0x7);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_HALFLSB_EN], 0x1);\n+\n+\t/* Setup PCW */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);\n+\n+\t/* Setup KBand */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_CODE], 0xe4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_OPTION], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KS], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KF], 0x3);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KFC], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_DIV], 0x4);\n+\n+\t/* Setup DIV */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_POSTDIV_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_MMD_PREDIV_MODE],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCODIV],\n+\t\t\t vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :\n+\t\t\t\t AIROHA_PCS_ANA_TXPLL_VCODIV_1);\n+\n+\t/* Setup TCL */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_KBAND_VREF], 0xf);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_VREF],\n+\t\t\t tcl_amp_vref);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_GAIN],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_BW],\n+\t\t\t AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_EN], 0x1);\n+\n+\t/* Enable PLL */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);\n+\n+\t/* Enale PLL Output */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);\n+}\n+\n+static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tu32 fir_cn1, fir_c0b, fir_c1;\n+\tu32 tx_rate_ctrl;\n+\tu32 ckin_divisor;\n+\tu32 xfi_tx_mode;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tckin_divisor = BIT(1);\n+\t\ttx_rate_ctrl = BIT(0);\n+\t\tfir_cn1 = 0;\n+\t\tfir_c0b = 12;\n+\t\tfir_c1 = 0;\n+\t\txfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_1G25;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tckin_divisor = BIT(2);\n+\t\ttx_rate_ctrl = BIT(0);\n+\t\tfir_cn1 = 0;\n+\t\tfir_c0b = 11;\n+\t\tfir_c1 = 1;\n+\t\txfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_3G12;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tckin_divisor = BIT(2) | BIT(0);\n+\t\ttx_rate_ctrl = BIT(1);\n+\t\tfir_cn1 = 1;\n+\t\tfir_c0b = 1;\n+\t\tfir_c1 = 11;\n+\t\txfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_10G3;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* Set TX rate ctrl */\n+\tif (priv-\u003edata-\u003eport_type == AIROHA_PCS_PCIE) {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,\n+\t\t\t\t AIROHA_PCS_PMA_2L_TX_RATE_CTRL,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_2L_TX_RATE_CTRL,\n+\t\t\t\t\t tx_rate_ctrl));\n+\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,\n+\t\t\t\t AIROHA_PCS_PMA_XFI_TX_MODE,\n+\t\t\t\t xfi_tx_mode);\n+\t} else {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,\n+\t\t\t\t AIROHA_PCS_PMA_PON_TX_RATE_CTRL,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,\n+\t\t\t\t\t tx_rate_ctrl));\n+\t}\n+\n+\t/* Setup TX Config */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TX_DMEDGEGEN_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_TX_CKLDO_EN], 0x1);\n+\n+\tudelay(1);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);\n+\n+\t/* FIXME: Ask Airoha TX term is OK to reset? */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,\n+\t\t\t\t ckin_divisor));\n+\n+\tif (priv-\u003edata-\u003eport_type != AIROHA_PCS_PCIE) {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,\n+\t\t\t\t\t tx_rate_ctrl));\n+\t}\n+\n+\t/* Setup TX FIR Load Parameters (Reference 660mV) */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));\n+\n+\t/* Reset TX Bar */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B,\n+\t\t\tAIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);\n+}\n+\n+static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tu32 phyck_div, phyck_sel;\n+\tu32 pr_cdr_beta_dac;\n+\tu32 cdr_pr_buf_in_sr;\n+\tbool cdr_pr_cap_en;\n+\tu32 sigdet_vth_sel;\n+\tu32 rx_rate_ctrl;\n+\tu32 xfi_rx_mode;\n+\tu32 osr;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tosr = BIT(1) | BIT(0); /* 1.25G */\n+\t\tpr_cdr_beta_dac = BIT(3);\n+\t\trx_rate_ctrl = 0;\n+\t\tcdr_pr_cap_en = false;\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);\n+\t\tsigdet_vth_sel = BIT(2) | BIT(1);\n+\t\tphyck_div = BIT(5) | BIT(3) | BIT(0);\n+\t\tphyck_sel = BIT(0);\n+\t\txfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_1G25;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tosr = BIT(0); /* 2.5G */\n+\t\tpr_cdr_beta_dac = BIT(2) | BIT(1);\n+\t\trx_rate_ctrl = 0;\n+\t\tcdr_pr_cap_en = true;\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1);\n+\t\tsigdet_vth_sel = BIT(2) | BIT(1);\n+\t\tphyck_div = BIT(3) | BIT(1) | BIT(0);\n+\t\tphyck_sel = BIT(0);\n+\t\txfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_3G12;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tosr = 0; /* 10G */\n+\t\tcdr_pr_cap_en = false;\n+\t\tpr_cdr_beta_dac = BIT(3);\n+\t\trx_rate_ctrl = BIT(1);\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);\n+\t\tsigdet_vth_sel = BIT(1);\n+\t\tphyck_div = BIT(6) | BIT(1);\n+\t\tphyck_sel = BIT(1);\n+\t\txfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_10G3;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* Set RX rate ctrl */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_2,\n+\t\t\t\t AIROHA_PCS_PMA_CK_RATE,\n+\t\t\t\t AIROHA_PCS_PMA_CK_RATE_10);\n+\n+\tif (priv-\u003edata-\u003eport_type == AIROHA_PCS_PCIE) {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,\n+\t\t\t\t AIROHA_PCS_PMA_2L_RX_RATE_CTRL,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_2L_RX_RATE_CTRL,\n+\t\t\t\t\t rx_rate_ctrl));\n+\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,\n+\t\t\t\t AIROHA_PCS_PMA_XFI_RX_MODE,\n+\t\t\t\t xfi_rx_mode);\n+\t} else {\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,\n+\t\t\t\t AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,\n+\t\t\t\t\t rx_rate_ctrl));\n+\t}\n+\n+\t/* Setup RX Path */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_5,\n+\t\t\t AIROHA_PCS_PMA_FLL_IDAC_MIN |\n+\t\t\t AIROHA_PCS_PMA_FLL_IDAC_MAX,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VCM_GEN_PWDB], 0x1);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,\n+\t\t\tAIROHA_PCS_PMA_LCPLL_MAN_PWDB);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_AEQ_OFORCE],\n+\t\t\t AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_OSCAL_FORCE],\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |\n+\t\t\t AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,\n+\t\t\t AIROHA_PCS_PMA_DISB_BLWC_OFFSET);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,\n+\t\t\t AIROHA_PCS_PMA_DISB_LEQ);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_PICAL_CKD8_INV], 0x0);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_MON], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_XFICK_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPI_EN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPR_EN], 0x0);\n+\n+\t/* Setup FE Gain and FE Peacking */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0));\n+\n+\t/* Setup FE VOS */\n+\tif (interface != PHY_INTERFACE_MODE_USXGMII \u0026\u0026\n+\t interface != PHY_INTERFACE_MODE_10GBASER)\n+\t\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_DA_FE_VOS,\n+\t\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));\n+\n+\t/* Setup FLL PR FMeter (no bypass mode)*/\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,\n+\t\t\t AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,\n+\t\t\t AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |\n+\t\t\t AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,\n+\t\t\t AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));\n+\n+\t/* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */\n+\t/* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */\n+\t/* Setup REV */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL],\n+\t\t\t BIT(2));\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL],\n+\t\t\t BIT(2));\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_SIGDET_ILEAK], 0x0);\n+\n+\t/* Setup Rdy Timeout */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,\n+\t\t\t AIROHA_PCS_PMA_RX_RDY |\n+\t\t\t AIROHA_PCS_PMA_RX_BLWC_RDY_EN,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));\n+\n+\t/* Setup CaBoundry Init */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,\n+\t\t\t AIROHA_PCS_PMA_RX_OS_START |\n+\t\t\t AIROHA_PCS_PMA_OSC_SPEED_OPT,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |\n+\t\t\t AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,\n+\t\t\t AIROHA_PCS_PMA_RX_OS_END,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,\n+\t\t\t AIROHA_PCS_PMA_RX_PICAL_END |\n+\t\t\t AIROHA_PCS_PMA_RX_PICAL_START,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,\n+\t\t\t AIROHA_PCS_PMA_RX_SDCAL_END |\n+\t\t\t AIROHA_PCS_PMA_RX_SDCAL_START,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,\n+\t\t\t AIROHA_PCS_PMA_RX_PDOS_END |\n+\t\t\t AIROHA_PCS_PMA_RX_PDOS_START,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,\n+\t\t\t AIROHA_PCS_PMA_RX_FEOS_END |\n+\t\t\t AIROHA_PCS_PMA_RX_FEOS_START,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));\n+\n+\t/* Setup By Serdes*/\n+\t/* Setup RX OSR */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], !!osr);\n+\n+\t/* Setup CDR LPF Ratio */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_TOP_LIM], 0x20000);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_RATIO], osr);\n+\n+\t/* Setup CDR PR */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_KBAND_DIV], 0x4);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_SEL], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VCOADC_OS], 0x8);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_DAC],\n+\t\t\t pr_cdr_beta_dac);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_FBKSEL], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_DAC_BAND],\n+\t\t\t pr_cdr_beta_dac);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL], 0x6);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_IBAND_VAL], 0x6);\n+\n+\t/* Setup Eye Mon */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,\n+\t\t\t AIROHA_PCS_PMA_EQ_DEBUG_SEL |\n+\t\t\t AIROHA_PCS_PMA_FOM_NUM_ORDER |\n+\t\t\t AIROHA_PCS_PMA_A_SEL,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,\n+\t\t\t AIROHA_PCS_PMA_DATA_SHIFT |\n+\t\t\t AIROHA_PCS_PMA_EYECNT_FAST,\n+\t\t\t AIROHA_PCS_PMA_EYECNT_FAST);\n+\n+\t/* Calibration Start */\n+\n+\t/* Enable SYS */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,\n+\t\t\t AIROHA_PCS_PMA_RX_SYS_EN_SEL,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,\n+\t\t\tAIROHA_PCS_PMA_SW_LCPLL_EN);\n+\n+\tusleep_range(500, 600);\n+\n+\t/* Setup FLL PR FMeter (bypass mode)*/\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,\n+\t\t\t AIROHA_PCS_PMA_DISB_FBCK_LOCK);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,\n+\t\t\tAIROHA_PCS_PMA_FORCE_FBCK_LOCK);\n+\n+\t/* Enable CMLEQ */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_EQ_HZEN], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ3_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ2_EN], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ1_EN], 0x1);\n+\n+\t/* Setup CDR PR */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_CAP_EN],\n+\t\t\t cdr_pr_cap_en);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_BUF_IN_SR],\n+\t\t\t cdr_pr_buf_in_sr);\n+\n+\t/* Setup CDR xxx Pwdb, set force and disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,\n+\t\t\t AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |\n+\t\t\t AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |\n+\t\t\t AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |\n+\t\t\t AIROHA_PCS_PMA_XPON_RX_FE_PWDB);\n+\n+\t/* FIXME: Ask Airoha WHY it's cleared? */\n+\t/* regmap_clear_bits(priv-\u003epcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,\n+\t *\t\t AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);\n+\t */\n+\n+\t/* Setup SigDet */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_VTH_SEL],\n+\t\t\t sigdet_vth_sel);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_PEAK],\n+\t\t\t BIT(1));\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_LPF_CTRL],\n+\t\t\t BIT(1) | BIT(0));\n+\n+\t/* Disable SigDet Pwdb */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,\n+\t\t\t AIROHA_PCS_PMA_RX_SIDGET_PWDB);\n+\n+\t/* Setup PHYCK */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_TDC_CK_SEL], 0x0);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_RSTB], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_SEL],\n+\t\t\t phyck_sel);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_DIV],\n+\t\t\t phyck_div);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL_FORCE], 0x1);\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL], 0x0);\n+\n+\tusleep_range(100, 200);\n+\n+\t/* Enable CDR xxx Pwdb */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PD_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PW_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_RX_FE_PWDB);\n+\n+\t/* Enable SigDet Pwdb */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,\n+\t\t\tAIROHA_PCS_PMA_RX_SIDGET_PWDB);\n+}\n+\n+static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t\t int index, u32 cdr_pr_idac)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tu32 val = UINT_MAX;\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\t AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,\n+\t\t\t\t cdr_pr_idac));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t AIROHA_PCS_PMA_FREQLOCK_DET_EN,\n+\t\t\t AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t AIROHA_PCS_PMA_FREQLOCK_DET_EN,\n+\t\t\t AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);\n+\n+\tusleep_range(5000, 7000);\n+\n+\tregmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, \u0026val);\n+\n+\treturn FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);\n+}\n+\n+static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t int index, u32 target_fl_out)\n+{\n+\tunsigned int fl_out_diff = UINT_MAX;\n+\tunsigned int prcal_search;\n+\tu32 cdr_pr_idac = 0;\n+\n+\tfor (prcal_search = 0; prcal_search \u003c 8 ; prcal_search++) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tunsigned int fl_out;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\t/* try to find the upper value by setting the last 3 bit */\n+\t\tcdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t prcal_search);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs_diff(fl_out, target_fl_out);\n+\t\tdev_dbg(priv-\u003edev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\t\tif (fl_out_diff_new \u003c fl_out_diff) {\n+\t\t\tcdr_pr_idac = cdr_pr_idac_tmp;\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\t\t}\n+\t}\n+\n+\treturn cdr_pr_idac;\n+}\n+\n+static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\t u32 target_fl_out, u32 cdr_pr_idac_major)\n+{\n+\tunsigned int remaining_prcal_search_bits = 0;\n+\tu32 cdr_pr_idac = cdr_pr_idac_major;\n+\tunsigned int fl_out, fl_out_diff;\n+\tint best_prcal_search_bit = -1;\n+\tint prcal_search_bit;\n+\n+\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);\n+\tfl_out_diff = abs_diff(fl_out, target_fl_out);\n+\n+\t/* Deadline search part.\n+\t * We start from top bits to bottom as we progressively decrease the\n+\t * signal.\n+\t */\n+\tfor (prcal_search_bit = 7; prcal_search_bit \u003e= 0; prcal_search_bit--) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tcdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs_diff(fl_out, target_fl_out);\n+\t\tdev_dbg(priv-\u003edev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\t\tif (fl_out_diff_new \u003c fl_out_diff) {\n+\t\t\tbest_prcal_search_bit = prcal_search_bit;\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\t\t}\n+\t}\n+\n+\t/* Set the idac with the best value we found and\n+\t * reset the search bit to start from bottom to top.\n+\t */\n+\tif (best_prcal_search_bit \u003e= 0) {\n+\t\tcdr_pr_idac |= BIT(best_prcal_search_bit);\n+\t\tremaining_prcal_search_bits = best_prcal_search_bit;\n+\t\tprcal_search_bit = 0;\n+\t}\n+\n+\t/* Fine tune part.\n+\t * Test remaining bits to find an even closer signal level to target\n+\t * by increasing the signal.\n+\t */\n+\twhile (remaining_prcal_search_bits) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tcdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs_diff(fl_out, target_fl_out);\n+\t\t/* Assume we found the deadline when the new absolue signal difference\n+\t\t * from target is greater than the previous and the difference is at\n+\t\t * least 10% greater between the old and new value.\n+\t\t * This is to account for signal detection level tollerance making\n+\t\t * sure we are actually over a deadline (AKA we are getting farther\n+\t\t * from target)\n+\t\t */\n+\t\tdev_dbg(priv-\u003edev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\n+\t\t/* Exact match, set the bit and exit */\n+\t\tif (!fl_out_diff_new) {\n+\t\t\tcdr_pr_idac |= BIT(prcal_search_bit);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (fl_out_diff \u0026\u0026 fl_out_diff_new \u003e fl_out_diff \u0026\u0026\n+\t\t (abs_diff(fl_out_diff_new, fl_out_diff) * 100) / fl_out_diff \u003e 10) {\n+\t\t\t/* Exit early if we are already at the deadline */\n+\t\t\tif (prcal_search_bit == 0)\n+\t\t\t\tbreak;\n+\n+\t\t\t/* We found the deadline, set the value to the previous\n+\t\t\t * bit, and reset the loop to fine tune with the\n+\t\t\t * remaining values.\n+\t\t\t */\n+\t\t\tcdr_pr_idac |= BIT(prcal_search_bit - 1);\n+\t\t\tremaining_prcal_search_bits = prcal_search_bit - 1;\n+\t\t\tprcal_search_bit = 0;\n+\t\t} else {\n+\t\t\t/* Update the signal level diff and try the next bit */\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\n+\t\t\t/* If we didn't found the deadline, set the last bit\n+\t\t\t * and reset the loop to fine tune with the remainig\n+\t\t\t * values.\n+\t\t\t */\n+\t\t\tif (prcal_search_bit == remaining_prcal_search_bits - 1) {\n+\t\t\t\tcdr_pr_idac |= BIT(prcal_search_bit);\n+\t\t\t\tremaining_prcal_search_bits = prcal_search_bit;\n+\t\t\t\tprcal_search_bit = 0;\n+\t\t\t} else {\n+\t\t\t\tprcal_search_bit++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn cdr_pr_idac;\n+}\n+\n+static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv,\n+\t\t\t\tint index, phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tu32 cdr_pr_idac_major, cdr_pr_idac;\n+\tunsigned int fl_out, fl_out_diff;\n+\n+\tu32 target_fl_out;\n+\tu32 cyclecnt;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\ttarget_fl_out = 0xa3d6;\n+\t\tcyclecnt = 32767;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */\n+\t\ttarget_fl_out = 0xa000;\n+\t\tcyclecnt = 20000;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\ttarget_fl_out = 0x9edf;\n+\t\tcyclecnt = 32767;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tusleep_range(100, 200);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,\n+\t\t\t AIROHA_PCS_PMA_LOCK_TARGET_END |\n+\t\t\t AIROHA_PCS_PMA_LOCK_TARGET_BEG,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,\n+\t\t\t AIROHA_PCS_PMA_UNLOCK_CYCLECNT |\n+\t\t\t AIROHA_PCS_PMA_LOCK_CYCLECNT,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t AIROHA_PCS_PMA_LOCK_UNLOCKTH |\n+\t\t\t AIROHA_PCS_PMA_LOCK_LOCKTH,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,\n+\t\t\t AIROHA_PCS_PMA_UNLOCK_TARGET_END |\n+\t\t\t AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));\n+\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x1);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\t/* Calibration logic:\n+\t * First check the major value by looping with every\n+\t * value in the last 3 bit of CDR_PR_IDAC.\n+\t * Get the signal level and save the value that is closer to\n+\t * the target.\n+\t *\n+\t * Then check each remaining 7 bits in search of the deadline\n+\t * where the signal gets farther than signal target.\n+\t *\n+\t * Finally fine tune for the remaining bits to find the one that\n+\t * produce the closest signal level.\n+\t */\n+\tcdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv, index, target_fl_out);\n+\n+\tcdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, index,\n+\t\t\t\t\t\t target_fl_out, cdr_pr_idac_major);\n+\n+\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);\n+\tfl_out_diff = abs_diff(fl_out, target_fl_out);\n+\tif (fl_out_diff \u003e 100) {\n+\t\tu32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t cdr_pr_idac_major);\n+\t\tunsigned int fl_out_tmp, fl_out_diff_tmp;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tif (pr_idac_major \u003e 0) {\n+\t\t\tcdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t\t pr_idac_major - 1);\n+\n+\t\t\tdev_dbg(priv-\u003edev, \"Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\\n\",\n+\t\t\t\tfl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp);\n+\n+\t\t\tcdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, index,\n+\t\t\t\t\t\t\t\t\t target_fl_out,\n+\t\t\t\t\t\t\t\t\t cdr_pr_idac_tmp);\n+\n+\t\t\tfl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, index,\n+\t\t\t\t\t\t\t\t cdr_pr_idac_tmp);\n+\t\t\tfl_out_diff_tmp = abs_diff(fl_out_tmp, target_fl_out);\n+\t\t\tif (fl_out_diff_tmp \u003c fl_out_diff) {\n+\t\t\t\tfl_out = fl_out_tmp;\n+\t\t\t\tfl_out_diff = fl_out_diff_tmp;\n+\t\t\t\tcdr_pr_idac = cdr_pr_idac_tmp;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tdev_dbg(priv-\u003edev, \"Selected CDR Pr Idac: %x Fl Out: %x\\n\", cdr_pr_idac, fl_out);\n+\tif (fl_out_diff \u003e 100)\n+\t\tdev_dbg(priv-\u003edev, \"Fl Out is %d far from target %d on intermediate calibration.\\n\",\n+\t\t\tfl_out_diff, target_fl_out);\n+\n+\t/* Setup Load Band */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x0);\n+\n+\t/* Disable force of LPF C previously enabled */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_B,\n+\t\t\tAIROHA_PCS_PMA_LOAD_EN);\n+\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_1,\n+\t\t\t AIROHA_PCS_PMA_LPATH_IDAC,\n+\t\t\t FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t AIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tusleep_range(100, 200);\n+}\n+\n+/* This is used to both calibrate and lock to signal (after a previous\n+ * calibration) after a global reset.\n+ */\n+static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t phy_interface_t interface, bool calibrate)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\n+\t/* Setup LPF L2D force and disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);\n+\n+\t/* Calibrate IDAC and setup Load Band */\n+\tif (calibrate)\n+\t\tan7581_pcs_rx_prcal(priv, index, interface);\n+\n+\t/* Setup LPF RSTB force and disable */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |\n+\t\t\t AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);\n+\n+\tusleep_range(700, 1000);\n+\n+\t/* Force Enable LPF RSTB */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);\n+\n+\tusleep_range(100, 200);\n+\n+\t/* Force Enable LPF L2D */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);\n+\n+\t/* Disable LPF RSTB force bit */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);\n+\n+\t/* Disable LPF L2D force bit */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);\n+}\n+\n+static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tint calibration_try = 0;\n+\tu32 val = 0;\n+\n+\tan7581_pcs_tx_bringup(priv, index, interface);\n+\tan7581_pcs_rx_bringup(priv, index, interface);\n+\n+\tusleep_range(100, 200);\n+\n+retry_calibration:\n+\tan7581_pcs_cdr_reset(priv, index, interface, priv-\u003emanual_rx_calib);\n+\n+\t/* Global reset clear */\n+\tregmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_REF_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_ALLPCS_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_PMA_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_TX_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_RX_RST_N |\n+\t\t\t AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,\n+\t\t\t AIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tusleep_range(100, 200);\n+\n+\t/* Global reset */\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_TX_FIFO_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_REF_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_ALLPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_PMA_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_TX_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_RX_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_RX_FIFO_RST_N);\n+\n+\tusleep_range(5000, 7000);\n+\n+\tan7581_pcs_cdr_reset(priv, index, interface, false);\n+\n+\t/* Manual RX calibration is required only for SoC before E2\n+\t * revision. E2+ SoC autocalibrate RX and only CDR reset is needed.\n+\t */\n+\tif (!priv-\u003emanual_rx_calib)\n+\t\treturn 0;\n+\n+\t/* It was discovered that after a global reset and auto mode gets\n+\t * actually enabled, the fl_out from calibration might change and\n+\t * might deviates a lot from the expected value it was calibrated for.\n+\t * To correctly work, the PCS FreqDet module needs to Lock to the fl_out\n+\t * (frequency level output) or no signal can correctly be transmitted.\n+\t * This is detected by checking the FreqDet module Lock bit.\n+\t *\n+\t * If it's detected that the FreqDet module is not locked, retry\n+\t * calibration. From observation on real hardware with a 10g SFP module,\n+\t * it required a maximum of an additional calibration to actually make\n+\t * the FreqDet module to lock. Try 50 times before failing to handle\n+\t * really strange case.\n+\t */\n+\tregmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, \u0026val);\n+\tif (!(val \u0026 AIROHA_PCS_PMA_FBCK_LOCK)) {\n+\t\tif (calibration_try \u003e AIROHA_PCS_MAX_CALIBRATION_TRY) {\n+\t\t\tdev_err(priv-\u003edev, \"No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\\n\",\n+\t\t\t\tAIROHA_PCS_MAX_CALIBRATION_TRY);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tcalibration_try++;\n+\n+\t\tdev_dbg(priv-\u003edev, \"No FBCK Lock from FreqDet module, retry calibration.\\n\");\n+\t\tgoto retry_calibration;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t int index, phy_interface_t interface)\n+{\n+\tan7581_pcs_jcpll_bringup(priv, index, interface);\n+\n+\tusleep_range(200, 300);\n+\n+\tan7581_pcs_txpll_bringup(priv, index, interface);\n+\n+\tusleep_range(200, 300);\n+}\n+\n+int an7581_pcs_bringup(struct airoha_pcs_priv *priv, int index,\n+\t\t phy_interface_t interface)\n+{\n+\tstruct regmap_field **pcs_ana_fields = priv-\u003epcs_ana_fields[index];\n+\n+\t/* Enable Analog Common Lane */\n+\tregmap_field_write(pcs_ana_fields[AN7581_PCS_CMN_EN], 0x1);\n+\n+\t/* Setup PLL */\n+\tan7581_pcs_pll_bringup(priv, index, interface);\n+\n+\tmsleep(100);\n+\n+\t/* Setup PHYA */\n+\treturn an7581_pcs_phya_bringup(priv, index, interface);\n+}\n+\n+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t int index, phy_interface_t interface)\n+{\n+\tint ret;\n+\n+\tret = phy_set_mode_ext(priv-\u003ephy, PHY_MODE_ETHERNET, interface);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR |\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 |\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR, 0xf) |\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1, 0xc) |\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, 0x3));\n+\n+\t\tregmap_set_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,\n+\t\t\t\tAIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);\n+\t} else {\n+\t\tregmap_clear_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);\n+\t}\n+\n+\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32);\n+\n+\tregmap_clear_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE);\n+\n+\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV,\n+\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, 0x1));\n+\n+\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19,\n+\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,\n+\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,\n+\t\t\t\t FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV,\n+\t\t\t\t\t\t AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK)));\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII);\n+\telse\n+\t\tregmap_update_bits(priv-\u003epcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,\n+\t\t\t\t AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII);\n+\n+\treturn 0;\n+}\n+\n+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\n+\t/* Reset TXPCS on link up */\n+\tregmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);\n+\n+\tusleep_range(100, 200);\n+\n+\tregmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);\n+}\n+\n+static int __an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv, int index,\n+\t\t\t\t\t const struct reg_field *fields)\n+{\n+\tstruct device *dev = priv-\u003edev;\n+\tint i;\n+\n+\tpriv-\u003epcs_ana_fields[index] = devm_kcalloc(dev, AN7581_PCS_FIELDS_MAX,\n+\t\t\t\t\t\t sizeof(*priv-\u003epcs_ana_fields[index]),\n+\t\t\t\t\t\t GFP_KERNEL);\n+\tif (!priv-\u003epcs_ana_fields[index])\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0; i \u003c AN7581_PCS_FIELDS_MAX; i++) {\n+\t\tstruct regmap_field *field;\n+\n+\t\tfield = devm_regmap_field_alloc(dev, priv-\u003epcs_ana,\n+\t\t\t\t\t\tfields[i]);\n+\t\tif (IS_ERR(field))\n+\t\t\treturn PTR_ERR(field);\n+\n+\t\tpriv-\u003epcs_ana_fields[index][i] = field;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)\n+{\n+\treturn __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_fields);\n+}\n+\n+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)\n+{\n+\tint ret;\n+\n+\tret = __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_pcie0_fields);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn __an7581_pcs_alloc_regmap_fields(priv, 1, an7581_pcs_pcie1_fields);\n+}\n+\n+static bool an7581_pcs_have_rx_signal(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct regmap *pcs_pma = priv-\u003epcs_pma[index];\n+\tunsigned int count = 0;\n+\tu32 val = 0;\n+\tint i;\n+\n+\tregmap_write(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_0,\n+\t\t AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN);\n+\n+\t/* Scan 6 times for RX sigdet module to detect RX signal */\n+\tfor (i = 0; i \u003c AIROHA_PCS_MAX_RX_SIGDET_TRY; i++) {\n+\t\tregmap_read(pcs_pma, AIROHA_PCS_PMA_DIG_RO_RESERVE_2,\n+\t\t\t \u0026val);\n+\t\tif (val \u0026 AIROHA_PCS_RX_SIGDET)\n+\t\t\tcount++;\n+\t}\n+\n+\t/* Consider signal presence if we detect signal at least 4 times */\n+\treturn count \u003e= AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT;\n+}\n+\n+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index)\n+{\n+\tstruct airoha_pcs_maps *maps = \u0026priv-\u003emaps[index];\n+\tu32 val = 0;\n+\n+\t/* Check if PCS is UP or Down */\n+\tregmap_read(maps-\u003eusxgmii_pcs, AIROHA_PCS_USXGMII_PCS_STUS_1, \u0026val);\n+\tif (val \u0026 AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP)\n+\t\treturn 0;\n+\n+\t/* Validate if this is consistent with RX SigDet module */\n+\tif (!an7581_pcs_have_rx_signal(priv, index))\n+\t\treturn 0;\n+\n+\t/* If PCS is down but RX SigDet module detected signal,\n+\t * trigger CDR reset.\n+\t */\n+\tan7581_pcs_cdr_reset(priv, index, PHY_INTERFACE_MODE_NA, false);\n+\n+\t/* Report there is an error with Link Detection and we\n+\t * should test again later.\n+\t */\n+\treturn -EINVAL;\n+}\ndiff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c\nnew file mode 100644\nindex 0000000000000..fef560eddf2a9\n--- /dev/null\n+++ b/drivers/net/pcs/pcs.c\n@@ -0,0 +1,314 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+\n+#include \u003clinux/mutex.h\u003e\n+#include \u003clinux/property.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/pcs/pcs.h\u003e\n+#include \u003clinux/pcs/pcs-provider.h\u003e\n+\n+MODULE_DESCRIPTION(\"PCS library\");\n+MODULE_AUTHOR(\"Christian Marangi \u003cansuelsmth@gmail.com\u003e\");\n+MODULE_LICENSE(\"GPL\");\n+\n+struct fwnode_pcs_provider {\n+\tstruct list_head link;\n+\n+\tstruct fwnode_handle *fwnode;\n+\tstruct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t void *data);\n+\n+\tvoid *data;\n+};\n+\n+static LIST_HEAD(fwnode_pcs_providers);\n+static DEFINE_MUTEX(fwnode_pcs_mutex);\n+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);\n+\n+int register_fwnode_pcs_notifier(struct notifier_block *nb)\n+{\n+\treturn blocking_notifier_chain_register(\u0026fwnode_pcs_notify_list, nb);\n+}\n+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);\n+\n+int unregister_fwnode_pcs_notifier(struct notifier_block *nb)\n+{\n+\treturn blocking_notifier_chain_unregister(\u0026fwnode_pcs_notify_list, nb);\n+}\n+EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier);\n+\n+struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t void *data)\n+{\n+\treturn data;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_xlate);\n+\n+struct fwnode_pcs_provider *\n+fwnode_pcs_add_provider(struct fwnode_handle *fwnode,\n+\t\t\tstruct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t\t\t void *data),\n+\t\t\tvoid *data)\n+{\n+\tstruct fwnode_pcs_provider *pp;\n+\n+\tif (!fwnode)\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\tpp = kzalloc_obj(*pp);\n+\tif (!pp)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tpp-\u003efwnode = fwnode_handle_get(fwnode);\n+\tpp-\u003edata = data;\n+\tpp-\u003efwnode_xlate = fwnode_xlate;\n+\n+\tmutex_lock(\u0026fwnode_pcs_mutex);\n+\n+\tlist_add(\u0026pp-\u003elink, \u0026fwnode_pcs_providers);\n+\tfwnode_dev_initialized(fwnode, true);\n+\n+\tmutex_unlock(\u0026fwnode_pcs_mutex);\n+\n+\tblocking_notifier_call_chain(\u0026fwnode_pcs_notify_list,\n+\t\t\t\t FWNODE_PCS_PROVIDER_ADD,\n+\t\t\t\t pp);\n+\n+\tpr_debug(\"Added pcs provider from %pfwf\\n\", fwnode);\n+\n+\treturn pp;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);\n+\n+void fwnode_pcs_del_provider(struct fwnode_pcs_provider *pp)\n+{\n+\tif (IS_ERR_OR_NULL(pp))\n+\t\treturn;\n+\n+\tmutex_lock(\u0026fwnode_pcs_mutex);\n+\n+\tlist_del(\u0026pp-\u003elink);\n+\tfwnode_dev_initialized(pp-\u003efwnode, false);\n+\n+\tmutex_unlock(\u0026fwnode_pcs_mutex);\n+\n+\t/* Signal phylink to release any PCS from this provider */\n+\tblocking_notifier_call_chain(\u0026fwnode_pcs_notify_list,\n+\t\t\t\t FWNODE_PCS_PROVIDER_DEL,\n+\t\t\t\t pp);\n+\n+\tfwnode_handle_put(pp-\u003efwnode);\n+\tkfree(pp);\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);\n+\n+static void devm_fwnode_pcs_del(struct device *dev, void *res)\n+{\n+\tstruct fwnode_pcs_provider *pp = *(struct fwnode_pcs_provider **)res;\n+\n+\tfwnode_pcs_del_provider(pp);\n+}\n+\n+struct fwnode_pcs_provider *\n+devm_fwnode_pcs_add_provider(struct device *dev, struct fwnode_handle *fwnode,\n+\t\t\t struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t\t\t\t void *data),\n+\t\t\t void *data)\n+{\n+\tstruct fwnode_pcs_provider **ptr, *pp;\n+\n+\tptr = devres_alloc(devm_fwnode_pcs_del, sizeof(*ptr), GFP_KERNEL);\n+\tif (!ptr)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tpp = fwnode_pcs_add_provider(fwnode, fwnode_xlate, data);\n+\n+\tif (!IS_ERR(pp)) {\n+\t\t*ptr = pp;\n+\t\tdevres_add(dev, ptr);\n+\t} else {\n+\t\tdevres_free(ptr);\n+\t}\n+\n+\treturn pp;\n+}\n+EXPORT_SYMBOL_GPL(devm_fwnode_pcs_add_provider);\n+\n+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode,\n+\t\t\t\tint index, const char *name,\n+\t\t\t\tstruct fwnode_reference_args *out_args)\n+{\n+\tif (!fwnode)\n+\t\treturn -EINVAL;\n+\n+\tif (name) {\n+\t\tindex = fwnode_property_match_string(fwnode, \"pcs-names\",\n+\t\t\t\t\t\t name);\n+\t\tif (index \u003c 0)\n+\t\t\treturn index;\n+\t}\n+\n+\treturn fwnode_property_get_reference_args(fwnode, \"pcs-handle\",\n+\t\t\t\t\t\t \"#pcs-cells\", 0, index,\n+\t\t\t\t\t\t out_args);\n+}\n+\n+static struct phylink_pcs *\n+__fwnode_pcs_get_from_pcsspec_provider(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t struct fwnode_pcs_provider *provider)\n+{\n+\tif (provider-\u003efwnode != pcsspec-\u003efwnode)\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\treturn provider-\u003efwnode_xlate(pcsspec, provider-\u003edata);\n+}\n+\n+static struct phylink_pcs *\n+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)\n+{\n+\tstruct fwnode_pcs_provider *provider;\n+\tstruct phylink_pcs *pcs = NULL;\n+\n+\tif (!pcsspec)\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\tmutex_lock(\u0026fwnode_pcs_mutex);\n+\tlist_for_each_entry(provider, \u0026fwnode_pcs_providers, link) {\n+\t\tpcs = __fwnode_pcs_get_from_pcsspec_provider(pcsspec, provider);\n+\t\tif (!IS_ERR(pcs))\n+\t\t\tbreak;\n+\t}\n+\tmutex_unlock(\u0026fwnode_pcs_mutex);\n+\n+\treturn !IS_ERR_OR_NULL(pcs) ? pcs : ERR_PTR(-ENODEV);\n+}\n+\n+static struct phylink_pcs *__fwnode_pcs_get(const struct fwnode_handle *fwnode,\n+\t\t\t\t\t unsigned int index, const char *con_id)\n+{\n+\tstruct fwnode_reference_args pcsspec;\n+\tstruct phylink_pcs *pcs;\n+\tint ret;\n+\n+\tret = fwnode_parse_pcsspec(fwnode, index, con_id, \u0026pcsspec);\n+\tif (ret)\n+\t\treturn ERR_PTR(ret);\n+\n+\tpcs = fwnode_pcs_get_from_pcsspec(\u0026pcsspec);\n+\tfwnode_handle_put(pcsspec.fwnode);\n+\n+\treturn pcs;\n+}\n+\n+struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode, unsigned int index)\n+{\n+\treturn __fwnode_pcs_get(fwnode, index, NULL);\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_get);\n+\n+struct phylink_pcs *fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,\n+\t\t\t\t\t\t const struct fwnode_handle *fwnode,\n+\t\t\t\t\t\t int index)\n+{\n+\tstruct fwnode_reference_args pcsspec;\n+\tstruct phylink_pcs *pcs;\n+\tint ret;\n+\n+\tret = fwnode_parse_pcsspec(fwnode, index, NULL, \u0026pcsspec);\n+\tif (ret)\n+\t\treturn ERR_PTR(ret);\n+\n+\tpcs = __fwnode_pcs_get_from_pcsspec_provider(\u0026pcsspec, provider);\n+\tfwnode_handle_put(pcsspec.fwnode);\n+\treturn pcs;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_get_from_provider);\n+\n+bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,\n+\t\t\t\t const struct fwnode_handle *fwnode,\n+\t\t\t\t struct phylink_pcs *pl_pcs)\n+{\n+\tstruct fwnode_reference_args pcsspec;\n+\tint index = 0;\n+\tint ret;\n+\n+\twhile (true) {\n+\t\tstruct phylink_pcs *pcs;\n+\n+\t\tret = fwnode_parse_pcsspec(fwnode, index, NULL, \u0026pcsspec);\n+\t\tif (ret)\n+\t\t\treturn false;\n+\n+\t\tpcs = __fwnode_pcs_get_from_pcsspec_provider(\u0026pcsspec, provider);\n+\t\tif (!IS_ERR(pcs) \u0026\u0026 pcs == pl_pcs) {\n+\t\t\tfwnode_handle_put(pcsspec.fwnode);\n+\t\t\treturn true;\n+\t\t}\n+\n+\t\tfwnode_handle_put(pcsspec.fwnode);\n+\t\tindex++;\n+\t}\n+\n+\treturn false;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_pcs_matches_provider);\n+\n+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)\n+{\n+\tstruct fwnode_reference_args out_args;\n+\tint index = 0;\n+\tint ret;\n+\n+\twhile (true) {\n+\t\tret = fwnode_property_get_reference_args(fwnode, \"pcs-handle\",\n+\t\t\t\t\t\t\t \"#pcs-cells\", 0, index,\n+\t\t\t\t\t\t\t \u0026out_args);\n+\t\t/* We expect to reach an -ENOENT error while counting */\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\tfwnode_handle_put(out_args.fwnode);\n+\t\tindex++;\n+\t}\n+\n+\treturn index;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_count);\n+\n+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,\n+\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t unsigned int num_pcs)\n+{\n+\tunsigned int i, found = 0;\n+\n+\tif (!available_pcs)\n+\t\treturn -EINVAL;\n+\n+\tif (!fwnode_property_present(fwnode, \"pcs-handle\"))\n+\t\treturn -ENODEV;\n+\n+\tfor (i = 0; i \u003c num_pcs; i++) {\n+\t\tstruct phylink_pcs *pcs;\n+\n+\t\tpcs = fwnode_pcs_get(fwnode, i);\n+\t\tif (IS_ERR(pcs)) {\n+\t\t\t/* Exit early if no PCS remain.*/\n+\t\t\tif (PTR_ERR(pcs) == -ENOENT)\n+\t\t\t\tbreak;\n+\n+\t\t\t/*\n+\t\t\t * Ignore -ENODEV error for PCS that still\n+\t\t\t * needs to probe.\n+\t\t\t */\n+\t\t\tif (PTR_ERR(pcs) == -ENODEV)\n+\t\t\t\tcontinue;\n+\n+\t\t\treturn PTR_ERR(pcs);\n+\t\t}\n+\n+\t\tavailable_pcs[found] = pcs;\n+\t\tfound++;\n+\t}\n+\n+\treturn found;\n+}\n+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);\ndiff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c\nindex a7d086cdc9b25..28dad1393b694 100644\n--- a/drivers/net/phy/phylink.c\n+++ b/drivers/net/phy/phylink.c\n@@ -12,6 +12,7 @@\n #include \u003clinux/netdevice.h\u003e\n #include \u003clinux/of.h\u003e\n #include \u003clinux/of_mdio.h\u003e\n+#include \u003clinux/pcs/pcs.h\u003e\n #include \u003clinux/phy.h\u003e\n #include \u003clinux/phy_fixed.h\u003e\n #include \u003clinux/phylink.h\u003e\n@@ -44,6 +45,7 @@ struct phylink {\n \tconst struct phylink_mac_ops *mac_ops;\n \tstruct phylink_config *config;\n \tstruct phylink_pcs *pcs;\n+\tstruct fwnode_handle *fwnode;\n \tstruct device *dev;\n \tunsigned int old_link_state:1;\n \n@@ -60,6 +62,15 @@ struct phylink {\n \t/* The link configuration settings */\n \tstruct phylink_link_state link_config;\n \n+\t/* List of available PCS */\n+\tstruct list_head pcs_list;\n+\tstruct notifier_block fwnode_pcs_nb;\n+\n+\t/* What interface are supported by the current link.\n+\t * Can change on removal or addition of new PCS.\n+\t */\n+\tDECLARE_PHY_INTERFACE_MASK(supported_interfaces);\n+\n \t/* The current settings */\n \tphy_interface_t cur_interface;\n \n@@ -512,6 +523,22 @@ static void phylink_validate_mask_caps(unsigned long *supported,\n \tlinkmode_and(state-\u003eadvertising, state-\u003eadvertising, mask);\n }\n \n+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,\n+\t\t\t\t\t phy_interface_t interface)\n+{\n+\t/* If PCS define an empty supported_interfaces value, assume\n+\t * all interface are supported.\n+\t */\n+\tif (phy_interface_empty(pcs-\u003esupported_interfaces))\n+\t\treturn 0;\n+\n+\t/* Ensure that this PCS supports the interface mode */\n+\tif (!test_bit(interface, pcs-\u003esupported_interfaces))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n static int phylink_validate_mac_and_pcs(struct phylink *pl,\n \t\t\t\t\tunsigned long *supported,\n \t\t\t\t\tstruct phylink_link_state *state)\n@@ -520,11 +547,30 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,\n \tunsigned long capabilities;\n \tint ret;\n \n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\n \t/* Get the PCS for this interface mode */\n \tif (pl-\u003emac_ops-\u003emac_select_pcs) {\n \t\tpcs = pl-\u003emac_ops-\u003emac_select_pcs(pl-\u003econfig, state-\u003einterface);\n-\t\tif (IS_ERR(pcs))\n+\t\tif (IS_ERR(pcs)) {\n+\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n \t\t\treturn PTR_ERR(pcs);\n+\t\t}\n+\t/*\n+\t * Find a PCS in available PCS list for the requested interface.\n+\t *\n+\t * Skip searching if the MAC doesn't require a dedicated PCS for\n+\t * the requested interface.\n+\t */\n+\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\n+\t\tstruct phylink_pcs *tmp;\n+\n+\t\tlist_for_each_entry(tmp, \u0026pl-\u003epcs_list, list) {\n+\t\t\tif (!phylink_validate_pcs_interface(tmp, state-\u003einterface)) {\n+\t\t\t\tpcs = tmp;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \t}\n \n \tif (pcs) {\n@@ -533,19 +579,18 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,\n \t\t * error and backtrace rather than oopsing the kernel.\n \t\t */\n \t\tif (!pcs-\u003eops) {\n+\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n \t\t\tphylink_err(pl, \"interface %s: uninitialised PCS\\n\",\n \t\t\t\t phy_modes(state-\u003einterface));\n \t\t\tdump_stack();\n \t\t\treturn -EINVAL;\n \t\t}\n \n-\t\t/* Ensure that this PCS supports the interface which the MAC\n-\t\t * returned it for. It is an error for the MAC to return a PCS\n-\t\t * that does not support the interface mode.\n-\t\t */\n-\t\tif (!phy_interface_empty(pcs-\u003esupported_interfaces) \u0026\u0026\n-\t\t !test_bit(state-\u003einterface, pcs-\u003esupported_interfaces)) {\n-\t\t\tphylink_err(pl, \"MAC returned PCS which does not support %s\\n\",\n+\t\t/* Recheck PCS to handle legacy way for .mac_select_pcs */\n+\t\tret = phylink_validate_pcs_interface(pcs, state-\u003einterface);\n+\t\tif (ret) {\n+\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\t\t\tphylink_err(pl, \"selected PCS does not support %s\\n\",\n \t\t\t\t phy_modes(state-\u003einterface));\n \t\t\treturn -EINVAL;\n \t\t}\n@@ -553,8 +598,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,\n \t\t/* Validate the link parameters with the PCS */\n \t\tif (pcs-\u003eops-\u003epcs_validate) {\n \t\t\tret = pcs-\u003eops-\u003epcs_validate(pcs, supported, state);\n-\t\t\tif (ret \u003c 0 || phylink_is_empty_linkmode(supported))\n+\t\t\tif (ret \u003c 0 || phylink_is_empty_linkmode(supported)) {\n+\t\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n \t\t\t\treturn -EINVAL;\n+\t\t\t}\n \n \t\t\t/* Ensure the advertising mask is a subset of the\n \t\t\t * supported mask.\n@@ -564,6 +611,8 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,\n \t\t}\n \t}\n \n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n \t/* Then validate the link parameters with the MAC */\n \tif (pl-\u003emac_ops-\u003emac_get_caps)\n \t\tcapabilities = pl-\u003emac_ops-\u003emac_get_caps(pl-\u003econfig,\n@@ -628,7 +677,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,\n static int phylink_validate(struct phylink *pl, unsigned long *supported,\n \t\t\t struct phylink_link_state *state)\n {\n-\tconst unsigned long *interfaces = pl-\u003econfig-\u003esupported_interfaces;\n+\tconst unsigned long *interfaces = pl-\u003esupported_interfaces;\n \n \tif (state-\u003einterface == PHY_INTERFACE_MODE_NA)\n \t\treturn phylink_validate_mask(pl, NULL, supported, state,\n@@ -940,6 +989,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,\n \t\tpcs-\u003eops-\u003epcs_link_up(pcs, neg_mode, interface, speed, duplex);\n }\n \n+static void phylink_pcs_link_down(struct phylink_pcs *pcs)\n+{\n+\tif (pcs \u0026\u0026 pcs-\u003eops-\u003epcs_link_down)\n+\t\tpcs-\u003eops-\u003epcs_link_down(pcs);\n+}\n+\n static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)\n {\n \tif (pcs \u0026\u0026 pcs-\u003eops-\u003epcs_disable_eee)\n@@ -958,16 +1013,34 @@ static void phylink_pcs_enable_eee(struct phylink_pcs *pcs)\n static unsigned int phylink_inband_caps(struct phylink *pl,\n \t\t\t\t\t phy_interface_t interface)\n {\n-\tstruct phylink_pcs *pcs;\n+\tstruct phylink_pcs *pcs = NULL;\n+\tint ret = 0;\n \n-\tif (!pl-\u003emac_ops-\u003emac_select_pcs)\n-\t\treturn 0;\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\n+\tif (pl-\u003emac_ops-\u003emac_select_pcs) {\n+\t\tpcs = pl-\u003emac_ops-\u003emac_select_pcs(pl-\u003econfig,\n+\t\t\t\t\t\t interface);\n+\t} else if (test_bit(interface, pl-\u003econfig-\u003epcs_interfaces)) {\n+\t\tstruct phylink_pcs *tmp;\n+\n+\t\tlist_for_each_entry(tmp, \u0026pl-\u003epcs_list, list) {\n+\t\t\tif (!phylink_validate_pcs_interface(tmp, interface)) {\n+\t\t\t\tpcs = tmp;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n \n-\tpcs = pl-\u003emac_ops-\u003emac_select_pcs(pl-\u003econfig, interface);\n \tif (IS_ERR_OR_NULL(pcs))\n-\t\treturn 0;\n+\t\tgoto exit;\n \n-\treturn phylink_pcs_inband_caps(pcs, interface);\n+\tret = phylink_pcs_inband_caps(pcs, interface);\n+\n+exit:\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n+\treturn ret;\n }\n \n static void phylink_pcs_poll_stop(struct phylink *pl)\n@@ -1260,10 +1333,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,\n \t\t\tpl-\u003emajor_config_failed = true;\n \t\t\treturn;\n \t\t}\n+\t/* Find a PCS in available PCS list for the requested interface.\n+\t * This doesn't overwrite the previous .mac_select_pcs as either\n+\t * .mac_select_pcs or PCS list implementation are permitted.\n+\t *\n+\t * Skip searching if the MAC doesn't require a dedicated PCS for\n+\t * the requested interface.\n+\t */\n+\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\n+\t\tstruct phylink_pcs *tmp;\n+\n+\t\tlist_for_each_entry(tmp, \u0026pl-\u003epcs_list, list) {\n+\t\t\tif (!phylink_validate_pcs_interface(tmp,\n+\t\t\t\t\t\t\t state-\u003einterface)) {\n+\t\t\t\tpcs = tmp;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \n-\t\tpcs_changed = pl-\u003epcs != pcs;\n+\t\tif (!pcs) {\n+\t\t\tphylink_err(pl,\n+\t\t\t\t \"couldn't find a PCS for %s\\n\",\n+\t\t\t\t phy_modes(state-\u003einterface));\n+\n+\t\t\tpl-\u003emajor_config_failed = true;\n+\t\t\treturn;\n+\t\t}\n \t}\n \n+\tpcs_changed = pl-\u003epcs != pcs;\n+\n \tphylink_pcs_neg_mode(pl, pcs, state-\u003einterface, state-\u003eadvertising);\n \n \tphylink_dbg(pl, \"major config, active %s/%s/%s\\n\",\n@@ -1290,13 +1389,15 @@ static void phylink_major_config(struct phylink *pl, bool restart,\n \tif (pcs_changed) {\n \t\tphylink_pcs_disable(pl-\u003epcs);\n \n-\t\tif (pl-\u003epcs)\n-\t\t\tpl-\u003epcs-\u003ephylink = NULL;\n+\t\tif (pl-\u003emac_ops-\u003emac_select_pcs) {\n+\t\t\tif (pl-\u003epcs)\n+\t\t\t\tpl-\u003epcs-\u003ephylink = NULL;\n \n-\t\tif (pcs)\n-\t\t\tpcs-\u003ephylink = pl;\n+\t\t\tif (pcs)\n+\t\t\t\tpcs-\u003ephylink = pl;\n+\t\t}\n \n-\t\tpl-\u003epcs = pcs;\n+\t\tWRITE_ONCE(pl-\u003epcs, pcs);\n \t}\n \n \tif (pl-\u003epcs)\n@@ -1480,7 +1581,9 @@ static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)\n \tphylink_apply_manual_flow(pl, \u0026link_state);\n \tif (phy)\n \t\tmutex_lock(\u0026phy-\u003elock);\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n \tphylink_major_config(pl, force_restart, \u0026link_state);\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n \tif (phy)\n \t\tmutex_unlock(\u0026phy-\u003elock);\n }\n@@ -1604,6 +1707,9 @@ static void phylink_link_down(struct phylink *pl)\n \n \tpl-\u003emac_ops-\u003emac_link_down(pl-\u003econfig, pl-\u003eact_link_an_mode,\n \t\t\t\t pl-\u003ecur_interface);\n+\n+\tphylink_pcs_link_down(pl-\u003epcs);\n+\n \tphylink_info(pl, \"Link is Down\\n\");\n }\n \n@@ -1831,6 +1937,179 @@ int phylink_set_fixed_link(struct phylink *pl,\n }\n EXPORT_SYMBOL_GPL(phylink_set_fixed_link);\n \n+static bool phylink_add_pcs(struct phylink *pl, struct phylink_pcs *pcs)\n+{\n+\tstruct phylink_pcs *tmp;\n+\n+\t/*\n+\t * Make sure state mutex is locked to protect concurrent\n+\t * access to phylink instance PCS list from\n+\t * initial fill_available_pcs and late PCS attach\n+\t */\n+\tlockdep_assert_held(\u0026pl-\u003estate_mutex);\n+\n+\t/* Make sure PCS is not already in the list */\n+\tlist_for_each_entry(tmp, \u0026pl-\u003epcs_list, list)\n+\t\tif (tmp == pcs)\n+\t\t\treturn false;\n+\n+\tlist_add_tail(\u0026pcs-\u003elist, \u0026pl-\u003epcs_list);\n+\n+\t/* Link PCS to phylink */\n+\tpcs-\u003ephylink = pl;\n+\n+\treturn true;\n+}\n+\n+static int phylink_fill_available_pcs(struct phylink *pl,\n+\t\t\t\t struct phylink_config *config)\n+{\n+\tstruct phylink_pcs **pcss;\n+\tint i, ret;\n+\n+\tif (!config-\u003enum_possible_pcs)\n+\t\treturn 0;\n+\n+\tif (!config-\u003efill_available_pcs) {\n+\t\tdev_err(config-\u003edev,\n+\t\t\t\"phylink: error: num_possible_pcs defined but no fill_available_pcs\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpcss = kzalloc_objs(*pcss, config-\u003enum_possible_pcs);\n+\tif (!pcss)\n+\t\treturn -ENOMEM;\n+\n+\t/* Lock state_mutex while filling to handle PCS notify */\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\n+\tret = config-\u003efill_available_pcs(config, pcss, config-\u003enum_possible_pcs);\n+\tif (ret \u003c 0)\n+\t\tgoto out;\n+\n+\tfor (i = 0; i \u003c config-\u003enum_possible_pcs; i++) {\n+\t\tstruct phylink_pcs *pcs = pcss[i];\n+\n+\t\tif (!pcs)\n+\t\t\tcontinue;\n+\n+\t\tphylink_add_pcs(pl, pcs);\n+\t}\n+\n+out:\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n+\tkfree(pcss);\n+\n+\treturn ret;\n+}\n+\n+static void phylink_del_pcs(struct phylink *pl, struct phylink_pcs *pcs)\n+{\n+\tlockdep_assert_held(\u0026pl-\u003estate_mutex);\n+\n+\tlist_del(\u0026pcs-\u003elist);\n+\tpcs-\u003ephylink = NULL;\n+\n+\t/*\n+\t * Check if we are removing the PCS currently\n+\t * in use by this phylink instance. If this is the case,\n+\t * tear down the link, force phylink resolve to reconfigure the\n+\t * interface mode, disable the current PCS and set the\n+\t * phylink PCS to NULL.\n+\t */\n+\tif (pl-\u003epcs == pcs) {\n+\t\tif (pl-\u003eold_link_state) {\n+\t\t\tphylink_link_down(pl);\n+\t\t\tpl-\u003eold_link_state = false;\n+\t\t}\n+\t\tif (pl-\u003ecfg_link_an_mode == MLO_AN_INBAND)\n+\t\t\ttimer_delete_sync(\u0026pl-\u003elink_poll);\n+\t\tphylink_pcs_disable(pl-\u003epcs);\n+\n+\t\tpl-\u003eforce_major_config = true;\n+\t\tWRITE_ONCE(pl-\u003epcs, NULL);\n+\t}\n+}\n+\n+static int pcs_provider_notify(struct notifier_block *self,\n+\t\t\t unsigned long val, void *data)\n+{\n+\tstruct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);\n+\tstruct fwnode_pcs_provider *pp = data;\n+\tstruct phylink_pcs *pcs, *tmp;\n+\tbool resolve = false;\n+\tint count, i;\n+\n+\trtnl_lock();\n+\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\n+\tswitch (val) {\n+\tcase FWNODE_PCS_PROVIDER_ADD:\n+\t\tcount = fwnode_phylink_pcs_count(pl-\u003efwnode);\n+\t\tfor (i = 0; i \u003c count; i++) {\n+\t\t\tpcs = fwnode_pcs_get_from_provider(pp, pl-\u003efwnode, i);\n+\t\t\tif (IS_ERR(pcs))\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Trigger a resolve only if a PCS is actually added */\n+\t\t\tif (phylink_add_pcs(pl, pcs))\n+\t\t\t\tresolve = true;\n+\t\t}\n+\n+\t\t/* Force an interface reconfig if major config fail */\n+\t\tif (resolve \u0026\u0026 pl-\u003emajor_config_failed)\n+\t\t\tpl-\u003eforce_major_config = true;\n+\n+\t\tbreak;\n+\tcase FWNODE_PCS_PROVIDER_DEL:\n+\t\t/*\n+\t\t * Loop all the PCS for phylink instance and check if\n+\t\t * this notification is relevant for some of them.\n+\t\t */\n+\t\tlist_for_each_entry_safe(pcs, tmp, \u0026pl-\u003epcs_list, list) {\n+\t\t\tif (!fwnode_pcs_matches_provider(pp, pl-\u003efwnode, pcs))\n+\t\t\t\tcontinue;\n+\n+\t\t\tphylink_del_pcs(pl, pcs);\n+\t\t\tresolve = true;\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\t/* Exit early if nothing has changed */\n+\tif (!resolve) {\n+\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n+\t\trtnl_unlock();\n+\n+\t\treturn NOTIFY_DONE;\n+\t}\n+\n+\t/* Refresh supported interfaces */\n+\tphy_interface_copy(pl-\u003esupported_interfaces,\n+\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n+\t\tphy_interface_or(pl-\u003esupported_interfaces,\n+\t\t\t\t pl-\u003esupported_interfaces,\n+\t\t\t\t pcs-\u003esupported_interfaces);\n+\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n+\t/* Recalculate capabilities */\n+\tlinkmode_fill(pl-\u003esupported);\n+\tlinkmode_fill(pl-\u003elink_config.advertising);\n+\tphylink_validate_mask(pl, NULL, pl-\u003esupported, \u0026pl-\u003elink_config,\n+\t\t\t pl-\u003esupported_interfaces);\n+\n+\trtnl_unlock();\n+\n+\tphylink_run_resolve(pl);\n+\n+\treturn NOTIFY_OK;\n+}\n+\n /**\n * phylink_update_pause_state() - Update the phylink pause frame configuration\n * @pl: a pointer to a \u0026struct phylink instance\n@@ -1972,9 +2251,20 @@ struct phylink *phylink_create(struct phylink_config *config,\n \t\t\t phy_interface_t iface,\n \t\t\t const struct phylink_mac_ops *mac_ops)\n {\n+\tstruct phylink_pcs *tmp, *pcs;\n \tstruct phylink *pl;\n \tint ret;\n \n+\t/*\n+\t * Make sure either PCS internal validation or .mac_select_pcs\n+\t * is used. Return error if both are defined.\n+\t */\n+\tif (config-\u003enum_possible_pcs \u0026\u0026 mac_ops-\u003emac_select_pcs) {\n+\t\tdev_err(config-\u003edev,\n+\t\t\t\"phylink: error: either phylink_config .num_possible_pcs or .mac_select_pcs must be used\\n\");\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\n \t/* Validate the supplied configuration */\n \tif (phy_interface_empty(config-\u003esupported_interfaces)) {\n \t\tdev_err(config-\u003edev,\n@@ -1989,8 +2279,10 @@ struct phylink *phylink_create(struct phylink_config *config,\n \tmutex_init(\u0026pl-\u003ephydev_mutex);\n \tmutex_init(\u0026pl-\u003estate_mutex);\n \tINIT_WORK(\u0026pl-\u003eresolve, phylink_resolve);\n+\tINIT_LIST_HEAD(\u0026pl-\u003epcs_list);\n \n \tpl-\u003econfig = config;\n+\tpl-\u003efwnode = fwnode_handle_get((struct fwnode_handle *)fwnode);\n \tif (config-\u003etype == PHYLINK_NETDEV) {\n \t\tpl-\u003enetdev = to_net_dev(config-\u003edev);\n \t\tnetif_carrier_off(pl-\u003enetdev);\n@@ -2026,13 +2318,37 @@ struct phylink *phylink_create(struct phylink_config *config,\n \t__set_bit(PHYLINK_DISABLE_STOPPED, \u0026pl-\u003ephylink_disable_state);\n \ttimer_setup(\u0026pl-\u003elink_poll, phylink_fixed_poll, 0);\n \n+\t/* First register notifier for hotplug PCS events */\n+\tif (!phy_interface_empty(config-\u003epcs_interfaces)) {\n+\t\tpl-\u003efwnode_pcs_nb.notifier_call = pcs_provider_notify;\n+\t\tregister_fwnode_pcs_notifier(\u0026pl-\u003efwnode_pcs_nb);\n+\t}\n+\n+\t/* Fill the PCS list with available PCS from phylink config */\n+\tret = phylink_fill_available_pcs(pl, config);\n+\tif (ret \u003c 0)\n+\t\tgoto unregister_pcs_notify;\n+\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\n+\tphy_interface_copy(pl-\u003esupported_interfaces,\n+\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\n+\t/* Update supported interfaces */\n+\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n+\t\tphy_interface_or(pl-\u003esupported_interfaces,\n+\t\t\t\t pl-\u003esupported_interfaces,\n+\t\t\t\t pcs-\u003esupported_interfaces);\n+\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n \tlinkmode_fill(pl-\u003esupported);\n \tlinkmode_copy(pl-\u003elink_config.advertising, pl-\u003esupported);\n \tphylink_validate(pl, pl-\u003esupported, \u0026pl-\u003elink_config);\n \n \tret = phylink_parse_mode(pl, fwnode);\n \tif (ret \u003c 0)\n-\t\tgoto free_pl;\n+\t\tgoto unregister_pcs_notify;\n \n \tif (pl-\u003ecfg_link_an_mode == MLO_AN_FIXED) {\n \t\tret = phylink_parse_fixedlink(pl, fwnode);\n@@ -2051,7 +2367,19 @@ struct phylink *phylink_create(struct phylink_config *config,\n release_link_gpio:\n \tif (pl-\u003elink_gpio)\n \t\tgpiod_put(pl-\u003elink_gpio);\n+unregister_pcs_notify:\n+\tif (pl-\u003efwnode_pcs_nb.notifier_call)\n+\t\tunregister_fwnode_pcs_notifier(\u0026pl-\u003efwnode_pcs_nb);\n+\t/* PCS notifier might queue a resolve, cancel it */\n+\tcancel_work_sync(\u0026pl-\u003eresolve);\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\tlist_for_each_entry_safe(pcs, tmp, \u0026pl-\u003epcs_list, list) {\n+\t\tlist_del(\u0026pcs-\u003elist);\n+\t\tpcs-\u003ephylink = NULL;\n+\t}\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n free_pl:\n+\tfwnode_handle_put(pl-\u003efwnode);\n \tkfree(pl);\n \treturn ERR_PTR(ret);\n }\n@@ -2068,11 +2396,30 @@ EXPORT_SYMBOL_GPL(phylink_create);\n */\n void phylink_destroy(struct phylink *pl)\n {\n+\tstruct phylink_pcs *pcs, *tmp;\n+\n \tsfp_bus_del_upstream(pl-\u003esfp_bus);\n \tif (pl-\u003elink_gpio)\n \t\tgpiod_put(pl-\u003elink_gpio);\n \n+\t/* Unregister notifier for late PCS attach */\n+\tif (pl-\u003efwnode_pcs_nb.notifier_call)\n+\t\tunregister_fwnode_pcs_notifier(\u0026pl-\u003efwnode_pcs_nb);\n+\n \tcancel_work_sync(\u0026pl-\u003eresolve);\n+\n+\tmutex_lock(\u0026pl-\u003estate_mutex);\n+\n+\t/* Remove every PCS from phylink PCS list */\n+\tlist_for_each_entry_safe(pcs, tmp, \u0026pl-\u003epcs_list, list) {\n+\t\tpcs-\u003ephylink = NULL;\n+\t\tlist_del(\u0026pcs-\u003elist);\n+\t}\n+\n+\tmutex_unlock(\u0026pl-\u003estate_mutex);\n+\n+\tfwnode_handle_put(pl-\u003efwnode);\n+\n \tkfree(pl);\n }\n EXPORT_SYMBOL_GPL(phylink_destroy);\n@@ -2147,7 +2494,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,\n \t\t * those which the host supports.\n \t\t */\n \t\tphy_interface_and(interfaces, phy-\u003epossible_interfaces,\n-\t\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\t\t\t\t pl-\u003esupported_interfaces);\n \n \t\tif (phy_interface_empty(interfaces)) {\n \t\t\tphylink_err(pl, \"PHY has no common interfaces\\n\");\n@@ -2538,8 +2885,15 @@ void phylink_pcs_change(struct phylink_pcs *pcs, bool up)\n {\n \tstruct phylink *pl = pcs-\u003ephylink;\n \n-\tif (pl)\n-\t\tphylink_link_changed(pl, up, \"pcs\");\n+\t/*\n+\t * Ignore PCS link state change if the PCS is not\n+\t * attached to a phylink instance or the phylink\n+\t * instance is not currently using this PCS.\n+\t */\n+\tif (!pl || READ_ONCE(pl-\u003epcs) != pcs)\n+\t\treturn;\n+\n+\tphylink_link_changed(pl, up, \"pcs\");\n }\n EXPORT_SYMBOL_GPL(phylink_pcs_change);\n \n@@ -2961,12 +3315,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,\n \t\treturn interface;\n \t}\n \n-\tif (!test_bit(interface, pl-\u003econfig-\u003esupported_interfaces)) {\n+\tif (!test_bit(interface, pl-\u003esupported_interfaces)) {\n \t\tphylink_err(pl,\n \t\t\t \"selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\\n\",\n \t\t\t phy_modes(interface), interface,\n \t\t\t (int)PHY_INTERFACE_MODE_MAX,\n-\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\t\t\t pl-\u003esupported_interfaces);\n \t\treturn PHY_INTERFACE_MODE_NA;\n \t}\n \n@@ -3845,14 +4199,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)\n \n \tphylink_dbg(pl, \"optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\\n\",\n \t\t (int)PHY_INTERFACE_MODE_MAX,\n-\t\t pl-\u003econfig-\u003esupported_interfaces,\n+\t\t pl-\u003esupported_interfaces,\n \t\t (int)PHY_INTERFACE_MODE_MAX,\n \t\t pl-\u003esfp_interfaces);\n \n \t/* Find the union of the supported interfaces by the PCS/MAC and\n \t * the SFP module.\n \t */\n-\tphy_interface_and(pl-\u003esfp_interfaces, pl-\u003econfig-\u003esupported_interfaces,\n+\tphy_interface_and(pl-\u003esfp_interfaces, pl-\u003esupported_interfaces,\n \t\t\t pl-\u003esfp_interfaces);\n \tif (phy_interface_empty(pl-\u003esfp_interfaces)) {\n \t\tphylink_err(pl, \"unsupported SFP module: no common interface modes\\n\");\n@@ -4023,7 +4377,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)\n \n \t/* Set the PHY's host supported interfaces */\n \tphy_interface_and(phy-\u003ehost_interfaces, phylink_sfp_interfaces,\n-\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n+\t\t\t pl-\u003esupported_interfaces);\n \n \t/* Do the initial configuration */\n \treturn phylink_sfp_config_phy(pl, phy);\ndiff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h\nnew file mode 100644\nindex 0000000000000..15c198ffdd580\n--- /dev/null\n+++ b/include/linux/pcs/pcs-provider.h\n@@ -0,0 +1,70 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+#ifndef __LINUX_PCS_PROVIDER_H\n+#define __LINUX_PCS_PROVIDER_H\n+\n+struct fwnode_pcs_provider;\n+\n+/**\n+ * fwnode_pcs_simple_xlate - Simple xlate function to retrieve PCS\n+ * @pcsspec: reference arguments\n+ * @data: Context data (assumed assigned to the single PCS)\n+ *\n+ * Returns: the PCS pointed by data.\n+ */\n+struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t void *data);\n+\n+/**\n+ * fwnode_pcs_add_provider - Registers a new PCS provider\n+ * @fwnode: Firmware node\n+ * @fwnode_xlate: xlate function to retrieve the PCS\n+ * @data: Context data\n+ *\n+ * Register and add a new PCS provider to the global providers list\n+ * for the firmware node. The relevant PCS from the PCS provider\n+ * is retrieved from the passed fwnode_xlate function.\n+ *\n+ * The xlate function MUST return a pointer to an existing, already-allocated\n+ * struct phylink_pcs and MUST NOT dynamically allocate a new PCS.\n+ * The same PCS object must be returned for a given firmware reference and args,\n+ * as PCS pointer identity is used to associate PCS objects with their provider.\n+ *\n+ * Returns: A pointer to the registered PCS provider on success, or\n+ * an ERR_PTR() encoded error code on failure.\n+ */\n+struct fwnode_pcs_provider *\n+fwnode_pcs_add_provider(struct fwnode_handle *fwnode,\n+\t\t\tstruct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t\t\t void *data),\n+\t\t\tvoid *data);\n+\n+/**\n+ * fwnode_pcs_del_provider - Removes a PCS provider\n+ * @pp: PCS provider returned by fwnode_pcs_add_provider()\n+ */\n+void fwnode_pcs_del_provider(struct fwnode_pcs_provider *pp);\n+\n+/**\n+ * devm_fwnode_pcs_add_provider - Registers a new PCS provider\n+ * @dev: Device of the PCS provider\n+ * @fwnode: Firmware node\n+ * @fwnode_xlate: xlate function to retrieve the PCS\n+ * @data: Context data\n+ *\n+ * Register and add a new PCS provider to the global providers list\n+ * for the firmware node. The relevant PCS from the PCS provider\n+ * is retrieved from the passed fwnode_xlate function. While at that, it\n+ * also associates the device with the PCS provider using devres.\n+ * On driver detach, release function is invoked on the devres data,\n+ * then, devres data is freed.\n+ *\n+ * Returns: A pointer to the registered PCS provider on success, or\n+ * an ERR_PTR() encoded error code on failure.\n+ */\n+struct fwnode_pcs_provider *\n+devm_fwnode_pcs_add_provider(struct device *dev, struct fwnode_handle *fwnode,\n+\t\t\t struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,\n+\t\t\t\t\t\t\t\t void *data),\n+\t\t\t void *data);\n+\n+#endif /* __LINUX_PCS_PROVIDER_H */\ndiff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h\nnew file mode 100644\nindex 0000000000000..00a636c82c65f\n--- /dev/null\n+++ b/include/linux/pcs/pcs.h\n@@ -0,0 +1,174 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+#ifndef __LINUX_PCS_H\n+#define __LINUX_PCS_H\n+\n+#include \u003clinux/phylink.h\u003e\n+\n+enum fwnode_pcs_notify_event {\n+\tFWNODE_PCS_PROVIDER_ADD,\n+\tFWNODE_PCS_PROVIDER_DEL,\n+};\n+\n+struct fwnode_pcs_provider;\n+\n+#if IS_ENABLED(CONFIG_FWNODE_PCS)\n+/**\n+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode\n+ *\t\t\t\t PCS events\n+ * @nb: pointer to the notifier block\n+ *\n+ * Registers a notifier block to the fwnode_pcs_notify_list blocking\n+ * notifier chain. This allows phylink instance to subscribe for\n+ * PCS provider events.\n+ *\n+ * Returns: 0 or a negative error.\n+ */\n+int register_fwnode_pcs_notifier(struct notifier_block *nb);\n+\n+/**\n+ * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode\n+ *\t\t\t\t PCS events\n+ * @nb: pointer to the notifier block\n+ *\n+ * Unregisters a notifier block to the fwnode_pcs_notify_list blocking\n+ * notifier chain.\n+ *\n+ * Returns: 0 or a negative error.\n+ */\n+int unregister_fwnode_pcs_notifier(struct notifier_block *nb);\n+\n+/**\n+ * fwnode_pcs_get - Retrieves a PCS from a firmware node\n+ * @fwnode: firmware node\n+ * @index: index fwnode PCS handle in firmware node\n+ *\n+ * Get a PCS from the firmware node at index.\n+ *\n+ * Returns: a pointer to the phylink_pcs or a negative error pointer. Can\n+ * return -ENODEV if the PCS is not present in global providers list (either\n+ * due to driver still needs to be probed or it failed to probe/removed).\n+ */\n+struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode,\n+\t\t\t\t unsigned int index);\n+\n+/**\n+ * fwnode_pcs_get_from_provider() - Retrieve a PCS from a specific provider\n+ * @provider: PCS provider to use\n+ * @fwnode: firmware node\n+ * @index: index fwnode PCS handle in firmware node\n+ *\n+ * Get a PCS from the firmware node at index specifically provided by\n+ * passed PCS provider.\n+ *\n+ * Unlike fwnode_pcs_get(), this function does not search the global list of\n+ * PCS providers. The caller must provide the provider responsible for the\n+ * referenced PCS.\n+ *\n+ * Returns: a pointer to the phylink_pcs or a negative error pointer. Can\n+ * return -ENODEV if the PCS is not present in global providers list (either\n+ * due to driver still needs to be probed or it failed to probe/removed) or\n+ * can return -EINVAL if the PCS provider doesn't expose any PCS for the fwnode.\n+ */\n+struct phylink_pcs *fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,\n+\t\t\t\t\t\t const struct fwnode_handle *fwnode,\n+\t\t\t\t\t\t int index);\n+\n+/**\n+ * fwnode_pcs_matches_provider() - Check whether a PCS belongs to a provider\n+ * @provider: PCS provider to check\n+ * @fwnode: firmware node containing the PCS references\n+ * @pl_pcs: PCS to check\n+ *\n+ * Parse the PCS references from the \"pcs-handle\" property of a firmware node\n+ * and use provider to determine whether pl_pcs is one of the PCS provided by\n+ * provider.\n+ *\n+ * This function is intended to be used when handling provider removal\n+ * notifications, where the provider is already known and its PCS need to be\n+ * identified among the PCS associated with a phylink instance.\n+ *\n+ * Returns: true if pl_pcs is provided by provider and referenced by fwnode,\n+ * false otherwise.\n+ */\n+bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,\n+\t\t\t\t const struct fwnode_handle *fwnode,\n+\t\t\t\t struct phylink_pcs *pl_pcs);\n+\n+/**\n+ * fwnode_phylink_pcs_count - Count PCS entries described in firmware node\n+ * @fwnode: firmware node\n+ *\n+ * Helper function to count the number of PCS entries referenced by the\n+ * \"pcs-handle\" property in a firmware node.\n+ *\n+ * Note that this function counts all PCS references in the firmware node,\n+ * regardless of whether the corresponding PCS devices are already probed.\n+ *\n+ * Returns: number of PCS entries described in the firmware node.\n+ */\n+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode);\n+\n+/**\n+ * fwnode_phylink_pcs_parse - Parse available PCS from firmware node\n+ * @fwnode: firmware node\n+ * @available_pcs: pointer to preallocated array of PCS\n+ * @num_pcs: maximum number of PCS entries to scan\n+ *\n+ * Helper function that parses PCS references from the \"pcs-handle\"\n+ * property of a firmware node and fills @available_pcs with PCS that are\n+ * currently available up to @num_pcs.\n+ *\n+ * Only PCS that are currently available are stored in @available_pcs.\n+ * PCS that returns -ENODEV are skipped.\n+ *\n+ * Returns: number of PCS stored in @available_pcs, or negative error code.\n+ */\n+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,\n+\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t unsigned int num_pcs);\n+#else\n+static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline int unregister_fwnode_pcs_notifier(struct notifier_block *nb)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode,\n+\t\t\t\t\t\t unsigned int index)\n+{\n+\treturn ERR_PTR(-ENOENT);\n+}\n+\n+static inline struct phylink_pcs *\n+fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,\n+\t\t\t const struct fwnode_handle *fwnode,\n+\t\t\t int index)\n+{\n+\treturn ERR_PTR(-ENOENT);\n+}\n+\n+static inline bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,\n+\t\t\t\t\t const struct fwnode_handle *fwnode,\n+\t\t\t\t\t struct phylink_pcs *pl_pcs)\n+{\n+\treturn false;\n+}\n+\n+static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)\n+{\n+\treturn 0;\n+}\n+\n+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,\n+\t\t\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t\t\t unsigned int num_pcs)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+#endif\n+\n+#endif /* __LINUX_PCS_H */\ndiff --git a/include/linux/phylink.h b/include/linux/phylink.h\nindex 3a88a69882a61..f03c1dc0a4a11 100644\n--- a/include/linux/phylink.h\n+++ b/include/linux/phylink.h\n@@ -12,6 +12,7 @@ struct ethtool_cmd;\n struct fwnode_handle;\n struct net_device;\n struct phylink;\n+struct phylink_pcs;\n \n enum {\n \tMLO_PAUSE_NONE,\n@@ -151,6 +152,8 @@ enum phylink_op_type {\n *\t\t if MAC link is at %MLO_AN_FIXED mode.\n * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx\n * are supported by the MAC/PCS.\n+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a\n+ *\t\t dedicated PCS is required.\n * @lpi_interfaces: bitmap describing which PHY interface modes can support\n *\t\t LPI signalling.\n * @mac_capabilities: MAC pause/speed/duplex capabilities.\n@@ -160,6 +163,10 @@ enum phylink_op_type {\n * @wol_phy_legacy: Use Wake-on-Lan with PHY even if phy_can_wakeup() is false\n * @wol_phy_speed_ctrl: Use phy speed control on suspend/resume\n * @wol_mac_support: Bitmask of MAC supported %WAKE_* options\n+ * @num_possible_pcs: num of possible phylink_pcs PCS\n+ * @fill_available_pcs: callback to fill the available PCS in the passed\n+ *\t\t\tarray struct of phylink_pcs PCS available_pcs up to\n+ *\t\t\tnum_possible_pcs.\n */\n struct phylink_config {\n \tstruct device *dev;\n@@ -172,6 +179,7 @@ struct phylink_config {\n \tvoid (*get_fixed_state)(struct phylink_config *config,\n \t\t\t\tstruct phylink_link_state *state);\n \tDECLARE_PHY_INTERFACE_MASK(supported_interfaces);\n+\tDECLARE_PHY_INTERFACE_MASK(pcs_interfaces);\n \tDECLARE_PHY_INTERFACE_MASK(lpi_interfaces);\n \tunsigned long mac_capabilities;\n \tunsigned long lpi_capabilities;\n@@ -182,6 +190,11 @@ struct phylink_config {\n \tbool wol_phy_legacy;\n \tbool wol_phy_speed_ctrl;\n \tu32 wol_mac_support;\n+\n+\tunsigned int num_possible_pcs;\n+\tint (*fill_available_pcs)(struct phylink_config *config,\n+\t\t\t\t struct phylink_pcs **available_pcs,\n+\t\t\t\t unsigned int num_possible_pcs);\n };\n \n void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);\n@@ -497,6 +510,9 @@ struct phylink_pcs {\n \tstruct phylink *phylink;\n \tbool poll;\n \tbool rxc_always_on;\n+\n+\t/* private: */\n+\tstruct list_head list;\n };\n \n /**\n@@ -512,6 +528,7 @@ struct phylink_pcs {\n * @pcs_an_restart: restart 802.3z BaseX autonegotiation.\n * @pcs_link_up: program the PCS for the resolved link configuration\n * (where necessary).\n+ * @pcs_link_down: tear down link between MAC and PCS.\n * @pcs_disable_eee: optional notification to PCS that EEE has been disabled\n *\t\t at the MAC.\n * @pcs_enable_eee: optional notification to PCS that EEE will be enabled at\n@@ -539,6 +556,7 @@ struct phylink_pcs_ops {\n \tvoid (*pcs_an_restart)(struct phylink_pcs *pcs);\n \tvoid (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,\n \t\t\t phy_interface_t interface, int speed, int duplex);\n+\tvoid (*pcs_link_down)(struct phylink_pcs *pcs);\n \tvoid (*pcs_disable_eee)(struct phylink_pcs *pcs);\n \tvoid (*pcs_enable_eee)(struct phylink_pcs *pcs);\n \tint (*pcs_pre_init)(struct phylink_pcs *pcs);\n@@ -674,6 +692,16 @@ void pcs_an_restart(struct phylink_pcs *pcs);\n void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,\n \t\t phy_interface_t interface, int speed, int duplex);\n \n+/**\n+ * pcs_link_down() - tear down link between MAC and PCS\n+ * @pcs: a pointer to a \u0026struct phylink_pcs.\n+ *\n+ * This call will be made just after mac_link_down() to inform the PCS the\n+ * link has gone down. PCS should be configured to stop processing packets\n+ * for transmission and reception.\n+ */\n+void pcs_link_down(struct phylink_pcs *pcs);\n+\n /**\n * pcs_disable_eee() - Disable EEE at the PCS\n * @pcs: a pointer to a \u0026struct phylink_pcs\n"
} |
| 2/1 | 2026/10/09 21:55 | agent | patch-evaluator |
6mModel:core Args: null Results: {
"EnableConfigs": [
"PHYLINK",
"FWNODE_PCS"
],
"FocusSymbols": [
"phylink_create",
"phylink_destroy",
"phylink_pcs_change",
"phylink_update_mac_pause_capabilities",
"phylink_ethtool_ksettings_set",
"fwnode_phylink_pcs_parse",
"fwnode_phylink_pcs_count",
"fwnode_pcs_add_provider",
"fwnode_pcs_del_provider",
"fwnode_pcs_matches_provider",
"register_fwnode_pcs_notifier",
"unregister_fwnode_pcs_notifier"
],
"Reasoning": "The patch series introduces a new generic Ethernet PCS firmware node framework (drivers/net/pcs/pcs.c) and makes significant modifications to the core phylink subsystem (drivers/net/phy/phylink.c) to handle multiple PCS devices, dynamic interface mask updates, and hotplug PCS provider notifications. Phylink is reachable via standard virtualized netdevices (including USB Ethernet devices like asix and lan78xx, DSA, and PCIe drivers like r8169). Furthermore, the locking modifications introduce mutex acquisition of pl-\u003estate_mutex in phylink_validate_mac_and_pcs(), which creates a recursive deadlock hazard in reachable call paths like phylink_update_mac_pause_capabilities(). Therefore, the changes affect reachable code and warrant fuzzing.",
"WorthFuzzing": true
}Instruction: You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.
IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.
================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.
- REACHABILITY IS THE PRIMARY GATE:
Fuzzing can only discover bugs in code that can actually execute in standard virtualized
environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
regardless of whether it adds assertions or complex logic.
- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
Patch authors routinely label changes as "cleanups", "refactorings", or state
"No functional change intended". Do NOT take these claims at face value.
Code refactorings that rearrange logic, introduce helper functions, or alter state management
in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
If reachable executable code is modified or refactored, it MUST be fuzzed.
- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
Even if the author believes the invariant always holds, fuzzing is essential to verify whether
an unusual sequence of operations can violate it.
================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:
- Non-kernel and non-executable changes:
* Modifications to Documentation/, comments, or spelling fixes.
* User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
that do not affect the compiled kernel image (vmlinux) or kernel modules.
* Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
that do not alter control flow or data structures.
* Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
* Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
* Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
physical PCI hot-unplug or manual sysfs driver unbinding.
* Code paths exclusive to architectures other than the target architecture.
================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
* Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
* Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
* Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
* Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).
================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:
- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
Do NOT list generic, ubiquitous functions called by almost every program in the corpus
(including, but not limited to: general memory allocators and deallocators, page fault
and trap handlers, or core synchronization primitives; this is not an exhaustive list).
Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
which severely dilutes fuzzing effort away from the actual changes.
- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
List functions that specifically implement the logic being added or altered, or direct API entrypoints
for the subsystem feature under review.
- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).
================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.
Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.
Prompt: Target architecture: amd64
For your convenience, here is the diff of the changes:
commit fa50ce9901b4f80b61fb05d00ca168060d135a73
Author: syz-cluster <triage@syzkaller.com>
Date: Fri Oct 9 21:55:49 2026 +0000
syz-cluster: applied patch under review
diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 0000000000000..9c1d116c1b016
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,261 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+ the various Serdes port supporting different Media Independent Interface
+ (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+ compatible:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+ - airoha,an7581-pcs-pcie
+ - airoha,an7581-pcs-usb
+
+ reg:
+ minItems: 6
+ maxItems: 15
+
+ reg-names:
+ minItems: 6
+ maxItems: 15
+
+ airoha,scu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the SCU node required to configure
+ the serdes line to the correct interface mode.
+
+ phys:
+ maxItems: 1
+
+ "#pcs-cells": true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#pcs-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: USXGMII reg
+ - description: HSGMII rate adaption reg
+ - description: PCS Analog register
+ - description: PCS PMA (Physical Medium Attachment) register
+
+ reg-names:
+ items:
+ - const: pcs_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: usxgmii
+ - const: hsgmii_rate_adp
+ - const: pcs_ana
+ - const: pcs_pma
+
+ phys: false
+
+ "#pcs-cells":
+ const: 0
+
+ required:
+ - airoha,scu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: airoha,an7581-pcs-pcie
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC 0 reg
+ - description: HSGMII AN 0 reg
+ - description: HSGMII PCS 0 reg
+ - description: MULTI SGMII 0 reg
+ - description: USXGMII 0 reg
+ - description: HSGMII rate adaption 0 reg
+ - description: PCS MAC 1 reg
+ - description: HSGMII AN 1 reg
+ - description: HSGMII PCS 1 reg
+ - description: MULTI SGMII 1 reg
+ - description: USXGMII 1 reg
+ - description: HSGMII rate adaption 1 reg
+ - description: PCS Analog register
+ - description: PCS PMA (Physical Medium Attachment) 0 register
+ - description: PCS PMA (Physical Medium Attachment) 1 register
+
+ reg-names:
+ items:
+ - const: pcs_mac0
+ - const: hsgmii_an0
+ - const: hsgmii_pcs0
+ - const: multi_sgmii0
+ - const: usxgmii0
+ - const: hsgmii_rate_adp0
+ - const: pcs_mac1
+ - const: hsgmii_an1
+ - const: hsgmii_pcs1
+ - const: multi_sgmii1
+ - const: usxgmii1
+ - const: hsgmii_rate_adp1
+ - const: pcs_ana
+ - const: pcs_pma0
+ - const: pcs_pma1
+
+ phys: false
+
+ "#pcs-cells":
+ const: 1
+
+ required:
+ - airoha,scu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: airoha,an7581-pcs-usb
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: HSGMII rate adaption reg
+ - description: PCS Analog register
+
+ reg-names:
+ items:
+ - const: pcs_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: hsgmii_rate_adp
+ - const: pcs_ana
+
+ airoha,scu: false
+
+ "#pcs-cells":
+ const: 0
+
+ required:
+ - phys
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ pcs@1fa08000 {
+ compatible = "airoha,an7581-pcs-pon";
+ reg = <0x1fa08000 0x1000>,
+ <0x1fa80000 0x60>,
+ <0x1fa80a00 0x164>,
+ <0x1fa84000 0x450>,
+ <0x1fa85900 0x338>,
+ <0x1fa86000 0x300>,
+ <0x1fa8a000 0x1000>,
+ <0x1fa8b000 0x1000>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "pcs_ana", "pcs_pma";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa09000 {
+ compatible = "airoha,an7581-pcs-eth";
+ reg = <0x1fa09000 0x1000>,
+ <0x1fa70000 0x60>,
+ <0x1fa70a00 0x164>,
+ <0x1fa74000 0x450>,
+ <0x1fa75900 0x338>,
+ <0x1fa76000 0x300>,
+ <0x1fa7a000 0x1000>,
+ <0x1fa7b000 0x1000>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "pcs_ana", "pcs_pma";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa04000 {
+ compatible = "airoha,an7581-pcs-pcie";
+ reg = <0x1fa04000 0x1000>,
+ <0x1fa50000 0x60>,
+ <0x1fa50a00 0x164>,
+ <0x1fa54000 0x450>,
+ <0x1fa55900 0x338>,
+ <0x1fa56000 0x300>,
+ <0x1fa05000 0x1000>,
+ <0x1fa60000 0x60>,
+ <0x1fa60a00 0x164>,
+ <0x1fa64000 0x450>,
+ <0x1fa65900 0x338>,
+ <0x1fa66000 0x300>,
+ <0x1fa5a000 0x1000>,
+ <0x1fa5b000 0x1000>,
+ <0x1fa5c000 0x1000>;
+ reg-names = "pcs_mac0", "hsgmii_an0", "hsgmii_pcs0",
+ "multi_sgmii0", "usxgmii0",
+ "hsgmii_rate_adp0",
+ "pcs_mac1", "hsgmii_an1", "hsgmii_pcs1",
+ "multi_sgmii1", "usxgmii1",
+ "hsgmii_rate_adp1",
+ "pcs_ana", "pcs_pma0", "pcs_pma1";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <1>;
+ };
+
+ pcs@1fa07000 {
+ compatible = "airoha,an7581-pcs-usb";
+ reg = <0x1fa07000 0x1000>,
+ <0x1fa90000 0x60>,
+ <0x1fa90a00 0x164>,
+ <0x1fa94000 0x450>,
+ <0x1fa96000 0x300>,
+ <0x1fa9a000 0x600>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "hsgmii_rate_adp","pcs_ana";
+
+ phys = <&usb0_phy PHY_TYPE_USB3>;
+
+ #pcs-cells = <0>;
+ };
diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst
index 44a422ad3b055..3fce8f6ac089e 100644
--- a/Documentation/networking/index.rst
+++ b/Documentation/networking/index.rst
@@ -28,6 +28,7 @@ Contents:
net_failover
page_pool
phy
+ pcs
sfp-phylink
alias
bridge
diff --git a/Documentation/networking/pcs.rst b/Documentation/networking/pcs.rst
new file mode 100644
index 0000000000000..2cae702319484
--- /dev/null
+++ b/Documentation/networking/pcs.rst
@@ -0,0 +1,234 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=============
+PCS Subsystem
+=============
+
+The PCS (Physical Coding Sublayer) subsystem handles the registration and lookup
+of PCS devices. These devices contain the upper sublayers of the Ethernet
+physical layer, generally handling framing, scrambling, and encoding tasks. PCS
+devices may also include PMA (Physical Medium Attachment) components. PCS
+devices transfer data between the Link-layer MAC device, and the rest of the
+physical layer, typically via a serdes. The output of the serdes may be
+connected more-or-less directly to the medium when using fiber-optic or
+backplane connections (1000BASE-SX, 1000BASE-KX, etc). It may also communicate
+with a separate PHY (such as over SGMII) which handles the connection to the
+medium (such as 1000BASE-T).
+
+Remark on usage of .mac_select_pcs and fw_node PCS
+--------------------------------------------------
+
+There are generally two ways to look up a PCS device.
+
+1. MAC OP struct .mac_select_pcs (considered deprecated)
+2. Internal PCS handling with ``num_possible_pcs`` and ``fill_available_pcs``
+
+Implementation 1 leaves the entire handling of the PCS to the MAC
+driver with the selection of the PCS driven by .mac_select_pcs.
+Custom implementations are required if the PCS is external to the MAC
+and needs to be handled by a separate driver.
+
+Implementation 2 makes the phylink core code to select the PCS
+provided by ``num_possible_pcs`` and ``fill_available_pcs`` either
+via internal MAC handling or firmware node (fwnode)
+
+Implementation 1 is considered deprecated and it's suggested to
+switch to implementation 2 and where possible switch to firmware
+node design.
+
+.. _pcs_fwnode:
+
+Looking up PCS Devices (fwnode implementation)
+-----------------------------------------------
+
+The lookup of a PCS device follows the common producer/consumer implementation
+used by similar subsystems with a ``#pcs-cells`` on the producer and a
+``pcs-handle`` property on the consumer::
+
+ pcs: pcs {
+ // ...
+ #pcs-cells = <0>;
+ };
+
+ ethernet-controller {
+ // ...
+ pcs-handle = <&pcs>;
+ };
+
+On :c:func:`phylink_create`, phylink will use the ``num_possible_pcs``
+value and ``fill_available_pcs`` helper function in
+:c:struct:`phylink_config` to compose the list of available PCS that can be
+used for the phylink instance.
+
+Phylink will then internally handle the selection of the correct PCS for
+the requested interface mode based on the interface modes configured in
+``pcs_interfaces`` in :c:struct:`phylink_config` struct and
+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.
+
+A PCS is considered eligible when the requested interface mode is present
+in both ``pcs_interfaces`` in :c:struct:`phylink_config` struct and
+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.
+
+``supported_interfaces`` describes all interface modes supported by the MAC,
+whereas ``pcs_interfaces`` identifies the subset that require PCS selection.
+
+For the special implementation where the PCS is internal or part of the MAC
+and a dedicated driver is not needed, it's possible to leave the implementation
+of the PCS to the MAC driver and just implement the ``num_possible_pcs``
+value and ``fill_available_pcs`` helper function in
+:c:struct:`phylink_config` referencing the local :c:struct:`phylink_pcs`
+struct allocated from the MAC driver.
+
+.. _pcs_consumer:
+
+Using PCS Devices
+-----------------
+
+It's mandatory to either implement the ``mac_select_pcs`` callback
+of :c:struct:`phylink_mac_ops` or ``num_possible_pcs`` and ``fill_available_pcs``
+of :c:struct:`phylink_config` to use a PCS for a MAC.
+
+The fwnode implementation exposes simple helpers to parse the PCS from
+the fwnode :c:func:`fwnode_phylink_pcs_count` and
+:c:func:`fwnode_phylink_pcs_parse`. The :c:func:`fwnode_phylink_pcs_count` helper
+takes the fwnode where the ``pcs-handle`` should be parsed and return the
+number of PCS entries described in the fwnode.
+The :c:func:`fwnode_phylink_pcs_parse` helper takes three arguments,
+the fwnode where the ``pcs-handle`` should be parsed, an allocated array
+of :c:struct:`phylink_pcs` pointer where to put the parsed PCS from the fwnode
+and the maximum number of PCS to parse.
+Contrary to :c:func:`fwnode_phylink_pcs_count`, :c:func:`fwnode_phylink_pcs_parse`
+helper fills the allocated array with ONLY the available PCS and return the
+number of available PCS found. PCS that returns -ENODEV will be skipped and
+won't be inserted in the allocated array.
+
+A phylink instance may use multiple PCS devices. The maximum number is reported
+through ``num_possible_pcs``.
+
+It's mandatory to specify for what interface a PCS is needed. This can be done
+by filling the ``pcs_interfaces`` in :c:struct:`phylink_config` struct.
+If the requested interface mode is not present in this bitmask, phylink does
+not search for a PCS for that specific mode. (example MAC doesn't need a PCS
+for SGMII but require one for USXGMII)
+
+With the use of the :c:func:`fwnode_phylink_pcs_parse` a common implementation
+is the following::
+
+ static int mac_fill_available_pcs(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs)
+ {
+ struct device *dev = config->dev;
+
+ return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
+ num_possible_pcs);
+ }
+
+ static int mac_setup_phylink(struct net_device *netdev)
+ {
+ struct phylink_config *config;
+
+ // ...
+
+ config->dev = &netdev->dev;
+
+ // ...
+
+ // Parse possible PCS and fill num_possible_pcs.
+ config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(&netdev->dev));
+ config->fill_available_pcs = mac_fill_available_pcs;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces);
+
+ // PCS required only for USXGMII
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config->pcs_interfaces);
+
+ phylink = phylink_create(config, //...
+
+It's worth to mention that it's phylink code that takes care of allocating
+the array of :c:struct:`phylink_pcs` pointer for ``fill_available_pcs``
+callback based on the value set in ``num_possible_pcs`` for
+:c:struct:`phylink_config` struct.
+
+The ``fill_available_pcs`` callback must not write more than
+``num_possible_pcs`` entries. The third argument may be used to validate
+that there is enough space to fill all the available PCS in the passed array
+of :c:struct:`phylink_pcs` pointer.
+
+The ``fill_available_pcs`` callback is called only on :c:func:`phylink_create`
+and is used only to compose the initial available PCS list. Ownership of PCS
+is held by phylink.
+
+.. _pcs_producer:
+
+Writing PCS Drivers
+-------------------
+
+To write a PCS driver, first implement :c:struct:`phylink_pcs_ops`. Then,
+register your PCS in your probe function using :c:func:`fwnode_pcs_add_provider`.
+The :c:func:`fwnode_pcs_add_provider` takes three arguments, the fwnode where
+the PCS provider should be registered to, a xlate function to return the requested
+PCS based on ``#pcs-cells`` and a pointer to reference private data for the xlate
+function.
+
+The PCS will then be registered to a global list of PCS provider that the
+PCS fwnode implementation will use to parse it.
+
+For the simple case where the PCS driver expose a single PCS,
+:c:func:`fwnode_pcs_simple_xlate` can be used as the xlate function.
+
+You must call :c:func:`fwnode_pcs_del_provider` from your remove function
+on driver detach.
+
+A devm variant, :c:func:`devm_fwnode_pcs_add_provider`, is available to
+automatically release the PCS provider on driver detach.
+
+It's worth to mention that xlate function MUST reference already allocated
+:c:struct:`phylink_pcs` pointer and MUST NOT dynamically allocate new PCS.
+The returned pointer is used to identify the PCS across provider lookup and
+removal notifications.
+
+Late PCS registration handling
+------------------------------
+
+It's possible that a PCS becomes available after the MAC finished probing.
+Contrary to the usual producer/consumer implementation, when a PCS is not
+registered and can't be found, the fwnode parser helper returns ``-ENODEV``
+instead of ``-EPROBE_DEFER``.
+
+This is to prevent race condition with particular devices that register
+MAC and PCS with USB or PCIe and require the MAC to be registered before
+the PCS.
+
+The phylink logic correctly handle this special case and keep the phylink
+instance in a fail condition.
+
+The PCS fwnode implementation provides a notifier to which each phylink
+instance with a non-empty ``pcs_interfaces`` in :c:type:`phylink_config`
+registers. When a new PCS provider is registered, the notifier is called
+triggering the :c:func:`pcs_provider_notify` function.
+
+Function :c:func:`pcs_provider_notify` will check if the just added PCS
+should be used by the phylink instance. If it should be used then,
+it's added to the internal list of available PCS and a phylink major
+config is forced.
+
+If a phylink instance was in a failure state, with the just added PCS
+now part of the available PCS internal phylink list, provided all other
+conditions are satisfied, the configuration is retried and the failure
+condition is cleared.
+
+API Reference
+-------------
+
+.. kernel-doc:: include/linux/phylink.h
+ :identifiers: phylink_pcs
+
+.. kernel-doc:: include/linux/pcs/pcs.h
+ :internal:
+
+.. kernel-doc:: include/linux/pcs/pcs-provider.h
+ :internal:
diff --git a/Documentation/networking/sfp-phylink.rst b/Documentation/networking/sfp-phylink.rst
index 5bf285d73e8a1..306505118eba9 100644
--- a/Documentation/networking/sfp-phylink.rst
+++ b/Documentation/networking/sfp-phylink.rst
@@ -311,33 +311,20 @@ this documentation.
priv->pcs = lynx_pcs_create_mdiodev(bus, 0);
- Some PCS can be recovered based on firmware information:
+ PCS that should be recovered based on firmware information should implement
+ the external PCS as a :ref:`PCS provider <pcs_producer>` and reference it
+ with the use of PCS fwnode helper :ref:`PCS fwnode helper <pcs_fwnode>`.
- .. code-block:: c
-
- priv->pcs = lynx_pcs_create_fwnode(of_fwnode_handle(node));
-
-12. Populate the :c:func:`mac_select_pcs` callback and add it to your
- :c:type:`struct phylink_mac_ops <phylink_mac_ops>` set of ops. This function
- must return a pointer to the relevant :c:type:`struct phylink_pcs <phylink_pcs>`
- that will be used for the requested link configuration:
-
- .. code-block:: c
-
- static struct phylink_pcs *foo_select_pcs(struct phylink_config *config,
- phy_interface_t interface)
- {
- struct foo_priv *priv = container_of(config, struct foo_priv,
- phylink_config);
-
- if ( /* 'interface' needs a PCS to function */ )
- return priv->pcs;
+12. Populate the :c:var:`num_possible_pcs` value and
+ :c:func:`fill_available_pcs` callback and add it to your
+ :c:type:`struct phylink_config <phylink_config>`.
- return NULL;
- }
+ Refer to :ref:`Documentation/networking/pcs.rst <pcs_consumer>` for
+ further details and examples.
- See :c:func:`mvpp2_select_pcs` for an example of a driver that has multiple
- internal PCS.
+ Notice that the previous implementation of populating
+ :c:func:`mac_select_pcs` is considered deprecated in favor of the new
+ described above.
13. Fill-in all the :c:type:`phy_interface_t <phy_interface_t>` (i.e. all MAC to
PHY link modes) that your MAC can output. The following example shows a
diff --git a/MAINTAINERS b/MAINTAINERS
index 509b35b5a0e7a..d8533e36941c7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9759,6 +9759,15 @@ F: include/uapi/linux/if_bridge.h
F: include/linux/netfilter_bridge/
F: net/bridge/
+ETHERNET PCS SUBSYSTEM
+M: Christian Marangi <ansuelsmth@gmail.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/networking/pcs.rst
+F: drivers/net/pcs/pcs.c
+F: include/linux/pcs/pcs-provider.h
+F: include/linux/pcs/pcs.h
+
ETHERNET PHY LIBRARY
M: Andrew Lunn <andrew@lunn.ch>
M: Heiner Kallweit <hkallweit1@gmail.com>
diff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig
index 1f6640a15fc94..5c54a07d2a768 100644
--- a/drivers/net/ethernet/airoha/Kconfig
+++ b/drivers/net/ethernet/airoha/Kconfig
@@ -20,6 +20,8 @@ config NET_AIROHA
depends on NET_DSA || !NET_DSA
select NET_AIROHA_NPU
select PAGE_POOL
+ select PCS_AIROHA
+ select PHYLINK
help
This driver supports the gigabit ethernet MACs in the
Airoha SoC family.
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index b164a78ddac9d..81a8da721c13a 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -6,6 +6,7 @@
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/of_reserved_mem.h>
+#include <linux/pcs/pcs.h>
#include <linux/platform_device.h>
#include <linux/tcp.h>
#include <linux/u64_stats_sync.h>
@@ -2194,10 +2195,18 @@ static int airoha_dev_open(struct net_device *netdev)
return -EBUSY;
}
+ err = phylink_of_phy_connect(dev->phylink, netdev->dev.of_node, 0);
+ if (err) {
+ netdev_err(netdev, "could not attach PHY: %d\n", err);
+ return err;
+ }
+
+ phylink_start(dev->phylink);
+
netif_tx_start_all_queues(netdev);
err = airoha_set_vip_for_gdm_port(dev, true);
if (err)
- return err;
+ goto err_phy_stop;
if (netdev_uses_dsa(netdev))
airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
@@ -2219,6 +2228,12 @@ static int airoha_dev_open(struct net_device *netdev)
airoha_dev_lro_enable(dev);
return 0;
+
+err_phy_stop:
+ phylink_stop(dev->phylink);
+ phylink_disconnect_phy(dev->phylink);
+
+ return err;
}
static int airoha_dev_stop(struct net_device *netdev)
@@ -2226,6 +2241,8 @@ static int airoha_dev_stop(struct net_device *netdev)
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
+ phylink_stop(dev->phylink);
+
netif_tx_disable(netdev);
airoha_set_vip_for_gdm_port(dev, false);
@@ -2239,6 +2256,8 @@ static int airoha_dev_stop(struct net_device *netdev)
if (netdev->features & NETIF_F_LRO)
airoha_dev_lro_disable(dev);
+ phylink_disconnect_phy(dev->phylink);
+
return 0;
}
@@ -2829,6 +2848,24 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,
} while (u64_stats_fetch_retry(&dev->stats.syncp, start));
}
+static int
+airoha_ethtool_get_link_ksettings(struct net_device *netdev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ return phylink_ethtool_ksettings_get(dev->phylink, cmd);
+}
+
+static int
+airoha_ethtool_set_link_ksettings(struct net_device *netdev,
+ const struct ethtool_link_ksettings *cmd)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ return phylink_ethtool_ksettings_set(dev->phylink, cmd);
+}
+
static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev,
int channel, enum tx_sched_mode mode,
const u16 *weights, u8 n_weights)
@@ -3696,7 +3733,8 @@ static const struct ethtool_ops airoha_ethtool_ops = {
.get_drvinfo = airoha_ethtool_get_drvinfo,
.get_eth_mac_stats = airoha_ethtool_get_mac_stats,
.get_rmon_stats = airoha_ethtool_get_rmon_stats,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .get_link_ksettings = airoha_ethtool_get_link_ksettings,
+ .set_link_ksettings = airoha_ethtool_set_link_ksettings,
.get_link = ethtool_op_get_link,
};
@@ -3752,6 +3790,155 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
return false;
}
+/* Nothing to do in MAC, everything is handled in PCS */
+static void airoha_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+}
+
+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
+ unsigned int mode, phy_interface_t interface,
+ int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+ struct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev,
+ phylink_config);
+ struct airoha_gdm_port *port = dev->port;
+ struct airoha_eth *eth = dev->eth;
+ u32 frag_size_tx, frag_size_rx;
+
+ /* TX/RX frag is configured only for GDM4 */
+ if (port->id != AIROHA_GDM4_IDX)
+ return;
+
+ switch (speed) {
+ case SPEED_10000:
+ case SPEED_5000:
+ frag_size_tx = 8;
+ frag_size_rx = 8;
+ break;
+ case SPEED_2500:
+ frag_size_tx = 2;
+ frag_size_rx = 1;
+ break;
+ default:
+ frag_size_tx = 1;
+ frag_size_rx = 0;
+ break;
+ }
+
+ mutex_lock(&port->link_lock);
+
+ /* Configure TX/RX frag based on speed */
+ if (dev->nbq == 1) {
+ airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG,
+ GDM4_SGMII1_TX_FRAG_SIZE_MASK,
+ FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK,
+ frag_size_tx));
+
+ airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG,
+ GDM4_SGMII1_RX_FRAG_SIZE_MASK,
+ FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK,
+ frag_size_rx));
+ } else {
+ airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG,
+ GDM4_SGMII0_TX_FRAG_SIZE_MASK,
+ FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK,
+ frag_size_tx));
+
+ airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG,
+ GDM4_SGMII0_RX_FRAG_SIZE_MASK,
+ FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK,
+ frag_size_rx));
+ }
+
+ mutex_unlock(&port->link_lock);
+}
+
+/* Nothing to do in MAC, everything is handled in PCS */
+static void airoha_mac_link_down(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+}
+
+static const struct phylink_mac_ops airoha_phylink_ops = {
+ .mac_config = airoha_mac_config,
+ .mac_link_up = airoha_mac_link_up,
+ .mac_link_down = airoha_mac_link_down,
+};
+
+static int airoha_fill_available_pcs(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs)
+{
+ struct device *dev = config->dev;
+
+ return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
+ num_possible_pcs);
+}
+
+static int airoha_setup_phylink(struct net_device *netdev)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+ struct device_node *np = netdev->dev.of_node;
+ struct airoha_gdm_port *port = dev->port;
+ struct phylink_config *config;
+ phy_interface_t phy_mode;
+ struct phylink *phylink;
+ int err;
+
+ err = of_get_phy_mode(np, &phy_mode);
+ if (err) {
+ dev_err(&netdev->dev, "incorrect phy-mode\n");
+ return err;
+ }
+
+ config = &dev->phylink_config;
+ config->dev = &netdev->dev;
+ config->type = PHYLINK_NETDEV;
+
+ /*
+ * GDM1 only supports internal for Embedded Switch
+ * and doesn't require a PCS.
+ */
+ if (port->id == AIROHA_GDM1_IDX) {
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10000FD;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ } else {
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000 |
+ MAC_2500FD | MAC_5000FD | MAC_10000FD;
+
+ config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config->dev));
+ config->fill_available_pcs = airoha_fill_available_pcs;
+
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ config->supported_interfaces);
+
+ phy_interface_copy(config->pcs_interfaces,
+ config->supported_interfaces);
+ }
+
+ phylink = phylink_create(config, of_fwnode_handle(np),
+ phy_mode, &airoha_phylink_ops);
+ if (IS_ERR(phylink))
+ return PTR_ERR(phylink);
+
+ dev->phylink = phylink;
+
+ return 0;
+}
+
static int airoha_alloc_gdm_device(struct airoha_eth *eth,
struct airoha_gdm_port *port,
int nbq, struct device_node *np)
@@ -3815,7 +4002,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
dev->nbq = nbq;
port->devs[index] = dev;
- return 0;
+ return airoha_setup_phylink(netdev);
}
static int airoha_alloc_gdm_port(struct airoha_eth *eth,
@@ -3851,6 +4038,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
port->id = id;
spin_lock_init(&port->stats_lock);
+ mutex_init(&port->link_lock);
eth->ports[p] = port;
err = airoha_metadata_dst_alloc(port);
@@ -4047,6 +4235,8 @@ static int airoha_probe(struct platform_device *pdev)
netdev = netdev_from_priv(dev);
if (netdev->reg_state == NETREG_REGISTERED)
unregister_netdev(netdev);
+ if (dev->phylink)
+ phylink_destroy(dev->phylink);
of_node_put(netdev->dev.of_node);
}
airoha_metadata_dst_free(port);
@@ -4085,6 +4275,7 @@ static void airoha_remove(struct platform_device *pdev)
netdev = netdev_from_priv(dev);
unregister_netdev(netdev);
+ phylink_destroy(dev->phylink);
of_node_put(netdev->dev.of_node);
}
airoha_metadata_dst_free(port);
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index d270729e22ff9..909e75fec2797 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -612,6 +612,9 @@ struct airoha_gdm_dev {
* QDMA migration.
*/
spinlock_t txq_lock[AIROHA_NUM_NETDEV_TX_RINGS];
+
+ struct phylink *phylink;
+ struct phylink_config phylink_config;
};
struct airoha_gdm_port {
@@ -621,6 +624,8 @@ struct airoha_gdm_port {
/* protect concurrent hw_stats accesses */
spinlock_t stats_lock;
+ /* protect concurrent GDM4 register access */
+ struct mutex link_lock;
struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
};
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index 07dd04859fde8..94d53d4c3ab70 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -371,6 +371,18 @@
#define IP_FRAGMENT_PORT_MASK GENMASK(8, 5)
#define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0)
+#define REG_FE_GDM4_TMBI_FRAG 0x2028
+#define GDM4_SGMII1_TX_WEIGHT_MASK GENMASK(31, 26)
+#define GDM4_SGMII1_TX_FRAG_SIZE_MASK GENMASK(25, 16)
+#define GDM4_SGMII0_TX_WEIGHT_MASK GENMASK(15, 10)
+#define GDM4_SGMII0_TX_FRAG_SIZE_MASK GENMASK(9, 0)
+
+#define REG_FE_GDM4_RMBI_FRAG 0x202c
+#define GDM4_SGMII1_RX_WEIGHT_MASK GENMASK(31, 26)
+#define GDM4_SGMII1_RX_FRAG_SIZE_MASK GENMASK(25, 16)
+#define GDM4_SGMII0_RX_WEIGHT_MASK GENMASK(15, 10)
+#define GDM4_SGMII0_RX_FRAG_SIZE_MASK GENMASK(9, 0)
+
#define REG_MC_VLAN_EN 0x2100
#define MC_VLAN_EN_MASK BIT(0)
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index e417fd66f660a..8fae619f24322 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,12 @@
menu "PCS device drivers"
+config FWNODE_PCS
+ bool "PCS Firmware Node"
+ depends on ACPI || OF || COMPILE_TEST
+ help
+ Firmware node PCS accessors
+
config PCS_XPCS
tristate "Synopsys DesignWare Ethernet XPCS"
select PHYLINK
@@ -35,4 +41,6 @@ config PCS_RZN1_MIIC
Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to
RMII/RGMII, or can be set in pass-through mode for MII.
+source "drivers/net/pcs/airoha/Kconfig"
+
endmenu
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b900..91593aa8d9266 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for Linux PCS drivers
+obj-$(CONFIG_FWNODE_PCS) += pcs.o
pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
pcs-xpcs-nxp.o pcs-xpcs-wx.o
@@ -8,3 +9,5 @@ obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o
obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
+
+obj-$(CONFIG_PCS_AIROHA) += airoha/
diff --git a/drivers/net/pcs/airoha/Kconfig b/drivers/net/pcs/airoha/Kconfig
new file mode 100644
index 0000000000000..1aa4c0d33b87d
--- /dev/null
+++ b/drivers/net/pcs/airoha/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PCS_AIROHA
+ tristate
+ select FWNODE_PCS
+
+config PCS_AIROHA_AN7581
+ tristate "Airoha AN7581 PCS driver"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ select PCS_AIROHA
+ help
+ This module provides helper to phylink for managing the Airoha
+ AN7581 PCS for SoC Ethernet and PON SERDES.
diff --git a/drivers/net/pcs/airoha/Makefile b/drivers/net/pcs/airoha/Makefile
new file mode 100644
index 0000000000000..c5201d5cc3569
--- /dev/null
+++ b/drivers/net/pcs/airoha/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PCS_AIROHA) := pcs-airoha.o
+pcs-airoha-objs := pcs-airoha-common.o
+ifdef CONFIG_PCS_AIROHA_AN7581
+pcs-airoha-objs += pcs-an7581.o
+endif
diff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c
new file mode 100644
index 0000000000000..d9ec0e97b746a
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c
@@ -0,0 +1,1303 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/rtnetlink.h>
+
+#include "pcs-airoha.h"
+
+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
+ AIROHA_SCU_ETH_XSI_SEL,
+ xsi_sel);
+}
+
+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel, wan_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PON_XSI_SEL,
+ xsi_sel);
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+ AIROHA_SCU_WAN_SEL,
+ wan_sel);
+}
+
+static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ if (index == 0) {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_PCIE_XSI0_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI0_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI0_SEL,
+ xsi_sel);
+ } else {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI1_SEL,
+ xsi_sel);
+ }
+}
+
+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ int ret;
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ airoha_pcs_setup_scu_eth(priv, interface);
+ break;
+ case AIROHA_PCS_PON:
+ airoha_pcs_setup_scu_pon(priv, interface);
+ break;
+ case AIROHA_PCS_PCIE:
+ airoha_pcs_setup_scu_pcie(priv, index, interface);
+ break;
+ case AIROHA_PCS_USB:
+ break;
+ }
+
+ ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_set_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ /* Disable Hibernation */
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+ AIROHA_PCS_USXGMII_SPEED_SEL_H);
+
+ /* FIXME: wait Airoha */
+ /* Avoid PCS sending garbage to MAC in some HW revision (E0) */
+ regmap_write(maps->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+}
+
+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE,
+ priv->phy ? 0 : AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
+
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
+}
+
+static void airoha_pcs_init(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_init_sgmii(priv, index);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_init_hsgmii(priv, index);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_init_usxgmii(priv, index);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ /* Disable every interrupt */
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+ /* Clear interrupt */
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+}
+
+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ /* Disable every Interrupt */
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
+ AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
+ AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
+ AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
+
+ /* Clear any pending interrupt */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT);
+
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT);
+
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
+
+ /* Interrupt saddly seems to be not weel supported for Link Down.
+ * PCS Poll is a must to correctly read and react on Cable Deatch
+ * as only cable attach interrupt are fired and Link Down interrupt
+ * are fired only in special case like AN restart.
+ */
+}
+
+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return airoha_pcs_interrupt_init_sgmii(priv, index);
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ return airoha_pcs_interrupt_init_usxgmii(priv, index);
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
+ unsigned int neg_mode, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr = 0, lpa = 0;
+
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
+ &lpa);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+ lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
+ phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_hsgmii(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr = 0;
+
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+
+ state->link = !!(bmsr & BMSR_LSTATUS);
+ state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
+ state->speed = SPEED_2500;
+ state->duplex = DUPLEX_FULL;
+}
+
+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 an_done = 0, lpa = 0;
+
+ /* Trigger HW workaround if needed. If an error is reported,
+ * consider link down and test again later.
+ */
+ if (data->rxlock_workaround && data->rxlock_workaround(priv, index)) {
+ state->link = false;
+ return;
+ }
+
+ /* Toggle AN Status */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_2, &an_done);
+
+ state->link = !!(lpa & MDIO_USXGMII_LINK);
+ state->an_complete = !!(an_done & AIROHA_PCS_USXGMII_PCS_AN_COMPLETE);
+
+ phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void airoha_pcs_get_state_10gbaser(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 status = 0, curr_mode = 0;
+
+ /* Toggle AN Status */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1,
+ &status);
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &curr_mode);
+
+ state->link = !!(status & AIROHA_PCS_USXGMII_RX_LINK_STUS);
+
+ switch (curr_mode & AIROHA_PCS_USXGMII_CUR_USXGMII_MODE) {
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G:
+ state->speed = SPEED_10000;
+ break;
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G:
+ state->speed = SPEED_5000;
+ break;
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G:
+ state->speed = SPEED_2500;
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ return;
+ }
+
+ state->duplex = DUPLEX_FULL;
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
+ unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_get_state_sgmii(priv, neg_mode, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_get_state_hsgmii(priv, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ airoha_pcs_get_state_usxgmii(priv, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_get_state_10gbaser(priv, port->index, state);
+ break;
+ default:
+ return;
+ }
+}
+
+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ const struct airoha_pcs_match_data *data;
+ struct airoha_pcs_maps *maps;
+ int index = port->index;
+ u32 rate_adapt;
+ int ret;
+
+ maps = &priv->maps[port->index];
+ port->interface = interface;
+ data = priv->data;
+
+ /* Apply Analog and Digital configuration for PCS */
+ if (data->bringup) {
+ ret = data->bringup(priv, index, interface);
+ if (ret)
+ return ret;
+ }
+
+ /* Set final configuration for various modes */
+ airoha_pcs_init(priv, index, interface);
+
+ /* Configure Interrupt for various modes */
+ airoha_pcs_interrupt_init(priv, index, interface);
+
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ rate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS;
+
+ /* AN Auto Settings (Rate Adaptation) */
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+ else
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
+ } else {
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
+ }
+ }
+
+ /* Clear any force bit that my be set by bootloader */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0 |
+ AIROHA_PCS_FORCE_LINKDOWN_P0 |
+ AIROHA_PCS_FORCE_LINKUP_P0);
+ }
+
+ /* Toggle Rate Adaption for SGMII/HSGMII mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_clear_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ else
+ regmap_set_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ }
+
+ /* Setup AN Link Timer */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 an_timer;
+
+ an_timer = phylink_get_link_timer_ns(interface);
+
+ /* Value needs to be shifted by 4, seems value is internally * 16 */
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ an_timer >> 4));
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
+ AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ an_timer >> 4));
+ }
+
+ /* Setup SGMII AN and advertisement in DEV_ABILITY */
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+ advertising);
+ if (advertise < 0)
+ return advertise;
+
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
+ AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ advertise));
+
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ } else {
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ }
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
+
+ /* Toggle SGMII or 1000base-x mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN;
+
+ if (neg_mode & PHYLINK_PCS_NEG_INBAND)
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+ else
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* Clear force speed bits and MAC mode */
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ } else {
+ /* Enable compatibility with MAC PCS Layer */
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
+
+ /* AN off force rate adaption, speed is set later in Link Up */
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ }
+
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
+ AIROHA_PCS_HSGMII_PCS_MODE2_EN);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_1000BASEX &&
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
+
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
+ AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY);
+ }
+
+ /* Configure Flow Control on XFI */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
+ permit_pause_to_mac ?
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
+ 0);
+
+ return 0;
+}
+
+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ switch (port->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface, int speed, int duplex)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ const struct airoha_pcs_match_data *data;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+ data = priv->data;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
+ udelay(1);
+ regmap_update_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
+ }
+ } else {
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ u32 mode;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_10000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
+ mode = AIROHA_PCS_USXGMII_MODE_10000;
+ break;
+ case SPEED_5000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
+ mode = AIROHA_PCS_USXGMII_MODE_5000;
+ break;
+ case SPEED_2500:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
+ mode = AIROHA_PCS_USXGMII_MODE_2500;
+ break;
+ case SPEED_1000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
+ mode = AIROHA_PCS_USXGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
+ mode = AIROHA_PCS_USXGMII_MODE_100;
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ /* Force USXGMII to selected speed */
+ regmap_update_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_MODE, mode);
+
+ if (interface == PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 force_speed;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_1000:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
+ break;
+ case SPEED_100:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
+ break;
+ case SPEED_10:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
+ force_speed | rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ u32 ck_gen_mode;
+ u32 speed_reg;
+ u32 if_mode;
+
+ switch (speed) {
+ case SPEED_2500:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
+ break;
+ case SPEED_1000:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
+ break;
+ case SPEED_10:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_10M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
+ break;
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
+ if_mode);
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
+ ck_gen_mode |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
+ }
+
+ regmap_update_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0,
+ speed_reg |
+ AIROHA_PCS_FORCE_SPD_MODE_P0);
+ }
+ }
+
+ if (data->link_up)
+ data->link_up(priv, port->index);
+
+ /* BPI BMI enable */
+ regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_link_down(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* MPI MBI disable */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* Select HSGMII or USXGMII in SCU regs */
+ airoha_pcs_setup_scu(priv, port->index, interface);
+
+ /* MPI MBI disable */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+
+ /* Write 1 to trigger reset and clear */
+ regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+ AIROHA_PCS_XFI_MAC_LOGIC_RST);
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+ AIROHA_PCS_XFI_MAC_LOGIC_RST);
+
+ usleep_range(1000, 2000);
+
+ /* Clear XFI MAC counter */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,
+ AIROHA_PCS_XFI_GLB_CNT_CLR);
+}
+
+static int airoha_pcs_post_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* Frag disable */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RX_FRAG_LEN,
+ FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31));
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FRAG_LEN,
+ FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31));
+
+ /* IPG NUM */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_IPG_NUM,
+ FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10));
+
+ return 0;
+}
+
+static unsigned int airoha_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
+}
+
+static const struct phylink_pcs_ops airoha_pcs_ops = {
+ .pcs_inband_caps = airoha_pcs_inband_caps,
+ .pcs_pre_config = airoha_pcs_pre_config,
+ .pcs_post_config = airoha_pcs_post_config,
+ .pcs_get_state = airoha_pcs_get_state,
+ .pcs_config = airoha_pcs_config,
+ .pcs_an_restart = airoha_pcs_an_restart,
+ .pcs_link_up = airoha_pcs_link_up,
+ .pcs_link_down = airoha_pcs_link_down,
+};
+
+static int airoha_pcs_init_named_regmap(struct platform_device *pdev,
+ const char *name, struct regmap **regmap)
+{
+ struct regmap_config config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ };
+ void __iomem *base;
+
+ base = devm_platform_ioremap_resource_byname(pdev, name);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ config.name = name;
+ *regmap = devm_regmap_init_mmio(&pdev->dev, base, &config);
+
+ return PTR_ERR_OR_ZERO(*regmap);
+}
+
+static int airoha_pcs_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[0];
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii", &maps->usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static int airoha_pcs_usb_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[0];
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sgmii);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = priv->maps;
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac0", &maps[0].pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an0", &maps[0].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs0", &maps[0].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp0", &maps[0].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii0", &maps[0].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii0", &maps[0].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac1", &maps[1].pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an1", &maps[1].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs1", &maps[1].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp1", &maps[1].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii1", &maps[1].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii1", &maps[1].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma0", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma1", &priv->pcs_pma[1]);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static struct phylink_pcs *airoha_pcs_xlate(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ struct airoha_pcs_priv *priv = data;
+ struct device *dev = priv->dev;
+ u64 index = 0;
+
+ switch (priv->data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ case AIROHA_PCS_USB:
+ if (pcsspec->nargs) {
+ dev_err(dev, "invalid number of cells in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ break;
+ case AIROHA_PCS_PCIE:
+ if (pcsspec->nargs != 1) {
+ dev_err(dev, "invalid number of cells in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ break;
+ }
+
+ if (pcsspec->nargs)
+ index = pcsspec->args[0];
+
+ if (index >= priv->data->num_port) {
+ dev_err(dev, "invalid index cell in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &priv->ports[index].pcs;
+}
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+ const struct airoha_pcs_match_data *data;
+ struct fwnode_pcs_provider *pcs_provider;
+ struct device *dev = &pdev->dev;
+ struct airoha_pcs_priv *priv;
+ int index, ret;
+
+ data = of_device_get_match_data(dev);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->ports = devm_kcalloc(dev, data->num_port,
+ sizeof(*priv->ports), GFP_KERNEL);
+ if (!priv->ports)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->data = data;
+
+ if (data->port_type == AIROHA_PCS_USB) {
+ struct phy *phy;
+
+ phy = devm_phy_get(dev, NULL);
+ if (IS_ERR(phy))
+ return dev_err_probe(dev, PTR_ERR(phy), "failed to get phy\n");
+
+ priv->phy = phy;
+ }
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ ret = airoha_pcs_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ case AIROHA_PCS_PCIE:
+ ret = airoha_pcs_pcie_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ case AIROHA_PCS_USB:
+ ret = airoha_pcs_usb_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ }
+
+ if (data->alloc_regmap_fields) {
+ ret = data->alloc_regmap_fields(priv);
+ if (ret)
+ return ret;
+ }
+
+ /* SCU is used to toggle XFI or HSGMII in global SoC registers */
+ if (!priv->phy) {
+ priv->scu = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu");
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+ }
+
+ priv->rsts[0].id = "mac";
+ priv->rsts[1].id = "phy";
+ ret = devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
+ /* For Ethernet PCS, read the AN7581 SoC revision to check if
+ * manual rx calibration is needed. This is only limited to
+ * any SoC revision before E2.
+ */
+ if (device_is_compatible(dev, "airoha,an7581-pcs-eth")) {
+ u32 val;
+
+ ret = regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val);
+ if (ret)
+ return ret;
+
+ if (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) < 0x2)
+ priv->manual_rx_calib = true;
+ }
+
+ for (index = 0; index < data->num_port; index++) {
+ struct airoha_pcs_port *port = &priv->ports[index];
+
+ port->priv = priv;
+ port->index = index;
+ port->pcs.poll = true;
+ port->pcs.ops = &airoha_pcs_ops;
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ case AIROHA_PCS_PCIE:
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ port->pcs.supported_interfaces);
+ fallthrough;
+ case AIROHA_PCS_USB:
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ port->pcs.supported_interfaces);
+ break;
+ }
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ pcs_provider = devm_fwnode_pcs_add_provider(dev, dev_fwnode(dev),
+ airoha_pcs_xlate, priv);
+ if (IS_ERR(pcs_provider))
+ return PTR_ERR(pcs_provider);
+
+ return 0;
+}
+
+static const struct airoha_pcs_match_data an7581_pcs_eth = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_ETH,
+ .alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+ .rxlock_workaround = an7581_pcs_rxlock_workaround,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pon = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_PON,
+ .alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pcie = {
+ .num_port = 2,
+ .port_type = AIROHA_PCS_PCIE,
+ .alloc_regmap_fields = an7581_pcs_pcie_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_usb = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_USB,
+ .bringup = an7581_pcs_usb_bringup,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+ { .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+ { .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+ { .compatible = "airoha,an7581-pcs-pcie", .data = &an7581_pcs_pcie },
+ { .compatible = "airoha,an7581-pcs-usb", .data = &an7581_pcs_usb },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
+
+static struct platform_driver airoha_pcs_driver = {
+ .driver = {
+ .name = "airoha-pcs",
+ .of_match_table = airoha_pcs_of_table,
+ },
+ .probe = airoha_pcs_probe,
+};
+module_platform_driver(airoha_pcs_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Airoha PCS driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
diff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h
new file mode 100644
index 0000000000000..8a76d51b5d2c8
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha.h
@@ -0,0 +1,1311 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* SCU*/
+#define AIROHA_SCU_PDIDR 0x5c
+#define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0)
+#define AIROHA_SCU_WAN_CONF 0x70
+#define AIROHA_SCU_WAN_SEL GENMASK(7, 0)
+#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
+#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
+#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
+#define AIROHA_SCU_SSR3 0x94
+#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13)
+#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
+#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
+#define AIROHA_SCU_SSTR 0x9c
+#define AIROHA_SCU_PCIE_XSI0_SEL GENMASK(14, 13)
+#define AIROHA_SCU_PCIE_XSI0_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x1)
+#define AIROHA_SCU_PCIE_XSI0_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x2)
+#define AIROHA_SCU_PCIE_XSI1_SEL GENMASK(12, 11)
+#define AIROHA_SCU_PCIE_XSI1_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x1)
+#define AIROHA_SCU_PCIE_XSI1_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x2)
+#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9)
+#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
+#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
+
+/* XFI_MAC */
+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0
+#define AIROHA_PCS_XFI_RX_FRAG_LEN GENMASK(26, 22)
+#define AIROHA_PCS_XFI_TX_FRAG_LEN GENMASK(21, 17)
+#define AIROHA_PCS_XFI_IPG_NUM GENMASK(15, 10)
+#define AIROHA_PCS_XFI_TX_FC_EN BIT(5)
+#define AIROHA_PCS_XFI_RX_FC_EN BIT(4)
+#define AIROHA_PCS_XFI_RXMPI_STOP BIT(3)
+#define AIROHA_PCS_XFI_RXMBI_STOP BIT(2)
+#define AIROHA_PCS_XFI_TXMPI_STOP BIT(1)
+#define AIROHA_PCS_XFI_TXMBI_STOP BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST 0x10
+#define AIROHA_PCS_XFI_MAC_LOGIC_RST BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH 0x60
+#define AIROHA_PCS_XFI_MAC_MACADDRH GENMASK(15, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL 0x64
+#define AIROHA_PCS_XFI_MAC_MACADDRL GENMASK(31, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR 0x100
+#define AIROHA_PCS_XFI_GLB_CNT_CLR BIT(0)
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0
+#define AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY BIT(15)
+#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */
+#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10
+#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */
+#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
+#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1)
+#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
+#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0)
+
+/* HSGMII_PCS */
+#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_TBI_10B_MODE BIT(30)
+#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24)
+#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8
+#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8)
+#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
+#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104
+#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5)
+#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c
+#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0)
+
+/* HSGMII_ANA */
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6 0x18
+#define AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC BIT(20)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8 0x20
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR GENMASK(11, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 GENMASK(7, 4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0 GENMASK(3, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11 0x2c
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_MODE GENMASK(1, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18 0x48
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV GENMASK(28, 27)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19 0x4c
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV GENMASK(15, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_LV GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG GENMASK(2, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_GND FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONFBK_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONREF_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x3)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_CKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_FBCKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x5)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_TX2500M_A FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_CDR_250M_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x7)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24 0x60
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE GENMASK(31, 24)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26 0x68
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY GENMASK(7, 6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x3)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14
+#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
+#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4)
+#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
+#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
+#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
+#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
+#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2)
+#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1)
+#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28)
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c
+#define AIROHA_PCS_HSGMII_PCS_INT BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c
+#define AIROHA_PCS_LINK_STS_P0 BIT(3)
+#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0)
+#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
+#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
+#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448
+#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2)
+#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1)
+#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0)
+
+/* HSGMII_RATE_ADP */
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31)
+
+/* USXGMII */
+#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13)
+#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x4
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP \
+ FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x1)
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_DOWN \
+ FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x0)
+#define AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1 0x30
+#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12)
+#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
+#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0)
+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c
+#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0
+#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4
+#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8
+#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8)
+#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
+#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318
+#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c
+#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320
+#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12)
+#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8)
+#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)
+
+/* PMA_PHYA */
+#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0
+#define AIROHA_PCS_ANA_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 0x1
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 0x2
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 0x3
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 0x4
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 0x5
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 0x6
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 0x1
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 0x2
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 0x3
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 0x4
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17)
+#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
+#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8)
+#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38
+#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16)
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48
+#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO BIT(5)
+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50
+#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54
+#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64
+#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 0x0
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 0x1
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 0x2
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68
+#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 0x2
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 0x4
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74
+#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c
+#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84
+#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94
+#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4
+#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4
+#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8
+#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
+#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8
+#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4
+#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8
+#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
+#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c
+#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24)
+#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19)
+#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2)
+#define AIROHA_PCS_ANA_CDR_PR_MONPI_EN BIT(1)
+#define AIROHA_PCS_ANA_CDR_PR_MONPR_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110
+#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114
+#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8)
+#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c
+#define AIROHA_PCS_ANA_RX_FE_VCM_GEN_PWDB BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c
+#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
+#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148
+#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYA 2L */
+#define AIROHA_PCS_ANA_PXP_2L_CMN_EN 0x0
+#define AIROHA_PCS_ANA_2L_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_2L_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_20_25 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_40_50 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_80_100 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_150_200 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_300_400 0x5
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_600_800 0x6
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_4 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_6 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_8 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_10 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN 0x38
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1 0x3c
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD 0x40
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN 0x4c
+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L GENMASK(31, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF 0x50
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN 0x54
+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IBIAS GENMASK(29, 24)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST 0x58
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BP GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IOFST GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR 0x5c
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_CODE GENMASK(31, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_OPTION BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV 0x60
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KF GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KFC GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_DIV GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN 0x64
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_POSTDIV_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN 0x68
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_INTERNAL BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV 0x6c
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_PLL_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_RST_DLY GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_1 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_2 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_3 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_4 0x3
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS 0x70
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_IFM BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT 0x74
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2_5 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_3 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_4 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_6 0x4
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_HREN BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_OUT BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF 0x78
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW 0x7c
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_HALFLSB_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_CFIX GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW GENMASK(2, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR 0x80
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_TCLVAR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_SCAPWR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN 0x84
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1 0x88
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD 0x8c
+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF 0x9c
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN 0xcc
+#define AIROHA_PCS_ANA_2L_TX0_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TX0_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN 0xe8
+#define AIROHA_PCS_ANA_2L_TX1_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TX1_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL 0xf4
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_2L_RX0_REV_0 0xfc
+#define AIROHA_PCS_ANA_2L_RX0_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV 0x100
+#define AIROHA_PCS_ANA_2L_RX0_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV 0x104
+#define AIROHA_PCS_ANA_2L_CDR0_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO 0x110
+#define AIROHA_PCS_ANA_2L_CDR0_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE 0x11c
+#define AIROHA_PCS_ANA_2L_CDR0_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC 0x120
+#define AIROHA_PCS_ANA_2L_CDR0_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL 0x124
+#define AIROHA_PCS_ANA_2L_CDR0_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN 0x130
+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPR_EN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN 0x134
+#define AIROHA_PCS_ANA_2L_CDR0_PR_XFICK_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR 0x138
+#define AIROHA_PCS_ANA_2L_CDR0_PR_CAP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BUF_IN_SR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON 0x13c
+#define AIROHA_PCS_ANA_2L_RX0_DAC_MON GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN 0x140
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_PEAK GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_LPF_CTRL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL 0x144
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ1_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_FE_EQ_HZEN BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_VTH_SEL GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN 0x148
+#define AIROHA_PCS_ANA_2L_RX0_FE_VCM_GEN_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ3_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ2_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE 0x150
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE 0x170
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ 0x17c
+#define AIROHA_PCS_ANA_2L_RX0_DAC_E1_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_E0_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_D1_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_D0_BYPASS_AEQ BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ 0x180
+#define AIROHA_PCS_ANA_2L_RX0_DAC_EYE_BYPASS_AEQ BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB 0x234
+#define AIROHA_PCS_ANA_2L_RX1_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL 0x1ac
+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_2L_RX1_REV_0 0x1b4
+#define AIROHA_PCS_ANA_2L_RX1_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV 0x1b8
+#define AIROHA_PCS_ANA_2L_RX1_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV 0x1bc
+#define AIROHA_PCS_ANA_2L_CDR1_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO 0x1c8
+#define AIROHA_PCS_ANA_2L_CDR1_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE 0x1d4
+#define AIROHA_PCS_ANA_2L_CDR1_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC 0x1d8
+#define AIROHA_PCS_ANA_2L_CDR1_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL 0x1dc
+#define AIROHA_PCS_ANA_2L_CDR1_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN 0x1e8
+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPR_EN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN 0x1ec
+#define AIROHA_PCS_ANA_2L_CDR1_PR_XFICK_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR 0x1f0
+#define AIROHA_PCS_ANA_2L_RX1_DAC_MON GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_CAP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BUF_IN_SR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE 0x1f4
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH 0x1f8
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL 0x1fc
+#define AIROHA_PCS_ANA_2L_RX1_FE_EQ_HZEN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN 0x200
+#define AIROHA_PCS_ANA_2L_RX1_FE_VCM_GEN_PWDB BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ3_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ2_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ1_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW 0x208
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE GENMASK(25, 16)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE 0x228
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE GENMASK(27, 16)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ 0x238
+#define AIROHA_PCS_ANA_2L_RX1_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYD */
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0
+#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4
+#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88
+#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8)
+#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c
+#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90
+#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94
+#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98
+#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c
+#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100
+#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104
+#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
+#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
+#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120
+#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8)
+#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c
+#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150
+#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158
+#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12)
+#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c
+#define AIROHA_PCS_PMA_SIGDET_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_1 0x174
+#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_2 0x178
+#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16)
+#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
+#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
+#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_RX_FLL_5 0x184
+#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16)
+#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_B 0x19c
+#define AIROHA_PCS_PMA_LOAD_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_1 0x208
+#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_RST_B 0x260
+#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320
+#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330
+#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c
+#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c
+#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24)
+#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16)
+#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8)
+#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350
+#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360
+#define AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN GENMASK(17, 16)
+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374
+#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2 0x380
+#define AIROHA_PCS_RX_SIGDET BIT(8)
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390
+#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c
+#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414
+#define AIROHA_PCS_PMA_XFI_RX_MODE GENMASK(11, 9)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x0)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x1)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x2)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x3)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x4)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x5)
+#define AIROHA_PCS_PMA_R2T_MODE BIT(8)
+#define AIROHA_PCS_PMA_XFI_TX_MODE GENMASK(5, 3)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x0)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x1)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x2)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x3)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x4)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x5)
+#define AIROHA_PCS_PMA_SW_RST_SET 0x460
+#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11)
+#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8)
+#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7)
+#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6)
+#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5)
+#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4)
+#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3)
+#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2)
+#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1)
+#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0)
+#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474
+#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16)
+#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c
+#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
+#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
+#define AIROHA_PCS_PMA_RX_FREQDET 0x530
+#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580
+#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)
+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_29 0x910
+#define AIROHA_PCS_PMA_2L_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_2L_RX_RATE_CTRL GENMASK(5, 4)
+
+#define AIROHA_PCS_MAX_CALIBRATION_TRY 50
+#define AIROHA_PCS_MAX_RX_SIGDET_TRY 6
+#define AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT 4
+#define AIROHA_PCS_MAX_NUM_RSTS 2
+
+enum xfi_port_type {
+ AIROHA_PCS_ETH,
+ AIROHA_PCS_PON,
+ AIROHA_PCS_USB,
+ AIROHA_PCS_PCIE,
+};
+
+struct airoha_pcs_maps {
+ struct regmap *pcs_mac;
+ struct regmap *hsgmii_an;
+ struct regmap *hsgmii_pcs;
+ struct regmap *hsgmii_rate_adp;
+ struct regmap *multi_sgmii;
+ struct regmap *usxgmii_pcs;
+};
+
+struct airoha_pcs_priv {
+ struct device *dev;
+ const struct airoha_pcs_match_data *data;
+
+ struct airoha_pcs_port *ports;
+
+ struct regmap *scu;
+
+ struct airoha_pcs_maps maps[2];
+
+ struct regmap *pcs_pma[2];
+ struct regmap *pcs_ana;
+ struct regmap_field **pcs_ana_fields[2];
+
+ struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
+
+ struct phy *phy;
+
+ bool manual_rx_calib;
+};
+
+struct airoha_pcs_port {
+ struct airoha_pcs_priv *priv;
+ phy_interface_t interface;
+ int index;
+
+ struct phylink_pcs pcs;
+};
+
+struct airoha_pcs_match_data {
+ int num_port;
+ enum xfi_port_type port_type;
+
+ int (*alloc_regmap_fields)(struct airoha_pcs_priv *priv);
+ int (*bringup)(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+ void (*link_up)(struct airoha_pcs_priv *priv, int index);
+ int (*rxlock_workaround)(struct airoha_pcs_priv *priv, int index);
+};
+
+#define to_airoha_pcs_port(n) container_of(n, struct airoha_pcs_port, pcs)
+
+#if IS_ENABLED(CONFIG_PCS_AIROHA_AN7581)
+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv);
+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv);
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index);
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index);
+#else
+static inline int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv,
+ int index)
+{
+}
+
+static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv,
+ int index)
+{
+ return 0;
+}
+#endif
diff --git a/drivers/net/pcs/airoha/pcs-an7581.c b/drivers/net/pcs/airoha/pcs-an7581.c
new file mode 100644
index 0000000000000..95e155a7fa621
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-an7581.c
@@ -0,0 +1,2100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/math.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/regmap.h>
+
+#include "pcs-airoha.h"
+
+#include <linux/of.h>
+
+enum {
+ AN7581_PCS_CMN_EN,
+
+ AN7581_PCS_JCPLL_SPARE_L,
+ AN7581_PCS_JCPLL_RST_DLY,
+ AN7581_PCS_JCPLL_PLL_RSTB,
+ AN7581_PCS_JCPLL_SDM_DI_EN,
+ AN7581_PCS_JCPLL_SDM_DI_LS,
+
+ AN7581_PCS_JCPLL_SDM_OUT,
+ AN7581_PCS_JCPLL_SDM_ORD,
+ AN7581_PCS_JCPLL_SDM_MODE,
+ AN7581_PCS_JCPLL_SDM_IFM,
+ AN7581_PCS_JCPLL_SDM_HREN,
+
+ AN7581_PCS_JCPLL_CHP_IOFST,
+ AN7581_PCS_JCPLL_CHP_IBIAS,
+ AN7581_PCS_JCPLL_LPF_SHCK_EN,
+
+ AN7581_PCS_JCPLL_LPF_BWR,
+ AN7581_PCS_JCPLL_LPF_BP,
+ AN7581_PCS_JCPLL_LPF_BC,
+ AN7581_PCS_JCPLL_LPF_BR,
+ AN7581_PCS_JCPLL_LPF_BWC,
+
+ AN7581_PCS_JCPLL_VCO_SCAPWR,
+ AN7581_PCS_JCPLL_VCO_HALFLSB_EN,
+ AN7581_PCS_JCPLL_VCO_CFIX,
+ AN7581_PCS_JCPLL_VCODIV,
+ AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L,
+ AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H,
+ AN7581_PCS_JCPLL_VCO_TCLVAR,
+
+ AN7581_PCS_JCPLL_POSTDIV_D5,
+ AN7581_PCS_JCPLL_MMD_PREDIV_MODE,
+
+ AN7581_PCS_JCPLL_KBAND_KS,
+ AN7581_PCS_JCPLL_KBAND_KF,
+ AN7581_PCS_JCPLL_KBAND_KFC,
+ AN7581_PCS_JCPLL_KBAND_DIV,
+ AN7581_PCS_JCPLL_KBAND_CODE,
+ AN7581_PCS_JCPLL_KBAND_OPTION,
+
+ AN7581_PCS_JCPLL_TCL_AMP_VREF,
+ AN7581_PCS_JCPLL_TCL_AMP_GAIN,
+ AN7581_PCS_JCPLL_TCL_AMP_EN,
+
+ AN7581_PCS_JCPLL_TCL_LPF_BW,
+ AN7581_PCS_JCPLL_TCL_LPF_EN,
+
+ AN7581_PCS_JCPLL_SSC_DELTA,
+ AN7581_PCS_JCPLL_SSC_DELTA1,
+ AN7581_PCS_JCPLL_SSC_PERIOD,
+ AN7581_PCS_JCPLL_SSC_TRI_EN,
+ AN7581_PCS_JCPLL_SSC_EN,
+ AN7581_PCS_JCPLL_SSC_PHASE_INI,
+ AN7581_PCS_JCPLL_TCL_KBAND_VREF,
+
+ AN7581_PCS_TXPLL_LDO_VCO_OUT,
+ AN7581_PCS_TXPLL_LDO_OUT,
+ AN7581_PCS_TXPLL_PLL_RSTB,
+ AN7581_PCS_TXPLL_RST_DLY,
+ AN7581_PCS_TXPLL_REFIN_DIV,
+ AN7581_PCS_TXPLL_REFIN_INTERNAL,
+ AN7581_PCS_TXPLL_SDM_MODE,
+ AN7581_PCS_TXPLL_SDM_IFM,
+ AN7581_PCS_TXPLL_SDM_DI_LS,
+ AN7581_PCS_TXPLL_SDM_DI_EN,
+ AN7581_PCS_TXPLL_SDM_HREN,
+ AN7581_PCS_TXPLL_SDM_ORD,
+ AN7581_PCS_TXPLL_SDM_OUT,
+ AN7581_PCS_TXPLL_SSC_DELTA1,
+ AN7581_PCS_TXPLL_SSC_DELTA,
+ AN7581_PCS_TXPLL_SSC_TRI_EN,
+ AN7581_PCS_TXPLL_SSC_PHASE_INI,
+ AN7581_PCS_TXPLL_SSC_EN,
+ AN7581_PCS_TXPLL_SSC_PERIOD,
+ AN7581_PCS_TXPLL_LPF_BC,
+ AN7581_PCS_TXPLL_LPF_BR,
+ AN7581_PCS_TXPLL_LPF_BP,
+ AN7581_PCS_TXPLL_LPF_BWC,
+ AN7581_PCS_TXPLL_LPF_BWR,
+ AN7581_PCS_TXPLL_CHP_IOFST,
+ AN7581_PCS_TXPLL_CHP_IBIAS,
+ AN7581_PCS_TXPLL_VCO_CFIX,
+ AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L,
+ AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H,
+ AN7581_PCS_TXPLL_VCO_TCLVAR,
+ AN7581_PCS_TXPLL_VCO_SCAPWR,
+ AN7581_PCS_TXPLL_VCO_HALFLSB_EN,
+ AN7581_PCS_TXPLL_KBAND_CODE,
+ AN7581_PCS_TXPLL_KBAND_OPTION,
+ AN7581_PCS_TXPLL_KBAND_KS,
+ AN7581_PCS_TXPLL_KBAND_KF,
+ AN7581_PCS_TXPLL_KBAND_KFC,
+ AN7581_PCS_TXPLL_KBAND_DIV,
+ AN7581_PCS_TXPLL_MMD_PREDIV_MODE,
+ AN7581_PCS_TXPLL_POSTDIV_EN,
+ AN7581_PCS_TXPLL_VCODIV,
+ AN7581_PCS_TXPLL_TCL_KBAND_VREF,
+ AN7581_PCS_TXPLL_TCL_AMP_GAIN,
+ AN7581_PCS_TXPLL_TCL_AMP_VREF,
+ AN7581_PCS_TXPLL_TCL_LPF_BW,
+ AN7581_PCS_TXPLL_TCL_LPF_EN,
+ AN7581_PCS_TXPLL_TCL_AMP_EN,
+
+ AN7581_PCS_TX_DMEDGEGEN_EN,
+ AN7581_PCS_TX_CKLDO_EN,
+
+ AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_E1_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_E0_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_D1_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_D0_BYPASS_AEQ,
+ AN7581_PCS_RX_FE_VCM_GEN_PWDB,
+ AN7581_PCS_RX_OSCAL_FORCE,
+ AN7581_PCS_RX_DAC_MON,
+ AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL,
+ AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL,
+ AN7581_PCS_RX_REV_1_SIGDET_ILEAK,
+ AN7581_PCS_RX_FE_VB_EQ3_EN,
+ AN7581_PCS_RX_FE_VB_EQ2_EN,
+ AN7581_PCS_RX_FE_VB_EQ1_EN,
+ AN7581_PCS_RX_FE_EQ_HZEN,
+ AN7581_PCS_RX_SIGDET_VTH_SEL,
+ AN7581_PCS_RX_SIGDET_PEAK,
+ AN7581_PCS_RX_SIGDET_LPF_CTRL,
+ AN7581_PCS_RX_TDC_CK_SEL,
+ AN7581_PCS_RX_PHYCK_RSTB,
+ AN7581_PCS_RX_PHYCK_SEL,
+ AN7581_PCS_RX_PHYCK_DIV,
+ AN7581_PCS_RX_PHY_CK_SEL_FORCE,
+ AN7581_PCS_RX_PHY_CK_SEL,
+
+ AN7581_PCS_AEQ_OFORCE,
+
+ AN7581_PCS_CDR_PD_EDGE_DIS,
+ AN7581_PCS_CDR_PD_PICAL_CKD8_INV,
+
+ AN7581_PCS_CDR_PR_XFICK_EN,
+ AN7581_PCS_CDR_PR_MONPI_EN,
+ AN7581_PCS_CDR_PR_MONPR_EN,
+ AN7581_PCS_CDR_PR_KBAND_DIV,
+ AN7581_PCS_CDR_PR_BETA_SEL,
+ AN7581_PCS_CDR_PR_VCOADC_OS,
+ AN7581_PCS_CDR_PR_BETA_DAC,
+ AN7581_PCS_CDR_PR_FBKSEL,
+ AN7581_PCS_CDR_PR_DAC_BAND,
+ AN7581_PCS_CDR_PR_VREG_CKBUF_VAL,
+ AN7581_PCS_CDR_PR_VREG_IBAND_VAL,
+ AN7581_PCS_CDR_PR_CAP_EN,
+ AN7581_PCS_CDR_PR_INJ_FORCE_OFF,
+
+ AN7581_PCS_CDR_BUF_IN_SR,
+
+ AN7581_PCS_CDR_LPF_TOP_LIM,
+ AN7581_PCS_CDR_LPF_RATIO,
+
+ AN7581_PCS_FIELDS_MAX,
+};
+
+static const struct reg_field an7581_pcs_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 8, 15),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 8, 23),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 0, 0),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 17, 17),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 16, 16),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 16, 20),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 3, 5),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 24, 24),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 16, 18),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 8, 9),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 24, 25),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 8, 9),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 16, 16),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 0, 1),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 24, 28),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 16, 20),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 8, 13),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 0, 5),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 0, 4),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 24, 25),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 27, 29),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 0, 0),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 0, 7),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 0, 1),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 8, 10),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 16, 17),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 8, 8),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 16, 17),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 8, 12),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 8, 10),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 24, 24),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB, 24, 24),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB, 0, 0),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_AEQ_CFORCE, 8, 19),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW, 8, 17),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 24, 28),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 2, 2),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 1, 1),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 0, 0),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 24, 24),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 16, 16),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 8, 8),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 0, 0),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 19, 19),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 16, 18),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 16, 20),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 8, 9),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_RANGE, 24, 25),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, 24, 24),
+};
+
+static const struct reg_field an7581_pcs_pcie0_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 16, 16),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 16, 16),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE, 8, 19),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE, 8, 17),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON, 0, 4),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 8, 8),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 0, 0),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN, 24, 24),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 8, 8),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 0, 0),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 24, 24),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 8, 8),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 0, 2),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 0, 4),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 24, 25),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 8, 9),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE, 24, 24),
+};
+
+static const struct reg_field an7581_pcs_pcie1_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 16, 16),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB, 24, 24),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 24, 24),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE, 16, 27),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW, 16, 25),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 16, 20),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 8, 8),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 0, 0),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN, 24, 24),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 16, 16),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 8, 8),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 0, 0),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL, 24, 24),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 8, 8),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 0, 2),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 16, 20),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 8, 9),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE, 24, 25),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE, 24, 24),
+};
+
+static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma;
+ u32 kband_vref;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ kband_vref = 0x10;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ kband_vref = 0xf;
+ break;
+ default:
+ return;
+ }
+
+ /* This comment only apply to Serdes PCIe that expose
+ * 2 PCS.
+ *
+ * The Serdes PCIe expose 2 PCS but always require
+ * the PMA for the first PCS to be configured
+ * for correct functionality for JCPLL.
+ */
+ pcs_pma = priv->pcs_pma[0];
+
+ /* Setup LDO */
+ usleep_range(200, 300);
+
+ regmap_field_set_bits(pcs_ana_fields[AN7581_PCS_JCPLL_SPARE_L],
+ AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
+
+ /* Setup RSTB */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_RST_DLY],
+ AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_PLL_RSTB], 0x1);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
+
+ /* Setup SDM */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_LS],
+ AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_EN], 0x0);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_OUT], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_ORD],
+ AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_MODE], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_IFM], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_HREN], 0x0);
+
+ /* Setup SSC */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA1], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PERIOD], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_TRI_EN], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_EN], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PHASE_INI], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0);
+
+ /* Setup LPF */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IOFST], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IBIAS], 0x18);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_SHCK_EN], 0);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWR], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BP], 0x10);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BC], 0x1f);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BR], BIT(3) | BIT(1));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWC], 0x0);
+
+ /* Setup VCO */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_SCAPWR], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_HALFLSB_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_CFIX], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x3);
+
+ /* Setup PCW */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
+
+ /* Setup DIV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_POSTDIV_D5], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_MMD_PREDIV_MODE],
+ AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCODIV],
+ AIROHA_PCS_ANA_JCPLL_VCODIV_1);
+
+ /* Setup KBand */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KS], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KF], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KFC], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_DIV], 0x2);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_CODE], 0xe4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_OPTION], 0x0);
+
+ /* Setup TCL */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_KBAND_VREF],
+ kband_vref);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_VREF], 0x5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_GAIN],
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_EN], 0x1);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_BW],
+ AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_EN], 0x1);
+
+ /* Enable PLL */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
+}
+
+static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
+ struct regmap *pcs_pma;
+ u32 tcl_amp_vref;
+ bool sdm_hren;
+ u32 vco_cfix;
+ bool vcodiv;
+ u32 pcw;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(1) | BIT(0);
+ pcw = BIT(27);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ lpf_chp_ibias = 0xa;
+ lpf_bp = BIT(2) | BIT(0);
+ lpf_bwr = 0;
+ lpf_bwc = 0;
+ vco_cfix = 0;
+ pcw = BIT(27) | BIT(25);
+ tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
+ vcodiv = true;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(0);
+ pcw = BIT(27) | BIT(22);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = true;
+ break;
+ default:
+ return;
+ }
+
+ /* This comment only apply to Serdes PCIe that expose
+ * 2 PCS.
+ *
+ * The Serdes PCIe expose 2 PCS but always require
+ * the PMA for the first PCS to be configured
+ * for correct functionality for TXPLL.
+ */
+ pcs_pma = priv->pcs_pma[0];
+
+ /* Setup VCO LDO Output */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_VCO_OUT], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_OUT], 0x1);
+
+ /* Setup RSTB */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_PLL_RSTB], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_RST_DLY], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_DIV],
+ AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_INTERNAL], 0x1);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+ /* Setup SDM */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_MODE], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_IFM], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_LS],
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_HREN], sdm_hren);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_OUT], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_ORD],
+ AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
+
+ /* Setup SSC */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA1], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_TRI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PHASE_INI], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PERIOD], 0x0);
+
+ /* Setup LPF */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IBIAS],
+ lpf_chp_ibias);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IOFST], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BC], 0x1f);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BR], 0x5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWC], lpf_bwc);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWR], lpf_bwr);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BP], lpf_bp);
+
+ /* Setup VCO */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_CFIX], vco_cfix);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_TCLVAR], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_SCAPWR], 0x7);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_HALFLSB_EN], 0x1);
+
+ /* Setup PCW */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+ /* Setup KBand */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_CODE], 0xe4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_OPTION], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KS], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KF], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KFC], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_DIV], 0x4);
+
+ /* Setup DIV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_POSTDIV_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_MMD_PREDIV_MODE],
+ AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCODIV],
+ vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+ AIROHA_PCS_ANA_TXPLL_VCODIV_1);
+
+ /* Setup TCL */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_KBAND_VREF], 0xf);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_VREF],
+ tcl_amp_vref);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_GAIN],
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_BW],
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_EN], 0x1);
+
+ /* Enable PLL */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+}
+
+static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 fir_cn1, fir_c0b, fir_c1;
+ u32 tx_rate_ctrl;
+ u32 ckin_divisor;
+ u32 xfi_tx_mode;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ ckin_divisor = BIT(1);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 12;
+ fir_c1 = 0;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_1G25;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ ckin_divisor = BIT(2);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 11;
+ fir_c1 = 1;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_3G12;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ ckin_divisor = BIT(2) | BIT(0);
+ tx_rate_ctrl = BIT(1);
+ fir_cn1 = 1;
+ fir_c0b = 1;
+ fir_c1 = 11;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_10G3;
+ break;
+ default:
+ return;
+ }
+
+ /* Set TX rate ctrl */
+ if (priv->data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,
+ AIROHA_PCS_PMA_2L_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_2L_TX_RATE_CTRL,
+ tx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_XFI_TX_MODE,
+ xfi_tx_mode);
+ } else {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ tx_rate_ctrl));
+ }
+
+ /* Setup TX Config */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_DMEDGEGEN_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_CKLDO_EN], 0x1);
+
+ udelay(1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+ /* FIXME: Ask Airoha TX term is OK to reset? */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+ ckin_divisor));
+
+ if (priv->data->port_type != AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ tx_rate_ctrl));
+ }
+
+ /* Setup TX FIR Load Parameters (Reference 660mV) */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+ /* Reset TX Bar */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B,
+ AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
+}
+
+static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 phyck_div, phyck_sel;
+ u32 pr_cdr_beta_dac;
+ u32 cdr_pr_buf_in_sr;
+ bool cdr_pr_cap_en;
+ u32 sigdet_vth_sel;
+ u32 rx_rate_ctrl;
+ u32 xfi_rx_mode;
+ u32 osr;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ osr = BIT(1) | BIT(0); /* 1.25G */
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = false;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(5) | BIT(3) | BIT(0);
+ phyck_sel = BIT(0);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_1G25;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ osr = BIT(0); /* 2.5G */
+ pr_cdr_beta_dac = BIT(2) | BIT(1);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = true;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(3) | BIT(1) | BIT(0);
+ phyck_sel = BIT(0);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_3G12;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ osr = 0; /* 10G */
+ cdr_pr_cap_en = false;
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = BIT(1);
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(1);
+ phyck_div = BIT(6) | BIT(1);
+ phyck_sel = BIT(1);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_10G3;
+ break;
+ default:
+ return;
+ }
+
+ /* Set RX rate ctrl */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_2,
+ AIROHA_PCS_PMA_CK_RATE,
+ AIROHA_PCS_PMA_CK_RATE_10);
+
+ if (priv->data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,
+ AIROHA_PCS_PMA_2L_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_2L_RX_RATE_CTRL,
+ rx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_XFI_RX_MODE,
+ xfi_rx_mode);
+ } else {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+ AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ rx_rate_ctrl));
+ }
+
+ /* Setup RX Path */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_5,
+ AIROHA_PCS_PMA_FLL_IDAC_MIN |
+ AIROHA_PCS_PMA_FLL_IDAC_MAX,
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VCM_GEN_PWDB], 0x1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+ AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_AEQ_OFORCE],
+ AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_OSCAL_FORCE],
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+ AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+ AIROHA_PCS_PMA_DISB_LEQ);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_PICAL_CKD8_INV], 0x0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
+ AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_MON], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_XFICK_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPR_EN], 0x0);
+
+ /* Setup FE Gain and FE Peacking */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0));
+
+ /* Setup FE VOS */
+ if (interface != PHY_INTERFACE_MODE_USXGMII &&
+ interface != PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
+
+ /* Setup FLL PR FMeter (no bypass mode)*/
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
+ AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
+ AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
+
+ /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
+ /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
+ /* Setup REV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL],
+ BIT(2));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL],
+ BIT(2));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_SIGDET_ILEAK], 0x0);
+
+ /* Setup Rdy Timeout */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+ AIROHA_PCS_PMA_RX_RDY |
+ AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+ /* Setup CaBoundry Init */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+ AIROHA_PCS_PMA_RX_OS_START |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+ AIROHA_PCS_PMA_RX_OS_END,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+ AIROHA_PCS_PMA_RX_PICAL_END |
+ AIROHA_PCS_PMA_RX_PICAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+ AIROHA_PCS_PMA_RX_SDCAL_END |
+ AIROHA_PCS_PMA_RX_SDCAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+ AIROHA_PCS_PMA_RX_PDOS_END |
+ AIROHA_PCS_PMA_RX_PDOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+ AIROHA_PCS_PMA_RX_FEOS_END |
+ AIROHA_PCS_PMA_RX_FEOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+ /* Setup By Serdes*/
+ /* Setup RX OSR */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], !!osr);
+
+ /* Setup CDR LPF Ratio */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_TOP_LIM], 0x20000);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_RATIO], osr);
+
+ /* Setup CDR PR */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_KBAND_DIV], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_SEL], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VCOADC_OS], 0x8);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_DAC],
+ pr_cdr_beta_dac);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_FBKSEL], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_DAC_BAND],
+ pr_cdr_beta_dac);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL], 0x6);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_IBAND_VAL], 0x6);
+
+ /* Setup Eye Mon */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,
+ AIROHA_PCS_PMA_EQ_DEBUG_SEL |
+ AIROHA_PCS_PMA_FOM_NUM_ORDER |
+ AIROHA_PCS_PMA_A_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
+ FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+ FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+ AIROHA_PCS_PMA_DATA_SHIFT |
+ AIROHA_PCS_PMA_EYECNT_FAST,
+ AIROHA_PCS_PMA_EYECNT_FAST);
+
+ /* Calibration Start */
+
+ /* Enable SYS */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+ AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+ AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+ usleep_range(500, 600);
+
+ /* Setup FLL PR FMeter (bypass mode)*/
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+ /* Enable CMLEQ */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_EQ_HZEN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ3_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ2_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ1_EN], 0x1);
+
+ /* Setup CDR PR */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_CAP_EN],
+ cdr_pr_cap_en);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_BUF_IN_SR],
+ cdr_pr_buf_in_sr);
+
+ /* Setup CDR xxx Pwdb, set force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* FIXME: Ask Airoha WHY it's cleared? */
+ /* regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+ * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
+ */
+
+ /* Setup SigDet */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_VTH_SEL],
+ sigdet_vth_sel);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_PEAK],
+ BIT(1));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_LPF_CTRL],
+ BIT(1) | BIT(0));
+
+ /* Disable SigDet Pwdb */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+ /* Setup PHYCK */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_TDC_CK_SEL], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_RSTB], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_SEL],
+ phyck_sel);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_DIV],
+ phyck_div);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL_FORCE], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL], 0x0);
+
+ usleep_range(100, 200);
+
+ /* Enable CDR xxx Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* Enable SigDet Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+}
+
+static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
+ int index, u32 cdr_pr_idac)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 val = UINT_MAX;
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ cdr_pr_idac));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
+
+ usleep_range(5000, 7000);
+
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+
+ return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
+}
+
+static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv,
+ int index, u32 target_fl_out)
+{
+ unsigned int fl_out_diff = UINT_MAX;
+ unsigned int prcal_search;
+ u32 cdr_pr_idac = 0;
+
+ for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
+ unsigned int fl_out_diff_new;
+ unsigned int fl_out;
+ u32 cdr_pr_idac_tmp;
+
+ /* try to find the upper value by setting the last 3 bit */
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ prcal_search);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff_new < fl_out_diff) {
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ fl_out_diff = fl_out_diff_new;
+ }
+ }
+
+ return cdr_pr_idac;
+}
+
+static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, int index,
+ u32 target_fl_out, u32 cdr_pr_idac_major)
+{
+ unsigned int remaining_prcal_search_bits = 0;
+ u32 cdr_pr_idac = cdr_pr_idac_major;
+ unsigned int fl_out, fl_out_diff;
+ int best_prcal_search_bit = -1;
+ int prcal_search_bit;
+
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);
+ fl_out_diff = abs_diff(fl_out, target_fl_out);
+
+ /* Deadline search part.
+ * We start from top bits to bottom as we progressively decrease the
+ * signal.
+ */
+ for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff_new < fl_out_diff) {
+ best_prcal_search_bit = prcal_search_bit;
+ fl_out_diff = fl_out_diff_new;
+ }
+ }
+
+ /* Set the idac with the best value we found and
+ * reset the search bit to start from bottom to top.
+ */
+ if (best_prcal_search_bit >= 0) {
+ cdr_pr_idac |= BIT(best_prcal_search_bit);
+ remaining_prcal_search_bits = best_prcal_search_bit;
+ prcal_search_bit = 0;
+ }
+
+ /* Fine tune part.
+ * Test remaining bits to find an even closer signal level to target
+ * by increasing the signal.
+ */
+ while (remaining_prcal_search_bits) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ /* Assume we found the deadline when the new absolue signal difference
+ * from target is greater than the previous and the difference is at
+ * least 10% greater between the old and new value.
+ * This is to account for signal detection level tollerance making
+ * sure we are actually over a deadline (AKA we are getting farther
+ * from target)
+ */
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+
+ /* Exact match, set the bit and exit */
+ if (!fl_out_diff_new) {
+ cdr_pr_idac |= BIT(prcal_search_bit);
+ break;
+ }
+
+ if (fl_out_diff && fl_out_diff_new > fl_out_diff &&
+ (abs_diff(fl_out_diff_new, fl_out_diff) * 100) / fl_out_diff > 10) {
+ /* Exit early if we are already at the deadline */
+ if (prcal_search_bit == 0)
+ break;
+
+ /* We found the deadline, set the value to the previous
+ * bit, and reset the loop to fine tune with the
+ * remaining values.
+ */
+ cdr_pr_idac |= BIT(prcal_search_bit - 1);
+ remaining_prcal_search_bits = prcal_search_bit - 1;
+ prcal_search_bit = 0;
+ } else {
+ /* Update the signal level diff and try the next bit */
+ fl_out_diff = fl_out_diff_new;
+
+ /* If we didn't found the deadline, set the last bit
+ * and reset the loop to fine tune with the remainig
+ * values.
+ */
+ if (prcal_search_bit == remaining_prcal_search_bits - 1) {
+ cdr_pr_idac |= BIT(prcal_search_bit);
+ remaining_prcal_search_bits = prcal_search_bit;
+ prcal_search_bit = 0;
+ } else {
+ prcal_search_bit++;
+ }
+ }
+ }
+
+ return cdr_pr_idac;
+}
+
+static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 cdr_pr_idac_major, cdr_pr_idac;
+ unsigned int fl_out, fl_out_diff;
+
+ u32 target_fl_out;
+ u32 cyclecnt;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */
+ case PHY_INTERFACE_MODE_1000BASEX:
+ target_fl_out = 0xa3d6;
+ cyclecnt = 32767;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */
+ target_fl_out = 0xa000;
+ cyclecnt = 20000;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */
+ case PHY_INTERFACE_MODE_10GBASER:
+ target_fl_out = 0x9edf;
+ cyclecnt = 32767;
+ break;
+ default:
+ return;
+ }
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
+ AIROHA_PCS_PMA_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+ AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+ AIROHA_PCS_PMA_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_LOCK_UNLOCKTH |
+ AIROHA_PCS_PMA_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
+ AIROHA_PCS_PMA_UNLOCK_TARGET_END |
+ AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ /* Calibration logic:
+ * First check the major value by looping with every
+ * value in the last 3 bit of CDR_PR_IDAC.
+ * Get the signal level and save the value that is closer to
+ * the target.
+ *
+ * Then check each remaining 7 bits in search of the deadline
+ * where the signal gets farther than signal target.
+ *
+ * Finally fine tune for the remaining bits to find the one that
+ * produce the closest signal level.
+ */
+ cdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv, index, target_fl_out);
+
+ cdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, index,
+ target_fl_out, cdr_pr_idac_major);
+
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);
+ fl_out_diff = abs_diff(fl_out, target_fl_out);
+ if (fl_out_diff > 100) {
+ u32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ cdr_pr_idac_major);
+ unsigned int fl_out_tmp, fl_out_diff_tmp;
+ u32 cdr_pr_idac_tmp;
+
+ if (pr_idac_major > 0) {
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ pr_idac_major - 1);
+
+ dev_dbg(priv->dev, "Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\n",
+ fl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp);
+
+ cdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, index,
+ target_fl_out,
+ cdr_pr_idac_tmp);
+
+ fl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, index,
+ cdr_pr_idac_tmp);
+ fl_out_diff_tmp = abs_diff(fl_out_tmp, target_fl_out);
+ if (fl_out_diff_tmp < fl_out_diff) {
+ fl_out = fl_out_tmp;
+ fl_out_diff = fl_out_diff_tmp;
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ }
+ }
+ }
+ dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
+ if (fl_out_diff > 100)
+ dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n",
+ fl_out_diff, target_fl_out);
+
+ /* Setup Load Band */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x0);
+
+ /* Disable force of LPF C previously enabled */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_B,
+ AIROHA_PCS_PMA_LOAD_EN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_1,
+ AIROHA_PCS_PMA_LPATH_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+}
+
+/* This is used to both calibrate and lock to signal (after a previous
+ * calibration) after a global reset.
+ */
+static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, int index,
+ phy_interface_t interface, bool calibrate)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Setup LPF L2D force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+ /* Calibrate IDAC and setup Load Band */
+ if (calibrate)
+ an7581_pcs_rx_prcal(priv, index, interface);
+
+ /* Setup LPF RSTB force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ usleep_range(700, 1000);
+
+ /* Force Enable LPF RSTB */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+ usleep_range(100, 200);
+
+ /* Force Enable LPF L2D */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+ /* Disable LPF RSTB force bit */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ /* Disable LPF L2D force bit */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+}
+
+static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ int calibration_try = 0;
+ u32 val = 0;
+
+ an7581_pcs_tx_bringup(priv, index, interface);
+ an7581_pcs_rx_bringup(priv, index, interface);
+
+ usleep_range(100, 200);
+
+retry_calibration:
+ an7581_pcs_cdr_reset(priv, index, interface, priv->manual_rx_calib);
+
+ /* Global reset clear */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ /* Global reset */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+ usleep_range(5000, 7000);
+
+ an7581_pcs_cdr_reset(priv, index, interface, false);
+
+ /* Manual RX calibration is required only for SoC before E2
+ * revision. E2+ SoC autocalibrate RX and only CDR reset is needed.
+ */
+ if (!priv->manual_rx_calib)
+ return 0;
+
+ /* It was discovered that after a global reset and auto mode gets
+ * actually enabled, the fl_out from calibration might change and
+ * might deviates a lot from the expected value it was calibrated for.
+ * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
+ * (frequency level output) or no signal can correctly be transmitted.
+ * This is detected by checking the FreqDet module Lock bit.
+ *
+ * If it's detected that the FreqDet module is not locked, retry
+ * calibration. From observation on real hardware with a 10g SFP module,
+ * it required a maximum of an additional calibration to actually make
+ * the FreqDet module to lock. Try 50 times before failing to handle
+ * really strange case.
+ */
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+ if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
+ if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
+ dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
+ AIROHA_PCS_MAX_CALIBRATION_TRY);
+ return -EIO;
+ }
+
+ calibration_try++;
+
+ dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
+ goto retry_calibration;
+ }
+
+ return 0;
+}
+
+static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ an7581_pcs_jcpll_bringup(priv, index, interface);
+
+ usleep_range(200, 300);
+
+ an7581_pcs_txpll_bringup(priv, index, interface);
+
+ usleep_range(200, 300);
+}
+
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv, int index,
+ phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+
+ /* Enable Analog Common Lane */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CMN_EN], 0x1);
+
+ /* Setup PLL */
+ an7581_pcs_pll_bringup(priv, index, interface);
+
+ msleep(100);
+
+ /* Setup PHYA */
+ return an7581_pcs_phya_bringup(priv, index, interface);
+}
+
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ int ret;
+
+ ret = phy_set_mode_ext(priv->phy, PHY_MODE_ETHERNET, interface);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1, 0xc) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, 0x3));
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ } else {
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ }
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32);
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, 0x1));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK)));
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII);
+ else
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII);
+
+ return 0;
+}
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Reset TXPCS on link up */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+}
+
+static int __an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv, int index,
+ const struct reg_field *fields)
+{
+ struct device *dev = priv->dev;
+ int i;
+
+ priv->pcs_ana_fields[index] = devm_kcalloc(dev, AN7581_PCS_FIELDS_MAX,
+ sizeof(*priv->pcs_ana_fields[index]),
+ GFP_KERNEL);
+ if (!priv->pcs_ana_fields[index])
+ return -ENOMEM;
+
+ for (i = 0; i < AN7581_PCS_FIELDS_MAX; i++) {
+ struct regmap_field *field;
+
+ field = devm_regmap_field_alloc(dev, priv->pcs_ana,
+ fields[i]);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ priv->pcs_ana_fields[index][i] = field;
+ }
+
+ return 0;
+}
+
+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_fields);
+}
+
+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ int ret;
+
+ ret = __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_pcie0_fields);
+ if (ret)
+ return ret;
+
+ return __an7581_pcs_alloc_regmap_fields(priv, 1, an7581_pcs_pcie1_fields);
+}
+
+static bool an7581_pcs_have_rx_signal(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ unsigned int count = 0;
+ u32 val = 0;
+ int i;
+
+ regmap_write(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_0,
+ AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN);
+
+ /* Scan 6 times for RX sigdet module to detect RX signal */
+ for (i = 0; i < AIROHA_PCS_MAX_RX_SIGDET_TRY; i++) {
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_DIG_RO_RESERVE_2,
+ &val);
+ if (val & AIROHA_PCS_RX_SIGDET)
+ count++;
+ }
+
+ /* Consider signal presence if we detect signal at least 4 times */
+ return count >= AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT;
+}
+
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 val = 0;
+
+ /* Check if PCS is UP or Down */
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_STUS_1, &val);
+ if (val & AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP)
+ return 0;
+
+ /* Validate if this is consistent with RX SigDet module */
+ if (!an7581_pcs_have_rx_signal(priv, index))
+ return 0;
+
+ /* If PCS is down but RX SigDet module detected signal,
+ * trigger CDR reset.
+ */
+ an7581_pcs_cdr_reset(priv, index, PHY_INTERFACE_MODE_NA, false);
+
+ /* Report there is an error with Link Detection and we
+ * should test again later.
+ */
+ return -EINVAL;
+}
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
new file mode 100644
index 0000000000000..fef560eddf2a9
--- /dev/null
+++ b/drivers/net/pcs/pcs.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+ struct list_head link;
+
+ struct fwnode_handle *fwnode;
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+ void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
+
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier);
+
+struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_xlate);
+
+struct fwnode_pcs_provider *
+fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return ERR_PTR(-EINVAL);
+
+ pp = kzalloc_obj(*pp);
+ if (!pp)
+ return ERR_PTR(-ENOMEM);
+
+ pp->fwnode = fwnode_handle_get(fwnode);
+ pp->data = data;
+ pp->fwnode_xlate = fwnode_xlate;
+
+ mutex_lock(&fwnode_pcs_mutex);
+
+ list_add(&pp->link, &fwnode_pcs_providers);
+ fwnode_dev_initialized(fwnode, true);
+
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+ FWNODE_PCS_PROVIDER_ADD,
+ pp);
+
+ pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+ return pp;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_pcs_provider *pp)
+{
+ if (IS_ERR_OR_NULL(pp))
+ return;
+
+ mutex_lock(&fwnode_pcs_mutex);
+
+ list_del(&pp->link);
+ fwnode_dev_initialized(pp->fwnode, false);
+
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ /* Signal phylink to release any PCS from this provider */
+ blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+ FWNODE_PCS_PROVIDER_DEL,
+ pp);
+
+ fwnode_handle_put(pp->fwnode);
+ kfree(pp);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static void devm_fwnode_pcs_del(struct device *dev, void *res)
+{
+ struct fwnode_pcs_provider *pp = *(struct fwnode_pcs_provider **)res;
+
+ fwnode_pcs_del_provider(pp);
+}
+
+struct fwnode_pcs_provider *
+devm_fwnode_pcs_add_provider(struct device *dev, struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data)
+{
+ struct fwnode_pcs_provider **ptr, *pp;
+
+ ptr = devres_alloc(devm_fwnode_pcs_del, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return ERR_PTR(-ENOMEM);
+
+ pp = fwnode_pcs_add_provider(fwnode, fwnode_xlate, data);
+
+ if (!IS_ERR(pp)) {
+ *ptr = pp;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return pp;
+}
+EXPORT_SYMBOL_GPL(devm_fwnode_pcs_add_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode,
+ int index, const char *name,
+ struct fwnode_reference_args *out_args)
+{
+ if (!fwnode)
+ return -EINVAL;
+
+ if (name) {
+ index = fwnode_property_match_string(fwnode, "pcs-names",
+ name);
+ if (index < 0)
+ return index;
+ }
+
+ return fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells", 0, index,
+ out_args);
+}
+
+static struct phylink_pcs *
+__fwnode_pcs_get_from_pcsspec_provider(struct fwnode_reference_args *pcsspec,
+ struct fwnode_pcs_provider *provider)
+{
+ if (provider->fwnode != pcsspec->fwnode)
+ return ERR_PTR(-EINVAL);
+
+ return provider->fwnode_xlate(pcsspec, provider->data);
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+ struct fwnode_pcs_provider *provider;
+ struct phylink_pcs *pcs = NULL;
+
+ if (!pcsspec)
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+ pcs = __fwnode_pcs_get_from_pcsspec_provider(pcsspec, provider);
+ if (!IS_ERR(pcs))
+ break;
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ return !IS_ERR_OR_NULL(pcs) ? pcs : ERR_PTR(-ENODEV);
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(const struct fwnode_handle *fwnode,
+ unsigned int index, const char *con_id)
+{
+ struct fwnode_reference_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+ fwnode_handle_put(pcsspec.fwnode);
+
+ return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode, unsigned int index)
+{
+ return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+struct phylink_pcs *fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ int index)
+{
+ struct fwnode_reference_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = __fwnode_pcs_get_from_pcsspec_provider(&pcsspec, provider);
+ fwnode_handle_put(pcsspec.fwnode);
+ return pcs;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get_from_provider);
+
+bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ struct phylink_pcs *pl_pcs)
+{
+ struct fwnode_reference_args pcsspec;
+ int index = 0;
+ int ret;
+
+ while (true) {
+ struct phylink_pcs *pcs;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+ if (ret)
+ return false;
+
+ pcs = __fwnode_pcs_get_from_pcsspec_provider(&pcsspec, provider);
+ if (!IS_ERR(pcs) && pcs == pl_pcs) {
+ fwnode_handle_put(pcsspec.fwnode);
+ return true;
+ }
+
+ fwnode_handle_put(pcsspec.fwnode);
+ index++;
+ }
+
+ return false;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_matches_provider);
+
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ struct fwnode_reference_args out_args;
+ int index = 0;
+ int ret;
+
+ while (true) {
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells", 0, index,
+ &out_args);
+ /* We expect to reach an -ENOENT error while counting */
+ if (ret)
+ break;
+
+ fwnode_handle_put(out_args.fwnode);
+ index++;
+ }
+
+ return index;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_count);
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ unsigned int i, found = 0;
+
+ if (!available_pcs)
+ return -EINVAL;
+
+ if (!fwnode_property_present(fwnode, "pcs-handle"))
+ return -ENODEV;
+
+ for (i = 0; i < num_pcs; i++) {
+ struct phylink_pcs *pcs;
+
+ pcs = fwnode_pcs_get(fwnode, i);
+ if (IS_ERR(pcs)) {
+ /* Exit early if no PCS remain.*/
+ if (PTR_ERR(pcs) == -ENOENT)
+ break;
+
+ /*
+ * Ignore -ENODEV error for PCS that still
+ * needs to probe.
+ */
+ if (PTR_ERR(pcs) == -ENODEV)
+ continue;
+
+ return PTR_ERR(pcs);
+ }
+
+ available_pcs[found] = pcs;
+ found++;
+ }
+
+ return found;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index a7d086cdc9b25..28dad1393b694 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/phylink.h>
@@ -44,6 +45,7 @@ struct phylink {
const struct phylink_mac_ops *mac_ops;
struct phylink_config *config;
struct phylink_pcs *pcs;
+ struct fwnode_handle *fwnode;
struct device *dev;
unsigned int old_link_state:1;
@@ -60,6 +62,15 @@ struct phylink {
/* The link configuration settings */
struct phylink_link_state link_config;
+ /* List of available PCS */
+ struct list_head pcs_list;
+ struct notifier_block fwnode_pcs_nb;
+
+ /* What interface are supported by the current link.
+ * Can change on removal or addition of new PCS.
+ */
+ DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+
/* The current settings */
phy_interface_t cur_interface;
@@ -512,6 +523,22 @@ static void phylink_validate_mask_caps(unsigned long *supported,
linkmode_and(state->advertising, state->advertising, mask);
}
+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* If PCS define an empty supported_interfaces value, assume
+ * all interface are supported.
+ */
+ if (phy_interface_empty(pcs->supported_interfaces))
+ return 0;
+
+ /* Ensure that this PCS supports the interface mode */
+ if (!test_bit(interface, pcs->supported_interfaces))
+ return -EINVAL;
+
+ return 0;
+}
+
static int phylink_validate_mac_and_pcs(struct phylink *pl,
unsigned long *supported,
struct phylink_link_state *state)
@@ -520,11 +547,30 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
unsigned long capabilities;
int ret;
+ mutex_lock(&pl->state_mutex);
+
/* Get the PCS for this interface mode */
if (pl->mac_ops->mac_select_pcs) {
pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
- if (IS_ERR(pcs))
+ if (IS_ERR(pcs)) {
+ mutex_unlock(&pl->state_mutex);
return PTR_ERR(pcs);
+ }
+ /*
+ * Find a PCS in available PCS list for the requested interface.
+ *
+ * Skip searching if the MAC doesn't require a dedicated PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ struct phylink_pcs *tmp;
+
+ list_for_each_entry(tmp, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(tmp, state->interface)) {
+ pcs = tmp;
+ break;
+ }
+ }
}
if (pcs) {
@@ -533,19 +579,18 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
* error and backtrace rather than oopsing the kernel.
*/
if (!pcs->ops) {
+ mutex_unlock(&pl->state_mutex);
phylink_err(pl, "interface %s: uninitialised PCS\n",
phy_modes(state->interface));
dump_stack();
return -EINVAL;
}
- /* Ensure that this PCS supports the interface which the MAC
- * returned it for. It is an error for the MAC to return a PCS
- * that does not support the interface mode.
- */
- if (!phy_interface_empty(pcs->supported_interfaces) &&
- !test_bit(state->interface, pcs->supported_interfaces)) {
- phylink_err(pl, "MAC returned PCS which does not support %s\n",
+ /* Recheck PCS to handle legacy way for .mac_select_pcs */
+ ret = phylink_validate_pcs_interface(pcs, state->interface);
+ if (ret) {
+ mutex_unlock(&pl->state_mutex);
+ phylink_err(pl, "selected PCS does not support %s\n",
phy_modes(state->interface));
return -EINVAL;
}
@@ -553,8 +598,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
/* Validate the link parameters with the PCS */
if (pcs->ops->pcs_validate) {
ret = pcs->ops->pcs_validate(pcs, supported, state);
- if (ret < 0 || phylink_is_empty_linkmode(supported))
+ if (ret < 0 || phylink_is_empty_linkmode(supported)) {
+ mutex_unlock(&pl->state_mutex);
return -EINVAL;
+ }
/* Ensure the advertising mask is a subset of the
* supported mask.
@@ -564,6 +611,8 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
}
}
+ mutex_unlock(&pl->state_mutex);
+
/* Then validate the link parameters with the MAC */
if (pl->mac_ops->mac_get_caps)
capabilities = pl->mac_ops->mac_get_caps(pl->config,
@@ -628,7 +677,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
static int phylink_validate(struct phylink *pl, unsigned long *supported,
struct phylink_link_state *state)
{
- const unsigned long *interfaces = pl->config->supported_interfaces;
+ const unsigned long *interfaces = pl->supported_interfaces;
if (state->interface == PHY_INTERFACE_MODE_NA)
return phylink_validate_mask(pl, NULL, supported, state,
@@ -940,6 +989,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
}
+static void phylink_pcs_link_down(struct phylink_pcs *pcs)
+{
+ if (pcs && pcs->ops->pcs_link_down)
+ pcs->ops->pcs_link_down(pcs);
+}
+
static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)
{
if (pcs && pcs->ops->pcs_disable_eee)
@@ -958,16 +1013,34 @@ static void phylink_pcs_enable_eee(struct phylink_pcs *pcs)
static unsigned int phylink_inband_caps(struct phylink *pl,
phy_interface_t interface)
{
- struct phylink_pcs *pcs;
+ struct phylink_pcs *pcs = NULL;
+ int ret = 0;
- if (!pl->mac_ops->mac_select_pcs)
- return 0;
+ mutex_lock(&pl->state_mutex);
+
+ if (pl->mac_ops->mac_select_pcs) {
+ pcs = pl->mac_ops->mac_select_pcs(pl->config,
+ interface);
+ } else if (test_bit(interface, pl->config->pcs_interfaces)) {
+ struct phylink_pcs *tmp;
+
+ list_for_each_entry(tmp, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(tmp, interface)) {
+ pcs = tmp;
+ break;
+ }
+ }
+ }
- pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
if (IS_ERR_OR_NULL(pcs))
- return 0;
+ goto exit;
- return phylink_pcs_inband_caps(pcs, interface);
+ ret = phylink_pcs_inband_caps(pcs, interface);
+
+exit:
+ mutex_unlock(&pl->state_mutex);
+
+ return ret;
}
static void phylink_pcs_poll_stop(struct phylink *pl)
@@ -1260,10 +1333,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
pl->major_config_failed = true;
return;
}
+ /* Find a PCS in available PCS list for the requested interface.
+ * This doesn't overwrite the previous .mac_select_pcs as either
+ * .mac_select_pcs or PCS list implementation are permitted.
+ *
+ * Skip searching if the MAC doesn't require a dedicated PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ struct phylink_pcs *tmp;
+
+ list_for_each_entry(tmp, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(tmp,
+ state->interface)) {
+ pcs = tmp;
+ break;
+ }
+ }
- pcs_changed = pl->pcs != pcs;
+ if (!pcs) {
+ phylink_err(pl,
+ "couldn't find a PCS for %s\n",
+ phy_modes(state->interface));
+
+ pl->major_config_failed = true;
+ return;
+ }
}
+ pcs_changed = pl->pcs != pcs;
+
phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
phylink_dbg(pl, "major config, active %s/%s/%s\n",
@@ -1290,13 +1389,15 @@ static void phylink_major_config(struct phylink *pl, bool restart,
if (pcs_changed) {
phylink_pcs_disable(pl->pcs);
- if (pl->pcs)
- pl->pcs->phylink = NULL;
+ if (pl->mac_ops->mac_select_pcs) {
+ if (pl->pcs)
+ pl->pcs->phylink = NULL;
- if (pcs)
- pcs->phylink = pl;
+ if (pcs)
+ pcs->phylink = pl;
+ }
- pl->pcs = pcs;
+ WRITE_ONCE(pl->pcs, pcs);
}
if (pl->pcs)
@@ -1480,7 +1581,9 @@ static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)
phylink_apply_manual_flow(pl, &link_state);
if (phy)
mutex_lock(&phy->lock);
+ mutex_lock(&pl->state_mutex);
phylink_major_config(pl, force_restart, &link_state);
+ mutex_unlock(&pl->state_mutex);
if (phy)
mutex_unlock(&phy->lock);
}
@@ -1604,6 +1707,9 @@ static void phylink_link_down(struct phylink *pl)
pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
pl->cur_interface);
+
+ phylink_pcs_link_down(pl->pcs);
+
phylink_info(pl, "Link is Down\n");
}
@@ -1831,6 +1937,179 @@ int phylink_set_fixed_link(struct phylink *pl,
}
EXPORT_SYMBOL_GPL(phylink_set_fixed_link);
+static bool phylink_add_pcs(struct phylink *pl, struct phylink_pcs *pcs)
+{
+ struct phylink_pcs *tmp;
+
+ /*
+ * Make sure state mutex is locked to protect concurrent
+ * access to phylink instance PCS list from
+ * initial fill_available_pcs and late PCS attach
+ */
+ lockdep_assert_held(&pl->state_mutex);
+
+ /* Make sure PCS is not already in the list */
+ list_for_each_entry(tmp, &pl->pcs_list, list)
+ if (tmp == pcs)
+ return false;
+
+ list_add_tail(&pcs->list, &pl->pcs_list);
+
+ /* Link PCS to phylink */
+ pcs->phylink = pl;
+
+ return true;
+}
+
+static int phylink_fill_available_pcs(struct phylink *pl,
+ struct phylink_config *config)
+{
+ struct phylink_pcs **pcss;
+ int i, ret;
+
+ if (!config->num_possible_pcs)
+ return 0;
+
+ if (!config->fill_available_pcs) {
+ dev_err(config->dev,
+ "phylink: error: num_possible_pcs defined but no fill_available_pcs\n");
+ return -EINVAL;
+ }
+
+ pcss = kzalloc_objs(*pcss, config->num_possible_pcs);
+ if (!pcss)
+ return -ENOMEM;
+
+ /* Lock state_mutex while filling to handle PCS notify */
+ mutex_lock(&pl->state_mutex);
+
+ ret = config->fill_available_pcs(config, pcss, config->num_possible_pcs);
+ if (ret < 0)
+ goto out;
+
+ for (i = 0; i < config->num_possible_pcs; i++) {
+ struct phylink_pcs *pcs = pcss[i];
+
+ if (!pcs)
+ continue;
+
+ phylink_add_pcs(pl, pcs);
+ }
+
+out:
+ mutex_unlock(&pl->state_mutex);
+
+ kfree(pcss);
+
+ return ret;
+}
+
+static void phylink_del_pcs(struct phylink *pl, struct phylink_pcs *pcs)
+{
+ lockdep_assert_held(&pl->state_mutex);
+
+ list_del(&pcs->list);
+ pcs->phylink = NULL;
+
+ /*
+ * Check if we are removing the PCS currently
+ * in use by this phylink instance. If this is the case,
+ * tear down the link, force phylink resolve to reconfigure the
+ * interface mode, disable the current PCS and set the
+ * phylink PCS to NULL.
+ */
+ if (pl->pcs == pcs) {
+ if (pl->old_link_state) {
+ phylink_link_down(pl);
+ pl->old_link_state = false;
+ }
+ if (pl->cfg_link_an_mode == MLO_AN_INBAND)
+ timer_delete_sync(&pl->link_poll);
+ phylink_pcs_disable(pl->pcs);
+
+ pl->force_major_config = true;
+ WRITE_ONCE(pl->pcs, NULL);
+ }
+}
+
+static int pcs_provider_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+ struct fwnode_pcs_provider *pp = data;
+ struct phylink_pcs *pcs, *tmp;
+ bool resolve = false;
+ int count, i;
+
+ rtnl_lock();
+
+ mutex_lock(&pl->state_mutex);
+
+ switch (val) {
+ case FWNODE_PCS_PROVIDER_ADD:
+ count = fwnode_phylink_pcs_count(pl->fwnode);
+ for (i = 0; i < count; i++) {
+ pcs = fwnode_pcs_get_from_provider(pp, pl->fwnode, i);
+ if (IS_ERR(pcs))
+ continue;
+
+ /* Trigger a resolve only if a PCS is actually added */
+ if (phylink_add_pcs(pl, pcs))
+ resolve = true;
+ }
+
+ /* Force an interface reconfig if major config fail */
+ if (resolve && pl->major_config_failed)
+ pl->force_major_config = true;
+
+ break;
+ case FWNODE_PCS_PROVIDER_DEL:
+ /*
+ * Loop all the PCS for phylink instance and check if
+ * this notification is relevant for some of them.
+ */
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) {
+ if (!fwnode_pcs_matches_provider(pp, pl->fwnode, pcs))
+ continue;
+
+ phylink_del_pcs(pl, pcs);
+ resolve = true;
+ }
+ break;
+ }
+
+ /* Exit early if nothing has changed */
+ if (!resolve) {
+ mutex_unlock(&pl->state_mutex);
+
+ rtnl_unlock();
+
+ return NOTIFY_DONE;
+ }
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ mutex_unlock(&pl->state_mutex);
+
+ /* Recalculate capabilities */
+ linkmode_fill(pl->supported);
+ linkmode_fill(pl->link_config.advertising);
+ phylink_validate_mask(pl, NULL, pl->supported, &pl->link_config,
+ pl->supported_interfaces);
+
+ rtnl_unlock();
+
+ phylink_run_resolve(pl);
+
+ return NOTIFY_OK;
+}
+
/**
* phylink_update_pause_state() - Update the phylink pause frame configuration
* @pl: a pointer to a &struct phylink instance
@@ -1972,9 +2251,20 @@ struct phylink *phylink_create(struct phylink_config *config,
phy_interface_t iface,
const struct phylink_mac_ops *mac_ops)
{
+ struct phylink_pcs *tmp, *pcs;
struct phylink *pl;
int ret;
+ /*
+ * Make sure either PCS internal validation or .mac_select_pcs
+ * is used. Return error if both are defined.
+ */
+ if (config->num_possible_pcs && mac_ops->mac_select_pcs) {
+ dev_err(config->dev,
+ "phylink: error: either phylink_config .num_possible_pcs or .mac_select_pcs must be used\n");
+ return ERR_PTR(-EINVAL);
+ }
+
/* Validate the supplied configuration */
if (phy_interface_empty(config->supported_interfaces)) {
dev_err(config->dev,
@@ -1989,8 +2279,10 @@ struct phylink *phylink_create(struct phylink_config *config,
mutex_init(&pl->phydev_mutex);
mutex_init(&pl->state_mutex);
INIT_WORK(&pl->resolve, phylink_resolve);
+ INIT_LIST_HEAD(&pl->pcs_list);
pl->config = config;
+ pl->fwnode = fwnode_handle_get((struct fwnode_handle *)fwnode);
if (config->type == PHYLINK_NETDEV) {
pl->netdev = to_net_dev(config->dev);
netif_carrier_off(pl->netdev);
@@ -2026,13 +2318,37 @@ struct phylink *phylink_create(struct phylink_config *config,
__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
+ /* First register notifier for hotplug PCS events */
+ if (!phy_interface_empty(config->pcs_interfaces)) {
+ pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+ register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+ }
+
+ /* Fill the PCS list with available PCS from phylink config */
+ ret = phylink_fill_available_pcs(pl, config);
+ if (ret < 0)
+ goto unregister_pcs_notify;
+
+ mutex_lock(&pl->state_mutex);
+
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+
+ /* Update supported interfaces */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ mutex_unlock(&pl->state_mutex);
+
linkmode_fill(pl->supported);
linkmode_copy(pl->link_config.advertising, pl->supported);
phylink_validate(pl, pl->supported, &pl->link_config);
ret = phylink_parse_mode(pl, fwnode);
if (ret < 0)
- goto free_pl;
+ goto unregister_pcs_notify;
if (pl->cfg_link_an_mode == MLO_AN_FIXED) {
ret = phylink_parse_fixedlink(pl, fwnode);
@@ -2051,7 +2367,19 @@ struct phylink *phylink_create(struct phylink_config *config,
release_link_gpio:
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+unregister_pcs_notify:
+ if (pl->fwnode_pcs_nb.notifier_call)
+ unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+ /* PCS notifier might queue a resolve, cancel it */
+ cancel_work_sync(&pl->resolve);
+ mutex_lock(&pl->state_mutex);
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) {
+ list_del(&pcs->list);
+ pcs->phylink = NULL;
+ }
+ mutex_unlock(&pl->state_mutex);
free_pl:
+ fwnode_handle_put(pl->fwnode);
kfree(pl);
return ERR_PTR(ret);
}
@@ -2068,11 +2396,30 @@ EXPORT_SYMBOL_GPL(phylink_create);
*/
void phylink_destroy(struct phylink *pl)
{
+ struct phylink_pcs *pcs, *tmp;
+
sfp_bus_del_upstream(pl->sfp_bus);
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+ /* Unregister notifier for late PCS attach */
+ if (pl->fwnode_pcs_nb.notifier_call)
+ unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+
cancel_work_sync(&pl->resolve);
+
+ mutex_lock(&pl->state_mutex);
+
+ /* Remove every PCS from phylink PCS list */
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) {
+ pcs->phylink = NULL;
+ list_del(&pcs->list);
+ }
+
+ mutex_unlock(&pl->state_mutex);
+
+ fwnode_handle_put(pl->fwnode);
+
kfree(pl);
}
EXPORT_SYMBOL_GPL(phylink_destroy);
@@ -2147,7 +2494,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
* those which the host supports.
*/
phy_interface_and(interfaces, phy->possible_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
if (phy_interface_empty(interfaces)) {
phylink_err(pl, "PHY has no common interfaces\n");
@@ -2538,8 +2885,15 @@ void phylink_pcs_change(struct phylink_pcs *pcs, bool up)
{
struct phylink *pl = pcs->phylink;
- if (pl)
- phylink_link_changed(pl, up, "pcs");
+ /*
+ * Ignore PCS link state change if the PCS is not
+ * attached to a phylink instance or the phylink
+ * instance is not currently using this PCS.
+ */
+ if (!pl || READ_ONCE(pl->pcs) != pcs)
+ return;
+
+ phylink_link_changed(pl, up, "pcs");
}
EXPORT_SYMBOL_GPL(phylink_pcs_change);
@@ -2961,12 +3315,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,
return interface;
}
- if (!test_bit(interface, pl->config->supported_interfaces)) {
+ if (!test_bit(interface, pl->supported_interfaces)) {
phylink_err(pl,
"selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\n",
phy_modes(interface), interface,
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
return PHY_INTERFACE_MODE_NA;
}
@@ -3845,14 +4199,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)
phylink_dbg(pl, "optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\n",
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces,
+ pl->supported_interfaces,
(int)PHY_INTERFACE_MODE_MAX,
pl->sfp_interfaces);
/* Find the union of the supported interfaces by the PCS/MAC and
* the SFP module.
*/
- phy_interface_and(pl->sfp_interfaces, pl->config->supported_interfaces,
+ phy_interface_and(pl->sfp_interfaces, pl->supported_interfaces,
pl->sfp_interfaces);
if (phy_interface_empty(pl->sfp_interfaces)) {
phylink_err(pl, "unsupported SFP module: no common interface modes\n");
@@ -4023,7 +4377,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
/* Set the PHY's host supported interfaces */
phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
/* Do the initial configuration */
return phylink_sfp_config_phy(pl, phy);
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 0000000000000..15c198ffdd580
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+struct fwnode_pcs_provider;
+
+/**
+ * fwnode_pcs_simple_xlate - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns: the PCS pointed by data.
+ */
+struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @fwnode: Firmware node
+ * @fwnode_xlate: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS provider to the global providers list
+ * for the firmware node. The relevant PCS from the PCS provider
+ * is retrieved from the passed fwnode_xlate function.
+ *
+ * The xlate function MUST return a pointer to an existing, already-allocated
+ * struct phylink_pcs and MUST NOT dynamically allocate a new PCS.
+ * The same PCS object must be returned for a given firmware reference and args,
+ * as PCS pointer identity is used to associate PCS objects with their provider.
+ *
+ * Returns: A pointer to the registered PCS provider on success, or
+ * an ERR_PTR() encoded error code on failure.
+ */
+struct fwnode_pcs_provider *
+fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @pp: PCS provider returned by fwnode_pcs_add_provider()
+ */
+void fwnode_pcs_del_provider(struct fwnode_pcs_provider *pp);
+
+/**
+ * devm_fwnode_pcs_add_provider - Registers a new PCS provider
+ * @dev: Device of the PCS provider
+ * @fwnode: Firmware node
+ * @fwnode_xlate: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS provider to the global providers list
+ * for the firmware node. The relevant PCS from the PCS provider
+ * is retrieved from the passed fwnode_xlate function. While at that, it
+ * also associates the device with the PCS provider using devres.
+ * On driver detach, release function is invoked on the devres data,
+ * then, devres data is freed.
+ *
+ * Returns: A pointer to the registered PCS provider on success, or
+ * an ERR_PTR() encoded error code on failure.
+ */
+struct fwnode_pcs_provider *
+devm_fwnode_pcs_add_provider(struct device *dev, struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 0000000000000..00a636c82c65f
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+enum fwnode_pcs_notify_event {
+ FWNODE_PCS_PROVIDER_ADD,
+ FWNODE_PCS_PROVIDER_DEL,
+};
+
+struct fwnode_pcs_provider;
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns: 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
+/**
+ * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Unregisters a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain.
+ *
+ * Returns: 0 or a negative error.
+ */
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb);
+
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative error pointer. Can
+ * return -ENODEV if the PCS is not present in global providers list (either
+ * due to driver still needs to be probed or it failed to probe/removed).
+ */
+struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode,
+ unsigned int index);
+
+/**
+ * fwnode_pcs_get_from_provider() - Retrieve a PCS from a specific provider
+ * @provider: PCS provider to use
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index specifically provided by
+ * passed PCS provider.
+ *
+ * Unlike fwnode_pcs_get(), this function does not search the global list of
+ * PCS providers. The caller must provide the provider responsible for the
+ * referenced PCS.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative error pointer. Can
+ * return -ENODEV if the PCS is not present in global providers list (either
+ * due to driver still needs to be probed or it failed to probe/removed) or
+ * can return -EINVAL if the PCS provider doesn't expose any PCS for the fwnode.
+ */
+struct phylink_pcs *fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ int index);
+
+/**
+ * fwnode_pcs_matches_provider() - Check whether a PCS belongs to a provider
+ * @provider: PCS provider to check
+ * @fwnode: firmware node containing the PCS references
+ * @pl_pcs: PCS to check
+ *
+ * Parse the PCS references from the "pcs-handle" property of a firmware node
+ * and use provider to determine whether pl_pcs is one of the PCS provided by
+ * provider.
+ *
+ * This function is intended to be used when handling provider removal
+ * notifications, where the provider is already known and its PCS need to be
+ * identified among the PCS associated with a phylink instance.
+ *
+ * Returns: true if pl_pcs is provided by provider and referenced by fwnode,
+ * false otherwise.
+ */
+bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ struct phylink_pcs *pl_pcs);
+
+/**
+ * fwnode_phylink_pcs_count - Count PCS entries described in firmware node
+ * @fwnode: firmware node
+ *
+ * Helper function to count the number of PCS entries referenced by the
+ * "pcs-handle" property in a firmware node.
+ *
+ * Note that this function counts all PCS references in the firmware node,
+ * regardless of whether the corresponding PCS devices are already probed.
+ *
+ * Returns: number of PCS entries described in the firmware node.
+ */
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode);
+
+/**
+ * fwnode_phylink_pcs_parse - Parse available PCS from firmware node
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: maximum number of PCS entries to scan
+ *
+ * Helper function that parses PCS references from the "pcs-handle"
+ * property of a firmware node and fills @available_pcs with PCS that are
+ * currently available up to @num_pcs.
+ *
+ * Only PCS that are currently available are stored in @available_pcs.
+ * PCS that returns -ENODEV are skipped.
+ *
+ * Returns: number of PCS stored in @available_pcs, or negative error code.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs);
+#else
+static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode,
+ unsigned int index)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline struct phylink_pcs *
+fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ int index)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ struct phylink_pcs *pl_pcs)
+{
+ return false;
+}
+
+static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ return 0;
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 3a88a69882a61..f03c1dc0a4a11 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -12,6 +12,7 @@ struct ethtool_cmd;
struct fwnode_handle;
struct net_device;
struct phylink;
+struct phylink_pcs;
enum {
MLO_PAUSE_NONE,
@@ -151,6 +152,8 @@ enum phylink_op_type {
* if MAC link is at %MLO_AN_FIXED mode.
* @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
* are supported by the MAC/PCS.
+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
+ * dedicated PCS is required.
* @lpi_interfaces: bitmap describing which PHY interface modes can support
* LPI signalling.
* @mac_capabilities: MAC pause/speed/duplex capabilities.
@@ -160,6 +163,10 @@ enum phylink_op_type {
* @wol_phy_legacy: Use Wake-on-Lan with PHY even if phy_can_wakeup() is false
* @wol_phy_speed_ctrl: Use phy speed control on suspend/resume
* @wol_mac_support: Bitmask of MAC supported %WAKE_* options
+ * @num_possible_pcs: num of possible phylink_pcs PCS
+ * @fill_available_pcs: callback to fill the available PCS in the passed
+ * array struct of phylink_pcs PCS available_pcs up to
+ * num_possible_pcs.
*/
struct phylink_config {
struct device *dev;
@@ -172,6 +179,7 @@ struct phylink_config {
void (*get_fixed_state)(struct phylink_config *config,
struct phylink_link_state *state);
DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+ DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
unsigned long mac_capabilities;
unsigned long lpi_capabilities;
@@ -182,6 +190,11 @@ struct phylink_config {
bool wol_phy_legacy;
bool wol_phy_speed_ctrl;
u32 wol_mac_support;
+
+ unsigned int num_possible_pcs;
+ int (*fill_available_pcs)(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs);
};
void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
@@ -497,6 +510,9 @@ struct phylink_pcs {
struct phylink *phylink;
bool poll;
bool rxc_always_on;
+
+ /* private: */
+ struct list_head list;
};
/**
@@ -512,6 +528,7 @@ struct phylink_pcs {
* @pcs_an_restart: restart 802.3z BaseX autonegotiation.
* @pcs_link_up: program the PCS for the resolved link configuration
* (where necessary).
+ * @pcs_link_down: tear down link between MAC and PCS.
* @pcs_disable_eee: optional notification to PCS that EEE has been disabled
* at the MAC.
* @pcs_enable_eee: optional notification to PCS that EEE will be enabled at
@@ -539,6 +556,7 @@ struct phylink_pcs_ops {
void (*pcs_an_restart)(struct phylink_pcs *pcs);
void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface, int speed, int duplex);
+ void (*pcs_link_down)(struct phylink_pcs *pcs);
void (*pcs_disable_eee)(struct phylink_pcs *pcs);
void (*pcs_enable_eee)(struct phylink_pcs *pcs);
int (*pcs_pre_init)(struct phylink_pcs *pcs);
@@ -674,6 +692,16 @@ void pcs_an_restart(struct phylink_pcs *pcs);
void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface, int speed, int duplex);
+/**
+ * pcs_link_down() - tear down link between MAC and PCS
+ * @pcs: a pointer to a &struct phylink_pcs.
+ *
+ * This call will be made just after mac_link_down() to inform the PCS the
+ * link has gone down. PCS should be configured to stop processing packets
+ * for transmission and reception.
+ */
+void pcs_link_down(struct phylink_pcs *pcs);
+
/**
* pcs_disable_eee() - Disable EEE at the PCS
* @pcs: a pointer to a &struct phylink_pcs
|
| 3/2 | 2026/10/09 21:55 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 140819 output: 29 thoughts: 559 Thoughts: **Analyzing the Patch Series: Network PCS and Phylink Integration** Okay, let's break this down. My initial scan tells me this patch series is focused on integrating a new PCS (Physical Coding Sublayer) – specifically an Airoha PCS – into the kernel's networking stack. The files listed point to a comprehensive set of changes. I see documentation (devicetree bindings, RST files), maintainer entries (crucial), driver code (Kconfig, C files, headers for the Airoha PCS), PCS-specific Kconfig and Makefiles, the PCS framework itself, and, most importantly, core changes within the `phylink.c` file. I'm also seeing core header file changes. Now, let's zero in on the architecture: `amd64`. This is a standard target, but the real meat is in the modification to `drivers/net/phy/phylink.c`. *That's* the library containing the core phylink functionality - critical infrastructure. Is it used in amd64 kernels in any form, or virtualized environments? Of course! Phylink is a central component for PHY drivers and network PHY libraries. I'm now going to focus intensely on the `phylink.c` changes: It's all about how `phylink` interacts with PCS sublayers now. These aren't just minor tweaks; we are talking about *fundamental* additions for managing PCS instances. The list of changed functions is telling: `phylink_validate_mac_and_pcs()`, `phylink_major_config()`, `phylink_inband_caps()`, `phylink_create()`, `phylink_destroy()`, `phylink_fill_available_pcs()`, `phylink_add_pcs()`, `phylink_del_pcs()`, `pcs_provider_notify()`, `phylink_pcs_link_down()`, `phylink_pcs_change()`, `phylink_sfp_select_interface()`, `phylink_sfp_config_optical()`, `phylink_sfp_connect_phy()` - this is *deep* integration of a multi-PCS model within phylink. This is *big*. To get a full picture, I need to understand what drivers already use phylink and how these changes will impact them. A `grep` for phylink throughout the kernel source is in order. |
| 4/2 | 2026/10/09 21:56 | tool | grepper |
0mArgs:{
"Expression": "phylink_create",
"PathPrefixes": [
"drivers/net/"
]
}Results: {
"Output": "\nFull output is too long, showing 200 out of 456 lines.\nUse more precise expression or PathPrefixes if possible.\n\nNumber of matching lines per file (34 files in total):\ndrivers/net/ethernet/airoha/airoha_eth.c:1\ndrivers/net/ethernet/altera/altera_tse_main.c:1\ndrivers/net/ethernet/atheros/ag71xx.c:1\ndrivers/net/ethernet/cadence/macb_main.c:1\ndrivers/net/ethernet/freescale/dpaa/dpaa_eth.c:1\ndrivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c:1\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c:3\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c:3\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c:3\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.h:1\ndrivers/net/ethernet/freescale/fs_enet/fs_enet-main.c:1\ndrivers/net/ethernet/freescale/ucc_geth.c:1\ndrivers/net/ethernet/marvell/mvneta.c:1\ndrivers/net/ethernet/marvell/mvpp2/mvpp2_main.c:1\ndrivers/net/ethernet/marvell/prestera/prestera_main.c:1\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c:1\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.c:1\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.h:1\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c:3\ndrivers/net/ethernet/microchip/lan743x_main.c:3\ndrivers/net/ethernet/microchip/lan966x/lan966x_main.c:1\ndrivers/net/ethernet/microchip/sparx5/sparx5_main.c:1\ndrivers/net/ethernet/mscc/ocelot_net.c:3\ndrivers/net/ethernet/realtek/r8169_main.c:1\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:1\ndrivers/net/ethernet/tehuti/tn40_phy.c:1\ndrivers/net/ethernet/ti/am65-cpsw-nuss.c:1\ndrivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c:1\ndrivers/net/ethernet/wangxun/txgbe/txgbe_aml.c:1\ndrivers/net/ethernet/wangxun/txgbe/txgbe_phy.c:1\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:2\ndrivers/net/phy/phylink.c:36\ndrivers/net/usb/asix_devices.c:1\ndrivers/net/usb/lan78xx.c:1\n\ndrivers/net/ethernet/airoha/airoha_eth.c=3879=static int airoha_setup_phylink(struct net_device *netdev)\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3931-\ndrivers/net/ethernet/airoha/airoha_eth.c:3932:\tphylink = phylink_create(config, of_fwnode_handle(np),\ndrivers/net/ethernet/airoha/airoha_eth.c-3933-\t\t\t\t phy_mode, \u0026airoha_phylink_ops);\n--\ndrivers/net/ethernet/altera/altera_tse_main.c=1128=static int altera_tse_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/altera/altera_tse_main.c-1415-\ndrivers/net/ethernet/altera/altera_tse_main.c:1416:\tpriv-\u003ephylink = phylink_create(\u0026priv-\u003ephylink_config,\ndrivers/net/ethernet/altera/altera_tse_main.c-1417-\t\t\t\t of_fwnode_handle(priv-\u003edevice-\u003eof_node),\n--\ndrivers/net/ethernet/atheros/ag71xx.c=1074=static int ag71xx_phylink_setup(struct ag71xx *ag)\n--\ndrivers/net/ethernet/atheros/ag71xx.c-1108-\ndrivers/net/ethernet/atheros/ag71xx.c:1109:\tphylink = phylink_create(\u0026ag-\u003ephylink_config, ag-\u003epdev-\u003edev.fwnode,\ndrivers/net/ethernet/atheros/ag71xx.c-1110-\t\t\t\t ag-\u003ephy_if_mode, \u0026ag71xx_phylink_mac_ops);\n--\ndrivers/net/ethernet/cadence/macb_main.c=1037=static int macb_mii_probe(struct net_device *netdev)\n--\ndrivers/net/ethernet/cadence/macb_main.c-1104-\ndrivers/net/ethernet/cadence/macb_main.c:1105:\tbp-\u003ephylink = phylink_create(\u0026bp-\u003ephylink_config, bp-\u003epdev-\u003edev.fwnode,\ndrivers/net/ethernet/cadence/macb_main.c-1106-\t\t\t\t bp-\u003ephy_interface, \u0026macb_phylink_ops);\n--\ndrivers/net/ethernet/freescale/dpaa/dpaa_eth.c=201=static int dpaa_netdev_init(struct net_device *net_dev,\n--\ndrivers/net/ethernet/freescale/dpaa/dpaa_eth.c-274-\tmac_dev-\u003eupdate_speed = dpaa_eth_cgr_set_speed;\ndrivers/net/ethernet/freescale/dpaa/dpaa_eth.c:275:\tmac_dev-\u003ephylink = phylink_create(\u0026mac_dev-\u003ephylink_config,\ndrivers/net/ethernet/freescale/dpaa/dpaa_eth.c-276-\t\t\t\t\t dev_fwnode(mac_dev-\u003edev),\n--\ndrivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c=560=int dpaa2_mac_connect(struct dpaa2_mac *mac)\n--\ndrivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c-624-\ndrivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c:625:\tphylink = phylink_create(\u0026mac-\u003ephylink_config,\ndrivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c-626-\t\t\t\t dpmac_node, mac-\u003eif_mode,\n--\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c=949=static int enetc4_link_init(struct enetc_ndev_priv *priv,\n--\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c-967-\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c:968:\terr = enetc_phylink_create(priv, node, \u0026enetc_pl_mac_ops);\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c-969-\tif (err) {\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c-970-\t\tdev_err(dev, \"Failed to create phylink\\n\");\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c:971:\t\tgoto err_phylink_create;\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c-972-\t}\n--\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c-975-\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c:976:err_phylink_create:\ndrivers/net/ethernet/freescale/enetc/enetc4_pf.c-977-\tenetc_mdiobus_destroy(pf);\n--\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c=787=static int enetc_pf_probe(struct pci_dev *pdev,\n--\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c-869-\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c:870:\terr = enetc_phylink_create(priv, node, \u0026enetc_mac_phylink_ops);\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c-871-\tif (err)\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c:872:\t\tgoto err_phylink_create;\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c-873-\n--\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c-881-\tenetc_phylink_destroy(priv);\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c:882:err_phylink_create:\ndrivers/net/ethernet/freescale/enetc/enetc_pf.c-883-\tenetc_mdiobus_destroy(pf);\n--\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c=437=EXPORT_SYMBOL_GPL(enetc_mdiobus_destroy);\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c-438-\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c:439:int enetc_phylink_create(struct enetc_ndev_priv *priv, struct device_node *node,\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c-440-\t\t\t const struct phylink_mac_ops *ops)\n--\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c-479-\tpf-\u003ephylink_config.mac_capabilities = mac_caps;\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c:480:\tphylink = phylink_create(\u0026pf-\u003ephylink_config, of_fwnode_handle(node),\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c-481-\t\t\t\t pf-\u003eif_mode, ops);\n--\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c-490-}\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c:491:EXPORT_SYMBOL_GPL(enetc_phylink_create);\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.c-492-\n--\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.h=12=void enetc_mdiobus_destroy(struct enetc_pf *pf);\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.h:13:int enetc_phylink_create(struct enetc_ndev_priv *priv, struct device_node *node,\ndrivers/net/ethernet/freescale/enetc/enetc_pf_common.h-14-\t\t\t const struct phylink_mac_ops *ops);\n--\ndrivers/net/ethernet/freescale/fs_enet/fs_enet-main.c=853=static int fs_enet_probe(struct platform_device *ofdev)\n--\ndrivers/net/ethernet/freescale/fs_enet/fs_enet-main.c-932-\ndrivers/net/ethernet/freescale/fs_enet/fs_enet-main.c:933:\tphylink = phylink_create(\u0026fep-\u003ephylink_config, dev_fwnode(fep-\u003edev),\ndrivers/net/ethernet/freescale/fs_enet/fs_enet-main.c-934-\t\t\t\t phy_mode, \u0026fs_enet_phylink_mac_ops);\n--\ndrivers/net/ethernet/freescale/ucc_geth.c=3419=static int ucc_geth_probe(struct platform_device* ofdev)\n--\ndrivers/net/ethernet/freescale/ucc_geth.c-3573-\ndrivers/net/ethernet/freescale/ucc_geth.c:3574:\tphylink = phylink_create(\u0026ugeth-\u003ephylink_config, dev_fwnode(\u0026dev-\u003edev),\ndrivers/net/ethernet/freescale/ucc_geth.c-3575-\t\t\t\t phy_interface, \u0026ugeth_mac_ops);\n--\ndrivers/net/ethernet/marvell/mvneta.c=5480=static int mvneta_probe(struct platform_device *pdev)\n--\ndrivers/net/ethernet/marvell/mvneta.c-5598-\ndrivers/net/ethernet/marvell/mvneta.c:5599:\tphylink = phylink_create(\u0026pp-\u003ephylink_config, pdev-\u003edev.fwnode,\ndrivers/net/ethernet/marvell/mvneta.c-5600-\t\t\t\t phy_mode, \u0026mvneta_phylink_ops);\n--\ndrivers/net/ethernet/marvell/mvpp2/mvpp2_main.c=6841=static int mvpp2_port_probe(struct platform_device *pdev,\n--\ndrivers/net/ethernet/marvell/mvpp2/mvpp2_main.c-7148-\ndrivers/net/ethernet/marvell/mvpp2/mvpp2_main.c:7149:\t\tphylink = phylink_create(\u0026port-\u003ephylink_config, port_fwnode,\ndrivers/net/ethernet/marvell/mvpp2/mvpp2_main.c-7150-\t\t\t\t\t phy_mode, \u0026mvpp2_phylink_ops);\n--\ndrivers/net/ethernet/marvell/prestera/prestera_main.c=370=static int prestera_port_sfp_bind(struct prestera_port *port)\n--\ndrivers/net/ethernet/marvell/prestera/prestera_main.c-416-\ndrivers/net/ethernet/marvell/prestera/prestera_main.c:417:\t\tphy_link = phylink_create(\u0026port-\u003ephy_config, fwnode,\ndrivers/net/ethernet/marvell/prestera/prestera_main.c-418-\t\t\t\t\t PHY_INTERFACE_MODE_INTERNAL,\n--\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c=4828=static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)\n--\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c-4984-\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c:4985:\tphylink = phylink_create(\u0026mac-\u003ephylink_config,\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c-4986-\t\t\t\t of_fwnode_handle(mac-\u003eof_node),\n--\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.c=746=struct net_device *fbnic_netdev_alloc(struct fbnic_dev *fbd)\n--\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.c-838-\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.c:839:\tif (fbnic_phylink_create(netdev)) {\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.c-840-\t\tfree_netdev(netdev);\n--\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.h=111=int fbnic_phylink_get_fecparam(struct net_device *netdev,\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.h-112-\t\t\t struct ethtool_fecparam *fecparam);\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.h:113:int fbnic_phylink_create(struct net_device *netdev);\ndrivers/net/ethernet/meta/fbnic/fbnic_netdev.h-114-void fbnic_phylink_destroy(struct net_device *netdev);\n--\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c=177=static const struct phylink_mac_ops fbnic_phylink_mac_ops = {\n--\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c-186-/**\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c:187: * fbnic_phylink_create - Phylink device creation\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c-188- * @netdev: Network Device struct to attach phylink device\n--\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c-196- **/\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c:197:int fbnic_phylink_create(struct net_device *netdev)\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c-198-{\n--\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c-231-\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c:232:\tphylink = phylink_create(\u0026fbn-\u003ephylink_config, NULL,\ndrivers/net/ethernet/meta/fbnic/fbnic_phylink.c-233-\t\t\t\t fbnic_phylink_select_interface(fbn-\u003eaui),\n--\ndrivers/net/ethernet/microchip/lan743x_main.c=3152=static const struct phylink_mac_ops lan743x_phylink_mac_ops = {\n--\ndrivers/net/ethernet/microchip/lan743x_main.c-3159-\ndrivers/net/ethernet/microchip/lan743x_main.c:3160:static int lan743x_phylink_create(struct lan743x_adapter *adapter)\ndrivers/net/ethernet/microchip/lan743x_main.c-3161-{\n--\ndrivers/net/ethernet/microchip/lan743x_main.c-3211-\ndrivers/net/ethernet/microchip/lan743x_main.c:3212:\tpl = phylink_create(\u0026adapter-\u003ephylink_config, NULL,\ndrivers/net/ethernet/microchip/lan743x_main.c-3213-\t\t\t adapter-\u003ephy_interface, \u0026lan743x_phylink_mac_ops);\n--\ndrivers/net/ethernet/microchip/lan743x_main.c=3691=static int lan743x_pcidev_probe(struct pci_dev *pdev,\n--\ndrivers/net/ethernet/microchip/lan743x_main.c-3750-\ndrivers/net/ethernet/microchip/lan743x_main.c:3751:\tret = lan743x_phylink_create(adapter);\ndrivers/net/ethernet/microchip/lan743x_main.c-3752-\tif (ret \u003c 0) {\n--\ndrivers/net/ethernet/microchip/lan966x/lan966x_main.c=801=static int lan966x_probe_port(struct lan966x *lan966x, u32 p,\n--\ndrivers/net/ethernet/microchip/lan966x/lan966x_main.c-866-\ndrivers/net/ethernet/microchip/lan966x/lan966x_main.c:867:\tphylink = phylink_create(\u0026port-\u003ephylink_config,\ndrivers/net/ethernet/microchip/lan966x/lan966x_main.c-868-\t\t\t\t portnp,\n--\ndrivers/net/ethernet/microchip/sparx5/sparx5_main.c=312=static int sparx5_create_port(struct sparx5 *sparx5,\n--\ndrivers/net/ethernet/microchip/sparx5/sparx5_main.c-388-\ndrivers/net/ethernet/microchip/sparx5/sparx5_main.c:389:\tphylink = phylink_create(\u0026spx5_port-\u003ephylink_config,\ndrivers/net/ethernet/microchip/sparx5/sparx5_main.c-390-\t\t\t\t of_fwnode_handle(config-\u003enode),\n--\ndrivers/net/ethernet/mscc/ocelot_net.c=1774=static const struct phylink_mac_ops ocelot_phylink_ops = {\n--\ndrivers/net/ethernet/mscc/ocelot_net.c-1779-\ndrivers/net/ethernet/mscc/ocelot_net.c:1780:static int ocelot_port_phylink_create(struct ocelot *ocelot, int port,\ndrivers/net/ethernet/mscc/ocelot_net.c-1781-\t\t\t\t struct device_node *portnp)\n--\ndrivers/net/ethernet/mscc/ocelot_net.c-1820-\ndrivers/net/ethernet/mscc/ocelot_net.c:1821:\tphylink = phylink_create(\u0026priv-\u003ephylink_config,\ndrivers/net/ethernet/mscc/ocelot_net.c-1822-\t\t\t\t of_fwnode_handle(portnp),\n--\ndrivers/net/ethernet/mscc/ocelot_net.c=1843=int ocelot_probe_port(struct ocelot *ocelot, int port, struct regmap *target,\n--\ndrivers/net/ethernet/mscc/ocelot_net.c-1879-\ndrivers/net/ethernet/mscc/ocelot_net.c:1880:\terr = ocelot_port_phylink_create(ocelot, port, portnp);\ndrivers/net/ethernet/mscc/ocelot_net.c-1881-\tif (err)\n--\ndrivers/net/ethernet/realtek/r8169_main.c=5945=static int rtl_init_phylink(struct rtl8169_private *tp)\n--\ndrivers/net/ethernet/realtek/r8169_main.c-6004-\ndrivers/net/ethernet/realtek/r8169_main.c:6005:\tpl = phylink_create(\u0026tp-\u003ephylink_config, tp_to_dev(tp)-\u003efwnode,\ndrivers/net/ethernet/realtek/r8169_main.c-6006-\t\t\t phy_mode, \u0026rtl_phylink_mac_ops);\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c=1405=static int stmmac_phylink_setup(struct stmmac_priv *priv)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-1496-\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c:1497:\tphylink = phylink_create(config, dev_fwnode(priv-\u003edevice),\ndrivers/net/ethernet/stmicro/stmmac/stmmac_main.c-1498-\t\t\t\t priv-\u003eplat-\u003ephy_interface,\n--\ndrivers/net/ethernet/tehuti/tn40_phy.c=45=int tn40_phy_register(struct tn40_priv *priv)\n--\ndrivers/net/ethernet/tehuti/tn40_phy.c-62-\ndrivers/net/ethernet/tehuti/tn40_phy.c:63:\tphylink = phylink_create(config, NULL, PHY_INTERFACE_MODE_XAUI,\ndrivers/net/ethernet/tehuti/tn40_phy.c-64-\t\t\t\t \u0026tn40_mac_ops);\n\n"
} |
| 5/2 | 2026/10/09 21:56 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 148227 output: 31 thoughts: 159 Thoughts: **Network Driver Thoughts** Okay, so I'm thinking about network drivers again. I see this path, `drivers/net/ethernet/realtek/r8169_main.c`, and my mind immediately jumps to the r8169. It's that workhorse Realtek PCIe NIC, and it's practically *everywhere*. Wait a minute, I'm thinking about QEMU! I wonder if it even *has* r8169 emulation? I know QEMU does the rtl8139. But what about that r8169? I should check... maybe via USB? Let's see... `drivers/net/usb/asix_devices.c:1`... `drivers/net/usb/lan78xx.c:1`... okay, USB is definitely a possibility here! I should take a closer look at both `lan78xx.c` and `asix_devices.c`. Now, let's see, what are the USB network drivers using? What about phylink, I should grep the USB drivers! |
| 6/2 | 2026/10/09 21:56 | tool | grepper |
0mArgs:{
"Expression": "phylink_create",
"PathPrefixes": [
"drivers/net/usb/"
]
}Results: {
"Output": "drivers/net/usb/asix_devices.c=799=static int ax88772_phylink_setup(struct usbnet *dev)\n--\ndrivers/net/usb/asix_devices.c-819-\ndrivers/net/usb/asix_devices.c:820:\tphylink = phylink_create(\u0026priv-\u003ephylink_config, dev-\u003enet-\u003edev.fwnode,\ndrivers/net/usb/asix_devices.c-821-\t\t\t\t phy_if_mode, \u0026ax88772_phylink_mac_ops);\n--\ndrivers/net/usb/lan78xx.c=2799=static int lan78xx_phylink_setup(struct lan78xx_net *dev)\n--\ndrivers/net/usb/lan78xx.c-2838-\ndrivers/net/usb/lan78xx.c:2839:\tphylink = phylink_create(pc, dev-\u003enet-\u003edev.fwnode,\ndrivers/net/usb/lan78xx.c-2840-\t\t\t\t dev-\u003einterface, \u0026lan78xx_phylink_mac_ops);\n"
} |
| 7/2 | 2026/10/09 21:56 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 148950 output: 30 thoughts: 92 Thoughts: Here's my thought process, as it stands: **Network Driver Investigation: Phylink and Potential Fuzzing Targets** Okay, so I'm thinking about network drivers and potential fuzzing targets. I recall that the `drivers/net/usb/asix_devices.c` and `lan78xx.c` drivers, both USB Ethernet adapters, utilize `phylink_create()`. That's interesting, as USB devices are often prime candidates for fuzzing via syzkaller's USB raw / gadget emulation. This sounds like a good lead! Then my mind drifts to the more common ethernet chip, `r8169` which is PCIe based. I am not seeing a direct path for fuzzing that particular driver. But wait a minute, DSA switches! Now, does DSA, the Distributed Switch Architecture, interact with `phylink`? That's the question I need to answer. Let me quickly check the `net/dsa/` directory to see how DSA handles its PHY interaction. This could open up a whole new avenue for fuzzing, and if DSA uses `phylink` in its architecture, that would give me another useful target! |
| 8/2 | 2026/10/09 21:56 | tool | grepper |
0mArgs:{
"Expression": "phylink_create",
"PathPrefixes": [
"net/dsa/"
]
}Results: {
"Output": "net/dsa/port.c=1611=static const struct phylink_mac_ops dsa_port_phylink_mac_ops = {\n--\nnet/dsa/port.c-1616-\nnet/dsa/port.c:1617:int dsa_port_phylink_create(struct dsa_port *dp)\nnet/dsa/port.c-1618-{\n--\nnet/dsa/port.c-1646-\nnet/dsa/port.c:1647:\tpl = phylink_create(\u0026dp-\u003epl_config, of_fwnode_handle(dp-\u003edn), mode,\nnet/dsa/port.c-1648-\t\t\t mac_ops);\n--\nnet/dsa/port.c=1665=static int dsa_shared_port_phylink_register(struct dsa_port *dp)\n--\nnet/dsa/port.c-1673-\nnet/dsa/port.c:1674:\terr = dsa_port_phylink_create(dp);\nnet/dsa/port.c-1675-\tif (err)\n--\nnet/dsa/port.h=100=int dsa_port_mrp_del_ring_role(const struct dsa_port *dp,\nnet/dsa/port.h-101-\t\t\t const struct switchdev_obj_ring_role_mrp *mrp);\nnet/dsa/port.h:102:int dsa_port_phylink_create(struct dsa_port *dp);\nnet/dsa/port.h-103-void dsa_port_phylink_destroy(struct dsa_port *dp);\n--\nnet/dsa/user.c=2654=static int dsa_user_phy_setup(struct net_device *user_dev)\n--\nnet/dsa/user.c-2673-\nnet/dsa/user.c:2674:\tret = dsa_port_phylink_create(dp);\nnet/dsa/user.c-2675-\tif (ret)\n"
} |
| 9/2 | 2026/10/09 21:56 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 149865 output: 38 thoughts: 640 Thoughts: **Analyzing Potential Phylink Vulnerabilities** Okay, so I'm diving into this `phylink` stuff, specifically trying to figure out if syzkaller can trigger anything interesting. The core of my thought process right now is around how `phylink` is being used, and if I can get a controlled environment (like a syzkaller VM) to poke at it. First off, I see that the `dsa_port_phylink_create()` function is involved in DSA user setup and shared ports. Then I remember that `virtio` and `loopback` don't use phylink, so no luck there. I need to focus on netdevices that *do* rely on it. I'm taking a careful look at this patch series. It seems to be adding a bunch of documentation (bindings, RST files, MAINTAINERS updates), and then there are the driver changes: an Airoha AN7581 SoC Ethernet MAC driver, an Airoha AN7581 PCS driver, a generic PCS subsystem, and updates to the `phylink` core. The updates in `phylink.c` are interesting. It looks like the patches are adding multiple PCS support, late PCS attach/hotplug via `register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb)`, dynamic updating of `pl->supported_interfaces`, `phylink_pcs_link_down()`, locking with `pl->state_mutex`, and `pcs_provider_notify()`. So, can syzkaller interact with `phylink` at all? I need to figure out how it's interacted with from userspace. `Phylink` seems to be managing network interface links, ethtool settings, SFP modules, PHY devices, net_device state transitions (like `dev_open`, `dev_close`, `dev_change_flags`), ethtool link ksettings (SIOCETHTOOL, ETHTOOL_MSG_LINKMODES_SET, ETHTOOL_MSG_LINKMODES_GET, etc.), and PHY netlink notifications. Right, syzkaller *can* interact with phylink through netdevices that use it! The key question now is which of these netdevices are available in a syzkaller VM (QEMU amd64)? Can I use mock, virtual, or "gadget" devices that use phylink? I need to know if the mock or dummy DSA setup creates DSA devices. And since I'm thinking of "gadget" netdevices, I know syzkaller can emulate USB devices via `syz_usb_connect`. The file `asix_devices.c` seems to have AX88772. I should check how this gets probed, because maybe I can use that and get something that interacts with `phylink`. I'll see how the AX88772 is probed in `drivers/net/usb/asix_devices.c`. |
| 10/2 | 2026/10/09 21:56 | tool | grepper |
0mArgs:{
"Expression": "ax88772_phylink_setup",
"PathPrefixes": [
"drivers/net/usb/"
]
}Results: {
"Output": "drivers/net/usb/asix_devices.c=793=static const struct phylink_mac_ops ax88772_phylink_mac_ops = {\n--\ndrivers/net/usb/asix_devices.c-798-\ndrivers/net/usb/asix_devices.c:799:static int ax88772_phylink_setup(struct usbnet *dev)\ndrivers/net/usb/asix_devices.c-800-{\n--\ndrivers/net/usb/asix_devices.c=829=static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)\n--\ndrivers/net/usb/asix_devices.c-920-\ndrivers/net/usb/asix_devices.c:921:\tret = ax88772_phylink_setup(dev);\ndrivers/net/usb/asix_devices.c-922-\tif (ret)\n"
} |
| 11/2 | 2026/10/09 21:56 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 151426 output: 36 thoughts: 51 Thoughts: Okay, here's my interpretation of that code snippet, presented as my internal thought process: **Network Driver Phylink Setup Thoughts** Right, so `ax88772_bind` is calling `ax88772_phylink_setup(dev)`. That's the expected driver binding sequence. So far, so good. That's how we're initiating the network interface setup when the device is detected. And then, looking at `lan78xx.c`, I see a corresponding `lan78xx_phylink_setup(dev)` routine there. Interesting. This confirms my expectation that these drivers are following a similar phylink-based approach. We can assume that the `phylink` setup is the general routine used for configuring the physical layer for these drivers. Makes sense that this pattern would be consistent between different USB Ethernet adapter drivers. It shows that `ax88772` and `lan78xx` and likely other similar drivers are using phylink, and that the phylink structure is likely consistent, too. |
| 12/2 | 2026/10/09 21:56 | tool | grepper |
0mArgs:{
"Expression": "lan78xx_phylink_setup",
"PathPrefixes": [
"drivers/net/usb/"
]
}Results: {
"Output": "drivers/net/usb/lan78xx.c=2769=static int lan78xx_configure_leds_from_dt(struct lan78xx_net *dev,\n--\ndrivers/net/usb/lan78xx.c-2798-\ndrivers/net/usb/lan78xx.c:2799:static int lan78xx_phylink_setup(struct lan78xx_net *dev)\ndrivers/net/usb/lan78xx.c-2800-{\n--\ndrivers/net/usb/lan78xx.c=2858=static int lan78xx_phy_init(struct lan78xx_net *dev)\n--\ndrivers/net/usb/lan78xx.c-2870-\ndrivers/net/usb/lan78xx.c:2871:\tret = lan78xx_phylink_setup(dev);\ndrivers/net/usb/lan78xx.c-2872-\tif (ret \u003c 0)\n"
} |
| 13/2 | 2026/10/09 21:56 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 152001 output: 41 thoughts: 570 Thoughts: **My Analysis of USB Ethernet Driver Interactions with the PHY and PCS Framework** Okay, so I'm diving into how these USB ethernet drivers, specifically `ax88772` and `lan78xx`, interact with the system when syzkaller is using its USB fuzzing capabilities. I see that syzkaller can connect devices matching these drivers—devices like those with vendor 0x0b95, product 0x7720 for `ax88772`, and Microchip LAN78xx for `lan78xx`. That's standard behavior. What's interesting is how it probes them, creates a netdevice, uses `phylink_create`, runs `phylink_start`, `phylink_stop`, `phylink_destroy`, and then throws some ethtool ioctls at it. Standard testing and driver lifecycle stuff here, but this interaction is the key. Now, I'm thinking about other network drivers and how they fit in. Let's see if `r8169` is used in QEMU. QEMU uses the RTL8139. Quick check with `qemu-system-x86_64 -device help | grep -i r8169` or `rtl8139` confirms QEMU's RTL8139 is the PCI device 10ec:8139, handled by the `8139too` or `8139cp` driver. No real surprise there, but the main point is that USB devices like asix and lan78xx are definitely software-emulated devices in syzkaller. But let's shift gears and look at the new PCS framework and `phylink` changes more closely. I need to understand what's changed. Specifically, I'm going to look at the differences in `drivers/net/phy/phylink.c`. Okay, the diff in `phylink.c` reveals several important additions in `struct phylink`. We've got `struct fwnode_handle *fwnode;`, `struct list_head pcs_list;`, `struct notifier_block fwnode_pcs_nb;`, and `DECLARE_PHY_INTERFACE_MASK(supported_interfaces);`. All related to PCS interaction and framework support. We also have this new `phylink_validate_pcs_interface` function. Then there's `phylink_validate_mac_and_pcs`. Ah, this is important. They added locking with `mutex_lock(&pl->state_mutex);` and unlocking, which is across pcs selection. This means that we're dealing with concurrent access! We need to make sure this is done correctly. Wait a second. I just realized that `phylink_validate_mac_and_pcs` *holds* `pl->state_mutex` now! This could be a potential race condition! Is `state_mutex` already held by any callers of `phylink_validate_mac_and_pcs`? I've got to check where `phylink_validate_mac_and_pcs` is called! |
| 14/2 | 2026/10/09 21:56 | tool | grepper |
0mArgs:{
"Expression": "phylink_validate_mac_and_pcs",
"PathPrefixes": [
"drivers/net/phy/phylink.c"
]
}Results: {
"Output": "drivers/net/phy/phylink.c=526=static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,\n--\ndrivers/net/phy/phylink.c-541-\ndrivers/net/phy/phylink.c:542:static int phylink_validate_mac_and_pcs(struct phylink *pl,\ndrivers/net/phy/phylink.c-543-\t\t\t\t\tunsigned long *supported,\n--\ndrivers/net/phy/phylink.c=628=static void phylink_validate_one(struct phylink *pl, struct phy_device *phy,\n--\ndrivers/net/phy/phylink.c-645-\ndrivers/net/phy/phylink.c:646:\tif (!phylink_validate_mac_and_pcs(pl, tmp_supported, \u0026tmp_state)) {\ndrivers/net/phy/phylink.c-647-\t\tphylink_dbg(pl, \" interface %u (%s) rate match %s supports %*pbl\\n\",\n--\ndrivers/net/phy/phylink.c=677=static int phylink_validate(struct phylink *pl, unsigned long *supported,\n--\ndrivers/net/phy/phylink.c-688-\ndrivers/net/phy/phylink.c:689:\treturn phylink_validate_mac_and_pcs(pl, supported, state);\ndrivers/net/phy/phylink.c-690-}\n"
} |
| 15/2 | 2026/10/09 21:56 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 153655 output: 34 thoughts: 75 Thoughts: Here's my thought process, as requested: **Debugging PHYLINK Locking** Okay, I need to get to the bottom of some potential locking issues within the PHYLINK subsystem. First things first, I need to understand how the `phylink_validate()` and `phylink_validate_one()` functions are interacting with the `pl->state_mutex`. I'm especially concerned about potential deadlocks or lockdep problems. My gut feeling is that these functions, or the call paths they take, might be mishandling the mutex. To dig in, I'm going to track all references to either the function or mutex, making sure to track the call stack for each of them. My immediate plan is to search the `drivers/net/phy/phylink.c` file for instances of `state_mutex`. That should give me a good starting point for mapping out the locking behavior. From there, I can analyze the code more carefully to determine if there is a path to a deadlock. |
| 16/2 | 2026/10/09 21:56 | tool | grepper |
0mArgs:{
"Expression": "state_mutex",
"PathPrefixes": [
"drivers/net/phy/phylink.c"
]
}Results: {
"Output": "\nFull output is too long, showing 200 out of 215 lines.\nUse more precise expression or PathPrefixes if possible.\n\nNumber of matching lines per file (1 files in total):\ndrivers/net/phy/phylink.c:47\n\ndrivers/net/phy/phylink.c=42=struct phylink {\n--\ndrivers/net/phy/phylink.c-80-\ndrivers/net/phy/phylink.c:81:\tstruct mutex state_mutex;\ndrivers/net/phy/phylink.c-82-\t/* Serialize updates to pl-\u003ephydev with phylink_resolve() */\n--\ndrivers/net/phy/phylink.c=542=static int phylink_validate_mac_and_pcs(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-549-\ndrivers/net/phy/phylink.c:550:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-551-\n--\ndrivers/net/phy/phylink.c-555-\t\tif (IS_ERR(pcs)) {\ndrivers/net/phy/phylink.c:556:\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-557-\t\t\treturn PTR_ERR(pcs);\n--\ndrivers/net/phy/phylink.c-581-\t\tif (!pcs-\u003eops) {\ndrivers/net/phy/phylink.c:582:\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-583-\t\t\tphylink_err(pl, \"interface %s: uninitialised PCS\\n\",\n--\ndrivers/net/phy/phylink.c-591-\t\tif (ret) {\ndrivers/net/phy/phylink.c:592:\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-593-\t\t\tphylink_err(pl, \"selected PCS does not support %s\\n\",\n--\ndrivers/net/phy/phylink.c-601-\t\t\tif (ret \u003c 0 || phylink_is_empty_linkmode(supported)) {\ndrivers/net/phy/phylink.c:602:\t\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-603-\t\t\t\treturn -EINVAL;\n--\ndrivers/net/phy/phylink.c-613-\ndrivers/net/phy/phylink.c:614:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-615-\n--\ndrivers/net/phy/phylink.c=1013=static unsigned int phylink_inband_caps(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-1018-\ndrivers/net/phy/phylink.c:1019:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-1020-\n--\ndrivers/net/phy/phylink.c-1040-exit:\ndrivers/net/phy/phylink.c:1041:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-1042-\n--\ndrivers/net/phy/phylink.c=1555=static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)\n--\ndrivers/net/phy/phylink.c-1583-\t\tmutex_lock(\u0026phy-\u003elock);\ndrivers/net/phy/phylink.c:1584:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-1585-\tphylink_major_config(pl, force_restart, \u0026link_state);\ndrivers/net/phy/phylink.c:1586:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-1587-\tif (phy)\n--\ndrivers/net/phy/phylink.c=1721=static void phylink_resolve(struct work_struct *w)\n--\ndrivers/net/phy/phylink.c-1733-\t\tmutex_lock(\u0026phy-\u003elock);\ndrivers/net/phy/phylink.c:1734:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-1735-\tcur_link_state = phylink_link_is_up(pl);\n--\ndrivers/net/phy/phylink.c-1835-\t}\ndrivers/net/phy/phylink.c:1836:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-1837-\tif (phy)\n--\ndrivers/net/phy/phylink.c=1940=static bool phylink_add_pcs(struct phylink *pl, struct phylink_pcs *pcs)\n--\ndrivers/net/phy/phylink.c-1948-\t */\ndrivers/net/phy/phylink.c:1949:\tlockdep_assert_held(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-1950-\n--\ndrivers/net/phy/phylink.c=1964=static int phylink_fill_available_pcs(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-1982-\ndrivers/net/phy/phylink.c:1983:\t/* Lock state_mutex while filling to handle PCS notify */\ndrivers/net/phy/phylink.c:1984:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-1985-\n--\ndrivers/net/phy/phylink.c-1999-out:\ndrivers/net/phy/phylink.c:2000:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2001-\n--\ndrivers/net/phy/phylink.c=2007=static void phylink_del_pcs(struct phylink *pl, struct phylink_pcs *pcs)\ndrivers/net/phy/phylink.c-2008-{\ndrivers/net/phy/phylink.c:2009:\tlockdep_assert_held(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2010-\n--\ndrivers/net/phy/phylink.c=2035=static int pcs_provider_notify(struct notifier_block *self,\n--\ndrivers/net/phy/phylink.c-2045-\ndrivers/net/phy/phylink.c:2046:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2047-\n--\ndrivers/net/phy/phylink.c-2082-\tif (!resolve) {\ndrivers/net/phy/phylink.c:2083:\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2084-\n--\ndrivers/net/phy/phylink.c-2097-\ndrivers/net/phy/phylink.c:2098:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2099-\n--\ndrivers/net/phy/phylink.c=2120=static void phylink_update_pause_state(struct phylink *pl, int pause_state)\n--\ndrivers/net/phy/phylink.c-2126-\ndrivers/net/phy/phylink.c:2127:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2128-\n--\ndrivers/net/phy/phylink.c-2156-\ndrivers/net/phy/phylink.c:2157:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2158-\n--\ndrivers/net/phy/phylink.c=2186=void phylink_update_mac_pause_capabilities(struct phylink *pl, unsigned long mac_pause)\n--\ndrivers/net/phy/phylink.c-2202-\ndrivers/net/phy/phylink.c:2203:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2204-\n--\ndrivers/net/phy/phylink.c-2226-\ndrivers/net/phy/phylink.c:2227:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2228-\n--\ndrivers/net/phy/phylink.c=2249=struct phylink *phylink_create(struct phylink_config *config,\n--\ndrivers/net/phy/phylink.c-2279-\tmutex_init(\u0026pl-\u003ephydev_mutex);\ndrivers/net/phy/phylink.c:2280:\tmutex_init(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2281-\tINIT_WORK(\u0026pl-\u003eresolve, phylink_resolve);\n--\ndrivers/net/phy/phylink.c-2331-\ndrivers/net/phy/phylink.c:2332:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2333-\n--\ndrivers/net/phy/phylink.c-2342-\ndrivers/net/phy/phylink.c:2343:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2344-\n--\ndrivers/net/phy/phylink.c-2374-\tcancel_work_sync(\u0026pl-\u003eresolve);\ndrivers/net/phy/phylink.c:2375:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2376-\tlist_for_each_entry_safe(pcs, tmp, \u0026pl-\u003epcs_list, list) {\n--\ndrivers/net/phy/phylink.c-2379-\t}\ndrivers/net/phy/phylink.c:2380:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2381-free_pl:\n--\ndrivers/net/phy/phylink.c=2397=void phylink_destroy(struct phylink *pl)\n--\ndrivers/net/phy/phylink.c-2410-\ndrivers/net/phy/phylink.c:2411:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2412-\n--\ndrivers/net/phy/phylink.c-2418-\ndrivers/net/phy/phylink.c:2419:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2420-\n--\ndrivers/net/phy/phylink.c=2444=static void phylink_phy_change(struct phy_device *phydev, bool up)\n--\ndrivers/net/phy/phylink.c-2450-\ndrivers/net/phy/phylink.c:2451:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2452-\tpl-\u003ephy_state.speed = phydev-\u003espeed;\n--\ndrivers/net/phy/phylink.c-2467-\tpl-\u003emac_tx_lpi_timer = phydev-\u003eeee_cfg.tx_lpi_timer;\ndrivers/net/phy/phylink.c:2468:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2469-\n--\ndrivers/net/phy/phylink.c=2555=static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,\n--\ndrivers/net/phy/phylink.c-2597-\tmutex_lock(\u0026phy-\u003elock);\ndrivers/net/phy/phylink.c:2598:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2599-\tpl-\u003ephy_state.interface = interface;\n--\ndrivers/net/phy/phylink.c-2638-\ndrivers/net/phy/phylink.c:2639:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2640-\tmutex_unlock(\u0026phy-\u003elock);\n--\ndrivers/net/phy/phylink.c-2673-\tmutex_lock(\u0026phy-\u003elock);\ndrivers/net/phy/phylink.c:2674:\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2675-\tpl-\u003ephydev = phy;\ndrivers/net/phy/phylink.c:2676:\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2677-\tmutex_unlock(\u0026phy-\u003elock);\n--\ndrivers/net/phy/phylink.c=2825=void phylink_disconnect_phy(struct phylink *pl)\n--\ndrivers/net/phy/phylink.c-2834-\t\tmutex_lock(\u0026phy-\u003elock);\ndrivers/net/phy/phylink.c:2835:\t\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2836-\t\tpl-\u003ephydev = NULL;\n--\ndrivers/net/phy/phylink.c-2838-\t\tpl-\u003emac_tx_clk_stop = false;\ndrivers/net/phy/phylink.c:2839:\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-2840-\t\tmutex_unlock(\u0026phy-\u003elock);\n--\ndrivers/net/phy/phylink.c=3101=void phylink_suspend(struct phylink *pl, bool mac_wol)\n--\ndrivers/net/phy/phylink.c-3109-\t\t/* Wake-on-Lan enabled, MAC handling */\ndrivers/net/phy/phylink.c:3110:\t\tmutex_lock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-3111-\n--\ndrivers/net/phy/phylink.c-3128-\t\t */\ndrivers/net/phy/phylink.c:3129:\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\ndrivers/net/phy/phylink.c-3130-\t} else {\n--\ndrivers/net/phy/phylink.c=3171=void phylink_resume(struct phylink *pl)\n--\ndrivers/net/phy/phylink.c-3182-\t\t\t/* Call mac_link_down() so we keep the overall state\ndrivers/net/phy/phylink.c:3183:\t\t\t * balanced. Do this under the state_mutex lock for\ndrivers/net/phy/phylink.c-3184-\t\t\t * consistency. This will cause a \"Link Down\" message\n--\n\n"
} |
| 17/2 | 2026/10/09 21:57 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 157800 output: 37 thoughts: 557 Thoughts: **Potential Race Condition in Phylink Validation** Okay, here's what I'm seeing. I'm focusing on this `pcs_provider_notify()` function, specifically line 2045. I notice this `pl->state_mutex` is involved, which makes me pay attention. Then I see on line 2102, a call to `phylink_validate_mask`, *after* the `pl->state_mutex` is unlocked. That's a little concerning on its own, I'm always very careful about the locking/unlocking order. Now, I need to understand what `phylink_validate_mask` does. It appears that `phylink_validate_mask` calls `phylink_validate_one()`, and *that* calls `phylink_validate_mac_and_pcs()`. And now I see the problem - `phylink_validate_mac_and_pcs()` *re-acquires* `pl->state_mutex`! That's a definite red flag. My primary concern now is this potential for a double lock. If `phylink_validate_mac_and_pcs()` is called from a context where `pl->state_mutex` is already held, we've got a race condition. This could lead to a deadlock. So the next thing I'm checking is if `phylink_resolve` holds the mutex when it calls `phylink_validate_mac_and_pcs`! Line 1734 shows that `phylink_resolve()` does indeed lock `pl->state_mutex` itself. I need to now check if `phylink_resolve()` calls something that calls `phylink_validate_mac_and_pcs()`, because that would be a problem. |
| 18/2 | 2026/10/09 21:57 | tool | grepper |
0mArgs:{
"Expression": "static void phylink_resolve",
"PathPrefixes": [
"drivers/net/phy/phylink.c"
]
}Results: {
"Output": "drivers/net/phy/phylink.c=902=static void phylink_apply_manual_flow(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-914-\ndrivers/net/phy/phylink.c:915:static void phylink_resolve_an_pause(struct phylink_link_state *state)\ndrivers/net/phy/phylink.c-916-{\n--\ndrivers/net/phy/phylink.c=1716=static bool phylink_link_is_up(struct phylink *pl)\n--\ndrivers/net/phy/phylink.c-1720-\ndrivers/net/phy/phylink.c:1721:static void phylink_resolve(struct work_struct *w)\ndrivers/net/phy/phylink.c-1722-{\n"
} |
| 19/2 | 2026/10/09 21:57 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 158992 output: 40 thoughts: 28 Thoughts: Okay, let's dive into this. Here's my thought process on tackling `phylink_resolve()`: **Analyzing `phylink_resolve()` (Lines 1720-1840)** Alright, so I need to understand what's happening within `phylink_resolve()`. My immediate plan is to use `read-file` and zero in on the specific lines we're interested in, around 1720 to 1840. That should give me a good, focused view of the relevant code section without the surrounding context cluttering my mental model. From there, I'll need to rapidly parse the logic: identify the inputs, the critical internal data structures being used and the control flow involved. I will then seek to understand the intended behavior of the function, and hopefully discover some patterns. My brain will then hopefully form an initial hypothesis regarding its primary purpose and contribution to the overall system. From there I can assess whether a deeper dive is warranted based on initial understanding. |
| 20/2 | 2026/10/09 21:57 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 1721,
"LineCount": 100
}Results: {
"Contents": "1721:\tstatic void phylink_resolve(struct work_struct *w)\n1722:\t{\n1723:\t\tstruct phylink *pl = container_of(w, struct phylink, resolve);\n1724:\t\tstruct phylink_link_state link_state;\n1725:\t\tbool mac_config = false;\n1726:\t\tbool retrigger = false;\n1727:\t\tstruct phy_device *phy;\n1728:\t\tbool cur_link_state;\n1729:\t\n1730:\t\tmutex_lock(\u0026pl-\u003ephydev_mutex);\n1731:\t\tphy = pl-\u003ephydev;\n1732:\t\tif (phy)\n1733:\t\t\tmutex_lock(\u0026phy-\u003elock);\n1734:\t\tmutex_lock(\u0026pl-\u003estate_mutex);\n1735:\t\tcur_link_state = phylink_link_is_up(pl);\n1736:\t\n1737:\t\tif (pl-\u003ephylink_disable_state) {\n1738:\t\t\tpl-\u003elink_failed = false;\n1739:\t\t\tlink_state = pl-\u003elink_config;\n1740:\t\t\tlink_state.link = false;\n1741:\t\t} else if (pl-\u003elink_failed) {\n1742:\t\t\tlink_state = pl-\u003elink_config;\n1743:\t\t\tlink_state.link = false;\n1744:\t\t\tretrigger = true;\n1745:\t\t} else if (pl-\u003eact_link_an_mode == MLO_AN_FIXED) {\n1746:\t\t\tphylink_get_fixed_state(pl, \u0026link_state);\n1747:\t\t\tmac_config = link_state.link;\n1748:\t\t} else if (pl-\u003eact_link_an_mode == MLO_AN_PHY) {\n1749:\t\t\tlink_state = pl-\u003ephy_state;\n1750:\t\t\tmac_config = link_state.link;\n1751:\t\t} else {\n1752:\t\t\tphylink_mac_pcs_get_state(pl, \u0026link_state);\n1753:\t\n1754:\t\t\t/* The PCS may have a latching link-fail indicator. If the link\n1755:\t\t\t * was up, bring the link down and re-trigger the resolve.\n1756:\t\t\t * Otherwise, re-read the PCS state to get the current status\n1757:\t\t\t * of the link.\n1758:\t\t\t */\n1759:\t\t\tif (!link_state.link) {\n1760:\t\t\t\tif (cur_link_state)\n1761:\t\t\t\t\tretrigger = true;\n1762:\t\t\t\telse\n1763:\t\t\t\t\tphylink_mac_pcs_get_state(pl, \u0026link_state);\n1764:\t\t\t}\n1765:\t\n1766:\t\t\t/* If we have a phy, the \"up\" state is the union of both the\n1767:\t\t\t * PHY and the MAC\n1768:\t\t\t */\n1769:\t\t\tif (phy)\n1770:\t\t\t\tlink_state.link \u0026= pl-\u003ephy_state.link;\n1771:\t\n1772:\t\t\t/* Only update if the PHY link is up */\n1773:\t\t\tif (phy \u0026\u0026 pl-\u003ephy_state.link) {\n1774:\t\t\t\t/* If the interface has changed, force a link down\n1775:\t\t\t\t * event if the link isn't already down, and re-resolve.\n1776:\t\t\t\t */\n1777:\t\t\t\tif (link_state.interface != pl-\u003ephy_state.interface) {\n1778:\t\t\t\t\tretrigger = true;\n1779:\t\t\t\t\tlink_state.link = false;\n1780:\t\t\t\t}\n1781:\t\n1782:\t\t\t\tlink_state.interface = pl-\u003ephy_state.interface;\n1783:\t\n1784:\t\t\t\t/* If we are doing rate matching, then the link\n1785:\t\t\t\t * speed/duplex comes from the PHY\n1786:\t\t\t\t */\n1787:\t\t\t\tif (pl-\u003ephy_state.rate_matching) {\n1788:\t\t\t\t\tlink_state.rate_matching =\n1789:\t\t\t\t\t\tpl-\u003ephy_state.rate_matching;\n1790:\t\t\t\t\tlink_state.speed = pl-\u003ephy_state.speed;\n1791:\t\t\t\t\tlink_state.duplex = pl-\u003ephy_state.duplex;\n1792:\t\t\t\t}\n1793:\t\n1794:\t\t\t\t/* If we have a PHY, we need to update with the PHY\n1795:\t\t\t\t * flow control bits.\n1796:\t\t\t\t */\n1797:\t\t\t\tlink_state.pause = pl-\u003ephy_state.pause;\n1798:\t\t\t\tmac_config = true;\n1799:\t\t\t}\n1800:\t\t}\n1801:\t\n1802:\t\tif (pl-\u003eact_link_an_mode != MLO_AN_FIXED)\n1803:\t\t\tphylink_apply_manual_flow(pl, \u0026link_state);\n1804:\t\n1805:\t\tif ((mac_config \u0026\u0026 link_state.interface != pl-\u003elink_config.interface) ||\n1806:\t\t pl-\u003eforce_major_config) {\n1807:\t\t\t/* The interface has changed or a forced major configuration\n1808:\t\t\t * was requested, so force the link down and then reconfigure.\n1809:\t\t\t */\n1810:\t\t\tif (cur_link_state) {\n1811:\t\t\t\tphylink_link_down(pl);\n1812:\t\t\t\tcur_link_state = false;\n1813:\t\t\t}\n1814:\t\t\tphylink_major_config(pl, false, \u0026link_state);\n1815:\t\t\tpl-\u003elink_config.interface = link_state.interface;\n1816:\t\t\tpl-\u003eforce_major_config = false;\n1817:\t\t}\n1818:\t\n1819:\t\t/* If configuration of the interface failed, force the link down\n1820:\t\t * until we get a successful configuration.\n"
} |
| 21/2 | 2026/10/09 21:57 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 160834 output: 39 thoughts: 183 Thoughts: Okay, here's my breakdown of what's going on, thinking through this code: **Analyzing the phylink Configuration Process** Alright, let's dive into this `phylink_major_config` function. I'm focusing on line 1814, but need to understand its context. It's immediately clear that `phylink_major_config` is being called with `pl` (presumably a phylink instance), `false` for `force_restart`, and a pointer to `link_state`. The interesting part is what are the arguments of the call? I need to quickly check the callers. Lines 1480 and 1584 are calling `phylink_major_config`, within the `phylink_mac_initial_config` function. This function clearly handles initial configuration. I'm seeing that the `phylink_major_config` function is being called with `force_restart` as an argument that we passed as `false` in this line. Furthermore, I note the mutex locking and unlocking around the `phylink_major_config` call. It looks like `pl->state_mutex` and possibly `phy->lock` are being used for synchronization, which is good practice. This is pretty standard for managing shared resources in a multi-threaded environment. I'm noting the locking and unlocking to ensure proper concurrency management, which is critical in this context. Now, I'll need to go deeper. The heart of the matter is what `phylink_major_config` *itself* does. I need to understand how `force_restart` and `link_state` interact with the phylink instance during configuration. That's the key to understanding the overall initialization and operation. I'll need to examine that function's implementation directly to get the full picture. |
| 22/2 | 2026/10/09 21:57 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 1330,
"LineCount": 80
}Results: {
"Contents": "1330:\t\t\t\t\t \"mac_select_pcs unexpectedly failed: %pe\\n\",\n1331:\t\t\t\t\t pcs);\n1332:\t\n1333:\t\t\t\tpl-\u003emajor_config_failed = true;\n1334:\t\t\t\treturn;\n1335:\t\t\t}\n1336:\t\t/* Find a PCS in available PCS list for the requested interface.\n1337:\t\t * This doesn't overwrite the previous .mac_select_pcs as either\n1338:\t\t * .mac_select_pcs or PCS list implementation are permitted.\n1339:\t\t *\n1340:\t\t * Skip searching if the MAC doesn't require a dedicated PCS for\n1341:\t\t * the requested interface.\n1342:\t\t */\n1343:\t\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\n1344:\t\t\tstruct phylink_pcs *tmp;\n1345:\t\n1346:\t\t\tlist_for_each_entry(tmp, \u0026pl-\u003epcs_list, list) {\n1347:\t\t\t\tif (!phylink_validate_pcs_interface(tmp,\n1348:\t\t\t\t\t\t\t\t state-\u003einterface)) {\n1349:\t\t\t\t\tpcs = tmp;\n1350:\t\t\t\t\tbreak;\n1351:\t\t\t\t}\n1352:\t\t\t}\n1353:\t\n1354:\t\t\tif (!pcs) {\n1355:\t\t\t\tphylink_err(pl,\n1356:\t\t\t\t\t \"couldn't find a PCS for %s\\n\",\n1357:\t\t\t\t\t phy_modes(state-\u003einterface));\n1358:\t\n1359:\t\t\t\tpl-\u003emajor_config_failed = true;\n1360:\t\t\t\treturn;\n1361:\t\t\t}\n1362:\t\t}\n1363:\t\n1364:\t\tpcs_changed = pl-\u003epcs != pcs;\n1365:\t\n1366:\t\tphylink_pcs_neg_mode(pl, pcs, state-\u003einterface, state-\u003eadvertising);\n1367:\t\n1368:\t\tphylink_dbg(pl, \"major config, active %s/%s/%s\\n\",\n1369:\t\t\t phylink_an_mode_str(pl-\u003eact_link_an_mode),\n1370:\t\t\t phylink_pcs_mode_str(pl-\u003epcs_neg_mode),\n1371:\t\t\t phy_modes(state-\u003einterface));\n1372:\t\n1373:\t\tphylink_pcs_poll_stop(pl);\n1374:\t\n1375:\t\tif (pl-\u003emac_ops-\u003emac_prepare) {\n1376:\t\t\terr = pl-\u003emac_ops-\u003emac_prepare(pl-\u003econfig, pl-\u003eact_link_an_mode,\n1377:\t\t\t\t\t\t state-\u003einterface);\n1378:\t\t\tif (err \u003c 0) {\n1379:\t\t\t\tphylink_err(pl, \"mac_prepare failed: %pe\\n\",\n1380:\t\t\t\t\t ERR_PTR(err));\n1381:\t\t\t\tpl-\u003emajor_config_failed = true;\n1382:\t\t\t\treturn;\n1383:\t\t\t}\n1384:\t\t}\n1385:\t\n1386:\t\t/* If we have a new PCS, switch to the new PCS after preparing the MAC\n1387:\t\t * for the change.\n1388:\t\t */\n1389:\t\tif (pcs_changed) {\n1390:\t\t\tphylink_pcs_disable(pl-\u003epcs);\n1391:\t\n1392:\t\t\tif (pl-\u003emac_ops-\u003emac_select_pcs) {\n1393:\t\t\t\tif (pl-\u003epcs)\n1394:\t\t\t\t\tpl-\u003epcs-\u003ephylink = NULL;\n1395:\t\n1396:\t\t\t\tif (pcs)\n1397:\t\t\t\t\tpcs-\u003ephylink = pl;\n1398:\t\t\t}\n1399:\t\n1400:\t\t\tWRITE_ONCE(pl-\u003epcs, pcs);\n1401:\t\t}\n1402:\t\n1403:\t\tif (pl-\u003epcs)\n1404:\t\t\tphylink_pcs_pre_config(pl-\u003epcs, state-\u003einterface);\n1405:\t\n1406:\t\tphylink_mac_config(pl, state);\n1407:\t\n1408:\t\tif (pl-\u003epcs) {\n1409:\t\t\terr = phylink_pcs_post_config(pl-\u003epcs, state-\u003einterface);\n"
} |
| 23/2 | 2026/10/09 21:57 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 162595 output: 36 thoughts: 97 Thoughts: **Investigating the Configuration Validation Flow** Okay, let's dive in. My immediate question is whether `phylink_major_config` leverages `phylink_validate_mac_and_pcs` during its execution. I need to understand the configuration validation flow, so this is a crucial point. A quick search... nope, it doesn't appear that `phylink_major_config` directly calls that function. Hmm, that's interesting. So, if `phylink_major_config` doesn't validate the MAC and PCS settings specifically through this particular function, then who does? I need to understand which parts of the system *do* call `phylink_validate_mac_and_pcs` and also `phylink_validate`, because it's probably related. Time to check the call graph for both of those validation functions and trace where they fit within the overall system design. Let's see who's invoking them. I need to trace the data flow. |
| 24/2 | 2026/10/09 21:57 | tool | grepper |
0mArgs:{
"Expression": "phylink_validate\\(",
"PathPrefixes": [
"drivers/net/phy/phylink.c"
]
}Results: {
"Output": "drivers/net/phy/phylink.c=658=static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,\n--\ndrivers/net/phy/phylink.c-676-\ndrivers/net/phy/phylink.c:677:static int phylink_validate(struct phylink *pl, unsigned long *supported,\ndrivers/net/phy/phylink.c-678-\t\t\t struct phylink_link_state *state)\n--\ndrivers/net/phy/phylink.c=708=static int phylink_parse_fixedlink(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-788-\tlinkmode_copy(pl-\u003elink_config.advertising, pl-\u003esupported);\ndrivers/net/phy/phylink.c:789:\tphylink_validate(pl, pl-\u003esupported, \u0026pl-\u003elink_config);\ndrivers/net/phy/phylink.c-790-\n--\ndrivers/net/phy/phylink.c=822=static int phylink_parse_mode(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-891-\ndrivers/net/phy/phylink.c:892:\t\tif (phylink_validate(pl, pl-\u003esupported, \u0026pl-\u003elink_config)) {\ndrivers/net/phy/phylink.c-893-\t\t\tphylink_err(pl,\n--\ndrivers/net/phy/phylink.c=2186=void phylink_update_mac_pause_capabilities(struct phylink *pl, unsigned long mac_pause)\n--\ndrivers/net/phy/phylink.c-2215-\ndrivers/net/phy/phylink.c:2216:\tphylink_validate(pl, pl-\u003esupported, config);\ndrivers/net/phy/phylink.c-2217-\n--\ndrivers/net/phy/phylink.c=2249=struct phylink *phylink_create(struct phylink_config *config,\n--\ndrivers/net/phy/phylink.c-2346-\tlinkmode_copy(pl-\u003elink_config.advertising, pl-\u003esupported);\ndrivers/net/phy/phylink.c:2347:\tphylink_validate(pl, pl-\u003esupported, \u0026pl-\u003elink_config);\ndrivers/net/phy/phylink.c-2348-\n--\ndrivers/net/phy/phylink.c=2482=static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,\n--\ndrivers/net/phy/phylink.c-2551-\ndrivers/net/phy/phylink.c:2552:\treturn phylink_validate(pl, supported, state);\ndrivers/net/phy/phylink.c-2553-}\n--\ndrivers/net/phy/phylink.c=3467=int phylink_ethtool_ksettings_set(struct phylink *pl,\n--\ndrivers/net/phy/phylink.c-3577-\t\tlinkmode_copy(support, pl-\u003esupported);\ndrivers/net/phy/phylink.c:3578:\t\tif (phylink_validate(pl, support, \u0026config)) {\ndrivers/net/phy/phylink.c-3579-\t\t\tphylink_err(pl, \"validation of %s/%s with support %*pb failed\\n\",\n--\ndrivers/net/phy/phylink.c-3587-\t\tlinkmode_copy(support, pl-\u003esupported);\ndrivers/net/phy/phylink.c:3588:\t\tif (phylink_validate(pl, support, \u0026config))\ndrivers/net/phy/phylink.c-3589-\t\t\treturn -EINVAL;\n--\ndrivers/net/phy/phylink.c=4141=static int phylink_sfp_config_phy(struct phylink *pl, struct phy_device *phy)\n--\ndrivers/net/phy/phylink.c-4158-\t/* Ignore errors if we're expecting a PHY to attach later */\ndrivers/net/phy/phylink.c:4159:\tret = phylink_validate(pl, support, \u0026config);\ndrivers/net/phy/phylink.c-4160-\tif (ret) {\n--\ndrivers/net/phy/phylink.c=4192=static int phylink_sfp_config_optical(struct phylink *pl)\n--\ndrivers/net/phy/phylink.c-4268-\t/* Ignore errors if we're expecting a PHY to attach later */\ndrivers/net/phy/phylink.c:4269:\tret = phylink_validate(pl, support, \u0026config);\ndrivers/net/phy/phylink.c-4270-\tif (ret) {\n"
} |
| 25/2 | 2026/10/09 21:57 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 164131 output: 39 thoughts: 52 Thoughts: Here's my summary, as though I'm thinking through it: **Diving into the PHY Link Update** Okay, the task at hand… I need to understand this `phylink_update_mac_pause_capabilities` function. Let's pinpoint that specific line in the `drivers/net/phy/phylink.c` file – ah, there it is: line 2186. Right, let's take a look at lines 2186 through 2230. That block should give me the core logic of what's happening. I expect this function deals with communicating the link's pause capabilities to the MAC layer, making sure everything is properly negotiated for flow control. The function probably evaluates the PHY's advertised capabilities and then sets the appropriate registers or structures to inform the MAC. I'm keen to see if it's handling any edge cases or specific vendor nuances. I'll be looking for things like mutexes or spinlocks for concurrent access and how it handles potential errors. Let's see... |
| 26/2 | 2026/10/09 21:57 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 2186,
"LineCount": 50
}Results: {
"Contents": "2186:\tvoid phylink_update_mac_pause_capabilities(struct phylink *pl, unsigned long mac_pause)\n2187:\t{\n2188:\t\tstruct phylink_link_state *config = \u0026pl-\u003elink_config;\n2189:\t\tunsigned long old_pause;\n2190:\t\tint pause_state;\n2191:\t\n2192:\t\tASSERT_RTNL();\n2193:\t\n2194:\t\tif (mac_pause \u0026 ~(MAC_SYM_PAUSE | MAC_ASYM_PAUSE)) {\n2195:\t\t\tphylink_err(pl, \"Attempted to dynamically change non-pause MAC capabilities\\n\");\n2196:\t\t\treturn;\n2197:\t\t}\n2198:\t\n2199:\t\told_pause = pl-\u003econfig-\u003emac_capabilities \u0026 (MAC_SYM_PAUSE | MAC_ASYM_PAUSE);\n2200:\t\tif (old_pause == mac_pause)\n2201:\t\t\treturn;\n2202:\t\n2203:\t\tmutex_lock(\u0026pl-\u003estate_mutex);\n2204:\t\n2205:\t\tpl-\u003econfig-\u003emac_capabilities \u0026= ~(MAC_SYM_PAUSE | MAC_ASYM_PAUSE);\n2206:\t\tpl-\u003econfig-\u003emac_capabilities |= mac_pause;\n2207:\t\n2208:\t\tphylink_set(pl-\u003esupported, Pause);\n2209:\t\tphylink_set(pl-\u003esupported, Asym_Pause);\n2210:\t\n2211:\t\tif (pl-\u003ephydev)\n2212:\t\t\tlinkmode_and(pl-\u003esupported, pl-\u003esupported, pl-\u003ephydev-\u003esupported);\n2213:\t\telse if (pl-\u003esfp_bus)\n2214:\t\t\tlinkmode_and(pl-\u003esupported, pl-\u003esupported, pl-\u003esfp_support);\n2215:\t\n2216:\t\tphylink_validate(pl, pl-\u003esupported, config);\n2217:\t\n2218:\t\tpause_state = config-\u003epause;\n2219:\t\n2220:\t\tif (!phylink_test(pl-\u003esupported, Pause)) {\n2221:\t\t\tpause_state \u0026= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);\n2222:\t\t} else if (!phylink_test(pl-\u003esupported, Asym_Pause)) {\n2223:\t\t\tif ((pause_state \u0026 MLO_PAUSE_RX) ^ (pause_state \u0026 MLO_PAUSE_TX))\n2224:\t\t\t\tpause_state \u0026= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);\n2225:\t\t}\n2226:\t\n2227:\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n2228:\t\n2229:\t\tphylink_update_pause_state(pl, pause_state);\n2230:\t}\n2231:\tEXPORT_SYMBOL_GPL(phylink_update_mac_pause_capabilities);\n2232:\t\n2233:\t/**\n2234:\t * phylink_create() - create a phylink instance\n2235:\t * @config: a pointer to the target \u0026struct phylink_config\n"
} |
| 27/2 | 2026/10/09 21:57 | llm | patch-evaluator |
1mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 165278 output: 37 thoughts: 249 Thoughts: Here's my analysis of the code, as I understand it: **Potential Deadlock in phylink Update Process** Okay, so I'm digging into this `phylink` code and I see a potential issue. Looking at line 2203 in `phylink_update_mac_pause_capabilities`, it locks `pl->state_mutex`. Fine, standard practice for protecting shared state. Then, on line 2216, it calls `phylink_validate()` with `pl->state_mutex` held. Hmm, let's trace this function call. `phylink_validate()` then calls `phylink_validate_mac_and_pcs()` which is on line 689. Then, crucially, line 550 in `phylink_validate_mac_and_pcs()` tries to lock `pl->state_mutex` *again*. **DEADLOCK!** The `pl->state_mutex` is already held by `phylink_update_mac_pause_capabilities()`! This is a classic mutex re-acquisition scenario that's going to stall the system. But wait, I need to be thorough. Let me quickly check the call path of `phylink_validate_phy()` to be certain there isn't another similar re-entrant problem in that function, as well. Gotta rule out other similar issues. |
| 28/2 | 2026/10/09 21:58 | tool | grepper |
0mArgs:{
"Expression": "phylink_validate_phy",
"PathPrefixes": [
"drivers/net/phy/phylink.c"
]
}Results: {
"Output": "drivers/net/phy/phylink.c=2444=static void phylink_phy_change(struct phy_device *phydev, bool up)\n--\ndrivers/net/phy/phylink.c-2481-\ndrivers/net/phy/phylink.c:2482:static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,\ndrivers/net/phy/phylink.c-2483-\t\t\t\tunsigned long *supported,\n--\ndrivers/net/phy/phylink.c=2555=static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,\n--\ndrivers/net/phy/phylink.c-2576-\ndrivers/net/phy/phylink.c:2577:\tret = phylink_validate_phy(pl, phy, supported, \u0026config);\ndrivers/net/phy/phylink.c-2578-\tif (ret) {\n"
} |
| 29/2 | 2026/10/09 21:58 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 166105 output: 24 thoughts: 148 Thoughts: **Deadlock Detected in Phylink Driver!** Okay, so I'm digging into this `phylink_bringup_phy` function, specifically around lines 2577 and 2598. It looks like line 2577 gets executed *before* the `mutex_lock(&pl->state_mutex)` call on 2598. Which means, at that point, the function isn't holding the `state_mutex`. Fine, that seems normal. But, here's where it gets interesting... I need to look at `phylink_update_mac_pause_capabilities`. I see that on line 2203, `state_mutex` is locked. Then, right after, on line 2216, it calls `phylink_validate()`, which then calls `phylink_validate_mac_and_pcs()` and *that* *also* locks `state_mutex`! Wait a minute... that's a direct self-deadlock! The function is trying to lock the same mutex twice, without releasing it first. This is a classic recipe for disaster. Now, I need to understand the full call graph to figure out the context of this. Let's trace back: who calls `phylink_update_mac_pause_capabilities`? Gotta find all the callers to understand how this deadlock is triggered in practice. Time to go hunting for the root cause... |
| 30/2 | 2026/10/09 21:58 | tool | grepper |
0mArgs:{
"Expression": "phylink_update_mac_pause_capabilities"
}Results: {
"Output": "drivers/net/ethernet/realtek/r8169_main.c=4293=static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)\n--\ndrivers/net/ethernet/realtek/r8169_main.c-4309-\ndrivers/net/ethernet/realtek/r8169_main.c:4310:\t\tphylink_update_mac_pause_capabilities(tp-\u003ephylink, caps);\ndrivers/net/ethernet/realtek/r8169_main.c-4311-\t}\n--\ndrivers/net/phy/phylink.c=2120=static void phylink_update_pause_state(struct phylink *pl, int pause_state)\n--\ndrivers/net/phy/phylink.c-2177-/**\ndrivers/net/phy/phylink.c:2178: * phylink_update_mac_pause_capabilities() - Dynamically update MAC pause\ndrivers/net/phy/phylink.c-2179- * @pl: a pointer to a \u0026struct phylink returned from phylink_create()\n--\ndrivers/net/phy/phylink.c-2185- */\ndrivers/net/phy/phylink.c:2186:void phylink_update_mac_pause_capabilities(struct phylink *pl, unsigned long mac_pause)\ndrivers/net/phy/phylink.c-2187-{\n--\ndrivers/net/phy/phylink.c-2230-}\ndrivers/net/phy/phylink.c:2231:EXPORT_SYMBOL_GPL(phylink_update_mac_pause_capabilities);\ndrivers/net/phy/phylink.c-2232-\n--\ninclude/linux/phylink.h=872=void phylink_replay_link_end(struct phylink *pl);\ninclude/linux/phylink.h-873-\ninclude/linux/phylink.h:874:void phylink_update_mac_pause_capabilities(struct phylink *pl, unsigned long mac_pause);\ninclude/linux/phylink.h-875-\n"
} |
| 31/2 | 2026/10/09 21:58 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 167127 output: 29 thoughts: 763 Thoughts: **Deadlock Detected in Phylink and Implications for Fuzzing** Okay, hold on a second... LOOK AT THIS! It looks like there's a serious deadlock lurking in this patch. I see that `r8169_main.c` calls `phylink_update_mac_pause_capabilities` when the MTU changes. That function, triggered by something as simple as an `ip link set` command, takes `pl->state_mutex`. Then, within `phylink_update_mac_pause_capabilities`, it calls `phylink_validate()` which leads to `phylink_validate_mac_and_pcs()`, and *that* attempts to acquire `pl->state_mutex` AGAIN. It's a classic locking inversion! A guaranteed deadlock introduced by this patch series! And look at this `lockdep_assert_held(&pl->state_mutex);` in `phylink_add_pcs()`! It's right there, practically waving a red flag. The code clearly states that this mutex *must* be held before calling it. But the call stack above indicates it already has the mutex! This is a critical issue that demands immediate attention. I need to understand the implications of this. This isn't just a minor tweak; this patch touches core networking infrastructure. It's digging into `drivers/net/phy/phylink.c`, `drivers/net/pcs/pcs.c`, plus the relevant include files, `phylink.h` and `pcs.h`. Phylink is a central component! It's used by drivers for everything from USB networking (asix, lan78xx) to PCIe NICs (like r8169), DSA, and probably a host of other devices I'm not immediately thinking of. The patch modifies locking itself, the `pl->state_mutex` specifically, it *adds* the `lockdep_assert_held()` check, and it introduces new PCS matching logic. It's also messing with `supported_interfaces` bitmasks and adding provider notify callbacks. Hold on... I need to consider this in light of the fuzzing guidance. Section 1 of those instructions is ringing in my head: *Reachability is the primary gate!* And *NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED*. This definitely introduces new assertions *and* modifies reachable code! This is not just a “refactoring” or “no functional change” situation; this is modifying core logic. It falls into the “Core Subsystems” and “Reachable Drivers and Protocols” categories. Specifically, it touches networking, and, critically, it touches drivers accessible via virtual buses, like virtio and USB! This deadlock makes the code *even more* vulnerable to fuzzing. I need to design a fuzzing strategy that explicitly targets MTU changes and network configuration involving phylink-based drivers. Let's make sure we have the correct config settings in place for this. I need to verify how `phylink.c` is built; so I need to check `drivers/net/phy/Makefile` and `drivers/net/phy/Kconfig`. |
| 32/2 | 2026/10/09 21:59 | tool | grepper |
0mArgs:{
"Expression": "phylink",
"PathPrefixes": [
"drivers/net/phy/"
]
}Results: {
"Output": "\nFull output is too long, showing 200 out of 2507 lines.\nUse more precise expression or PathPrefixes if possible.\n\nNumber of matching lines per file (5 files in total):\ndrivers/net/phy/Makefile:1\ndrivers/net/phy/phy_device.c:3\ndrivers/net/phy/phylink.c:763\ndrivers/net/phy/qcom/at803x.c:6\ndrivers/net/phy/sfp-bus.c:50\n\ndrivers/net/phy/Makefile=18=obj-$(CONFIG_PHYLIB)\t\t+= mdio_bus.o\ndrivers/net/phy/Makefile:19:obj-$(CONFIG_PHYLINK)\t\t+= phylink.o\ndrivers/net/phy/Makefile-20-obj-$(CONFIG_PHYLIB)\t\t+= libphy.o\n--\ndrivers/net/phy/phy_device.c=251=static void phy_link_change(struct phy_device *phydev, bool up)\n--\ndrivers/net/phy/phy_device.c-275- *\ndrivers/net/phy/phy_device.c:276: * When the PHY driver is used by the MAC driver consumer through phylink (the\ndrivers/net/phy/phy_device.c-277- * only other provider of a phy_link_change() method), using the PHY state\n--\ndrivers/net/phy/phy_device.c=1684=static void phy_detach_internal(struct phy_device *phydev, bool notify_bus)\n--\ndrivers/net/phy/phy_device.c-1728-\tphydev-\u003ephy_link_change = NULL;\ndrivers/net/phy/phy_device.c:1729:\tphydev-\u003ephylink = NULL;\ndrivers/net/phy/phy_device.c-1730-\n--\ndrivers/net/phy/phy_device.c=2864=EXPORT_SYMBOL(phy_advertise_supported);\n--\ndrivers/net/phy/phy_device.c-2873- * trigger auto-negotiation, so must be called before phy_start()/\ndrivers/net/phy/phy_device.c:2874: * phylink_start() which will start auto-negotiation.\ndrivers/net/phy/phy_device.c-2875- */\n--\ndrivers/net/phy/phylink.c-2-/*\ndrivers/net/phy/phylink.c:3: * phylink models the MAC to optional PHY connection, supporting\ndrivers/net/phy/phylink.c-4- * technologies such as SFP cages where the PHY is hot-pluggable.\n--\ndrivers/net/phy/phylink.c-17-#include \u003clinux/phy_fixed.h\u003e\ndrivers/net/phy/phylink.c:18:#include \u003clinux/phylink.h\u003e\ndrivers/net/phy/phylink.c-19-#include \u003clinux/rtnetlink.h\u003e\n--\ndrivers/net/phy/phylink.c=28=enum {\n--\ndrivers/net/phy/phylink.c-39-/**\ndrivers/net/phy/phylink.c:40: * struct phylink - internal data type for phylink\ndrivers/net/phy/phylink.c-41- */\ndrivers/net/phy/phylink.c:42:struct phylink {\ndrivers/net/phy/phylink.c-43-\t/* private: */\ndrivers/net/phy/phylink.c-44-\tstruct net_device *netdev;\ndrivers/net/phy/phylink.c:45:\tconst struct phylink_mac_ops *mac_ops;\ndrivers/net/phy/phylink.c:46:\tstruct phylink_config *config;\ndrivers/net/phy/phylink.c:47:\tstruct phylink_pcs *pcs;\ndrivers/net/phy/phylink.c-48-\tstruct fwnode_handle *fwnode;\n--\ndrivers/net/phy/phylink.c-51-\ndrivers/net/phy/phylink.c:52:\tunsigned long phylink_disable_state; /* bitmask of disables */\ndrivers/net/phy/phylink.c-53-\tstruct phy_device *phydev;\n--\ndrivers/net/phy/phylink.c-62-\t/* The link configuration settings */\ndrivers/net/phy/phylink.c:63:\tstruct phylink_link_state link_config;\ndrivers/net/phy/phylink.c-64-\n--\ndrivers/net/phy/phylink.c-81-\tstruct mutex state_mutex;\ndrivers/net/phy/phylink.c:82:\t/* Serialize updates to pl-\u003ephydev with phylink_resolve() */\ndrivers/net/phy/phylink.c-83-\tstruct mutex phydev_mutex;\ndrivers/net/phy/phylink.c:84:\tstruct phylink_link_state phy_state;\ndrivers/net/phy/phylink.c-85-\tunsigned int phy_ib_mode;\n--\ndrivers/net/phy/phylink.c-113-\ndrivers/net/phy/phylink.c:114:#define phylink_printk(level, pl, fmt, ...) \\\ndrivers/net/phy/phylink.c-115-\tdo { \\\n--\ndrivers/net/phy/phylink.c-121-\ndrivers/net/phy/phylink.c:122:#define phylink_err(pl, fmt, ...) \\\ndrivers/net/phy/phylink.c:123:\tphylink_printk(KERN_ERR, pl, fmt, ##__VA_ARGS__)\ndrivers/net/phy/phylink.c:124:#define phylink_warn(pl, fmt, ...) \\\ndrivers/net/phy/phylink.c:125:\tphylink_printk(KERN_WARNING, pl, fmt, ##__VA_ARGS__)\ndrivers/net/phy/phylink.c:126:#define phylink_info(pl, fmt, ...) \\\ndrivers/net/phy/phylink.c:127:\tphylink_printk(KERN_INFO, pl, fmt, ##__VA_ARGS__)\ndrivers/net/phy/phylink.c-128-#if defined(CONFIG_DYNAMIC_DEBUG)\ndrivers/net/phy/phylink.c:129:#define phylink_dbg(pl, fmt, ...) \\\ndrivers/net/phy/phylink.c-130-do {\t\t\t\t\t\t\t\t\t\\\n--\ndrivers/net/phy/phylink.c-136-#elif defined(DEBUG)\ndrivers/net/phy/phylink.c:137:#define phylink_dbg(pl, fmt, ...)\t\t\t\t\t\\\ndrivers/net/phy/phylink.c:138:\tphylink_printk(KERN_DEBUG, pl, fmt, ##__VA_ARGS__)\ndrivers/net/phy/phylink.c-139-#else\ndrivers/net/phy/phylink.c:140:#define phylink_dbg(pl, fmt, ...)\t\t\t\t\t\\\ndrivers/net/phy/phylink.c-141-({\t\t\t\t\t\t\t\t\t\\\ndrivers/net/phy/phylink.c-142-\tif (0)\t\t\t\t\t\t\t\t\\\ndrivers/net/phy/phylink.c:143:\t\tphylink_printk(KERN_DEBUG, pl, fmt, ##__VA_ARGS__);\t\\\ndrivers/net/phy/phylink.c-144-})\n--\ndrivers/net/phy/phylink.c-146-\ndrivers/net/phy/phylink.c:147:static const phy_interface_t phylink_sfp_interface_preference[] = {\ndrivers/net/phy/phylink.c-148-\tPHY_INTERFACE_MODE_100GBASEP,\n--\ndrivers/net/phy/phylink.c-160-\ndrivers/net/phy/phylink.c:161:static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);\ndrivers/net/phy/phylink.c-162-\ndrivers/net/phy/phylink.c-163-/**\ndrivers/net/phy/phylink.c:164: * phylink_set_port_modes() - set the port type modes in the ethtool mask\ndrivers/net/phy/phylink.c-165- * @mask: ethtool link mode mask\n--\ndrivers/net/phy/phylink.c-168- */\ndrivers/net/phy/phylink.c:169:void phylink_set_port_modes(unsigned long *mask)\ndrivers/net/phy/phylink.c-170-{\ndrivers/net/phy/phylink.c:171:\tphylink_set(mask, TP);\ndrivers/net/phy/phylink.c:172:\tphylink_set(mask, AUI);\ndrivers/net/phy/phylink.c:173:\tphylink_set(mask, MII);\ndrivers/net/phy/phylink.c:174:\tphylink_set(mask, FIBRE);\ndrivers/net/phy/phylink.c:175:\tphylink_set(mask, BNC);\ndrivers/net/phy/phylink.c:176:\tphylink_set(mask, Backplane);\ndrivers/net/phy/phylink.c-177-}\ndrivers/net/phy/phylink.c:178:EXPORT_SYMBOL_GPL(phylink_set_port_modes);\ndrivers/net/phy/phylink.c-179-\ndrivers/net/phy/phylink.c:180:static int phylink_is_empty_linkmode(const unsigned long *linkmode)\ndrivers/net/phy/phylink.c-181-{\n--\ndrivers/net/phy/phylink.c-183-\ndrivers/net/phy/phylink.c:184:\tphylink_set_port_modes(tmp);\ndrivers/net/phy/phylink.c:185:\tphylink_set(tmp, Autoneg);\ndrivers/net/phy/phylink.c:186:\tphylink_set(tmp, Pause);\ndrivers/net/phy/phylink.c:187:\tphylink_set(tmp, Asym_Pause);\ndrivers/net/phy/phylink.c-188-\n--\ndrivers/net/phy/phylink.c-191-\ndrivers/net/phy/phylink.c:192:static const char *phylink_an_mode_str(unsigned int mode)\ndrivers/net/phy/phylink.c-193-{\n--\ndrivers/net/phy/phylink.c-202-\ndrivers/net/phy/phylink.c:203:static const char *phylink_pcs_mode_str(unsigned int mode)\ndrivers/net/phy/phylink.c-204-{\n--\ndrivers/net/phy/phylink.c-220-\ndrivers/net/phy/phylink.c:221:static unsigned int phylink_interface_signal_rate(phy_interface_t interface)\ndrivers/net/phy/phylink.c-222-{\n--\ndrivers/net/phy/phylink.c-238-/**\ndrivers/net/phy/phylink.c:239: * phylink_interface_max_speed() - get the maximum speed of a phy interface\ndrivers/net/phy/phylink.c-240- * @interface: phy interface mode defined by \u0026typedef phy_interface_t\n--\ndrivers/net/phy/phylink.c-247- */\ndrivers/net/phy/phylink.c:248:static int phylink_interface_max_speed(phy_interface_t interface)\ndrivers/net/phy/phylink.c-249-{\n--\ndrivers/net/phy/phylink.c=317=static struct {\n--\ndrivers/net/phy/phylink.c-321-\tunsigned int caps_bit;\ndrivers/net/phy/phylink.c:322:} phylink_caps_params[] = {\ndrivers/net/phy/phylink.c-323-\t{ MAC_400000FD, SPEED_400000, DUPLEX_FULL, BIT(LINK_CAPA_400000FD) },\n--\ndrivers/net/phy/phylink.c-343-/**\ndrivers/net/phy/phylink.c:344: * phylink_caps_to_link_caps() - Convert a set of MAC capabilities LINK caps\ndrivers/net/phy/phylink.c-345- * @caps: A set of MAC capabilities\n--\ndrivers/net/phy/phylink.c-348- */\ndrivers/net/phy/phylink.c:349:static unsigned long phylink_caps_to_link_caps(unsigned long caps)\ndrivers/net/phy/phylink.c-350-{\n--\ndrivers/net/phy/phylink.c-353-\ndrivers/net/phy/phylink.c:354:\tfor (i = 0; i \u003c ARRAY_SIZE(phylink_caps_params); i++)\ndrivers/net/phy/phylink.c:355:\t\tif (caps \u0026 phylink_caps_params[i].mask)\ndrivers/net/phy/phylink.c:356:\t\t\tlink_caps |= phylink_caps_params[i].caps_bit;\ndrivers/net/phy/phylink.c-357-\n--\ndrivers/net/phy/phylink.c-360-\ndrivers/net/phy/phylink.c:361:static unsigned long phylink_link_caps_to_mac_caps(unsigned long link_caps)\ndrivers/net/phy/phylink.c-362-{\n--\ndrivers/net/phy/phylink.c-365-\ndrivers/net/phy/phylink.c:366:\tfor (i = 0; i \u003c ARRAY_SIZE(phylink_caps_params); i++)\ndrivers/net/phy/phylink.c:367:\t\tif (link_caps \u0026 phylink_caps_params[i].caps_bit)\ndrivers/net/phy/phylink.c:368:\t\t\tcaps |= phylink_caps_params[i].mask;\ndrivers/net/phy/phylink.c-369-\n--\ndrivers/net/phy/phylink.c-373-/**\ndrivers/net/phy/phylink.c:374: * phylink_caps_to_linkmodes() - Convert capabilities to ethtool link modes\ndrivers/net/phy/phylink.c-375- * @linkmodes: ethtool linkmode mask (must be already initialised)\n--\ndrivers/net/phy/phylink.c-380- */\ndrivers/net/phy/phylink.c:381:static void phylink_caps_to_linkmodes(unsigned long *linkmodes,\ndrivers/net/phy/phylink.c-382-\t\t\t\t unsigned long caps)\ndrivers/net/phy/phylink.c-383-{\ndrivers/net/phy/phylink.c:384:\tunsigned long link_caps = phylink_caps_to_link_caps(caps);\ndrivers/net/phy/phylink.c-385-\n--\ndrivers/net/phy/phylink.c-395-/**\ndrivers/net/phy/phylink.c:396: * phylink_limit_mac_speed - limit the phylink_config to a maximum speed\ndrivers/net/phy/phylink.c:397: * @config: pointer to a \u0026struct phylink_config\ndrivers/net/phy/phylink.c-398- * @max_speed: maximum speed\n--\ndrivers/net/phy/phylink.c-402- */\ndrivers/net/phy/phylink.c:403:void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed)\ndrivers/net/phy/phylink.c-404-{\n--\ndrivers/net/phy/phylink.c-406-\ndrivers/net/phy/phylink.c:407:\tfor (i = 0; i \u003c ARRAY_SIZE(phylink_caps_params) \u0026\u0026\ndrivers/net/phy/phylink.c:408:\t\t phylink_caps_params[i].speed \u003e max_speed; i++)\ndrivers/net/phy/phylink.c:409:\t\tconfig-\u003emac_capabilities \u0026= ~phylink_caps_params[i].mask;\ndrivers/net/phy/phylink.c-410-}\ndrivers/net/phy/phylink.c:411:EXPORT_SYMBOL_GPL(phylink_limit_mac_speed);\ndrivers/net/phy/phylink.c-412-\ndrivers/net/phy/phylink.c-413-/**\ndrivers/net/phy/phylink.c:414: * phylink_cap_from_speed_duplex - Get mac capability from speed/duplex\ndrivers/net/phy/phylink.c-415- * @speed: the speed to search for\n--\ndrivers/net/phy/phylink.c-422- */\ndrivers/net/phy/phylink.c:423:static unsigned long phylink_cap_from_speed_duplex(int speed,\ndrivers/net/phy/phylink.c-424-\t\t\t\t\t\t unsigned int duplex)\n--\n\n"
} |
| 33/2 | 2026/10/09 21:59 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 172886 output: 29 thoughts: 16 Thoughts: Okay, here's my attempt at summarizing those thoughts from an expert's perspective, using a first-person narrative: **Kconfig Inquiry: PHYLINK and FWNODE_PCS** Alright, let's get down to brass tacks. I need to quickly refresh my mental map of the configuration space. Specifically, I need to check the Kconfig files for the definitions and dependencies of `PHYLINK` and `FWNODE_PCS`. These are critical, especially when dealing with network device drivers and platform integration. I want to make sure I understand how these features are conditionally compiled or enabled. I'm thinking, are these features enabled by default? Are there dependencies I'm overlooking? Do they tie into specific hardware platforms or networking subsystems? Is their configuration complex enough that I need to look deeper into the help text and source code associated with them? A cursory glance at Kconfig should quickly point me to the relevant options, their dependencies, and any default settings. This quick investigation will either reassure me that I'm on solid ground or immediately reveal potential configuration issues or areas requiring further investigation before I dig deeper into the code. Time to get to it! |
| 34/2 | 2026/10/09 21:59 | tool | grepper |
0mArgs:{
"Expression": "config PHYLINK",
"PathPrefixes": [
"drivers/net/"
]
}Results: {
"Output": "drivers/net/phy/Kconfig-5-\ndrivers/net/phy/Kconfig:6:config PHYLINK\ndrivers/net/phy/Kconfig-7-\ttristate\n"
} |
| 35/2 | 2026/10/09 21:59 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 173230 output: 34 thoughts: 19 Thoughts: Here's a summary of my thought process, as requested: **Diving into the PHY Configuration** Okay, let's get down to brass tacks. I need to understand the PHY configuration options, so my starting point is the `drivers/net/phy/Kconfig` file, specifically around line 6. I'm assuming that's where the primary configuration variables are introduced. From there, I'll be able to infer the structure of the relevant Kconfig options and their dependencies. I'm expecting this file to define which PHY drivers are built-in or modular, conditional on certain hardware or platform settings. Depending on the level of detail, I expect to see an introduction of various PHY features or maybe even specific driver selections. |
| 36/2 | 2026/10/09 21:59 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/Kconfig",
"FirstLine": 1,
"LineCount": 20
}Results: {
"Contents": " 1:\t# SPDX-License-Identifier: GPL-2.0-only\n 2:\t#\n 3:\t# PHY Layer Configuration\n 4:\t#\n 5:\t\n 6:\tconfig PHYLINK\n 7:\t\ttristate\n 8:\t\tselect PHYLIB\n 9:\t\tselect SWPHY\n 10:\t\thelp\n 11:\t\t PHYlink models the link between the PHY and MAC, allowing fixed\n 12:\t\t configuration links, PHYs, and Serdes links with MAC level\n 13:\t\t autonegotiation modes.\n 14:\t\n 15:\tmenuconfig PHYLIB\n 16:\t\ttristate \"PHY Device support and infrastructure\"\n 17:\t\thelp\n 18:\t\t Ethernet controllers are usually attached to PHY\n 19:\t\t devices. This option provides infrastructure for\n 20:\t\t managing PHY devices.\n"
} |
| 37/2 | 2026/10/09 21:59 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 173670 output: 19 thoughts: 95 Thoughts: **Examining the PCS Firmware Node Configuration** Okay, let's dive into this `FWNODE_PCS` configuration item within the `drivers/net/pcs/Kconfig` file. I see it's defined as a boolean, labeled "PCS Firmware Node," and it depends on either ACPI, OF, or `COMPILE_TEST`. That makes sense; it's likely related to accessing PCS functionality through the system's firmware, particularly on ACPI or Device Tree systems, or when testing. But hold on a second... is this configuration option *selected* or *enabled*? This is crucial for understanding its behavior within the build process and how it gets incorporated into the final image. I need to figure out which other configuration options are responsible for pulling in or explicitly activating `FWNODE_PCS`. I'll go digging to see what's selecting or enabling it. I need to trace this back. |
| 38/2 | 2026/10/09 21:59 | tool | grepper |
0mArgs:{
"Expression": "select FWNODE_PCS"
}Results: {
"Output": "drivers/net/pcs/airoha/Kconfig=3=config PCS_AIROHA\ndrivers/net/pcs/airoha/Kconfig-4-\ttristate\ndrivers/net/pcs/airoha/Kconfig:5:\tselect FWNODE_PCS\ndrivers/net/pcs/airoha/Kconfig-6-\n"
} |
| 39/2 | 2026/10/09 21:59 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 174063 output: 18 thoughts: 152 Thoughts: **My Configuration Investigation** Okay, so I'm digging into this configuration and it looks like `PCS_AIROHA` is choosing `FWNODE_PCS`. That's interesting, and it looks like `FWNODE_PCS` has a prompt defined in `drivers/net/pcs/Kconfig`: `"PCS Firmware Node"`. It also depends on either ACPI, OF, or COMPILE_TEST. The implication here is I can, in theory, directly enable it with `CONFIG_FWNODE_PCS=y` if I need to. Always good to have that flexibility in mind. Now, let's circle back. What precisely is *selecting* `PHYLINK`? That's the core of the matter. I know a bunch of drivers do: `NET_AIROHA`, `R8169`, `USB_NET_AX8817X` – wait a second, isn't that the ax88772 chipset as well? – and `USB_LAN78XX`, and undoubtedly many others. I'll need to go through and see *exactly* which drivers are setting `PHYLINK` to be true. I'll need to see that list, and what the dependencies are, so I can more intelligently build this thing out. |
| 40/2 | 2026/10/09 22:00 | tool | grepper |
0mArgs:{
"Expression": "select PHYLINK"
}Results: {
"Output": "\nFull output is too long, showing 200 out of 202 lines.\nUse more precise expression or PathPrefixes if possible.\n\nNumber of matching lines per file (29 files in total):\nDocumentation/networking/sfp-phylink.rst:1\ndrivers/net/ethernet/airoha/Kconfig:1\ndrivers/net/ethernet/altera/Kconfig:1\ndrivers/net/ethernet/atheros/Kconfig:1\ndrivers/net/ethernet/cadence/Kconfig:1\ndrivers/net/ethernet/freescale/Kconfig:1\ndrivers/net/ethernet/freescale/dpaa/Kconfig:1\ndrivers/net/ethernet/freescale/dpaa2/Kconfig:2\ndrivers/net/ethernet/freescale/enetc/Kconfig:3\ndrivers/net/ethernet/freescale/fman/Kconfig:1\ndrivers/net/ethernet/freescale/fs_enet/Kconfig:1\ndrivers/net/ethernet/marvell/Kconfig:2\ndrivers/net/ethernet/marvell/prestera/Kconfig:1\ndrivers/net/ethernet/mediatek/Kconfig:1\ndrivers/net/ethernet/meta/Kconfig:1\ndrivers/net/ethernet/microchip/Kconfig:1\ndrivers/net/ethernet/microchip/lan966x/Kconfig:1\ndrivers/net/ethernet/microchip/sparx5/Kconfig:1\ndrivers/net/ethernet/mscc/Kconfig:1\ndrivers/net/ethernet/realtek/Kconfig:1\ndrivers/net/ethernet/renesas/Kconfig:1\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:1\ndrivers/net/ethernet/tehuti/Kconfig:1\ndrivers/net/ethernet/ti/Kconfig:1\ndrivers/net/ethernet/wangxun/Kconfig:1\ndrivers/net/ethernet/xilinx/Kconfig:1\ndrivers/net/pcs/Kconfig:1\ndrivers/net/usb/Kconfig:2\nnet/dsa/Kconfig:1\n\nDocumentation/networking/sfp-phylink.rst=74=this documentation.\n--\nDocumentation/networking/sfp-phylink.rst-91-\nDocumentation/networking/sfp-phylink.rst:92:\tselect PHYLINK\nDocumentation/networking/sfp-phylink.rst-93-\n--\ndrivers/net/ethernet/airoha/Kconfig=18=config NET_AIROHA\n--\ndrivers/net/ethernet/airoha/Kconfig-23-\tselect PCS_AIROHA\ndrivers/net/ethernet/airoha/Kconfig:24:\tselect PHYLINK\ndrivers/net/ethernet/airoha/Kconfig-25-\thelp\n--\ndrivers/net/ethernet/altera/Kconfig=2=config ALTERA_TSE\n--\ndrivers/net/ethernet/altera/Kconfig-6-\tselect PHYLIB\ndrivers/net/ethernet/altera/Kconfig:7:\tselect PHYLINK\ndrivers/net/ethernet/altera/Kconfig-8-\tselect PCS_LYNX\n--\ndrivers/net/ethernet/atheros/Kconfig=20=config AG71XX\n--\ndrivers/net/ethernet/atheros/Kconfig-22-\tdepends on ATH79 || COMPILE_TEST\ndrivers/net/ethernet/atheros/Kconfig:23:\tselect PHYLINK\ndrivers/net/ethernet/atheros/Kconfig-24-\timply NET_SELFTESTS\n--\ndrivers/net/ethernet/cadence/Kconfig=22=config MACB\n--\ndrivers/net/ethernet/cadence/Kconfig-25-\tdepends on PTP_1588_CLOCK_OPTIONAL\ndrivers/net/ethernet/cadence/Kconfig:26:\tselect PHYLINK\ndrivers/net/ethernet/cadence/Kconfig-27-\tselect CRC32\n--\ndrivers/net/ethernet/freescale/Kconfig=80=config UCC_GETH\n--\ndrivers/net/ethernet/freescale/Kconfig-83-\tselect FSL_PQ_MDIO\ndrivers/net/ethernet/freescale/Kconfig:84:\tselect PHYLINK\ndrivers/net/ethernet/freescale/Kconfig-85-\thelp\n--\ndrivers/net/ethernet/freescale/dpaa/Kconfig=2=menuconfig FSL_DPAA_ETH\n--\ndrivers/net/ethernet/freescale/dpaa/Kconfig-4-\tdepends on FSL_DPAA \u0026\u0026 FSL_FMAN\ndrivers/net/ethernet/freescale/dpaa/Kconfig:5:\tselect PHYLINK\ndrivers/net/ethernet/freescale/dpaa/Kconfig-6-\tselect PCS_LYNX\n--\ndrivers/net/ethernet/freescale/dpaa2/Kconfig=2=config FSL_DPAA2_ETH\n--\ndrivers/net/ethernet/freescale/dpaa2/Kconfig-4-\tdepends on FSL_MC_BUS \u0026\u0026 FSL_MC_DPIO\ndrivers/net/ethernet/freescale/dpaa2/Kconfig:5:\tselect PHYLINK\ndrivers/net/ethernet/freescale/dpaa2/Kconfig-6-\tselect PCS_LYNX\n--\ndrivers/net/ethernet/freescale/dpaa2/Kconfig=33=config FSL_DPAA2_SWITCH\n--\ndrivers/net/ethernet/freescale/dpaa2/Kconfig-37-\tdepends on FSL_MC_BUS \u0026\u0026 FSL_MC_DPIO\ndrivers/net/ethernet/freescale/dpaa2/Kconfig:38:\tselect PHYLINK\ndrivers/net/ethernet/freescale/dpaa2/Kconfig-39-\tselect PCS_LYNX\n--\ndrivers/net/ethernet/freescale/enetc/Kconfig=30=config FSL_ENETC\n--\ndrivers/net/ethernet/freescale/enetc/Kconfig-37-\tselect NXP_ENETC_PF_COMMON\ndrivers/net/ethernet/freescale/enetc/Kconfig:38:\tselect PHYLINK\ndrivers/net/ethernet/freescale/enetc/Kconfig-39-\tselect PCS_LYNX\n--\ndrivers/net/ethernet/freescale/enetc/Kconfig=48=config NXP_ENETC4\n--\ndrivers/net/ethernet/freescale/enetc/Kconfig-55-\tselect NXP_NTMP\ndrivers/net/ethernet/freescale/enetc/Kconfig:56:\tselect PHYLINK\ndrivers/net/ethernet/freescale/enetc/Kconfig-57-\tselect DIMLIB\n--\ndrivers/net/ethernet/freescale/enetc/Kconfig=66=config FSL_ENETC_VF\n--\ndrivers/net/ethernet/freescale/enetc/Kconfig-72-\tselect NXP_NTMP\ndrivers/net/ethernet/freescale/enetc/Kconfig:73:\tselect PHYLINK\ndrivers/net/ethernet/freescale/enetc/Kconfig-74-\tselect DIMLIB\n--\ndrivers/net/ethernet/freescale/fman/Kconfig=2=config FSL_FMAN\n--\ndrivers/net/ethernet/freescale/fman/Kconfig-5-\tselect GENERIC_ALLOCATOR\ndrivers/net/ethernet/freescale/fman/Kconfig:6:\tselect PHYLINK\ndrivers/net/ethernet/freescale/fman/Kconfig-7-\tselect PCS_LYNX\n--\ndrivers/net/ethernet/freescale/fs_enet/Kconfig=2=config FS_ENET\n--\ndrivers/net/ethernet/freescale/fs_enet/Kconfig-5-\tselect MII\ndrivers/net/ethernet/freescale/fs_enet/Kconfig:6:\tselect PHYLINK\ndrivers/net/ethernet/freescale/fs_enet/Kconfig-7-\n--\ndrivers/net/ethernet/marvell/Kconfig=59=config MVNETA\n--\ndrivers/net/ethernet/marvell/Kconfig-62-\tselect MVMDIO\ndrivers/net/ethernet/marvell/Kconfig:63:\tselect PHYLINK\ndrivers/net/ethernet/marvell/Kconfig-64-\tselect PAGE_POOL\n--\ndrivers/net/ethernet/marvell/Kconfig=86=config MVPP2\n--\ndrivers/net/ethernet/marvell/Kconfig-89-\tselect MVMDIO\ndrivers/net/ethernet/marvell/Kconfig:90:\tselect PHYLINK\ndrivers/net/ethernet/marvell/Kconfig-91-\tselect PAGE_POOL\n--\ndrivers/net/ethernet/marvell/prestera/Kconfig=6=config PRESTERA\n--\ndrivers/net/ethernet/marvell/prestera/Kconfig-10-\tselect NET_DEVLINK\ndrivers/net/ethernet/marvell/prestera/Kconfig:11:\tselect PHYLINK\ndrivers/net/ethernet/marvell/prestera/Kconfig-12-\thelp\n--\ndrivers/net/ethernet/mediatek/Kconfig=14=config NET_MEDIATEK_SOC\n--\ndrivers/net/ethernet/mediatek/Kconfig-17-\tselect PINCTRL\ndrivers/net/ethernet/mediatek/Kconfig:18:\tselect PHYLINK\ndrivers/net/ethernet/mediatek/Kconfig-19-\tselect DIMLIB\n--\ndrivers/net/ethernet/meta/Kconfig=20=config FBNIC\n--\ndrivers/net/ethernet/meta/Kconfig-29-\tselect PCS_XPCS\ndrivers/net/ethernet/meta/Kconfig:30:\tselect PHYLINK\ndrivers/net/ethernet/meta/Kconfig-31-\tselect PLDMFW\n--\ndrivers/net/ethernet/microchip/Kconfig=45=config LAN743X\n--\ndrivers/net/ethernet/microchip/Kconfig-51-\tselect CRC32\ndrivers/net/ethernet/microchip/Kconfig:52:\tselect PHYLINK\ndrivers/net/ethernet/microchip/Kconfig-53-\thelp\n--\ndrivers/net/ethernet/microchip/lan966x/Kconfig=1=config LAN966X_SWITCH\n--\ndrivers/net/ethernet/microchip/lan966x/Kconfig-7-\tdepends on BRIDGE || BRIDGE=n\ndrivers/net/ethernet/microchip/lan966x/Kconfig:8:\tselect PHYLINK\ndrivers/net/ethernet/microchip/lan966x/Kconfig-9-\tselect PAGE_POOL\n--\ndrivers/net/ethernet/microchip/sparx5/Kconfig=1=config SPARX5_SWITCH\n--\ndrivers/net/ethernet/microchip/sparx5/Kconfig-8-\tdepends on BRIDGE || BRIDGE=n\ndrivers/net/ethernet/microchip/sparx5/Kconfig:9:\tselect PHYLINK\ndrivers/net/ethernet/microchip/sparx5/Kconfig-10-\tselect PHY_SPARX5_SERDES\n--\ndrivers/net/ethernet/mscc/Kconfig=15=config MSCC_OCELOT_SWITCH_LIB\n--\ndrivers/net/ethernet/mscc/Kconfig-19-\tselect PACKING\ndrivers/net/ethernet/mscc/Kconfig:20:\tselect PHYLINK\ndrivers/net/ethernet/mscc/Kconfig-21-\ttristate\n--\ndrivers/net/ethernet/realtek/Kconfig=84=config R8169\n--\ndrivers/net/ethernet/realtek/Kconfig-89-\tselect REALTEK_PHY\ndrivers/net/ethernet/realtek/Kconfig:90:\tselect PHYLINK\ndrivers/net/ethernet/realtek/Kconfig-91-\thelp\n--\ndrivers/net/ethernet/renesas/Kconfig=42=config RENESAS_ETHER_SWITCH\n--\ndrivers/net/ethernet/renesas/Kconfig-47-\tselect MII\ndrivers/net/ethernet/renesas/Kconfig:48:\tselect PHYLINK\ndrivers/net/ethernet/renesas/Kconfig-49-\tselect RENESAS_GEN4_PTP\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig=2=config STMMAC_ETH\n--\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-9-\tselect PAGE_POOL\ndrivers/net/ethernet/stmicro/stmmac/Kconfig:10:\tselect PHYLINK\ndrivers/net/ethernet/stmicro/stmmac/Kconfig-11-\tselect CRC32\n--\ndrivers/net/ethernet/tehuti/Kconfig=26=config TEHUTI_TN40\n--\ndrivers/net/ethernet/tehuti/Kconfig-30-\tselect FW_LOADER\ndrivers/net/ethernet/tehuti/Kconfig:31:\tselect PHYLINK\ndrivers/net/ethernet/tehuti/Kconfig-32-\thelp\n--\ndrivers/net/ethernet/ti/Kconfig=96=config TI_K3_AM65_CPSW_NUSS\n--\ndrivers/net/ethernet/ti/Kconfig-100-\tselect TI_DAVINCI_MDIO\ndrivers/net/ethernet/ti/Kconfig:101:\tselect PHYLINK\ndrivers/net/ethernet/ti/Kconfig-102-\tselect PAGE_POOL\n--\ndrivers/net/ethernet/wangxun/Kconfig=19=config LIBWX\n--\ndrivers/net/ethernet/wangxun/Kconfig-23-\tselect DIMLIB\ndrivers/net/ethernet/wangxun/Kconfig:24:\tselect PHYLINK\ndrivers/net/ethernet/wangxun/Kconfig-25-\thelp\n--\ndrivers/net/ethernet/xilinx/Kconfig=26=config XILINX_AXI_EMAC\n--\ndrivers/net/ethernet/xilinx/Kconfig-29-\tdepends on XILINX_DMA\ndrivers/net/ethernet/xilinx/Kconfig:30:\tselect PHYLINK\ndrivers/net/ethernet/xilinx/Kconfig-31-\tselect DIMLIB\n--\ndrivers/net/pcs/Kconfig=14=config PCS_XPCS\ndrivers/net/pcs/Kconfig-15-\ttristate \"Synopsys DesignWare Ethernet XPCS\"\ndrivers/net/pcs/Kconfig:16:\tselect PHYLINK\ndrivers/net/pcs/Kconfig-17-\thelp\n--\ndrivers/net/usb/Kconfig=113=config USB_LAN78XX\n--\ndrivers/net/usb/Kconfig-115-\tselect MII\ndrivers/net/usb/Kconfig:116:\tselect PHYLINK\ndrivers/net/usb/Kconfig-117-\tselect MICROCHIP_PHY\n--\ndrivers/net/usb/Kconfig=166=config USB_NET_AX8817X\n--\ndrivers/net/usb/Kconfig-169-\tselect CRC32\ndrivers/net/usb/Kconfig:170:\tselect PHYLINK\ndrivers/net/usb/Kconfig-171-\tselect AX88796B_PHY\n--\nnet/dsa/Kconfig=3=menuconfig NET_DSA\n--\nnet/dsa/Kconfig-9-\tselect NET_SWITCHDEV\n\n"
} |
| 41/2 | 2026/10/09 22:00 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 178351 output: 22 thoughts: 1544 Thoughts: **Fuzzing Target Refinement: Phylink Subsystem** Okay, let's nail down this fuzzing target. First, a quick sanity check: we're on the `amd64` architecture, good. Now, let's see which drivers actually *use* the `PHYLINK` subsystem. I see several: `R8169`, `USB_NET_AX8817X`, `USB_LAN78XX`, `NET_DSA`, `LAN743X`, `FBNIC`, and `FWNODE_PCS`. That's a decent breadth of potential targets. The USB drivers are particularly interesting since they are fuzzable via syzkaller USB raw gadget. The changes in the patch are clearly indicating that fuzzing is valuable. Now the crucial part: determining the `FocusSymbols`. Let's stick to the rules. No ubiquitous lifecycle functions – we need to target the *specific* logic and entry points modified. Static inline helpers... we'll look for caller functions in `.c` files that exercise them, avoiding ubiquitous wrappers. Now, let's dissect the patch. In `drivers/net/phy/phylink.c` the non-static and exported functions are: `phylink_create`, `phylink_destroy`, `phylink_pcs_change`, `phylink_update_mac_pause_capabilities`, and `phylink_ethtool_ksettings_set`. These are the strong candidates for our focus symbols, especially since `phylink_update_mac_pause_capabilities` calls that deadlock-prone validate. In `drivers/net/pcs/pcs.c` we have `fwnode_pcs_add_provider`, `fwnode_pcs_del_provider`, `fwnode_pcs_get`, `fwnode_pcs_matches_provider`, `register_fwnode_pcs_notifier`, and `unregister_fwnode_pcs_notifier`. These are also strong candidates. We should be particularly interested in the `phylink_update_mac_pause_capabilities` call, since it calls the deadlock-prone validate. Let's not forget the `airoha` drivers as they add to the equation, and could provide additional insights: In `drivers/net/pcs/pcs.c`, `airoha_pcs_probe`, `airoha_pcs_config`, `airoha_pcs_link_up`, and `airoha_pcs_link_down`. And in `drivers/net/ethernet/airoha/airoha_eth.c`: `airoha_setup_phylink`, `airoha_fill_available_pcs`, `airoha_mac_link_up`, and `airoha_ethtool_set_link_ksettings`. But, we need to consider if these are SoC-specific and potentially unavailable. So, in summary, we're targeting the core `PHYLINK` and `FWNODE_PCS` infrastructure, and any feature-specific additions within the Airoha driver tree, if available. Let's make sure we have the right configuration, we'll need `PHYLINK` and `FWNODE_PCS`, and possibly `NET_AIROHA` or `PCS_AIROHA_AN7581` if they are available. Let's double check `NET_AIROHA` depends on `NET_DSA || !NET_DSA` does not depend on ARCH_AIROHA. |
| 42/2 | 2026/10/09 22:00 | tool | grepper |
0mArgs:{
"Expression": "NET_AIROHA_NPU"
}Results: {
"Output": "drivers/net/ethernet/airoha/Kconfig=8=if NET_VENDOR_AIROHA\ndrivers/net/ethernet/airoha/Kconfig-9-\ndrivers/net/ethernet/airoha/Kconfig:10:config NET_AIROHA_NPU\ndrivers/net/ethernet/airoha/Kconfig-11-\ttristate \"Airoha NPU support\"\n--\ndrivers/net/ethernet/airoha/Kconfig=18=config NET_AIROHA\n--\ndrivers/net/ethernet/airoha/Kconfig-20-\tdepends on NET_DSA || !NET_DSA\ndrivers/net/ethernet/airoha/Kconfig:21:\tselect NET_AIROHA_NPU\ndrivers/net/ethernet/airoha/Kconfig-22-\tselect PAGE_POOL\n--\ndrivers/net/ethernet/airoha/Kconfig=29=config NET_AIROHA_FLOW_STATS\n--\ndrivers/net/ethernet/airoha/Kconfig-31-\tbool \"Airoha flow stats\"\ndrivers/net/ethernet/airoha/Kconfig:32:\tdepends on NET_AIROHA \u0026\u0026 NET_AIROHA_NPU\ndrivers/net/ethernet/airoha/Kconfig-33-\thelp\n--\ndrivers/net/ethernet/airoha/Makefile=8=airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/wireless/mediatek/mt76/Kconfig=40=config MT76_NPU\ndrivers/net/wireless/mediatek/mt76/Kconfig-41-\ttristate\ndrivers/net/wireless/mediatek/mt76/Kconfig:42:\tdepends on NET_AIROHA_NPU=y || MT76_CORE=NET_AIROHA_NPU\ndrivers/net/wireless/mediatek/mt76/Kconfig-43-\n--\ndrivers/net/wireless/mediatek/mt76/mt7996/Kconfig=16=config MT7996_NPU\n--\ndrivers/net/wireless/mediatek/mt76/mt7996/Kconfig-18-\tdepends on MT7996E\ndrivers/net/wireless/mediatek/mt76/mt7996/Kconfig:19:\tdepends on NET_AIROHA_NPU=y || MT76_CORE=NET_AIROHA_NPU\ndrivers/net/wireless/mediatek/mt76/mt7996/Kconfig-20-\tselect MT76_NPU\n--\ninclude/linux/soc/airoha/airoha_offload.h=166=struct airoha_npu {\ninclude/linux/soc/airoha/airoha_offload.h:167:#if (IS_BUILTIN(CONFIG_NET_AIROHA_NPU) || IS_MODULE(CONFIG_NET_AIROHA_NPU))\ninclude/linux/soc/airoha/airoha_offload.h-168-\tstruct device *dev;\n--\ninclude/linux/soc/airoha/airoha_offload.h-210-\ninclude/linux/soc/airoha/airoha_offload.h:211:#if (IS_BUILTIN(CONFIG_NET_AIROHA_NPU) || IS_MODULE(CONFIG_NET_AIROHA_NPU))\ninclude/linux/soc/airoha/airoha_offload.h-212-struct airoha_npu *airoha_npu_get(struct device *dev);\n"
} |
| 43/2 | 2026/10/09 22:00 | llm | patch-evaluator |
1mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 181583 output: 21 thoughts: 28 Thoughts: Okay, here's my take on those thoughts, framed as a first-person expert summary: **Digging into the Airoha Ethernet Driver Configuration** Right, let's get down to brass tacks. I need to understand how the Airoha ethernet driver is configured in this kernel. My initial thought is to go straight to the source, to the configuration file. Specifically, I'm thinking I should start by checking out `NET_VENDOR_AIROHA` within the `drivers/net/ethernet/airoha/Kconfig` file. That's the logical starting point for understanding what options are available, what dependencies might exist, and how the Airoha ethernet support is architected at the configuration level. I'm assuming that this Kconfig file holds the key to the driver's build-time options and dependencies. This is where I'll find out what features are enabled by default, what customizations are possible, and whether there are any prerequisites before considering anything further with this particular driver. Knowing the configuration setup is the groundwork before diving into the code itself. |
| 44/2 | 2026/10/09 22:01 | tool | grepper |
0mArgs:{
"Expression": "NET_VENDOR_AIROHA"
}Results: {
"Output": "drivers/net/ethernet/Makefile=12=obj-$(CONFIG_NET_VENDOR_AGERE) += agere/\ndrivers/net/ethernet/Makefile:13:obj-$(CONFIG_NET_VENDOR_AIROHA) += airoha/\ndrivers/net/ethernet/Makefile-14-obj-$(CONFIG_NET_VENDOR_ALACRITECH) += alacritech/\n--\ndrivers/net/ethernet/airoha/Kconfig-1-# SPDX-License-Identifier: GPL-2.0-only\ndrivers/net/ethernet/airoha/Kconfig:2:config NET_VENDOR_AIROHA\ndrivers/net/ethernet/airoha/Kconfig-3-\tbool \"Airoha devices\"\n--\ndrivers/net/ethernet/airoha/Kconfig-7-\ndrivers/net/ethernet/airoha/Kconfig:8:if NET_VENDOR_AIROHA\ndrivers/net/ethernet/airoha/Kconfig-9-\n--\ndrivers/net/ethernet/airoha/Kconfig=29=config NET_AIROHA_FLOW_STATS\n--\ndrivers/net/ethernet/airoha/Kconfig-35-\ndrivers/net/ethernet/airoha/Kconfig:36:endif #NET_VENDOR_AIROHA\n"
} |
| 45/2 | 2026/10/09 22:01 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 182176 output: 337 thoughts: 1575 Thoughts: **Analysis of Network Phylink and PCS Framework for Fuzzing**
Okay, so I've got this patch series for network phylink and PCS, and I need to determine if it's worth fuzzing and, if so, how to configure the fuzzing effort. My initial thought was that `NET_AIROHA` (and therefore `airoha_eth.c`) was a platform-specific driver, tied to the Airoha AN7581 SoC and needing a device tree. However, this series introduces much more general frameworks for PCS and phylink, and they are compiled as part of the normal kernel config.
Specifically, this patch series touches `drivers/net/phy/phylink.c` and `drivers/net/pcs/pcs.c` and new headers in `include/linux/` that provide `phylink` and `FWNODE_PCS` functionality. The `FWNODE_PCS` functionality is enabled on amd64 when either ACPI or COMPILE_TEST is enabled, both of which are common. Importantly, these changes *aren't* limited to the Airoha platform; they're generic to the PCS framework and the core phylink functionality.
So, I need to configure the fuzzing appropriately. My reasoning is that this patch series introduces several changes: a generic PCS framework, modifications to the `phylink` subsystem to support multiple PCS devices, addition/removal notifications, dynamic recalculations, and new mutex locking (`pl->state_mutex`). These have the potential to introduce issues in many network device drivers. A particularly important point to test is the potential recursive deadlock introduced by changes to `phylink_validate_mac_and_pcs()` and interactions with `phylink_update_mac_pause_capabilities()`.
I've determined the following:
* **WorthFuzzing**: `true` (Absolutely)
* **Reasoning**: As described above, the generic nature of these changes and the new locking make this series a good target for fuzzing. It impacts core network functionality used by many drivers, and the interaction of the mutexes is a concern.
* **EnableConfigs**: I need `PHYLINK` and `FWNODE_PCS` enabled.
* **FocusSymbols**: I need to pick specific kernel functions as focus symbols to guide the fuzzer:
* `phylink_create`
* `phylink_destroy`
* `phylink_pcs_change`
* `phylink_update_mac_pause_capabilities`
* `phylink_ethtool_ksettings_set`
* `fwnode_pcs_add_provider`
* `fwnode_pcs_del_provider`
* `fwnode_pcs_get`
* `fwnode_pcs_get_from_provider`
* `fwnode_pcs_matches_provider`
* `fwnode_phylink_pcs_count`
* `fwnode_phylink_pcs_parse`
* `register_fwnode_pcs_notifier`
* `unregister_fwnode_pcs_notifier`
These functions are all specific to the PCS/phylink frameworks and are not ubiquitous kernel functions. They are all exported symbols, so should be accessible to coverage based fuzzers. I've also carefully avoided static functions that might be inlined.
Now, I can confidently invoke `set-results` with these parameters.
|
| 46/2 | 2026/10/09 22:02 | tool | set-results |
0mArgs:{
"EnableConfigs": [
"PHYLINK",
"FWNODE_PCS"
],
"FocusSymbols": [
"phylink_create",
"phylink_destroy",
"phylink_pcs_change",
"phylink_update_mac_pause_capabilities",
"phylink_ethtool_ksettings_set",
"fwnode_phylink_pcs_parse",
"fwnode_phylink_pcs_count",
"fwnode_pcs_add_provider",
"fwnode_pcs_del_provider",
"fwnode_pcs_matches_provider",
"register_fwnode_pcs_notifier",
"unregister_fwnode_pcs_notifier"
],
"Reasoning": "The patch series introduces a new generic Ethernet PCS firmware node framework (drivers/net/pcs/pcs.c) and makes significant modifications to the core phylink subsystem (drivers/net/phy/phylink.c) to handle multiple PCS devices, dynamic interface mask updates, and hotplug PCS provider notifications. Phylink is reachable via standard virtualized netdevices (including USB Ethernet devices like asix and lan78xx, DSA, and PCIe drivers like r8169). Furthermore, the locking modifications introduce mutex acquisition of pl-\u003estate_mutex in phylink_validate_mac_and_pcs(), which creates a recursive deadlock hazard in reachable call paths like phylink_update_mac_pause_capabilities(). Therefore, the changes affect reachable code and warrant fuzzing.",
"WorthFuzzing": true
}Results: {
"EnableConfigs": [
"PHYLINK",
"FWNODE_PCS"
],
"FocusSymbols": [
"phylink_create",
"phylink_destroy",
"phylink_pcs_change",
"phylink_update_mac_pause_capabilities",
"phylink_ethtool_ksettings_set",
"fwnode_phylink_pcs_parse",
"fwnode_phylink_pcs_count",
"fwnode_pcs_add_provider",
"fwnode_pcs_del_provider",
"fwnode_pcs_matches_provider",
"register_fwnode_pcs_notifier",
"unregister_fwnode_pcs_notifier"
],
"Reasoning": "The patch series introduces a new generic Ethernet PCS firmware node framework (drivers/net/pcs/pcs.c) and makes significant modifications to the core phylink subsystem (drivers/net/phy/phylink.c) to handle multiple PCS devices, dynamic interface mask updates, and hotplug PCS provider notifications. Phylink is reachable via standard virtualized netdevices (including USB Ethernet devices like asix and lan78xx, DSA, and PCIe drivers like r8169). Furthermore, the locking modifications introduce mutex acquisition of pl-\u003estate_mutex in phylink_validate_mac_and_pcs(), which creates a recursive deadlock hazard in reachable call paths like phylink_update_mac_pause_capabilities(). Therefore, the changes affect reachable code and warrant fuzzing.",
"WorthFuzzing": true
} |
| 47/1 | 2026/10/09 22:02 | action | If |
2mArgs:{
"WorthFuzzing": true
}Results: null |
| 48/2 | 2026/10/09 22:02 | agent | kmsan-evaluator |
2mModel:core Args: null Results: {
"KMSANReasoning": "The patch series introduces a new firmware-node (fwnode) PCS subsystem framework, adds support for Airoha PCS hardware (common and AN7581-specific drivers), and updates the phylink core and the Airoha Ethernet driver to support dynamic PCS discovery and hotplug notifications.\n\nAn audit of the changes shows no uninitialized memory risks:\n1. All newly allocated kernel heap objects and arrays are zero-initialized at allocation time:\n - `struct fwnode_pcs_provider` uses `kzalloc_obj`.\n - Device resources use `devres_alloc` and `devm_kzalloc` / `devm_kcalloc` (e.g., `struct airoha_pcs_priv`, port arrays, regmap field arrays).\n - Temporary arrays such as `pcss` in `phylink_fill_available_pcs()` are allocated via `kzalloc_objs`.\n - `struct phylink` is allocated with `kzalloc_obj`.\n2. All local stack variables across new and modified functions (such as register read values, status flags, and temporary pointers) are explicitly initialized at declaration or safely populated before read.\n3. No data is copied to user space via `copy_to_user`, `put_user`, Netlink attributes, ioctls, or socket buffers. The addition of `.get_link_ksettings` in `airoha_eth.c` delegates to `phylink_ethtool_ksettings_get()`, which operates on an `ethtool_link_ksettings` structure already zeroed by the ethtool core.\n4. Any potential risks introduced by the patch involve list operations, reference counting (`fwnode_handle_get`/`put`), locking under `state_mutex`/`rtnl_lock`, or lifecycle management. These classes of bugs are already covered by standard KASAN, LOCKDEP, and general kernel debuggers.\n\nTherefore, there is no risk of uninitialized memory reads or information leaks that would justify a dedicated KMSAN session.",
"NeedsKMSAN": false
}Instruction: You are an expert Linux kernel security engineer specializing in kernel memory
error detectors (KASAN and KMSAN). Your job is to review the provided patch series and
determine if the code changes justify spawning a dedicated KMSAN (KernelMemorySanitizer)
fuzzing session in addition to standard KASAN fuzzing.
CRITICAL DISTINCTION BETWEEN KASAN AND KMSAN:
- Standard KASAN kernel builds (upstream-apparmor-kasan.config) already enable
a comprehensive suite of debugging tools and sanitizers, including KASAN
(out-of-bounds accesses, use-after-free, double free, invalid free), LOCKDEP
(locking bugs and deadlocks), UB-sanitizers, and memory corruption checks.
- KMSAN (KernelMemorySanitizer) detects reads of UNINITIALIZED memory (stack, heap,
or page allocations) and kernel-to-user memory info-leaks.
Rule: THERE IS NO SENSE IN RUNNING A KMSAN SESSION IF A BUG CAN BE CAUGHT BY KASAN,
LOCKDEP, OR OTHER STANDARD BUG DETECTORS.
A dedicated KMSAN fuzzing session incurs significant resource costs. You must ONLY
set NeedsKMSAN=true if the code changes introduce or expose UNINITIALIZED MEMORY risks
that are detected ONLY by KMSAN.
Look holistically at the patch series and surrounding code. Even if no direct
uninitialized field accesses or new buffer allocations are added in the diff itself,
a patch may alter control flow, bounds checking, or data length calculations in ways
that change how the rest of the code operates on existing buffers (e.g. allowing
uninitialized stack/heap memory to be read, copied to user space, or used in control
flow). Do not hesitate to use your code access tools to inspect the surrounding code,
called functions, and callers.
Set NeedsKMSAN=true ONLY IF the patch introduces or modifies:
1. Kernel structures sent to user space (via copy_to_user, put_user, netlink skb
attributes, ioctl output arguments, socket options, or BPF buffers) where fields
or structure padding might not be fully initialized/zeroed.
2. Conditional logic or branching that depends on potentially uninitialized variables
or struct fields.
3. Allocation or initialization of complex data structures where uninitialized fields
could be read later in reachable code paths.
4. Bounds checks, lengths, or logic in a way that allows surrounding code to access
uninitialized bytes of existing buffers.
Set NeedsKMSAN=false IF:
- The code changes primarily risk out-of-bounds access, array overflows, NULL pointer
dereferences, locking deadlocks, or use-after-free bugs (these are already caught
by KASAN, LOCKDEP, or standard bug detectors).
- All stack/heap structures touched or introduced by the patch are fully zeroed
or initialized (e.g. using = {0}, memset, kzalloc) before being read or copied.
- The patch does not introduce any risk of uninitialized memory usage or info-leaks.
Use your code access tools to inspect the surrounding code if necessary, then provide
detailed KMSANReasoning contrasting KASAN vs KMSAN applicability for this patch.
Prefer calling several tools at the same time to save round-trips.
Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.
Prompt: Target architecture: amd64
For your convenience, here is the diff of the changes:
commit fa50ce9901b4f80b61fb05d00ca168060d135a73
Author: syz-cluster <triage@syzkaller.com>
Date: Fri Oct 9 21:55:49 2026 +0000
syz-cluster: applied patch under review
diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 0000000000000..9c1d116c1b016
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,261 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+ the various Serdes port supporting different Media Independent Interface
+ (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+ compatible:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+ - airoha,an7581-pcs-pcie
+ - airoha,an7581-pcs-usb
+
+ reg:
+ minItems: 6
+ maxItems: 15
+
+ reg-names:
+ minItems: 6
+ maxItems: 15
+
+ airoha,scu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the SCU node required to configure
+ the serdes line to the correct interface mode.
+
+ phys:
+ maxItems: 1
+
+ "#pcs-cells": true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#pcs-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: USXGMII reg
+ - description: HSGMII rate adaption reg
+ - description: PCS Analog register
+ - description: PCS PMA (Physical Medium Attachment) register
+
+ reg-names:
+ items:
+ - const: pcs_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: usxgmii
+ - const: hsgmii_rate_adp
+ - const: pcs_ana
+ - const: pcs_pma
+
+ phys: false
+
+ "#pcs-cells":
+ const: 0
+
+ required:
+ - airoha,scu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: airoha,an7581-pcs-pcie
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC 0 reg
+ - description: HSGMII AN 0 reg
+ - description: HSGMII PCS 0 reg
+ - description: MULTI SGMII 0 reg
+ - description: USXGMII 0 reg
+ - description: HSGMII rate adaption 0 reg
+ - description: PCS MAC 1 reg
+ - description: HSGMII AN 1 reg
+ - description: HSGMII PCS 1 reg
+ - description: MULTI SGMII 1 reg
+ - description: USXGMII 1 reg
+ - description: HSGMII rate adaption 1 reg
+ - description: PCS Analog register
+ - description: PCS PMA (Physical Medium Attachment) 0 register
+ - description: PCS PMA (Physical Medium Attachment) 1 register
+
+ reg-names:
+ items:
+ - const: pcs_mac0
+ - const: hsgmii_an0
+ - const: hsgmii_pcs0
+ - const: multi_sgmii0
+ - const: usxgmii0
+ - const: hsgmii_rate_adp0
+ - const: pcs_mac1
+ - const: hsgmii_an1
+ - const: hsgmii_pcs1
+ - const: multi_sgmii1
+ - const: usxgmii1
+ - const: hsgmii_rate_adp1
+ - const: pcs_ana
+ - const: pcs_pma0
+ - const: pcs_pma1
+
+ phys: false
+
+ "#pcs-cells":
+ const: 1
+
+ required:
+ - airoha,scu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: airoha,an7581-pcs-usb
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: PCS MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: HSGMII rate adaption reg
+ - description: PCS Analog register
+
+ reg-names:
+ items:
+ - const: pcs_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: hsgmii_rate_adp
+ - const: pcs_ana
+
+ airoha,scu: false
+
+ "#pcs-cells":
+ const: 0
+
+ required:
+ - phys
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ pcs@1fa08000 {
+ compatible = "airoha,an7581-pcs-pon";
+ reg = <0x1fa08000 0x1000>,
+ <0x1fa80000 0x60>,
+ <0x1fa80a00 0x164>,
+ <0x1fa84000 0x450>,
+ <0x1fa85900 0x338>,
+ <0x1fa86000 0x300>,
+ <0x1fa8a000 0x1000>,
+ <0x1fa8b000 0x1000>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "pcs_ana", "pcs_pma";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa09000 {
+ compatible = "airoha,an7581-pcs-eth";
+ reg = <0x1fa09000 0x1000>,
+ <0x1fa70000 0x60>,
+ <0x1fa70a00 0x164>,
+ <0x1fa74000 0x450>,
+ <0x1fa75900 0x338>,
+ <0x1fa76000 0x300>,
+ <0x1fa7a000 0x1000>,
+ <0x1fa7b000 0x1000>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "pcs_ana", "pcs_pma";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa04000 {
+ compatible = "airoha,an7581-pcs-pcie";
+ reg = <0x1fa04000 0x1000>,
+ <0x1fa50000 0x60>,
+ <0x1fa50a00 0x164>,
+ <0x1fa54000 0x450>,
+ <0x1fa55900 0x338>,
+ <0x1fa56000 0x300>,
+ <0x1fa05000 0x1000>,
+ <0x1fa60000 0x60>,
+ <0x1fa60a00 0x164>,
+ <0x1fa64000 0x450>,
+ <0x1fa65900 0x338>,
+ <0x1fa66000 0x300>,
+ <0x1fa5a000 0x1000>,
+ <0x1fa5b000 0x1000>,
+ <0x1fa5c000 0x1000>;
+ reg-names = "pcs_mac0", "hsgmii_an0", "hsgmii_pcs0",
+ "multi_sgmii0", "usxgmii0",
+ "hsgmii_rate_adp0",
+ "pcs_mac1", "hsgmii_an1", "hsgmii_pcs1",
+ "multi_sgmii1", "usxgmii1",
+ "hsgmii_rate_adp1",
+ "pcs_ana", "pcs_pma0", "pcs_pma1";
+
+ airoha,scu = <&scuclk>;
+ #pcs-cells = <1>;
+ };
+
+ pcs@1fa07000 {
+ compatible = "airoha,an7581-pcs-usb";
+ reg = <0x1fa07000 0x1000>,
+ <0x1fa90000 0x60>,
+ <0x1fa90a00 0x164>,
+ <0x1fa94000 0x450>,
+ <0x1fa96000 0x300>,
+ <0x1fa9a000 0x600>;
+ reg-names = "pcs_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "hsgmii_rate_adp","pcs_ana";
+
+ phys = <&usb0_phy PHY_TYPE_USB3>;
+
+ #pcs-cells = <0>;
+ };
diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst
index 44a422ad3b055..3fce8f6ac089e 100644
--- a/Documentation/networking/index.rst
+++ b/Documentation/networking/index.rst
@@ -28,6 +28,7 @@ Contents:
net_failover
page_pool
phy
+ pcs
sfp-phylink
alias
bridge
diff --git a/Documentation/networking/pcs.rst b/Documentation/networking/pcs.rst
new file mode 100644
index 0000000000000..2cae702319484
--- /dev/null
+++ b/Documentation/networking/pcs.rst
@@ -0,0 +1,234 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=============
+PCS Subsystem
+=============
+
+The PCS (Physical Coding Sublayer) subsystem handles the registration and lookup
+of PCS devices. These devices contain the upper sublayers of the Ethernet
+physical layer, generally handling framing, scrambling, and encoding tasks. PCS
+devices may also include PMA (Physical Medium Attachment) components. PCS
+devices transfer data between the Link-layer MAC device, and the rest of the
+physical layer, typically via a serdes. The output of the serdes may be
+connected more-or-less directly to the medium when using fiber-optic or
+backplane connections (1000BASE-SX, 1000BASE-KX, etc). It may also communicate
+with a separate PHY (such as over SGMII) which handles the connection to the
+medium (such as 1000BASE-T).
+
+Remark on usage of .mac_select_pcs and fw_node PCS
+--------------------------------------------------
+
+There are generally two ways to look up a PCS device.
+
+1. MAC OP struct .mac_select_pcs (considered deprecated)
+2. Internal PCS handling with ``num_possible_pcs`` and ``fill_available_pcs``
+
+Implementation 1 leaves the entire handling of the PCS to the MAC
+driver with the selection of the PCS driven by .mac_select_pcs.
+Custom implementations are required if the PCS is external to the MAC
+and needs to be handled by a separate driver.
+
+Implementation 2 makes the phylink core code to select the PCS
+provided by ``num_possible_pcs`` and ``fill_available_pcs`` either
+via internal MAC handling or firmware node (fwnode)
+
+Implementation 1 is considered deprecated and it's suggested to
+switch to implementation 2 and where possible switch to firmware
+node design.
+
+.. _pcs_fwnode:
+
+Looking up PCS Devices (fwnode implementation)
+-----------------------------------------------
+
+The lookup of a PCS device follows the common producer/consumer implementation
+used by similar subsystems with a ``#pcs-cells`` on the producer and a
+``pcs-handle`` property on the consumer::
+
+ pcs: pcs {
+ // ...
+ #pcs-cells = <0>;
+ };
+
+ ethernet-controller {
+ // ...
+ pcs-handle = <&pcs>;
+ };
+
+On :c:func:`phylink_create`, phylink will use the ``num_possible_pcs``
+value and ``fill_available_pcs`` helper function in
+:c:struct:`phylink_config` to compose the list of available PCS that can be
+used for the phylink instance.
+
+Phylink will then internally handle the selection of the correct PCS for
+the requested interface mode based on the interface modes configured in
+``pcs_interfaces`` in :c:struct:`phylink_config` struct and
+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.
+
+A PCS is considered eligible when the requested interface mode is present
+in both ``pcs_interfaces`` in :c:struct:`phylink_config` struct and
+``supported_interfaces`` in :c:struct:`phylink_pcs` struct.
+
+``supported_interfaces`` describes all interface modes supported by the MAC,
+whereas ``pcs_interfaces`` identifies the subset that require PCS selection.
+
+For the special implementation where the PCS is internal or part of the MAC
+and a dedicated driver is not needed, it's possible to leave the implementation
+of the PCS to the MAC driver and just implement the ``num_possible_pcs``
+value and ``fill_available_pcs`` helper function in
+:c:struct:`phylink_config` referencing the local :c:struct:`phylink_pcs`
+struct allocated from the MAC driver.
+
+.. _pcs_consumer:
+
+Using PCS Devices
+-----------------
+
+It's mandatory to either implement the ``mac_select_pcs`` callback
+of :c:struct:`phylink_mac_ops` or ``num_possible_pcs`` and ``fill_available_pcs``
+of :c:struct:`phylink_config` to use a PCS for a MAC.
+
+The fwnode implementation exposes simple helpers to parse the PCS from
+the fwnode :c:func:`fwnode_phylink_pcs_count` and
+:c:func:`fwnode_phylink_pcs_parse`. The :c:func:`fwnode_phylink_pcs_count` helper
+takes the fwnode where the ``pcs-handle`` should be parsed and return the
+number of PCS entries described in the fwnode.
+The :c:func:`fwnode_phylink_pcs_parse` helper takes three arguments,
+the fwnode where the ``pcs-handle`` should be parsed, an allocated array
+of :c:struct:`phylink_pcs` pointer where to put the parsed PCS from the fwnode
+and the maximum number of PCS to parse.
+Contrary to :c:func:`fwnode_phylink_pcs_count`, :c:func:`fwnode_phylink_pcs_parse`
+helper fills the allocated array with ONLY the available PCS and return the
+number of available PCS found. PCS that returns -ENODEV will be skipped and
+won't be inserted in the allocated array.
+
+A phylink instance may use multiple PCS devices. The maximum number is reported
+through ``num_possible_pcs``.
+
+It's mandatory to specify for what interface a PCS is needed. This can be done
+by filling the ``pcs_interfaces`` in :c:struct:`phylink_config` struct.
+If the requested interface mode is not present in this bitmask, phylink does
+not search for a PCS for that specific mode. (example MAC doesn't need a PCS
+for SGMII but require one for USXGMII)
+
+With the use of the :c:func:`fwnode_phylink_pcs_parse` a common implementation
+is the following::
+
+ static int mac_fill_available_pcs(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs)
+ {
+ struct device *dev = config->dev;
+
+ return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
+ num_possible_pcs);
+ }
+
+ static int mac_setup_phylink(struct net_device *netdev)
+ {
+ struct phylink_config *config;
+
+ // ...
+
+ config->dev = &netdev->dev;
+
+ // ...
+
+ // Parse possible PCS and fill num_possible_pcs.
+ config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(&netdev->dev));
+ config->fill_available_pcs = mac_fill_available_pcs;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces);
+
+ // PCS required only for USXGMII
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, config->pcs_interfaces);
+
+ phylink = phylink_create(config, //...
+
+It's worth to mention that it's phylink code that takes care of allocating
+the array of :c:struct:`phylink_pcs` pointer for ``fill_available_pcs``
+callback based on the value set in ``num_possible_pcs`` for
+:c:struct:`phylink_config` struct.
+
+The ``fill_available_pcs`` callback must not write more than
+``num_possible_pcs`` entries. The third argument may be used to validate
+that there is enough space to fill all the available PCS in the passed array
+of :c:struct:`phylink_pcs` pointer.
+
+The ``fill_available_pcs`` callback is called only on :c:func:`phylink_create`
+and is used only to compose the initial available PCS list. Ownership of PCS
+is held by phylink.
+
+.. _pcs_producer:
+
+Writing PCS Drivers
+-------------------
+
+To write a PCS driver, first implement :c:struct:`phylink_pcs_ops`. Then,
+register your PCS in your probe function using :c:func:`fwnode_pcs_add_provider`.
+The :c:func:`fwnode_pcs_add_provider` takes three arguments, the fwnode where
+the PCS provider should be registered to, a xlate function to return the requested
+PCS based on ``#pcs-cells`` and a pointer to reference private data for the xlate
+function.
+
+The PCS will then be registered to a global list of PCS provider that the
+PCS fwnode implementation will use to parse it.
+
+For the simple case where the PCS driver expose a single PCS,
+:c:func:`fwnode_pcs_simple_xlate` can be used as the xlate function.
+
+You must call :c:func:`fwnode_pcs_del_provider` from your remove function
+on driver detach.
+
+A devm variant, :c:func:`devm_fwnode_pcs_add_provider`, is available to
+automatically release the PCS provider on driver detach.
+
+It's worth to mention that xlate function MUST reference already allocated
+:c:struct:`phylink_pcs` pointer and MUST NOT dynamically allocate new PCS.
+The returned pointer is used to identify the PCS across provider lookup and
+removal notifications.
+
+Late PCS registration handling
+------------------------------
+
+It's possible that a PCS becomes available after the MAC finished probing.
+Contrary to the usual producer/consumer implementation, when a PCS is not
+registered and can't be found, the fwnode parser helper returns ``-ENODEV``
+instead of ``-EPROBE_DEFER``.
+
+This is to prevent race condition with particular devices that register
+MAC and PCS with USB or PCIe and require the MAC to be registered before
+the PCS.
+
+The phylink logic correctly handle this special case and keep the phylink
+instance in a fail condition.
+
+The PCS fwnode implementation provides a notifier to which each phylink
+instance with a non-empty ``pcs_interfaces`` in :c:type:`phylink_config`
+registers. When a new PCS provider is registered, the notifier is called
+triggering the :c:func:`pcs_provider_notify` function.
+
+Function :c:func:`pcs_provider_notify` will check if the just added PCS
+should be used by the phylink instance. If it should be used then,
+it's added to the internal list of available PCS and a phylink major
+config is forced.
+
+If a phylink instance was in a failure state, with the just added PCS
+now part of the available PCS internal phylink list, provided all other
+conditions are satisfied, the configuration is retried and the failure
+condition is cleared.
+
+API Reference
+-------------
+
+.. kernel-doc:: include/linux/phylink.h
+ :identifiers: phylink_pcs
+
+.. kernel-doc:: include/linux/pcs/pcs.h
+ :internal:
+
+.. kernel-doc:: include/linux/pcs/pcs-provider.h
+ :internal:
diff --git a/Documentation/networking/sfp-phylink.rst b/Documentation/networking/sfp-phylink.rst
index 5bf285d73e8a1..306505118eba9 100644
--- a/Documentation/networking/sfp-phylink.rst
+++ b/Documentation/networking/sfp-phylink.rst
@@ -311,33 +311,20 @@ this documentation.
priv->pcs = lynx_pcs_create_mdiodev(bus, 0);
- Some PCS can be recovered based on firmware information:
+ PCS that should be recovered based on firmware information should implement
+ the external PCS as a :ref:`PCS provider <pcs_producer>` and reference it
+ with the use of PCS fwnode helper :ref:`PCS fwnode helper <pcs_fwnode>`.
- .. code-block:: c
-
- priv->pcs = lynx_pcs_create_fwnode(of_fwnode_handle(node));
-
-12. Populate the :c:func:`mac_select_pcs` callback and add it to your
- :c:type:`struct phylink_mac_ops <phylink_mac_ops>` set of ops. This function
- must return a pointer to the relevant :c:type:`struct phylink_pcs <phylink_pcs>`
- that will be used for the requested link configuration:
-
- .. code-block:: c
-
- static struct phylink_pcs *foo_select_pcs(struct phylink_config *config,
- phy_interface_t interface)
- {
- struct foo_priv *priv = container_of(config, struct foo_priv,
- phylink_config);
-
- if ( /* 'interface' needs a PCS to function */ )
- return priv->pcs;
+12. Populate the :c:var:`num_possible_pcs` value and
+ :c:func:`fill_available_pcs` callback and add it to your
+ :c:type:`struct phylink_config <phylink_config>`.
- return NULL;
- }
+ Refer to :ref:`Documentation/networking/pcs.rst <pcs_consumer>` for
+ further details and examples.
- See :c:func:`mvpp2_select_pcs` for an example of a driver that has multiple
- internal PCS.
+ Notice that the previous implementation of populating
+ :c:func:`mac_select_pcs` is considered deprecated in favor of the new
+ described above.
13. Fill-in all the :c:type:`phy_interface_t <phy_interface_t>` (i.e. all MAC to
PHY link modes) that your MAC can output. The following example shows a
diff --git a/MAINTAINERS b/MAINTAINERS
index 509b35b5a0e7a..d8533e36941c7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9759,6 +9759,15 @@ F: include/uapi/linux/if_bridge.h
F: include/linux/netfilter_bridge/
F: net/bridge/
+ETHERNET PCS SUBSYSTEM
+M: Christian Marangi <ansuelsmth@gmail.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/networking/pcs.rst
+F: drivers/net/pcs/pcs.c
+F: include/linux/pcs/pcs-provider.h
+F: include/linux/pcs/pcs.h
+
ETHERNET PHY LIBRARY
M: Andrew Lunn <andrew@lunn.ch>
M: Heiner Kallweit <hkallweit1@gmail.com>
diff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig
index 1f6640a15fc94..5c54a07d2a768 100644
--- a/drivers/net/ethernet/airoha/Kconfig
+++ b/drivers/net/ethernet/airoha/Kconfig
@@ -20,6 +20,8 @@ config NET_AIROHA
depends on NET_DSA || !NET_DSA
select NET_AIROHA_NPU
select PAGE_POOL
+ select PCS_AIROHA
+ select PHYLINK
help
This driver supports the gigabit ethernet MACs in the
Airoha SoC family.
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index b164a78ddac9d..81a8da721c13a 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -6,6 +6,7 @@
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/of_reserved_mem.h>
+#include <linux/pcs/pcs.h>
#include <linux/platform_device.h>
#include <linux/tcp.h>
#include <linux/u64_stats_sync.h>
@@ -2194,10 +2195,18 @@ static int airoha_dev_open(struct net_device *netdev)
return -EBUSY;
}
+ err = phylink_of_phy_connect(dev->phylink, netdev->dev.of_node, 0);
+ if (err) {
+ netdev_err(netdev, "could not attach PHY: %d\n", err);
+ return err;
+ }
+
+ phylink_start(dev->phylink);
+
netif_tx_start_all_queues(netdev);
err = airoha_set_vip_for_gdm_port(dev, true);
if (err)
- return err;
+ goto err_phy_stop;
if (netdev_uses_dsa(netdev))
airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
@@ -2219,6 +2228,12 @@ static int airoha_dev_open(struct net_device *netdev)
airoha_dev_lro_enable(dev);
return 0;
+
+err_phy_stop:
+ phylink_stop(dev->phylink);
+ phylink_disconnect_phy(dev->phylink);
+
+ return err;
}
static int airoha_dev_stop(struct net_device *netdev)
@@ -2226,6 +2241,8 @@ static int airoha_dev_stop(struct net_device *netdev)
struct airoha_gdm_dev *dev = netdev_priv(netdev);
struct airoha_gdm_port *port = dev->port;
+ phylink_stop(dev->phylink);
+
netif_tx_disable(netdev);
airoha_set_vip_for_gdm_port(dev, false);
@@ -2239,6 +2256,8 @@ static int airoha_dev_stop(struct net_device *netdev)
if (netdev->features & NETIF_F_LRO)
airoha_dev_lro_disable(dev);
+ phylink_disconnect_phy(dev->phylink);
+
return 0;
}
@@ -2829,6 +2848,24 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,
} while (u64_stats_fetch_retry(&dev->stats.syncp, start));
}
+static int
+airoha_ethtool_get_link_ksettings(struct net_device *netdev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ return phylink_ethtool_ksettings_get(dev->phylink, cmd);
+}
+
+static int
+airoha_ethtool_set_link_ksettings(struct net_device *netdev,
+ const struct ethtool_link_ksettings *cmd)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+
+ return phylink_ethtool_ksettings_set(dev->phylink, cmd);
+}
+
static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev,
int channel, enum tx_sched_mode mode,
const u16 *weights, u8 n_weights)
@@ -3696,7 +3733,8 @@ static const struct ethtool_ops airoha_ethtool_ops = {
.get_drvinfo = airoha_ethtool_get_drvinfo,
.get_eth_mac_stats = airoha_ethtool_get_mac_stats,
.get_rmon_stats = airoha_ethtool_get_rmon_stats,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .get_link_ksettings = airoha_ethtool_get_link_ksettings,
+ .set_link_ksettings = airoha_ethtool_set_link_ksettings,
.get_link = ethtool_op_get_link,
};
@@ -3752,6 +3790,155 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
return false;
}
+/* Nothing to do in MAC, everything is handled in PCS */
+static void airoha_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+}
+
+static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy,
+ unsigned int mode, phy_interface_t interface,
+ int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+ struct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev,
+ phylink_config);
+ struct airoha_gdm_port *port = dev->port;
+ struct airoha_eth *eth = dev->eth;
+ u32 frag_size_tx, frag_size_rx;
+
+ /* TX/RX frag is configured only for GDM4 */
+ if (port->id != AIROHA_GDM4_IDX)
+ return;
+
+ switch (speed) {
+ case SPEED_10000:
+ case SPEED_5000:
+ frag_size_tx = 8;
+ frag_size_rx = 8;
+ break;
+ case SPEED_2500:
+ frag_size_tx = 2;
+ frag_size_rx = 1;
+ break;
+ default:
+ frag_size_tx = 1;
+ frag_size_rx = 0;
+ break;
+ }
+
+ mutex_lock(&port->link_lock);
+
+ /* Configure TX/RX frag based on speed */
+ if (dev->nbq == 1) {
+ airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG,
+ GDM4_SGMII1_TX_FRAG_SIZE_MASK,
+ FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK,
+ frag_size_tx));
+
+ airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG,
+ GDM4_SGMII1_RX_FRAG_SIZE_MASK,
+ FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK,
+ frag_size_rx));
+ } else {
+ airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG,
+ GDM4_SGMII0_TX_FRAG_SIZE_MASK,
+ FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK,
+ frag_size_tx));
+
+ airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG,
+ GDM4_SGMII0_RX_FRAG_SIZE_MASK,
+ FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK,
+ frag_size_rx));
+ }
+
+ mutex_unlock(&port->link_lock);
+}
+
+/* Nothing to do in MAC, everything is handled in PCS */
+static void airoha_mac_link_down(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+}
+
+static const struct phylink_mac_ops airoha_phylink_ops = {
+ .mac_config = airoha_mac_config,
+ .mac_link_up = airoha_mac_link_up,
+ .mac_link_down = airoha_mac_link_down,
+};
+
+static int airoha_fill_available_pcs(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs)
+{
+ struct device *dev = config->dev;
+
+ return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs,
+ num_possible_pcs);
+}
+
+static int airoha_setup_phylink(struct net_device *netdev)
+{
+ struct airoha_gdm_dev *dev = netdev_priv(netdev);
+ struct device_node *np = netdev->dev.of_node;
+ struct airoha_gdm_port *port = dev->port;
+ struct phylink_config *config;
+ phy_interface_t phy_mode;
+ struct phylink *phylink;
+ int err;
+
+ err = of_get_phy_mode(np, &phy_mode);
+ if (err) {
+ dev_err(&netdev->dev, "incorrect phy-mode\n");
+ return err;
+ }
+
+ config = &dev->phylink_config;
+ config->dev = &netdev->dev;
+ config->type = PHYLINK_NETDEV;
+
+ /*
+ * GDM1 only supports internal for Embedded Switch
+ * and doesn't require a PCS.
+ */
+ if (port->id == AIROHA_GDM1_IDX) {
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10000FD;
+
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ } else {
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000 |
+ MAC_2500FD | MAC_5000FD | MAC_10000FD;
+
+ config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config->dev));
+ config->fill_available_pcs = airoha_fill_available_pcs;
+
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ config->supported_interfaces);
+
+ phy_interface_copy(config->pcs_interfaces,
+ config->supported_interfaces);
+ }
+
+ phylink = phylink_create(config, of_fwnode_handle(np),
+ phy_mode, &airoha_phylink_ops);
+ if (IS_ERR(phylink))
+ return PTR_ERR(phylink);
+
+ dev->phylink = phylink;
+
+ return 0;
+}
+
static int airoha_alloc_gdm_device(struct airoha_eth *eth,
struct airoha_gdm_port *port,
int nbq, struct device_node *np)
@@ -3815,7 +4002,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
dev->nbq = nbq;
port->devs[index] = dev;
- return 0;
+ return airoha_setup_phylink(netdev);
}
static int airoha_alloc_gdm_port(struct airoha_eth *eth,
@@ -3851,6 +4038,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
port->id = id;
spin_lock_init(&port->stats_lock);
+ mutex_init(&port->link_lock);
eth->ports[p] = port;
err = airoha_metadata_dst_alloc(port);
@@ -4047,6 +4235,8 @@ static int airoha_probe(struct platform_device *pdev)
netdev = netdev_from_priv(dev);
if (netdev->reg_state == NETREG_REGISTERED)
unregister_netdev(netdev);
+ if (dev->phylink)
+ phylink_destroy(dev->phylink);
of_node_put(netdev->dev.of_node);
}
airoha_metadata_dst_free(port);
@@ -4085,6 +4275,7 @@ static void airoha_remove(struct platform_device *pdev)
netdev = netdev_from_priv(dev);
unregister_netdev(netdev);
+ phylink_destroy(dev->phylink);
of_node_put(netdev->dev.of_node);
}
airoha_metadata_dst_free(port);
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index d270729e22ff9..909e75fec2797 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -612,6 +612,9 @@ struct airoha_gdm_dev {
* QDMA migration.
*/
spinlock_t txq_lock[AIROHA_NUM_NETDEV_TX_RINGS];
+
+ struct phylink *phylink;
+ struct phylink_config phylink_config;
};
struct airoha_gdm_port {
@@ -621,6 +624,8 @@ struct airoha_gdm_port {
/* protect concurrent hw_stats accesses */
spinlock_t stats_lock;
+ /* protect concurrent GDM4 register access */
+ struct mutex link_lock;
struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
};
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index 07dd04859fde8..94d53d4c3ab70 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -371,6 +371,18 @@
#define IP_FRAGMENT_PORT_MASK GENMASK(8, 5)
#define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0)
+#define REG_FE_GDM4_TMBI_FRAG 0x2028
+#define GDM4_SGMII1_TX_WEIGHT_MASK GENMASK(31, 26)
+#define GDM4_SGMII1_TX_FRAG_SIZE_MASK GENMASK(25, 16)
+#define GDM4_SGMII0_TX_WEIGHT_MASK GENMASK(15, 10)
+#define GDM4_SGMII0_TX_FRAG_SIZE_MASK GENMASK(9, 0)
+
+#define REG_FE_GDM4_RMBI_FRAG 0x202c
+#define GDM4_SGMII1_RX_WEIGHT_MASK GENMASK(31, 26)
+#define GDM4_SGMII1_RX_FRAG_SIZE_MASK GENMASK(25, 16)
+#define GDM4_SGMII0_RX_WEIGHT_MASK GENMASK(15, 10)
+#define GDM4_SGMII0_RX_FRAG_SIZE_MASK GENMASK(9, 0)
+
#define REG_MC_VLAN_EN 0x2100
#define MC_VLAN_EN_MASK BIT(0)
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index e417fd66f660a..8fae619f24322 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,12 @@
menu "PCS device drivers"
+config FWNODE_PCS
+ bool "PCS Firmware Node"
+ depends on ACPI || OF || COMPILE_TEST
+ help
+ Firmware node PCS accessors
+
config PCS_XPCS
tristate "Synopsys DesignWare Ethernet XPCS"
select PHYLINK
@@ -35,4 +41,6 @@ config PCS_RZN1_MIIC
Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to
RMII/RGMII, or can be set in pass-through mode for MII.
+source "drivers/net/pcs/airoha/Kconfig"
+
endmenu
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b900..91593aa8d9266 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for Linux PCS drivers
+obj-$(CONFIG_FWNODE_PCS) += pcs.o
pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
pcs-xpcs-nxp.o pcs-xpcs-wx.o
@@ -8,3 +9,5 @@ obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o
obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
+
+obj-$(CONFIG_PCS_AIROHA) += airoha/
diff --git a/drivers/net/pcs/airoha/Kconfig b/drivers/net/pcs/airoha/Kconfig
new file mode 100644
index 0000000000000..1aa4c0d33b87d
--- /dev/null
+++ b/drivers/net/pcs/airoha/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PCS_AIROHA
+ tristate
+ select FWNODE_PCS
+
+config PCS_AIROHA_AN7581
+ tristate "Airoha AN7581 PCS driver"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ select PCS_AIROHA
+ help
+ This module provides helper to phylink for managing the Airoha
+ AN7581 PCS for SoC Ethernet and PON SERDES.
diff --git a/drivers/net/pcs/airoha/Makefile b/drivers/net/pcs/airoha/Makefile
new file mode 100644
index 0000000000000..c5201d5cc3569
--- /dev/null
+++ b/drivers/net/pcs/airoha/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PCS_AIROHA) := pcs-airoha.o
+pcs-airoha-objs := pcs-airoha-common.o
+ifdef CONFIG_PCS_AIROHA_AN7581
+pcs-airoha-objs += pcs-an7581.o
+endif
diff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c
new file mode 100644
index 0000000000000..d9ec0e97b746a
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c
@@ -0,0 +1,1303 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/rtnetlink.h>
+
+#include "pcs-airoha.h"
+
+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
+ AIROHA_SCU_ETH_XSI_SEL,
+ xsi_sel);
+}
+
+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel, wan_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PON_XSI_SEL,
+ xsi_sel);
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+ AIROHA_SCU_WAN_SEL,
+ wan_sel);
+}
+
+static void airoha_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ if (index == 0) {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_PCIE_XSI0_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI0_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI0_SEL,
+ xsi_sel);
+ } else {
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_PCIE_XSI1_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PCIE_XSI1_SEL,
+ xsi_sel);
+ }
+}
+
+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ int ret;
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ airoha_pcs_setup_scu_eth(priv, interface);
+ break;
+ case AIROHA_PCS_PON:
+ airoha_pcs_setup_scu_pon(priv, interface);
+ break;
+ case AIROHA_PCS_PCIE:
+ airoha_pcs_setup_scu_pcie(priv, index, interface);
+ break;
+ case AIROHA_PCS_USB:
+ break;
+ }
+
+ ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_set_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ /* Disable Hibernation */
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+ AIROHA_PCS_USXGMII_SPEED_SEL_H);
+
+ /* FIXME: wait Airoha */
+ /* Avoid PCS sending garbage to MAC in some HW revision (E0) */
+ regmap_write(maps->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+}
+
+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE,
+ priv->phy ? 0 : AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
+
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
+}
+
+static void airoha_pcs_init(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_init_sgmii(priv, index);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_init_hsgmii(priv, index);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_init_usxgmii(priv, index);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ /* Disable every interrupt */
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+ /* Clear interrupt */
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+}
+
+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv,
+ int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+
+ /* Disable every Interrupt */
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
+ AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
+ AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
+ AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
+
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
+
+ /* Clear any pending interrupt */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT);
+
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT);
+
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
+
+ /* Interrupt saddly seems to be not weel supported for Link Down.
+ * PCS Poll is a must to correctly read and react on Cable Deatch
+ * as only cable attach interrupt are fired and Link Down interrupt
+ * are fired only in special case like AN restart.
+ */
+}
+
+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return airoha_pcs_interrupt_init_sgmii(priv, index);
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ return airoha_pcs_interrupt_init_usxgmii(priv, index);
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
+ unsigned int neg_mode, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr = 0, lpa = 0;
+
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
+ &lpa);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+ lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
+ phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_hsgmii(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr = 0;
+
+ regmap_read(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+
+ state->link = !!(bmsr & BMSR_LSTATUS);
+ state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
+ state->speed = SPEED_2500;
+ state->duplex = DUPLEX_FULL;
+}
+
+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ const struct airoha_pcs_match_data *data = priv->data;
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 an_done = 0, lpa = 0;
+
+ /* Trigger HW workaround if needed. If an error is reported,
+ * consider link down and test again later.
+ */
+ if (data->rxlock_workaround && data->rxlock_workaround(priv, index)) {
+ state->link = false;
+ return;
+ }
+
+ /* Toggle AN Status */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_2, &an_done);
+
+ state->link = !!(lpa & MDIO_USXGMII_LINK);
+ state->an_complete = !!(an_done & AIROHA_PCS_USXGMII_PCS_AN_COMPLETE);
+
+ phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void airoha_pcs_get_state_10gbaser(struct airoha_pcs_priv *priv, int index,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 status = 0, curr_mode = 0;
+
+ /* Toggle AN Status */
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1,
+ &status);
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &curr_mode);
+
+ state->link = !!(status & AIROHA_PCS_USXGMII_RX_LINK_STUS);
+
+ switch (curr_mode & AIROHA_PCS_USXGMII_CUR_USXGMII_MODE) {
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G:
+ state->speed = SPEED_10000;
+ break;
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G:
+ state->speed = SPEED_5000;
+ break;
+ case AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G:
+ state->speed = SPEED_2500;
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ return;
+ }
+
+ state->duplex = DUPLEX_FULL;
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
+ unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_get_state_sgmii(priv, neg_mode, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_get_state_hsgmii(priv, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ airoha_pcs_get_state_usxgmii(priv, port->index, state);
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_get_state_10gbaser(priv, port->index, state);
+ break;
+ default:
+ return;
+ }
+}
+
+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ const struct airoha_pcs_match_data *data;
+ struct airoha_pcs_maps *maps;
+ int index = port->index;
+ u32 rate_adapt;
+ int ret;
+
+ maps = &priv->maps[port->index];
+ port->interface = interface;
+ data = priv->data;
+
+ /* Apply Analog and Digital configuration for PCS */
+ if (data->bringup) {
+ ret = data->bringup(priv, index, interface);
+ if (ret)
+ return ret;
+ }
+
+ /* Set final configuration for various modes */
+ airoha_pcs_init(priv, index, interface);
+
+ /* Configure Interrupt for various modes */
+ airoha_pcs_interrupt_init(priv, index, interface);
+
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ rate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS;
+
+ /* AN Auto Settings (Rate Adaptation) */
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+ else
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
+ } else {
+ regmap_clear_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+
+ regmap_set_bits(maps->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
+ }
+ }
+
+ /* Clear any force bit that my be set by bootloader */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0 |
+ AIROHA_PCS_FORCE_LINKDOWN_P0 |
+ AIROHA_PCS_FORCE_LINKUP_P0);
+ }
+
+ /* Toggle Rate Adaption for SGMII/HSGMII mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_clear_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ else
+ regmap_set_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ }
+
+ /* Setup AN Link Timer */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 an_timer;
+
+ an_timer = phylink_get_link_timer_ns(interface);
+
+ /* Value needs to be shifted by 4, seems value is internally * 16 */
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ an_timer >> 4));
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
+ AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ an_timer >> 4));
+ }
+
+ /* Setup SGMII AN and advertisement in DEV_ABILITY */
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+ advertising);
+ if (advertise < 0)
+ return advertise;
+
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
+ AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ advertise));
+
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ } else {
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ }
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
+
+ /* Toggle SGMII or 1000base-x mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN;
+
+ if (neg_mode & PHYLINK_PCS_NEG_INBAND)
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+ else
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* Clear force speed bits and MAC mode */
+ regmap_clear_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ } else {
+ /* Enable compatibility with MAC PCS Layer */
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
+
+ /* AN off force rate adaption, speed is set later in Link Up */
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ }
+
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
+
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
+ AIROHA_PCS_HSGMII_PCS_MODE2_EN);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_1000BASEX &&
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ regmap_set_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
+
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
+ AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY);
+ }
+
+ /* Configure Flow Control on XFI */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
+ permit_pause_to_mac ?
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
+ 0);
+
+ return 0;
+}
+
+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ switch (port->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ regmap_set_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ regmap_set_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface, int speed, int duplex)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ const struct airoha_pcs_match_data *data;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+ data = priv->data;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
+ udelay(1);
+ regmap_update_bits(maps->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
+ }
+ } else {
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ u32 mode;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_10000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
+ mode = AIROHA_PCS_USXGMII_MODE_10000;
+ break;
+ case SPEED_5000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
+ mode = AIROHA_PCS_USXGMII_MODE_5000;
+ break;
+ case SPEED_2500:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
+ mode = AIROHA_PCS_USXGMII_MODE_2500;
+ break;
+ case SPEED_1000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
+ mode = AIROHA_PCS_USXGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
+ mode = AIROHA_PCS_USXGMII_MODE_100;
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ /* Force USXGMII to selected speed */
+ regmap_update_bits(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_MODE, mode);
+
+ if (interface == PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(maps->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 force_speed;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_1000:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
+ break;
+ case SPEED_100:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
+ break;
+ case SPEED_10:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
+ force_speed | rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ u32 ck_gen_mode;
+ u32 speed_reg;
+ u32 if_mode;
+
+ switch (speed) {
+ case SPEED_2500:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
+ break;
+ case SPEED_1000:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
+ break;
+ case SPEED_10:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_10M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
+ break;
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(maps->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
+ if_mode);
+
+ regmap_update_bits(maps->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
+ ck_gen_mode |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
+ }
+
+ regmap_update_bits(maps->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0,
+ speed_reg |
+ AIROHA_PCS_FORCE_SPD_MODE_P0);
+ }
+ }
+
+ if (data->link_up)
+ data->link_up(priv, port->index);
+
+ /* BPI BMI enable */
+ regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_link_down(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* MPI MBI disable */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+}
+
+static void airoha_pcs_pre_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* Select HSGMII or USXGMII in SCU regs */
+ airoha_pcs_setup_scu(priv, port->index, interface);
+
+ /* MPI MBI disable */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RXMPI_STOP |
+ AIROHA_PCS_XFI_RXMBI_STOP |
+ AIROHA_PCS_XFI_TXMPI_STOP |
+ AIROHA_PCS_XFI_TXMBI_STOP);
+
+ /* Write 1 to trigger reset and clear */
+ regmap_clear_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+ AIROHA_PCS_XFI_MAC_LOGIC_RST);
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,
+ AIROHA_PCS_XFI_MAC_LOGIC_RST);
+
+ usleep_range(1000, 2000);
+
+ /* Clear XFI MAC counter */
+ regmap_set_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,
+ AIROHA_PCS_XFI_GLB_CNT_CLR);
+}
+
+static int airoha_pcs_post_config(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ struct airoha_pcs_priv *priv = port->priv;
+ struct airoha_pcs_maps *maps;
+
+ maps = &priv->maps[port->index];
+
+ /* Frag disable */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_RX_FRAG_LEN,
+ FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31));
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FRAG_LEN,
+ FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31));
+
+ /* IPG NUM */
+ regmap_update_bits(maps->pcs_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_IPG_NUM,
+ FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10));
+
+ return 0;
+}
+
+static unsigned int airoha_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
+}
+
+static const struct phylink_pcs_ops airoha_pcs_ops = {
+ .pcs_inband_caps = airoha_pcs_inband_caps,
+ .pcs_pre_config = airoha_pcs_pre_config,
+ .pcs_post_config = airoha_pcs_post_config,
+ .pcs_get_state = airoha_pcs_get_state,
+ .pcs_config = airoha_pcs_config,
+ .pcs_an_restart = airoha_pcs_an_restart,
+ .pcs_link_up = airoha_pcs_link_up,
+ .pcs_link_down = airoha_pcs_link_down,
+};
+
+static int airoha_pcs_init_named_regmap(struct platform_device *pdev,
+ const char *name, struct regmap **regmap)
+{
+ struct regmap_config config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ };
+ void __iomem *base;
+
+ base = devm_platform_ioremap_resource_byname(pdev, name);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ config.name = name;
+ *regmap = devm_regmap_init_mmio(&pdev->dev, base, &config);
+
+ return PTR_ERR_OR_ZERO(*regmap);
+}
+
+static int airoha_pcs_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[0];
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii", &maps->usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static int airoha_pcs_usb_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[0];
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac", &maps->pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &maps->hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &maps->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &maps->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &maps->multi_sgmii);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static int airoha_pcs_pcie_alloc_maps(struct platform_device *pdev,
+ struct airoha_pcs_priv *priv)
+{
+ struct airoha_pcs_maps *maps = priv->maps;
+ int ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac0", &maps[0].pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an0", &maps[0].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs0", &maps[0].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp0", &maps[0].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii0", &maps[0].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii0", &maps[0].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_mac1", &maps[1].pcs_mac);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an1", &maps[1].hsgmii_an);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs1", &maps[1].hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp1", &maps[1].hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii1", &maps[1].multi_sgmii);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii1", &maps[1].usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma0", &priv->pcs_pma[0]);
+ if (ret)
+ return ret;
+
+ ret = airoha_pcs_init_named_regmap(pdev, "pcs_pma1", &priv->pcs_pma[1]);
+ if (ret)
+ return ret;
+
+ return airoha_pcs_init_named_regmap(pdev, "pcs_ana", &priv->pcs_ana);
+}
+
+static struct phylink_pcs *airoha_pcs_xlate(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ struct airoha_pcs_priv *priv = data;
+ struct device *dev = priv->dev;
+ u64 index = 0;
+
+ switch (priv->data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ case AIROHA_PCS_USB:
+ if (pcsspec->nargs) {
+ dev_err(dev, "invalid number of cells in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ break;
+ case AIROHA_PCS_PCIE:
+ if (pcsspec->nargs != 1) {
+ dev_err(dev, "invalid number of cells in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ break;
+ }
+
+ if (pcsspec->nargs)
+ index = pcsspec->args[0];
+
+ if (index >= priv->data->num_port) {
+ dev_err(dev, "invalid index cell in 'pcs-handle' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &priv->ports[index].pcs;
+}
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+ const struct airoha_pcs_match_data *data;
+ struct fwnode_pcs_provider *pcs_provider;
+ struct device *dev = &pdev->dev;
+ struct airoha_pcs_priv *priv;
+ int index, ret;
+
+ data = of_device_get_match_data(dev);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->ports = devm_kcalloc(dev, data->num_port,
+ sizeof(*priv->ports), GFP_KERNEL);
+ if (!priv->ports)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->data = data;
+
+ if (data->port_type == AIROHA_PCS_USB) {
+ struct phy *phy;
+
+ phy = devm_phy_get(dev, NULL);
+ if (IS_ERR(phy))
+ return dev_err_probe(dev, PTR_ERR(phy), "failed to get phy\n");
+
+ priv->phy = phy;
+ }
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ ret = airoha_pcs_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ case AIROHA_PCS_PCIE:
+ ret = airoha_pcs_pcie_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ case AIROHA_PCS_USB:
+ ret = airoha_pcs_usb_alloc_maps(pdev, priv);
+ if (ret)
+ return ret;
+
+ break;
+ }
+
+ if (data->alloc_regmap_fields) {
+ ret = data->alloc_regmap_fields(priv);
+ if (ret)
+ return ret;
+ }
+
+ /* SCU is used to toggle XFI or HSGMII in global SoC registers */
+ if (!priv->phy) {
+ priv->scu = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu");
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+ }
+
+ priv->rsts[0].id = "mac";
+ priv->rsts[1].id = "phy";
+ ret = devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
+ /* For Ethernet PCS, read the AN7581 SoC revision to check if
+ * manual rx calibration is needed. This is only limited to
+ * any SoC revision before E2.
+ */
+ if (device_is_compatible(dev, "airoha,an7581-pcs-eth")) {
+ u32 val;
+
+ ret = regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val);
+ if (ret)
+ return ret;
+
+ if (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) < 0x2)
+ priv->manual_rx_calib = true;
+ }
+
+ for (index = 0; index < data->num_port; index++) {
+ struct airoha_pcs_port *port = &priv->ports[index];
+
+ port->priv = priv;
+ port->index = index;
+ port->pcs.poll = true;
+ port->pcs.ops = &airoha_pcs_ops;
+
+ switch (data->port_type) {
+ case AIROHA_PCS_ETH:
+ case AIROHA_PCS_PON:
+ case AIROHA_PCS_PCIE:
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ port->pcs.supported_interfaces);
+ fallthrough;
+ case AIROHA_PCS_USB:
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ port->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ port->pcs.supported_interfaces);
+ break;
+ }
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ pcs_provider = devm_fwnode_pcs_add_provider(dev, dev_fwnode(dev),
+ airoha_pcs_xlate, priv);
+ if (IS_ERR(pcs_provider))
+ return PTR_ERR(pcs_provider);
+
+ return 0;
+}
+
+static const struct airoha_pcs_match_data an7581_pcs_eth = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_ETH,
+ .alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+ .rxlock_workaround = an7581_pcs_rxlock_workaround,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pon = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_PON,
+ .alloc_regmap_fields = an7581_pcs_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pcie = {
+ .num_port = 2,
+ .port_type = AIROHA_PCS_PCIE,
+ .alloc_regmap_fields = an7581_pcs_pcie_alloc_regmap_fields,
+ .bringup = an7581_pcs_bringup,
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_usb = {
+ .num_port = 1,
+ .port_type = AIROHA_PCS_USB,
+ .bringup = an7581_pcs_usb_bringup,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+ { .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+ { .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+ { .compatible = "airoha,an7581-pcs-pcie", .data = &an7581_pcs_pcie },
+ { .compatible = "airoha,an7581-pcs-usb", .data = &an7581_pcs_usb },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
+
+static struct platform_driver airoha_pcs_driver = {
+ .driver = {
+ .name = "airoha-pcs",
+ .of_match_table = airoha_pcs_of_table,
+ },
+ .probe = airoha_pcs_probe,
+};
+module_platform_driver(airoha_pcs_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Airoha PCS driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
diff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h
new file mode 100644
index 0000000000000..8a76d51b5d2c8
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha.h
@@ -0,0 +1,1311 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* SCU*/
+#define AIROHA_SCU_PDIDR 0x5c
+#define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0)
+#define AIROHA_SCU_WAN_CONF 0x70
+#define AIROHA_SCU_WAN_SEL GENMASK(7, 0)
+#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
+#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
+#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
+#define AIROHA_SCU_SSR3 0x94
+#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13)
+#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
+#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
+#define AIROHA_SCU_SSTR 0x9c
+#define AIROHA_SCU_PCIE_XSI0_SEL GENMASK(14, 13)
+#define AIROHA_SCU_PCIE_XSI0_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x1)
+#define AIROHA_SCU_PCIE_XSI0_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI0_SEL, 0x2)
+#define AIROHA_SCU_PCIE_XSI1_SEL GENMASK(12, 11)
+#define AIROHA_SCU_PCIE_XSI1_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x1)
+#define AIROHA_SCU_PCIE_XSI1_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PCIE_XSI1_SEL, 0x2)
+#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9)
+#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
+#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
+
+/* XFI_MAC */
+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0
+#define AIROHA_PCS_XFI_RX_FRAG_LEN GENMASK(26, 22)
+#define AIROHA_PCS_XFI_TX_FRAG_LEN GENMASK(21, 17)
+#define AIROHA_PCS_XFI_IPG_NUM GENMASK(15, 10)
+#define AIROHA_PCS_XFI_TX_FC_EN BIT(5)
+#define AIROHA_PCS_XFI_RX_FC_EN BIT(4)
+#define AIROHA_PCS_XFI_RXMPI_STOP BIT(3)
+#define AIROHA_PCS_XFI_RXMBI_STOP BIT(2)
+#define AIROHA_PCS_XFI_TXMPI_STOP BIT(1)
+#define AIROHA_PCS_XFI_TXMBI_STOP BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST 0x10
+#define AIROHA_PCS_XFI_MAC_LOGIC_RST BIT(0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH 0x60
+#define AIROHA_PCS_XFI_MAC_MACADDRH GENMASK(15, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL 0x64
+#define AIROHA_PCS_XFI_MAC_MACADDRL GENMASK(31, 0)
+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR 0x100
+#define AIROHA_PCS_XFI_GLB_CNT_CLR BIT(0)
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0
+#define AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY BIT(15)
+#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */
+#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10
+#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */
+#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
+#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1)
+#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
+#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0)
+
+/* HSGMII_PCS */
+#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_TBI_10B_MODE BIT(30)
+#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24)
+#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8
+#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8)
+#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
+#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104
+#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5)
+#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c
+#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0)
+
+/* HSGMII_ANA */
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6 0x18
+#define AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC BIT(20)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8 0x20
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR GENMASK(11, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 GENMASK(7, 4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0 GENMASK(3, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11 0x2c
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_MODE GENMASK(1, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18 0x48
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV GENMASK(28, 27)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19 0x4c
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV GENMASK(15, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_LV GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG GENMASK(2, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_GND FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONFBK_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONREF_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x3)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_CKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_FBCKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x5)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_TX2500M_A FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_CDR_250M_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x7)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24 0x60
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE GENMASK(31, 24)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26 0x68
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY GENMASK(7, 6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x3)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14
+#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
+#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4)
+#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
+#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
+#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
+#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
+#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2)
+#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1)
+#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28)
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c
+#define AIROHA_PCS_HSGMII_PCS_INT BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c
+#define AIROHA_PCS_LINK_STS_P0 BIT(3)
+#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0)
+#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
+#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
+#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448
+#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2)
+#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1)
+#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0)
+
+/* HSGMII_RATE_ADP */
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31)
+
+/* USXGMII */
+#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13)
+#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x4
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP \
+ FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x1)
+#define AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_DOWN \
+ FIELD_PREP_CONST(AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS, 0x0)
+#define AIROHA_PCS_USXGMII_BASE_R_10GB_T_PCS_STUS_1 0x30
+#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12)
+#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
+#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0)
+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c
+#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0
+#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4
+#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8
+#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8)
+#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
+#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318
+#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c
+#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320
+#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12)
+#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8)
+#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)
+
+/* PMA_PHYA */
+#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0
+#define AIROHA_PCS_ANA_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 0x1
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 0x2
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 0x3
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 0x4
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 0x5
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 0x6
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 0x1
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 0x2
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 0x3
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 0x4
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17)
+#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
+#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8)
+#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38
+#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16)
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48
+#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO BIT(5)
+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50
+#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54
+#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64
+#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 0x0
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 0x1
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 0x2
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68
+#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 0x2
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 0x4
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74
+#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c
+#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84
+#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94
+#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4
+#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4
+#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8
+#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
+#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8
+#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4
+#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8
+#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
+#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c
+#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24)
+#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19)
+#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2)
+#define AIROHA_PCS_ANA_CDR_PR_MONPI_EN BIT(1)
+#define AIROHA_PCS_ANA_CDR_PR_MONPR_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110
+#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114
+#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8)
+#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c
+#define AIROHA_PCS_ANA_RX_FE_VCM_GEN_PWDB BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c
+#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
+#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148
+#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYA 2L */
+#define AIROHA_PCS_ANA_PXP_2L_CMN_EN 0x0
+#define AIROHA_PCS_ANA_2L_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_2L_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_20_25 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_40_50 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_80_100 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_150_200 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_300_400 0x5
+#define AIROHA_PCS_ANA_2L_JCPLL_RST_DLY_600_800 0x6
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_4 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_6 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_8 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_GAIN_10 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_2L_JCPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN 0x38
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1 0x3c
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD 0x40
+#define AIROHA_PCS_ANA_2L_JCPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN 0x4c
+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L GENMASK(31, 24)
+#define AIROHA_PCS_ANA_2L_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
+#define AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF 0x50
+#define AIROHA_PCS_ANA_2L_JCPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN 0x54
+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IBIAS GENMASK(29, 24)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST 0x58
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BP GENMASK(28, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_CHP_IOFST GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR 0x5c
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_CODE GENMASK(31, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_OPTION BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_LPF_BWR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV 0x60
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KF GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_KFC GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_KBAND_DIV GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN 0x64
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_2 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_3 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_4 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_MMD_PREDIV_MODE_1 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_POSTDIV_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN 0x68
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_INTERNAL BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV 0x6c
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_PLL_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_RST_DLY GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_1 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_2 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_3 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_REFIN_DIV_4 0x3
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS 0x70
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_INT 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_1SDM 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_2SDM 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_ORD_3SDM 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_IFM BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_23 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_21 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_19 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_DI_LS_2_15 0x3
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT 0x74
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_2_5 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_3 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_4 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_GAIN_6 0x4
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_HREN BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SDM_OUT BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF 0x78
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_AMP_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW 0x7c
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_HALFLSB_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_CFIX GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_1 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_VCODIV_2 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW GENMASK(2, 0)
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_0_5 0x0
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_1 0x1
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_2 0x2
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_4 0x3
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_8 0x4
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_LPF_BW_16 0x6
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR 0x80
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(18, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_TCLVAR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_TXPLL_VCO_SCAPWR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN 0x84
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1 0x88
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD 0x8c
+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_2L_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF 0x9c
+#define AIROHA_PCS_ANA_2L_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN 0xcc
+#define AIROHA_PCS_ANA_2L_TX0_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TX0_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN 0xe8
+#define AIROHA_PCS_ANA_2L_TX1_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_TX1_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL 0xf4
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_2L_RX0_REV_0 0xfc
+#define AIROHA_PCS_ANA_2L_RX0_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV 0x100
+#define AIROHA_PCS_ANA_2L_RX0_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_RX0_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV 0x104
+#define AIROHA_PCS_ANA_2L_CDR0_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO 0x110
+#define AIROHA_PCS_ANA_2L_CDR0_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE 0x11c
+#define AIROHA_PCS_ANA_2L_CDR0_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC 0x120
+#define AIROHA_PCS_ANA_2L_CDR0_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL 0x124
+#define AIROHA_PCS_ANA_2L_CDR0_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN 0x130
+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPR_EN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN 0x134
+#define AIROHA_PCS_ANA_2L_CDR0_PR_XFICK_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_MONPI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR 0x138
+#define AIROHA_PCS_ANA_2L_CDR0_PR_CAP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR0_PR_BUF_IN_SR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON 0x13c
+#define AIROHA_PCS_ANA_2L_RX0_DAC_MON GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN 0x140
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_PEAK GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_LPF_CTRL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL 0x144
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ1_EN BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_FE_EQ_HZEN BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_SIGDET_VTH_SEL GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN 0x148
+#define AIROHA_PCS_ANA_2L_RX0_FE_VCM_GEN_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ3_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_FE_VB_EQ2_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE 0x150
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE 0x170
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_2L_AEQ0_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ 0x17c
+#define AIROHA_PCS_ANA_2L_RX0_DAC_E1_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_E0_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_D1_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_2L_RX0_DAC_D0_BYPASS_AEQ BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ 0x180
+#define AIROHA_PCS_ANA_2L_RX0_DAC_EYE_BYPASS_AEQ BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB 0x234
+#define AIROHA_PCS_ANA_2L_RX1_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL 0x1ac
+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_PHY_CK_SEL BIT(16)
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_PR 0x0
+#define AIROHA_PCS_ANA_2L_RX0_PHY_CK_SEL_FROM_DES 0x1
+#define AIROHA_PCS_ANA_PXP_2L_RX1_REV_0 0x1b4
+#define AIROHA_PCS_ANA_2L_RX1_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_2L_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_2L_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_REV_0 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)
+#define AIROHA_PCS_ANA_2L_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)
+#define AIROHA_PCS_ANA_2L_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)
+#define AIROHA_PCS_ANA_2L_REV_0_VOS_PNINV GENMASK(3, 2)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYEBD4 BIT(1)
+#define AIROHA_PCS_ANA_2L_REV_0_PLEYE_XOR_MON_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV 0x1b8
+#define AIROHA_PCS_ANA_2L_RX1_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_2L_RX1_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV 0x1bc
+#define AIROHA_PCS_ANA_2L_CDR1_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO 0x1c8
+#define AIROHA_PCS_ANA_2L_CDR1_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE 0x1d4
+#define AIROHA_PCS_ANA_2L_CDR1_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC 0x1d8
+#define AIROHA_PCS_ANA_2L_CDR1_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL 0x1dc
+#define AIROHA_PCS_ANA_2L_CDR1_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN 0x1e8
+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPR_EN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN 0x1ec
+#define AIROHA_PCS_ANA_2L_CDR1_PR_XFICK_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_MONPI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR 0x1f0
+#define AIROHA_PCS_ANA_2L_RX1_DAC_MON GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_CAP_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_CDR1_PR_BUF_IN_SR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE 0x1f4
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH 0x1f8
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_2L_RX1_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL 0x1fc
+#define AIROHA_PCS_ANA_2L_RX1_FE_EQ_HZEN BIT(24)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN 0x200
+#define AIROHA_PCS_ANA_2L_RX1_FE_VCM_GEN_PWDB BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ3_EN BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ2_EN BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_FE_VB_EQ1_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW 0x208
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE GENMASK(25, 16)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2VOS BIT(0)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA2IOS BIT(1)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1VOS BIT(2)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_VGA1IOS BIT(3)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2VOS BIT(4)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE2IOS BIT(5)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1VOS BIT(6)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_CTLE1IOS BIT(7)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_LVSH BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_OSCAL_FORCE_COMPOS BIT(9)
+#define AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE 0x228
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE GENMASK(27, 16)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_SAOS BIT(0)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP1 BIT(1)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP2 BIT(2)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP3 BIT(3)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP4 BIT(4)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP5 BIT(5)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP6 BIT(6)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_DFETP7 BIT(7)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_VGA BIT(8)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_CTLE BIT(9)
+#define AIROHA_PCS_ANA_2L_AEQ1_OFORCE_ATT BIT(10)
+#define AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ 0x238
+#define AIROHA_PCS_ANA_2L_RX1_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_2L_RX1_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYD */
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0
+#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4
+#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88
+#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8)
+#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c
+#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90
+#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94
+#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98
+#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c
+#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100
+#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104
+#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
+#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
+#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120
+#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8)
+#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c
+#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150
+#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158
+#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12)
+#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c
+#define AIROHA_PCS_PMA_SIGDET_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_1 0x174
+#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_2 0x178
+#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16)
+#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
+#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
+#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_RX_FLL_5 0x184
+#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16)
+#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_B 0x19c
+#define AIROHA_PCS_PMA_LOAD_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_1 0x208
+#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_RST_B 0x260
+#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320
+#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330
+#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c
+#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c
+#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24)
+#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16)
+#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8)
+#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350
+#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360
+#define AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN GENMASK(17, 16)
+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374
+#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2 0x380
+#define AIROHA_PCS_RX_SIGDET BIT(8)
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390
+#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c
+#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414
+#define AIROHA_PCS_PMA_XFI_RX_MODE GENMASK(11, 9)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x0)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x1)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x2)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x3)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x4)
+#define AIROHA_PCS_PMA_XFI_RX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_RX_MODE, 0x5)
+#define AIROHA_PCS_PMA_R2T_MODE BIT(8)
+#define AIROHA_PCS_PMA_XFI_TX_MODE GENMASK(5, 3)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_10G3 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x0)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_5G15 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x1)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_6G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x2)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_2G57 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x3)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_3G12 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x4)
+#define AIROHA_PCS_PMA_XFI_TX_MODE_1G25 FIELD_PREP_CONST(AIROHA_PCS_PMA_XFI_TX_MODE, 0x5)
+#define AIROHA_PCS_PMA_SW_RST_SET 0x460
+#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11)
+#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8)
+#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7)
+#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6)
+#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5)
+#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4)
+#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3)
+#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2)
+#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1)
+#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0)
+#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474
+#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16)
+#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c
+#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
+#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
+#define AIROHA_PCS_PMA_RX_FREQDET 0x530
+#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580
+#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)
+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_29 0x910
+#define AIROHA_PCS_PMA_2L_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_2L_RX_RATE_CTRL GENMASK(5, 4)
+
+#define AIROHA_PCS_MAX_CALIBRATION_TRY 50
+#define AIROHA_PCS_MAX_RX_SIGDET_TRY 6
+#define AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT 4
+#define AIROHA_PCS_MAX_NUM_RSTS 2
+
+enum xfi_port_type {
+ AIROHA_PCS_ETH,
+ AIROHA_PCS_PON,
+ AIROHA_PCS_USB,
+ AIROHA_PCS_PCIE,
+};
+
+struct airoha_pcs_maps {
+ struct regmap *pcs_mac;
+ struct regmap *hsgmii_an;
+ struct regmap *hsgmii_pcs;
+ struct regmap *hsgmii_rate_adp;
+ struct regmap *multi_sgmii;
+ struct regmap *usxgmii_pcs;
+};
+
+struct airoha_pcs_priv {
+ struct device *dev;
+ const struct airoha_pcs_match_data *data;
+
+ struct airoha_pcs_port *ports;
+
+ struct regmap *scu;
+
+ struct airoha_pcs_maps maps[2];
+
+ struct regmap *pcs_pma[2];
+ struct regmap *pcs_ana;
+ struct regmap_field **pcs_ana_fields[2];
+
+ struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
+
+ struct phy *phy;
+
+ bool manual_rx_calib;
+};
+
+struct airoha_pcs_port {
+ struct airoha_pcs_priv *priv;
+ phy_interface_t interface;
+ int index;
+
+ struct phylink_pcs pcs;
+};
+
+struct airoha_pcs_match_data {
+ int num_port;
+ enum xfi_port_type port_type;
+
+ int (*alloc_regmap_fields)(struct airoha_pcs_priv *priv);
+ int (*bringup)(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+ void (*link_up)(struct airoha_pcs_priv *priv, int index);
+ int (*rxlock_workaround)(struct airoha_pcs_priv *priv, int index);
+};
+
+#define to_airoha_pcs_port(n) container_of(n, struct airoha_pcs_port, pcs)
+
+#if IS_ENABLED(CONFIG_PCS_AIROHA_AN7581)
+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv);
+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv);
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface);
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index);
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index);
+#else
+static inline int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv,
+ int index)
+{
+}
+
+static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv,
+ int index)
+{
+ return 0;
+}
+#endif
diff --git a/drivers/net/pcs/airoha/pcs-an7581.c b/drivers/net/pcs/airoha/pcs-an7581.c
new file mode 100644
index 0000000000000..95e155a7fa621
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-an7581.c
@@ -0,0 +1,2100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/math.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/regmap.h>
+
+#include "pcs-airoha.h"
+
+#include <linux/of.h>
+
+enum {
+ AN7581_PCS_CMN_EN,
+
+ AN7581_PCS_JCPLL_SPARE_L,
+ AN7581_PCS_JCPLL_RST_DLY,
+ AN7581_PCS_JCPLL_PLL_RSTB,
+ AN7581_PCS_JCPLL_SDM_DI_EN,
+ AN7581_PCS_JCPLL_SDM_DI_LS,
+
+ AN7581_PCS_JCPLL_SDM_OUT,
+ AN7581_PCS_JCPLL_SDM_ORD,
+ AN7581_PCS_JCPLL_SDM_MODE,
+ AN7581_PCS_JCPLL_SDM_IFM,
+ AN7581_PCS_JCPLL_SDM_HREN,
+
+ AN7581_PCS_JCPLL_CHP_IOFST,
+ AN7581_PCS_JCPLL_CHP_IBIAS,
+ AN7581_PCS_JCPLL_LPF_SHCK_EN,
+
+ AN7581_PCS_JCPLL_LPF_BWR,
+ AN7581_PCS_JCPLL_LPF_BP,
+ AN7581_PCS_JCPLL_LPF_BC,
+ AN7581_PCS_JCPLL_LPF_BR,
+ AN7581_PCS_JCPLL_LPF_BWC,
+
+ AN7581_PCS_JCPLL_VCO_SCAPWR,
+ AN7581_PCS_JCPLL_VCO_HALFLSB_EN,
+ AN7581_PCS_JCPLL_VCO_CFIX,
+ AN7581_PCS_JCPLL_VCODIV,
+ AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L,
+ AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H,
+ AN7581_PCS_JCPLL_VCO_TCLVAR,
+
+ AN7581_PCS_JCPLL_POSTDIV_D5,
+ AN7581_PCS_JCPLL_MMD_PREDIV_MODE,
+
+ AN7581_PCS_JCPLL_KBAND_KS,
+ AN7581_PCS_JCPLL_KBAND_KF,
+ AN7581_PCS_JCPLL_KBAND_KFC,
+ AN7581_PCS_JCPLL_KBAND_DIV,
+ AN7581_PCS_JCPLL_KBAND_CODE,
+ AN7581_PCS_JCPLL_KBAND_OPTION,
+
+ AN7581_PCS_JCPLL_TCL_AMP_VREF,
+ AN7581_PCS_JCPLL_TCL_AMP_GAIN,
+ AN7581_PCS_JCPLL_TCL_AMP_EN,
+
+ AN7581_PCS_JCPLL_TCL_LPF_BW,
+ AN7581_PCS_JCPLL_TCL_LPF_EN,
+
+ AN7581_PCS_JCPLL_SSC_DELTA,
+ AN7581_PCS_JCPLL_SSC_DELTA1,
+ AN7581_PCS_JCPLL_SSC_PERIOD,
+ AN7581_PCS_JCPLL_SSC_TRI_EN,
+ AN7581_PCS_JCPLL_SSC_EN,
+ AN7581_PCS_JCPLL_SSC_PHASE_INI,
+ AN7581_PCS_JCPLL_TCL_KBAND_VREF,
+
+ AN7581_PCS_TXPLL_LDO_VCO_OUT,
+ AN7581_PCS_TXPLL_LDO_OUT,
+ AN7581_PCS_TXPLL_PLL_RSTB,
+ AN7581_PCS_TXPLL_RST_DLY,
+ AN7581_PCS_TXPLL_REFIN_DIV,
+ AN7581_PCS_TXPLL_REFIN_INTERNAL,
+ AN7581_PCS_TXPLL_SDM_MODE,
+ AN7581_PCS_TXPLL_SDM_IFM,
+ AN7581_PCS_TXPLL_SDM_DI_LS,
+ AN7581_PCS_TXPLL_SDM_DI_EN,
+ AN7581_PCS_TXPLL_SDM_HREN,
+ AN7581_PCS_TXPLL_SDM_ORD,
+ AN7581_PCS_TXPLL_SDM_OUT,
+ AN7581_PCS_TXPLL_SSC_DELTA1,
+ AN7581_PCS_TXPLL_SSC_DELTA,
+ AN7581_PCS_TXPLL_SSC_TRI_EN,
+ AN7581_PCS_TXPLL_SSC_PHASE_INI,
+ AN7581_PCS_TXPLL_SSC_EN,
+ AN7581_PCS_TXPLL_SSC_PERIOD,
+ AN7581_PCS_TXPLL_LPF_BC,
+ AN7581_PCS_TXPLL_LPF_BR,
+ AN7581_PCS_TXPLL_LPF_BP,
+ AN7581_PCS_TXPLL_LPF_BWC,
+ AN7581_PCS_TXPLL_LPF_BWR,
+ AN7581_PCS_TXPLL_CHP_IOFST,
+ AN7581_PCS_TXPLL_CHP_IBIAS,
+ AN7581_PCS_TXPLL_VCO_CFIX,
+ AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L,
+ AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H,
+ AN7581_PCS_TXPLL_VCO_TCLVAR,
+ AN7581_PCS_TXPLL_VCO_SCAPWR,
+ AN7581_PCS_TXPLL_VCO_HALFLSB_EN,
+ AN7581_PCS_TXPLL_KBAND_CODE,
+ AN7581_PCS_TXPLL_KBAND_OPTION,
+ AN7581_PCS_TXPLL_KBAND_KS,
+ AN7581_PCS_TXPLL_KBAND_KF,
+ AN7581_PCS_TXPLL_KBAND_KFC,
+ AN7581_PCS_TXPLL_KBAND_DIV,
+ AN7581_PCS_TXPLL_MMD_PREDIV_MODE,
+ AN7581_PCS_TXPLL_POSTDIV_EN,
+ AN7581_PCS_TXPLL_VCODIV,
+ AN7581_PCS_TXPLL_TCL_KBAND_VREF,
+ AN7581_PCS_TXPLL_TCL_AMP_GAIN,
+ AN7581_PCS_TXPLL_TCL_AMP_VREF,
+ AN7581_PCS_TXPLL_TCL_LPF_BW,
+ AN7581_PCS_TXPLL_TCL_LPF_EN,
+ AN7581_PCS_TXPLL_TCL_AMP_EN,
+
+ AN7581_PCS_TX_DMEDGEGEN_EN,
+ AN7581_PCS_TX_CKLDO_EN,
+
+ AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_E1_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_E0_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_D1_BYPASS_AEQ,
+ AN7581_PCS_RX_DAC_D0_BYPASS_AEQ,
+ AN7581_PCS_RX_FE_VCM_GEN_PWDB,
+ AN7581_PCS_RX_OSCAL_FORCE,
+ AN7581_PCS_RX_DAC_MON,
+ AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL,
+ AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL,
+ AN7581_PCS_RX_REV_1_SIGDET_ILEAK,
+ AN7581_PCS_RX_FE_VB_EQ3_EN,
+ AN7581_PCS_RX_FE_VB_EQ2_EN,
+ AN7581_PCS_RX_FE_VB_EQ1_EN,
+ AN7581_PCS_RX_FE_EQ_HZEN,
+ AN7581_PCS_RX_SIGDET_VTH_SEL,
+ AN7581_PCS_RX_SIGDET_PEAK,
+ AN7581_PCS_RX_SIGDET_LPF_CTRL,
+ AN7581_PCS_RX_TDC_CK_SEL,
+ AN7581_PCS_RX_PHYCK_RSTB,
+ AN7581_PCS_RX_PHYCK_SEL,
+ AN7581_PCS_RX_PHYCK_DIV,
+ AN7581_PCS_RX_PHY_CK_SEL_FORCE,
+ AN7581_PCS_RX_PHY_CK_SEL,
+
+ AN7581_PCS_AEQ_OFORCE,
+
+ AN7581_PCS_CDR_PD_EDGE_DIS,
+ AN7581_PCS_CDR_PD_PICAL_CKD8_INV,
+
+ AN7581_PCS_CDR_PR_XFICK_EN,
+ AN7581_PCS_CDR_PR_MONPI_EN,
+ AN7581_PCS_CDR_PR_MONPR_EN,
+ AN7581_PCS_CDR_PR_KBAND_DIV,
+ AN7581_PCS_CDR_PR_BETA_SEL,
+ AN7581_PCS_CDR_PR_VCOADC_OS,
+ AN7581_PCS_CDR_PR_BETA_DAC,
+ AN7581_PCS_CDR_PR_FBKSEL,
+ AN7581_PCS_CDR_PR_DAC_BAND,
+ AN7581_PCS_CDR_PR_VREG_CKBUF_VAL,
+ AN7581_PCS_CDR_PR_VREG_IBAND_VAL,
+ AN7581_PCS_CDR_PR_CAP_EN,
+ AN7581_PCS_CDR_PR_INJ_FORCE_OFF,
+
+ AN7581_PCS_CDR_BUF_IN_SR,
+
+ AN7581_PCS_CDR_LPF_TOP_LIM,
+ AN7581_PCS_CDR_LPF_RATIO,
+
+ AN7581_PCS_FIELDS_MAX,
+};
+
+static const struct reg_field an7581_pcs_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 8, 15),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 8, 23),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, 0, 0),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 17, 17),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 16, 16),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, 16, 20),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 3, 5),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 24, 24),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 16, 18),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 8, 9),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 24, 25),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 8, 9),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 16, 16),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 0, 1),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 24, 28),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 16, 20),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 8, 13),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, 0, 5),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 0, 4),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 24, 25),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 27, 29),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, 0, 0),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 0, 7),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 0, 1),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, 8, 10),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 16, 17),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, 8, 8),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 16, 17),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, 8, 12),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 8, 10),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, 0, 0),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, 24, 24),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB, 24, 24),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB, 0, 0),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_AEQ_CFORCE, 8, 19),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW, 8, 17),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 24, 28),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 2, 2),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 1, 1),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 0, 0),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 24, 24),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 16, 16),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 8, 8),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, 0, 0),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 19, 19),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, 16, 18),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 16, 20),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, 8, 9),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_DAC_RANGE, 24, 25),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, 24, 24),
+};
+
+static const struct reg_field an7581_pcs_pcie0_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 16, 16),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX0_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_EYE_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_D0_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 16, 16),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ0_CFORCE, 8, 19),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_OSCAL_FORCE, 8, 17),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_DAC_MON, 0, 4),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 8, 8),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_MONPI_EN, 0, 0),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_COR_HBW_EN, 24, 24),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 8, 8),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_FE_VB_EQ2_EN, 0, 0),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 24, 24),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 8, 8),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_BUF_IN_SR, 0, 2),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_VTH_SEL, 0, 4),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 24, 25),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_SIGDET_DCTEST_EN, 8, 9),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX0_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR0_PR_INJ_MODE, 24, 24),
+};
+
+static const struct reg_field an7581_pcs_pcie1_fields[AN7581_PCS_FIELDS_MAX] = {
+ [AN7581_PCS_CMN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CMN_EN, 0, 0),
+
+ [AN7581_PCS_JCPLL_SPARE_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_VTP_EN, 24, 31),
+
+ [AN7581_PCS_JCPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 0, 2),
+ [AN7581_PCS_JCPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 8, 8),
+ [AN7581_PCS_JCPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 16, 16),
+ [AN7581_PCS_JCPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_RST_DLY, 24, 25),
+
+ [AN7581_PCS_JCPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 24, 24),
+ [AN7581_PCS_JCPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 16, 17),
+ [AN7581_PCS_JCPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 8, 9),
+ [AN7581_PCS_JCPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_IFM, 0, 0),
+ [AN7581_PCS_JCPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 0, 0),
+
+ [AN7581_PCS_JCPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 24, 29),
+ [AN7581_PCS_JCPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 16, 21),
+ [AN7581_PCS_JCPLL_LPF_SHCK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_IB_EXT_EN, 8, 8),
+
+ [AN7581_PCS_JCPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 24, 28),
+ [AN7581_PCS_JCPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 16, 20),
+ [AN7581_PCS_JCPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 8, 12),
+ [AN7581_PCS_JCPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BR, 0, 4),
+ [AN7581_PCS_JCPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 0, 4),
+
+ [AN7581_PCS_JCPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 24, 26),
+ [AN7581_PCS_JCPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 16, 16),
+ [AN7581_PCS_JCPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 8, 9),
+ [AN7581_PCS_JCPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCODIV, 0, 1),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 16, 18),
+ [AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 8, 10),
+ [AN7581_PCS_JCPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_VCO_TCLVAR, 0, 2),
+
+ [AN7581_PCS_JCPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_JCPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_JCPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_JCPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_JCPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_JCPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_KBAND_VREF, 0, 4),
+
+ [AN7581_PCS_JCPLL_POSTDIV_D5] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 24, 24),
+ [AN7581_PCS_JCPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_MMD_PREDIV_MODE, 0, 1),
+
+ [AN7581_PCS_JCPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 16, 17),
+ [AN7581_PCS_JCPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 8, 9),
+ [AN7581_PCS_JCPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_KBAND_KFC, 0, 1),
+ [AN7581_PCS_JCPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 24, 26),
+ [AN7581_PCS_JCPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 16, 23),
+ [AN7581_PCS_JCPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_LPF_BWC, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 24, 28),
+ [AN7581_PCS_JCPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 16, 18),
+ [AN7581_PCS_JCPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_SDM_HREN, 8, 8),
+
+ [AN7581_PCS_JCPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 24, 26),
+ [AN7581_PCS_JCPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_JCPLL_TCL_CMP_EN, 16, 16),
+
+ [AN7581_PCS_TXPLL_LDO_VCO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 24, 25),
+ [AN7581_PCS_TXPLL_LDO_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 16, 17),
+ [AN7581_PCS_TXPLL_PLL_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 16, 16),
+ [AN7581_PCS_TXPLL_RST_DLY] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 8, 10),
+ [AN7581_PCS_TXPLL_REFIN_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 0, 1),
+ [AN7581_PCS_TXPLL_REFIN_INTERNAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_PHY_CK2_EN, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 16, 17),
+ [AN7581_PCS_TXPLL_SDM_IFM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_DI_LS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 0, 1),
+ [AN7581_PCS_TXPLL_SDM_DI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_REFIN_DIV, 24, 24),
+ [AN7581_PCS_TXPLL_SDM_HREN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 8, 8),
+ [AN7581_PCS_TXPLL_SDM_OUT] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 0, 0),
+ [AN7581_PCS_TXPLL_SDM_ORD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_DI_LS, 24, 25),
+ [AN7581_PCS_TXPLL_SSC_DELTA1] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 16, 31),
+ [AN7581_PCS_TXPLL_SSC_DELTA] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_DELTA1, 0, 15),
+ [AN7581_PCS_TXPLL_SSC_TRI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 16, 16),
+ [AN7581_PCS_TXPLL_SSC_PHASE_INI] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 8, 8),
+ [AN7581_PCS_TXPLL_SSC_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_EN, 0, 0),
+ [AN7581_PCS_TXPLL_SSC_PERIOD] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SSC_PERIOD, 0, 15),
+ [AN7581_PCS_TXPLL_LPF_BC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 16, 20),
+ [AN7581_PCS_TXPLL_LPF_BR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 8, 12),
+ [AN7581_PCS_TXPLL_CHP_IOFST] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 0, 5),
+ [AN7581_PCS_TXPLL_CHP_IBIAS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_750M_SYS_CK_EN, 24, 29),
+ [AN7581_PCS_TXPLL_LPF_BWC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 8, 12),
+ [AN7581_PCS_TXPLL_LPF_BWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 0, 4),
+ [AN7581_PCS_TXPLL_LPF_BP] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_CHP_IOFST, 24, 28),
+ [AN7581_PCS_TXPLL_VCO_CFIX] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 16, 17),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 24, 26),
+ [AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 16, 18),
+ [AN7581_PCS_TXPLL_VCO_TCLVAR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 8, 10),
+ [AN7581_PCS_TXPLL_VCO_SCAPWR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_VCO_SCAPWR, 0, 2),
+ [AN7581_PCS_TXPLL_VCO_HALFLSB_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 24, 24),
+ [AN7581_PCS_TXPLL_KBAND_CODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 24, 31),
+ [AN7581_PCS_TXPLL_KBAND_OPTION] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_LPF_BWR, 16, 16),
+ [AN7581_PCS_TXPLL_KBAND_KS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 24, 25),
+ [AN7581_PCS_TXPLL_KBAND_KF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 16, 17),
+ [AN7581_PCS_TXPLL_KBAND_KFC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 8, 9),
+ [AN7581_PCS_TXPLL_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_KBAND_DIV, 0, 2),
+ [AN7581_PCS_TXPLL_MMD_PREDIV_MODE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 8, 9),
+ [AN7581_PCS_TXPLL_POSTDIV_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_POSTDIV_EN, 0, 0),
+ [AN7581_PCS_TXPLL_VCODIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 8, 9),
+ [AN7581_PCS_TXPLL_TCL_KBAND_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_KBAND_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_AMP_GAIN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 24, 26),
+ [AN7581_PCS_TXPLL_TCL_AMP_VREF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 0, 4),
+ [AN7581_PCS_TXPLL_TCL_LPF_BW] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_LPF_BW, 0, 2),
+ [AN7581_PCS_TXPLL_TCL_LPF_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_TCL_AMP_VREF, 24, 24),
+ [AN7581_PCS_TXPLL_TCL_AMP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TXPLL_SDM_OUT, 16, 16),
+
+ [AN7581_PCS_TX_DMEDGEGEN_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 24, 24),
+ [AN7581_PCS_TX_CKLDO_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_TX1_CKLDO_EN, 0, 0),
+
+ [AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 24, 24),
+ [AN7581_PCS_RX_DAC_E1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 16, 16),
+ [AN7581_PCS_RX_DAC_E0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 8, 8),
+ [AN7581_PCS_RX_DAC_D1_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_D1_BYPASS_AEQ, 0, 0),
+ [AN7581_PCS_RX_DAC_D0_BYPASS_AEQ] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_PEACKING_CTRL_LSB, 24, 24),
+ [AN7581_PCS_RX_FE_VCM_GEN_PWDB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 24, 24),
+
+ [AN7581_PCS_AEQ_OFORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_AEQ1_CFORCE, 16, 27),
+ [AN7581_PCS_RX_OSCAL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_OSCAL_WATCH_WNDW, 16, 25),
+
+ [AN7581_PCS_CDR_PD_EDGE_DIS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 8, 8),
+ [AN7581_PCS_CDR_PD_PICAL_CKD8_INV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PD_PICAL_CKD8_INV, 0, 0),
+
+ [AN7581_PCS_RX_DAC_MON] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 16, 20),
+ [AN7581_PCS_CDR_PR_XFICK_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 8, 8),
+ [AN7581_PCS_CDR_PR_MONPI_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_MONPI_EN, 0, 0),
+ [AN7581_PCS_CDR_PR_MONPR_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_COR_HBW_EN, 24, 24),
+
+ [AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 24, 26),
+ [AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 20, 22),
+ [AN7581_PCS_RX_REV_1_SIGDET_ILEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_REV_0, 18, 19),
+
+ [AN7581_PCS_CDR_LPF_TOP_LIM] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 8, 26),
+ [AN7581_PCS_CDR_LPF_RATIO] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_LPF_RATIO, 0, 1),
+
+ [AN7581_PCS_CDR_PR_KBAND_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 24, 26),
+ [AN7581_PCS_CDR_PR_BETA_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 16, 19),
+ [AN7581_PCS_CDR_PR_VCOADC_OS] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 8, 11),
+ [AN7581_PCS_CDR_PR_BETA_DAC] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BETA_DAC, 0, 6),
+ [AN7581_PCS_CDR_PR_FBKSEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 24, 25),
+ [AN7581_PCS_CDR_PR_DAC_BAND] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 16, 20),
+ [AN7581_PCS_CDR_PR_VREG_CKBUF_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 8, 10),
+ [AN7581_PCS_CDR_PR_VREG_IBAND_VAL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_VREG_IBAND_VAL, 0, 2),
+
+ [AN7581_PCS_RX_FE_VB_EQ3_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 16, 16),
+ [AN7581_PCS_RX_FE_VB_EQ2_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 8, 8),
+ [AN7581_PCS_RX_FE_VB_EQ1_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_VB_EQ1_EN, 0, 0),
+ [AN7581_PCS_RX_FE_EQ_HZEN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_FE_50OHMS_SEL, 24, 24),
+
+ [AN7581_PCS_CDR_PR_CAP_EN] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 8, 8),
+ [AN7581_PCS_CDR_BUF_IN_SR] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_BUF_IN_SR, 0, 2),
+
+ [AN7581_PCS_RX_SIGDET_VTH_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 16, 20),
+ [AN7581_PCS_RX_SIGDET_PEAK] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_SIGDET_NOVTH, 8, 9),
+ [AN7581_PCS_RX_SIGDET_LPF_CTRL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_DAC_RANGE_EYE, 24, 25),
+
+ [AN7581_PCS_RX_TDC_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 24, 24),
+ [AN7581_PCS_RX_PHYCK_RSTB] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 16, 16),
+ [AN7581_PCS_RX_PHYCK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 8, 9),
+ [AN7581_PCS_RX_PHYCK_DIV] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_PHYCK_DIV, 0, 7),
+ [AN7581_PCS_RX_PHY_CK_SEL_FORCE] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 24, 24),
+ [AN7581_PCS_RX_PHY_CK_SEL] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_RX1_BUSBIT_SEL, 16, 16),
+
+ [AN7581_PCS_CDR_PR_INJ_FORCE_OFF] = REG_FIELD(AIROHA_PCS_ANA_PXP_2L_CDR1_PR_INJ_MODE, 24, 24),
+};
+
+static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma;
+ u32 kband_vref;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ kband_vref = 0x10;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ kband_vref = 0xf;
+ break;
+ default:
+ return;
+ }
+
+ /* This comment only apply to Serdes PCIe that expose
+ * 2 PCS.
+ *
+ * The Serdes PCIe expose 2 PCS but always require
+ * the PMA for the first PCS to be configured
+ * for correct functionality for JCPLL.
+ */
+ pcs_pma = priv->pcs_pma[0];
+
+ /* Setup LDO */
+ usleep_range(200, 300);
+
+ regmap_field_set_bits(pcs_ana_fields[AN7581_PCS_JCPLL_SPARE_L],
+ AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
+
+ /* Setup RSTB */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_RST_DLY],
+ AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_PLL_RSTB], 0x1);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
+
+ /* Setup SDM */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_LS],
+ AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_DI_EN], 0x0);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_OUT], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_ORD],
+ AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_MODE], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_IFM], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SDM_HREN], 0x0);
+
+ /* Setup SSC */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_DELTA1], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PERIOD], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_TRI_EN], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_EN], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_SSC_PHASE_INI], 0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0);
+
+ /* Setup LPF */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IOFST], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_CHP_IBIAS], 0x18);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_SHCK_EN], 0);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWR], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BP], 0x10);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BC], 0x1f);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BR], BIT(3) | BIT(1));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_LPF_BWC], 0x0);
+
+ /* Setup VCO */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_SCAPWR], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_HALFLSB_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_CFIX], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_L], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_VCOVAR_BIAS_H], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCO_TCLVAR], 0x3);
+
+ /* Setup PCW */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
+
+ /* Setup DIV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_POSTDIV_D5], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_MMD_PREDIV_MODE],
+ AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_VCODIV],
+ AIROHA_PCS_ANA_JCPLL_VCODIV_1);
+
+ /* Setup KBand */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KS], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KF], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_KFC], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_DIV], 0x2);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_CODE], 0xe4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_KBAND_OPTION], 0x0);
+
+ /* Setup TCL */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_KBAND_VREF],
+ kband_vref);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_VREF], 0x5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_GAIN],
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_AMP_EN], 0x1);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_BW],
+ AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_JCPLL_TCL_LPF_EN], 0x1);
+
+ /* Enable PLL */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
+}
+
+static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
+ struct regmap *pcs_pma;
+ u32 tcl_amp_vref;
+ bool sdm_hren;
+ u32 vco_cfix;
+ bool vcodiv;
+ u32 pcw;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(1) | BIT(0);
+ pcw = BIT(27);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ lpf_chp_ibias = 0xa;
+ lpf_bp = BIT(2) | BIT(0);
+ lpf_bwr = 0;
+ lpf_bwc = 0;
+ vco_cfix = 0;
+ pcw = BIT(27) | BIT(25);
+ tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
+ vcodiv = true;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(0);
+ pcw = BIT(27) | BIT(22);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = true;
+ break;
+ default:
+ return;
+ }
+
+ /* This comment only apply to Serdes PCIe that expose
+ * 2 PCS.
+ *
+ * The Serdes PCIe expose 2 PCS but always require
+ * the PMA for the first PCS to be configured
+ * for correct functionality for TXPLL.
+ */
+ pcs_pma = priv->pcs_pma[0];
+
+ /* Setup VCO LDO Output */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_VCO_OUT], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LDO_OUT], 0x1);
+
+ /* Setup RSTB */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_PLL_RSTB], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_RST_DLY], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_DIV],
+ AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_REFIN_INTERNAL], 0x1);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+ /* Setup SDM */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_MODE], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_IFM], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_LS],
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_DI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_HREN], sdm_hren);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_OUT], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SDM_ORD],
+ AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
+
+ /* Setup SSC */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA1], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_DELTA], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_TRI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PHASE_INI], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_SSC_PERIOD], 0x0);
+
+ /* Setup LPF */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IBIAS],
+ lpf_chp_ibias);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_CHP_IOFST], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BC], 0x1f);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BR], 0x5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWC], lpf_bwc);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BWR], lpf_bwr);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_LPF_BP], lpf_bp);
+
+ /* Setup VCO */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_CFIX], vco_cfix);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_L], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_VCOVAR_BIAS_H], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_TCLVAR], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_SCAPWR], 0x7);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCO_HALFLSB_EN], 0x1);
+
+ /* Setup PCW */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+ /* Setup KBand */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_CODE], 0xe4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_OPTION], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KS], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KF], 0x3);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_KFC], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_KBAND_DIV], 0x4);
+
+ /* Setup DIV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_POSTDIV_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_MMD_PREDIV_MODE],
+ AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_VCODIV],
+ vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+ AIROHA_PCS_ANA_TXPLL_VCODIV_1);
+
+ /* Setup TCL */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_KBAND_VREF], 0xf);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_VREF],
+ tcl_amp_vref);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_GAIN],
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_BW],
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_LPF_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TXPLL_TCL_AMP_EN], 0x1);
+
+ /* Enable PLL */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+}
+
+static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 fir_cn1, fir_c0b, fir_c1;
+ u32 tx_rate_ctrl;
+ u32 ckin_divisor;
+ u32 xfi_tx_mode;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ ckin_divisor = BIT(1);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 12;
+ fir_c1 = 0;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_1G25;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ ckin_divisor = BIT(2);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 11;
+ fir_c1 = 1;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_3G12;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ ckin_divisor = BIT(2) | BIT(0);
+ tx_rate_ctrl = BIT(1);
+ fir_cn1 = 1;
+ fir_c0b = 1;
+ fir_c1 = 11;
+ xfi_tx_mode = AIROHA_PCS_PMA_XFI_TX_MODE_10G3;
+ break;
+ default:
+ return;
+ }
+
+ /* Set TX rate ctrl */
+ if (priv->data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,
+ AIROHA_PCS_PMA_2L_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_2L_TX_RATE_CTRL,
+ tx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_XFI_TX_MODE,
+ xfi_tx_mode);
+ } else {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ tx_rate_ctrl));
+ }
+
+ /* Setup TX Config */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_DMEDGEGEN_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_TX_CKLDO_EN], 0x1);
+
+ udelay(1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+ /* FIXME: Ask Airoha TX term is OK to reset? */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+ ckin_divisor));
+
+ if (priv->data->port_type != AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ tx_rate_ctrl));
+ }
+
+ /* Setup TX FIR Load Parameters (Reference 660mV) */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+ /* Reset TX Bar */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_TX_RST_B,
+ AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
+}
+
+static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 phyck_div, phyck_sel;
+ u32 pr_cdr_beta_dac;
+ u32 cdr_pr_buf_in_sr;
+ bool cdr_pr_cap_en;
+ u32 sigdet_vth_sel;
+ u32 rx_rate_ctrl;
+ u32 xfi_rx_mode;
+ u32 osr;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ osr = BIT(1) | BIT(0); /* 1.25G */
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = false;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(5) | BIT(3) | BIT(0);
+ phyck_sel = BIT(0);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_1G25;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ osr = BIT(0); /* 2.5G */
+ pr_cdr_beta_dac = BIT(2) | BIT(1);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = true;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(3) | BIT(1) | BIT(0);
+ phyck_sel = BIT(0);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_3G12;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ osr = 0; /* 10G */
+ cdr_pr_cap_en = false;
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = BIT(1);
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(1);
+ phyck_div = BIT(6) | BIT(1);
+ phyck_sel = BIT(1);
+ xfi_rx_mode = AIROHA_PCS_PMA_XFI_RX_MODE_10G3;
+ break;
+ default:
+ return;
+ }
+
+ /* Set RX rate ctrl */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_2,
+ AIROHA_PCS_PMA_CK_RATE,
+ AIROHA_PCS_PMA_CK_RATE_10);
+
+ if (priv->data->port_type == AIROHA_PCS_PCIE) {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_29,
+ AIROHA_PCS_PMA_2L_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_2L_RX_RATE_CTRL,
+ rx_rate_ctrl));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_ADD_XPON_MODE_1,
+ AIROHA_PCS_PMA_XFI_RX_MODE,
+ xfi_rx_mode);
+ } else {
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+ AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ rx_rate_ctrl));
+ }
+
+ /* Setup RX Path */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_5,
+ AIROHA_PCS_PMA_FLL_IDAC_MIN |
+ AIROHA_PCS_PMA_FLL_IDAC_MAX,
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_EYE_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E1_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_E0_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D1_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_D0_BYPASS_AEQ], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VCM_GEN_PWDB], 0x1);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+ AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_AEQ_OFORCE],
+ AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_OSCAL_FORCE],
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+ AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+ AIROHA_PCS_PMA_DISB_LEQ);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_PICAL_CKD8_INV], 0x0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
+ AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_DAC_MON], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_XFICK_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPI_EN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_MONPR_EN], 0x0);
+
+ /* Setup FE Gain and FE Peacking */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0));
+
+ /* Setup FE VOS */
+ if (interface != PHY_INTERFACE_MODE_USXGMII &&
+ interface != PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
+
+ /* Setup FLL PR FMeter (no bypass mode)*/
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
+ AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
+ AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
+
+ /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
+ /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
+ /* Setup REV */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF1_BIAS_CTRL],
+ BIT(2));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_FE_BUF2_BIAS_CTRL],
+ BIT(2));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_REV_1_SIGDET_ILEAK], 0x0);
+
+ /* Setup Rdy Timeout */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+ AIROHA_PCS_PMA_RX_RDY |
+ AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+ /* Setup CaBoundry Init */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+ AIROHA_PCS_PMA_RX_OS_START |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+ AIROHA_PCS_PMA_RX_OS_END,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+ AIROHA_PCS_PMA_RX_PICAL_END |
+ AIROHA_PCS_PMA_RX_PICAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+ AIROHA_PCS_PMA_RX_SDCAL_END |
+ AIROHA_PCS_PMA_RX_SDCAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+ AIROHA_PCS_PMA_RX_PDOS_END |
+ AIROHA_PCS_PMA_RX_PDOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+ AIROHA_PCS_PMA_RX_FEOS_END |
+ AIROHA_PCS_PMA_RX_FEOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+ /* Setup By Serdes*/
+ /* Setup RX OSR */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PD_EDGE_DIS], !!osr);
+
+ /* Setup CDR LPF Ratio */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_TOP_LIM], 0x20000);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_LPF_RATIO], osr);
+
+ /* Setup CDR PR */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_KBAND_DIV], 0x4);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_SEL], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VCOADC_OS], 0x8);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_BETA_DAC],
+ pr_cdr_beta_dac);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_FBKSEL], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_DAC_BAND],
+ pr_cdr_beta_dac);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_CKBUF_VAL], 0x6);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_VREG_IBAND_VAL], 0x6);
+
+ /* Setup Eye Mon */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,
+ AIROHA_PCS_PMA_EQ_DEBUG_SEL |
+ AIROHA_PCS_PMA_FOM_NUM_ORDER |
+ AIROHA_PCS_PMA_A_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
+ FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+ FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+ AIROHA_PCS_PMA_DATA_SHIFT |
+ AIROHA_PCS_PMA_EYECNT_FAST,
+ AIROHA_PCS_PMA_EYECNT_FAST);
+
+ /* Calibration Start */
+
+ /* Enable SYS */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+ AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+ AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+ usleep_range(500, 600);
+
+ /* Setup FLL PR FMeter (bypass mode)*/
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+ /* Enable CMLEQ */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_EQ_HZEN], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ3_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ2_EN], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_FE_VB_EQ1_EN], 0x1);
+
+ /* Setup CDR PR */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_CAP_EN],
+ cdr_pr_cap_en);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_BUF_IN_SR],
+ cdr_pr_buf_in_sr);
+
+ /* Setup CDR xxx Pwdb, set force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* FIXME: Ask Airoha WHY it's cleared? */
+ /* regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+ * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
+ */
+
+ /* Setup SigDet */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_VTH_SEL],
+ sigdet_vth_sel);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_PEAK],
+ BIT(1));
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_SIGDET_LPF_CTRL],
+ BIT(1) | BIT(0));
+
+ /* Disable SigDet Pwdb */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+ /* Setup PHYCK */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_TDC_CK_SEL], 0x0);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_RSTB], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_SEL],
+ phyck_sel);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHYCK_DIV],
+ phyck_div);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL_FORCE], 0x1);
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_RX_PHY_CK_SEL], 0x0);
+
+ usleep_range(100, 200);
+
+ /* Enable CDR xxx Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* Enable SigDet Pwdb */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+}
+
+static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
+ int index, u32 cdr_pr_idac)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 val = UINT_MAX;
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ cdr_pr_idac));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
+
+ usleep_range(5000, 7000);
+
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+
+ return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
+}
+
+static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv,
+ int index, u32 target_fl_out)
+{
+ unsigned int fl_out_diff = UINT_MAX;
+ unsigned int prcal_search;
+ u32 cdr_pr_idac = 0;
+
+ for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
+ unsigned int fl_out_diff_new;
+ unsigned int fl_out;
+ u32 cdr_pr_idac_tmp;
+
+ /* try to find the upper value by setting the last 3 bit */
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ prcal_search);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff_new < fl_out_diff) {
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ fl_out_diff = fl_out_diff_new;
+ }
+ }
+
+ return cdr_pr_idac;
+}
+
+static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, int index,
+ u32 target_fl_out, u32 cdr_pr_idac_major)
+{
+ unsigned int remaining_prcal_search_bits = 0;
+ u32 cdr_pr_idac = cdr_pr_idac_major;
+ unsigned int fl_out, fl_out_diff;
+ int best_prcal_search_bit = -1;
+ int prcal_search_bit;
+
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);
+ fl_out_diff = abs_diff(fl_out, target_fl_out);
+
+ /* Deadline search part.
+ * We start from top bits to bottom as we progressively decrease the
+ * signal.
+ */
+ for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+ if (fl_out_diff_new < fl_out_diff) {
+ best_prcal_search_bit = prcal_search_bit;
+ fl_out_diff = fl_out_diff_new;
+ }
+ }
+
+ /* Set the idac with the best value we found and
+ * reset the search bit to start from bottom to top.
+ */
+ if (best_prcal_search_bit >= 0) {
+ cdr_pr_idac |= BIT(best_prcal_search_bit);
+ remaining_prcal_search_bits = best_prcal_search_bit;
+ prcal_search_bit = 0;
+ }
+
+ /* Fine tune part.
+ * Test remaining bits to find an even closer signal level to target
+ * by increasing the signal.
+ */
+ while (remaining_prcal_search_bits) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs_diff(fl_out, target_fl_out);
+ /* Assume we found the deadline when the new absolue signal difference
+ * from target is greater than the previous and the difference is at
+ * least 10% greater between the old and new value.
+ * This is to account for signal detection level tollerance making
+ * sure we are actually over a deadline (AKA we are getting farther
+ * from target)
+ */
+ dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n",
+ cdr_pr_idac_tmp, fl_out, fl_out_diff_new);
+
+ /* Exact match, set the bit and exit */
+ if (!fl_out_diff_new) {
+ cdr_pr_idac |= BIT(prcal_search_bit);
+ break;
+ }
+
+ if (fl_out_diff && fl_out_diff_new > fl_out_diff &&
+ (abs_diff(fl_out_diff_new, fl_out_diff) * 100) / fl_out_diff > 10) {
+ /* Exit early if we are already at the deadline */
+ if (prcal_search_bit == 0)
+ break;
+
+ /* We found the deadline, set the value to the previous
+ * bit, and reset the loop to fine tune with the
+ * remaining values.
+ */
+ cdr_pr_idac |= BIT(prcal_search_bit - 1);
+ remaining_prcal_search_bits = prcal_search_bit - 1;
+ prcal_search_bit = 0;
+ } else {
+ /* Update the signal level diff and try the next bit */
+ fl_out_diff = fl_out_diff_new;
+
+ /* If we didn't found the deadline, set the last bit
+ * and reset the loop to fine tune with the remainig
+ * values.
+ */
+ if (prcal_search_bit == remaining_prcal_search_bits - 1) {
+ cdr_pr_idac |= BIT(prcal_search_bit);
+ remaining_prcal_search_bits = prcal_search_bit;
+ prcal_search_bit = 0;
+ } else {
+ prcal_search_bit++;
+ }
+ }
+ }
+
+ return cdr_pr_idac;
+}
+
+static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ u32 cdr_pr_idac_major, cdr_pr_idac;
+ unsigned int fl_out, fl_out_diff;
+
+ u32 target_fl_out;
+ u32 cyclecnt;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */
+ case PHY_INTERFACE_MODE_1000BASEX:
+ target_fl_out = 0xa3d6;
+ cyclecnt = 32767;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */
+ target_fl_out = 0xa000;
+ cyclecnt = 20000;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */
+ case PHY_INTERFACE_MODE_10GBASER:
+ target_fl_out = 0x9edf;
+ cyclecnt = 32767;
+ break;
+ default:
+ return;
+ }
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
+ AIROHA_PCS_PMA_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+ AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+ AIROHA_PCS_PMA_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_LOCK_UNLOCKTH |
+ AIROHA_PCS_PMA_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
+ AIROHA_PCS_PMA_UNLOCK_TARGET_END |
+ AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x1);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ /* Calibration logic:
+ * First check the major value by looping with every
+ * value in the last 3 bit of CDR_PR_IDAC.
+ * Get the signal level and save the value that is closer to
+ * the target.
+ *
+ * Then check each remaining 7 bits in search of the deadline
+ * where the signal gets farther than signal target.
+ *
+ * Finally fine tune for the remaining bits to find the one that
+ * produce the closest signal level.
+ */
+ cdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv, index, target_fl_out);
+
+ cdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, index,
+ target_fl_out, cdr_pr_idac_major);
+
+ fl_out = an7581_pcs_apply_cdr_pr_idac(priv, index, cdr_pr_idac);
+ fl_out_diff = abs_diff(fl_out, target_fl_out);
+ if (fl_out_diff > 100) {
+ u32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ cdr_pr_idac_major);
+ unsigned int fl_out_tmp, fl_out_diff_tmp;
+ u32 cdr_pr_idac_tmp;
+
+ if (pr_idac_major > 0) {
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ pr_idac_major - 1);
+
+ dev_dbg(priv->dev, "Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\n",
+ fl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp);
+
+ cdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, index,
+ target_fl_out,
+ cdr_pr_idac_tmp);
+
+ fl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, index,
+ cdr_pr_idac_tmp);
+ fl_out_diff_tmp = abs_diff(fl_out_tmp, target_fl_out);
+ if (fl_out_diff_tmp < fl_out_diff) {
+ fl_out = fl_out_tmp;
+ fl_out_diff = fl_out_diff_tmp;
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ }
+ }
+ }
+ dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
+ if (fl_out_diff > 100)
+ dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n",
+ fl_out_diff, target_fl_out);
+
+ /* Setup Load Band */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CDR_PR_INJ_FORCE_OFF], 0x0);
+
+ /* Disable force of LPF C previously enabled */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_B,
+ AIROHA_PCS_PMA_LOAD_EN);
+
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_RX_FLL_1,
+ AIROHA_PCS_PMA_LPATH_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+}
+
+/* This is used to both calibrate and lock to signal (after a previous
+ * calibration) after a global reset.
+ */
+static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, int index,
+ phy_interface_t interface, bool calibrate)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Setup LPF L2D force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+ /* Calibrate IDAC and setup Load Band */
+ if (calibrate)
+ an7581_pcs_rx_prcal(priv, index, interface);
+
+ /* Setup LPF RSTB force and disable */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ usleep_range(700, 1000);
+
+ /* Force Enable LPF RSTB */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+ usleep_range(100, 200);
+
+ /* Force Enable LPF L2D */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+ /* Disable LPF RSTB force bit */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ /* Disable LPF L2D force bit */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+}
+
+static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ int calibration_try = 0;
+ u32 val = 0;
+
+ an7581_pcs_tx_bringup(priv, index, interface);
+ an7581_pcs_rx_bringup(priv, index, interface);
+
+ usleep_range(100, 200);
+
+retry_calibration:
+ an7581_pcs_cdr_reset(priv, index, interface, priv->manual_rx_calib);
+
+ /* Global reset clear */
+ regmap_update_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ /* Global reset */
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+ usleep_range(5000, 7000);
+
+ an7581_pcs_cdr_reset(priv, index, interface, false);
+
+ /* Manual RX calibration is required only for SoC before E2
+ * revision. E2+ SoC autocalibrate RX and only CDR reset is needed.
+ */
+ if (!priv->manual_rx_calib)
+ return 0;
+
+ /* It was discovered that after a global reset and auto mode gets
+ * actually enabled, the fl_out from calibration might change and
+ * might deviates a lot from the expected value it was calibrated for.
+ * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
+ * (frequency level output) or no signal can correctly be transmitted.
+ * This is detected by checking the FreqDet module Lock bit.
+ *
+ * If it's detected that the FreqDet module is not locked, retry
+ * calibration. From observation on real hardware with a 10g SFP module,
+ * it required a maximum of an additional calibration to actually make
+ * the FreqDet module to lock. Try 50 times before failing to handle
+ * really strange case.
+ */
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+ if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
+ if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
+ dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
+ AIROHA_PCS_MAX_CALIBRATION_TRY);
+ return -EIO;
+ }
+
+ calibration_try++;
+
+ dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
+ goto retry_calibration;
+ }
+
+ return 0;
+}
+
+static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ an7581_pcs_jcpll_bringup(priv, index, interface);
+
+ usleep_range(200, 300);
+
+ an7581_pcs_txpll_bringup(priv, index, interface);
+
+ usleep_range(200, 300);
+}
+
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv, int index,
+ phy_interface_t interface)
+{
+ struct regmap_field **pcs_ana_fields = priv->pcs_ana_fields[index];
+
+ /* Enable Analog Common Lane */
+ regmap_field_write(pcs_ana_fields[AN7581_PCS_CMN_EN], 0x1);
+
+ /* Setup PLL */
+ an7581_pcs_pll_bringup(priv, index, interface);
+
+ msleep(100);
+
+ /* Setup PHYA */
+ return an7581_pcs_phya_bringup(priv, index, interface);
+}
+
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ int index, phy_interface_t interface)
+{
+ int ret;
+
+ ret = phy_set_mode_ext(priv->phy, PHY_MODE_ETHERNET, interface);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1, 0xc) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, 0x3));
+
+ regmap_set_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ } else {
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ }
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32);
+
+ regmap_clear_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE);
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, 0x1));
+
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK)));
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII);
+ else
+ regmap_update_bits(priv->pcs_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII);
+
+ return 0;
+}
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+
+ /* Reset TXPCS on link up */
+ regmap_clear_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_set_bits(pcs_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+}
+
+static int __an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv, int index,
+ const struct reg_field *fields)
+{
+ struct device *dev = priv->dev;
+ int i;
+
+ priv->pcs_ana_fields[index] = devm_kcalloc(dev, AN7581_PCS_FIELDS_MAX,
+ sizeof(*priv->pcs_ana_fields[index]),
+ GFP_KERNEL);
+ if (!priv->pcs_ana_fields[index])
+ return -ENOMEM;
+
+ for (i = 0; i < AN7581_PCS_FIELDS_MAX; i++) {
+ struct regmap_field *field;
+
+ field = devm_regmap_field_alloc(dev, priv->pcs_ana,
+ fields[i]);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ priv->pcs_ana_fields[index][i] = field;
+ }
+
+ return 0;
+}
+
+int an7581_pcs_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ return __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_fields);
+}
+
+int an7581_pcs_pcie_alloc_regmap_fields(struct airoha_pcs_priv *priv)
+{
+ int ret;
+
+ ret = __an7581_pcs_alloc_regmap_fields(priv, 0, an7581_pcs_pcie0_fields);
+ if (ret)
+ return ret;
+
+ return __an7581_pcs_alloc_regmap_fields(priv, 1, an7581_pcs_pcie1_fields);
+}
+
+static bool an7581_pcs_have_rx_signal(struct airoha_pcs_priv *priv, int index)
+{
+ struct regmap *pcs_pma = priv->pcs_pma[index];
+ unsigned int count = 0;
+ u32 val = 0;
+ int i;
+
+ regmap_write(pcs_pma, AIROHA_PCS_PMA_DIG_RESERVE_0,
+ AIROHA_PCS_TRIGGER_RX_SIDGET_SCAN);
+
+ /* Scan 6 times for RX sigdet module to detect RX signal */
+ for (i = 0; i < AIROHA_PCS_MAX_RX_SIGDET_TRY; i++) {
+ regmap_read(pcs_pma, AIROHA_PCS_PMA_DIG_RO_RESERVE_2,
+ &val);
+ if (val & AIROHA_PCS_RX_SIGDET)
+ count++;
+ }
+
+ /* Consider signal presence if we detect signal at least 4 times */
+ return count >= AIROHA_PCS_MAX_RX_SIGDET_PRESENCE_CNT;
+}
+
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv, int index)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 val = 0;
+
+ /* Check if PCS is UP or Down */
+ regmap_read(maps->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_STUS_1, &val);
+ if (val & AIROHA_PCS_USXGMII_PCS_RX_LINK_STATUS_UP)
+ return 0;
+
+ /* Validate if this is consistent with RX SigDet module */
+ if (!an7581_pcs_have_rx_signal(priv, index))
+ return 0;
+
+ /* If PCS is down but RX SigDet module detected signal,
+ * trigger CDR reset.
+ */
+ an7581_pcs_cdr_reset(priv, index, PHY_INTERFACE_MODE_NA, false);
+
+ /* Report there is an error with Link Detection and we
+ * should test again later.
+ */
+ return -EINVAL;
+}
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
new file mode 100644
index 0000000000000..fef560eddf2a9
--- /dev/null
+++ b/drivers/net/pcs/pcs.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+ struct list_head link;
+
+ struct fwnode_handle *fwnode;
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+ void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
+
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier);
+
+struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_xlate);
+
+struct fwnode_pcs_provider *
+fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return ERR_PTR(-EINVAL);
+
+ pp = kzalloc_obj(*pp);
+ if (!pp)
+ return ERR_PTR(-ENOMEM);
+
+ pp->fwnode = fwnode_handle_get(fwnode);
+ pp->data = data;
+ pp->fwnode_xlate = fwnode_xlate;
+
+ mutex_lock(&fwnode_pcs_mutex);
+
+ list_add(&pp->link, &fwnode_pcs_providers);
+ fwnode_dev_initialized(fwnode, true);
+
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+ FWNODE_PCS_PROVIDER_ADD,
+ pp);
+
+ pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+ return pp;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_pcs_provider *pp)
+{
+ if (IS_ERR_OR_NULL(pp))
+ return;
+
+ mutex_lock(&fwnode_pcs_mutex);
+
+ list_del(&pp->link);
+ fwnode_dev_initialized(pp->fwnode, false);
+
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ /* Signal phylink to release any PCS from this provider */
+ blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+ FWNODE_PCS_PROVIDER_DEL,
+ pp);
+
+ fwnode_handle_put(pp->fwnode);
+ kfree(pp);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static void devm_fwnode_pcs_del(struct device *dev, void *res)
+{
+ struct fwnode_pcs_provider *pp = *(struct fwnode_pcs_provider **)res;
+
+ fwnode_pcs_del_provider(pp);
+}
+
+struct fwnode_pcs_provider *
+devm_fwnode_pcs_add_provider(struct device *dev, struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data)
+{
+ struct fwnode_pcs_provider **ptr, *pp;
+
+ ptr = devres_alloc(devm_fwnode_pcs_del, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return ERR_PTR(-ENOMEM);
+
+ pp = fwnode_pcs_add_provider(fwnode, fwnode_xlate, data);
+
+ if (!IS_ERR(pp)) {
+ *ptr = pp;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return pp;
+}
+EXPORT_SYMBOL_GPL(devm_fwnode_pcs_add_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode,
+ int index, const char *name,
+ struct fwnode_reference_args *out_args)
+{
+ if (!fwnode)
+ return -EINVAL;
+
+ if (name) {
+ index = fwnode_property_match_string(fwnode, "pcs-names",
+ name);
+ if (index < 0)
+ return index;
+ }
+
+ return fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells", 0, index,
+ out_args);
+}
+
+static struct phylink_pcs *
+__fwnode_pcs_get_from_pcsspec_provider(struct fwnode_reference_args *pcsspec,
+ struct fwnode_pcs_provider *provider)
+{
+ if (provider->fwnode != pcsspec->fwnode)
+ return ERR_PTR(-EINVAL);
+
+ return provider->fwnode_xlate(pcsspec, provider->data);
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+ struct fwnode_pcs_provider *provider;
+ struct phylink_pcs *pcs = NULL;
+
+ if (!pcsspec)
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+ pcs = __fwnode_pcs_get_from_pcsspec_provider(pcsspec, provider);
+ if (!IS_ERR(pcs))
+ break;
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ return !IS_ERR_OR_NULL(pcs) ? pcs : ERR_PTR(-ENODEV);
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(const struct fwnode_handle *fwnode,
+ unsigned int index, const char *con_id)
+{
+ struct fwnode_reference_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+ fwnode_handle_put(pcsspec.fwnode);
+
+ return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode, unsigned int index)
+{
+ return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+struct phylink_pcs *fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ int index)
+{
+ struct fwnode_reference_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = __fwnode_pcs_get_from_pcsspec_provider(&pcsspec, provider);
+ fwnode_handle_put(pcsspec.fwnode);
+ return pcs;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get_from_provider);
+
+bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ struct phylink_pcs *pl_pcs)
+{
+ struct fwnode_reference_args pcsspec;
+ int index = 0;
+ int ret;
+
+ while (true) {
+ struct phylink_pcs *pcs;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+ if (ret)
+ return false;
+
+ pcs = __fwnode_pcs_get_from_pcsspec_provider(&pcsspec, provider);
+ if (!IS_ERR(pcs) && pcs == pl_pcs) {
+ fwnode_handle_put(pcsspec.fwnode);
+ return true;
+ }
+
+ fwnode_handle_put(pcsspec.fwnode);
+ index++;
+ }
+
+ return false;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_matches_provider);
+
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ struct fwnode_reference_args out_args;
+ int index = 0;
+ int ret;
+
+ while (true) {
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells", 0, index,
+ &out_args);
+ /* We expect to reach an -ENOENT error while counting */
+ if (ret)
+ break;
+
+ fwnode_handle_put(out_args.fwnode);
+ index++;
+ }
+
+ return index;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_count);
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ unsigned int i, found = 0;
+
+ if (!available_pcs)
+ return -EINVAL;
+
+ if (!fwnode_property_present(fwnode, "pcs-handle"))
+ return -ENODEV;
+
+ for (i = 0; i < num_pcs; i++) {
+ struct phylink_pcs *pcs;
+
+ pcs = fwnode_pcs_get(fwnode, i);
+ if (IS_ERR(pcs)) {
+ /* Exit early if no PCS remain.*/
+ if (PTR_ERR(pcs) == -ENOENT)
+ break;
+
+ /*
+ * Ignore -ENODEV error for PCS that still
+ * needs to probe.
+ */
+ if (PTR_ERR(pcs) == -ENODEV)
+ continue;
+
+ return PTR_ERR(pcs);
+ }
+
+ available_pcs[found] = pcs;
+ found++;
+ }
+
+ return found;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index a7d086cdc9b25..28dad1393b694 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/phylink.h>
@@ -44,6 +45,7 @@ struct phylink {
const struct phylink_mac_ops *mac_ops;
struct phylink_config *config;
struct phylink_pcs *pcs;
+ struct fwnode_handle *fwnode;
struct device *dev;
unsigned int old_link_state:1;
@@ -60,6 +62,15 @@ struct phylink {
/* The link configuration settings */
struct phylink_link_state link_config;
+ /* List of available PCS */
+ struct list_head pcs_list;
+ struct notifier_block fwnode_pcs_nb;
+
+ /* What interface are supported by the current link.
+ * Can change on removal or addition of new PCS.
+ */
+ DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+
/* The current settings */
phy_interface_t cur_interface;
@@ -512,6 +523,22 @@ static void phylink_validate_mask_caps(unsigned long *supported,
linkmode_and(state->advertising, state->advertising, mask);
}
+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* If PCS define an empty supported_interfaces value, assume
+ * all interface are supported.
+ */
+ if (phy_interface_empty(pcs->supported_interfaces))
+ return 0;
+
+ /* Ensure that this PCS supports the interface mode */
+ if (!test_bit(interface, pcs->supported_interfaces))
+ return -EINVAL;
+
+ return 0;
+}
+
static int phylink_validate_mac_and_pcs(struct phylink *pl,
unsigned long *supported,
struct phylink_link_state *state)
@@ -520,11 +547,30 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
unsigned long capabilities;
int ret;
+ mutex_lock(&pl->state_mutex);
+
/* Get the PCS for this interface mode */
if (pl->mac_ops->mac_select_pcs) {
pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
- if (IS_ERR(pcs))
+ if (IS_ERR(pcs)) {
+ mutex_unlock(&pl->state_mutex);
return PTR_ERR(pcs);
+ }
+ /*
+ * Find a PCS in available PCS list for the requested interface.
+ *
+ * Skip searching if the MAC doesn't require a dedicated PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ struct phylink_pcs *tmp;
+
+ list_for_each_entry(tmp, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(tmp, state->interface)) {
+ pcs = tmp;
+ break;
+ }
+ }
}
if (pcs) {
@@ -533,19 +579,18 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
* error and backtrace rather than oopsing the kernel.
*/
if (!pcs->ops) {
+ mutex_unlock(&pl->state_mutex);
phylink_err(pl, "interface %s: uninitialised PCS\n",
phy_modes(state->interface));
dump_stack();
return -EINVAL;
}
- /* Ensure that this PCS supports the interface which the MAC
- * returned it for. It is an error for the MAC to return a PCS
- * that does not support the interface mode.
- */
- if (!phy_interface_empty(pcs->supported_interfaces) &&
- !test_bit(state->interface, pcs->supported_interfaces)) {
- phylink_err(pl, "MAC returned PCS which does not support %s\n",
+ /* Recheck PCS to handle legacy way for .mac_select_pcs */
+ ret = phylink_validate_pcs_interface(pcs, state->interface);
+ if (ret) {
+ mutex_unlock(&pl->state_mutex);
+ phylink_err(pl, "selected PCS does not support %s\n",
phy_modes(state->interface));
return -EINVAL;
}
@@ -553,8 +598,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
/* Validate the link parameters with the PCS */
if (pcs->ops->pcs_validate) {
ret = pcs->ops->pcs_validate(pcs, supported, state);
- if (ret < 0 || phylink_is_empty_linkmode(supported))
+ if (ret < 0 || phylink_is_empty_linkmode(supported)) {
+ mutex_unlock(&pl->state_mutex);
return -EINVAL;
+ }
/* Ensure the advertising mask is a subset of the
* supported mask.
@@ -564,6 +611,8 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
}
}
+ mutex_unlock(&pl->state_mutex);
+
/* Then validate the link parameters with the MAC */
if (pl->mac_ops->mac_get_caps)
capabilities = pl->mac_ops->mac_get_caps(pl->config,
@@ -628,7 +677,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
static int phylink_validate(struct phylink *pl, unsigned long *supported,
struct phylink_link_state *state)
{
- const unsigned long *interfaces = pl->config->supported_interfaces;
+ const unsigned long *interfaces = pl->supported_interfaces;
if (state->interface == PHY_INTERFACE_MODE_NA)
return phylink_validate_mask(pl, NULL, supported, state,
@@ -940,6 +989,12 @@ static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
}
+static void phylink_pcs_link_down(struct phylink_pcs *pcs)
+{
+ if (pcs && pcs->ops->pcs_link_down)
+ pcs->ops->pcs_link_down(pcs);
+}
+
static void phylink_pcs_disable_eee(struct phylink_pcs *pcs)
{
if (pcs && pcs->ops->pcs_disable_eee)
@@ -958,16 +1013,34 @@ static void phylink_pcs_enable_eee(struct phylink_pcs *pcs)
static unsigned int phylink_inband_caps(struct phylink *pl,
phy_interface_t interface)
{
- struct phylink_pcs *pcs;
+ struct phylink_pcs *pcs = NULL;
+ int ret = 0;
- if (!pl->mac_ops->mac_select_pcs)
- return 0;
+ mutex_lock(&pl->state_mutex);
+
+ if (pl->mac_ops->mac_select_pcs) {
+ pcs = pl->mac_ops->mac_select_pcs(pl->config,
+ interface);
+ } else if (test_bit(interface, pl->config->pcs_interfaces)) {
+ struct phylink_pcs *tmp;
+
+ list_for_each_entry(tmp, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(tmp, interface)) {
+ pcs = tmp;
+ break;
+ }
+ }
+ }
- pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
if (IS_ERR_OR_NULL(pcs))
- return 0;
+ goto exit;
- return phylink_pcs_inband_caps(pcs, interface);
+ ret = phylink_pcs_inband_caps(pcs, interface);
+
+exit:
+ mutex_unlock(&pl->state_mutex);
+
+ return ret;
}
static void phylink_pcs_poll_stop(struct phylink *pl)
@@ -1260,10 +1333,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
pl->major_config_failed = true;
return;
}
+ /* Find a PCS in available PCS list for the requested interface.
+ * This doesn't overwrite the previous .mac_select_pcs as either
+ * .mac_select_pcs or PCS list implementation are permitted.
+ *
+ * Skip searching if the MAC doesn't require a dedicated PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ struct phylink_pcs *tmp;
+
+ list_for_each_entry(tmp, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(tmp,
+ state->interface)) {
+ pcs = tmp;
+ break;
+ }
+ }
- pcs_changed = pl->pcs != pcs;
+ if (!pcs) {
+ phylink_err(pl,
+ "couldn't find a PCS for %s\n",
+ phy_modes(state->interface));
+
+ pl->major_config_failed = true;
+ return;
+ }
}
+ pcs_changed = pl->pcs != pcs;
+
phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
phylink_dbg(pl, "major config, active %s/%s/%s\n",
@@ -1290,13 +1389,15 @@ static void phylink_major_config(struct phylink *pl, bool restart,
if (pcs_changed) {
phylink_pcs_disable(pl->pcs);
- if (pl->pcs)
- pl->pcs->phylink = NULL;
+ if (pl->mac_ops->mac_select_pcs) {
+ if (pl->pcs)
+ pl->pcs->phylink = NULL;
- if (pcs)
- pcs->phylink = pl;
+ if (pcs)
+ pcs->phylink = pl;
+ }
- pl->pcs = pcs;
+ WRITE_ONCE(pl->pcs, pcs);
}
if (pl->pcs)
@@ -1480,7 +1581,9 @@ static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)
phylink_apply_manual_flow(pl, &link_state);
if (phy)
mutex_lock(&phy->lock);
+ mutex_lock(&pl->state_mutex);
phylink_major_config(pl, force_restart, &link_state);
+ mutex_unlock(&pl->state_mutex);
if (phy)
mutex_unlock(&phy->lock);
}
@@ -1604,6 +1707,9 @@ static void phylink_link_down(struct phylink *pl)
pl->mac_ops->mac_link_down(pl->config, pl->act_link_an_mode,
pl->cur_interface);
+
+ phylink_pcs_link_down(pl->pcs);
+
phylink_info(pl, "Link is Down\n");
}
@@ -1831,6 +1937,179 @@ int phylink_set_fixed_link(struct phylink *pl,
}
EXPORT_SYMBOL_GPL(phylink_set_fixed_link);
+static bool phylink_add_pcs(struct phylink *pl, struct phylink_pcs *pcs)
+{
+ struct phylink_pcs *tmp;
+
+ /*
+ * Make sure state mutex is locked to protect concurrent
+ * access to phylink instance PCS list from
+ * initial fill_available_pcs and late PCS attach
+ */
+ lockdep_assert_held(&pl->state_mutex);
+
+ /* Make sure PCS is not already in the list */
+ list_for_each_entry(tmp, &pl->pcs_list, list)
+ if (tmp == pcs)
+ return false;
+
+ list_add_tail(&pcs->list, &pl->pcs_list);
+
+ /* Link PCS to phylink */
+ pcs->phylink = pl;
+
+ return true;
+}
+
+static int phylink_fill_available_pcs(struct phylink *pl,
+ struct phylink_config *config)
+{
+ struct phylink_pcs **pcss;
+ int i, ret;
+
+ if (!config->num_possible_pcs)
+ return 0;
+
+ if (!config->fill_available_pcs) {
+ dev_err(config->dev,
+ "phylink: error: num_possible_pcs defined but no fill_available_pcs\n");
+ return -EINVAL;
+ }
+
+ pcss = kzalloc_objs(*pcss, config->num_possible_pcs);
+ if (!pcss)
+ return -ENOMEM;
+
+ /* Lock state_mutex while filling to handle PCS notify */
+ mutex_lock(&pl->state_mutex);
+
+ ret = config->fill_available_pcs(config, pcss, config->num_possible_pcs);
+ if (ret < 0)
+ goto out;
+
+ for (i = 0; i < config->num_possible_pcs; i++) {
+ struct phylink_pcs *pcs = pcss[i];
+
+ if (!pcs)
+ continue;
+
+ phylink_add_pcs(pl, pcs);
+ }
+
+out:
+ mutex_unlock(&pl->state_mutex);
+
+ kfree(pcss);
+
+ return ret;
+}
+
+static void phylink_del_pcs(struct phylink *pl, struct phylink_pcs *pcs)
+{
+ lockdep_assert_held(&pl->state_mutex);
+
+ list_del(&pcs->list);
+ pcs->phylink = NULL;
+
+ /*
+ * Check if we are removing the PCS currently
+ * in use by this phylink instance. If this is the case,
+ * tear down the link, force phylink resolve to reconfigure the
+ * interface mode, disable the current PCS and set the
+ * phylink PCS to NULL.
+ */
+ if (pl->pcs == pcs) {
+ if (pl->old_link_state) {
+ phylink_link_down(pl);
+ pl->old_link_state = false;
+ }
+ if (pl->cfg_link_an_mode == MLO_AN_INBAND)
+ timer_delete_sync(&pl->link_poll);
+ phylink_pcs_disable(pl->pcs);
+
+ pl->force_major_config = true;
+ WRITE_ONCE(pl->pcs, NULL);
+ }
+}
+
+static int pcs_provider_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+ struct fwnode_pcs_provider *pp = data;
+ struct phylink_pcs *pcs, *tmp;
+ bool resolve = false;
+ int count, i;
+
+ rtnl_lock();
+
+ mutex_lock(&pl->state_mutex);
+
+ switch (val) {
+ case FWNODE_PCS_PROVIDER_ADD:
+ count = fwnode_phylink_pcs_count(pl->fwnode);
+ for (i = 0; i < count; i++) {
+ pcs = fwnode_pcs_get_from_provider(pp, pl->fwnode, i);
+ if (IS_ERR(pcs))
+ continue;
+
+ /* Trigger a resolve only if a PCS is actually added */
+ if (phylink_add_pcs(pl, pcs))
+ resolve = true;
+ }
+
+ /* Force an interface reconfig if major config fail */
+ if (resolve && pl->major_config_failed)
+ pl->force_major_config = true;
+
+ break;
+ case FWNODE_PCS_PROVIDER_DEL:
+ /*
+ * Loop all the PCS for phylink instance and check if
+ * this notification is relevant for some of them.
+ */
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) {
+ if (!fwnode_pcs_matches_provider(pp, pl->fwnode, pcs))
+ continue;
+
+ phylink_del_pcs(pl, pcs);
+ resolve = true;
+ }
+ break;
+ }
+
+ /* Exit early if nothing has changed */
+ if (!resolve) {
+ mutex_unlock(&pl->state_mutex);
+
+ rtnl_unlock();
+
+ return NOTIFY_DONE;
+ }
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ mutex_unlock(&pl->state_mutex);
+
+ /* Recalculate capabilities */
+ linkmode_fill(pl->supported);
+ linkmode_fill(pl->link_config.advertising);
+ phylink_validate_mask(pl, NULL, pl->supported, &pl->link_config,
+ pl->supported_interfaces);
+
+ rtnl_unlock();
+
+ phylink_run_resolve(pl);
+
+ return NOTIFY_OK;
+}
+
/**
* phylink_update_pause_state() - Update the phylink pause frame configuration
* @pl: a pointer to a &struct phylink instance
@@ -1972,9 +2251,20 @@ struct phylink *phylink_create(struct phylink_config *config,
phy_interface_t iface,
const struct phylink_mac_ops *mac_ops)
{
+ struct phylink_pcs *tmp, *pcs;
struct phylink *pl;
int ret;
+ /*
+ * Make sure either PCS internal validation or .mac_select_pcs
+ * is used. Return error if both are defined.
+ */
+ if (config->num_possible_pcs && mac_ops->mac_select_pcs) {
+ dev_err(config->dev,
+ "phylink: error: either phylink_config .num_possible_pcs or .mac_select_pcs must be used\n");
+ return ERR_PTR(-EINVAL);
+ }
+
/* Validate the supplied configuration */
if (phy_interface_empty(config->supported_interfaces)) {
dev_err(config->dev,
@@ -1989,8 +2279,10 @@ struct phylink *phylink_create(struct phylink_config *config,
mutex_init(&pl->phydev_mutex);
mutex_init(&pl->state_mutex);
INIT_WORK(&pl->resolve, phylink_resolve);
+ INIT_LIST_HEAD(&pl->pcs_list);
pl->config = config;
+ pl->fwnode = fwnode_handle_get((struct fwnode_handle *)fwnode);
if (config->type == PHYLINK_NETDEV) {
pl->netdev = to_net_dev(config->dev);
netif_carrier_off(pl->netdev);
@@ -2026,13 +2318,37 @@ struct phylink *phylink_create(struct phylink_config *config,
__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
+ /* First register notifier for hotplug PCS events */
+ if (!phy_interface_empty(config->pcs_interfaces)) {
+ pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+ register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+ }
+
+ /* Fill the PCS list with available PCS from phylink config */
+ ret = phylink_fill_available_pcs(pl, config);
+ if (ret < 0)
+ goto unregister_pcs_notify;
+
+ mutex_lock(&pl->state_mutex);
+
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+
+ /* Update supported interfaces */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ mutex_unlock(&pl->state_mutex);
+
linkmode_fill(pl->supported);
linkmode_copy(pl->link_config.advertising, pl->supported);
phylink_validate(pl, pl->supported, &pl->link_config);
ret = phylink_parse_mode(pl, fwnode);
if (ret < 0)
- goto free_pl;
+ goto unregister_pcs_notify;
if (pl->cfg_link_an_mode == MLO_AN_FIXED) {
ret = phylink_parse_fixedlink(pl, fwnode);
@@ -2051,7 +2367,19 @@ struct phylink *phylink_create(struct phylink_config *config,
release_link_gpio:
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+unregister_pcs_notify:
+ if (pl->fwnode_pcs_nb.notifier_call)
+ unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+ /* PCS notifier might queue a resolve, cancel it */
+ cancel_work_sync(&pl->resolve);
+ mutex_lock(&pl->state_mutex);
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) {
+ list_del(&pcs->list);
+ pcs->phylink = NULL;
+ }
+ mutex_unlock(&pl->state_mutex);
free_pl:
+ fwnode_handle_put(pl->fwnode);
kfree(pl);
return ERR_PTR(ret);
}
@@ -2068,11 +2396,30 @@ EXPORT_SYMBOL_GPL(phylink_create);
*/
void phylink_destroy(struct phylink *pl)
{
+ struct phylink_pcs *pcs, *tmp;
+
sfp_bus_del_upstream(pl->sfp_bus);
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+ /* Unregister notifier for late PCS attach */
+ if (pl->fwnode_pcs_nb.notifier_call)
+ unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+
cancel_work_sync(&pl->resolve);
+
+ mutex_lock(&pl->state_mutex);
+
+ /* Remove every PCS from phylink PCS list */
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list) {
+ pcs->phylink = NULL;
+ list_del(&pcs->list);
+ }
+
+ mutex_unlock(&pl->state_mutex);
+
+ fwnode_handle_put(pl->fwnode);
+
kfree(pl);
}
EXPORT_SYMBOL_GPL(phylink_destroy);
@@ -2147,7 +2494,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
* those which the host supports.
*/
phy_interface_and(interfaces, phy->possible_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
if (phy_interface_empty(interfaces)) {
phylink_err(pl, "PHY has no common interfaces\n");
@@ -2538,8 +2885,15 @@ void phylink_pcs_change(struct phylink_pcs *pcs, bool up)
{
struct phylink *pl = pcs->phylink;
- if (pl)
- phylink_link_changed(pl, up, "pcs");
+ /*
+ * Ignore PCS link state change if the PCS is not
+ * attached to a phylink instance or the phylink
+ * instance is not currently using this PCS.
+ */
+ if (!pl || READ_ONCE(pl->pcs) != pcs)
+ return;
+
+ phylink_link_changed(pl, up, "pcs");
}
EXPORT_SYMBOL_GPL(phylink_pcs_change);
@@ -2961,12 +3315,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,
return interface;
}
- if (!test_bit(interface, pl->config->supported_interfaces)) {
+ if (!test_bit(interface, pl->supported_interfaces)) {
phylink_err(pl,
"selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\n",
phy_modes(interface), interface,
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
return PHY_INTERFACE_MODE_NA;
}
@@ -3845,14 +4199,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)
phylink_dbg(pl, "optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\n",
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces,
+ pl->supported_interfaces,
(int)PHY_INTERFACE_MODE_MAX,
pl->sfp_interfaces);
/* Find the union of the supported interfaces by the PCS/MAC and
* the SFP module.
*/
- phy_interface_and(pl->sfp_interfaces, pl->config->supported_interfaces,
+ phy_interface_and(pl->sfp_interfaces, pl->supported_interfaces,
pl->sfp_interfaces);
if (phy_interface_empty(pl->sfp_interfaces)) {
phylink_err(pl, "unsupported SFP module: no common interface modes\n");
@@ -4023,7 +4377,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
/* Set the PHY's host supported interfaces */
phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
/* Do the initial configuration */
return phylink_sfp_config_phy(pl, phy);
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 0000000000000..15c198ffdd580
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+struct fwnode_pcs_provider;
+
+/**
+ * fwnode_pcs_simple_xlate - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns: the PCS pointed by data.
+ */
+struct phylink_pcs *fwnode_pcs_simple_xlate(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @fwnode: Firmware node
+ * @fwnode_xlate: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS provider to the global providers list
+ * for the firmware node. The relevant PCS from the PCS provider
+ * is retrieved from the passed fwnode_xlate function.
+ *
+ * The xlate function MUST return a pointer to an existing, already-allocated
+ * struct phylink_pcs and MUST NOT dynamically allocate a new PCS.
+ * The same PCS object must be returned for a given firmware reference and args,
+ * as PCS pointer identity is used to associate PCS objects with their provider.
+ *
+ * Returns: A pointer to the registered PCS provider on success, or
+ * an ERR_PTR() encoded error code on failure.
+ */
+struct fwnode_pcs_provider *
+fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @pp: PCS provider returned by fwnode_pcs_add_provider()
+ */
+void fwnode_pcs_del_provider(struct fwnode_pcs_provider *pp);
+
+/**
+ * devm_fwnode_pcs_add_provider - Registers a new PCS provider
+ * @dev: Device of the PCS provider
+ * @fwnode: Firmware node
+ * @fwnode_xlate: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS provider to the global providers list
+ * for the firmware node. The relevant PCS from the PCS provider
+ * is retrieved from the passed fwnode_xlate function. While at that, it
+ * also associates the device with the PCS provider using devres.
+ * On driver detach, release function is invoked on the devres data,
+ * then, devres data is freed.
+ *
+ * Returns: A pointer to the registered PCS provider on success, or
+ * an ERR_PTR() encoded error code on failure.
+ */
+struct fwnode_pcs_provider *
+devm_fwnode_pcs_add_provider(struct device *dev, struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*fwnode_xlate)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 0000000000000..00a636c82c65f
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+enum fwnode_pcs_notify_event {
+ FWNODE_PCS_PROVIDER_ADD,
+ FWNODE_PCS_PROVIDER_DEL,
+};
+
+struct fwnode_pcs_provider;
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns: 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
+/**
+ * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Unregisters a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain.
+ *
+ * Returns: 0 or a negative error.
+ */
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb);
+
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative error pointer. Can
+ * return -ENODEV if the PCS is not present in global providers list (either
+ * due to driver still needs to be probed or it failed to probe/removed).
+ */
+struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode,
+ unsigned int index);
+
+/**
+ * fwnode_pcs_get_from_provider() - Retrieve a PCS from a specific provider
+ * @provider: PCS provider to use
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index specifically provided by
+ * passed PCS provider.
+ *
+ * Unlike fwnode_pcs_get(), this function does not search the global list of
+ * PCS providers. The caller must provide the provider responsible for the
+ * referenced PCS.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative error pointer. Can
+ * return -ENODEV if the PCS is not present in global providers list (either
+ * due to driver still needs to be probed or it failed to probe/removed) or
+ * can return -EINVAL if the PCS provider doesn't expose any PCS for the fwnode.
+ */
+struct phylink_pcs *fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ int index);
+
+/**
+ * fwnode_pcs_matches_provider() - Check whether a PCS belongs to a provider
+ * @provider: PCS provider to check
+ * @fwnode: firmware node containing the PCS references
+ * @pl_pcs: PCS to check
+ *
+ * Parse the PCS references from the "pcs-handle" property of a firmware node
+ * and use provider to determine whether pl_pcs is one of the PCS provided by
+ * provider.
+ *
+ * This function is intended to be used when handling provider removal
+ * notifications, where the provider is already known and its PCS need to be
+ * identified among the PCS associated with a phylink instance.
+ *
+ * Returns: true if pl_pcs is provided by provider and referenced by fwnode,
+ * false otherwise.
+ */
+bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ struct phylink_pcs *pl_pcs);
+
+/**
+ * fwnode_phylink_pcs_count - Count PCS entries described in firmware node
+ * @fwnode: firmware node
+ *
+ * Helper function to count the number of PCS entries referenced by the
+ * "pcs-handle" property in a firmware node.
+ *
+ * Note that this function counts all PCS references in the firmware node,
+ * regardless of whether the corresponding PCS devices are already probed.
+ *
+ * Returns: number of PCS entries described in the firmware node.
+ */
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode);
+
+/**
+ * fwnode_phylink_pcs_parse - Parse available PCS from firmware node
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: maximum number of PCS entries to scan
+ *
+ * Helper function that parses PCS references from the "pcs-handle"
+ * property of a firmware node and fills @available_pcs with PCS that are
+ * currently available up to @num_pcs.
+ *
+ * Only PCS that are currently available are stored in @available_pcs.
+ * PCS that returns -ENODEV are skipped.
+ *
+ * Returns: number of PCS stored in @available_pcs, or negative error code.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs);
+#else
+static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline struct phylink_pcs *fwnode_pcs_get(const struct fwnode_handle *fwnode,
+ unsigned int index)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline struct phylink_pcs *
+fwnode_pcs_get_from_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ int index)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline bool fwnode_pcs_matches_provider(struct fwnode_pcs_provider *provider,
+ const struct fwnode_handle *fwnode,
+ struct phylink_pcs *pl_pcs)
+{
+ return false;
+}
+
+static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ return 0;
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 3a88a69882a61..f03c1dc0a4a11 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -12,6 +12,7 @@ struct ethtool_cmd;
struct fwnode_handle;
struct net_device;
struct phylink;
+struct phylink_pcs;
enum {
MLO_PAUSE_NONE,
@@ -151,6 +152,8 @@ enum phylink_op_type {
* if MAC link is at %MLO_AN_FIXED mode.
* @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
* are supported by the MAC/PCS.
+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
+ * dedicated PCS is required.
* @lpi_interfaces: bitmap describing which PHY interface modes can support
* LPI signalling.
* @mac_capabilities: MAC pause/speed/duplex capabilities.
@@ -160,6 +163,10 @@ enum phylink_op_type {
* @wol_phy_legacy: Use Wake-on-Lan with PHY even if phy_can_wakeup() is false
* @wol_phy_speed_ctrl: Use phy speed control on suspend/resume
* @wol_mac_support: Bitmask of MAC supported %WAKE_* options
+ * @num_possible_pcs: num of possible phylink_pcs PCS
+ * @fill_available_pcs: callback to fill the available PCS in the passed
+ * array struct of phylink_pcs PCS available_pcs up to
+ * num_possible_pcs.
*/
struct phylink_config {
struct device *dev;
@@ -172,6 +179,7 @@ struct phylink_config {
void (*get_fixed_state)(struct phylink_config *config,
struct phylink_link_state *state);
DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+ DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
unsigned long mac_capabilities;
unsigned long lpi_capabilities;
@@ -182,6 +190,11 @@ struct phylink_config {
bool wol_phy_legacy;
bool wol_phy_speed_ctrl;
u32 wol_mac_support;
+
+ unsigned int num_possible_pcs;
+ int (*fill_available_pcs)(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs);
};
void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
@@ -497,6 +510,9 @@ struct phylink_pcs {
struct phylink *phylink;
bool poll;
bool rxc_always_on;
+
+ /* private: */
+ struct list_head list;
};
/**
@@ -512,6 +528,7 @@ struct phylink_pcs {
* @pcs_an_restart: restart 802.3z BaseX autonegotiation.
* @pcs_link_up: program the PCS for the resolved link configuration
* (where necessary).
+ * @pcs_link_down: tear down link between MAC and PCS.
* @pcs_disable_eee: optional notification to PCS that EEE has been disabled
* at the MAC.
* @pcs_enable_eee: optional notification to PCS that EEE will be enabled at
@@ -539,6 +556,7 @@ struct phylink_pcs_ops {
void (*pcs_an_restart)(struct phylink_pcs *pcs);
void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface, int speed, int duplex);
+ void (*pcs_link_down)(struct phylink_pcs *pcs);
void (*pcs_disable_eee)(struct phylink_pcs *pcs);
void (*pcs_enable_eee)(struct phylink_pcs *pcs);
int (*pcs_pre_init)(struct phylink_pcs *pcs);
@@ -674,6 +692,16 @@ void pcs_an_restart(struct phylink_pcs *pcs);
void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface, int speed, int duplex);
+/**
+ * pcs_link_down() - tear down link between MAC and PCS
+ * @pcs: a pointer to a &struct phylink_pcs.
+ *
+ * This call will be made just after mac_link_down() to inform the PCS the
+ * link has gone down. PCS should be configured to stop processing packets
+ * for transmission and reception.
+ */
+void pcs_link_down(struct phylink_pcs *pcs);
+
/**
* pcs_disable_eee() - Disable EEE at the PCS
* @pcs: a pointer to a &struct phylink_pcs
|
| 49/3 | 2026/10/09 22:02 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 140031 output: 37 thoughts: 2643 Thoughts: **KMSAN Assessment: Airoha Ethernet PCS Driver Patch Series** Okay, let's break this down. My goal here is to determine if this patch series necessitates a KMSAN session. Given my experience, I'm acutely aware of the resource overhead of KMSAN and I only want to deploy it if absolutely critical for detecting uninitialized memory reads that KASAN or other standard bug detectors would miss. The patch touches documentation, Airoha Ethernet driver code, the PCS subsystem, and Phylink core code. Let's see what we have here. First, let's establish the context: We're on amd64, and KASAN is already enabled. That means we have the standard checks for OOB, UAF, double frees, and memory corruption covered. KMSAN is for catching reads of *uninitialized* memory, which can lead to information leaks or unpredictable behavior. My rule is simple: If KASAN, LOCKDEP, or similar tools can catch a bug, *we don't need KMSAN*. KMSAN is for those tricky cases where uninitialized memory is read. So, my focus is on identifying situations where: 1. Kernel structures might be sent to userspace with uninitialized fields. 2. Conditional logic relies on potentially uninitialized variables. 3. Complex data structures are allocated where uninitialized fields could be read later. 4. There could be bounds checks that allow access to uninitialized bytes of existing buffers. Conversely, I can rule out KMSAN if: * The code is primarily about OOB access, overflows, NULL dereferences, deadlocks, or UAF bugs. * All stack/heap structures are zeroed or initialized before use. * The patch doesn't introduce any risk of uninitialized memory usage or leaks. Okay, let's dig into the code changes. **Part 1: `airoha_eth.c`** * `airoha_dev_open/stop`: Uses `phylink_*` functions. These functions seem to be standard operations for setting up and tearing down the link, which does not look like there are risks of uninitialized memory here. * `airoha_ethtool_get_link_ksettings`: This one is interesting. The key question is whether data is copied to userspace and if anything is uninitialized. My focus is now on `phylink_ethtool_ksettings_get` and ethtool, and whether it could lead to uninitialized memory being exposed. Ethtool core allocates and zeroes `cmd`, but I need to make sure `phylink_ethtool_ksettings_get` itself doesn't introduce a problem. * `airoha_mac_link_up`: Reads/writes registers via `airoha_fe_rmw`. This seems safe; register operations don't typically involve uninitialized memory concerns. * `airoha_fill_available_pcs`: Calls `fwnode_phylink_pcs_parse`. * `airoha_setup_phylink`: Allocates the `dev` struct with `kzalloc`, so `dev->phylink_config` is zero-initialized. Also calls `phylink_create`. **Part 2: `drivers/net/pcs/pcs.c`** * `fwnode_pcs_add_provider`, `devm_fwnode_pcs_add_provider`: These use `kzalloc`. Good. * `fwnode_parse_pcsspec`: Parses property data. No concerns here as far as I can see. * `fwnode_phylink_pcs_parse`: The key here is the `available_pcs` array. It looks like it is zero-allocated with `kzalloc_objs` and initialized by a caller. `pcss` is freed with `kfree`. The entire structure seems properly handled to prevent the use of uninitialized memory. **Part 3: `drivers/net/pcs/airoha/pcs-airoha-common.c`** * `airoha_pcs_probe`: Uses `devm_kzalloc` and `devm_kcalloc`. Excellent! All allocated memory is zero-initialized. * `an7581_pcs_alloc_regmap_fields`: Uses `devm_kcalloc`. Also zero-initialized. * All register operations: All variables are initialized to zero before register reads. This is good coding practice. There's a check on a return value before reading `val`. **Part 4: `drivers/net/pcs/airoha/pcs-an7581.c`** * `an7581_pcs_phya_bringup`, |
| 50/3 | 2026/10/09 22:02 | tool | grepper |
0mError:no matches Args: {
"Expression": "kzalloc.*struct phylink",
"PathPrefixes": [
"drivers/net/phy/phylink.c"
]
}Results: {
"error": "no matches"
} |
| 51/3 | 2026/10/09 22:02 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 143750 output: 39 thoughts: 23 Thoughts: Okay, let's dive into this. Here's my take on understanding this code: **Analyzing `phylink_create` in `drivers/net/phy/phylink.c`** Alright, time to crack open `phylink_create` and see what's what. I know this is a core function for establishing the connection between network interfaces and PHY devices, so I need to understand its fundamental purpose and how it fits into the broader networking stack. I'm expecting this function to handle the initial setup of a PHY link object, which, at the very least, would involve allocating memory, populating data structures with essential information (like the relevant MDIO bus and PHY address), and potentially performing some initial configuration or initialization steps. I'll need to pay close attention to the arguments it takes – things like the device struct, phy_device struct and any configuration parameters – as those will give me clues about its inputs and how the function is used by the calling code. I'll also be watching for any locking mechanisms it employs. Synchronization is critical in this type of driver code, and I'd expect to find some mutexes or spinlocks to ensure thread-safety. I'll be looking for any hints about callbacks or hooks that are established as part of the PHY link setup so that I can figure out how the device interacts with the network stack. I'm ready to dig in and see how the driver configures and manages these interactions. |
| 52/3 | 2026/10/09 22:02 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 2250,
"LineCount": 50
}Results: {
"Contents": "2250:\t\t\t\t const struct fwnode_handle *fwnode,\n2251:\t\t\t\t phy_interface_t iface,\n2252:\t\t\t\t const struct phylink_mac_ops *mac_ops)\n2253:\t{\n2254:\t\tstruct phylink_pcs *tmp, *pcs;\n2255:\t\tstruct phylink *pl;\n2256:\t\tint ret;\n2257:\t\n2258:\t\t/*\n2259:\t\t * Make sure either PCS internal validation or .mac_select_pcs\n2260:\t\t * is used. Return error if both are defined.\n2261:\t\t */\n2262:\t\tif (config-\u003enum_possible_pcs \u0026\u0026 mac_ops-\u003emac_select_pcs) {\n2263:\t\t\tdev_err(config-\u003edev,\n2264:\t\t\t\t\"phylink: error: either phylink_config .num_possible_pcs or .mac_select_pcs must be used\\n\");\n2265:\t\t\treturn ERR_PTR(-EINVAL);\n2266:\t\t}\n2267:\t\n2268:\t\t/* Validate the supplied configuration */\n2269:\t\tif (phy_interface_empty(config-\u003esupported_interfaces)) {\n2270:\t\t\tdev_err(config-\u003edev,\n2271:\t\t\t\t\"phylink: error: empty supported_interfaces\\n\");\n2272:\t\t\treturn ERR_PTR(-EINVAL);\n2273:\t\t}\n2274:\t\n2275:\t\tpl = kzalloc_obj(*pl);\n2276:\t\tif (!pl)\n2277:\t\t\treturn ERR_PTR(-ENOMEM);\n2278:\t\n2279:\t\tmutex_init(\u0026pl-\u003ephydev_mutex);\n2280:\t\tmutex_init(\u0026pl-\u003estate_mutex);\n2281:\t\tINIT_WORK(\u0026pl-\u003eresolve, phylink_resolve);\n2282:\t\tINIT_LIST_HEAD(\u0026pl-\u003epcs_list);\n2283:\t\n2284:\t\tpl-\u003econfig = config;\n2285:\t\tpl-\u003efwnode = fwnode_handle_get((struct fwnode_handle *)fwnode);\n2286:\t\tif (config-\u003etype == PHYLINK_NETDEV) {\n2287:\t\t\tpl-\u003enetdev = to_net_dev(config-\u003edev);\n2288:\t\t\tnetif_carrier_off(pl-\u003enetdev);\n2289:\t\t} else if (config-\u003etype == PHYLINK_DEV) {\n2290:\t\t\tpl-\u003edev = config-\u003edev;\n2291:\t\t} else {\n2292:\t\t\tret = -EINVAL;\n2293:\t\t\tgoto free_pl;\n2294:\t\t}\n2295:\t\n2296:\t\tpl-\u003emac_supports_eee_ops = phylink_mac_implements_lpi(mac_ops);\n2297:\t\tpl-\u003emac_supports_eee = pl-\u003emac_supports_eee_ops \u0026\u0026\n2298:\t\t\t\t pl-\u003econfig-\u003elpi_capabilities \u0026\u0026\n2299:\t\t\t\t !phy_interface_empty(pl-\u003econfig-\u003elpi_interfaces);\n"
} |
| 53/3 | 2026/10/09 22:02 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 144929 output: 39 thoughts: 45 Thoughts: Here's my summary, as though I'm thinking through this myself: **Initial Assessment: Potential Memory Issue in Network PHY Linking** Okay, so the code flags `pl = kzalloc_obj(*pl);`. That immediately screams "zero-allocated!" to me. This needs a deeper dive. My initial gut feeling is that a zero-allocation, especially on a pointer like `pl`, often leads to a null pointer and potential access issues if the allocation fails or isn't handled correctly down the line. We need to confirm if this allocation is successful and handled correctly. My next step is to drill down to the source. Let's head over to `drivers/net/phy/phylink.c` and specifically examine lines 2315 through 2365. This range likely contains the definition or use of `kzalloc_obj`, the variable `pl`, and potentially the error handling or initialization logic associated with the newly allocated memory. I’ll be looking for where and how `pl` is used after this allocation. Is there a null-pointer check? Are the members being initialized appropriately? Are there potential race conditions in this segment of code if this object is used in a multithreaded environment? The context is the important thing here - I am looking for the usage and lifetime of this object, to see if the zero allocation is actually going to be a problem. This should illuminate the root cause, if there is one. |
| 54/3 | 2026/10/09 22:02 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 2315,
"LineCount": 55
}Results: {
"Contents": "2315:\t\tpl-\u003elink_config.duplex = DUPLEX_UNKNOWN;\n2316:\t\tpl-\u003epcs_state = PCS_STATE_DOWN;\n2317:\t\tpl-\u003emac_ops = mac_ops;\n2318:\t\t__set_bit(PHYLINK_DISABLE_STOPPED, \u0026pl-\u003ephylink_disable_state);\n2319:\t\ttimer_setup(\u0026pl-\u003elink_poll, phylink_fixed_poll, 0);\n2320:\t\n2321:\t\t/* First register notifier for hotplug PCS events */\n2322:\t\tif (!phy_interface_empty(config-\u003epcs_interfaces)) {\n2323:\t\t\tpl-\u003efwnode_pcs_nb.notifier_call = pcs_provider_notify;\n2324:\t\t\tregister_fwnode_pcs_notifier(\u0026pl-\u003efwnode_pcs_nb);\n2325:\t\t}\n2326:\t\n2327:\t\t/* Fill the PCS list with available PCS from phylink config */\n2328:\t\tret = phylink_fill_available_pcs(pl, config);\n2329:\t\tif (ret \u003c 0)\n2330:\t\t\tgoto unregister_pcs_notify;\n2331:\t\n2332:\t\tmutex_lock(\u0026pl-\u003estate_mutex);\n2333:\t\n2334:\t\tphy_interface_copy(pl-\u003esupported_interfaces,\n2335:\t\t\t\t pl-\u003econfig-\u003esupported_interfaces);\n2336:\t\n2337:\t\t/* Update supported interfaces */\n2338:\t\tlist_for_each_entry(pcs, \u0026pl-\u003epcs_list, list)\n2339:\t\t\tphy_interface_or(pl-\u003esupported_interfaces,\n2340:\t\t\t\t\t pl-\u003esupported_interfaces,\n2341:\t\t\t\t\t pcs-\u003esupported_interfaces);\n2342:\t\n2343:\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n2344:\t\n2345:\t\tlinkmode_fill(pl-\u003esupported);\n2346:\t\tlinkmode_copy(pl-\u003elink_config.advertising, pl-\u003esupported);\n2347:\t\tphylink_validate(pl, pl-\u003esupported, \u0026pl-\u003elink_config);\n2348:\t\n2349:\t\tret = phylink_parse_mode(pl, fwnode);\n2350:\t\tif (ret \u003c 0)\n2351:\t\t\tgoto unregister_pcs_notify;\n2352:\t\n2353:\t\tif (pl-\u003ecfg_link_an_mode == MLO_AN_FIXED) {\n2354:\t\t\tret = phylink_parse_fixedlink(pl, fwnode);\n2355:\t\t\tif (ret \u003c 0)\n2356:\t\t\t\tgoto release_link_gpio;\n2357:\t\t}\n2358:\t\n2359:\t\tpl-\u003ereq_link_an_mode = pl-\u003ecfg_link_an_mode;\n2360:\t\n2361:\t\tret = phylink_register_sfp(pl, fwnode);\n2362:\t\tif (ret \u003c 0)\n2363:\t\t\tgoto release_link_gpio;\n2364:\t\n2365:\t\treturn pl;\n2366:\t\n2367:\trelease_link_gpio:\n2368:\t\tif (pl-\u003elink_gpio)\n2369:\t\t\tgpiod_put(pl-\u003elink_gpio);\n"
} |
| 55/3 | 2026/10/09 22:02 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 146199 output: 42 thoughts: 2690 Thoughts: **Analyzing Phylink and PCS State Management** Okay, let's break down this code and piece together the key aspects of phylink and PCS interaction, especially focusing on how link states are handled and how configuration data flows. First, I see `phylink_fill_available_pcs`. This function looks critical. It's responsible for populating a list of available PCS instances. The use of `kzalloc_objs` is important – it ensures the memory for `pcss` is zeroed, which might be important for initialization or avoiding garbage data. The `mutex_lock` around the PCS filling suggests it needs to be synchronized, likely to handle notifications or race conditions around PCS state changes. The `config->fill_available_pcs` function pointer is the workhorse here – it’s a callback that's *expected* to populate this list, and I need to investigate the implementer's behavior. An error here is fatal. Next, the `fwnode_*` functions are all about parsing Device Tree (or Flattened Device Tree) information related to PCS devices. `fwnode_parse_pcsspec` is the cornerstone. It seems to handle both string-based lookups (`pcs-names`) and reference-based lookups (`pcs-handle`), meaning it can resolve PCS instances based on names or direct references. The critical point is that these functions return a *reference* (`struct fwnode_reference_args`), which gets passed down. The functions with "provider" in the name probably handle a specific implementation or driver. The `airoha_*` functions are specific to the Airoha platform. I see `airoha_pcs_xlate` is called to translate an `fwnode_reference_args` (returned by the fwnode functions) into a `struct phylink_pcs`. The switch statement in `airoha_pcs_xlate` shows that the expected format of `pcs-handle` will change based on the underlying port type. This indicates that the device tree binding will vary based on port type. The `airoha_pcs_get_state` function is key to how the link state of each PCS is determined. It then calls device-specific versions, for example, `airoha_pcs_get_state_sgmii`, `airoha_pcs_get_state_hsgmii`, etc. Importantly, these specific functions *update* a `struct phylink_link_state` structure, which contains link status, speed, duplex, and AN completion information. `phylink_mii_c22_pcs_decode_state` is probably a helper function for decoding the bits from the PCS registers. And I can see that the individual implementations make a specific assessment of link status (linked or not, based on the bit values). Finally, the `airoha_ethtool_*` functions delegate to `phylink_ethtool_*`, so these are likely just wrappers for standard phylink ethtool functionality. These likely pull the link settings from the `phylink` and, through phylink, ultimately back to the PCS and PHY state. |
| 56/3 | 2026/10/09 22:03 | tool | grepper |
0mArgs:{
"Expression": "phylink_ethtool_ksettings_get",
"PathPrefixes": [
"drivers/net/phy/phylink.c"
]
}Results: {
"Output": "drivers/net/phy/phylink.c=3374=static void phylink_get_ksettings(const struct phylink_link_state *state,\n--\ndrivers/net/phy/phylink.c-3388-/**\ndrivers/net/phy/phylink.c:3389: * phylink_ethtool_ksettings_get() - get the current link settings\ndrivers/net/phy/phylink.c-3390- * @pl: a pointer to a \u0026struct phylink returned from phylink_create()\n--\ndrivers/net/phy/phylink.c-3396- */\ndrivers/net/phy/phylink.c:3397:int phylink_ethtool_ksettings_get(struct phylink *pl,\ndrivers/net/phy/phylink.c-3398-\t\t\t\t struct ethtool_link_ksettings *kset)\n--\ndrivers/net/phy/phylink.c-3439-}\ndrivers/net/phy/phylink.c:3440:EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_get);\ndrivers/net/phy/phylink.c-3441-\n"
} |
| 57/3 | 2026/10/09 22:03 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 149891 output: 39 thoughts: 17 Thoughts: Okay, here's my attempt at summarizing the thought process, speaking as though *I* were the one having them, assuming I'm an expert and this is my internal monologue: **Diving into `phylink_ethtool_ksettings_get`** Alright, let's get into this `phylink_ethtool_ksettings_get` function. My initial thought is, this is probably where the kernel interacts with the PHY (Physical Layer) settings through ethtool, and likely focuses on *getting* those settings. I'm assuming it's a critical component for fetching the current negotiated link parameters. So, things like speed, duplex, autonegotiation state, and potentially more nuanced details like flow control configurations would be on my radar. I need to quickly assess how it interfaces with the Phylink core, specifically how it takes the PhyLink structure, I'd bet this is the central point of my investigation. Are we dealing with cached values here, or is it a direct read from the PHY registers? If it's cached, I'll want to trace how that cache is populated and invalidated – performance implications are always in the back of my mind. Given that this is `get`, error handling is the first thing I would check: how gracefully it handles PHYs that aren't available, or when it encounters communication errors with the PHY. Proper error reporting to userspace is key. I'll need to know what happens in each failure situation. I'll pay close attention to the data structures involved, the specific ethtool commands it's responding to, and the data it returns. If this deals with PHY-specific settings (or potentially is abstracted to work with different PHY types), I'll need to see how it manages that. I will also be curious if any of the assumptions here are tied to certain PHY technologies or particular hardware. My primary focus will be understanding the overall logic flow and how it fits into the broader network stack, especially in relation to the relevant phylink core functions. Let's see what’s going on inside. |
| 58/3 | 2026/10/09 22:03 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 3397,
"LineCount": 45
}Results: {
"Contents": "3397:\tint phylink_ethtool_ksettings_get(struct phylink *pl,\n3398:\t\t\t\t\t struct ethtool_link_ksettings *kset)\n3399:\t{\n3400:\t\tstruct phylink_link_state link_state;\n3401:\t\n3402:\t\tASSERT_RTNL();\n3403:\t\n3404:\t\tif (pl-\u003ephydev)\n3405:\t\t\tphy_ethtool_ksettings_get(pl-\u003ephydev, kset);\n3406:\t\telse\n3407:\t\t\tkset-\u003ebase.port = pl-\u003elink_port;\n3408:\t\n3409:\t\tlinkmode_copy(kset-\u003elink_modes.supported, pl-\u003esupported);\n3410:\t\n3411:\t\tswitch (pl-\u003eact_link_an_mode) {\n3412:\t\tcase MLO_AN_FIXED:\n3413:\t\t\t/* We are using fixed settings. Report these as the\n3414:\t\t\t * current link settings - and note that these also\n3415:\t\t\t * represent the supported speeds/duplex/pause modes.\n3416:\t\t\t */\n3417:\t\t\tphylink_get_fixed_state(pl, \u0026link_state);\n3418:\t\t\tphylink_get_ksettings(\u0026link_state, kset);\n3419:\t\t\tbreak;\n3420:\t\n3421:\t\tcase MLO_AN_INBAND:\n3422:\t\t\t/* If there is a phy attached, then use the reported\n3423:\t\t\t * settings from the phy with no modification.\n3424:\t\t\t */\n3425:\t\t\tif (pl-\u003ephydev)\n3426:\t\t\t\tbreak;\n3427:\t\n3428:\t\t\tphylink_mac_pcs_get_state(pl, \u0026link_state);\n3429:\t\n3430:\t\t\t/* The MAC is reporting the link results from its own PCS\n3431:\t\t\t * layer via in-band status. Report these as the current\n3432:\t\t\t * link settings.\n3433:\t\t\t */\n3434:\t\t\tphylink_get_ksettings(\u0026link_state, kset);\n3435:\t\t\tbreak;\n3436:\t\t}\n3437:\t\n3438:\t\treturn 0;\n3439:\t}\n3440:\tEXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_get);\n3441:\t\n"
} |
| 59/3 | 2026/10/09 22:03 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 151041 output: 33 thoughts: 66 Thoughts: Okay, here's my take on those thoughts, framed as my own: **Verifying Ehtool's kset Initialization** Right, so I'm digging into ethtool and I've got this nagging feeling about how `kset` is handled during initialization. The core seems to be initializing `kset` before calling `get_link_ksettings`, which is good practice. To confirm, I want to trace the path and verify this initialization. I'm thinking I should jump into either `net/ethtool/ioctl.c` or `net/ethtool/linkstate.c`. I need to ensure that `kset` is properly zeroed out (likely with a `memset`) *before* it's passed or used in that `get_link_ksettings` function. I just want to be absolutely sure this initialization is happening correctly to prevent potential garbage data from creeping in and causing unexpected behavior later on. It's a fundamental thing, but worth the quick check. |
| 60/3 | 2026/10/09 22:03 | tool | grepper |
0mArgs:{
"Expression": "memset.*link_ksettings",
"PathPrefixes": [
"net/ethtool/"
]
}Results: {
"Output": "net/ethtool/common.c=590=convert_legacy_settings_to_link_ksettings(\n--\nnet/ethtool/common.c-595-\nnet/ethtool/common.c:596:\tmemset(link_ksettings, 0, sizeof(*link_ksettings));\nnet/ethtool/common.c-597-\n--\nnet/ethtool/ioctl.c=440=int netif_get_link_ksettings(struct net_device *dev,\n--\nnet/ethtool/ioctl.c-450-\nnet/ethtool/ioctl.c:451:\tmemset(link_ksettings, 0, sizeof(*link_ksettings));\nnet/ethtool/ioctl.c-452-\treturn dev-\u003eethtool_ops-\u003eget_link_ksettings(dev, link_ksettings);\n--\nnet/ethtool/ioctl.c=542=static int ethtool_get_link_ksettings(struct net_device *dev,\n--\nnet/ethtool/ioctl.c-559-\t\t/* wrong link mode nbits requested */\nnet/ethtool/ioctl.c:560:\t\tmemset(\u0026link_ksettings, 0, sizeof(link_ksettings));\nnet/ethtool/ioctl.c-561-\t\tlink_ksettings.base.cmd = ETHTOOL_GLINKSETTINGS;\n--\nnet/ethtool/ioctl.c-581-\nnet/ethtool/ioctl.c:582:\tmemset(\u0026link_ksettings, 0, sizeof(link_ksettings));\nnet/ethtool/ioctl.c-583-\terr = dev-\u003eethtool_ops-\u003eget_link_ksettings(dev, \u0026link_ksettings);\n--\nnet/ethtool/ioctl.c=673=static int ethtool_get_settings(struct net_device *dev, void __user *useraddr)\n--\nnet/ethtool/ioctl.c-685-\nnet/ethtool/ioctl.c:686:\tmemset(\u0026link_ksettings, 0, sizeof(link_ksettings));\nnet/ethtool/ioctl.c-687-\terr = dev-\u003eethtool_ops-\u003eget_link_ksettings(dev, \u0026link_ksettings);\n"
} |
| 61/3 | 2026/10/09 22:03 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 151936 output: 38 thoughts: 1227 Thoughts: **Code Review: Userspace Interactions and Uninitialized Memory** Okay, let's break this down. My initial concern was whether this patch introduces any new paths where we copy data to userspace, or, even worse, read uninitialized memory. Starting with `ethtool`, I see that it zeroes `link_ksettings` before calling `.get_link_ksettings`. That's good; it means we should be safe. And, the `phylink_ethtool_ksettings_get` is standard kernel code, and the `airoha_eth` code just calls it, so that's not a point of concern. Now, I need to methodically check the rest of the patch. I'm going through the files, methodically looking for any instances where we're copying data *to* userspace. The devicetree docs (`airoha,pcs.yaml`), other documentation files (`pcs.rst`, `sfp-phylink.rst`, `MAINTAINERS`) aren't relevant. * `drivers/net/pcs/pcs.c`: This one's important. I'm looking at functions that might handle user input or output. None of these functions: `register_fwnode_pcs_notifier`, `unregister_fwnode_pcs_notifier`, `fwnode_pcs_simple_xlate`, `fwnode_pcs_add_provider`, `fwnode_pcs_del_provider`, `devm_fwnode_pcs_add_provider`, `fwnode_pcs_get`, `fwnode_pcs_get_from_provider`, `fwnode_pcs_matches_provider`, `fwnode_phylink_pcs_count`, `fwnode_phylink_pcs_parse` copy anything to userspace. * `drivers/net/pcs/airoha/pcs-airoha-common.c`: This is about hardware register manipulation via regmap and PCS callbacks. Specifically looking at: `airoha_pcs_inband_caps`, `airoha_pcs_pre_config`, `airoha_pcs_post_config`, `airoha_pcs_get_state`, `airoha_pcs_config`, `airoha_pcs_an_restart`, `airoha_pcs_link_up`, `airoha_pcs_link_down`. And the platform driver probe and init functions. None of these deal with userspace buffers or copy data to userspace. * `drivers/net/pcs/airoha/pcs-an7581.c`: Register fields allocation and PHY bringup/calibration routines. Again, no userspace interaction here. * `drivers/net/phy/phylink.c`: This one's the most critical because it's where the core changes are. I see several additions: `pl->fwnode`, `pl->pcs_list`, `fwnode_pcs_nb` notifier, `pl->supported_interfaces`, `phylink_fill_available_pcs`, `pcs_provider_notify`, `phylink_add_pcs`, `phylink_del_pcs`. The updates to `phylink_validate_mac_and_pcs` and `phylink_major_config` to use `pl->pcs_list` are good but I need to look closely at those functions' read/write accesses to see how they're used. Also, `phylink_pcs_link_down(pl->pcs)` and interface validation. After carefully looking at these and the other changes, I can confirm there are no new `copy_to_user`, `put_user`, netlink skb attributes, ioctl outputs, socket options, or BPF buffers added or modified. Now, the potential for uninitialized memory reads. This is where I need to be extra careful, looking at every memory allocation in the context of `phylink`, `airoha_eth`, `pcs`, and `airoha-pcs`. 1. `drivers/net/pcs/pcs.c`: `kzalloc_obj`, and `devres_alloc` look safe since they zero the allocated memory. 2. `drivers/net/pcs/airoha/pcs-airoha-common.c`: `devm_kzalloc` and `devm_kcalloc` both zero memory. 3. `drivers/net/pcs/airoha/pcs-an7581.c`: More `devm_kcalloc` calls – all good. 4. `drivers/net/phy/phylink.c`: `kzalloc_objs`, and `kzalloc_obj` are also zeroing memory. 5. In `pcs_provider_notify`: The variables are |
| 62/3 | 2026/10/09 22:03 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 540,
"LineCount": 40
}Results: {
"Contents": " 540:\t}\n 541:\t\n 542:\tstatic int phylink_validate_mac_and_pcs(struct phylink *pl,\n 543:\t\t\t\t\t\tunsigned long *supported,\n 544:\t\t\t\t\t\tstruct phylink_link_state *state)\n 545:\t{\n 546:\t\tstruct phylink_pcs *pcs = NULL;\n 547:\t\tunsigned long capabilities;\n 548:\t\tint ret;\n 549:\t\n 550:\t\tmutex_lock(\u0026pl-\u003estate_mutex);\n 551:\t\n 552:\t\t/* Get the PCS for this interface mode */\n 553:\t\tif (pl-\u003emac_ops-\u003emac_select_pcs) {\n 554:\t\t\tpcs = pl-\u003emac_ops-\u003emac_select_pcs(pl-\u003econfig, state-\u003einterface);\n 555:\t\t\tif (IS_ERR(pcs)) {\n 556:\t\t\t\tmutex_unlock(\u0026pl-\u003estate_mutex);\n 557:\t\t\t\treturn PTR_ERR(pcs);\n 558:\t\t\t}\n 559:\t\t/*\n 560:\t\t * Find a PCS in available PCS list for the requested interface.\n 561:\t\t *\n 562:\t\t * Skip searching if the MAC doesn't require a dedicated PCS for\n 563:\t\t * the requested interface.\n 564:\t\t */\n 565:\t\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\n 566:\t\t\tstruct phylink_pcs *tmp;\n 567:\t\n 568:\t\t\tlist_for_each_entry(tmp, \u0026pl-\u003epcs_list, list) {\n 569:\t\t\t\tif (!phylink_validate_pcs_interface(tmp, state-\u003einterface)) {\n 570:\t\t\t\t\tpcs = tmp;\n 571:\t\t\t\t\tbreak;\n 572:\t\t\t\t}\n 573:\t\t\t}\n 574:\t\t}\n 575:\t\n 576:\t\tif (pcs) {\n 577:\t\t\t/* The PCS, if present, must be setup before phylink_create()\n 578:\t\t\t * has been called. If the ops is not initialised, print an\n 579:\t\t\t * error and backtrace rather than oopsing the kernel.\n"
} |
| 63/3 | 2026/10/09 22:03 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 154814 output: 39 thoughts: 27 Thoughts: Here's my analysis of the provided snippet: **Initialization and Configuration Check** Okay, so I see that `pcs` is being initialized to `NULL` on line 546. This is a pretty standard initialization practice in C, but it's important to keep track of. Now, given that initialization, let's turn our attention to `phylink_major_config`. I need to understand what state this structure represents and how its value interacts with `pcs` down the line. We need to be absolutely certain we are handling edge cases where `phylink_major_config` may be unexpectedly initialized. The next few lines of code *must* provide relevant context. |
| 64/3 | 2026/10/09 22:03 | tool | read-file |
0mArgs:{
"File": "drivers/net/phy/phylink.c",
"FirstLine": 1310,
"LineCount": 55
}Results: {
"Contents": "1310:\t}\n1311:\t\n1312:\tstatic void phylink_major_config(struct phylink *pl, bool restart,\n1313:\t\t\t\t\t const struct phylink_link_state *state)\n1314:\t{\n1315:\t\tstruct phylink_pcs *pcs = NULL;\n1316:\t\tbool pcs_changed = false;\n1317:\t\tunsigned int rate_kbd;\n1318:\t\tint err;\n1319:\t\n1320:\t\tphylink_dbg(pl, \"major config, requested %s/%s\\n\",\n1321:\t\t\t phylink_an_mode_str(pl-\u003ereq_link_an_mode),\n1322:\t\t\t phy_modes(state-\u003einterface));\n1323:\t\n1324:\t\tpl-\u003emajor_config_failed = false;\n1325:\t\n1326:\t\tif (pl-\u003emac_ops-\u003emac_select_pcs) {\n1327:\t\t\tpcs = pl-\u003emac_ops-\u003emac_select_pcs(pl-\u003econfig, state-\u003einterface);\n1328:\t\t\tif (IS_ERR(pcs)) {\n1329:\t\t\t\tphylink_err(pl,\n1330:\t\t\t\t\t \"mac_select_pcs unexpectedly failed: %pe\\n\",\n1331:\t\t\t\t\t pcs);\n1332:\t\n1333:\t\t\t\tpl-\u003emajor_config_failed = true;\n1334:\t\t\t\treturn;\n1335:\t\t\t}\n1336:\t\t/* Find a PCS in available PCS list for the requested interface.\n1337:\t\t * This doesn't overwrite the previous .mac_select_pcs as either\n1338:\t\t * .mac_select_pcs or PCS list implementation are permitted.\n1339:\t\t *\n1340:\t\t * Skip searching if the MAC doesn't require a dedicated PCS for\n1341:\t\t * the requested interface.\n1342:\t\t */\n1343:\t\t} else if (test_bit(state-\u003einterface, pl-\u003econfig-\u003epcs_interfaces)) {\n1344:\t\t\tstruct phylink_pcs *tmp;\n1345:\t\n1346:\t\t\tlist_for_each_entry(tmp, \u0026pl-\u003epcs_list, list) {\n1347:\t\t\t\tif (!phylink_validate_pcs_interface(tmp,\n1348:\t\t\t\t\t\t\t\t state-\u003einterface)) {\n1349:\t\t\t\t\tpcs = tmp;\n1350:\t\t\t\t\tbreak;\n1351:\t\t\t\t}\n1352:\t\t\t}\n1353:\t\n1354:\t\t\tif (!pcs) {\n1355:\t\t\t\tphylink_err(pl,\n1356:\t\t\t\t\t \"couldn't find a PCS for %s\\n\",\n1357:\t\t\t\t\t phy_modes(state-\u003einterface));\n1358:\t\n1359:\t\t\t\tpl-\u003emajor_config_failed = true;\n1360:\t\t\t\treturn;\n1361:\t\t\t}\n1362:\t\t}\n1363:\t\n1364:\t\tpcs_changed = pl-\u003epcs != pcs;\n"
} |
| 65/3 | 2026/10/09 22:03 | llm | kmsan-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 155821 output: 463 thoughts: 2457 Thoughts: **KMSAN Assessment: No Uninitialized Memory Risks Detected** As I examine this patch, my primary concern is to identify any potential risks stemming from uninitialized memory usage. I've meticulously reviewed the code, focusing on the allocation and initialization of various structures and variables within the phylink, PCS driver subsystem, and network device drivers. My analysis reveals the following key points: 1. **Memory Allocation and Initialization:** Every dynamically allocated memory region – including those for `struct phylink`, `struct fwnode_pcs_provider`, `struct airoha_pcs_priv`, arrays for ports and regmap fields, and the PCS pointer array within phylink – utilizes `kzalloc`, `devm_kzalloc`, `kcalloc`, or related functions. These functions ensure that the allocated memory is fully zero-initialized before any usage. Stack variables are explicitly initialized upon declaration, or properly initialized prior to reading the data. 2. **Data Transfer to Userspace:** I found no new instances of `copy_to_user`, `put_user`, netlink attributes, socket options, or BPF buffers being introduced or modified by this patch. The ethtool settings are handled using the existing `phylink_ethtool_ksettings_get`, which interacts with a zeroed `ethtool_link_ksettings` structure provided by the ethtool core, effectively eliminating the risk of uninitialized memory exposure to userspace. 3. **Potential Bugs and Detection:** The patch introduces no uninitialized memory risks. Instead, the changes focus on integrating firmware node PCS framework, adding an Airoha PCS driver, and supporting multi-PCS dynamic lookup and notifications. Potential bugs associated with these changes are not related to uninitialized memory. They are primarily concerned with concurrency and locking, which are addressed by LOCKDEP, reference counting/lifecycles, and use-after-free/pointer bugs, which KASAN helps detect. In light of these findings, I am confident that this patch does not introduce or expose any uninitialized memory risks. This leads me to conclude that setting `NeedsKMSAN=false` is appropriate. |
| 66/3 | 2026/10/09 22:04 | tool | set-results |
0mArgs:{
"KMSANReasoning": "The patch series introduces a new firmware-node (fwnode) PCS subsystem framework, adds support for Airoha PCS hardware (common and AN7581-specific drivers), and updates the phylink core and the Airoha Ethernet driver to support dynamic PCS discovery and hotplug notifications.\n\nAn audit of the changes shows no uninitialized memory risks:\n1. All newly allocated kernel heap objects and arrays are zero-initialized at allocation time:\n - `struct fwnode_pcs_provider` uses `kzalloc_obj`.\n - Device resources use `devres_alloc` and `devm_kzalloc` / `devm_kcalloc` (e.g., `struct airoha_pcs_priv`, port arrays, regmap field arrays).\n - Temporary arrays such as `pcss` in `phylink_fill_available_pcs()` are allocated via `kzalloc_objs`.\n - `struct phylink` is allocated with `kzalloc_obj`.\n2. All local stack variables across new and modified functions (such as register read values, status flags, and temporary pointers) are explicitly initialized at declaration or safely populated before read.\n3. No data is copied to user space via `copy_to_user`, `put_user`, Netlink attributes, ioctls, or socket buffers. The addition of `.get_link_ksettings` in `airoha_eth.c` delegates to `phylink_ethtool_ksettings_get()`, which operates on an `ethtool_link_ksettings` structure already zeroed by the ethtool core.\n4. Any potential risks introduced by the patch involve list operations, reference counting (`fwnode_handle_get`/`put`), locking under `state_mutex`/`rtnl_lock`, or lifecycle management. These classes of bugs are already covered by standard KASAN, LOCKDEP, and general kernel debuggers.\n\nTherefore, there is no risk of uninitialized memory reads or information leaks that would justify a dedicated KMSAN session.",
"NeedsKMSAN": false
}Results: {
"KMSANReasoning": "The patch series introduces a new firmware-node (fwnode) PCS subsystem framework, adds support for Airoha PCS hardware (common and AN7581-specific drivers), and updates the phylink core and the Airoha Ethernet driver to support dynamic PCS discovery and hotplug notifications.\n\nAn audit of the changes shows no uninitialized memory risks:\n1. All newly allocated kernel heap objects and arrays are zero-initialized at allocation time:\n - `struct fwnode_pcs_provider` uses `kzalloc_obj`.\n - Device resources use `devres_alloc` and `devm_kzalloc` / `devm_kcalloc` (e.g., `struct airoha_pcs_priv`, port arrays, regmap field arrays).\n - Temporary arrays such as `pcss` in `phylink_fill_available_pcs()` are allocated via `kzalloc_objs`.\n - `struct phylink` is allocated with `kzalloc_obj`.\n2. All local stack variables across new and modified functions (such as register read values, status flags, and temporary pointers) are explicitly initialized at declaration or safely populated before read.\n3. No data is copied to user space via `copy_to_user`, `put_user`, Netlink attributes, ioctls, or socket buffers. The addition of `.get_link_ksettings` in `airoha_eth.c` delegates to `phylink_ethtool_ksettings_get()`, which operates on an `ethtool_link_ksettings` structure already zeroed by the ethtool core.\n4. Any potential risks introduced by the patch involve list operations, reference counting (`fwnode_handle_get`/`put`), locking under `state_mutex`/`rtnl_lock`, or lifecycle management. These classes of bugs are already covered by standard KASAN, LOCKDEP, and general kernel debuggers.\n\nTherefore, there is no risk of uninitialized memory reads or information leaks that would justify a dedicated KMSAN session.",
"NeedsKMSAN": false
} |
| Total Calls | Total Tokens | Avg Tokens | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|
| Total Calls | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|