AI Trajectory


Trajectory: (Expand/Collapse All)
Seq Timestamp Type Name Duration
0/0 2026/07/06 11:06 flow patch-triage
0m Args: 
null

Results: 
{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch primarily adds device tree bindings and files for Alientek CLRV1126F SoM based boards. The only executable code change is a trivial clock initialization (devm_clk_get_optional_enabled) in the hardware-specific motorcomm PHY driver, which is not meaningfully fuzzable in a virtualized environment.",
  "WorthFuzzing": false
}
1/1 2026/07/06 11:06 action read-patch-diff
0m Args: 
null

Results: 
{
  "PatchDiff": "commit 7fbf1d98011dacbdf701f66d0cbb0668bc9b83c2\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Mon Jul 6 11:06:43 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml\nindex 1a9dde18626d00..9058f2a461d577 100644\n--- a/Documentation/devicetree/bindings/arm/rockchip.yaml\n+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml\n@@ -162,6 +162,13 @@ properties:\n           - const: coolpi,pi-4b\n           - const: rockchip,rk3588s\n \n+      - description: Alientek CLRV1126F SoM based boards\n+        items:\n+          - enum:\n+              - alientek,dlrv1126\n+          - const: alientek,clrv1126f\n+          - const: rockchip,rv1126\n+\n       - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards\n         items:\n           - const: edgeble,neural-compute-module-2-io   # Edgeble Neural Compute Module 2 IO Board\ndiff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml\nindex 396044f368e7cf..914d5a8fd628de 100644\n--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml\n+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml\n@@ -88,6 +88,8 @@ patternProperties:\n     description: ALFA Network Inc.\n   \"^algoltek,.*\":\n     description: AlgolTek, Inc.\n+  \"^alientek,.*\":\n+    description: Guangzhou Xingyi Intelligent Technology Co., Ltd.\n   \"^allegro,.*\":\n     description: Allegro DVT\n   \"^allegromicro,.*\":\ndiff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile\nindex d0154fd7ff24f9..e9f9e0ac3bfd48 100644\n--- a/arch/arm/boot/dts/rockchip/Makefile\n+++ b/arch/arm/boot/dts/rockchip/Makefile\n@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \\\n \trv1108-evb.dtb \\\n \trv1109-relfor-saib.dtb \\\n \trv1109-sonoff-ihost.dtb \\\n+\trv1126-alientek-dlrv1126.dtb \\\n \trv1126-edgeble-neu2-io.dtb \\\n \trv1126-sonoff-ihost.dtb \\\n \trk3036-evb.dtb \\\ndiff --git a/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi b/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi\nnew file mode 100644\nindex 00000000000000..9bee424b179793\n--- /dev/null\n+++ b/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi\n@@ -0,0 +1,277 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (c) 2026 Yanan He \u003cgrumpycat921013@gmail.com\u003e\n+ */\n+\n+#include \"rv1126.dtsi\"\n+\n+/ {\n+\tcompatible = \"alientek,clrv1126f\", \"rockchip,rv1126\";\n+\n+\taliases {\n+\t\tmmc0 = \u0026emmc;\n+\t};\n+};\n+\n+\u0026cpu0 {\n+\tcpu-supply = \u003c\u0026vdd_arm\u003e;\n+};\n+\n+\u0026cpu1 {\n+\tcpu-supply = \u003c\u0026vdd_arm\u003e;\n+};\n+\n+\u0026cpu2 {\n+\tcpu-supply = \u003c\u0026vdd_arm\u003e;\n+};\n+\n+\u0026cpu3 {\n+\tcpu-supply = \u003c\u0026vdd_arm\u003e;\n+};\n+\n+\u0026emmc {\n+\tbus-width = \u003c8\u003e;\n+\tcap-mmc-highspeed;\n+\tmmc-hs200-1_8v;\n+\tnon-removable;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026emmc_bus8 \u0026emmc_cmd \u0026emmc_clk \u0026emmc_rstnout\u003e;\n+\trockchip,default-sample-phase = \u003c90\u003e;\n+\tvmmc-supply = \u003c\u0026vcc_3v3\u003e;\n+\tvqmmc-supply = \u003c\u0026vcc_1v8\u003e;\n+\tstatus = \"okay\";\n+};\n+\n+\u0026i2c0 {\n+\tclock-frequency = \u003c400000\u003e;\n+\tstatus = \"okay\";\n+\n+\trk809: pmic@20 {\n+\t\tcompatible = \"rockchip,rk809\";\n+\t\treg = \u003c0x20\u003e;\n+\t\tinterrupt-parent = \u003c\u0026gpio0\u003e;\n+\t\tinterrupts = \u003cRK_PB1 IRQ_TYPE_LEVEL_LOW\u003e;\n+\t\t#clock-cells = \u003c1\u003e;\n+\t\t#sound-dai-cells = \u003c0\u003e;\n+\t\tclock-output-names = \"rk808-clkout1\", \"rk808-clkout2\";\n+\t\tclock-names = \"mclk\";\n+\t\tclocks = \u003c\u0026cru MCLK_I2S0_TX_OUT2IO\u003e;\n+\t\tassigned-clocks = \u003c\u0026cru MCLK_I2S0_TX_OUT2IO\u003e;\n+\t\tassigned-clock-parents = \u003c\u0026cru MCLK_I2S0_TX\u003e;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = \u003c\u0026pmic_int_l\u003e;\n+\t\trockchip,system-power-controller;\n+\t\twakeup-source;\n+\n+\t\tvcc1-supply = \u003c\u0026vcc5v0_sys\u003e;\n+\t\tvcc2-supply = \u003c\u0026vcc5v0_sys\u003e;\n+\t\tvcc3-supply = \u003c\u0026vcc5v0_sys\u003e;\n+\t\tvcc4-supply = \u003c\u0026vcc5v0_sys\u003e;\n+\t\tvcc5-supply = \u003c\u0026vcc_buck5\u003e;\n+\t\tvcc6-supply = \u003c\u0026vcc_buck5\u003e;\n+\t\tvcc7-supply = \u003c\u0026vcc5v0_sys\u003e;\n+\t\tvcc8-supply = \u003c\u0026vcc3v3_sys\u003e;\n+\t\tvcc9-supply = \u003c\u0026vcc5v0_sys\u003e;\n+\n+\t\tregulators {\n+\t\t\tvdd_npu_vepu: DCDC_REG1 {\n+\t\t\t\tregulator-name = \"vdd_npu_vepu\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-initial-mode = \u003c0x2\u003e;\n+\t\t\t\tregulator-min-microvolt = \u003c650000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c950000\u003e;\n+\t\t\t\tregulator-ramp-delay = \u003c6001\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvdd_arm: DCDC_REG2 {\n+\t\t\t\tregulator-name = \"vdd_arm\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-initial-mode = \u003c0x2\u003e;\n+\t\t\t\tregulator-min-microvolt = \u003c725000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c1350000\u003e;\n+\t\t\t\tregulator-ramp-delay = \u003c6001\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc_ddr: DCDC_REG3 {\n+\t\t\t\tregulator-name = \"vcc_ddr\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-initial-mode = \u003c0x2\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc3v3_sys: DCDC_REG4 {\n+\t\t\t\tregulator-name = \"vcc3v3_sys\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-initial-mode = \u003c0x2\u003e;\n+\t\t\t\tregulator-min-microvolt = \u003c3300000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\tregulator-suspend-microvolt = \u003c3300000\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc_buck5: DCDC_REG5 {\n+\t\t\t\tregulator-name = \"vcc_buck5\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-min-microvolt = \u003c2200000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c2200000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\tregulator-suspend-microvolt = \u003c2200000\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc_0v8: LDO_REG1 {\n+\t\t\t\tregulator-name = \"vcc_0v8\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-min-microvolt = \u003c800000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c800000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc1v8_pmu: LDO_REG2 {\n+\t\t\t\tregulator-name = \"vcc1v8_pmu\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-min-microvolt = \u003c1800000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c1800000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\tregulator-suspend-microvolt = \u003c1800000\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvdd0v8_pmu: LDO_REG3 {\n+\t\t\t\tregulator-name = \"vcc0v8_pmu\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-min-microvolt = \u003c800000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c800000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\tregulator-suspend-microvolt = \u003c800000\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc_1v8: LDO_REG4 {\n+\t\t\t\tregulator-name = \"vcc_1v8\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-min-microvolt = \u003c1800000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c1800000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\tregulator-suspend-microvolt = \u003c1800000\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc_dovdd: LDO_REG5 {\n+\t\t\t\tregulator-name = \"vcc_dovdd\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-min-microvolt = \u003c1800000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c1800000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc_dvdd: LDO_REG6 {\n+\t\t\t\tregulator-name = \"vcc_dvdd\";\n+\t\t\t\tregulator-min-microvolt = \u003c1200000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c1200000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc_avdd: LDO_REG7 {\n+\t\t\t\tregulator-name = \"vcc_avdd\";\n+\t\t\t\tregulator-min-microvolt = \u003c2800000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c2800000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvccio_sd: LDO_REG8 {\n+\t\t\t\tregulator-name = \"vccio_sd\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-min-microvolt = \u003c1800000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc3v3_sd: LDO_REG9 {\n+\t\t\t\tregulator-name = \"vcc3v3_sd\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-min-microvolt = \u003c3300000\u003e;\n+\t\t\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\t\t\t\tregulator-state-mem {\n+\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvcc_5v0: SWITCH_REG1 {\n+\t\t\t\tregulator-name = \"vcc_5v0\";\n+\t\t\t};\n+\n+\t\t\tvcc_3v3: SWITCH_REG2 {\n+\t\t\t\tregulator-name = \"vcc_3v3\";\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+\u0026pinctrl {\n+\tpmic {\n+\t\tpmic_int_l: pmic-int-l {\n+\t\t\trockchip,pins = \u003c0 RK_PB1 RK_FUNC_GPIO \u0026pcfg_pull_up\u003e;\n+\t\t};\n+\t};\n+};\n+\n+\u0026pmu_io_domains {\n+\tpmuio0-supply = \u003c\u0026vcc3v3_sys\u003e;\n+\tpmuio1-supply = \u003c\u0026vcc3v3_sys\u003e;\n+\tvccio1-supply = \u003c\u0026vcc_1v8\u003e;\n+\tvccio2-supply = \u003c\u0026vccio_sd\u003e;\n+\tvccio3-supply = \u003c\u0026vcc_1v8\u003e;\n+\tvccio4-supply = \u003c\u0026vcc_3v3\u003e;\n+\tvccio5-supply = \u003c\u0026vcc_3v3\u003e;\n+\tvccio6-supply = \u003c\u0026vcc_3v3\u003e;\n+\tvccio7-supply = \u003c\u0026vcc_1v8\u003e;\n+\tstatus = \"okay\";\n+};\n+\n+\u0026saradc {\n+\tvref-supply = \u003c\u0026vcc_1v8\u003e;\n+\tstatus = \"okay\";\n+};\n+\n+\u0026wdt {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts b/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts\nnew file mode 100644\nindex 00000000000000..33c6c74d08b916\n--- /dev/null\n+++ b/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts\n@@ -0,0 +1,256 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (c) 2026 Yanan He \u003cgrumpycat921013@gmail.com\u003e\n+ */\n+\n+/dts-v1/;\n+#include \u003cdt-bindings/input/input.h\u003e\n+#include \"rv1126-alientek-clrv1126f.dtsi\"\n+\n+/ {\n+\tmodel = \"Alientek ATK-DLRV1126\";\n+\tcompatible = \"alientek,dlrv1126\", \"alientek,clrv1126f\", \"rockchip,rv1126\";\n+\n+\taliases {\n+\t\tethernet0 = \u0026gmac;\n+\t\tmmc1 = \u0026sdio;\n+\t\tmmc2 = \u0026sdmmc;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial2:1500000n8\";\n+\t};\n+\n+\tadc-keys {\n+\t\tcompatible = \"adc-keys\";\n+\t\tio-channels = \u003c\u0026saradc 0\u003e;\n+\t\tio-channel-names = \"buttons\";\n+\t\tkeyup-threshold-microvolt = \u003c1800000\u003e;\n+\t\tpoll-interval = \u003c100\u003e;\n+\n+\t\tbutton-esc {\n+\t\t\tlabel = \"esc\";\n+\t\t\tlinux,code = \u003cKEY_ESC\u003e;\n+\t\t\tpress-threshold-microvolt = \u003c0\u003e;\n+\t\t};\n+\n+\t\tbutton-right {\n+\t\t\tlabel = \"right\";\n+\t\t\tlinux,code = \u003cKEY_RIGHT\u003e;\n+\t\t\tpress-threshold-microvolt = \u003c400781\u003e;\n+\t\t};\n+\n+\t\tbutton-left {\n+\t\t\tlabel = \"left\";\n+\t\t\tlinux,code = \u003cKEY_LEFT\u003e;\n+\t\t\tpress-threshold-microvolt = \u003c801562\u003e;\n+\t\t};\n+\n+\t\tbutton-menu {\n+\t\t\tlabel = \"menu\";\n+\t\t\tlinux,code = \u003cKEY_MENU\u003e;\n+\t\t\tpress-threshold-microvolt = \u003c1198828\u003e;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled-0 {\n+\t\t\tlabel = \"sys-led\";\n+\t\t\tgpios = \u003c\u0026gpio3 RK_PD4 GPIO_ACTIVE_HIGH\u003e;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\n+\t\tled-1 {\n+\t\t\tlabel = \"user-led\";\n+\t\t\tgpios = \u003c\u0026gpio3 RK_PD6 GPIO_ACTIVE_HIGH\u003e;\n+\t\t\tlinux,default-trigger = \"none\";\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\t};\n+\n+\tsound {\n+\t\tcompatible = \"simple-audio-card\";\n+\t\tsimple-audio-card,format = \"i2s\";\n+\t\tsimple-audio-card,name = \"Analog RK809\";\n+\t\tsimple-audio-card,mclk-fs = \u003c256\u003e;\n+\t\tsimple-audio-card,widgets =\n+\t\t\t\"Speaker\", \"Speaker\",\n+\t\t\t\"Headphone\", \"Headphones\",\n+\t\t\t\"Microphone\", \"Mic Jack\";\n+\t\tsimple-audio-card,routing =\n+\t\t\t\"Speaker\", \"SPKO\",\n+\t\t\t\"Headphones\", \"HPOL\",\n+\t\t\t\"Headphones\", \"HPOR\",\n+\t\t\t\"MICL\", \"Mic Jack\";\n+\n+\t\tsimple-audio-card,cpu {\n+\t\t\tsound-dai = \u003c\u0026i2s0\u003e;\n+\t\t};\n+\n+\t\tsimple-audio-card,codec {\n+\t\t\tsound-dai = \u003c\u0026rk809\u003e;\n+\t\t};\n+\t};\n+\n+\tvcc5v0_sys: regulator-vcc5v0-sys {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vcc5v0_sys\";\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t\tregulator-min-microvolt = \u003c5000000\u003e;\n+\t\tregulator-max-microvolt = \u003c5000000\u003e;\n+\t};\n+\n+\tsdio_pwrseq: pwrseq-sdio {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = \u003c\u0026wifi_enable_h\u003e;\n+\t\treset-gpios = \u003c\u0026gpio0 RK_PA6 GPIO_ACTIVE_LOW\u003e;\n+\t\tpost-power-on-delay-ms = \u003c200\u003e;\n+\t\tpower-off-delay-us = \u003c20000\u003e;\n+\t};\n+};\n+\n+\u0026i2c5 {\n+\tstatus = \"okay\";\n+\tclock-frequency = \u003c400000\u003e;\n+\n+\tpcf8563: rtc@51 {\n+\t\tcompatible = \"nxp,pcf8563\";\n+\t\treg = \u003c0x51\u003e;\n+\t\t#clock-cells = \u003c0\u003e;\n+\t\tinterrupt-parent = \u003c\u0026gpio1\u003e;\n+\t\tinterrupts = \u003cRK_PD0 IRQ_TYPE_LEVEL_LOW\u003e;\n+\t\tclock-output-names = \"xin32k\";\n+\t};\n+};\n+\n+\u0026gmac {\n+\tphy-mode = \"rgmii-id\";\n+\tclock_in_out = \"input\";\n+\tassigned-clocks = \u003c\u0026cru CLK_GMAC_SRC\u003e, \u003c\u0026cru CLK_GMAC_TX_RX\u003e,\n+\t\t\t  \u003c\u0026cru CLK_GMAC_ETHERNET_OUT\u003e;\n+\tassigned-clock-parents = \u003c\u0026cru CLK_GMAC_SRC_M1\u003e,\n+\t\t\t\t \u003c\u0026cru RGMII_MODE_CLK\u003e;\n+\tassigned-clock-rates = \u003c125000000\u003e, \u003c0\u003e, \u003c25000000\u003e;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026rgmiim1_miim \u0026rgmiim1_bus2 \u0026rgmiim1_bus4\n+\t\t     \u0026clk_out_ethernetm1_pins\u003e;\n+\tphy-handle = \u003c\u0026phy\u003e;\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdio {\n+\tphy: ethernet-phy@1 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = \u003c0x1\u003e;\n+\t\tclocks = \u003c\u0026cru CLK_GMAC_ETHERNET_OUT\u003e;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = \u003c\u0026eth_phy_rst\u003e;\n+\t\treset-gpios = \u003c\u0026gpio3 RK_PA0 GPIO_ACTIVE_LOW\u003e;\n+\t\treset-assert-us = \u003c20000\u003e;\n+\t\treset-deassert-us = \u003c100000\u003e;\n+\t};\n+};\n+\n+\u0026pinctrl {\n+\tethernet {\n+\t\teth_phy_rst: eth-phy-rst {\n+\t\t\trockchip,pins = \u003c3 RK_PA0 RK_FUNC_GPIO \u0026pcfg_pull_down\u003e;\n+\t\t};\n+\t};\n+\n+\tbt {\n+\t\tbt_enable: bt-enable {\n+\t\t\trockchip,pins = \u003c0 RK_PA7 RK_FUNC_GPIO \u0026pcfg_pull_none\u003e;\n+\t\t};\n+\n+\t\tbt_wake_dev: bt-wake-dev {\n+\t\t\trockchip,pins = \u003c1 RK_PD1 RK_FUNC_GPIO \u0026pcfg_pull_none\u003e;\n+\t\t};\n+\n+\t\tbt_wake_host: bt-wake-host {\n+\t\t\trockchip,pins = \u003c0 RK_PA5 RK_FUNC_GPIO \u0026pcfg_pull_none\u003e;\n+\t\t};\n+\t};\n+\n+\twifi {\n+\t\twifi_enable_h: wifi-enable-h {\n+\t\t\trockchip,pins = \u003c0 RK_PA6 RK_FUNC_GPIO \u0026pcfg_pull_none\u003e;\n+\t\t};\n+\t};\n+};\n+\n+\u0026sdio {\n+\tbus-width = \u003c4\u003e;\n+\tcap-sdio-irq;\n+\tkeep-power-in-suspend;\n+\tmax-frequency = \u003c25000000\u003e;\n+\tmmc-pwrseq = \u003c\u0026sdio_pwrseq\u003e;\n+\tnon-removable;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026sdmmc1_clk \u0026sdmmc1_cmd \u0026sdmmc1_bus4\u003e;\n+\trockchip,default-sample-phase = \u003c90\u003e;\n+\tvmmc-supply = \u003c\u0026vcc3v3_sd\u003e;\n+\tvqmmc-supply = \u003c\u0026vcc_1v8\u003e;\n+\tstatus = \"okay\";\n+};\n+\n+\u0026sdmmc {\n+\tbus-width = \u003c4\u003e;\n+\tcap-mmc-highspeed;\n+\tcap-sd-highspeed;\n+\tcard-detect-delay = \u003c200\u003e;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026sdmmc0_clk \u0026sdmmc0_cmd \u0026sdmmc0_bus4 \u0026sdmmc0_det\u003e;\n+\trockchip,default-sample-phase = \u003c90\u003e;\n+\tsd-uhs-sdr12;\n+\tsd-uhs-sdr25;\n+\tsd-uhs-sdr104;\n+\tvmmc-supply = \u003c\u0026vcc3v3_sd\u003e;\n+\tvqmmc-supply = \u003c\u0026vccio_sd\u003e;\n+\tstatus = \"okay\";\n+};\n+\n+\u0026uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart0_xfer \u0026uart0_ctsn \u0026uart0_rtsn\u003e;\n+\tuart-has-rtscts;\n+\tstatus = \"okay\";\n+\n+\tbluetooth {\n+\t\tcompatible = \"brcm,bcm43430a1-bt\";\n+\t\tshutdown-gpios = \u003c\u0026gpio0 RK_PA7 GPIO_ACTIVE_HIGH\u003e;\n+\t\tdevice-wakeup-gpios = \u003c\u0026gpio1 RK_PD1 GPIO_ACTIVE_HIGH\u003e;\n+\t\tclocks = \u003c\u0026rk809 1\u003e;\n+\t\tclock-names = \"lpo\";\n+\t\tinterrupt-parent = \u003c\u0026gpio0\u003e;\n+\t\tinterrupts = \u003cRK_PA5 IRQ_TYPE_EDGE_RISING\u003e;\n+\t\tinterrupt-names = \"host-wakeup\";\n+\t\tmax-speed = \u003c115200\u003e;\n+\t\tvbat-supply = \u003c\u0026vcc_3v3\u003e;\n+\t\tvddio-supply = \u003c\u0026vcc_1v8\u003e;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = \u003c\u0026bt_enable\u003e, \u003c\u0026bt_wake_dev\u003e, \u003c\u0026bt_wake_host\u003e;\n+\t};\n+};\n+\n+\u0026uart2 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026i2s0 {\n+\trockchip,trcm-sync-tx-only;\n+\trockchip,i2s-rx-route = \u003c3 1 2 0\u003e;\n+\trockchip,i2s-tx-route = \u003c0 1 2 3\u003e;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2s0m0_sclk_tx\u003e,\n+\t\t    \u003c\u0026i2s0m0_mclk\u003e,\n+\t\t    \u003c\u0026i2s0m0_lrck_tx\u003e,\n+\t\t    \u003c\u0026i2s0m0_sdo0\u003e,\n+\t\t    \u003c\u0026i2s0m0_sdo1_sdi3\u003e;\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi\nindex 35ef6732281fd9..1d883b80aed434 100644\n--- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi\n+++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi\n@@ -123,6 +123,16 @@ i2c3m2_xfer: i2c3m2-xfer {\n \t\t\t\t\u003c1 RK_PD7 3 \u0026pcfg_pull_none\u003e;\n \t\t};\n \t};\n+\ti2c5 {\n+\t\t/omit-if-no-ref/\n+\t\ti2c5m0_xfer: i2c5m0-xfer {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c5_scl_m0 */\n+\t\t\t\t\u003c2 RK_PA5 7 \u0026pcfg_pull_none_drv_level_0_smt\u003e,\n+\t\t\t\t/* i2c5_sda_m0 */\n+\t\t\t\t\u003c2 RK_PB3 7 \u0026pcfg_pull_none_drv_level_0_smt\u003e;\n+\t\t};\n+\t};\n \ti2s0 {\n \t\ti2s0m0_lrck_tx: i2s0m0-lrck-tx {\n \t\t\trockchip,pins =\ndiff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi\nindex d6e8b63daa4207..d0cdc5f742120f 100644\n--- a/arch/arm/boot/dts/rockchip/rv1126.dtsi\n+++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi\n@@ -23,6 +23,7 @@ aliases {\n \t\ti2c0 = \u0026i2c0;\n \t\ti2c2 = \u0026i2c2;\n \t\ti2c3 = \u0026i2c3;\n+\t\ti2c5 = \u0026i2c5;\n \t\tserial0 = \u0026uart0;\n \t\tserial1 = \u0026uart1;\n \t\tserial2 = \u0026uart2;\n@@ -400,6 +401,20 @@ i2c3: i2c@ff520000 {\n \t\tstatus = \"disabled\";\n \t};\n \n+\ti2c5: i2c@ff540000 {\n+\t\tcompatible = \"rockchip,rv1126-i2c\", \"rockchip,rk3399-i2c\";\n+\t\treg = \u003c0xff540000 0x1000\u003e;\n+\t\tinterrupts = \u003cGIC_SPI 9 IRQ_TYPE_LEVEL_HIGH\u003e;\n+\t\tclocks = \u003c\u0026cru CLK_I2C5\u003e, \u003c\u0026cru PCLK_I2C5\u003e;\n+\t\tclock-names = \"i2c\", \"pclk\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = \u003c\u0026i2c5m0_xfer\u003e;\n+\t\trockchip,grf = \u003c\u0026pmugrf\u003e;\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n \tpwm8: pwm@ff550000 {\n \t\tcompatible = \"rockchip,rv1126-pwm\", \"rockchip,rk3328-pwm\";\n \t\treg = \u003c0xff550000 0x10\u003e;\ndiff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c\nindex 5071605a1a117a..3396a38cfc0f2a 100644\n--- a/drivers/net/phy/motorcomm.c\n+++ b/drivers/net/phy/motorcomm.c\n@@ -6,6 +6,7 @@\n  * Author: Frank \u003cFrank.Sae@motor-comm.com\u003e\n  */\n \n+#include \u003clinux/clk.h\u003e\n #include \u003clinux/etherdevice.h\u003e\n #include \u003clinux/kernel.h\u003e\n #include \u003clinux/module.h\u003e\n@@ -1180,9 +1181,15 @@ static int yt8521_probe(struct phy_device *phydev)\n static int yt8531_probe(struct phy_device *phydev)\n {\n \tstruct device *dev = \u0026phydev-\u003emdio.dev;\n+\tstruct clk *clk;\n \tu16 mask, val;\n \tu32 freq;\n \n+\tclk = devm_clk_get_optional_enabled(dev, NULL);\n+\tif (IS_ERR(clk))\n+\t\treturn dev_err_probe(dev, PTR_ERR(clk),\n+\t\t\t\t     \"failed to get and enable PHY clock\\n\");\n+\n \tif (device_property_read_u32(dev, \"motorcomm,clk-out-frequency-hz\", \u0026freq))\n \t\tfreq = YTPHY_DTS_OUTPUT_CLK_DIS;\n \n"
}
2/1 2026/07/06 11:06 agent patch-evaluator
0m Model: 
gemini-3.1-pro-preview

Args: 
null

Results: 
{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch primarily adds device tree bindings and files for Alientek CLRV1126F SoM based boards. The only executable code change is a trivial clock initialization (devm_clk_get_optional_enabled) in the hardware-specific motorcomm PHY driver, which is not meaningfully fuzzable in a virtualized environment.",
  "WorthFuzzing": false
}

Instruction: 
You are an expert Linux kernel maintainer.
Your job is to review a provided patch series and determine
if it makes functional changes to the kernel that should be fuzzed.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively
use your code access tools to examine the actual source code and confirm any assumptions.

Return WorthFuzzing=false if the patch only contains:
- Modifications to Documentation/, Kconfig files, or code comments.
- Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints.
- Changes to numeric constants or macros that do not functionally alter execution flow.
- Code paths that are impossible to reach in virtualized environments like GCE or QEMU,
even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim).

If it modifies reachable core kernel logic, drivers, or architectures, use your code search
tools to verify the code can be executed, then return WorthFuzzing=true.

When returning WorthFuzzing=true, you MUST ALSO:
1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols.
   Avoid listing generic hot-path functions to prevent skewed test distributions.
2. Identify any specific CONFIG_ options required to properly test this new/modified feature.
   Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions.
   Do not list too generic configs (we already have them enabled). Only list those that
   specifically cover the modified code. List them in the EnableConfigs output array,
   and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Prompt: 
For your convenience, here is the diff of the changes:
commit 7fbf1d98011dacbdf701f66d0cbb0668bc9b83c2
Author: syz-cluster <triage@syzkaller.com>
Date:   Mon Jul 6 11:06:43 2026 +0000

    syz-cluster: applied patch under review

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 1a9dde18626d00..9058f2a461d577 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -162,6 +162,13 @@ properties:
           - const: coolpi,pi-4b
           - const: rockchip,rk3588s
 
+      - description: Alientek CLRV1126F SoM based boards
+        items:
+          - enum:
+              - alientek,dlrv1126
+          - const: alientek,clrv1126f
+          - const: rockchip,rv1126
+
       - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
         items:
           - const: edgeble,neural-compute-module-2-io   # Edgeble Neural Compute Module 2 IO Board
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 396044f368e7cf..914d5a8fd628de 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -88,6 +88,8 @@ patternProperties:
     description: ALFA Network Inc.
   "^algoltek,.*":
     description: AlgolTek, Inc.
+  "^alientek,.*":
+    description: Guangzhou Xingyi Intelligent Technology Co., Ltd.
   "^allegro,.*":
     description: Allegro DVT
   "^allegromicro,.*":
diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile
index d0154fd7ff24f9..e9f9e0ac3bfd48 100644
--- a/arch/arm/boot/dts/rockchip/Makefile
+++ b/arch/arm/boot/dts/rockchip/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1108-evb.dtb \
 	rv1109-relfor-saib.dtb \
 	rv1109-sonoff-ihost.dtb \
+	rv1126-alientek-dlrv1126.dtb \
 	rv1126-edgeble-neu2-io.dtb \
 	rv1126-sonoff-ihost.dtb \
 	rk3036-evb.dtb \
diff --git a/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi b/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi
new file mode 100644
index 00000000000000..9bee424b179793
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2026 Yanan He <grumpycat921013@gmail.com>
+ */
+
+#include "rv1126.dtsi"
+
+/ {
+	compatible = "alientek,clrv1126f", "rockchip,rv1126";
+
+	aliases {
+		mmc0 = &emmc;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+	rockchip,default-sample-phase = <90>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		#sound-dai-cells = <0>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		clock-names = "mclk";
+		clocks = <&cru MCLK_I2S0_TX_OUT2IO>;
+		assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>;
+		assigned-clock-parents = <&cru MCLK_I2S0_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc_buck5>;
+		vcc6-supply = <&vcc_buck5>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+
+		regulators {
+			vdd_npu_vepu: DCDC_REG1 {
+				regulator-name = "vdd_npu_vepu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <650000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <725000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_sys: DCDC_REG4 {
+				regulator-name = "vcc3v3_sys";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_buck5: DCDC_REG5 {
+				regulator-name = "vcc_buck5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <2200000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2200000>;
+				};
+			};
+
+			vcc_0v8: LDO_REG1 {
+				regulator-name = "vcc_0v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG2 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd0v8_pmu: LDO_REG3 {
+				regulator-name = "vcc0v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <800000>;
+				};
+			};
+
+			vcc_1v8: LDO_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_dovdd: LDO_REG5 {
+				regulator-name = "vcc_dovdd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_dvdd: LDO_REG6 {
+				regulator-name = "vcc_dvdd";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_avdd: LDO_REG7 {
+				regulator-name = "vcc_avdd";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG8 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: LDO_REG9 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_5v0: SWITCH_REG1 {
+				regulator-name = "vcc_5v0";
+			};
+
+			vcc_3v3: SWITCH_REG2 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio0-supply = <&vcc3v3_sys>;
+	pmuio1-supply = <&vcc3v3_sys>;
+	vccio1-supply = <&vcc_1v8>;
+	vccio2-supply = <&vccio_sd>;
+	vccio3-supply = <&vcc_1v8>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts b/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts
new file mode 100644
index 00000000000000..33c6c74d08b916
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2026 Yanan He <grumpycat921013@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "rv1126-alientek-clrv1126f.dtsi"
+
+/ {
+	model = "Alientek ATK-DLRV1126";
+	compatible = "alientek,dlrv1126", "alientek,clrv1126f", "rockchip,rv1126";
+
+	aliases {
+		ethernet0 = &gmac;
+		mmc1 = &sdio;
+		mmc2 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-esc {
+			label = "esc";
+			linux,code = <KEY_ESC>;
+			press-threshold-microvolt = <0>;
+		};
+
+		button-right {
+			label = "right";
+			linux,code = <KEY_RIGHT>;
+			press-threshold-microvolt = <400781>;
+		};
+
+		button-left {
+			label = "left";
+			linux,code = <KEY_LEFT>;
+			press-threshold-microvolt = <801562>;
+		};
+
+		button-menu {
+			label = "menu";
+			linux,code = <KEY_MENU>;
+			press-threshold-microvolt = <1198828>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "sys-led";
+			gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+		};
+
+		led-1 {
+			label = "user-led";
+			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "none";
+			default-state = "on";
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,widgets =
+			"Speaker", "Speaker",
+			"Headphone", "Headphones",
+			"Microphone", "Mic Jack";
+		simple-audio-card,routing =
+			"Speaker", "SPKO",
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"MICL", "Mic Jack";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	sdio_pwrseq: pwrseq-sdio {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <200>;
+		power-off-delay-us = <20000>;
+	};
+};
+
+&i2c5 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	pcf8563: rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
+		clock-output-names = "xin32k";
+	};
+};
+
+&gmac {
+	phy-mode = "rgmii-id";
+	clock_in_out = "input";
+	assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
+			  <&cru CLK_GMAC_ETHERNET_OUT>;
+	assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>,
+				 <&cru RGMII_MODE_CLK>;
+	assigned-clock-rates = <125000000>, <0>, <25000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4
+		     &clk_out_ethernetm1_pins>;
+	phy-handle = <&phy>;
+	status = "okay";
+};
+
+&mdio {
+	phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		clocks = <&cru CLK_GMAC_ETHERNET_OUT>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&eth_phy_rst>;
+		reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+	};
+};
+
+&pinctrl {
+	ethernet {
+		eth_phy_rst: eth-phy-rst {
+			rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	bt {
+		bt_enable: bt-enable {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_dev: bt-wake-dev {
+			rockchip,pins = <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_host: bt-wake-host {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdio {
+	bus-width = <4>;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	max-frequency = <25000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
+	rockchip,default-sample-phase = <90>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
+	rockchip,default-sample-phase = <90>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43430a1-bt";
+		shutdown-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA5 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "host-wakeup";
+		max-speed = <115200>;
+		vbat-supply = <&vcc_3v3>;
+		vddio-supply = <&vcc_1v8>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&i2s0 {
+	rockchip,trcm-sync-tx-only;
+	rockchip,i2s-rx-route = <3 1 2 0>;
+	rockchip,i2s-tx-route = <0 1 2 3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0m0_sclk_tx>,
+		    <&i2s0m0_mclk>,
+		    <&i2s0m0_lrck_tx>,
+		    <&i2s0m0_sdo0>,
+		    <&i2s0m0_sdo1_sdi3>;
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
index 35ef6732281fd9..1d883b80aed434 100644
--- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
@@ -123,6 +123,16 @@ i2c3m2_xfer: i2c3m2-xfer {
 				<1 RK_PD7 3 &pcfg_pull_none>;
 		};
 	};
+	i2c5 {
+		/omit-if-no-ref/
+		i2c5m0_xfer: i2c5m0-xfer {
+			rockchip,pins =
+				/* i2c5_scl_m0 */
+				<2 RK_PA5 7 &pcfg_pull_none_drv_level_0_smt>,
+				/* i2c5_sda_m0 */
+				<2 RK_PB3 7 &pcfg_pull_none_drv_level_0_smt>;
+		};
+	};
 	i2s0 {
 		i2s0m0_lrck_tx: i2s0m0-lrck-tx {
 			rockchip,pins =
diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi
index d6e8b63daa4207..d0cdc5f742120f 100644
--- a/arch/arm/boot/dts/rockchip/rv1126.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi
@@ -23,6 +23,7 @@ aliases {
 		i2c0 = &i2c0;
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
+		i2c5 = &i2c5;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
@@ -400,6 +401,20 @@ i2c3: i2c@ff520000 {
 		status = "disabled";
 	};
 
+	i2c5: i2c@ff540000 {
+		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+		reg = <0xff540000 0x1000>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+		clock-names = "i2c", "pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c5m0_xfer>;
+		rockchip,grf = <&pmugrf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	pwm8: pwm@ff550000 {
 		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
 		reg = <0xff550000 0x10>;
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index 5071605a1a117a..3396a38cfc0f2a 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -6,6 +6,7 @@
  * Author: Frank <Frank.Sae@motor-comm.com>
  */
 
+#include <linux/clk.h>
 #include <linux/etherdevice.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -1180,9 +1181,15 @@ static int yt8521_probe(struct phy_device *phydev)
 static int yt8531_probe(struct phy_device *phydev)
 {
 	struct device *dev = &phydev->mdio.dev;
+	struct clk *clk;
 	u16 mask, val;
 	u32 freq;
 
+	clk = devm_clk_get_optional_enabled(dev, NULL);
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "failed to get and enable PHY clock\n");
+
 	if (device_property_read_u32(dev, "motorcomm,clk-out-frequency-hz", &freq))
 		freq = YTPHY_DTS_OUTPUT_CLK_DIS;

3/2 2026/07/06 11:06 llm patch-evaluator
0m Model: 
gemini-3.1-pro-preview

Args: 
null

Results: 
null

Tokens: 
							input: 10067
							output: 21
							thoughts: 581

Thoughts: 
**Analyzing the Alientek CLRV1126F SoM Patch**

Okay, so I'm looking at this patch for the Alientek CLRV1126F SoM boards. It seems to be adding device tree bindings and some files, along with a modification to `drivers/net/phy/motorcomm.c`. The interesting part is the addition in `yt8531_probe` – getting and enabling an optional clock.

My initial thought is to quickly assess the nature of the change. This is a functional modification within a PHY driver. I immediately start thinking about fuzzing potential. Can this be reached in a virtualized setting? PHY drivers are typically accessed through the MDIO bus. Can I set up a virtual MDIO bus in QEMU? Yes, that's possible, either via the device tree or through sysfs. 

Then I remember that syzkaller *might* be relevant here. Can syzkaller inject devices, or can I simply load the module and attempt to mock the MDIO bus? Ah, yes, syzkaller does have some support for MDIO/PHY fuzzing, either via netlink or through mock devices. But then I quickly re-calibrate my approach. Most PHY drivers are probed when a network device that utilizes an MDIO bus is registered.

Focusing on the core change, which is in the `yt8531_probe` function for the PHY device, the actual functional addition is just `devm_clk_get_optional_enabled`. Is fuzzing this even worth it? Really, all we'd be testing is the behavior of `devm_clk_get_optional_enabled` in this context. Is it a significant functional change? No, it's a very minor change within a specific PHY driver. It's a question of whether `MOTORCOMM_PHY` is enabled or even can be enabled. Okay, I'll quickly grep for `yt8531_probe` to confirm that.

4/2 2026/07/06 11:06 tool grepper
0m Args: 
{
  "Expression": "yt8531_probe"
}

Results: 
{
  "Output": "drivers/net/phy/motorcomm.c=1064=static int yt8521_probe(struct phy_device *phydev)\n--\ndrivers/net/phy/motorcomm.c-1180-\ndrivers/net/phy/motorcomm.c:1181:static int yt8531_probe(struct phy_device *phydev)\ndrivers/net/phy/motorcomm.c-1182-{\n--\ndrivers/net/phy/motorcomm.c=3069=static struct phy_driver motorcomm_phy_drvs[] = {\n--\ndrivers/net/phy/motorcomm.c-3109-\t\t.name\t\t= \"YT8531 Gigabit Ethernet\",\ndrivers/net/phy/motorcomm.c:3110:\t\t.probe\t\t= yt8531_probe,\ndrivers/net/phy/motorcomm.c-3111-\t\t.config_init\t= yt8531_config_init,\n"
}
5/2 2026/07/06 11:06 llm patch-evaluator
0m Model: 
gemini-3.1-pro-preview

Args: 
null

Results: 
null

Tokens: 
							input: 11341
							output: 100
							thoughts: 607

Thoughts: 
**Fuzzing Decision for `drivers/net/phy/motorcomm.c`**

Okay, let's break this down. My initial thought is, "Is this even fuzzable?" We're looking at a specific PHY driver, `motorcomm.c`. Realistically, reaching this code path requires either specific hardware or, at the very least, a mocked MDIO bus. That's a hurdle, right off the bat.

Even if we get that far, the code change itself is minimal. It's just a call to `devm_clk_get_optional_enabled`. Not exactly a prime target for fuzzing. The rest of the patch is all device tree stuff: bindings, `.yaml` and `.dts` files, and a `Makefile`. Those aren't executable code; they're declarative. They define the hardware configuration.

The only executable code change is in `motorcomm.c`. The question is, can we trigger that in a virtualized environment? Probably not easily. Unless there's a virtual MDIO bus that just probes all PHYs. But even then, this is still just a clock get.

Wait a second, syzkaller doesn't typically go after PHY drivers unless they're exposed to userspace somehow. Okay, but I remember that PHY drivers can be reached if a virtual netdev is created, and if the MDIO bus is exposed on that virtual netdev. However, the change here is minimal.

So, I'm going to mark this as `WorthFuzzing=false`. It's largely device tree changes, which are not code, and the C file has a trivial clock initialization. Just fetching a clock.

Just to be absolutely certain, let me double-check the other files that are touched by this diff. Okay, the diff touches: Documentation, a bunch of device tree files (`.yaml`, `.dts`, `.dtsi`), a `Makefile`, and the `motorcomm.c` driver.

Yes, only the C file, `motorcomm.c`, actually contains executable code. And that's just six lines to fetch a clock. Fuzzing that? No. Not worth it.

6/2 2026/07/06 11:07 tool set-results
0m Args: 
{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch primarily adds device tree bindings and files for Alientek CLRV1126F SoM based boards. The only executable code change is a trivial clock initialization (devm_clk_get_optional_enabled) in the hardware-specific motorcomm PHY driver, which is not meaningfully fuzzable in a virtualized environment.",
  "WorthFuzzing": false
}

Results: 
{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch primarily adds device tree bindings and files for Alientek CLRV1126F SoM based boards. The only executable code change is a trivial clock initialization (devm_clk_get_optional_enabled) in the hardware-specific motorcomm PHY driver, which is not meaningfully fuzzable in a virtualized environment.",
  "WorthFuzzing": false
}
LLM Calls Summary:
Total Calls Total Tokens Avg Tokens Total Duration (Seconds) Avg Duration (Seconds)
Tool Calls Summary:
Total Calls Total Duration (Seconds) Avg Duration (Seconds)