AI Trajectory

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies the Airoha SoC Gigabit Ethernet driver (drivers/net/ethernet/airoha/), which is a platform driver specifically targeting Airoha SoCs (e.g., EN7581). This hardware cannot be reached or emulated in standard virtualized environments like QEMU or GCE.",
  "WorthFuzzing": false
}

null

{
  "PatchDiff": "commit 45d74778d2e5f7ac7e385c3554cb52ebde7809dd\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Wed Sep 2 06:50:32 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c\nindex 64619e9a704dd..c59201aded26f 100644\n--- a/drivers/net/ethernet/airoha/airoha_eth.c\n+++ b/drivers/net/ethernet/airoha/airoha_eth.c\n@@ -784,13 +784,16 @@ static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)\n \t\tint i, qid = q - \u0026qdma-\u003eq_rx[0];\n \t\tint intr_reg = qid \u003c RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1\n \t\t\t\t\t\t\t : QDMA_INT_REG_IDX2;\n+\t\tu32 irq_id = qid % RX_DONE_HIGH_OFFSET;\n+\t\tu32 intr_mask = BIT(irq_id) |\n+\t\t\t\tBIT(irq_id + RX_NO_CPU_DSCP_LOW_OFFSET);\n \n \t\tfor (i = 0; i \u003c ARRAY_SIZE(qdma-\u003eirq_banks); i++) {\n \t\t\tif (!(BIT(qid) \u0026 RX_IRQ_BANK_PIN_MASK(i)))\n \t\t\t\tcontinue;\n \n \t\t\tairoha_qdma_irq_enable(\u0026qdma-\u003eirq_banks[i], intr_reg,\n-\t\t\t\t\t       BIT(qid % RX_DONE_HIGH_OFFSET));\n+\t\t\t\t\t       intr_mask);\n \t\t}\n \t}\n \n@@ -1468,16 +1471,19 @@ static irqreturn_t airoha_irq_handler(int irq, void *dev_instance)\n \tif (!test_bit(DEV_STATE_INITIALIZED, \u0026qdma-\u003eeth-\u003estate))\n \t\treturn IRQ_NONE;\n \n-\trx_intr1 = intr[1] \u0026 RX_DONE_LOW_INT_MASK;\n+\trx_intr1 = intr[1] \u0026 (RX_DONE_LOW_INT_MASK | RX_NO_CPU_DSCP_LOW_INT_MASK);\n \tif (rx_intr1) {\n \t\tairoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1);\n-\t\trx_intr_mask |= rx_intr1;\n+\t\trx_intr_mask |= (rx_intr1 \u0026 RX_DONE_LOW_INT_MASK) |\n+\t\t\t\tRX_NO_CPU_DSCP_INT_RX1_MASK(rx_intr1);\n \t}\n \n-\trx_intr2 = intr[2] \u0026 RX_DONE_HIGH_INT_MASK;\n+\trx_intr2 = intr[2] \u0026 (RX_DONE_HIGH_INT_MASK | RX_NO_CPU_DSCP_HIGH_INT_MASK);\n \tif (rx_intr2) {\n \t\tairoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2);\n-\t\trx_intr_mask |= (rx_intr2 \u003c\u003c 16);\n+\t\trx_intr_mask |= ((rx_intr2 \u0026 RX_DONE_HIGH_INT_MASK) \u003c\u003c\n+\t\t\t\t RX_DONE_HIGH_OFFSET) |\n+\t\t\t\t(rx_intr2 \u0026 RX_NO_CPU_DSCP_HIGH_INT_MASK);\n \t}\n \n \tfor (i = 0; rx_intr_mask \u0026\u0026 i \u003c ARRAY_SIZE(qdma-\u003eq_rx); i++) {\ndiff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h\nindex fa9a8edce22ff..7fc37f159d2b8 100644\n--- a/drivers/net/ethernet/airoha/airoha_eth.h\n+++ b/drivers/net/ethernet/airoha/airoha_eth.h\n@@ -41,9 +41,10 @@\n #define TX_DSCP_NUM\t\t\t1024\n #define RX_DSCP_NUM(_n)\t\t\t\\\n \t((_n) ==  2 ? 128 :\t\t\\\n+\t (_n) ==  4 ? 128 :\t\t\\\n \t (_n) == 11 ? 128 :\t\t\\\n \t (_n) == 15 ? 128 :\t\t\\\n-\t (_n) ==  0 ? 1024 : 16)\n+\t (_n) ==  0 ? 1024 : 32)\n \n #define PSE_RSV_PAGES\t\t\t128\n #define PSE_QUEUE_RSV_PAGES\t\t64\ndiff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h\nindex 442b48c9b991e..bde3d599d8b7c 100644\n--- a/drivers/net/ethernet/airoha/airoha_regs.h\n+++ b/drivers/net/ethernet/airoha/airoha_regs.h\n@@ -549,6 +549,8 @@\n #define INT_RX1_MASK(_n)\t\t\t\t\t\t\t\\\n \t((((_n) \u003c\u003c RX_NO_CPU_DSCP_LOW_OFFSET) \u0026 RX_NO_CPU_DSCP_LOW_INT_MASK) |\t\\\n \t (RX_DONE_LOW_INT_MASK \u0026 (_n)))\n+#define RX_NO_CPU_DSCP_INT_RX1_MASK(_n)\t\t\t\t\t\\\n+\t(((_n) \u0026 RX_NO_CPU_DSCP_LOW_INT_MASK) \u003e\u003e RX_NO_CPU_DSCP_LOW_OFFSET)\n \n /* QDMA_CSR_INT_ENABLE3 */\n #define RX31_NO_CPU_DSCP_INT_MASK\tBIT(31)\n"
}

core

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Airoha SoC Gigabit Ethernet driver (drivers/net/ethernet/airoha/), which is a platform driver specifically targeting Airoha SoCs (e.g., EN7581). This hardware cannot be reached or emulated in standard virtualized environments like QEMU or GCE.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer.
Your job is to review a provided patch series and determine
if it makes functional changes to the kernel that should be fuzzed.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively
use your code access tools to examine the actual source code and confirm any assumptions.

Return WorthFuzzing=false if the patch only contains:
- Modifications to Documentation/, Kconfig files, or code comments.
- Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints.
- Changes to numeric constants or macros that do not functionally alter execution flow.
- Code paths that are impossible to reach in virtualized environments like GCE or QEMU,
  even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim).
- Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed,
  ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU.
- Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove)
  that are executed only during PCI hot-unplug or sysfs driver unbind operations.

If it modifies reachable core kernel logic, drivers, or architectures, use your code search
tools to verify the code can be executed, then return WorthFuzzing=true.

When returning WorthFuzzing=true, you MUST ALSO:
1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols.
   Avoid listing generic hot-path functions to prevent skewed test distributions.
   Prefer non-static, non-inlined API entrypoint functions over internal static helper functions
   (which are inlined by the compiler and do not have distinct symbol addresses).
2. Identify any specific CONFIG_ options required to properly test this new/modified feature.
   Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions.
   Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs
   needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs
   output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

For your convenience, here is the diff of the changes:
commit 45d74778d2e5f7ac7e385c3554cb52ebde7809dd
Author: syz-cluster <triage@syzkaller.com>
Date:   Wed Sep 2 06:50:32 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 64619e9a704dd..c59201aded26f 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -784,13 +784,16 @@ static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)
 		int i, qid = q - &qdma->q_rx[0];
 		int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1
 							 : QDMA_INT_REG_IDX2;
+		u32 irq_id = qid % RX_DONE_HIGH_OFFSET;
+		u32 intr_mask = BIT(irq_id) |
+				BIT(irq_id + RX_NO_CPU_DSCP_LOW_OFFSET);
 
 		for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
 			if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i)))
 				continue;
 
 			airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg,
-					       BIT(qid % RX_DONE_HIGH_OFFSET));
+					       intr_mask);
 		}
 	}
 
@@ -1468,16 +1471,19 @@ static irqreturn_t airoha_irq_handler(int irq, void *dev_instance)
 	if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state))
 		return IRQ_NONE;
 
-	rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK;
+	rx_intr1 = intr[1] & (RX_DONE_LOW_INT_MASK | RX_NO_CPU_DSCP_LOW_INT_MASK);
 	if (rx_intr1) {
 		airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1);
-		rx_intr_mask |= rx_intr1;
+		rx_intr_mask |= (rx_intr1 & RX_DONE_LOW_INT_MASK) |
+				RX_NO_CPU_DSCP_INT_RX1_MASK(rx_intr1);
 	}
 
-	rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK;
+	rx_intr2 = intr[2] & (RX_DONE_HIGH_INT_MASK | RX_NO_CPU_DSCP_HIGH_INT_MASK);
 	if (rx_intr2) {
 		airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2);
-		rx_intr_mask |= (rx_intr2 << 16);
+		rx_intr_mask |= ((rx_intr2 & RX_DONE_HIGH_INT_MASK) <<
+				 RX_DONE_HIGH_OFFSET) |
+				(rx_intr2 & RX_NO_CPU_DSCP_HIGH_INT_MASK);
 	}
 
 	for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) {
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index fa9a8edce22ff..7fc37f159d2b8 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -41,9 +41,10 @@
 #define TX_DSCP_NUM			1024
 #define RX_DSCP_NUM(_n)			\
 	((_n) ==  2 ? 128 :		\
+	 (_n) ==  4 ? 128 :		\
 	 (_n) == 11 ? 128 :		\
 	 (_n) == 15 ? 128 :		\
-	 (_n) ==  0 ? 1024 : 16)
+	 (_n) ==  0 ? 1024 : 32)
 
 #define PSE_RSV_PAGES			128
 #define PSE_QUEUE_RSV_PAGES		64
diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h
index 442b48c9b991e..bde3d599d8b7c 100644
--- a/drivers/net/ethernet/airoha/airoha_regs.h
+++ b/drivers/net/ethernet/airoha/airoha_regs.h
@@ -549,6 +549,8 @@
 #define INT_RX1_MASK(_n)							\
 	((((_n) << RX_NO_CPU_DSCP_LOW_OFFSET) & RX_NO_CPU_DSCP_LOW_INT_MASK) |	\
 	 (RX_DONE_LOW_INT_MASK & (_n)))
+#define RX_NO_CPU_DSCP_INT_RX1_MASK(_n)					\
+	(((_n) & RX_NO_CPU_DSCP_LOW_INT_MASK) >> RX_NO_CPU_DSCP_LOW_OFFSET)
 
 /* QDMA_CSR_INT_ENABLE3 */
 #define RX31_NO_CPU_DSCP_INT_MASK	BIT(31)

gemini-3.7-flash

null

null

							input: 3348
							output: 32
							thoughts: 82
						

Okay, here's my summary, presented as a stream of consciousness:

**Diving into the Airoha Ethernet Driver Patch**

Alright, so this patch is touching `drivers/net/ethernet/airoha/airoha_eth.c`, `airoha_eth.h`, and `airoha_regs.h`. My immediate thought is, "Okay, Airoha. Right. Let's get a handle on this." I need to understand what kind of beast this Airoha Ethernet driver *is*. Is this a platform driver for a specific SoC? Is it dealing with a physical Ethernet controller integrated directly onto an Airoha chip? Perhaps it's a PCIe based solution? I need to quickly establish the underlying architecture. Time to employ some classic techniques. I'll probably start with a quick `read-file` or `grepper` search within the kernel source. Get a feel for the surrounding code, the device tree bindings if it's a platform driver, or any clues about the hardware it's interfacing with. Gotta build that mental model, quickly.

{
  "Expression": "airoha",
  "PathPrefix": "drivers/net/ethernet/airoha/"
}

{
  "Output": "\nFull output is too long, showing 500 out of 3675 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/airoha/Makefile-5-\ndrivers/net/ethernet/airoha/Makefile:6:obj-$(CONFIG_NET_AIROHA) += airoha-eth.o\ndrivers/net/ethernet/airoha/Makefile:7:airoha-eth-y := airoha_eth.o airoha_ppe.o\ndrivers/net/ethernet/airoha/Makefile:8:airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-16-\ndrivers/net/ethernet/airoha/airoha_eth.c:17:#include \"airoha_regs.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c:18:#include \"airoha_eth.h\"\ndrivers/net/ethernet/airoha/airoha_eth.c-19-\ndrivers/net/ethernet/airoha/airoha_eth.c:20:u32 airoha_rr(void __iomem *base, u32 offset)\ndrivers/net/ethernet/airoha/airoha_eth.c-21-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-24-\ndrivers/net/ethernet/airoha/airoha_eth.c:25:void airoha_wr(void __iomem *base, u32 offset, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-26-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-29-\ndrivers/net/ethernet/airoha/airoha_eth.c:30:u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-31-{\ndrivers/net/ethernet/airoha/airoha_eth.c:32:\tval |= (airoha_rr(base, offset) \u0026 ~mask);\ndrivers/net/ethernet/airoha/airoha_eth.c:33:\tairoha_wr(base, offset, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-34-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-37-\ndrivers/net/ethernet/airoha/airoha_eth.c:38:static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-39-\t\t\t\t    int index, u32 clear, u32 set)\ndrivers/net/ethernet/airoha/airoha_eth.c-40-{\ndrivers/net/ethernet/airoha/airoha_eth.c:41:\tstruct airoha_qdma *qdma = irq_bank-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-42-\tint bank = irq_bank - \u0026qdma-\u003eirq_banks[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-51-\tirq_bank-\u003eirqmask[index] |= set;\ndrivers/net/ethernet/airoha/airoha_eth.c:52:\tairoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),\ndrivers/net/ethernet/airoha/airoha_eth.c-53-\t\t       irq_bank-\u003eirqmask[index]);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-56-\t */\ndrivers/net/ethernet/airoha/airoha_eth.c:57:\tairoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));\ndrivers/net/ethernet/airoha/airoha_eth.c-58-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-61-\ndrivers/net/ethernet/airoha/airoha_eth.c:62:static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-63-\t\t\t\t   int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-64-{\ndrivers/net/ethernet/airoha/airoha_eth.c:65:\tairoha_qdma_set_irqmask(irq_bank, index, 0, mask);\ndrivers/net/ethernet/airoha/airoha_eth.c-66-}\ndrivers/net/ethernet/airoha/airoha_eth.c-67-\ndrivers/net/ethernet/airoha/airoha_eth.c:68:static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,\ndrivers/net/ethernet/airoha/airoha_eth.c-69-\t\t\t\t    int index, u32 mask)\ndrivers/net/ethernet/airoha/airoha_eth.c-70-{\ndrivers/net/ethernet/airoha/airoha_eth.c:71:\tairoha_qdma_set_irqmask(irq_bank, index, mask, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-72-}\ndrivers/net/ethernet/airoha/airoha_eth.c-73-\ndrivers/net/ethernet/airoha/airoha_eth.c:74:static int airoha_set_macaddr(struct airoha_gdm_dev *dev, const u8 *addr)\ndrivers/net/ethernet/airoha/airoha_eth.c-75-{\ndrivers/net/ethernet/airoha/airoha_eth.c-76-\tu8 ref_addr[ETH_ALEN] __aligned(2);\ndrivers/net/ethernet/airoha/airoha_eth.c:77:\tstruct airoha_eth *eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-78-\tu32 reg, val, lmin, lmax;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-85-\tfor (i = 0; i \u003c ARRAY_SIZE(eth-\u003eports); i++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:86:\t\tstruct airoha_gdm_port *port = eth-\u003eports[i];\ndrivers/net/ethernet/airoha/airoha_eth.c-87-\t\tint j;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-92-\t\tfor (j = 0; j \u003c ARRAY_SIZE(port-\u003edevs); j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:93:\t\t\tstruct airoha_gdm_dev *iter_dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-94-\t\t\tstruct net_device *netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-99-\ndrivers/net/ethernet/airoha/airoha_eth.c:100:\t\t\tif (airoha_is_lan_gdm_dev(iter_dev) !=\ndrivers/net/ethernet/airoha/airoha_eth.c:101:\t\t\t    airoha_is_lan_gdm_dev(dev))\ndrivers/net/ethernet/airoha/airoha_eth.c-102-\t\t\t\tcontinue;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-133-\ndrivers/net/ethernet/airoha/airoha_eth.c:134:\treg = airoha_is_lan_gdm_dev(dev) ? REG_FE_LAN_MAC_H : REG_FE_WAN_MAC_H;\ndrivers/net/ethernet/airoha/airoha_eth.c-135-\tval = (addr[0] \u003c\u003c 16) | (addr[1] \u003c\u003c 8) | addr[2];\ndrivers/net/ethernet/airoha/airoha_eth.c:136:\tairoha_fe_wr(eth, reg, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-137-\ndrivers/net/ethernet/airoha/airoha_eth.c:138:\tairoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), lmin);\ndrivers/net/ethernet/airoha/airoha_eth.c:139:\tairoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), lmax);\ndrivers/net/ethernet/airoha/airoha_eth.c-140-\ndrivers/net/ethernet/airoha/airoha_eth.c:141:\tairoha_ppe_init_upd_mem(dev, addr);\ndrivers/net/ethernet/airoha/airoha_eth.c-142-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-145-\ndrivers/net/ethernet/airoha/airoha_eth.c:146:static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,\ndrivers/net/ethernet/airoha/airoha_eth.c-147-\t\t\t\t\tu32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-148-{\ndrivers/net/ethernet/airoha/airoha_eth.c:149:\tairoha_fe_rmw(eth, addr, GDM_OCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-150-\t\t      FIELD_PREP(GDM_OCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:151:\tairoha_fe_rmw(eth, addr, GDM_MCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-152-\t\t      FIELD_PREP(GDM_MCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:153:\tairoha_fe_rmw(eth, addr, GDM_BCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-154-\t\t      FIELD_PREP(GDM_BCFQ_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:155:\tairoha_fe_rmw(eth, addr, GDM_UCFQ_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-156-\t\t      FIELD_PREP(GDM_UCFQ_MASK, val));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-158-\ndrivers/net/ethernet/airoha/airoha_eth.c:159:static int airoha_set_vip_for_gdm_port(struct airoha_gdm_dev *dev, bool enable)\ndrivers/net/ethernet/airoha/airoha_eth.c-160-{\ndrivers/net/ethernet/airoha/airoha_eth.c:161:\tstruct airoha_gdm_port *port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c:162:\tstruct airoha_eth *eth = dev-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-163-\tu32 vip_port;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-166-\tif (enable) {\ndrivers/net/ethernet/airoha/airoha_eth.c:167:\t\tairoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:168:\t\tairoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-169-\t} else {\ndrivers/net/ethernet/airoha/airoha_eth.c:170:\t\tairoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c:171:\t\tairoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port);\ndrivers/net/ethernet/airoha/airoha_eth.c-172-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-176-\ndrivers/net/ethernet/airoha/airoha_eth.c:177:static void airoha_fe_maccr_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-178-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-181-\tfor (p = 1; p \u003c= ARRAY_SIZE(eth-\u003eports); p++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:182:\t\tairoha_fe_set(eth, REG_GDM_FWD_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-183-\t\t\t      GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-184-\t\t\t      GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:185:\t\tairoha_fe_rmw(eth, REG_GDM_LEN_CFG(p),\ndrivers/net/ethernet/airoha/airoha_eth.c-186-\t\t\t      GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-190-\ndrivers/net/ethernet/airoha/airoha_eth.c:191:\tairoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-192-\t\t      FIELD_PREP(CDM_VLAN_MASK, 0x8100));\ndrivers/net/ethernet/airoha/airoha_eth.c-193-\ndrivers/net/ethernet/airoha/airoha_eth.c:194:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD);\ndrivers/net/ethernet/airoha/airoha_eth.c-195-}\ndrivers/net/ethernet/airoha/airoha_eth.c-196-\ndrivers/net/ethernet/airoha/airoha_eth.c:197:static void airoha_fe_vip_setup(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-198-{\ndrivers/net/ethernet/airoha/airoha_eth.c:199:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC);\ndrivers/net/ethernet/airoha/airoha_eth.c:200:\tairoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-201-\ndrivers/net/ethernet/airoha/airoha_eth.c:202:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:203:\tairoha_fe_wr(eth, REG_FE_VIP_EN(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-204-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-206-\ndrivers/net/ethernet/airoha/airoha_eth.c:207:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP);\ndrivers/net/ethernet/airoha/airoha_eth.c:208:\tairoha_fe_wr(eth, REG_FE_VIP_EN(6),\ndrivers/net/ethernet/airoha/airoha_eth.c-209-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-211-\ndrivers/net/ethernet/airoha/airoha_eth.c:212:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:213:\tairoha_fe_wr(eth, REG_FE_VIP_EN(7),\ndrivers/net/ethernet/airoha/airoha_eth.c-214-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-217-\t/* BOOTP (0x43) */\ndrivers/net/ethernet/airoha/airoha_eth.c:218:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43);\ndrivers/net/ethernet/airoha/airoha_eth.c:219:\tairoha_fe_wr(eth, REG_FE_VIP_EN(8),\ndrivers/net/ethernet/airoha/airoha_eth.c-220-\t\t     PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-223-\t/* BOOTP (0x44) */\ndrivers/net/ethernet/airoha/airoha_eth.c:224:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44);\ndrivers/net/ethernet/airoha/airoha_eth.c:225:\tairoha_fe_wr(eth, REG_FE_VIP_EN(9),\ndrivers/net/ethernet/airoha/airoha_eth.c-226-\t\t     PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-229-\t/* ISAKMP */\ndrivers/net/ethernet/airoha/airoha_eth.c:230:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4);\ndrivers/net/ethernet/airoha/airoha_eth.c:231:\tairoha_fe_wr(eth, REG_FE_VIP_EN(10),\ndrivers/net/ethernet/airoha/airoha_eth.c-232-\t\t     PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-234-\ndrivers/net/ethernet/airoha/airoha_eth.c:235:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP);\ndrivers/net/ethernet/airoha/airoha_eth.c:236:\tairoha_fe_wr(eth, REG_FE_VIP_EN(11),\ndrivers/net/ethernet/airoha/airoha_eth.c-237-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-240-\t/* DHCPv6 */\ndrivers/net/ethernet/airoha/airoha_eth.c:241:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223);\ndrivers/net/ethernet/airoha/airoha_eth.c:242:\tairoha_fe_wr(eth, REG_FE_VIP_EN(12),\ndrivers/net/ethernet/airoha/airoha_eth.c-243-\t\t     PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-245-\ndrivers/net/ethernet/airoha/airoha_eth.c:246:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP);\ndrivers/net/ethernet/airoha/airoha_eth.c:247:\tairoha_fe_wr(eth, REG_FE_VIP_EN(19),\ndrivers/net/ethernet/airoha/airoha_eth.c-248-\t\t     PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-251-\t/* ETH-\u003eETH_P_1905 (0x893a) */\ndrivers/net/ethernet/airoha/airoha_eth.c:252:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a);\ndrivers/net/ethernet/airoha/airoha_eth.c:253:\tairoha_fe_wr(eth, REG_FE_VIP_EN(20),\ndrivers/net/ethernet/airoha/airoha_eth.c-254-\t\t     PATN_FCPU_EN_MASK | PATN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-255-\ndrivers/net/ethernet/airoha/airoha_eth.c:256:\tairoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP);\ndrivers/net/ethernet/airoha/airoha_eth.c:257:\tairoha_fe_wr(eth, REG_FE_VIP_EN(21),\ndrivers/net/ethernet/airoha/airoha_eth.c-258-\t\t     PATN_FCPU_EN_MASK | PATN_EN_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-260-\ndrivers/net/ethernet/airoha/airoha_eth.c:261:static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-262-\t\t\t\t\t     u32 port, u32 queue)\ndrivers/net/ethernet/airoha/airoha_eth.c-263-{\ndrivers/net/ethernet/airoha/airoha_eth.c:264:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-265-\t\t      PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-268-\ndrivers/net/ethernet/airoha/airoha_eth.c:269:\treturn airoha_fe_get(eth, REG_FE_PSE_QUEUE_CFG_VAL,\ndrivers/net/ethernet/airoha/airoha_eth.c-270-\t\t\t     PSE_CFG_OQ_RSV_MASK);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-272-\ndrivers/net/ethernet/airoha/airoha_eth.c:273:static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-274-\t\t\t\t\t      u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-275-{\ndrivers/net/ethernet/airoha/airoha_eth.c:276:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-277-\t\t      FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val));\ndrivers/net/ethernet/airoha/airoha_eth.c:278:\tairoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,\ndrivers/net/ethernet/airoha/airoha_eth.c-279-\t\t      PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-285-\ndrivers/net/ethernet/airoha/airoha_eth.c:286:static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-287-{\ndrivers/net/ethernet/airoha/airoha_eth.c:288:\treturn airoha_fe_get(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-289-}\ndrivers/net/ethernet/airoha/airoha_eth.c-290-\ndrivers/net/ethernet/airoha/airoha_eth.c:291:static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,\ndrivers/net/ethernet/airoha/airoha_eth.c-292-\t\t\t\t    u32 port, u32 queue, u32 val)\ndrivers/net/ethernet/airoha/airoha_eth.c-293-{\ndrivers/net/ethernet/airoha/airoha_eth.c:294:\tu32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);\ndrivers/net/ethernet/airoha/airoha_eth.c-295-\tu32 tmp, all_rsv, fq_limit;\ndrivers/net/ethernet/airoha/airoha_eth.c-296-\ndrivers/net/ethernet/airoha/airoha_eth.c:297:\tairoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);\ndrivers/net/ethernet/airoha/airoha_eth.c-298-\ndrivers/net/ethernet/airoha/airoha_eth.c-299-\t/* modify all rsv */\ndrivers/net/ethernet/airoha/airoha_eth.c:300:\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-301-\tall_rsv += (val - orig_val);\ndrivers/net/ethernet/airoha/airoha_eth.c:302:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-303-\t\t      FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-305-\t/* modify hthd */\ndrivers/net/ethernet/airoha/airoha_eth.c:306:\tfq_limit = airoha_fe_get(eth, PSE_FQ_CFG, PSE_FQ_LIMIT_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-307-\ttmp = fq_limit - all_rsv - 0x20;\ndrivers/net/ethernet/airoha/airoha_eth.c:308:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-309-\t\t      PSE_SHARE_USED_HTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-312-\ttmp = fq_limit - all_rsv - 0x100;\ndrivers/net/ethernet/airoha/airoha_eth.c:313:\tairoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,\ndrivers/net/ethernet/airoha/airoha_eth.c-314-\t\t      PSE_SHARE_USED_MTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-316-\ttmp = (3 * tmp) \u003e\u003e 2;\ndrivers/net/ethernet/airoha/airoha_eth.c:317:\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET,\ndrivers/net/ethernet/airoha/airoha_eth.c-318-\t\t      PSE_SHARE_USED_LTHD_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-323-\ndrivers/net/ethernet/airoha/airoha_eth.c:324:static void airoha_fe_pse_ports_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-325-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-340-\ndrivers/net/ethernet/airoha/airoha_eth.c:341:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-342-\t\tu32 all_rsv;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-344-\t\t/* hw misses PPE2 oq rsv */\ndrivers/net/ethernet/airoha/airoha_eth.c:345:\t\tall_rsv = airoha_fe_get_pse_all_rsv(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-346-\t\tall_rsv += PSE_RSV_PAGES *\ndrivers/net/ethernet/airoha/airoha_eth.c-347-\t\t\t   pse_port_num_queues[FE_PSE_PORT_PPE2];\ndrivers/net/ethernet/airoha/airoha_eth.c:348:\t\tairoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-349-\t\t\t      FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-353-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:354:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-355-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-357-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM1]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:358:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-359-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-361-\tfor (q = 6; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:362:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-363-\t/* GDM3 */\ndrivers/net/ethernet/airoha/airoha_eth.c-364-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM3]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:365:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-366-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-369-\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE1] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:370:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-371-\t\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c-372-\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:373:\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-374-\t}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-376-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM2]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:377:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-378-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-380-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:381:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0);\ndrivers/net/ethernet/airoha/airoha_eth.c-382-\t/* CDM4 */\ndrivers/net/ethernet/airoha/airoha_eth.c-383-\tfor (q = 4; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:384:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-385-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\ndrivers/net/ethernet/airoha/airoha_eth.c:386:\tif (airoha_ppe_is_enabled(eth, 1)) {\ndrivers/net/ethernet/airoha/airoha_eth.c-387-\t\t/* PPE2 */\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-389-\t\t\tif (q \u003c pse_port_num_queues[FE_PSE_PORT_PPE2] / 2)\ndrivers/net/ethernet/airoha/airoha_eth.c:390:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-391-\t\t\t\t\t\t\t q,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-393-\t\t\telse\ndrivers/net/ethernet/airoha/airoha_eth.c:394:\t\t\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,\ndrivers/net/ethernet/airoha/airoha_eth.c-395-\t\t\t\t\t\t\t q, 0);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-399-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:400:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-401-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-403-\tfor (q = 0; q \u003c pse_port_num_queues[FE_PSE_PORT_CDM5]; q++)\ndrivers/net/ethernet/airoha/airoha_eth.c:404:\t\tairoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q,\ndrivers/net/ethernet/airoha/airoha_eth.c-405-\t\t\t\t\t PSE_QUEUE_RSV_PAGES);\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-407-\ndrivers/net/ethernet/airoha/airoha_eth.c:408:static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-409-{\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-415-\ndrivers/net/ethernet/airoha/airoha_eth.c:416:\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-417-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-419-\t\t      MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:420:\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:421:\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-422-\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-428-\t\tfor (j = 0; j \u003c AIROHA_FE_MC_MAX_VLAN_PORT; j++) {\ndrivers/net/ethernet/airoha/airoha_eth.c:429:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);\ndrivers/net/ethernet/airoha/airoha_eth.c-430-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-433-\t\t\t      MC_VLAN_CFG_RW_MASK;\ndrivers/net/ethernet/airoha/airoha_eth.c:434:\t\t\tairoha_fe_wr(eth, REG_MC_VLAN_CFG, val);\ndrivers/net/ethernet/airoha/airoha_eth.c:435:\t\t\terr = read_poll_timeout(airoha_fe_rr, val,\ndrivers/net/ethernet/airoha/airoha_eth.c-436-\t\t\t\t\t\tval \u0026 MC_VLAN_CFG_CMD_DONE_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-447-\ndrivers/net/ethernet/airoha/airoha_eth.c:448:static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-449-{\ndrivers/net/ethernet/airoha/airoha_eth.c-450-\t/* CDM1_CRSN_QSEL */\ndrivers/net/ethernet/airoha/airoha_eth.c:451:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-452-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-454-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:455:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-456-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-458-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:459:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-460-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-462-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:463:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-464-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-466-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:467:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-468-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-471-\t/* CDM2_CRSN_QSEL */\ndrivers/net/ethernet/airoha/airoha_eth.c:472:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-473-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_08),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-475-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:476:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-477-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_21),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-479-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:480:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-481-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_22),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-483-\t\t\t\t CDM_CRSN_QSEL_Q1));\ndrivers/net/ethernet/airoha/airoha_eth.c:484:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-485-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_24),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-487-\t\t\t\t CDM_CRSN_QSEL_Q6));\ndrivers/net/ethernet/airoha/airoha_eth.c:488:\tairoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 \u003e\u003e 2),\ndrivers/net/ethernet/airoha/airoha_eth.c-489-\t\t      CDM_CRSN_QSEL_REASON_MASK(CRSN_25),\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-493-\ndrivers/net/ethernet/airoha/airoha_eth.c:494:static int airoha_fe_init(struct airoha_eth *eth)\ndrivers/net/ethernet/airoha/airoha_eth.c-495-{\ndrivers/net/ethernet/airoha/airoha_eth.c:496:\tairoha_fe_maccr_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-497-\ndrivers/net/ethernet/airoha/airoha_eth.c-498-\t/* PSE IQ reserve */\ndrivers/net/ethernet/airoha/airoha_eth.c:499:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-500-\t\t      FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10));\ndrivers/net/ethernet/airoha/airoha_eth.c:501:\tairoha_fe_rmw(eth, REG_PSE_IQ_REV2,\ndrivers/net/ethernet/airoha/airoha_eth.c-502-\t\t      PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-506-\t/* enable FE copy engine for KA/DPI */\ndrivers/net/ethernet/airoha/airoha_eth.c:507:\tairoha_fe_wr(eth, REG_FE_PCE_CFG, PCE_DPI_EN_MASK | PCE_KA_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-508-\t/* set vip queue selection to ring 1 */\ndrivers/net/ethernet/airoha/airoha_eth.c:509:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-510-\t\t      FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c:511:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-512-\t\t      FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4));\ndrivers/net/ethernet/airoha/airoha_eth.c-513-\t/* set GDM4 source interface offset to 8 */\ndrivers/net/ethernet/airoha/airoha_eth.c:514:\tairoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4),\ndrivers/net/ethernet/airoha/airoha_eth.c-515-\t\t      GDM_SPORT_OFF2_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-522-\t/* set PSE Page as 128B */\ndrivers/net/ethernet/airoha/airoha_eth.c:523:\tairoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-524-\t\t      FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-526-\t\t      FE_DMA_GLO_PG_SZ_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:527:\tairoha_fe_wr(eth, REG_FE_RST_GLO_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-528-\t\t     FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-534-\t */\ndrivers/net/ethernet/airoha/airoha_eth.c:535:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:536:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c:537:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4));\ndrivers/net/ethernet/airoha/airoha_eth.c:538:\tairoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28));\ndrivers/net/ethernet/airoha/airoha_eth.c-539-\ndrivers/net/ethernet/airoha/airoha_eth.c:540:\tairoha_fe_vip_setup(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c:541:\tairoha_fe_pse_ports_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-542-\ndrivers/net/ethernet/airoha/airoha_eth.c:543:\tairoha_fe_set(eth, REG_GDM_MISC_CFG,\ndrivers/net/ethernet/airoha/airoha_eth.c-544-\t\t      GDM2_RDM_ACK_WAIT_PREF_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-545-\t\t      GDM2_CHN_VLD_MODE_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:546:\tairoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK,\ndrivers/net/ethernet/airoha/airoha_eth.c-547-\t\t      FIELD_PREP(CDM_OAM_QSEL_MASK, 15));\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-550-\t/* NPU Core-3, NPU Bridge Channel-3 */\ndrivers/net/ethernet/airoha/airoha_eth.c:551:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-552-\t\t      IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-555-\t/* QDMA LAN, RX Ring-22 */\ndrivers/net/ethernet/airoha/airoha_eth.c:556:\tairoha_fe_rmw(eth, REG_IP_FRAG_FP,\ndrivers/net/ethernet/airoha/airoha_eth.c-557-\t\t      IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-560-\ndrivers/net/ethernet/airoha/airoha_eth.c:561:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:562:\tairoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-563-\ndrivers/net/ethernet/airoha/airoha_eth.c-564-\t/* Enable split for MIB counters for GDM3 and GDM4 */\ndrivers/net/ethernet/airoha/airoha_eth.c:565:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM3_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-566-\t\t      FE_GDM_TX_MIB_SPLIT_EN_MASK |\ndrivers/net/ethernet/airoha/airoha_eth.c-567-\t\t      FE_GDM_RX_MIB_SPLIT_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:568:\tairoha_fe_set(eth, REG_FE_GDM_MIB_CFG(AIROHA_GDM4_IDX),\ndrivers/net/ethernet/airoha/airoha_eth.c-569-\t\t      FE_GDM_TX_MIB_SPLIT_EN_MASK |\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-571-\ndrivers/net/ethernet/airoha/airoha_eth.c:572:\tairoha_fe_crsn_qsel_init(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-573-\ndrivers/net/ethernet/airoha/airoha_eth.c:574:\tairoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c:575:\tairoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-576-\ndrivers/net/ethernet/airoha/airoha_eth.c-577-\t/* default aging mode for mbi unlock issue */\ndrivers/net/ethernet/airoha/airoha_eth.c:578:\tairoha_fe_rmw(eth, REG_GDM_CHN_RLS(2),\ndrivers/net/ethernet/airoha/airoha_eth.c-579-\t\t      MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-583-\t/* disable IFC by default */\ndrivers/net/ethernet/airoha/airoha_eth.c:584:\tairoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-585-\ndrivers/net/ethernet/airoha/airoha_eth.c-586-\t/* enable 1:N vlan action, init vlan table */\ndrivers/net/ethernet/airoha/airoha_eth.c:587:\tairoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK);\ndrivers/net/ethernet/airoha/airoha_eth.c-588-\ndrivers/net/ethernet/airoha/airoha_eth.c:589:\treturn airoha_fe_mc_vlan_clear(eth);\ndrivers/net/ethernet/airoha/airoha_eth.c-590-}\ndrivers/net/ethernet/airoha/airoha_eth.c-591-\ndrivers/net/ethernet/airoha/airoha_eth.c:592:static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)\ndrivers/net/ethernet/airoha/airoha_eth.c-593-{\ndrivers/net/ethernet/airoha/airoha_eth.c:594:\tstruct airoha_qdma *qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c-595-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-598-\twhile (q-\u003equeued \u003c q-\u003endesc - 1) {\ndrivers/net/ethernet/airoha/airoha_eth.c:599:\t\tstruct airoha_queue_entry *e = \u0026q-\u003eentry[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c:600:\t\tstruct airoha_qdma_desc *desc = \u0026q-\u003edesc[q-\u003ehead];\ndrivers/net/ethernet/airoha/airoha_eth.c-601-\t\tstruct page *page;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-630-\tif (nframes)\ndrivers/net/ethernet/airoha/airoha_eth.c:631:\t\tairoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid),\ndrivers/net/ethernet/airoha/airoha_eth.c-632-\t\t\t\tRX_RING_CPU_IDX_MASK,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-637-\ndrivers/net/ethernet/airoha/airoha_eth.c:638:static struct airoha_gdm_dev *\ndrivers/net/ethernet/airoha/airoha_eth.c:639:airoha_qdma_get_gdm_dev(struct airoha_eth *eth, struct airoha_qdma_desc *desc)\ndrivers/net/ethernet/airoha/airoha_eth.c-640-{\ndrivers/net/ethernet/airoha/airoha_eth.c:641:\tstruct airoha_gdm_port *port;\ndrivers/net/ethernet/airoha/airoha_eth.c-642-\tu16 p, d;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-659-\ndrivers/net/ethernet/airoha/airoha_eth.c:660:static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)\ndrivers/net/ethernet/airoha/airoha_eth.c-661-{\ndrivers/net/ethernet/airoha/airoha_eth.c-662-\tenum dma_data_direction dir = page_pool_get_dma_dir(q-\u003epage_pool);\ndrivers/net/ethernet/airoha/airoha_eth.c:663:\tstruct airoha_qdma *qdma = q-\u003eqdma;\ndrivers/net/ethernet/airoha/airoha_eth.c:664:\tstruct airoha_eth *eth = qdma-\u003eeth;\ndrivers/net/ethernet/airoha/airoha_eth.c-665-\tint qid = q - \u0026qdma-\u003eq_rx[0];\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-668-\twhile (done \u003c budget) {\ndrivers/net/ethernet/airoha/airoha_eth.c:669:\t\tstruct airoha_queue_entry *e = \u0026q-\u003eentry[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c:670:\t\tstruct airoha_qdma_desc *desc = \u0026q-\u003edesc[q-\u003etail];\ndrivers/net/ethernet/airoha/airoha_eth.c-671-\t\tu32 hash, reason, msg1, desc_ctrl;\ndrivers/net/ethernet/airoha/airoha_eth.c:672:\t\tstruct airoha_gdm_dev *dev;\ndrivers/net/ethernet/airoha/airoha_eth.c-673-\t\tstruct net_device *netdev;\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-694-\ndrivers/net/ethernet/airoha/airoha_eth.c:695:\t\tdev = airoha_qdma_get_gdm_dev(eth, desc);\ndrivers/net/ethernet/airoha/airoha_eth.c-696-\t\tif (IS_ERR(dev))\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-728-\t\tif (netdev_uses_dsa(netdev)) {\ndrivers/net/ethernet/airoha/airoha_eth.c:729:\t\t\tstruct airoha_gdm_port *port = dev-\u003eport;\ndrivers/net/ethernet/airoha/airoha_eth.c-730-\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-752-\t\tif (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)\ndrivers/net/ethernet/airoha/airoha_eth.c:753:\t\t\tairoha_ppe_check_skb(\u0026eth-\u003eppe-\u003edev, q-\u003eskb, hash,\n\n"
}

gemini-3.7-flash

null

null

							input: 19979
							output: 35
							thoughts: 13
						

Here's my attempt at summarizing the thought process, tailored for an expert audience:

**Analyzing the NET_AIROHA Kconfig**

Alright, let's dive into the Kconfig for NET_AIROHA. I'm going to take a look at this and see how the configuration options are laid out. I need to understand what features are being exposed, how they're dependent on other options, and any potential implications for the overall network stack. I'll be looking for any signs of vendor-specific quirks or optimizations, unusual dependencies, or anything that might require deeper investigation for integration or customization. My key areas of focus will include the device driver options, any network protocol support, security features, and how they relate to the target Airoha SoC's capabilities. I’ll also be searching for any potential conflicts or areas where performance tuning might be necessary.

{
  "Expression": "NET_AIROHA",
  "PathPrefix": "drivers/net/ethernet/airoha/"
}

{
  "Output": "drivers/net/ethernet/airoha/Kconfig=8=if NET_VENDOR_AIROHA\ndrivers/net/ethernet/airoha/Kconfig-9-\ndrivers/net/ethernet/airoha/Kconfig:10:config NET_AIROHA_NPU\ndrivers/net/ethernet/airoha/Kconfig-11-\ttristate \"Airoha NPU support\"\n--\ndrivers/net/ethernet/airoha/Kconfig-17-\ndrivers/net/ethernet/airoha/Kconfig:18:config NET_AIROHA\ndrivers/net/ethernet/airoha/Kconfig-19-\ttristate \"Airoha SoC Gigabit Ethernet support\"\ndrivers/net/ethernet/airoha/Kconfig-20-\tdepends on NET_DSA || !NET_DSA\ndrivers/net/ethernet/airoha/Kconfig:21:\tselect NET_AIROHA_NPU\ndrivers/net/ethernet/airoha/Kconfig-22-\tselect PAGE_POOL\n--\ndrivers/net/ethernet/airoha/Kconfig-26-\ndrivers/net/ethernet/airoha/Kconfig:27:config NET_AIROHA_FLOW_STATS\ndrivers/net/ethernet/airoha/Kconfig-28-\tdefault y\ndrivers/net/ethernet/airoha/Kconfig-29-\tbool \"Airoha flow stats\"\ndrivers/net/ethernet/airoha/Kconfig:30:\tdepends on NET_AIROHA \u0026\u0026 NET_AIROHA_NPU\ndrivers/net/ethernet/airoha/Kconfig-31-\thelp\n--\ndrivers/net/ethernet/airoha/Makefile-5-\ndrivers/net/ethernet/airoha/Makefile:6:obj-$(CONFIG_NET_AIROHA) += airoha-eth.o\ndrivers/net/ethernet/airoha/Makefile-7-airoha-eth-y := airoha_eth.o airoha_ppe.o\ndrivers/net/ethernet/airoha/Makefile=8=airoha-eth-$(CONFIG_DEBUG_FS) += airoha_ppe_debugfs.o\ndrivers/net/ethernet/airoha/Makefile:9:obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o\n--\ndrivers/net/ethernet/airoha/airoha_ppe.c=38=static int airoha_ppe_get_num_stats_entries(struct airoha_ppe *ppe)\ndrivers/net/ethernet/airoha/airoha_ppe.c-39-{\ndrivers/net/ethernet/airoha/airoha_ppe.c:40:\tif (!IS_ENABLED(CONFIG_NET_AIROHA_FLOW_STATS))\ndrivers/net/ethernet/airoha/airoha_ppe.c-41-\t\treturn -EOPNOTSUPP;\n"
}

gemini-3.7-flash

null

null

							input: 20912
							output: 38
							thoughts: 41
						

Okay, let's dive into this. Here's how I'd approach this task, thinking through it step-by-step:

**Checking the Airoha Ethernet Driver Configuration**

Right, so I need to understand the Airoha Ethernet driver configuration. First, my instinct is to jump into `drivers/net/ethernet/airoha/Kconfig`. That's where I expect to find the core configuration options for the driver, and crucially, how `NET_VENDOR_AIROHA` is defined. Knowing that symbol is key. I need to know *if* it's even enabled and what its dependencies might be. Once I have that, I can determine the level of support this driver has at a glance.

Next, I need to understand what devices or buses the `airoha_eth` driver is designed to bind to. Is it PCI, SPI, USB, or something else entirely? The Kconfig likely will provide some hints, but I'll probably have to trace the code to be absolutely sure. This context is essential to understanding how the driver integrates into the system and what hardware it's intended to support. This is where I can start to develop a mental map of the driver's role in the networking landscape.

{
  "File": "drivers/net/ethernet/airoha/Kconfig",
  "FirstLine": 1,
  "LineCount": 40
}

{
  "Contents": "   1:\t# SPDX-License-Identifier: GPL-2.0-only\n   2:\tconfig NET_VENDOR_AIROHA\n   3:\t\tbool \"Airoha devices\"\n   4:\t\tdepends on ARCH_AIROHA || COMPILE_TEST\n   5:\t\thelp\n   6:\t\t  If you have a Airoha SoC with ethernet, say Y.\n   7:\t\n   8:\tif NET_VENDOR_AIROHA\n   9:\t\n  10:\tconfig NET_AIROHA_NPU\n  11:\t\ttristate \"Airoha NPU support\"\n  12:\t\tselect WANT_DEV_COREDUMP\n  13:\t\tselect REGMAP_MMIO\n  14:\t\thelp\n  15:\t\t  This driver supports Airoha Network Processor (NPU) available\n  16:\t\t  on the Airoha Soc family.\n  17:\t\n  18:\tconfig NET_AIROHA\n  19:\t\ttristate \"Airoha SoC Gigabit Ethernet support\"\n  20:\t\tdepends on NET_DSA || !NET_DSA\n  21:\t\tselect NET_AIROHA_NPU\n  22:\t\tselect PAGE_POOL\n  23:\t\thelp\n  24:\t\t  This driver supports the gigabit ethernet MACs in the\n  25:\t\t  Airoha SoC family.\n  26:\t\n  27:\tconfig NET_AIROHA_FLOW_STATS\n  28:\t\tdefault y\n  29:\t\tbool \"Airoha flow stats\"\n  30:\t\tdepends on NET_AIROHA \u0026\u0026 NET_AIROHA_NPU\n  31:\t\thelp\n  32:\t\t  Enable Airoha flowtable statistic counters.\n  33:\t\n  34:\tendif #NET_VENDOR_AIROHA\n"
}

gemini-3.7-flash

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null

							input: 21702
							output: 33
							thoughts: 48
						

**Analyzing the Airoha Ethernet Driver**

Okay, let's dive in. I need to figure out what `airoha_eth` is doing in this context. My initial hunch is that it's a platform driver tailored for an Airoha System-on-a-Chip. Time to confirm that. I'm going to quickly navigate over to `airoha_eth.c` and zero in on the familiar patterns of a platform driver: specifically, I'll be looking for `module_platform_driver` or just `platform_driver` to see if this aligns with my initial assessment. I'll need to check the codebase.

{
  "Expression": "platform_driver",
  "PathPrefix": "drivers/net/ethernet/airoha/"
}

{
  "Output": "drivers/net/ethernet/airoha/airoha_eth.c=3958=MODULE_DEVICE_TABLE(of, of_airoha_match);\ndrivers/net/ethernet/airoha/airoha_eth.c-3959-\ndrivers/net/ethernet/airoha/airoha_eth.c:3960:static struct platform_driver airoha_driver = {\ndrivers/net/ethernet/airoha/airoha_eth.c-3961-\t.probe = airoha_probe,\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3967-};\ndrivers/net/ethernet/airoha/airoha_eth.c:3968:module_platform_driver(airoha_driver);\ndrivers/net/ethernet/airoha/airoha_eth.c-3969-\n--\ndrivers/net/ethernet/airoha/airoha_npu.c=806=static void airoha_npu_remove(struct platform_device *pdev)\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-814-\ndrivers/net/ethernet/airoha/airoha_npu.c:815:static struct platform_driver airoha_npu_driver = {\ndrivers/net/ethernet/airoha/airoha_npu.c-816-\t.probe = airoha_npu_probe,\n--\ndrivers/net/ethernet/airoha/airoha_npu.c-822-};\ndrivers/net/ethernet/airoha/airoha_npu.c:823:module_platform_driver(airoha_npu_driver);\ndrivers/net/ethernet/airoha/airoha_npu.c-824-\n"
}

gemini-3.7-flash

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null

							input: 22373
							output: 36
							thoughts: 42
						

Here's my summary, as the expert:

**Investigating the Airoha Gigabit Ethernet Driver**

Okay, so I'm looking at `airoha_driver`. Right, that's the platform driver specifically designed for the Airoha SoC Gigabit Ethernet controller. The system identifies it using the Device Tree match string `of_airoha_match`. Alright, that's what I expect. I should check that `of_airoha_match` definition, just to be absolutely certain the system is correctly identifying the target hardware. Let me quickly examine that... it's the crucial link in the chain.

{
  "Expression": "of_airoha_match",
  "PathPrefix": "drivers/net/ethernet/airoha/"
}

{
  "Output": "drivers/net/ethernet/airoha/airoha_eth.c=3941=static const struct airoha_eth_soc_data an7583_soc_data = {\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3952-\ndrivers/net/ethernet/airoha/airoha_eth.c:3953:static const struct of_device_id of_airoha_match[] = {\ndrivers/net/ethernet/airoha/airoha_eth.c-3954-\t{ .compatible = \"airoha,en7581-eth\", .data = \u0026en7581_soc_data },\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3957-};\ndrivers/net/ethernet/airoha/airoha_eth.c:3958:MODULE_DEVICE_TABLE(of, of_airoha_match);\ndrivers/net/ethernet/airoha/airoha_eth.c-3959-\ndrivers/net/ethernet/airoha/airoha_eth.c=3960=static struct platform_driver airoha_driver = {\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-3964-\t\t.name = KBUILD_MODNAME,\ndrivers/net/ethernet/airoha/airoha_eth.c:3965:\t\t.of_match_table = of_airoha_match,\ndrivers/net/ethernet/airoha/airoha_eth.c-3966-\t},\n"
}

gemini-3.7-flash

null

null

							input: 22977
							output: 97
							thoughts: 613
						

**My Assessment of the Airoha Ethernet Driver Patch**

Okay, let's break this down. This patch is for an SoC-specific Ethernet driver, specifically the Airoha EN7581. The instructions are clear: if the code change can't be reached in a standard virtualized environment, we should return `WorthFuzzing=false`.

The critical question here is whether or not this driver, designed for an Airoha ARM SoC, is accessible in environments like QEMU or GCE. My understanding is that the Airoha EN7581 is a specialized piece of hardware, a platform driver dependent on specific SoC device tree configurations, hardware memory-mapped I/O, clocks, resets, etc. It's not something emulated in the standard virtualized environments. It needs the physical SoC. So, no, it's not reachable.

I've confirmed my understanding. There's no emulation or mock platform device for this Airoha hardware in the kernel or QEMU. It's a real-world SoC, part of the MediaTek group.

Therefore, the code path being modified is, by definition, unreachable in a virtualized fuzzing environment. The condition is met for `WorthFuzzing` to be `false`.

Let's quickly check the required output format for the `set-results` call to make sure I'm doing it right.

Here's my `set-results` data:

*   `WorthFuzzing`: `false`
*   `FocusSymbols`: `[]` (empty list, as nothing needs special focus)
*   `EnableConfigs`: `[]` (also empty, no configurations needed)
*   `Reasoning`: "The patch modifies the Airoha SoC Gigabit Ethernet driver (`drivers/net/ethernet/airoha/airoha_eth.c`), which is a platform driver for Airoha (EN7581) SoCs requiring physical hardware not emulated in standard virtualized environments like QEMU or GCE."

Now, let's call `set-results`. Done.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Airoha SoC Gigabit Ethernet driver (drivers/net/ethernet/airoha/), which is a platform driver specifically targeting Airoha SoCs (e.g., EN7581). This hardware cannot be reached or emulated in standard virtualized environments like QEMU or GCE.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies the Airoha SoC Gigabit Ethernet driver (drivers/net/ethernet/airoha/), which is a platform driver specifically targeting Airoha SoCs (e.g., EN7581). This hardware cannot be reached or emulated in standard virtualized environments like QEMU or GCE.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

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