AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/08/24 06:24	flow	patch-triage	0m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The patch series only adds device tree bindings and device tree source (DTS) files for a new RISC-V SoC (UltraRISC DP1000) and its associated boards. It does not contain any executable C code changes or modifications to kernel logic that can be fuzzed.", "WorthFuzzing": false }
1/1	2026/08/24 06:24	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit abedfd5586c0d4e72334bde3b92597c566cb440f\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Mon Aug 24 06:24:01 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml\nindex 0a30a455b0ee5..f7b5891f41ae9 100644\n--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml\n+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml\n@@ -27,6 +27,7 @@ properties:\n - enum:\n - altr,agilex5-axi-dma\n - sophgo,cv1800b-axi-dma\n+ - ultrarisc,dp1000-axi-dma\n - const: snps,axi-dma-1.01a\n \n reg:\ndiff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml\nindex 467bdcbb85389..eee21ca8d7eda 100644\n--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml\n+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml\n@@ -44,6 +44,7 @@ properties:\n - mscc,ocelot-i2c\n - sophgo,sg2044-i2c\n - thead,th1520-i2c\n+ - ultrarisc,dp1000-i2c\n - const: snps,designware-i2c\n \n reg:\ndiff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml\nindex 2449311c6d28e..2ed4564ae99d7 100644\n--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml\n+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml\n@@ -119,6 +119,7 @@ properties:\n - starfive,jh7110-dwmac\n - tesla,fsd-ethqos\n - thead,th1520-gmac\n+ - ultrarisc,dp1000-gmac\n \n reg:\n minItems: 1\ndiff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml\nindex 5feeb2203050a..85adf72899c9d 100644\n--- a/Documentation/devicetree/bindings/riscv/cpus.yaml\n+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml\n@@ -67,6 +67,7 @@ properties:\n - thead,c908\n - thead,c910\n - thead,c920\n+ - ultrarisc,cp100\n - const: riscv\n - items:\n - enum:\n@@ -117,8 +118,8 @@ properties:\n $ref: /schemas/types.yaml#/definitions/uint32\n description:\n VLEN/8, the vector register length in bytes. This property is required on\n- thead systems where the vector register length is not identical on all harts, or\n- the vlenb CSR is not available.\n+ thead systems where the vector register length is not identical on all\n+ harts, or the vlenb CSR is not available.\n \n # RISC-V has multiple properties for cache op block sizes as the sizes\n # differ between individual CBO extensions\n@@ -151,8 +152,8 @@ anyOf:\n - riscv,isa-base\n \n dependencies:\n- riscv,isa-base: [ \"riscv,isa-extensions\" ]\n- riscv,isa-extensions: [ \"riscv,isa-base\" ]\n+ riscv,isa-base: [\"riscv,isa-extensions\"]\n+ riscv,isa-extensions: [\"riscv,isa-base\"]\n \n required:\n - interrupt-controller\ndiff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml\nnew file mode 100644\nindex 0000000000000..a51e63dbeca33\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml\n@@ -0,0 +1,27 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: UltraRISC SoC-based boards\n+\n+maintainers:\n+ - Jia Wang \u003cwangjia@ultrarisc.com\u003e\n+\n+description:\n+ UltraRISC DP1000 SoC-based boards\n+\n+properties:\n+ $nodename:\n+ const: '/'\n+ compatible:\n+ oneOf:\n+ - items:\n+ - enum:\n+ - shenrongda,m0\n+ - milkv,titan\n+ - const: ultrarisc,dp1000\n+\n+additionalProperties: true\n+...\ndiff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml\nindex 1e70c6804d5d1..896205329d7e5 100644\n--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml\n+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml\n@@ -63,6 +63,7 @@ properties:\n - mscc,jaguar2-spi\n - sophgo,sg2042-spi\n - thead,th1520-spi\n+ - ultrarisc,dp1000-spi\n - const: snps,dw-apb-ssi\n - description: Vendor controllers compatible with v1.01a\n items:\ndiff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml\nindex 3673836e14dee..878f267d089b5 100644\n--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml\n+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml\n@@ -40,6 +40,7 @@ properties:\n - starfive,jh8100-clint # StarFive JH8100\n - starfive,jhb100-clint # StarFive JHB100\n - tenstorrent,blackhole-clint # Tenstorrent Blackhole\n+ - ultrarisc,dp1000-clint # UltraRISC DP1000\n - const: sifive,clint0 # SiFive CLINT v0 IP block\n - items:\n - {}\ndiff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml\nindex 6780b651acf80..61cd5e625a232 100644\n--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml\n+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml\n@@ -1505,6 +1505,8 @@ patternProperties:\n description: SGX Sensortech\n \"^sharp,.\":\n description: Sharp Corporation\n+ \"^shenrongda,.\":\n+ description: Shenzhen Rongda Computer Co., Ltd.\n \"^shift,.\":\n description: SHIFT GmbH\n \"^shimafuji,.\":\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex e3f4e0fcdb3a7..a8f3c256bda24 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -23517,6 +23517,14 @@ F:\tinclude/dt-bindings/power/thead,th1520-power.h\n F:\tinclude/dt-bindings/reset/thead,th1520-reset.h\n F:\tinclude/linux/firmware/thead/thead,th1520-aon.h\n \n+RISC-V ULTRARISC SoC SUPPORT\n+M:\tJia Wang \u003cwangjia@ultrarisc.com\u003e\n+L:\tlinux-riscv@lists.infradead.org\n+S:\tSupported\n+T:\tgit https://github.com/ultrarisc/linux.git\n+F:\tDocumentation/devicetree/bindings/riscv/ultrarisc.yaml\n+F:\tarch/riscv/boot/dts/ultrarisc/\n+\n RNBD BLOCK DRIVERS\n M:\tMd. Haris Iqbal \u003charis.iqbal@ionos.com\u003e\n M:\tJack Wang \u003cjinpu.wang@ionos.com\u003e\ndiff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile\nindex 69d8751fb17c8..7028829742518 100644\n--- a/arch/riscv/boot/dts/Makefile\n+++ b/arch/riscv/boot/dts/Makefile\n@@ -12,3 +12,4 @@ subdir-y += spacemit\n subdir-y += starfive\n subdir-y += tenstorrent\n subdir-y += thead\n+subdir-y += ultrarisc\ndiff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile\nnew file mode 100644\nindex 0000000000000..dfd15c064d078\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/Makefile\n@@ -0,0 +1,3 @@\n+# SPDX-License-Identifier: GPL-2.0\n+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb\n+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi\nnew file mode 100644\nindex 0000000000000..7a812e40a2496\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi\n@@ -0,0 +1,108 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/\n+ Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ /\n+\n+#include \"dp1000.dtsi\"\n+#include \"dp1000-pinctrl.h\"\n+\n+\u0026pinctrl {\n+\ti2c0_pins: i2c0-pins {\n+\t\tpins = \u003cPA12 PA13\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c1_pins: i2c1-pins {\n+\t\tpins = \u003cPB6 PB7\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c2_pins: i2c2-pins {\n+\t\tpins = \u003cPC0 PC1\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c3_pins: i2c3-pins {\n+\t\tpins = \u003cPC2 PC3\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tio_pins: io-pins {\n+\t\tpins = \u003cPA10 PA15 PB0 PB1 PB2 PD6 PD7\u003e;\n+\t\tfunction = \"gpio\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tgpio_keys_pins: gpio-keys-pins {\n+\t\tpins = \u003cPA4 PA11 PA14\u003e;\n+\t\tfunction = \"gpio\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tmux_dcdc_i2c_pins: mux-dcdc-i2c-pins {\n+\t\tpins = \u003cPA5\u003e;\n+\t\tfunction = \"gpio\";\n+\t};\n+\n+\tmux_i2c3_pins: mux-i2c3-pins {\n+\t\tpins = \u003cPA6\u003e;\n+\t\tfunction = \"gpio\";\n+\t};\n+\n+\tmux_uart0_pins: mux-uart0-pins {\n+\t\tpins = \u003cPA7\u003e;\n+\t\tfunction = \"gpio\";\n+\t};\n+\n+\tspi0_pins: spi0-pins {\n+\t\tpins = \u003cPD0 PD1 PD2 PD3 PD4 PD5\u003e;\n+\t\tfunction = \"spi\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tspi1_pins: spi1-pins {\n+\t\tpins = \u003cPA0 PA1 PA2 PA3\u003e;\n+\t\tfunction = \"spi\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart0_pins: uart0-pins {\n+\t\tpins = \u003cPA8 PA9\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart1_pins: uart1-pins {\n+\t\tpins = \u003cPB4 PB5\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart2_pins: uart2-pins {\n+\t\tpins = \u003cPC4 PC5\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart3_pins: uart3-pins {\n+\t\tpins = \u003cPC6 PC7\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+};\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts\nnew file mode 100644\nindex 0000000000000..f1a0efee3d746\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts\n@@ -0,0 +1,203 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ /\n+\n+#include \"dp1000-milkv-titan-pinctrl.dtsi\"\n+#include \u003cdt-bindings/gpio/gpio.h\u003e\n+#include \u003cdt-bindings/input/input.h\u003e\n+#include \u003cdt-bindings/input/gpio-keys.h\u003e\n+#include \u003cdt-bindings/interrupt-controller/irq.h\u003e\n+#include \u003cdt-bindings/leds/common.h\u003e\n+\n+/ {\n+\tmodel = \"Milk-V Titan\";\n+\tcompatible = \"milkv,titan\", \"ultrarisc,dp1000\";\n+\n+\taliases {\n+\t\tserial0 = \u0026uart0;\n+\t\tserial1 = \u0026uart1;\n+\t\tserial2 = \u0026uart2;\n+\t\tserial3 = \u0026uart3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = \u003c\u0026gpio_keys_pins\u003e;\n+\n+\t\tkey-wakeup-0 {\n+\t\t\tlabel = \"Wake-Up\";\n+\t\t\tgpios = \u003c\u0026gpio_a 14 GPIO_ACTIVE_LOW\u003e;\n+\t\t\tlinux,code = \u003cKEY_WAKEUP\u003e;\n+\t\t\tlinux,input-type = \u003cEV_KEY\u003e;\n+\t\t\tdebounce-interval = \u003c10\u003e;\n+\t\t\twakeup-source;\n+\t\t\twakeup-event-action = \u003cEV_ACT_ASSERTED\u003e;\n+\t\t};\n+\n+\t\tkey-wakeup-1 {\n+\t\t\tlabel = \"Power\";\n+\t\t\tgpios = \u003c\u0026gpio_a 11 GPIO_ACTIVE_LOW\u003e;\n+\t\t\tlinux,code = \u003cKEY_POWER\u003e;\n+\t\t\tlinux,input-type = \u003cEV_KEY\u003e;\n+\t\t\tdebounce-interval = \u003c10\u003e;\n+\t\t\twakeup-source;\n+\t\t\twakeup-event-action = \u003cEV_ACT_ASSERTED\u003e;\n+\t\t};\n+\n+\t\tkey-wakeup-2 {\n+\t\t\tlabel = \"Wake-Up-by-USB\";\n+\t\t\tinterrupts-extended = \u003c\u0026gpio_a 4 IRQ_TYPE_EDGE_FALLING\u003e;\n+\t\t\tlinux,code = \u003cKEY_WAKEUP\u003e;\n+\t\t\tlinux,input-type = \u003cEV_KEY\u003e;\n+\t\t\tdebounce-interval = \u003c10\u003e;\n+\t\t\twakeup-source;\n+\t\t};\n+\t};\n+};\n+\n+\u0026i2c0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c0_pins\u003e;\n+};\n+\n+\u0026i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c1_pins\u003e;\n+};\n+\n+\u0026i2c2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c2_pins\u003e;\n+\n+\trtc@68 {\n+\t\tcompatible = \"st,m41t11\";\n+\t\treg = \u003c0x68\u003e;\n+\t};\n+};\n+\n+\u0026i2c3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c3_pins\u003e;\n+};\n+\n+\u0026spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026spi0_pins\u003e;\n+};\n+\n+\u0026spi1 {\n+\tnum-cs = \u003c1\u003e;\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026spi1_pins\u003e;\n+};\n+\n+\u0026uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart0_pins\u003e;\n+};\n+\n+\u0026uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart1_pins\u003e;\n+};\n+\n+\u0026uart2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart2_pins\u003e;\n+};\n+\n+\u0026uart3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart3_pins\u003e;\n+};\n+\n+\u0026pcie_x16 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pcie_x4a {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pcie_x4b {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026gpio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026io_pins \u0026mux_dcdc_i2c_pins \u0026mux_i2c3_pins \u0026mux_uart0_pins\u003e;\n+};\n+\n+\u0026gpio_a {\n+\tdcdc-i2c-mux-hog {\n+\t\tgpio-hog;\n+\t\tgpios = \u003c5 GPIO_ACTIVE_HIGH\u003e;\n+\t\toutput-low;\n+\t\tline-name = \"dcdc-i2c-mux\";\n+\t};\n+\n+\ti2c3-mux-hog {\n+\t\tgpio-hog;\n+\t\tgpios = \u003c6 GPIO_ACTIVE_HIGH\u003e;\n+\t\toutput-low;\n+\t\tline-name = \"i2c3-mux\";\n+\t};\n+\n+\tuart0-mux-hog {\n+\t\tgpio-hog;\n+\t\tgpios = \u003c7 GPIO_ACTIVE_HIGH\u003e;\n+\t\toutput-high;\n+\t\tline-name = \"uart0-mux\";\n+\t};\n+};\n+\n+\u0026ethernet {\n+\tphy-handle = \u003c\u0026phy0\u003e;\n+\t/\n+\t * RTL8211F: board timing uses PHY strap delays; keep plain \"rgmii\".\n+\t * Enabling PHY internal delays via \"rgmii-id\" breaks Ethernet traffic.\n+\t /\n+\tphy-mode = \"rgmii\";\n+\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\n+\t\tphy0: phy@0 {\n+\t\t\treg = \u003c0\u003e;\n+\n+\t\t\tleds {\n+\t\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t\t#size-cells = \u003c0\u003e;\n+\n+\t\t\t\tled@1 {\n+\t\t\t\t\tlabel = \"eth-link\";\n+\t\t\t\t\treg = \u003c1\u003e;\n+\t\t\t\t\tcolor = \u003cLED_COLOR_ID_YELLOW\u003e;\n+\t\t\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\t\t\tdefault-state = \"keep\";\n+\t\t\t\t\tlinux,default-trigger = \"netdev\";\n+\t\t\t\t};\n+\n+\t\t\t\tled@2 {\n+\t\t\t\t\tlabel = \"eth-activity\";\n+\t\t\t\t\treg = \u003c2\u003e;\n+\t\t\t\t\tcolor = \u003cLED_COLOR_ID_GREEN\u003e;\n+\t\t\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\t\t\tdefault-state = \"keep\";\n+\t\t\t\t\tlinux,default-trigger = \"netdev\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h\nnew file mode 100644\nindex 0000000000000..4668e45d2335d\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h\n@@ -0,0 +1,63 @@\n+/ SPDX-License-Identifier: GPL-2.0-only /\n+/\n+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ /\n+\n+#ifndef _DP1000_PINCTRL_H\n+#define _DP1000_PINCTRL_H\n+\n+#define PA0\t\t0\n+#define PA1\t\t1\n+#define PA2\t\t2\n+#define PA3\t\t3\n+#define PA4\t\t4\n+#define PA5\t\t5\n+#define PA6\t\t6\n+#define PA7\t\t7\n+#define PA8\t\t8\n+#define PA9\t\t9\n+#define PA10\t\t10\n+#define PA11\t\t11\n+#define PA12\t\t12\n+#define PA13\t\t13\n+#define PA14\t\t14\n+#define PA15\t\t15\n+#define PB0\t\t16\n+#define PB1\t\t17\n+#define PB2\t\t18\n+#define PB3\t\t19\n+#define PB4\t\t20\n+#define PB5\t\t21\n+#define PB6\t\t22\n+#define PB7\t\t23\n+#define PC0\t\t24\n+#define PC1\t\t25\n+#define PC2\t\t26\n+#define PC3\t\t27\n+#define PC4\t\t28\n+#define PC5\t\t29\n+#define PC6\t\t30\n+#define PC7\t\t31\n+#define PD0\t\t32\n+#define PD1\t\t33\n+#define PD2\t\t34\n+#define PD3\t\t35\n+#define PD4\t\t36\n+#define PD5\t\t37\n+#define PD6\t\t38\n+#define PD7\t\t39\n+#define LPC0\t\t40\n+#define LPC1\t\t41\n+#define LPC2\t\t42\n+#define LPC3\t\t43\n+#define LPC4\t\t44\n+#define LPC5\t\t45\n+#define LPC6\t\t46\n+#define LPC7\t\t47\n+#define LPC8\t\t48\n+#define LPC9\t\t49\n+#define LPC10\t\t50\n+#define LPC11\t\t51\n+#define LPC12\t\t52\n+\n+#endif / _DP1000_PINCTRL_H /\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi\nnew file mode 100644\nindex 0000000000000..ab927c6cd6146\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi\n@@ -0,0 +1,79 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ /\n+\n+#include \"dp1000.dtsi\"\n+#include \"dp1000-pinctrl.h\"\n+\n+\u0026pinctrl {\n+\ti2c0_pins: i2c0-pins {\n+\t\tpins = \u003cPA12 PA13\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c1_pins: i2c1-pins {\n+\t\tpins = \u003cPB6 PB7\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c2_pins: i2c2-pins {\n+\t\tpins = \u003cPC0 PC1\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c3_pins: i2c3-pins {\n+\t\tpins = \u003cPC2 PC3\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tspi0_pins: spi0-pins {\n+\t\tpins = \u003cPD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7\u003e;\n+\t\tfunction = \"spi\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tspi1_pins: spi1-pins {\n+\t\tpins = \u003cPA0 PA1 PA2 PA3\u003e;\n+\t\tfunction = \"spi\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart0_pins: uart0-pins {\n+\t\tpins = \u003cPA8 PA9\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart1_pins: uart1-pins {\n+\t\tpins = \u003cPB4 PB5\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart2_pins: uart2-pins {\n+\t\tpins = \u003cPC4 PC5\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart3_pins: uart3-pins {\n+\t\tpins = \u003cPC6 PC7\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+};\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts\nnew file mode 100644\nindex 0000000000000..da831da819ef2\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts\n@@ -0,0 +1,114 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ /\n+\n+#include \"dp1000-shenrongda-m0-pinctrl.dtsi\"\n+#include \u003cdt-bindings/gpio/gpio.h\u003e\n+\n+/ {\n+\tmodel = \"Shenzhen Rongda M0 Board\";\n+\tcompatible = \"shenrongda,m0\", \"ultrarisc,dp1000\";\n+\n+\taliases {\n+\t\tserial0 = \u0026uart0;\n+\t\tserial1 = \u0026uart1;\n+\t\tserial2 = \u0026uart2;\n+\t\tserial3 = \u0026uart3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+};\n+\n+\u0026i2c0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c0_pins\u003e;\n+};\n+\n+\u0026i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c1_pins\u003e;\n+};\n+\n+\u0026i2c2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c2_pins\u003e;\n+\n+\trtc@32 {\n+\t\tcompatible = \"whwave,sd3078\";\n+\t\treg = \u003c0x32\u003e;\n+\t};\n+};\n+\n+\u0026i2c3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c3_pins\u003e;\n+};\n+\n+\u0026spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026spi0_pins\u003e;\n+};\n+\n+\u0026spi1 {\n+\tnum-cs = \u003c1\u003e;\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026spi1_pins\u003e;\n+};\n+\n+\u0026uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart0_pins\u003e;\n+};\n+\n+\u0026uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart1_pins\u003e;\n+};\n+\n+\u0026uart2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart2_pins\u003e;\n+};\n+\n+\u0026uart3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart3_pins\u003e;\n+};\n+\n+\u0026pcie_x16 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pcie_x4a {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pcie_x4b {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026ethernet {\n+\tphy-handle = \u003c\u0026phy0\u003e;\n+\t/\n+\t * YT8531 RGMII timing on this board requires no PHY internal delays.\n+\t * Using \"rgmii-id\" together with rx/tx-internal-delay-ps results in RX CRC\n+\t * errors and no usable traffic, so keep plain \"rgmii\" here.\n+\t /\n+\tphy-mode = \"rgmii\";\n+\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\n+\t\tphy0: phy@0 {\n+\t\t\treg = \u003c0\u003e;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi\nnew file mode 100644\nindex 0000000000000..470ab01e33b8a\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi\n@@ -0,0 +1,899 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ /\n+\n+/dts-v1/;\n+\n+#include \u003cdt-bindings/clock/ultrarisc,dp1000-clk.h\u003e\n+\n+/ {\n+\tcompatible = \"ultrarisc,dp1000\";\n+\t#address-cells = \u003c2\u003e;\n+\t#size-cells = \u003c2\u003e;\n+\n+\tcpus {\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\t\ttimebase-frequency = \u003c10000000\u003e;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x0\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t /\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache0\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu0_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache0: l2-cache {\n+\t\t\t\t/\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t /\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster0_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu1: cpu@1 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x1\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t /\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache1\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu1_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache1: l2-cache {\n+\t\t\t\t/\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t /\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster0_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu2: cpu@2 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x2\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t /\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache2\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu2_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache2: l2-cache {\n+\t\t\t\t/\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t /\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster0_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu3: cpu@3 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x3\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t /\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache3\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu3_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache3: l2-cache {\n+\t\t\t\t/\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t /\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster0_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu4: cpu@10 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x10\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t /\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache4\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu4_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache4: l2-cache {\n+\t\t\t\t/\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t /\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster1_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\t\tcpu5: cpu@11 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x11\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t /\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache5\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu5_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache5: l2-cache {\n+\t\t\t\t/\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t /\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster1_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\t\tcpu6: cpu@12 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x12\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t /\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache6\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu6_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache6: l2-cache {\n+\t\t\t\t/\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t /\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster1_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu7: cpu@13 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x13\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t /\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache7\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu7_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache7: l2-cache {\n+\t\t\t\t/\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t /\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster1_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu-map {\n+\t\t\tcluster0: cluster0 {\n+\t\t\t\tcore0 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu0\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore1 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu1\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore2 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu2\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore3 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu3\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcluster1: cluster1 {\n+\t\t\t\tcore0 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu4\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore1 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu5\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore2 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu6\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore3 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu7\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tcluster0_l3: l3-cache0 {\n+\t\t\t/\n+\t\t\t * L3 cache:\n+\t\t\t * cache-unified, block-size 64B\n+\t\t\t * 16-way set associative, size 4MB\n+\t\t\t * per-cluster.\n+\t\t\t /\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\tcache-level = \u003c3\u003e;\n+\t\t\tcache-size = \u003c0x400000\u003e;\n+\t\t\tcache-sets = \u003c0x1000\u003e;\n+\t\t\tcache-unified;\n+\t\t\tnext-level-cache = \u003c\u0026l4_cache\u003e;\n+\t\t};\n+\n+\t\tcluster1_l3: l3-cache1 {\n+\t\t\t/\n+\t\t\t * L3 cache:\n+\t\t\t * cache-unified, block-size 64B\n+\t\t\t * 16-way set associative, size 4MB\n+\t\t\t * per-cluster.\n+\t\t\t /\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\tcache-level = \u003c3\u003e;\n+\t\t\tcache-size = \u003c0x400000\u003e;\n+\t\t\tcache-sets = \u003c0x1000\u003e;\n+\t\t\tcache-unified;\n+\t\t\tnext-level-cache = \u003c\u0026l4_cache\u003e;\n+\t\t};\n+\t};\n+\n+\tl4_cache: l4-cache {\n+\t\t/\n+\t\t * L4 cache:\n+\t\t * cache-unified, block-size 64B\n+\t\t * 16-way set associative, size 16MB\n+\t\t * shared by the SoC.\n+\t\t */\n+\t\tcompatible = \"cache\";\n+\t\tcache-block-size = \u003c64\u003e;\n+\t\tcache-level = \u003c4\u003e;\n+\t\tcache-size = \u003c0x1000000\u003e;\n+\t\tcache-sets = \u003c0x4000\u003e;\n+\t\tcache-unified;\n+\t};\n+\n+\tosc_24m: clock-24m {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = \u003c0\u003e;\n+\t\tclock-frequency = \u003c24000000\u003e;\n+\t};\n+\n+\tsoc {\n+\t\tcompatible = \"simple-bus\";\n+\t\tranges;\n+\t\t#address-cells = \u003c2\u003e;\n+\t\t#size-cells = \u003c2\u003e;\n+\n+\t\tclint: clint@8000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-clint\", \"sifive,clint0\";\n+\t\t\treg = \u003c0x0 0x8000000 0x0 0x100000\u003e;\n+\t\t\tinterrupts-extended = \u003c\u0026cpu0_intc 3\u003e, \u003c\u0026cpu0_intc 7\u003e,\n+\t\t\t\t\t \u003c\u0026cpu1_intc 3\u003e, \u003c\u0026cpu1_intc 7\u003e,\n+\t\t\t\t\t \u003c\u0026cpu2_intc 3\u003e, \u003c\u0026cpu2_intc 7\u003e,\n+\t\t\t\t\t \u003c\u0026cpu3_intc 3\u003e, \u003c\u0026cpu3_intc 7\u003e,\n+\t\t\t\t\t \u003c\u0026cpu4_intc 3\u003e, \u003c\u0026cpu4_intc 7\u003e,\n+\t\t\t\t\t \u003c\u0026cpu5_intc 3\u003e, \u003c\u0026cpu5_intc 7\u003e,\n+\t\t\t\t\t \u003c\u0026cpu6_intc 3\u003e, \u003c\u0026cpu6_intc 7\u003e,\n+\t\t\t\t\t \u003c\u0026cpu7_intc 3\u003e, \u003c\u0026cpu7_intc 7\u003e;\n+\t\t};\n+\n+\t\tplic: plic@9000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-plic\", \"ultrarisc,cp100-plic\";\n+\t\t\treg = \u003c0x0 0x9000000 0x0 0x4000000\u003e;\n+\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t#address-cells = \u003c0\u003e;\n+\t\t\tinterrupt-controller;\n+\t\t\tinterrupts-extended = \u003c\u0026cpu0_intc 11\u003e, \u003c\u0026cpu0_intc 9\u003e, \u003c\u0026cpu0_intc 10\u003e,\n+\t\t\t\t\t \u003c\u0026cpu1_intc 11\u003e, \u003c\u0026cpu1_intc 9\u003e, \u003c\u0026cpu1_intc 10\u003e,\n+\t\t\t\t\t \u003c\u0026cpu2_intc 11\u003e, \u003c\u0026cpu2_intc 9\u003e, \u003c\u0026cpu2_intc 10\u003e,\n+\t\t\t\t\t \u003c\u0026cpu3_intc 11\u003e, \u003c\u0026cpu3_intc 9\u003e, \u003c\u0026cpu3_intc 10\u003e,\n+\t\t\t\t\t \u003c\u0026cpu4_intc 11\u003e, \u003c\u0026cpu4_intc 9\u003e, \u003c\u0026cpu4_intc 10\u003e,\n+\t\t\t\t\t \u003c\u0026cpu5_intc 11\u003e, \u003c\u0026cpu5_intc 9\u003e, \u003c\u0026cpu5_intc 10\u003e,\n+\t\t\t\t\t \u003c\u0026cpu6_intc 11\u003e, \u003c\u0026cpu6_intc 9\u003e, \u003c\u0026cpu6_intc 10\u003e,\n+\t\t\t\t\t \u003c\u0026cpu7_intc 11\u003e, \u003c\u0026cpu7_intc 9\u003e, \u003c\u0026cpu7_intc 10\u003e;\n+\t\t\triscv,ndev = \u003c160\u003e;\n+\t\t};\n+\n+\t\tclkc: clock-controller@11080000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-clk\";\n+\t\t\treg = \u003c0x0 0x11080000 0x0 0x1000\u003e;\n+\t\t\tclocks = \u003c\u0026osc_24m\u003e;\n+\t\t\t#clock-cells = \u003c1\u003e;\n+\t\t};\n+\n+\t\tpinctrl: pinctrl@11081000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-pinctrl\";\n+\t\t\treg = \u003c0x0 0x11081000 0x0 0x1000\u003e;\n+\t\t};\n+\n+\t\tgpio: gpio@20200000 {\n+\t\t\tcompatible = \"snps,dw-apb-gpio\";\n+\t\t\treg = \u003c0x0 0x20200000 0x0 0x1000\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-names = \"bus\", \"db\";\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\n+\t\t\tgpio_a: gpio-port@0 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\treg = \u003c0\u003e;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = \u003c2\u003e;\n+\t\t\t\tsnps,nr-gpios = \u003c16\u003e;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c2\u003e;\n+\t\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\t\tinterrupts = \u003c34\u003e;\n+\t\t\t\tgpio-ranges = \u003c\u0026pinctrl 0 0 16\u003e;\n+\t\t\t};\n+\n+\t\t\tgpio_b: gpio-port@1 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\treg = \u003c1\u003e;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = \u003c2\u003e;\n+\t\t\t\tsnps,nr-gpios = \u003c8\u003e;\n+\t\t\t\tgpio-ranges = \u003c\u0026pinctrl 0 16 8\u003e;\n+\t\t\t};\n+\n+\t\t\tgpio_c: gpio-port@2 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\treg = \u003c2\u003e;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = \u003c2\u003e;\n+\t\t\t\tsnps,nr-gpios = \u003c8\u003e;\n+\t\t\t\tgpio-ranges = \u003c\u0026pinctrl 0 24 8\u003e;\n+\t\t\t};\n+\n+\t\t\tgpio_d: gpio-port@3 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\treg = \u003c3\u003e;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = \u003c2\u003e;\n+\t\t\t\tsnps,nr-gpios = \u003c8\u003e;\n+\t\t\t\tgpio-ranges = \u003c\u0026pinctrl 0 32 8\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tuart0: serial@20300000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-uart\", \"snps,dw-apb-uart\";\n+\t\t\treg = \u003c0x0 0x20300000 0x0 0x10000\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c17\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_UART0\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\t\treg-io-width = \u003c4\u003e;\n+\t\t\treg-shift = \u003c2\u003e;\n+\t\t};\n+\n+\t\tuart1: serial@20310000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-uart\", \"snps,dw-apb-uart\";\n+\t\t\treg = \u003c0x0 0x20310000 0x0 0x10000\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c18\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_UART1\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\t\treg-io-width = \u003c4\u003e;\n+\t\t\treg-shift = \u003c2\u003e;\n+\t\t};\n+\n+\t\tuart2: serial@20400000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-uart\", \"snps,dw-apb-uart\";\n+\t\t\treg = \u003c0x0 0x20400000 0x0 0x10000\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c25\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_UART2\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\t\treg-io-width = \u003c4\u003e;\n+\t\t\treg-shift = \u003c2\u003e;\n+\t\t};\n+\n+\t\tuart3: serial@20410000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-uart\", \"snps,dw-apb-uart\";\n+\t\t\treg = \u003c0x0 0x20410000 0x0 0x10000\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c26\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_UART3\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\t\treg-io-width = \u003c4\u003e;\n+\t\t\treg-shift = \u003c2\u003e;\n+\t\t};\n+\n+\t\tspi0: spi@20320000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-spi\", \"snps,dw-apb-ssi\";\n+\t\t\treg = \u003c0x0 0x20320000 0x0 0x1000\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_SPI0\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ssi_clk\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c19\u003e;\n+\t\t\tnum-cs = \u003c3\u003e;\n+\t\t};\n+\n+\t\tspi1: spi@20420000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-spi\", \"snps,dw-apb-ssi\";\n+\t\t\treg = \u003c0x0 0x20420000 0x0 0x1000\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_SPI1\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ssi_clk\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c27\u003e;\n+\t\t\tnum-cs = \u003c3\u003e;\n+\t\t};\n+\n+\t\ti2c0: i2c@20330000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = \u003c0x0 0x20330000 0x0 0x100\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-frequency = \u003c400000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_I2C0\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ref\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c20\u003e;\n+\t\t};\n+\n+\t\ti2c1: i2c@20340000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = \u003c0x0 0x20340000 0x0 0x100\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-frequency = \u003c400000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_I2C1\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ref\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c21\u003e;\n+\t\t};\n+\n+\t\ti2c2: i2c@20430000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = \u003c0x0 0x20430000 0x0 0x100\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-frequency = \u003c400000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_I2C2\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ref\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c28\u003e;\n+\t\t};\n+\n+\t\ti2c3: i2c@20440000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = \u003c0x0 0x20440000 0x0 0x100\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-frequency = \u003c400000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_I2C3\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ref\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c29\u003e;\n+\t\t};\n+\n+\t\tpcie_x16: pcie@21000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-pcie\";\n+\t\t\treg = \u003c0x0 0x21000000 0x0 0x1000000\u003e,\n+\t\t\t \u003c0x0 0x4fff0000 0x0 0x10000\u003e;\n+\t\t\treg-names = \"dbi\", \"config\";\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_PCIEX16_CORE\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_DBI\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_AUX\u003e;\n+\t\t\tclock-names = \"core\", \"dbi\", \"aux\";\n+\t\t\tranges = \u003c0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000\u003e,\n+\t\t\t\t \u003c0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000\u003e,\n+\t\t\t\t \u003c0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000\u003e;\n+\t\t\t#address-cells = \u003c3\u003e;\n+\t\t\t#size-cells = \u003c2\u003e;\n+\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tbus-range = \u003c0x0 0xff\u003e;\n+\t\t\tnum-lanes = \u003c16\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c43\u003e, \u003c44\u003e, \u003c45\u003e, \u003c46\u003e, \u003c47\u003e;\n+\t\t\tinterrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+\t\t\tinterrupt-map-mask = \u003c0x0 0x0 0x0 0x7\u003e;\n+\t\t\tinterrupt-map = \u003c0x0 0x0 0x0 0x1 \u0026plic 44\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x2 \u0026plic 45\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x3 \u0026plic 46\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x4 \u0026plic 47\u003e;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpcie_x4a: pcie@23000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-pcie\";\n+\t\t\treg = \u003c0x0 0x23000000 0x0 0x1000000\u003e,\n+\t\t\t \u003c0x0 0x6fff0000 0x0 0x10000\u003e;\n+\t\t\treg-names = \"dbi\", \"config\";\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_PCIEX4_CORE\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_DBI\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_AUX\u003e;\n+\t\t\tclock-names = \"core\", \"dbi\", \"aux\";\n+\t\t\tranges = \u003c0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000\u003e,\n+\t\t\t\t \u003c0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000\u003e,\n+\t\t\t\t \u003c0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000\u003e;\n+\t\t\t#address-cells = \u003c3\u003e;\n+\t\t\t#size-cells = \u003c2\u003e;\n+\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tbus-range = \u003c0x0 0xff\u003e;\n+\t\t\tnum-lanes = \u003c4\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c63\u003e, \u003c64\u003e, \u003c65\u003e, \u003c66\u003e, \u003c67\u003e;\n+\t\t\tinterrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+\t\t\tinterrupt-map-mask = \u003c0x0 0x0 0x0 0x7\u003e;\n+\t\t\tinterrupt-map = \u003c0x0 0x0 0x0 0x1 \u0026plic 64\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x2 \u0026plic 65\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x3 \u0026plic 66\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x4 \u0026plic 67\u003e;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpcie_x4b: pcie@24000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-pcie\";\n+\t\t\treg = \u003c0x0 0x24000000 0x0 0x1000000\u003e,\n+\t\t\t \u003c0x0 0x7fff0000 0x0 0x10000\u003e;\n+\t\t\treg-names = \"dbi\", \"config\";\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_PCIEX4_CORE\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_DBI\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_AUX\u003e;\n+\t\t\tclock-names = \"core\", \"dbi\", \"aux\";\n+\t\t\tranges = \u003c0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000\u003e,\n+\t\t\t\t \u003c0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000\u003e,\n+\t\t\t\t \u003c0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000\u003e;\n+\t\t\t#address-cells = \u003c3\u003e;\n+\t\t\t#size-cells = \u003c2\u003e;\n+\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tbus-range = \u003c0x0 0xff\u003e;\n+\t\t\tnum-lanes = \u003c4\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c73\u003e, \u003c74\u003e, \u003c75\u003e, \u003c76\u003e, \u003c77\u003e;\n+\t\t\tinterrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+\t\t\tinterrupt-map-mask = \u003c0x0 0x0 0x0 0x7\u003e;\n+\t\t\tinterrupt-map = \u003c0x0 0x0 0x0 0x1 \u0026plic 74\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x2 \u0026plic 75\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x3 \u0026plic 76\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x4 \u0026plic 77\u003e;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tethernet: ethernet@38000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-gmac\", \"snps,dwmac-5.20\",\n+\t\t\t\t \"snps,dwmac\";\n+\t\t\treg = \u003c0x0 0x38000000 0x0 0x1000000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_GMAC\u003e;\n+\t\t\tclock-names = \"stmmaceth\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c84\u003e;\n+\t\t\tinterrupt-names = \"macirq\";\n+\t\t\tsnps,txpbl = \u003c8\u003e;\n+\t\t\tsnps,rxpbl = \u003c8\u003e;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdmac: dma-controller@39000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-axi-dma\", \"snps,axi-dma-1.01a\";\n+\t\t\treg = \u003c0x0 0x39000000 0x0 0x400\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_SYSPLL_DIV2\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"core-clk\", \"cfgr-clk\";\n+\t\t\t#dma-cells = \u003c1\u003e;\n+\t\t\tdma-channels = \u003c8\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c152\u003e;\n+\t\t\tsnps,dma-masters = \u003c1\u003e;\n+\t\t\tsnps,data-width = \u003c4\u003e;\n+\t\t\tsnps,block-size = \u003c512 512 512 512 512 512 512 512\u003e;\n+\t\t\tsnps,priority = \u003c0 1 2 3 4 5 6 7\u003e;\n+\t\t\tsnps,axi-max-burst-len = \u003c256\u003e;\n+\t\t};\n+\t};\n+};\n" }
2/1	2026/08/24 06:24	agent	patch-evaluator	0m Model: best-expensive Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch series only adds device tree bindings and device tree source (DTS) files for a new RISC-V SoC (UltraRISC DP1000) and its associated boards. It does not contain any executable C code changes or modifications to kernel logic that can be fuzzed.", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). - Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU. - Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove) that are executed only during PCI hot-unplug or sysfs driver unbind operations. If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. Prefer non-static, non-inlined API entrypoint functions over internal static helper functions (which are inlined by the compiler and do not have distinct symbol addresses). 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes: commit abedfd5586c0d4e72334bde3b92597c566cb440f Author: syz-cluster <triage@syzkaller.com> Date: Mon Aug 24 06:24:01 2026 +0000 syz-cluster: applied patch under review diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 0a30a455b0ee5..f7b5891f41ae9 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -27,6 +27,7 @@ properties: - enum: - altr,agilex5-axi-dma - sophgo,cv1800b-axi-dma + - ultrarisc,dp1000-axi-dma - const: snps,axi-dma-1.01a reg: diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index 467bdcbb85389..eee21ca8d7eda 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -44,6 +44,7 @@ properties: - mscc,ocelot-i2c - sophgo,sg2044-i2c - thead,th1520-i2c + - ultrarisc,dp1000-i2c - const: snps,designware-i2c reg: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 2449311c6d28e..2ed4564ae99d7 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -119,6 +119,7 @@ properties: - starfive,jh7110-dwmac - tesla,fsd-ethqos - thead,th1520-gmac + - ultrarisc,dp1000-gmac reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 5feeb2203050a..85adf72899c9d 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -67,6 +67,7 @@ properties: - thead,c908 - thead,c910 - thead,c920 + - ultrarisc,cp100 - const: riscv - items: - enum: @@ -117,8 +118,8 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: VLEN/8, the vector register length in bytes. This property is required on - thead systems where the vector register length is not identical on all harts, or - the vlenb CSR is not available. + thead systems where the vector register length is not identical on all + harts, or the vlenb CSR is not available. # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions @@ -151,8 +152,8 @@ anyOf: - riscv,isa-base dependencies: - riscv,isa-base: [ "riscv,isa-extensions" ] - riscv,isa-extensions: [ "riscv,isa-base" ] + riscv,isa-base: ["riscv,isa-extensions"] + riscv,isa-extensions: ["riscv,isa-base"] required: - interrupt-controller diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml new file mode 100644 index 0000000000000..a51e63dbeca33 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC SoC-based boards + +maintainers: + - Jia Wang <wangjia@ultrarisc.com> + +description: + UltraRISC DP1000 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - shenrongda,m0 + - milkv,titan + - const: ultrarisc,dp1000 + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 1e70c6804d5d1..896205329d7e5 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -63,6 +63,7 @@ properties: - mscc,jaguar2-spi - sophgo,sg2042-spi - thead,th1520-spi + - ultrarisc,dp1000-spi - const: snps,dw-apb-ssi - description: Vendor controllers compatible with v1.01a items: diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3673836e14dee..878f267d089b5 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -40,6 +40,7 @@ properties: - starfive,jh8100-clint # StarFive JH8100 - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole + - ultrarisc,dp1000-clint # UltraRISC DP1000 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6780b651acf80..61cd5e625a232 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1505,6 +1505,8 @@ patternProperties: description: SGX Sensortech "^sharp,.": description: Sharp Corporation + "^shenrongda,.": + description: Shenzhen Rongda Computer Co., Ltd. "^shift,.": description: SHIFT GmbH "^shimafuji,.": diff --git a/MAINTAINERS b/MAINTAINERS index e3f4e0fcdb3a7..a8f3c256bda24 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23517,6 +23517,14 @@ F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h +RISC-V ULTRARISC SoC SUPPORT +M: Jia Wang <wangjia@ultrarisc.com> +L: linux-riscv@lists.infradead.org +S: Supported +T: git https://github.com/ultrarisc/linux.git +F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml +F: arch/riscv/boot/dts/ultrarisc/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal <haris.iqbal@ionos.com> M: Jack Wang <jinpu.wang@ionos.com> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 69d8751fb17c8..7028829742518 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -12,3 +12,4 @@ subdir-y += spacemit subdir-y += starfive subdir-y += tenstorrent subdir-y += thead +subdir-y += ultrarisc diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile new file mode 100644 index 0000000000000..dfd15c064d078 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi new file mode 100644 index 0000000000000..7a812e40a2496 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + / + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins = <PA12 PA13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c1_pins: i2c1-pins { + pins = <PB6 PB7>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c2_pins: i2c2-pins { + pins = <PC0 PC1>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c3_pins: i2c3-pins { + pins = <PC2 PC3>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + io_pins: io-pins { + pins = <PA10 PA15 PB0 PB1 PB2 PD6 PD7>; + function = "gpio"; + bias-pull-up; + drive-strength = <33>; + }; + + gpio_keys_pins: gpio-keys-pins { + pins = <PA4 PA11 PA14>; + function = "gpio"; + bias-pull-up; + drive-strength = <33>; + }; + + mux_dcdc_i2c_pins: mux-dcdc-i2c-pins { + pins = <PA5>; + function = "gpio"; + }; + + mux_i2c3_pins: mux-i2c3-pins { + pins = <PA6>; + function = "gpio"; + }; + + mux_uart0_pins: mux-uart0-pins { + pins = <PA7>; + function = "gpio"; + }; + + spi0_pins: spi0-pins { + pins = <PD0 PD1 PD2 PD3 PD4 PD5>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + spi1_pins: spi1-pins { + pins = <PA0 PA1 PA2 PA3>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0_pins: uart0-pins { + pins = <PA8 PA9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart1_pins: uart1-pins { + pins = <PB4 PB5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart2_pins: uart2-pins { + pins = <PC4 PC5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart3_pins: uart3-pins { + pins = <PC6 PC7>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts new file mode 100644 index 0000000000000..f1a0efee3d746 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/ + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + / + +#include "dp1000-milkv-titan-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Milk-V Titan"; + compatible = "milkv,titan", "ultrarisc,dp1000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-wakeup-0 { + label = "Wake-Up"; + gpios = <&gpio_a 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + wakeup-event-action = <EV_ACT_ASSERTED>; + }; + + key-wakeup-1 { + label = "Power"; + gpios = <&gpio_a 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + wakeup-event-action = <EV_ACT_ASSERTED>; + }; + + key-wakeup-2 { + label = "Wake-Up-by-USB"; + interrupts-extended = <&gpio_a 4 IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_WAKEUP>; + linux,input-type = <EV_KEY>; + debounce-interval = <10>; + wakeup-source; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { + num-cs = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&pcie_x16 { + status = "okay"; +}; + +&pcie_x4a { + status = "okay"; +}; + +&pcie_x4b { + status = "okay"; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&io_pins &mux_dcdc_i2c_pins &mux_i2c3_pins &mux_uart0_pins>; +}; + +&gpio_a { + dcdc-i2c-mux-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "dcdc-i2c-mux"; + }; + + i2c3-mux-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "i2c3-mux"; + }; + + uart0-mux-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "uart0-mux"; + }; +}; + +&ethernet { + phy-handle = <&phy0>; + / + * RTL8211F: board timing uses PHY strap delays; keep plain "rgmii". + * Enabling PHY internal delays via "rgmii-id" breaks Ethernet traffic. + / + phy-mode = "rgmii"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + label = "eth-link"; + reg = <1>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_INDICATOR; + default-state = "keep"; + linux,default-trigger = "netdev"; + }; + + led@2 { + label = "eth-activity"; + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h new file mode 100644 index 0000000000000..4668e45d2335d --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h @@ -0,0 +1,63 @@ +/ SPDX-License-Identifier: GPL-2.0-only / +/ + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + / + +#ifndef _DP1000_PINCTRL_H +#define _DP1000_PINCTRL_H + +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PC0 24 +#define PC1 25 +#define PC2 26 +#define PC3 27 +#define PC4 28 +#define PC5 29 +#define PC6 30 +#define PC7 31 +#define PD0 32 +#define PD1 33 +#define PD2 34 +#define PD3 35 +#define PD4 36 +#define PD5 37 +#define PD6 38 +#define PD7 39 +#define LPC0 40 +#define LPC1 41 +#define LPC2 42 +#define LPC3 43 +#define LPC4 44 +#define LPC5 45 +#define LPC6 46 +#define LPC7 47 +#define LPC8 48 +#define LPC9 49 +#define LPC10 50 +#define LPC11 51 +#define LPC12 52 + +#endif / _DP1000_PINCTRL_H / diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi new file mode 100644 index 0000000000000..ab927c6cd6146 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/ + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + / + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins = <PA12 PA13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c1_pins: i2c1-pins { + pins = <PB6 PB7>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c2_pins: i2c2-pins { + pins = <PC0 PC1>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + i2c3_pins: i2c3-pins { + pins = <PC2 PC3>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + spi0_pins: spi0-pins { + pins = <PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + spi1_pins: spi1-pins { + pins = <PA0 PA1 PA2 PA3>; + function = "spi"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0_pins: uart0-pins { + pins = <PA8 PA9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart1_pins: uart1-pins { + pins = <PB4 PB5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart2_pins: uart2-pins { + pins = <PC4 PC5>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + + uart3_pins: uart3-pins { + pins = <PC6 PC7>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts new file mode 100644 index 0000000000000..da831da819ef2 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/ + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + / + +#include "dp1000-shenrongda-m0-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Shenzhen Rongda M0 Board"; + compatible = "shenrongda,m0", "ultrarisc,dp1000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + rtc@32 { + compatible = "whwave,sd3078"; + reg = <0x32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { + num-cs = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&pcie_x16 { + status = "okay"; +}; + +&pcie_x4a { + status = "okay"; +}; + +&pcie_x4b { + status = "okay"; +}; + +&ethernet { + phy-handle = <&phy0>; + / + * YT8531 RGMII timing on this board requires no PHY internal delays. + * Using "rgmii-id" together with rx/tx-internal-delay-ps results in RX CRC + * errors and no usable traffic, so keep plain "rgmii" here. + / + phy-mode = "rgmii"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi new file mode 100644 index 0000000000000..470ab01e33b8a --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi @@ -0,0 +1,899 @@ +// SPDX-License-Identifier: GPL-2.0 +/ + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + / + +/dts-v1/; + +#include <dt-bindings/clock/ultrarisc,dp1000-clk.h> + +/ { + compatible = "ultrarisc,dp1000"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + + cpu0: cpu@0 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x0>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + / + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + / + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache0>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache0: l2-cache { + / + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu1: cpu@1 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x1>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + / + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + / + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache1>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache1: l2-cache { + / + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu2: cpu@2 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x2>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + / + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + / + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache2>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache2: l2-cache { + / + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu3: cpu@3 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x3>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + / + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + / + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache3>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache3: l2-cache { + / + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster0_l3>; + }; + }; + + cpu4: cpu@10 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x10>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + / + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + / + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache4>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache4: l2-cache { + / + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + cpu5: cpu@11 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x11>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + / + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + / + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache5>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache5: l2-cache { + / + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + cpu6: cpu@12 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x12>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + / + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + / + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache6>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache6: l2-cache { + / + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + + cpu7: cpu@13 { + compatible = "ultrarisc,cp100", "riscv"; + reg = <0x13>; + device_type = "cpu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; + / + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + / + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + next-level-cache = <&l2_cache7>; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + l2_cache7: l2-cache { + / + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <0x80000>; + cache-sets = <1024>; + cache-unified; + next-level-cache = <&cluster1_l3>; + }; + }; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cluster0_l3: l3-cache0 { + / + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + next-level-cache = <&l4_cache>; + }; + + cluster1_l3: l3-cache1 { + / + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + / + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + next-level-cache = <&l4_cache>; + }; + }; + + l4_cache: l4-cache { + / + * L4 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 16MB + * shared by the SoC. + */ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <4>; + cache-size = <0x1000000>; + cache-sets = <0x4000>; + cache-unified; + }; + + osc_24m: clock-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + clint: clint@8000000 { + compatible = "ultrarisc,dp1000-clint", "sifive,clint0"; + reg = <0x0 0x8000000 0x0 0x100000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + plic: plic@9000000 { + compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + reg = <0x0 0x9000000 0x0 0x4000000>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu0_intc 10>, + <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu1_intc 10>, + <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu2_intc 10>, + <&cpu3_intc 11>, <&cpu3_intc 9>, <&cpu3_intc 10>, + <&cpu4_intc 11>, <&cpu4_intc 9>, <&cpu4_intc 10>, + <&cpu5_intc 11>, <&cpu5_intc 9>, <&cpu5_intc 10>, + <&cpu6_intc 11>, <&cpu6_intc 9>, <&cpu6_intc 10>, + <&cpu7_intc 11>, <&cpu7_intc 9>, <&cpu7_intc 10>; + riscv,ndev = <160>; + }; + + clkc: clock-controller@11080000 { + compatible = "ultrarisc,dp1000-clk"; + reg = <0x0 0x11080000 0x0 0x1000>; + clocks = <&osc_24m>; + #clock-cells = <1>; + }; + + pinctrl: pinctrl@11081000 { + compatible = "ultrarisc,dp1000-pinctrl"; + reg = <0x0 0x11081000 0x0 0x1000>; + }; + + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x20200000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "bus", "db"; + clocks = <&clkc DP1000_CLK_SUBSYS>, + <&clkc DP1000_CLK_SUBSYS>; + + gpio_a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <16>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&plic>; + interrupts = <34>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpio_b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 16 8>; + }; + + gpio_c: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 24 8>; + }; + + gpio_d: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + gpio-ranges = <&pinctrl 0 32 8>; + }; + }; + + uart0: serial@20300000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20300000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <17>; + clocks = <&clkc DP1000_CLK_UART0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart1: serial@20310000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20310000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <18>; + clocks = <&clkc DP1000_CLK_UART1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart2: serial@20400000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20400000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <25>; + clocks = <&clkc DP1000_CLK_UART2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + uart3: serial@20410000 { + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg = <0x0 0x20410000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <26>; + clocks = <&clkc DP1000_CLK_UART3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + spi0: spi@20320000 { + compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg = <0x0 0x20320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc DP1000_CLK_SPI0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ssi_clk", "pclk"; + interrupt-parent = <&plic>; + interrupts = <19>; + num-cs = <3>; + }; + + spi1: spi@20420000 { + compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg = <0x0 0x20420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc DP1000_CLK_SPI1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ssi_clk", "pclk"; + interrupt-parent = <&plic>; + interrupts = <27>; + num-cs = <3>; + }; + + i2c0: i2c@20330000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20330000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <20>; + }; + + i2c1: i2c@20340000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20340000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <21>; + }; + + i2c2: i2c@20430000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20430000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <28>; + }; + + i2c3: i2c@20440000 { + compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg = <0x0 0x20440000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clkc DP1000_CLK_I2C3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "ref", "pclk"; + interrupt-parent = <&plic>; + interrupts = <29>; + }; + + pcie_x16: pcie@21000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x21000000 0x0 0x1000000>, + <0x0 0x4fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX16_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <16>; + interrupt-parent = <&plic>; + interrupts = <43>, <44>, <45>, <46>, <47>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + + status = "disabled"; + }; + + pcie_x4a: pcie@23000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x23000000 0x0 0x1000000>, + <0x0 0x6fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, + <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <4>; + interrupt-parent = <&plic>; + interrupts = <63>, <64>, <65>, <66>, <67>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, + <0x0 0x0 0x0 0x3 &plic 66>, + <0x0 0x0 0x0 0x4 &plic 67>; + + status = "disabled"; + }; + + pcie_x4b: pcie@24000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x24000000 0x0 0x1000000>, + <0x0 0x7fff0000 0x0 0x10000>; + reg-names = "dbi", "config"; + clocks = <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, + <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <4>; + interrupt-parent = <&plic>; + interrupts = <73>, <74>, <75>, <76>, <77>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, + <0x0 0x0 0x0 0x3 &plic 76>, + <0x0 0x0 0x0 0x4 &plic 77>; + + status = "disabled"; + }; + + ethernet: ethernet@38000000 { + compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.20", + "snps,dwmac"; + reg = <0x0 0x38000000 0x0 0x1000000>; + clocks = <&clkc DP1000_CLK_GMAC>; + clock-names = "stmmaceth"; + interrupt-parent = <&plic>; + interrupts = <84>; + interrupt-names = "macirq"; + snps,txpbl = <8>; + snps,rxpbl = <8>; + + status = "disabled"; + }; + + dmac: dma-controller@39000000 { + compatible = "ultrarisc,dp1000-axi-dma", "snps,axi-dma-1.01a"; + reg = <0x0 0x39000000 0x0 0x400>; + clocks = <&clkc DP1000_CLK_SYSPLL_DIV2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <8>; + interrupt-parent = <&plic>; + interrupts = <152>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,block-size = <512 512 512 512 512 512 512 512>; + snps,priority = <0 1 2 3 4 5 6 7>; + snps,axi-max-burst-len = <256>; + }; + }; +};
3/2	2026/08/24 06:24	llm	patch-evaluator	0m Model: gemini-3.1-pro-preview Args: null Results: null Tokens: input: 23123 output: 92 thoughts: 933 Thoughts: WorthFuzzing=false: UltraRISC DP1000 SoC DTS Files Only Okay, here's the deal. I'm looking at this patch series, and it's all about adding Device Tree bindings and source files for this new UltraRISC DP1000 RISC-V SoC and its associated boards. The bulk of the changes are within the `Documentation/devicetree/bindings/` directory, along with the DTS files in `arch/riscv/boot/dts/ultrarisc/`, the `MAINTAINERS` file, and some `Makefile` updates in the DTS directories. Initial assessment: no C code changes. Wait, I should double check that. Okay, the diff confirms it: all DTS files, documentation, and makefiles. Perfect. The instructions I have say I need to return `WorthFuzzing=false` if the patch only contains modifications to documentation, Kconfig files, code comments, decorative changes, numeric constants/macros that don't alter execution, unreachable code in virtualized environments, or vendor-specific drivers for specific hardware that isn't emulated. So, this patch adds DTS files. DTS files aren't C code. They're just descriptive text files, essentially. They describe hardware, they don't contain executable logic. My primary concern, then, is whether this constitutes a "functional change to the kernel that should be fuzzed." Ordinarily, adding DTS files for a new SoC alone doesn't affect the kernel's execution flow in a way that warrants fuzzing unless we were specifically fuzzing the DTB parsing, which is a generic aspect of the kernel. The instructions also state: "If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true." Since there's no C code, there's no new executable logic to fuzz, which is the key. Let me just do one more quick scan to make absolutely sure there aren't any C files lurking anywhere. Nope. Just `.yaml`, `MAINTAINERS`, `Makefile`, `.dtsi`, `.dts`, and `.h` (which, again, is just a pinctrl header with macros). Therefore, I'm confident in setting `WorthFuzzing=false`.
4/2	2026/08/24 06:24	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The patch series only adds device tree bindings and device tree source (DTS) files for a new RISC-V SoC (UltraRISC DP1000) and its associated boards. It does not contain any executable C code changes or modifications to kernel logic that can be fuzzed.", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch series only adds device tree bindings and device tree source (DTS) files for a new RISC-V SoC (UltraRISC DP1000) and its associated boards. It does not contain any executable C code changes or modifications to kernel logic that can be fuzzed.", "WorthFuzzing": false }
5/1	2026/08/24 06:24	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "PatchDiff": "commit abedfd5586c0d4e72334bde3b92597c566cb440f\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Mon Aug 24 06:24:01 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml\nindex 0a30a455b0ee5..f7b5891f41ae9 100644\n--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml\n+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml\n@@ -27,6 +27,7 @@ properties:\n           - enum:\n               - altr,agilex5-axi-dma\n               - sophgo,cv1800b-axi-dma\n+              - ultrarisc,dp1000-axi-dma\n           - const: snps,axi-dma-1.01a\n \n   reg:\ndiff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml\nindex 467bdcbb85389..eee21ca8d7eda 100644\n--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml\n+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml\n@@ -44,6 +44,7 @@ properties:\n               - mscc,ocelot-i2c\n               - sophgo,sg2044-i2c\n               - thead,th1520-i2c\n+              - ultrarisc,dp1000-i2c\n           - const: snps,designware-i2c\n \n   reg:\ndiff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml\nindex 2449311c6d28e..2ed4564ae99d7 100644\n--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml\n+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml\n@@ -119,6 +119,7 @@ properties:\n         - starfive,jh7110-dwmac\n         - tesla,fsd-ethqos\n         - thead,th1520-gmac\n+        - ultrarisc,dp1000-gmac\n \n   reg:\n     minItems: 1\ndiff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml\nindex 5feeb2203050a..85adf72899c9d 100644\n--- a/Documentation/devicetree/bindings/riscv/cpus.yaml\n+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml\n@@ -67,6 +67,7 @@ properties:\n               - thead,c908\n               - thead,c910\n               - thead,c920\n+              - ultrarisc,cp100\n           - const: riscv\n       - items:\n           - enum:\n@@ -117,8 +118,8 @@ properties:\n     $ref: /schemas/types.yaml#/definitions/uint32\n     description:\n       VLEN/8, the vector register length in bytes. This property is required on\n-      thead systems where the vector register length is not identical on all harts, or\n-      the vlenb CSR is not available.\n+      thead systems where the vector register length is not identical on all\n+      harts, or the vlenb CSR is not available.\n \n   # RISC-V has multiple properties for cache op block sizes as the sizes\n   # differ between individual CBO extensions\n@@ -151,8 +152,8 @@ anyOf:\n       - riscv,isa-base\n \n dependencies:\n-  riscv,isa-base: [ \"riscv,isa-extensions\" ]\n-  riscv,isa-extensions: [ \"riscv,isa-base\" ]\n+  riscv,isa-base: [\"riscv,isa-extensions\"]\n+  riscv,isa-extensions: [\"riscv,isa-base\"]\n \n required:\n   - interrupt-controller\ndiff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml\nnew file mode 100644\nindex 0000000000000..a51e63dbeca33\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml\n@@ -0,0 +1,27 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: UltraRISC SoC-based boards\n+\n+maintainers:\n+  - Jia Wang \u003cwangjia@ultrarisc.com\u003e\n+\n+description:\n+  UltraRISC DP1000 SoC-based boards\n+\n+properties:\n+  $nodename:\n+    const: '/'\n+  compatible:\n+    oneOf:\n+      - items:\n+          - enum:\n+              - shenrongda,m0\n+              - milkv,titan\n+          - const: ultrarisc,dp1000\n+\n+additionalProperties: true\n+...\ndiff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml\nindex 1e70c6804d5d1..896205329d7e5 100644\n--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml\n+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml\n@@ -63,6 +63,7 @@ properties:\n               - mscc,jaguar2-spi\n               - sophgo,sg2042-spi\n               - thead,th1520-spi\n+              - ultrarisc,dp1000-spi\n           - const: snps,dw-apb-ssi\n       - description: Vendor controllers compatible with v1.01a\n         items:\ndiff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml\nindex 3673836e14dee..878f267d089b5 100644\n--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml\n+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml\n@@ -40,6 +40,7 @@ properties:\n               - starfive,jh8100-clint   # StarFive JH8100\n               - starfive,jhb100-clint   # StarFive JHB100\n               - tenstorrent,blackhole-clint # Tenstorrent Blackhole\n+              - ultrarisc,dp1000-clint  # UltraRISC DP1000\n           - const: sifive,clint0        # SiFive CLINT v0 IP block\n       - items:\n           - {}\ndiff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml\nindex 6780b651acf80..61cd5e625a232 100644\n--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml\n+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml\n@@ -1505,6 +1505,8 @@ patternProperties:\n     description: SGX Sensortech\n   \"^sharp,.*\":\n     description: Sharp Corporation\n+  \"^shenrongda,.*\":\n+    description: Shenzhen Rongda Computer Co., Ltd.\n   \"^shift,.*\":\n     description: SHIFT GmbH\n   \"^shimafuji,.*\":\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex e3f4e0fcdb3a7..a8f3c256bda24 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -23517,6 +23517,14 @@ F:\tinclude/dt-bindings/power/thead,th1520-power.h\n F:\tinclude/dt-bindings/reset/thead,th1520-reset.h\n F:\tinclude/linux/firmware/thead/thead,th1520-aon.h\n \n+RISC-V ULTRARISC SoC SUPPORT\n+M:\tJia Wang \u003cwangjia@ultrarisc.com\u003e\n+L:\tlinux-riscv@lists.infradead.org\n+S:\tSupported\n+T:\tgit https://github.com/ultrarisc/linux.git\n+F:\tDocumentation/devicetree/bindings/riscv/ultrarisc.yaml\n+F:\tarch/riscv/boot/dts/ultrarisc/\n+\n RNBD BLOCK DRIVERS\n M:\tMd. Haris Iqbal \u003charis.iqbal@ionos.com\u003e\n M:\tJack Wang \u003cjinpu.wang@ionos.com\u003e\ndiff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile\nindex 69d8751fb17c8..7028829742518 100644\n--- a/arch/riscv/boot/dts/Makefile\n+++ b/arch/riscv/boot/dts/Makefile\n@@ -12,3 +12,4 @@ subdir-y += spacemit\n subdir-y += starfive\n subdir-y += tenstorrent\n subdir-y += thead\n+subdir-y += ultrarisc\ndiff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile\nnew file mode 100644\nindex 0000000000000..dfd15c064d078\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/Makefile\n@@ -0,0 +1,3 @@\n+# SPDX-License-Identifier: GPL-2.0\n+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb\n+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi\nnew file mode 100644\nindex 0000000000000..7a812e40a2496\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi\n@@ -0,0 +1,108 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ */\n+\n+#include \"dp1000.dtsi\"\n+#include \"dp1000-pinctrl.h\"\n+\n+\u0026pinctrl {\n+\ti2c0_pins: i2c0-pins {\n+\t\tpins = \u003cPA12 PA13\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c1_pins: i2c1-pins {\n+\t\tpins = \u003cPB6 PB7\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c2_pins: i2c2-pins {\n+\t\tpins = \u003cPC0 PC1\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c3_pins: i2c3-pins {\n+\t\tpins = \u003cPC2 PC3\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tio_pins: io-pins {\n+\t\tpins = \u003cPA10 PA15 PB0 PB1 PB2 PD6 PD7\u003e;\n+\t\tfunction = \"gpio\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tgpio_keys_pins: gpio-keys-pins {\n+\t\tpins = \u003cPA4 PA11 PA14\u003e;\n+\t\tfunction = \"gpio\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tmux_dcdc_i2c_pins: mux-dcdc-i2c-pins {\n+\t\tpins = \u003cPA5\u003e;\n+\t\tfunction = \"gpio\";\n+\t};\n+\n+\tmux_i2c3_pins: mux-i2c3-pins {\n+\t\tpins = \u003cPA6\u003e;\n+\t\tfunction = \"gpio\";\n+\t};\n+\n+\tmux_uart0_pins: mux-uart0-pins {\n+\t\tpins = \u003cPA7\u003e;\n+\t\tfunction = \"gpio\";\n+\t};\n+\n+\tspi0_pins: spi0-pins {\n+\t\tpins = \u003cPD0 PD1 PD2 PD3 PD4 PD5\u003e;\n+\t\tfunction = \"spi\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tspi1_pins: spi1-pins {\n+\t\tpins = \u003cPA0 PA1 PA2 PA3\u003e;\n+\t\tfunction = \"spi\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart0_pins: uart0-pins {\n+\t\tpins = \u003cPA8 PA9\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart1_pins: uart1-pins {\n+\t\tpins = \u003cPB4 PB5\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart2_pins: uart2-pins {\n+\t\tpins = \u003cPC4 PC5\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart3_pins: uart3-pins {\n+\t\tpins = \u003cPC6 PC7\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+};\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts\nnew file mode 100644\nindex 0000000000000..f1a0efee3d746\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts\n@@ -0,0 +1,203 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ */\n+\n+#include \"dp1000-milkv-titan-pinctrl.dtsi\"\n+#include \u003cdt-bindings/gpio/gpio.h\u003e\n+#include \u003cdt-bindings/input/input.h\u003e\n+#include \u003cdt-bindings/input/gpio-keys.h\u003e\n+#include \u003cdt-bindings/interrupt-controller/irq.h\u003e\n+#include \u003cdt-bindings/leds/common.h\u003e\n+\n+/ {\n+\tmodel = \"Milk-V Titan\";\n+\tcompatible = \"milkv,titan\", \"ultrarisc,dp1000\";\n+\n+\taliases {\n+\t\tserial0 = \u0026uart0;\n+\t\tserial1 = \u0026uart1;\n+\t\tserial2 = \u0026uart2;\n+\t\tserial3 = \u0026uart3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = \u003c\u0026gpio_keys_pins\u003e;\n+\n+\t\tkey-wakeup-0 {\n+\t\t\tlabel = \"Wake-Up\";\n+\t\t\tgpios = \u003c\u0026gpio_a 14 GPIO_ACTIVE_LOW\u003e;\n+\t\t\tlinux,code = \u003cKEY_WAKEUP\u003e;\n+\t\t\tlinux,input-type = \u003cEV_KEY\u003e;\n+\t\t\tdebounce-interval = \u003c10\u003e;\n+\t\t\twakeup-source;\n+\t\t\twakeup-event-action = \u003cEV_ACT_ASSERTED\u003e;\n+\t\t};\n+\n+\t\tkey-wakeup-1 {\n+\t\t\tlabel = \"Power\";\n+\t\t\tgpios = \u003c\u0026gpio_a 11 GPIO_ACTIVE_LOW\u003e;\n+\t\t\tlinux,code = \u003cKEY_POWER\u003e;\n+\t\t\tlinux,input-type = \u003cEV_KEY\u003e;\n+\t\t\tdebounce-interval = \u003c10\u003e;\n+\t\t\twakeup-source;\n+\t\t\twakeup-event-action = \u003cEV_ACT_ASSERTED\u003e;\n+\t\t};\n+\n+\t\tkey-wakeup-2 {\n+\t\t\tlabel = \"Wake-Up-by-USB\";\n+\t\t\tinterrupts-extended = \u003c\u0026gpio_a 4 IRQ_TYPE_EDGE_FALLING\u003e;\n+\t\t\tlinux,code = \u003cKEY_WAKEUP\u003e;\n+\t\t\tlinux,input-type = \u003cEV_KEY\u003e;\n+\t\t\tdebounce-interval = \u003c10\u003e;\n+\t\t\twakeup-source;\n+\t\t};\n+\t};\n+};\n+\n+\u0026i2c0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c0_pins\u003e;\n+};\n+\n+\u0026i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c1_pins\u003e;\n+};\n+\n+\u0026i2c2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c2_pins\u003e;\n+\n+\trtc@68 {\n+\t\tcompatible = \"st,m41t11\";\n+\t\treg = \u003c0x68\u003e;\n+\t};\n+};\n+\n+\u0026i2c3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c3_pins\u003e;\n+};\n+\n+\u0026spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026spi0_pins\u003e;\n+};\n+\n+\u0026spi1 {\n+\tnum-cs = \u003c1\u003e;\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026spi1_pins\u003e;\n+};\n+\n+\u0026uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart0_pins\u003e;\n+};\n+\n+\u0026uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart1_pins\u003e;\n+};\n+\n+\u0026uart2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart2_pins\u003e;\n+};\n+\n+\u0026uart3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart3_pins\u003e;\n+};\n+\n+\u0026pcie_x16 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pcie_x4a {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pcie_x4b {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026gpio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026io_pins \u0026mux_dcdc_i2c_pins \u0026mux_i2c3_pins \u0026mux_uart0_pins\u003e;\n+};\n+\n+\u0026gpio_a {\n+\tdcdc-i2c-mux-hog {\n+\t\tgpio-hog;\n+\t\tgpios = \u003c5 GPIO_ACTIVE_HIGH\u003e;\n+\t\toutput-low;\n+\t\tline-name = \"dcdc-i2c-mux\";\n+\t};\n+\n+\ti2c3-mux-hog {\n+\t\tgpio-hog;\n+\t\tgpios = \u003c6 GPIO_ACTIVE_HIGH\u003e;\n+\t\toutput-low;\n+\t\tline-name = \"i2c3-mux\";\n+\t};\n+\n+\tuart0-mux-hog {\n+\t\tgpio-hog;\n+\t\tgpios = \u003c7 GPIO_ACTIVE_HIGH\u003e;\n+\t\toutput-high;\n+\t\tline-name = \"uart0-mux\";\n+\t};\n+};\n+\n+\u0026ethernet {\n+\tphy-handle = \u003c\u0026phy0\u003e;\n+\t/*\n+\t * RTL8211F: board timing uses PHY strap delays; keep plain \"rgmii\".\n+\t * Enabling PHY internal delays via \"rgmii-id\" breaks Ethernet traffic.\n+\t */\n+\tphy-mode = \"rgmii\";\n+\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\n+\t\tphy0: phy@0 {\n+\t\t\treg = \u003c0\u003e;\n+\n+\t\t\tleds {\n+\t\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t\t#size-cells = \u003c0\u003e;\n+\n+\t\t\t\tled@1 {\n+\t\t\t\t\tlabel = \"eth-link\";\n+\t\t\t\t\treg = \u003c1\u003e;\n+\t\t\t\t\tcolor = \u003cLED_COLOR_ID_YELLOW\u003e;\n+\t\t\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\t\t\tdefault-state = \"keep\";\n+\t\t\t\t\tlinux,default-trigger = \"netdev\";\n+\t\t\t\t};\n+\n+\t\t\t\tled@2 {\n+\t\t\t\t\tlabel = \"eth-activity\";\n+\t\t\t\t\treg = \u003c2\u003e;\n+\t\t\t\t\tcolor = \u003cLED_COLOR_ID_GREEN\u003e;\n+\t\t\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\t\t\tdefault-state = \"keep\";\n+\t\t\t\t\tlinux,default-trigger = \"netdev\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h\nnew file mode 100644\nindex 0000000000000..4668e45d2335d\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h\n@@ -0,0 +1,63 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ */\n+\n+#ifndef _DP1000_PINCTRL_H\n+#define _DP1000_PINCTRL_H\n+\n+#define PA0\t\t0\n+#define PA1\t\t1\n+#define PA2\t\t2\n+#define PA3\t\t3\n+#define PA4\t\t4\n+#define PA5\t\t5\n+#define PA6\t\t6\n+#define PA7\t\t7\n+#define PA8\t\t8\n+#define PA9\t\t9\n+#define PA10\t\t10\n+#define PA11\t\t11\n+#define PA12\t\t12\n+#define PA13\t\t13\n+#define PA14\t\t14\n+#define PA15\t\t15\n+#define PB0\t\t16\n+#define PB1\t\t17\n+#define PB2\t\t18\n+#define PB3\t\t19\n+#define PB4\t\t20\n+#define PB5\t\t21\n+#define PB6\t\t22\n+#define PB7\t\t23\n+#define PC0\t\t24\n+#define PC1\t\t25\n+#define PC2\t\t26\n+#define PC3\t\t27\n+#define PC4\t\t28\n+#define PC5\t\t29\n+#define PC6\t\t30\n+#define PC7\t\t31\n+#define PD0\t\t32\n+#define PD1\t\t33\n+#define PD2\t\t34\n+#define PD3\t\t35\n+#define PD4\t\t36\n+#define PD5\t\t37\n+#define PD6\t\t38\n+#define PD7\t\t39\n+#define LPC0\t\t40\n+#define LPC1\t\t41\n+#define LPC2\t\t42\n+#define LPC3\t\t43\n+#define LPC4\t\t44\n+#define LPC5\t\t45\n+#define LPC6\t\t46\n+#define LPC7\t\t47\n+#define LPC8\t\t48\n+#define LPC9\t\t49\n+#define LPC10\t\t50\n+#define LPC11\t\t51\n+#define LPC12\t\t52\n+\n+#endif /* _DP1000_PINCTRL_H */\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi\nnew file mode 100644\nindex 0000000000000..ab927c6cd6146\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi\n@@ -0,0 +1,79 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ */\n+\n+#include \"dp1000.dtsi\"\n+#include \"dp1000-pinctrl.h\"\n+\n+\u0026pinctrl {\n+\ti2c0_pins: i2c0-pins {\n+\t\tpins = \u003cPA12 PA13\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c1_pins: i2c1-pins {\n+\t\tpins = \u003cPB6 PB7\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c2_pins: i2c2-pins {\n+\t\tpins = \u003cPC0 PC1\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\ti2c3_pins: i2c3-pins {\n+\t\tpins = \u003cPC2 PC3\u003e;\n+\t\tfunction = \"i2c\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tspi0_pins: spi0-pins {\n+\t\tpins = \u003cPD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7\u003e;\n+\t\tfunction = \"spi\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tspi1_pins: spi1-pins {\n+\t\tpins = \u003cPA0 PA1 PA2 PA3\u003e;\n+\t\tfunction = \"spi\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart0_pins: uart0-pins {\n+\t\tpins = \u003cPA8 PA9\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart1_pins: uart1-pins {\n+\t\tpins = \u003cPB4 PB5\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart2_pins: uart2-pins {\n+\t\tpins = \u003cPC4 PC5\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+\n+\tuart3_pins: uart3-pins {\n+\t\tpins = \u003cPC6 PC7\u003e;\n+\t\tfunction = \"uart\";\n+\t\tbias-pull-up;\n+\t\tdrive-strength = \u003c33\u003e;\n+\t};\n+};\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts\nnew file mode 100644\nindex 0000000000000..da831da819ef2\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts\n@@ -0,0 +1,114 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ */\n+\n+#include \"dp1000-shenrongda-m0-pinctrl.dtsi\"\n+#include \u003cdt-bindings/gpio/gpio.h\u003e\n+\n+/ {\n+\tmodel = \"Shenzhen Rongda M0 Board\";\n+\tcompatible = \"shenrongda,m0\", \"ultrarisc,dp1000\";\n+\n+\taliases {\n+\t\tserial0 = \u0026uart0;\n+\t\tserial1 = \u0026uart1;\n+\t\tserial2 = \u0026uart2;\n+\t\tserial3 = \u0026uart3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+};\n+\n+\u0026i2c0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c0_pins\u003e;\n+};\n+\n+\u0026i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c1_pins\u003e;\n+};\n+\n+\u0026i2c2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c2_pins\u003e;\n+\n+\trtc@32 {\n+\t\tcompatible = \"whwave,sd3078\";\n+\t\treg = \u003c0x32\u003e;\n+\t};\n+};\n+\n+\u0026i2c3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026i2c3_pins\u003e;\n+};\n+\n+\u0026spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026spi0_pins\u003e;\n+};\n+\n+\u0026spi1 {\n+\tnum-cs = \u003c1\u003e;\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026spi1_pins\u003e;\n+};\n+\n+\u0026uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart0_pins\u003e;\n+};\n+\n+\u0026uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart1_pins\u003e;\n+};\n+\n+\u0026uart2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart2_pins\u003e;\n+};\n+\n+\u0026uart3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = \u003c\u0026uart3_pins\u003e;\n+};\n+\n+\u0026pcie_x16 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pcie_x4a {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pcie_x4b {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026ethernet {\n+\tphy-handle = \u003c\u0026phy0\u003e;\n+\t/*\n+\t * YT8531 RGMII timing on this board requires no PHY internal delays.\n+\t * Using \"rgmii-id\" together with rx/tx-internal-delay-ps results in RX CRC\n+\t * errors and no usable traffic, so keep plain \"rgmii\" here.\n+\t */\n+\tphy-mode = \"rgmii\";\n+\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\n+\t\tphy0: phy@0 {\n+\t\t\treg = \u003c0\u003e;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi\nnew file mode 100644\nindex 0000000000000..470ab01e33b8a\n--- /dev/null\n+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi\n@@ -0,0 +1,899 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ */\n+\n+/dts-v1/;\n+\n+#include \u003cdt-bindings/clock/ultrarisc,dp1000-clk.h\u003e\n+\n+/ {\n+\tcompatible = \"ultrarisc,dp1000\";\n+\t#address-cells = \u003c2\u003e;\n+\t#size-cells = \u003c2\u003e;\n+\n+\tcpus {\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\t\ttimebase-frequency = \u003c10000000\u003e;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x0\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t       \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t       \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t       \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t       \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t       \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t       \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t       \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/*\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t */\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache0\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu0_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache0: l2-cache {\n+\t\t\t\t/*\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t */\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster0_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu1: cpu@1 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x1\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t       \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t       \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t       \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t       \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t       \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t       \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t       \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/*\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t */\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache1\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu1_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache1: l2-cache {\n+\t\t\t\t/*\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t */\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster0_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu2: cpu@2 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x2\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t       \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t       \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t       \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t       \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t       \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t       \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t       \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/*\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t */\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache2\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu2_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache2: l2-cache {\n+\t\t\t\t/*\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t */\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster0_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu3: cpu@3 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x3\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t       \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t       \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t       \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t       \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t       \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t       \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t       \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/*\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t */\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache3\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu3_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache3: l2-cache {\n+\t\t\t\t/*\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t */\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster0_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu4: cpu@10 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x10\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t       \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t       \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t       \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t       \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t       \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t       \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t       \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/*\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t */\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache4\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu4_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache4: l2-cache {\n+\t\t\t\t/*\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t */\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster1_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\t\tcpu5: cpu@11 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x11\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t       \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t       \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t       \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t       \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t       \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t       \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t       \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/*\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t */\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache5\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu5_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache5: l2-cache {\n+\t\t\t\t/*\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t */\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster1_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\t\tcpu6: cpu@12 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x12\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t       \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t       \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t       \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t       \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t       \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t       \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t       \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/*\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t */\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache6\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu6_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache6: l2-cache {\n+\t\t\t\t/*\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t */\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster1_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu7: cpu@13 {\n+\t\t\tcompatible = \"ultrarisc,cp100\", \"riscv\";\n+\t\t\treg = \u003c0x13\u003e;\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\triscv,isa-base = \"rv64i\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"b\", \"h\",\n+\t\t\t\t\t       \"zba\", \"zbb\", \"zbc\", \"zbs\", \"zicntr\",\n+\t\t\t\t\t       \"zicsr\", \"zifencei\", \"zihpm\", \"ziccif\",\n+\t\t\t\t\t       \"ziccrse\", \"ziccamoa\", \"za64rs\", \"zicbom\",\n+\t\t\t\t\t       \"zicbop\", \"zicboz\", \"zkt\", \"svade\",\n+\t\t\t\t\t       \"ssccptr\", \"sstvecd\", \"sscounterenw\",\n+\t\t\t\t\t       \"shcounterenw\", \"shtvala\", \"shvstvecd\",\n+\t\t\t\t\t       \"shvsatpa\", \"svvptc\";\n+\t\t\tmmu-type = \"riscv,sv48\";\n+\t\t\tclock-frequency = \u003c2000000000\u003e;\n+\t\t\t/*\n+\t\t\t * L1 I-cache and D-cache:\n+\t\t\t * block-size 64B\n+\t\t\t * 4-way set associative, size 64KB\n+\t\t\t * per-core.\n+\t\t\t */\n+\t\t\td-cache-block-size = \u003c64\u003e;\n+\t\t\td-cache-sets = \u003c256\u003e;\n+\t\t\td-cache-size = \u003c0x10000\u003e;\n+\t\t\ti-cache-block-size = \u003c64\u003e;\n+\t\t\ti-cache-sets = \u003c256\u003e;\n+\t\t\ti-cache-size = \u003c0x10000\u003e;\n+\t\t\tnext-level-cache = \u003c\u0026l2_cache7\u003e;\n+\t\t\triscv,cbom-block-size = \u003c64\u003e;\n+\t\t\triscv,cbop-block-size = \u003c64\u003e;\n+\t\t\triscv,cboz-block-size = \u003c64\u003e;\n+\n+\t\t\tcpu7_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t};\n+\n+\t\t\tl2_cache7: l2-cache {\n+\t\t\t\t/*\n+\t\t\t\t * L2 cache:\n+\t\t\t\t * cache-unified, block-size 64B\n+\t\t\t\t * 8-way set associative, size 512KB\n+\t\t\t\t * per-core.\n+\t\t\t\t */\n+\t\t\t\tcompatible = \"cache\";\n+\t\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\t\tcache-level = \u003c2\u003e;\n+\t\t\t\tcache-size = \u003c0x80000\u003e;\n+\t\t\t\tcache-sets = \u003c1024\u003e;\n+\t\t\t\tcache-unified;\n+\t\t\t\tnext-level-cache = \u003c\u0026cluster1_l3\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tcpu-map {\n+\t\t\tcluster0: cluster0 {\n+\t\t\t\tcore0 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu0\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore1 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu1\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore2 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu2\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore3 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu3\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcluster1: cluster1 {\n+\t\t\t\tcore0 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu4\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore1 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu5\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore2 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu6\u003e;\n+\t\t\t\t};\n+\n+\t\t\t\tcore3 {\n+\t\t\t\t\tcpu = \u003c\u0026cpu7\u003e;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tcluster0_l3: l3-cache0 {\n+\t\t\t/*\n+\t\t\t * L3 cache:\n+\t\t\t * cache-unified, block-size 64B\n+\t\t\t * 16-way set associative, size 4MB\n+\t\t\t * per-cluster.\n+\t\t\t */\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\tcache-level = \u003c3\u003e;\n+\t\t\tcache-size = \u003c0x400000\u003e;\n+\t\t\tcache-sets = \u003c0x1000\u003e;\n+\t\t\tcache-unified;\n+\t\t\tnext-level-cache = \u003c\u0026l4_cache\u003e;\n+\t\t};\n+\n+\t\tcluster1_l3: l3-cache1 {\n+\t\t\t/*\n+\t\t\t * L3 cache:\n+\t\t\t * cache-unified, block-size 64B\n+\t\t\t * 16-way set associative, size 4MB\n+\t\t\t * per-cluster.\n+\t\t\t */\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-block-size = \u003c64\u003e;\n+\t\t\tcache-level = \u003c3\u003e;\n+\t\t\tcache-size = \u003c0x400000\u003e;\n+\t\t\tcache-sets = \u003c0x1000\u003e;\n+\t\t\tcache-unified;\n+\t\t\tnext-level-cache = \u003c\u0026l4_cache\u003e;\n+\t\t};\n+\t};\n+\n+\tl4_cache: l4-cache {\n+\t\t/*\n+\t\t * L4 cache:\n+\t\t * cache-unified, block-size 64B\n+\t\t * 16-way set associative, size 16MB\n+\t\t * shared by the SoC.\n+\t\t */\n+\t\tcompatible = \"cache\";\n+\t\tcache-block-size = \u003c64\u003e;\n+\t\tcache-level = \u003c4\u003e;\n+\t\tcache-size = \u003c0x1000000\u003e;\n+\t\tcache-sets = \u003c0x4000\u003e;\n+\t\tcache-unified;\n+\t};\n+\n+\tosc_24m: clock-24m {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = \u003c0\u003e;\n+\t\tclock-frequency = \u003c24000000\u003e;\n+\t};\n+\n+\tsoc {\n+\t\tcompatible = \"simple-bus\";\n+\t\tranges;\n+\t\t#address-cells = \u003c2\u003e;\n+\t\t#size-cells = \u003c2\u003e;\n+\n+\t\tclint: clint@8000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-clint\", \"sifive,clint0\";\n+\t\t\treg = \u003c0x0 0x8000000 0x0 0x100000\u003e;\n+\t\t\tinterrupts-extended = \u003c\u0026cpu0_intc 3\u003e, \u003c\u0026cpu0_intc 7\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu1_intc 3\u003e, \u003c\u0026cpu1_intc 7\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu2_intc 3\u003e, \u003c\u0026cpu2_intc 7\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu3_intc 3\u003e, \u003c\u0026cpu3_intc 7\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu4_intc 3\u003e, \u003c\u0026cpu4_intc 7\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu5_intc 3\u003e, \u003c\u0026cpu5_intc 7\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu6_intc 3\u003e, \u003c\u0026cpu6_intc 7\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu7_intc 3\u003e, \u003c\u0026cpu7_intc 7\u003e;\n+\t\t};\n+\n+\t\tplic: plic@9000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-plic\", \"ultrarisc,cp100-plic\";\n+\t\t\treg = \u003c0x0 0x9000000 0x0 0x4000000\u003e;\n+\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\t#address-cells = \u003c0\u003e;\n+\t\t\tinterrupt-controller;\n+\t\t\tinterrupts-extended = \u003c\u0026cpu0_intc 11\u003e, \u003c\u0026cpu0_intc 9\u003e, \u003c\u0026cpu0_intc 10\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu1_intc 11\u003e, \u003c\u0026cpu1_intc 9\u003e, \u003c\u0026cpu1_intc 10\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu2_intc 11\u003e, \u003c\u0026cpu2_intc 9\u003e, \u003c\u0026cpu2_intc 10\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu3_intc 11\u003e, \u003c\u0026cpu3_intc 9\u003e, \u003c\u0026cpu3_intc 10\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu4_intc 11\u003e, \u003c\u0026cpu4_intc 9\u003e, \u003c\u0026cpu4_intc 10\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu5_intc 11\u003e, \u003c\u0026cpu5_intc 9\u003e, \u003c\u0026cpu5_intc 10\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu6_intc 11\u003e, \u003c\u0026cpu6_intc 9\u003e, \u003c\u0026cpu6_intc 10\u003e,\n+\t\t\t\t\t      \u003c\u0026cpu7_intc 11\u003e, \u003c\u0026cpu7_intc 9\u003e, \u003c\u0026cpu7_intc 10\u003e;\n+\t\t\triscv,ndev = \u003c160\u003e;\n+\t\t};\n+\n+\t\tclkc: clock-controller@11080000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-clk\";\n+\t\t\treg = \u003c0x0 0x11080000 0x0 0x1000\u003e;\n+\t\t\tclocks = \u003c\u0026osc_24m\u003e;\n+\t\t\t#clock-cells = \u003c1\u003e;\n+\t\t};\n+\n+\t\tpinctrl: pinctrl@11081000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-pinctrl\";\n+\t\t\treg = \u003c0x0 0x11081000 0x0 0x1000\u003e;\n+\t\t};\n+\n+\t\tgpio: gpio@20200000 {\n+\t\t\tcompatible = \"snps,dw-apb-gpio\";\n+\t\t\treg = \u003c0x0 0x20200000 0x0 0x1000\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-names = \"bus\", \"db\";\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\n+\t\t\tgpio_a: gpio-port@0 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\treg = \u003c0\u003e;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = \u003c2\u003e;\n+\t\t\t\tsnps,nr-gpios = \u003c16\u003e;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = \u003c2\u003e;\n+\t\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\t\tinterrupts = \u003c34\u003e;\n+\t\t\t\tgpio-ranges = \u003c\u0026pinctrl 0 0 16\u003e;\n+\t\t\t};\n+\n+\t\t\tgpio_b: gpio-port@1 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\treg = \u003c1\u003e;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = \u003c2\u003e;\n+\t\t\t\tsnps,nr-gpios = \u003c8\u003e;\n+\t\t\t\tgpio-ranges = \u003c\u0026pinctrl 0 16 8\u003e;\n+\t\t\t};\n+\n+\t\t\tgpio_c: gpio-port@2 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\treg = \u003c2\u003e;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = \u003c2\u003e;\n+\t\t\t\tsnps,nr-gpios = \u003c8\u003e;\n+\t\t\t\tgpio-ranges = \u003c\u0026pinctrl 0 24 8\u003e;\n+\t\t\t};\n+\n+\t\t\tgpio_d: gpio-port@3 {\n+\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n+\t\t\t\treg = \u003c3\u003e;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = \u003c2\u003e;\n+\t\t\t\tsnps,nr-gpios = \u003c8\u003e;\n+\t\t\t\tgpio-ranges = \u003c\u0026pinctrl 0 32 8\u003e;\n+\t\t\t};\n+\t\t};\n+\n+\t\tuart0: serial@20300000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-uart\", \"snps,dw-apb-uart\";\n+\t\t\treg = \u003c0x0 0x20300000 0x0 0x10000\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c17\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_UART0\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\t\treg-io-width = \u003c4\u003e;\n+\t\t\treg-shift = \u003c2\u003e;\n+\t\t};\n+\n+\t\tuart1: serial@20310000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-uart\", \"snps,dw-apb-uart\";\n+\t\t\treg = \u003c0x0 0x20310000 0x0 0x10000\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c18\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_UART1\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\t\treg-io-width = \u003c4\u003e;\n+\t\t\treg-shift = \u003c2\u003e;\n+\t\t};\n+\n+\t\tuart2: serial@20400000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-uart\", \"snps,dw-apb-uart\";\n+\t\t\treg = \u003c0x0 0x20400000 0x0 0x10000\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c25\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_UART2\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\t\treg-io-width = \u003c4\u003e;\n+\t\t\treg-shift = \u003c2\u003e;\n+\t\t};\n+\n+\t\tuart3: serial@20410000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-uart\", \"snps,dw-apb-uart\";\n+\t\t\treg = \u003c0x0 0x20410000 0x0 0x10000\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c26\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_UART3\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\t\treg-io-width = \u003c4\u003e;\n+\t\t\treg-shift = \u003c2\u003e;\n+\t\t};\n+\n+\t\tspi0: spi@20320000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-spi\", \"snps,dw-apb-ssi\";\n+\t\t\treg = \u003c0x0 0x20320000 0x0 0x1000\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_SPI0\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ssi_clk\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c19\u003e;\n+\t\t\tnum-cs = \u003c3\u003e;\n+\t\t};\n+\n+\t\tspi1: spi@20420000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-spi\", \"snps,dw-apb-ssi\";\n+\t\t\treg = \u003c0x0 0x20420000 0x0 0x1000\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_SPI1\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ssi_clk\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c27\u003e;\n+\t\t\tnum-cs = \u003c3\u003e;\n+\t\t};\n+\n+\t\ti2c0: i2c@20330000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = \u003c0x0 0x20330000 0x0 0x100\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-frequency = \u003c400000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_I2C0\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ref\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c20\u003e;\n+\t\t};\n+\n+\t\ti2c1: i2c@20340000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = \u003c0x0 0x20340000 0x0 0x100\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-frequency = \u003c400000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_I2C1\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ref\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c21\u003e;\n+\t\t};\n+\n+\t\ti2c2: i2c@20430000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = \u003c0x0 0x20430000 0x0 0x100\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-frequency = \u003c400000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_I2C2\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ref\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c28\u003e;\n+\t\t};\n+\n+\t\ti2c3: i2c@20440000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-i2c\", \"snps,designware-i2c\";\n+\t\t\treg = \u003c0x0 0x20440000 0x0 0x100\u003e;\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c0\u003e;\n+\t\t\tclock-frequency = \u003c400000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_I2C3\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"ref\", \"pclk\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c29\u003e;\n+\t\t};\n+\n+\t\tpcie_x16: pcie@21000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-pcie\";\n+\t\t\treg = \u003c0x0 0x21000000 0x0 0x1000000\u003e,\n+\t\t\t      \u003c0x0 0x4fff0000 0x0 0x10000\u003e;\n+\t\t\treg-names = \"dbi\", \"config\";\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_PCIEX16_CORE\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_DBI\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_AUX\u003e;\n+\t\t\tclock-names = \"core\", \"dbi\", \"aux\";\n+\t\t\tranges = \u003c0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000\u003e,\n+\t\t\t\t \u003c0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000\u003e,\n+\t\t\t\t \u003c0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000\u003e;\n+\t\t\t#address-cells = \u003c3\u003e;\n+\t\t\t#size-cells = \u003c2\u003e;\n+\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tbus-range = \u003c0x0 0xff\u003e;\n+\t\t\tnum-lanes = \u003c16\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c43\u003e, \u003c44\u003e, \u003c45\u003e, \u003c46\u003e, \u003c47\u003e;\n+\t\t\tinterrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+\t\t\tinterrupt-map-mask = \u003c0x0 0x0 0x0 0x7\u003e;\n+\t\t\tinterrupt-map = \u003c0x0 0x0 0x0 0x1 \u0026plic 44\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x2 \u0026plic 45\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x3 \u0026plic 46\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x4 \u0026plic 47\u003e;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpcie_x4a: pcie@23000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-pcie\";\n+\t\t\treg = \u003c0x0 0x23000000 0x0 0x1000000\u003e,\n+\t\t\t      \u003c0x0 0x6fff0000 0x0 0x10000\u003e;\n+\t\t\treg-names = \"dbi\", \"config\";\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_PCIEX4_CORE\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_DBI\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_AUX\u003e;\n+\t\t\tclock-names = \"core\", \"dbi\", \"aux\";\n+\t\t\tranges = \u003c0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000\u003e,\n+\t\t\t\t \u003c0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000\u003e,\n+\t\t\t\t \u003c0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000\u003e;\n+\t\t\t#address-cells = \u003c3\u003e;\n+\t\t\t#size-cells = \u003c2\u003e;\n+\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tbus-range = \u003c0x0 0xff\u003e;\n+\t\t\tnum-lanes = \u003c4\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c63\u003e, \u003c64\u003e, \u003c65\u003e, \u003c66\u003e, \u003c67\u003e;\n+\t\t\tinterrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+\t\t\tinterrupt-map-mask = \u003c0x0 0x0 0x0 0x7\u003e;\n+\t\t\tinterrupt-map = \u003c0x0 0x0 0x0 0x1 \u0026plic 64\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x2 \u0026plic 65\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x3 \u0026plic 66\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x4 \u0026plic 67\u003e;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpcie_x4b: pcie@24000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-pcie\";\n+\t\t\treg = \u003c0x0 0x24000000 0x0 0x1000000\u003e,\n+\t\t\t      \u003c0x0 0x7fff0000 0x0 0x10000\u003e;\n+\t\t\treg-names = \"dbi\", \"config\";\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_PCIEX4_CORE\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_DBI\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_PCIE_AUX\u003e;\n+\t\t\tclock-names = \"core\", \"dbi\", \"aux\";\n+\t\t\tranges = \u003c0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000\u003e,\n+\t\t\t\t \u003c0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000\u003e,\n+\t\t\t\t \u003c0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000\u003e;\n+\t\t\t#address-cells = \u003c3\u003e;\n+\t\t\t#size-cells = \u003c2\u003e;\n+\t\t\t#interrupt-cells = \u003c1\u003e;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tbus-range = \u003c0x0 0xff\u003e;\n+\t\t\tnum-lanes = \u003c4\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c73\u003e, \u003c74\u003e, \u003c75\u003e, \u003c76\u003e, \u003c77\u003e;\n+\t\t\tinterrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+\t\t\tinterrupt-map-mask = \u003c0x0 0x0 0x0 0x7\u003e;\n+\t\t\tinterrupt-map = \u003c0x0 0x0 0x0 0x1 \u0026plic 74\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x2 \u0026plic 75\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x3 \u0026plic 76\u003e,\n+\t\t\t\t\t\u003c0x0 0x0 0x0 0x4 \u0026plic 77\u003e;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tethernet: ethernet@38000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-gmac\", \"snps,dwmac-5.20\",\n+\t\t\t\t     \"snps,dwmac\";\n+\t\t\treg = \u003c0x0 0x38000000 0x0 0x1000000\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_GMAC\u003e;\n+\t\t\tclock-names = \"stmmaceth\";\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c84\u003e;\n+\t\t\tinterrupt-names = \"macirq\";\n+\t\t\tsnps,txpbl = \u003c8\u003e;\n+\t\t\tsnps,rxpbl = \u003c8\u003e;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdmac: dma-controller@39000000 {\n+\t\t\tcompatible = \"ultrarisc,dp1000-axi-dma\", \"snps,axi-dma-1.01a\";\n+\t\t\treg = \u003c0x0 0x39000000 0x0 0x400\u003e;\n+\t\t\tclocks = \u003c\u0026clkc DP1000_CLK_SYSPLL_DIV2\u003e,\n+\t\t\t\t \u003c\u0026clkc DP1000_CLK_SUBSYS\u003e;\n+\t\t\tclock-names = \"core-clk\", \"cfgr-clk\";\n+\t\t\t#dma-cells = \u003c1\u003e;\n+\t\t\tdma-channels = \u003c8\u003e;\n+\t\t\tinterrupt-parent = \u003c\u0026plic\u003e;\n+\t\t\tinterrupts = \u003c152\u003e;\n+\t\t\tsnps,dma-masters = \u003c1\u003e;\n+\t\t\tsnps,data-width = \u003c4\u003e;\n+\t\t\tsnps,block-size = \u003c512 512 512 512 512 512 512 512\u003e;\n+\t\t\tsnps,priority = \u003c0 1 2 3 4 5 6 7\u003e;\n+\t\t\tsnps,axi-max-burst-len = \u003c256\u003e;\n+\t\t};\n+\t};\n+};\n"
}

For your convenience, here is the diff of the changes:
commit abedfd5586c0d4e72334bde3b92597c566cb440f
Author: syz-cluster <triage@syzkaller.com>
Date:   Mon Aug 24 06:24:01 2026 +0000

    syz-cluster: applied patch under review

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 0a30a455b0ee5..f7b5891f41ae9 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -27,6 +27,7 @@ properties:
           - enum:
               - altr,agilex5-axi-dma
               - sophgo,cv1800b-axi-dma
+              - ultrarisc,dp1000-axi-dma
           - const: snps,axi-dma-1.01a
 
   reg:
diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index 467bdcbb85389..eee21ca8d7eda 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -44,6 +44,7 @@ properties:
               - mscc,ocelot-i2c
               - sophgo,sg2044-i2c
               - thead,th1520-i2c
+              - ultrarisc,dp1000-i2c
           - const: snps,designware-i2c
 
   reg:
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 2449311c6d28e..2ed4564ae99d7 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -119,6 +119,7 @@ properties:
         - starfive,jh7110-dwmac
         - tesla,fsd-ethqos
         - thead,th1520-gmac
+        - ultrarisc,dp1000-gmac
 
   reg:
     minItems: 1
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5feeb2203050a..85adf72899c9d 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -67,6 +67,7 @@ properties:
               - thead,c908
               - thead,c910
               - thead,c920
+              - ultrarisc,cp100
           - const: riscv
       - items:
           - enum:
@@ -117,8 +118,8 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
       VLEN/8, the vector register length in bytes. This property is required on
-      thead systems where the vector register length is not identical on all harts, or
-      the vlenb CSR is not available.
+      thead systems where the vector register length is not identical on all
+      harts, or the vlenb CSR is not available.
 
   # RISC-V has multiple properties for cache op block sizes as the sizes
   # differ between individual CBO extensions
@@ -151,8 +152,8 @@ anyOf:
       - riscv,isa-base
 
 dependencies:
-  riscv,isa-base: [ "riscv,isa-extensions" ]
-  riscv,isa-extensions: [ "riscv,isa-base" ]
+  riscv,isa-base: ["riscv,isa-extensions"]
+  riscv,isa-extensions: ["riscv,isa-base"]
 
 required:
   - interrupt-controller
diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml
new file mode 100644
index 0000000000000..a51e63dbeca33
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC SoC-based boards
+
+maintainers:
+  - Jia Wang <wangjia@ultrarisc.com>
+
+description:
+  UltraRISC DP1000 SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - shenrongda,m0
+              - milkv,titan
+          - const: ultrarisc,dp1000
+
+additionalProperties: true
+...
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index 1e70c6804d5d1..896205329d7e5 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -63,6 +63,7 @@ properties:
               - mscc,jaguar2-spi
               - sophgo,sg2042-spi
               - thead,th1520-spi
+              - ultrarisc,dp1000-spi
           - const: snps,dw-apb-ssi
       - description: Vendor controllers compatible with v1.01a
         items:
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 3673836e14dee..878f267d089b5 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -40,6 +40,7 @@ properties:
               - starfive,jh8100-clint   # StarFive JH8100
               - starfive,jhb100-clint   # StarFive JHB100
               - tenstorrent,blackhole-clint # Tenstorrent Blackhole
+              - ultrarisc,dp1000-clint  # UltraRISC DP1000
           - const: sifive,clint0        # SiFive CLINT v0 IP block
       - items:
           - {}
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6780b651acf80..61cd5e625a232 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1505,6 +1505,8 @@ patternProperties:
     description: SGX Sensortech
   "^sharp,.*":
     description: Sharp Corporation
+  "^shenrongda,.*":
+    description: Shenzhen Rongda Computer Co., Ltd.
   "^shift,.*":
     description: SHIFT GmbH
   "^shimafuji,.*":
diff --git a/MAINTAINERS b/MAINTAINERS
index e3f4e0fcdb3a7..a8f3c256bda24 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23517,6 +23517,14 @@ F:	include/dt-bindings/power/thead,th1520-power.h
 F:	include/dt-bindings/reset/thead,th1520-reset.h
 F:	include/linux/firmware/thead/thead,th1520-aon.h
 
+RISC-V ULTRARISC SoC SUPPORT
+M:	Jia Wang <wangjia@ultrarisc.com>
+L:	linux-riscv@lists.infradead.org
+S:	Supported
+T:	git https://github.com/ultrarisc/linux.git
+F:	Documentation/devicetree/bindings/riscv/ultrarisc.yaml
+F:	arch/riscv/boot/dts/ultrarisc/
+
 RNBD BLOCK DRIVERS
 M:	Md. Haris Iqbal <haris.iqbal@ionos.com>
 M:	Jack Wang <jinpu.wang@ionos.com>
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 69d8751fb17c8..7028829742518 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -12,3 +12,4 @@ subdir-y += spacemit
 subdir-y += starfive
 subdir-y += tenstorrent
 subdir-y += thead
+subdir-y += ultrarisc
diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile
new file mode 100644
index 0000000000000..dfd15c064d078
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb
+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi
new file mode 100644
index 0000000000000..7a812e40a2496
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include "dp1000.dtsi"
+#include "dp1000-pinctrl.h"
+
+&pinctrl {
+	i2c0_pins: i2c0-pins {
+		pins = <PA12 PA13>;
+		function = "i2c";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c1_pins: i2c1-pins {
+		pins = <PB6 PB7>;
+		function = "i2c";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c2_pins: i2c2-pins {
+		pins = <PC0 PC1>;
+		function = "i2c";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c3_pins: i2c3-pins {
+		pins = <PC2 PC3>;
+		function = "i2c";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	io_pins: io-pins {
+		pins = <PA10 PA15 PB0 PB1 PB2 PD6 PD7>;
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	gpio_keys_pins: gpio-keys-pins {
+		pins = <PA4 PA11 PA14>;
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	mux_dcdc_i2c_pins: mux-dcdc-i2c-pins {
+		pins = <PA5>;
+		function = "gpio";
+	};
+
+	mux_i2c3_pins: mux-i2c3-pins {
+		pins = <PA6>;
+		function = "gpio";
+	};
+
+	mux_uart0_pins: mux-uart0-pins {
+		pins = <PA7>;
+		function = "gpio";
+	};
+
+	spi0_pins: spi0-pins {
+		pins = <PD0 PD1 PD2 PD3 PD4 PD5>;
+		function = "spi";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	spi1_pins: spi1-pins {
+		pins = <PA0 PA1 PA2 PA3>;
+		function = "spi";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart0_pins: uart0-pins {
+		pins = <PA8 PA9>;
+		function = "uart";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart1_pins: uart1-pins {
+		pins = <PB4 PB5>;
+		function = "uart";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart2_pins: uart2-pins {
+		pins = <PC4 PC5>;
+		function = "uart";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart3_pins: uart3-pins {
+		pins = <PC6 PC7>;
+		function = "uart";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+};
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts
new file mode 100644
index 0000000000000..f1a0efee3d746
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include "dp1000-milkv-titan-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Milk-V Titan";
+	compatible = "milkv,titan", "ultrarisc,dp1000";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_keys_pins>;
+
+		key-wakeup-0 {
+			label = "Wake-Up";
+			gpios = <&gpio_a 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WAKEUP>;
+			linux,input-type = <EV_KEY>;
+			debounce-interval = <10>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_ASSERTED>;
+		};
+
+		key-wakeup-1 {
+			label = "Power";
+			gpios = <&gpio_a 11 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			linux,input-type = <EV_KEY>;
+			debounce-interval = <10>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_ASSERTED>;
+		};
+
+		key-wakeup-2 {
+			label = "Wake-Up-by-USB";
+			interrupts-extended = <&gpio_a 4 IRQ_TYPE_EDGE_FALLING>;
+			linux,code = <KEY_WAKEUP>;
+			linux,input-type = <EV_KEY>;
+			debounce-interval = <10>;
+			wakeup-source;
+		};
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+
+	rtc@68 {
+		compatible = "st,m41t11";
+		reg = <0x68>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+};
+
+&spi1 {
+	num-cs = <1>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
+
+&pcie_x16 {
+	status = "okay";
+};
+
+&pcie_x4a {
+	status = "okay";
+};
+
+&pcie_x4b {
+	status = "okay";
+};
+
+&gpio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&io_pins &mux_dcdc_i2c_pins &mux_i2c3_pins &mux_uart0_pins>;
+};
+
+&gpio_a {
+	dcdc-i2c-mux-hog {
+		gpio-hog;
+		gpios = <5 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "dcdc-i2c-mux";
+	};
+
+	i2c3-mux-hog {
+		gpio-hog;
+		gpios = <6 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "i2c3-mux";
+	};
+
+	uart0-mux-hog {
+		gpio-hog;
+		gpios = <7 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "uart0-mux";
+	};
+};
+
+&ethernet {
+	phy-handle = <&phy0>;
+	/*
+	 * RTL8211F: board timing uses PHY strap delays; keep plain "rgmii".
+	 * Enabling PHY internal delays via "rgmii-id" breaks Ethernet traffic.
+	 */
+	phy-mode = "rgmii";
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: phy@0 {
+			reg = <0>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@1 {
+					label = "eth-link";
+					reg = <1>;
+					color = <LED_COLOR_ID_YELLOW>;
+					function = LED_FUNCTION_INDICATOR;
+					default-state = "keep";
+					linux,default-trigger = "netdev";
+				};
+
+				led@2 {
+					label = "eth-activity";
+					reg = <2>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_ACTIVITY;
+					default-state = "keep";
+					linux,default-trigger = "netdev";
+				};
+			};
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h
new file mode 100644
index 0000000000000..4668e45d2335d
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#ifndef _DP1000_PINCTRL_H
+#define _DP1000_PINCTRL_H
+
+#define PA0		0
+#define PA1		1
+#define PA2		2
+#define PA3		3
+#define PA4		4
+#define PA5		5
+#define PA6		6
+#define PA7		7
+#define PA8		8
+#define PA9		9
+#define PA10		10
+#define PA11		11
+#define PA12		12
+#define PA13		13
+#define PA14		14
+#define PA15		15
+#define PB0		16
+#define PB1		17
+#define PB2		18
+#define PB3		19
+#define PB4		20
+#define PB5		21
+#define PB6		22
+#define PB7		23
+#define PC0		24
+#define PC1		25
+#define PC2		26
+#define PC3		27
+#define PC4		28
+#define PC5		29
+#define PC6		30
+#define PC7		31
+#define PD0		32
+#define PD1		33
+#define PD2		34
+#define PD3		35
+#define PD4		36
+#define PD5		37
+#define PD6		38
+#define PD7		39
+#define LPC0		40
+#define LPC1		41
+#define LPC2		42
+#define LPC3		43
+#define LPC4		44
+#define LPC5		45
+#define LPC6		46
+#define LPC7		47
+#define LPC8		48
+#define LPC9		49
+#define LPC10		50
+#define LPC11		51
+#define LPC12		52
+
+#endif /* _DP1000_PINCTRL_H */
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi
new file mode 100644
index 0000000000000..ab927c6cd6146
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include "dp1000.dtsi"
+#include "dp1000-pinctrl.h"
+
+&pinctrl {
+	i2c0_pins: i2c0-pins {
+		pins = <PA12 PA13>;
+		function = "i2c";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c1_pins: i2c1-pins {
+		pins = <PB6 PB7>;
+		function = "i2c";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c2_pins: i2c2-pins {
+		pins = <PC0 PC1>;
+		function = "i2c";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c3_pins: i2c3-pins {
+		pins = <PC2 PC3>;
+		function = "i2c";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	spi0_pins: spi0-pins {
+		pins = <PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7>;
+		function = "spi";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	spi1_pins: spi1-pins {
+		pins = <PA0 PA1 PA2 PA3>;
+		function = "spi";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart0_pins: uart0-pins {
+		pins = <PA8 PA9>;
+		function = "uart";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart1_pins: uart1-pins {
+		pins = <PB4 PB5>;
+		function = "uart";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart2_pins: uart2-pins {
+		pins = <PC4 PC5>;
+		function = "uart";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart3_pins: uart3-pins {
+		pins = <PC6 PC7>;
+		function = "uart";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+};
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts
new file mode 100644
index 0000000000000..da831da819ef2
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include "dp1000-shenrongda-m0-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Shenzhen Rongda M0 Board";
+	compatible = "shenrongda,m0", "ultrarisc,dp1000";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+
+	rtc@32 {
+		compatible = "whwave,sd3078";
+		reg = <0x32>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+};
+
+&spi1 {
+	num-cs = <1>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
+
+&pcie_x16 {
+	status = "okay";
+};
+
+&pcie_x4a {
+	status = "okay";
+};
+
+&pcie_x4b {
+	status = "okay";
+};
+
+&ethernet {
+	phy-handle = <&phy0>;
+	/*
+	 * YT8531 RGMII timing on this board requires no PHY internal delays.
+	 * Using "rgmii-id" together with rx/tx-internal-delay-ps results in RX CRC
+	 * errors and no usable traffic, so keep plain "rgmii" here.
+	 */
+	phy-mode = "rgmii";
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: phy@0 {
+			reg = <0>;
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
new file mode 100644
index 0000000000000..470ab01e33b8a
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
@@ -0,0 +1,899 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/ultrarisc,dp1000-clk.h>
+
+/ {
+	compatible = "ultrarisc,dp1000";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <10000000>;
+
+		cpu0: cpu@0 {
+			compatible = "ultrarisc,cp100", "riscv";
+			reg = <0x0>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+					       "zba", "zbb", "zbc", "zbs", "zicntr",
+					       "zicsr", "zifencei", "zihpm", "ziccif",
+					       "ziccrse", "ziccamoa", "za64rs", "zicbom",
+					       "zicbop", "zicboz", "zkt", "svade",
+					       "ssccptr", "sstvecd", "sscounterenw",
+					       "shcounterenw", "shtvala", "shvstvecd",
+					       "shvsatpa", "svvptc";
+			mmu-type = "riscv,sv48";
+			clock-frequency = <2000000000>;
+			/*
+			 * L1 I-cache and D-cache:
+			 * block-size 64B
+			 * 4-way set associative, size 64KB
+			 * per-core.
+			 */
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <0x10000>;
+			next-level-cache = <&l2_cache0>;
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			l2_cache0: l2-cache {
+				/*
+				 * L2 cache:
+				 * cache-unified, block-size 64B
+				 * 8-way set associative, size 512KB
+				 * per-core.
+				 */
+				compatible = "cache";
+				cache-block-size = <64>;
+				cache-level = <2>;
+				cache-size = <0x80000>;
+				cache-sets = <1024>;
+				cache-unified;
+				next-level-cache = <&cluster0_l3>;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "ultrarisc,cp100", "riscv";
+			reg = <0x1>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+					       "zba", "zbb", "zbc", "zbs", "zicntr",
+					       "zicsr", "zifencei", "zihpm", "ziccif",
+					       "ziccrse", "ziccamoa", "za64rs", "zicbom",
+					       "zicbop", "zicboz", "zkt", "svade",
+					       "ssccptr", "sstvecd", "sscounterenw",
+					       "shcounterenw", "shtvala", "shvstvecd",
+					       "shvsatpa", "svvptc";
+			mmu-type = "riscv,sv48";
+			clock-frequency = <2000000000>;
+			/*
+			 * L1 I-cache and D-cache:
+			 * block-size 64B
+			 * 4-way set associative, size 64KB
+			 * per-core.
+			 */
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <0x10000>;
+			next-level-cache = <&l2_cache1>;
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			l2_cache1: l2-cache {
+				/*
+				 * L2 cache:
+				 * cache-unified, block-size 64B
+				 * 8-way set associative, size 512KB
+				 * per-core.
+				 */
+				compatible = "cache";
+				cache-block-size = <64>;
+				cache-level = <2>;
+				cache-size = <0x80000>;
+				cache-sets = <1024>;
+				cache-unified;
+				next-level-cache = <&cluster0_l3>;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "ultrarisc,cp100", "riscv";
+			reg = <0x2>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+					       "zba", "zbb", "zbc", "zbs", "zicntr",
+					       "zicsr", "zifencei", "zihpm", "ziccif",
+					       "ziccrse", "ziccamoa", "za64rs", "zicbom",
+					       "zicbop", "zicboz", "zkt", "svade",
+					       "ssccptr", "sstvecd", "sscounterenw",
+					       "shcounterenw", "shtvala", "shvstvecd",
+					       "shvsatpa", "svvptc";
+			mmu-type = "riscv,sv48";
+			clock-frequency = <2000000000>;
+			/*
+			 * L1 I-cache and D-cache:
+			 * block-size 64B
+			 * 4-way set associative, size 64KB
+			 * per-core.
+			 */
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <0x10000>;
+			next-level-cache = <&l2_cache2>;
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			l2_cache2: l2-cache {
+				/*
+				 * L2 cache:
+				 * cache-unified, block-size 64B
+				 * 8-way set associative, size 512KB
+				 * per-core.
+				 */
+				compatible = "cache";
+				cache-block-size = <64>;
+				cache-level = <2>;
+				cache-size = <0x80000>;
+				cache-sets = <1024>;
+				cache-unified;
+				next-level-cache = <&cluster0_l3>;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "ultrarisc,cp100", "riscv";
+			reg = <0x3>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+					       "zba", "zbb", "zbc", "zbs", "zicntr",
+					       "zicsr", "zifencei", "zihpm", "ziccif",
+					       "ziccrse", "ziccamoa", "za64rs", "zicbom",
+					       "zicbop", "zicboz", "zkt", "svade",
+					       "ssccptr", "sstvecd", "sscounterenw",
+					       "shcounterenw", "shtvala", "shvstvecd",
+					       "shvsatpa", "svvptc";
+			mmu-type = "riscv,sv48";
+			clock-frequency = <2000000000>;
+			/*
+			 * L1 I-cache and D-cache:
+			 * block-size 64B
+			 * 4-way set associative, size 64KB
+			 * per-core.
+			 */
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <0x10000>;
+			next-level-cache = <&l2_cache3>;
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			l2_cache3: l2-cache {
+				/*
+				 * L2 cache:
+				 * cache-unified, block-size 64B
+				 * 8-way set associative, size 512KB
+				 * per-core.
+				 */
+				compatible = "cache";
+				cache-block-size = <64>;
+				cache-level = <2>;
+				cache-size = <0x80000>;
+				cache-sets = <1024>;
+				cache-unified;
+				next-level-cache = <&cluster0_l3>;
+			};
+		};
+
+		cpu4: cpu@10 {
+			compatible = "ultrarisc,cp100", "riscv";
+			reg = <0x10>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+					       "zba", "zbb", "zbc", "zbs", "zicntr",
+					       "zicsr", "zifencei", "zihpm", "ziccif",
+					       "ziccrse", "ziccamoa", "za64rs", "zicbom",
+					       "zicbop", "zicboz", "zkt", "svade",
+					       "ssccptr", "sstvecd", "sscounterenw",
+					       "shcounterenw", "shtvala", "shvstvecd",
+					       "shvsatpa", "svvptc";
+			mmu-type = "riscv,sv48";
+			clock-frequency = <2000000000>;
+			/*
+			 * L1 I-cache and D-cache:
+			 * block-size 64B
+			 * 4-way set associative, size 64KB
+			 * per-core.
+			 */
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <0x10000>;
+			next-level-cache = <&l2_cache4>;
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			l2_cache4: l2-cache {
+				/*
+				 * L2 cache:
+				 * cache-unified, block-size 64B
+				 * 8-way set associative, size 512KB
+				 * per-core.
+				 */
+				compatible = "cache";
+				cache-block-size = <64>;
+				cache-level = <2>;
+				cache-size = <0x80000>;
+				cache-sets = <1024>;
+				cache-unified;
+				next-level-cache = <&cluster1_l3>;
+			};
+		};
+		cpu5: cpu@11 {
+			compatible = "ultrarisc,cp100", "riscv";
+			reg = <0x11>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+					       "zba", "zbb", "zbc", "zbs", "zicntr",
+					       "zicsr", "zifencei", "zihpm", "ziccif",
+					       "ziccrse", "ziccamoa", "za64rs", "zicbom",
+					       "zicbop", "zicboz", "zkt", "svade",
+					       "ssccptr", "sstvecd", "sscounterenw",
+					       "shcounterenw", "shtvala", "shvstvecd",
+					       "shvsatpa", "svvptc";
+			mmu-type = "riscv,sv48";
+			clock-frequency = <2000000000>;
+			/*
+			 * L1 I-cache and D-cache:
+			 * block-size 64B
+			 * 4-way set associative, size 64KB
+			 * per-core.
+			 */
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <0x10000>;
+			next-level-cache = <&l2_cache5>;
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			l2_cache5: l2-cache {
+				/*
+				 * L2 cache:
+				 * cache-unified, block-size 64B
+				 * 8-way set associative, size 512KB
+				 * per-core.
+				 */
+				compatible = "cache";
+				cache-block-size = <64>;
+				cache-level = <2>;
+				cache-size = <0x80000>;
+				cache-sets = <1024>;
+				cache-unified;
+				next-level-cache = <&cluster1_l3>;
+			};
+		};
+		cpu6: cpu@12 {
+			compatible = "ultrarisc,cp100", "riscv";
+			reg = <0x12>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+					       "zba", "zbb", "zbc", "zbs", "zicntr",
+					       "zicsr", "zifencei", "zihpm", "ziccif",
+					       "ziccrse", "ziccamoa", "za64rs", "zicbom",
+					       "zicbop", "zicboz", "zkt", "svade",
+					       "ssccptr", "sstvecd", "sscounterenw",
+					       "shcounterenw", "shtvala", "shvstvecd",
+					       "shvsatpa", "svvptc";
+			mmu-type = "riscv,sv48";
+			clock-frequency = <2000000000>;
+			/*
+			 * L1 I-cache and D-cache:
+			 * block-size 64B
+			 * 4-way set associative, size 64KB
+			 * per-core.
+			 */
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <0x10000>;
+			next-level-cache = <&l2_cache6>;
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			l2_cache6: l2-cache {
+				/*
+				 * L2 cache:
+				 * cache-unified, block-size 64B
+				 * 8-way set associative, size 512KB
+				 * per-core.
+				 */
+				compatible = "cache";
+				cache-block-size = <64>;
+				cache-level = <2>;
+				cache-size = <0x80000>;
+				cache-sets = <1024>;
+				cache-unified;
+				next-level-cache = <&cluster1_l3>;
+			};
+		};
+
+		cpu7: cpu@13 {
+			compatible = "ultrarisc,cp100", "riscv";
+			reg = <0x13>;
+			device_type = "cpu";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+					       "zba", "zbb", "zbc", "zbs", "zicntr",
+					       "zicsr", "zifencei", "zihpm", "ziccif",
+					       "ziccrse", "ziccamoa", "za64rs", "zicbom",
+					       "zicbop", "zicboz", "zkt", "svade",
+					       "ssccptr", "sstvecd", "sscounterenw",
+					       "shcounterenw", "shtvala", "shvstvecd",
+					       "shvsatpa", "svvptc";
+			mmu-type = "riscv,sv48";
+			clock-frequency = <2000000000>;
+			/*
+			 * L1 I-cache and D-cache:
+			 * block-size 64B
+			 * 4-way set associative, size 64KB
+			 * per-core.
+			 */
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <0x10000>;
+			next-level-cache = <&l2_cache7>;
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			l2_cache7: l2-cache {
+				/*
+				 * L2 cache:
+				 * cache-unified, block-size 64B
+				 * 8-way set associative, size 512KB
+				 * per-core.
+				 */
+				compatible = "cache";
+				cache-block-size = <64>;
+				cache-level = <2>;
+				cache-size = <0x80000>;
+				cache-sets = <1024>;
+				cache-unified;
+				next-level-cache = <&cluster1_l3>;
+			};
+		};
+
+		cpu-map {
+			cluster0: cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1: cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+
+				core2 {
+					cpu = <&cpu6>;
+				};
+
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cluster0_l3: l3-cache0 {
+			/*
+			 * L3 cache:
+			 * cache-unified, block-size 64B
+			 * 16-way set associative, size 4MB
+			 * per-cluster.
+			 */
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <3>;
+			cache-size = <0x400000>;
+			cache-sets = <0x1000>;
+			cache-unified;
+			next-level-cache = <&l4_cache>;
+		};
+
+		cluster1_l3: l3-cache1 {
+			/*
+			 * L3 cache:
+			 * cache-unified, block-size 64B
+			 * 16-way set associative, size 4MB
+			 * per-cluster.
+			 */
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <3>;
+			cache-size = <0x400000>;
+			cache-sets = <0x1000>;
+			cache-unified;
+			next-level-cache = <&l4_cache>;
+		};
+	};
+
+	l4_cache: l4-cache {
+		/*
+		 * L4 cache:
+		 * cache-unified, block-size 64B
+		 * 16-way set associative, size 16MB
+		 * shared by the SoC.
+		 */
+		compatible = "cache";
+		cache-block-size = <64>;
+		cache-level = <4>;
+		cache-size = <0x1000000>;
+		cache-sets = <0x4000>;
+		cache-unified;
+	};
+
+	osc_24m: clock-24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		clint: clint@8000000 {
+			compatible = "ultrarisc,dp1000-clint", "sifive,clint0";
+			reg = <0x0 0x8000000 0x0 0x100000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>,
+					      <&cpu5_intc 3>, <&cpu5_intc 7>,
+					      <&cpu6_intc 3>, <&cpu6_intc 7>,
+					      <&cpu7_intc 3>, <&cpu7_intc 7>;
+		};
+
+		plic: plic@9000000 {
+			compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic";
+			reg = <0x0 0x9000000 0x0 0x4000000>;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu0_intc 10>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu1_intc 10>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu2_intc 10>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>, <&cpu3_intc 10>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>, <&cpu4_intc 10>,
+					      <&cpu5_intc 11>, <&cpu5_intc 9>, <&cpu5_intc 10>,
+					      <&cpu6_intc 11>, <&cpu6_intc 9>, <&cpu6_intc 10>,
+					      <&cpu7_intc 11>, <&cpu7_intc 9>, <&cpu7_intc 10>;
+			riscv,ndev = <160>;
+		};
+
+		clkc: clock-controller@11080000 {
+			compatible = "ultrarisc,dp1000-clk";
+			reg = <0x0 0x11080000 0x0 0x1000>;
+			clocks = <&osc_24m>;
+			#clock-cells = <1>;
+		};
+
+		pinctrl: pinctrl@11081000 {
+			compatible = "ultrarisc,dp1000-pinctrl";
+			reg = <0x0 0x11081000 0x0 0x1000>;
+		};
+
+		gpio: gpio@20200000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0x20200000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "bus", "db";
+			clocks = <&clkc DP1000_CLK_SUBSYS>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+
+			gpio_a: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <16>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&plic>;
+				interrupts = <34>;
+				gpio-ranges = <&pinctrl 0 0 16>;
+			};
+
+			gpio_b: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <8>;
+				gpio-ranges = <&pinctrl 0 16 8>;
+			};
+
+			gpio_c: gpio-port@2 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <2>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <8>;
+				gpio-ranges = <&pinctrl 0 24 8>;
+			};
+
+			gpio_d: gpio-port@3 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <3>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <8>;
+				gpio-ranges = <&pinctrl 0 32 8>;
+			};
+		};
+
+		uart0: serial@20300000 {
+			compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart";
+			reg = <0x0 0x20300000 0x0 0x10000>;
+			interrupt-parent = <&plic>;
+			interrupts = <17>;
+			clocks = <&clkc DP1000_CLK_UART0>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-io-width = <4>;
+			reg-shift = <2>;
+		};
+
+		uart1: serial@20310000 {
+			compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart";
+			reg = <0x0 0x20310000 0x0 0x10000>;
+			interrupt-parent = <&plic>;
+			interrupts = <18>;
+			clocks = <&clkc DP1000_CLK_UART1>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-io-width = <4>;
+			reg-shift = <2>;
+		};
+
+		uart2: serial@20400000 {
+			compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart";
+			reg = <0x0 0x20400000 0x0 0x10000>;
+			interrupt-parent = <&plic>;
+			interrupts = <25>;
+			clocks = <&clkc DP1000_CLK_UART2>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-io-width = <4>;
+			reg-shift = <2>;
+		};
+
+		uart3: serial@20410000 {
+			compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart";
+			reg = <0x0 0x20410000 0x0 0x10000>;
+			interrupt-parent = <&plic>;
+			interrupts = <26>;
+			clocks = <&clkc DP1000_CLK_UART3>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "baudclk", "apb_pclk";
+			reg-io-width = <4>;
+			reg-shift = <2>;
+		};
+
+		spi0: spi@20320000 {
+			compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi";
+			reg = <0x0 0x20320000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clkc DP1000_CLK_SPI0>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "ssi_clk", "pclk";
+			interrupt-parent = <&plic>;
+			interrupts = <19>;
+			num-cs = <3>;
+		};
+
+		spi1: spi@20420000 {
+			compatible = "ultrarisc,dp1000-spi", "snps,dw-apb-ssi";
+			reg = <0x0 0x20420000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clkc DP1000_CLK_SPI1>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "ssi_clk", "pclk";
+			interrupt-parent = <&plic>;
+			interrupts = <27>;
+			num-cs = <3>;
+		};
+
+		i2c0: i2c@20330000 {
+			compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c";
+			reg = <0x0 0x20330000 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&clkc DP1000_CLK_I2C0>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "ref", "pclk";
+			interrupt-parent = <&plic>;
+			interrupts = <20>;
+		};
+
+		i2c1: i2c@20340000 {
+			compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c";
+			reg = <0x0 0x20340000 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&clkc DP1000_CLK_I2C1>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "ref", "pclk";
+			interrupt-parent = <&plic>;
+			interrupts = <21>;
+		};
+
+		i2c2: i2c@20430000 {
+			compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c";
+			reg = <0x0 0x20430000 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&clkc DP1000_CLK_I2C2>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "ref", "pclk";
+			interrupt-parent = <&plic>;
+			interrupts = <28>;
+		};
+
+		i2c3: i2c@20440000 {
+			compatible = "ultrarisc,dp1000-i2c", "snps,designware-i2c";
+			reg = <0x0 0x20440000 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&clkc DP1000_CLK_I2C3>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "ref", "pclk";
+			interrupt-parent = <&plic>;
+			interrupts = <29>;
+		};
+
+		pcie_x16: pcie@21000000 {
+			compatible = "ultrarisc,dp1000-pcie";
+			reg = <0x0 0x21000000 0x0 0x1000000>,
+			      <0x0 0x4fff0000 0x0 0x10000>;
+			reg-names = "dbi", "config";
+			clocks = <&clkc DP1000_CLK_PCIEX16_CORE>,
+				 <&clkc DP1000_CLK_PCIE_DBI>,
+				 <&clkc DP1000_CLK_PCIE_AUX>;
+			clock-names = "core", "dbi", "aux";
+			ranges = <0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000>,
+				 <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,
+				 <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			dma-coherent;
+			bus-range = <0x0 0xff>;
+			num-lanes = <16>;
+			interrupt-parent = <&plic>;
+			interrupts = <43>, <44>, <45>, <46>, <47>;
+			interrupt-names = "msi", "inta", "intb", "intc", "intd";
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+					<0x0 0x0 0x0 0x2 &plic 45>,
+					<0x0 0x0 0x0 0x3 &plic 46>,
+					<0x0 0x0 0x0 0x4 &plic 47>;
+
+			status = "disabled";
+		};
+
+		pcie_x4a: pcie@23000000 {
+			compatible = "ultrarisc,dp1000-pcie";
+			reg = <0x0 0x23000000 0x0 0x1000000>,
+			      <0x0 0x6fff0000 0x0 0x10000>;
+			reg-names = "dbi", "config";
+			clocks = <&clkc DP1000_CLK_PCIEX4_CORE>,
+				 <&clkc DP1000_CLK_PCIE_DBI>,
+				 <&clkc DP1000_CLK_PCIE_AUX>;
+			clock-names = "core", "dbi", "aux";
+			ranges = <0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000>,
+				 <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>,
+				 <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			dma-coherent;
+			bus-range = <0x0 0xff>;
+			num-lanes = <4>;
+			interrupt-parent = <&plic>;
+			interrupts = <63>, <64>, <65>, <66>, <67>;
+			interrupt-names = "msi", "inta", "intb", "intc", "intd";
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>,
+					<0x0 0x0 0x0 0x2 &plic 65>,
+					<0x0 0x0 0x0 0x3 &plic 66>,
+					<0x0 0x0 0x0 0x4 &plic 67>;
+
+			status = "disabled";
+		};
+
+		pcie_x4b: pcie@24000000 {
+			compatible = "ultrarisc,dp1000-pcie";
+			reg = <0x0 0x24000000 0x0 0x1000000>,
+			      <0x0 0x7fff0000 0x0 0x10000>;
+			reg-names = "dbi", "config";
+			clocks = <&clkc DP1000_CLK_PCIEX4_CORE>,
+				 <&clkc DP1000_CLK_PCIE_DBI>,
+				 <&clkc DP1000_CLK_PCIE_AUX>;
+			clock-names = "core", "dbi", "aux";
+			ranges = <0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000>,
+				 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>,
+				 <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			dma-coherent;
+			bus-range = <0x0 0xff>;
+			num-lanes = <4>;
+			interrupt-parent = <&plic>;
+			interrupts = <73>, <74>, <75>, <76>, <77>;
+			interrupt-names = "msi", "inta", "intb", "intc", "intd";
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>,
+					<0x0 0x0 0x0 0x2 &plic 75>,
+					<0x0 0x0 0x0 0x3 &plic 76>,
+					<0x0 0x0 0x0 0x4 &plic 77>;
+
+			status = "disabled";
+		};
+
+		ethernet: ethernet@38000000 {
+			compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.20",
+				     "snps,dwmac";
+			reg = <0x0 0x38000000 0x0 0x1000000>;
+			clocks = <&clkc DP1000_CLK_GMAC>;
+			clock-names = "stmmaceth";
+			interrupt-parent = <&plic>;
+			interrupts = <84>;
+			interrupt-names = "macirq";
+			snps,txpbl = <8>;
+			snps,rxpbl = <8>;
+
+			status = "disabled";
+		};
+
+		dmac: dma-controller@39000000 {
+			compatible = "ultrarisc,dp1000-axi-dma", "snps,axi-dma-1.01a";
+			reg = <0x0 0x39000000 0x0 0x400>;
+			clocks = <&clkc DP1000_CLK_SYSPLL_DIV2>,
+				 <&clkc DP1000_CLK_SUBSYS>;
+			clock-names = "core-clk", "cfgr-clk";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+			interrupt-parent = <&plic>;
+			interrupts = <152>;
+			snps,dma-masters = <1>;
+			snps,data-width = <4>;
+			snps,block-size = <512 512 512 512 512 512 512 512>;
+			snps,priority = <0 1 2 3 4 5 6 7>;
+			snps,axi-max-burst-len = <256>;
+		};
+	};
+};