AI Trajectory

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies power management and probe logic for the Marvell NETA Buffer Manager (mvneta_bm), which is a platform device specific to Marvell Armada SoCs. This hardware is not emulated in standard virtualized environments (like QEMU's 'virt' machine) used by fuzzers, making the code unreachable during fuzzing.",
  "WorthFuzzing": false
}

null

{
  "PatchDiff": "commit 125e7058d42fe244698b1d45fe3ff232edd1b03f\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Tue Jun 30 07:21:31 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c\nindex 744d6585a949d1..543e566425c1e5 100644\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -5678,6 +5678,24 @@ static int mvneta_probe(struct platform_device *pdev)\n \t\t\t\t\t \"use SW buffer management\\n\");\n \t\t\t\tmvneta_bm_put(pp-\u003ebm_priv);\n \t\t\t\tpp-\u003ebm_priv = NULL;\n+\t\t\t} else if (!device_link_add(\u0026pdev-\u003edev,\n+\t\t\t\t\t\t    \u0026pp-\u003ebm_priv-\u003epdev-\u003edev,\n+\t\t\t\t\t\t    DL_FLAG_AUTOREMOVE_CONSUMER)) {\n+\t\t\t\t/*\n+\t\t\t\t * Link guarantees BM resumes before mvneta.\n+\t\t\t\t * Without it, BM may not be ready when\n+\t\t\t\t * mvneta_bm_port_init() runs on resume,\n+\t\t\t\t * causing stale buffer addresses and a crash.\n+\t\t\t\t * Fall back to SW management to be safe.\n+\t\t\t\t */\n+\t\t\t\tdev_warn(\u0026pdev-\u003edev,\n+\t\t\t\t\t \"failed to link to BM, use SW buffer management\\n\");\n+\t\t\t\tmvneta_bm_pool_destroy(pp-\u003ebm_priv,\n+\t\t\t\t\t\t       pp-\u003epool_long, 1 \u003c\u003c pp-\u003eid);\n+\t\t\t\tmvneta_bm_pool_destroy(pp-\u003ebm_priv,\n+\t\t\t\t\t\t       pp-\u003epool_short, 1 \u003c\u003c pp-\u003eid);\n+\t\t\t\tmvneta_bm_put(pp-\u003ebm_priv);\n+\t\t\t\tpp-\u003ebm_priv = NULL;\n \t\t\t}\n \t\t}\n \t\t/* Set RX packet offset correction for platforms, whose\ndiff --git a/drivers/net/ethernet/marvell/mvneta_bm.c b/drivers/net/ethernet/marvell/mvneta_bm.c\nindex 6bb38049491906..e0c693c0a91063 100644\n--- a/drivers/net/ethernet/marvell/mvneta_bm.c\n+++ b/drivers/net/ethernet/marvell/mvneta_bm.c\n@@ -129,6 +129,7 @@ static int mvneta_bm_pool_create(struct mvneta_bm *priv,\n \tif (!IS_ALIGNED((u32)bm_pool-\u003evirt_addr, MVNETA_BM_POOL_PTR_ALIGN)) {\n \t\tdma_free_coherent(\u0026pdev-\u003edev, size_bytes, bm_pool-\u003evirt_addr,\n \t\t\t\t  bm_pool-\u003ephys_addr);\n+\t\tbm_pool-\u003evirt_addr = NULL;\n \t\tdev_err(\u0026pdev-\u003edev, \"BM pool %d is not %d bytes aligned\\n\",\n \t\t\tbm_pool-\u003eid, MVNETA_BM_POOL_PTR_ALIGN);\n \t\treturn -ENOMEM;\n@@ -139,6 +140,7 @@ static int mvneta_bm_pool_create(struct mvneta_bm *priv,\n \tif (err \u003c 0) {\n \t\tdma_free_coherent(\u0026pdev-\u003edev, size_bytes, bm_pool-\u003evirt_addr,\n \t\t\t\t  bm_pool-\u003ephys_addr);\n+\t\tbm_pool-\u003evirt_addr = NULL;\n \t\treturn err;\n \t}\n \n@@ -477,6 +479,75 @@ static void mvneta_bm_remove(struct platform_device *pdev)\n \tclk_disable_unprepare(priv-\u003eclk);\n }\n \n+static int mvneta_bm_suspend(struct device *dev)\n+{\n+\tstruct mvneta_bm *priv = dev_get_drvdata(dev);\n+\tint i;\n+\n+\t/* Drain buffers and free pool resources while BM is still clocked */\n+\tfor (i = 0; i \u003c MVNETA_BM_POOLS_NUM; i++) {\n+\t\tstruct mvneta_bm_pool *bm_pool = \u0026priv-\u003ebm_pools[i];\n+\t\tint size_bytes;\n+\n+\t\tif (bm_pool-\u003etype == MVNETA_BM_FREE)\n+\t\t\tcontinue;\n+\n+\t\tmvneta_bm_bufs_free(priv, bm_pool, bm_pool-\u003eport_map);\n+\t\tif (bm_pool-\u003ehwbm_pool.buf_num)\n+\t\t\tdev_warn(\u0026priv-\u003epdev-\u003edev,\n+\t\t\t\t \"pool %d: %d buffers not freed\\n\",\n+\t\t\t\t bm_pool-\u003eid, bm_pool-\u003ehwbm_pool.buf_num);\n+\n+\t\tmvneta_bm_pool_disable(priv, bm_pool-\u003eid);\n+\n+\t\tif (bm_pool-\u003evirt_addr) {\n+\t\t\tsize_bytes = sizeof(u32) * bm_pool-\u003ehwbm_pool.size;\n+\t\t\tdma_free_coherent(\u0026priv-\u003epdev-\u003edev, size_bytes,\n+\t\t\t\t\t  bm_pool-\u003evirt_addr,\n+\t\t\t\t\t  bm_pool-\u003ephys_addr);\n+\t\t\tbm_pool-\u003evirt_addr = NULL;\n+\t\t}\n+\t\t/*\n+\t\t * Safe to destroy: device_link guarantees all mvneta ports\n+\t\t * have already suspended, so no hwbm_pool_add() can be in\n+\t\t * progress holding buf_lock.  Pairs with mutex_init() in\n+\t\t * mvneta_bm_pool_use() on resume.\n+\t\t */\n+\t\tmutex_destroy(\u0026bm_pool-\u003ehwbm_pool.buf_lock);\n+\t\tbm_pool-\u003etype = MVNETA_BM_FREE;\n+\t}\n+\n+\tmvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_STOP_MASK);\n+\tclk_disable_unprepare(priv-\u003eclk);\n+\treturn 0;\n+}\n+\n+static int mvneta_bm_resume(struct device *dev)\n+{\n+\tstruct mvneta_bm *priv = dev_get_drvdata(dev);\n+\tint i, err;\n+\n+\terr = clk_prepare_enable(priv-\u003eclk);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* Reinitialize BM hardware; pools are refilled by mvneta_resume() */\n+\tmvneta_bm_default_set(priv);\n+\n+\t/* Restore pool registers lost during clock gating */\n+\tfor (i = 0; i \u003c MVNETA_BM_POOLS_NUM; i++) {\n+\t\tmvneta_bm_write(priv, MVNETA_BM_POOL_READ_PTR_REG(i), 0);\n+\t\tmvneta_bm_write(priv, MVNETA_BM_POOL_WRITE_PTR_REG(i), 0);\n+\t\tmvneta_bm_write(priv, MVNETA_BM_POOL_SIZE_REG(i),\n+\t\t\t\tpriv-\u003ebm_pools[i].hwbm_pool.size);\n+\t}\n+\n+\tmvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_START_MASK);\n+\treturn 0;\n+}\n+\n+static DEFINE_SIMPLE_DEV_PM_OPS(mvneta_bm_pm_ops, mvneta_bm_suspend, mvneta_bm_resume);\n+\n static const struct of_device_id mvneta_bm_match[] = {\n \t{ .compatible = \"marvell,armada-380-neta-bm\" },\n \t{ }\n@@ -489,6 +560,7 @@ static struct platform_driver mvneta_bm_driver = {\n \t.driver = {\n \t\t.name = MVNETA_BM_DRIVER_NAME,\n \t\t.of_match_table = mvneta_bm_match,\n+\t\t.pm = pm_sleep_ptr(\u0026mvneta_bm_pm_ops),\n \t},\n };\n \n"
}

gemini-3.1-pro-preview

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies power management and probe logic for the Marvell NETA Buffer Manager (mvneta_bm), which is a platform device specific to Marvell Armada SoCs. This hardware is not emulated in standard virtualized environments (like QEMU's 'virt' machine) used by fuzzers, making the code unreachable during fuzzing.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer.
Your job is to review a provided patch series and determine
if it makes functional changes to the kernel that should be fuzzed.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively
use your code access tools to examine the actual source code and confirm any assumptions.

Return WorthFuzzing=false if the patch only contains:
- Modifications to Documentation/, Kconfig files, or code comments.
- Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints.
- Changes to numeric constants or macros that do not functionally alter execution flow.
- Code paths that are impossible to reach in virtualized environments like GCE or QEMU,
even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim).

If it modifies reachable core kernel logic, drivers, or architectures, use your code search
tools to verify the code can be executed, then return WorthFuzzing=true.

When returning WorthFuzzing=true, you MUST ALSO:
1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols.
   Avoid listing generic hot-path functions to prevent skewed test distributions.
2. Identify any specific CONFIG_ options required to properly test this new/modified feature.
   Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions.
   Do not list too generic configs (we already have them enabled). Only list those that
   specifically cover the modified code. List them in the EnableConfigs output array,
   and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

For your convenience, here is the diff of the changes:
commit 125e7058d42fe244698b1d45fe3ff232edd1b03f
Author: syz-cluster <triage@syzkaller.com>
Date:   Tue Jun 30 07:21:31 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 744d6585a949d1..543e566425c1e5 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -5678,6 +5678,24 @@ static int mvneta_probe(struct platform_device *pdev)
 					 "use SW buffer management\n");
 				mvneta_bm_put(pp->bm_priv);
 				pp->bm_priv = NULL;
+			} else if (!device_link_add(&pdev->dev,
+						    &pp->bm_priv->pdev->dev,
+						    DL_FLAG_AUTOREMOVE_CONSUMER)) {
+				/*
+				 * Link guarantees BM resumes before mvneta.
+				 * Without it, BM may not be ready when
+				 * mvneta_bm_port_init() runs on resume,
+				 * causing stale buffer addresses and a crash.
+				 * Fall back to SW management to be safe.
+				 */
+				dev_warn(&pdev->dev,
+					 "failed to link to BM, use SW buffer management\n");
+				mvneta_bm_pool_destroy(pp->bm_priv,
+						       pp->pool_long, 1 << pp->id);
+				mvneta_bm_pool_destroy(pp->bm_priv,
+						       pp->pool_short, 1 << pp->id);
+				mvneta_bm_put(pp->bm_priv);
+				pp->bm_priv = NULL;
 			}
 		}
 		/* Set RX packet offset correction for platforms, whose
diff --git a/drivers/net/ethernet/marvell/mvneta_bm.c b/drivers/net/ethernet/marvell/mvneta_bm.c
index 6bb38049491906..e0c693c0a91063 100644
--- a/drivers/net/ethernet/marvell/mvneta_bm.c
+++ b/drivers/net/ethernet/marvell/mvneta_bm.c
@@ -129,6 +129,7 @@ static int mvneta_bm_pool_create(struct mvneta_bm *priv,
 	if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVNETA_BM_POOL_PTR_ALIGN)) {
 		dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
 				  bm_pool->phys_addr);
+		bm_pool->virt_addr = NULL;
 		dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
 			bm_pool->id, MVNETA_BM_POOL_PTR_ALIGN);
 		return -ENOMEM;
@@ -139,6 +140,7 @@ static int mvneta_bm_pool_create(struct mvneta_bm *priv,
 	if (err < 0) {
 		dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
 				  bm_pool->phys_addr);
+		bm_pool->virt_addr = NULL;
 		return err;
 	}
 
@@ -477,6 +479,75 @@ static void mvneta_bm_remove(struct platform_device *pdev)
 	clk_disable_unprepare(priv->clk);
 }
 
+static int mvneta_bm_suspend(struct device *dev)
+{
+	struct mvneta_bm *priv = dev_get_drvdata(dev);
+	int i;
+
+	/* Drain buffers and free pool resources while BM is still clocked */
+	for (i = 0; i < MVNETA_BM_POOLS_NUM; i++) {
+		struct mvneta_bm_pool *bm_pool = &priv->bm_pools[i];
+		int size_bytes;
+
+		if (bm_pool->type == MVNETA_BM_FREE)
+			continue;
+
+		mvneta_bm_bufs_free(priv, bm_pool, bm_pool->port_map);
+		if (bm_pool->hwbm_pool.buf_num)
+			dev_warn(&priv->pdev->dev,
+				 "pool %d: %d buffers not freed\n",
+				 bm_pool->id, bm_pool->hwbm_pool.buf_num);
+
+		mvneta_bm_pool_disable(priv, bm_pool->id);
+
+		if (bm_pool->virt_addr) {
+			size_bytes = sizeof(u32) * bm_pool->hwbm_pool.size;
+			dma_free_coherent(&priv->pdev->dev, size_bytes,
+					  bm_pool->virt_addr,
+					  bm_pool->phys_addr);
+			bm_pool->virt_addr = NULL;
+		}
+		/*
+		 * Safe to destroy: device_link guarantees all mvneta ports
+		 * have already suspended, so no hwbm_pool_add() can be in
+		 * progress holding buf_lock.  Pairs with mutex_init() in
+		 * mvneta_bm_pool_use() on resume.
+		 */
+		mutex_destroy(&bm_pool->hwbm_pool.buf_lock);
+		bm_pool->type = MVNETA_BM_FREE;
+	}
+
+	mvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_STOP_MASK);
+	clk_disable_unprepare(priv->clk);
+	return 0;
+}
+
+static int mvneta_bm_resume(struct device *dev)
+{
+	struct mvneta_bm *priv = dev_get_drvdata(dev);
+	int i, err;
+
+	err = clk_prepare_enable(priv->clk);
+	if (err)
+		return err;
+
+	/* Reinitialize BM hardware; pools are refilled by mvneta_resume() */
+	mvneta_bm_default_set(priv);
+
+	/* Restore pool registers lost during clock gating */
+	for (i = 0; i < MVNETA_BM_POOLS_NUM; i++) {
+		mvneta_bm_write(priv, MVNETA_BM_POOL_READ_PTR_REG(i), 0);
+		mvneta_bm_write(priv, MVNETA_BM_POOL_WRITE_PTR_REG(i), 0);
+		mvneta_bm_write(priv, MVNETA_BM_POOL_SIZE_REG(i),
+				priv->bm_pools[i].hwbm_pool.size);
+	}
+
+	mvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_START_MASK);
+	return 0;
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(mvneta_bm_pm_ops, mvneta_bm_suspend, mvneta_bm_resume);
+
 static const struct of_device_id mvneta_bm_match[] = {
 	{ .compatible = "marvell,armada-380-neta-bm" },
 	{ }
@@ -489,6 +560,7 @@ static struct platform_driver mvneta_bm_driver = {
 	.driver = {
 		.name = MVNETA_BM_DRIVER_NAME,
 		.of_match_table = mvneta_bm_match,
+		.pm = pm_sleep_ptr(&mvneta_bm_pm_ops),
 	},
 };
 

gemini-3.1-pro-preview

null

null

							input: 3572
							output: 36
							thoughts: 249
						

**Analyzing the Marvell NETA Buffer Manager Driver Patch**

Okay, so I've got a patch here that's touching `mvneta.c` and `mvneta_bm.c` – specifically, it's adding power management hooks, suspend/resume, for the Marvell NETA Buffer Manager. The patch also introduces a device link, which is a good practice for ensuring proper device ordering during power transitions, and fixes a possible null pointer dereference in `mvneta_bm_pool_create` after a `dma_free_coherent` call.

Now, the important question is: is this even worth digging into for fuzzing? My initial thought is to figure out the code's reachability. This driver targets Marvell Armada 380/38x SoCs. Those are generally *not* easily accessible in a standard virtualized environment like QEMU. SoC-specific Ethernet drivers can be a pain in QEMU unless you have a dedicated machine model specifically configured for the target hardware, or if it presents as a PCI device. So, the first step is to confirm the device's setup to see its reachability.

Let's check the Kconfig file for the `MVNETA` and `MVNETA_BM` symbols, see if there's any easy way to enable this in a more general configuration.

{
  "Expression": "config MVNETA",
  "PathPrefix": "drivers/net/ethernet/marvell/Kconfig"
}

{
  "Output": "drivers/net/ethernet/marvell/Kconfig=34=config MVMDIO\n--\ndrivers/net/ethernet/marvell/Kconfig-44-\ndrivers/net/ethernet/marvell/Kconfig:45:config MVNETA_BM_ENABLE\ndrivers/net/ethernet/marvell/Kconfig-46-\ttristate \"Marvell Armada 38x/XP network interface BM support\"\n--\ndrivers/net/ethernet/marvell/Kconfig-58-\ndrivers/net/ethernet/marvell/Kconfig:59:config MVNETA\ndrivers/net/ethernet/marvell/Kconfig-60-\ttristate \"Marvell Armada 370/38x/XP/37xx network interface support\"\n--\ndrivers/net/ethernet/marvell/Kconfig-74-\ndrivers/net/ethernet/marvell/Kconfig:75:config MVNETA_BM\ndrivers/net/ethernet/marvell/Kconfig-76-\ttristate\n"
}

gemini-3.1-pro-preview

null

null

							input: 4402
							output: 37
							thoughts: 254
						

**Analyzing the Marvell Armada Network Driver in Relation to QEMU and Fuzzing**

Okay, so I'm looking at this driver, "Marvell Armada 370/38x/XP/37xx network interface support." It's a `platform_driver`, which immediately makes me think about QEMU emulation. The question is, can we *reasonably* emulate this particular driver within QEMU? I need to check which ARM boards QEMU *actually* supports, and specifically if any of those boards are Armada 380/38x/XP based. If not, this is going to be a tough road.

My experience tells me that these platform device drivers, designed for specific SoCs, are rarely easily fuzzable *unless* we have a QEMU machine for that exact platform. Or, failing QEMU, there needs to be some way to inject the platform device. Syzkaller's pseudo-device injection comes to mind, but that's not the usual case. Syzkaller generally doesn't inject arbitrary platform devices unless there's a specific description provided. I do need to recall if Syzkaller has any *support* for injecting platform devices, provided they have a device description, but the chances of it being able to handle a random SoC ethernet driver are usually pretty slim.

Okay, let me eliminate some of these doubts: is the `MVNETA` interface a PCI device? Quick check... nope, it's a platform device. Now, I need to look directly at the driver code itself. I'll open up `drivers/net/ethernet/marvell/mvneta.c` and confirm that it's a `platform_driver` for further analysis.

{
  "Expression": "platform_driver",
  "PathPrefix": "drivers/net/ethernet/marvell/mvneta.c"
}

{
  "Output": "drivers/net/ethernet/marvell/mvneta.c=5937=MODULE_DEVICE_TABLE(of, mvneta_match);\ndrivers/net/ethernet/marvell/mvneta.c-5938-\ndrivers/net/ethernet/marvell/mvneta.c:5939:static struct platform_driver mvneta_driver = {\ndrivers/net/ethernet/marvell/mvneta.c-5940-\t.probe = mvneta_probe,\n--\ndrivers/net/ethernet/marvell/mvneta.c=5949=static int __init mvneta_driver_init(void)\n--\ndrivers/net/ethernet/marvell/mvneta.c-5965-\ndrivers/net/ethernet/marvell/mvneta.c:5966:\tret = platform_driver_register(\u0026mvneta_driver);\ndrivers/net/ethernet/marvell/mvneta.c-5967-\tif (ret)\n--\ndrivers/net/ethernet/marvell/mvneta.c=5980=static void __exit mvneta_driver_exit(void)\ndrivers/net/ethernet/marvell/mvneta.c-5981-{\ndrivers/net/ethernet/marvell/mvneta.c:5982:\tplatform_driver_unregister(\u0026mvneta_driver);\ndrivers/net/ethernet/marvell/mvneta.c-5983-\tcpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);\n"
}

gemini-3.1-pro-preview

null

null

							input: 5443
							output: 102
							thoughts: 364
						

**Unreachable Code: Platform Device in a Virtualized World**

Okay, so I'm looking at this code and immediately I see it's a driver specifically for a platform device. I'm thinking, "Is this even reachable in a standard fuzzing environment?" My initial gut feeling is no, given that it's dealing with the Armada 38x SoC. Unless QEMU specifically emulates *that* particular SoC, we're likely out of luck.

Let me just quickly confirm if QEMU even *has* Armada 38x support. Hmm, yeah, I don't think it does, and even if it did, Syzkaller, which is what we're probably using for fuzzing here, doesn't typically boot with that specific machine type anyway. Syzkaller sticks to `virt` for ARM64, and maybe `vexpress` or `virt` for ARM32. So, this code path is pretty much dead in the water as far as standard virtualization goes.

So, since it's unreachable in those environments, my first conclusion is that `WorthFuzzing` should definitely be `false`.

But, let's double check. Just to be completely thorough, let's see if there's *any* other possible angle. Okay, the patch modifies `mvneta_probe` to add a device link, and it also adds suspend/resume functions to `mvneta_bm.c`. The suspend/resume functions are only called during system suspend/resume, which means they'll only be triggered if the device is actually probed.

And since this device is a platform device, bound via a device tree entry (`marvell,armada-380-neta-bm`), the kernel will only probe it if that node is present in the DT. The thing is, Syzkaller doesn't just dynamically add arbitrary device tree nodes for platform devices. So, that's another dead end. It's unreachable.

Okay, that seals it. I'm going to set `WorthFuzzing = false`. The logic changes power management and probe logic for the Marvell NETA Buffer Manager. The Marvell NETA Buffer Manager is only available on Marvell Armada 38x SoCs. And that is not something that is emulated in standard virtualized environments, which makes this code unreachable during fuzzing.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies power management and probe logic for the Marvell NETA Buffer Manager (mvneta_bm), which is a platform device specific to Marvell Armada SoCs. This hardware is not emulated in standard virtualized environments (like QEMU's 'virt' machine) used by fuzzers, making the code unreachable during fuzzing.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies power management and probe logic for the Marvell NETA Buffer Manager (mvneta_bm), which is a platform device specific to Marvell Armada SoCs. This hardware is not emulated in standard virtualized environments (like QEMU's 'virt' machine) used by fuzzers, making the code unreachable during fuzzing.",
  "WorthFuzzing": false
}