AI Trajectory

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies error handling in msm_hdmi_phy_probe() within the Qualcomm MSM DRM HDMI PHY driver. This driver is designed for Qualcomm Snapdragon ARM/ARM64 SoCs and binds via Device Tree to physical Qualcomm SoC hardware (e.g., MSM8996/MSM8998) not emulated in standard amd64 QEMU/GCE environments. Consequently, the modified probe error path is structurally unreachable on the target architecture (amd64).",
  "WorthFuzzing": false
}

null

{
  "PatchDiff": "commit 0b88436bb49942a28e8fdc3a03d86a3aafc797ee\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Wed Sep 16 21:05:44 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c\nindex eb1088755cb3a..77dce35cd45e0 100644\n--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c\n+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c\n@@ -168,13 +168,13 @@ static int msm_hdmi_phy_probe(struct platform_device *pdev)\n \n \tret = msm_hdmi_phy_resource_enable(phy);\n \tif (ret)\n-\t\treturn ret;\n+\t\tgoto err_pm_disable;\n \n \tret = msm_hdmi_phy_pll_init(pdev, phy-\u003ecfg-\u003etype);\n \tif (ret) {\n \t\tDRM_DEV_ERROR(dev, \"couldn't init PLL\\n\");\n \t\tmsm_hdmi_phy_resource_disable(phy);\n-\t\treturn ret;\n+\t\tgoto err_pm_disable;\n \t}\n \n \tmsm_hdmi_phy_resource_disable(phy);\n@@ -182,6 +182,10 @@ static int msm_hdmi_phy_probe(struct platform_device *pdev)\n \tplatform_set_drvdata(pdev, phy);\n \n \treturn 0;\n+\n+err_pm_disable:\n+\tpm_runtime_disable(dev);\n+\treturn ret;\n }\n \n static void msm_hdmi_phy_remove(struct platform_device *pdev)\n"
}

core

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies error handling in msm_hdmi_phy_probe() within the Qualcomm MSM DRM HDMI PHY driver. This driver is designed for Qualcomm Snapdragon ARM/ARM64 SoCs and binds via Device Tree to physical Qualcomm SoC hardware (e.g., MSM8996/MSM8998) not emulated in standard amd64 QEMU/GCE environments. Consequently, the modified probe error path is structurally unreachable on the target architecture (amd64).",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit 0b88436bb49942a28e8fdc3a03d86a3aafc797ee
Author: syz-cluster <triage@syzkaller.com>
Date:   Wed Sep 16 21:05:44 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c
index eb1088755cb3a..77dce35cd45e0 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c
@@ -168,13 +168,13 @@ static int msm_hdmi_phy_probe(struct platform_device *pdev)
 
 	ret = msm_hdmi_phy_resource_enable(phy);
 	if (ret)
-		return ret;
+		goto err_pm_disable;
 
 	ret = msm_hdmi_phy_pll_init(pdev, phy->cfg->type);
 	if (ret) {
 		DRM_DEV_ERROR(dev, "couldn't init PLL\n");
 		msm_hdmi_phy_resource_disable(phy);
-		return ret;
+		goto err_pm_disable;
 	}
 
 	msm_hdmi_phy_resource_disable(phy);
@@ -182,6 +182,10 @@ static int msm_hdmi_phy_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, phy);
 
 	return 0;
+
+err_pm_disable:
+	pm_runtime_disable(dev);
+	return ret;
 }
 
 static void msm_hdmi_phy_remove(struct platform_device *pdev)

gemini-3.8-flash

null

null

							input: 3089
							output: 33
							thoughts: 553
						

**Analyzing a Qualcomm HDMI PHY Driver Patch**

Okay, so I've got a patch here that's touching `drivers/gpu/drm/msm/hdmi/hdmi_phy.c`. The first thing I'm doing is a quick scan of the code, and it looks like a fairly straightforward change. It's essentially adding an `err_pm_disable` label and `goto` statement to handle error scenarios within the `msm_hdmi_phy_probe` function. The key takeaway is it's handling errors better by disabling the runtime power management (`pm_runtime_disable`) of the device before returning the error code. This is likely to prevent issues if there is a problem during initialization of the PHY or PLL.

Now, because I am an expert in this field, I know instinctively that "MSM" usually means Qualcomm Snapdragon, which is ARM or ARM64-based, so I should see the Kconfig if this change is conditional. I need to make sure this change is appropriate for the architecture or hardware in the system I am working with. Let me cross check my findings.

{
  "Expression": "DRM_MSM",
  "PathPrefix": "drivers/gpu/drm/msm"
}

{
  "Output": "\nFull output is too long, showing 500 out of 579 lines.\nUse more precise expression if possible.\n\ndrivers/gpu/drm/msm/Kconfig-2-\ndrivers/gpu/drm/msm/Kconfig:3:config DRM_MSM\ndrivers/gpu/drm/msm/Kconfig-4-\ttristate \"MSM DRM\"\n--\ndrivers/gpu/drm/msm/Kconfig-36-\ndrivers/gpu/drm/msm/Kconfig:37:config DRM_MSM_GPU_STATE\ndrivers/gpu/drm/msm/Kconfig-38-\tbool\ndrivers/gpu/drm/msm/Kconfig:39:\tdepends on DRM_MSM \u0026\u0026 (DEBUG_FS || DEV_COREDUMP)\ndrivers/gpu/drm/msm/Kconfig-40-\tdefault y\ndrivers/gpu/drm/msm/Kconfig-41-\ndrivers/gpu/drm/msm/Kconfig:42:config DRM_MSM_GPU_SUDO\ndrivers/gpu/drm/msm/Kconfig-43-\tbool \"Enable SUDO flag on submits\"\ndrivers/gpu/drm/msm/Kconfig:44:\tdepends on DRM_MSM \u0026\u0026 EXPERT\ndrivers/gpu/drm/msm/Kconfig-45-\tdefault n\n--\ndrivers/gpu/drm/msm/Kconfig-54-\ndrivers/gpu/drm/msm/Kconfig:55:config DRM_MSM_VALIDATE_XML\ndrivers/gpu/drm/msm/Kconfig-56-\tbool \"Validate XML register files against schema\"\ndrivers/gpu/drm/msm/Kconfig:57:\tdepends on DRM_MSM \u0026\u0026 EXPERT\ndrivers/gpu/drm/msm/Kconfig-58-\tdepends on $(success,$(PYTHON3) -c \"import lxml\")\n--\ndrivers/gpu/drm/msm/Kconfig-62-\ndrivers/gpu/drm/msm/Kconfig:63:config DRM_MSM_KMS\ndrivers/gpu/drm/msm/Kconfig-64-\tdef_bool n\ndrivers/gpu/drm/msm/Kconfig:65:\tdepends on DRM_MSM\ndrivers/gpu/drm/msm/Kconfig-66-\tselect DRM_BRIDGE\n--\ndrivers/gpu/drm/msm/Kconfig-73-\ndrivers/gpu/drm/msm/Kconfig:74:config DRM_MSM_KMS_FBDEV\ndrivers/gpu/drm/msm/Kconfig-75-\tdef_bool DRM_FBDEV_EMULATION\ndrivers/gpu/drm/msm/Kconfig:76:\tdepends on DRM_MSM_KMS\ndrivers/gpu/drm/msm/Kconfig-77-\tselect FB_SYSMEM_HELPERS\ndrivers/gpu/drm/msm/Kconfig-78-\ndrivers/gpu/drm/msm/Kconfig:79:config DRM_MSM_MDSS\ndrivers/gpu/drm/msm/Kconfig-80-\tbool\ndrivers/gpu/drm/msm/Kconfig:81:\tdepends on DRM_MSM\ndrivers/gpu/drm/msm/Kconfig-82-\tdefault n\ndrivers/gpu/drm/msm/Kconfig-83-\ndrivers/gpu/drm/msm/Kconfig:84:config DRM_MSM_MDP4\ndrivers/gpu/drm/msm/Kconfig-85-\tbool \"Enable MDP4 support in MSM DRM driver\"\ndrivers/gpu/drm/msm/Kconfig:86:\tdepends on DRM_MSM\ndrivers/gpu/drm/msm/Kconfig:87:\tselect DRM_MSM_KMS\ndrivers/gpu/drm/msm/Kconfig-88-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-93-\ndrivers/gpu/drm/msm/Kconfig:94:config DRM_MSM_MDP5\ndrivers/gpu/drm/msm/Kconfig-95-\tbool \"Enable MDP5 support in MSM DRM driver\"\ndrivers/gpu/drm/msm/Kconfig:96:\tdepends on DRM_MSM\ndrivers/gpu/drm/msm/Kconfig:97:\tselect DRM_MSM_MDSS\ndrivers/gpu/drm/msm/Kconfig:98:\tselect DRM_MSM_KMS\ndrivers/gpu/drm/msm/Kconfig-99-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-104-\ndrivers/gpu/drm/msm/Kconfig:105:config DRM_MSM_DPU\ndrivers/gpu/drm/msm/Kconfig-106-\tbool \"Enable DPU support in MSM DRM driver\"\ndrivers/gpu/drm/msm/Kconfig:107:\tdepends on DRM_MSM\ndrivers/gpu/drm/msm/Kconfig:108:\tselect DRM_MSM_MDSS\ndrivers/gpu/drm/msm/Kconfig:109:\tselect DRM_MSM_KMS\ndrivers/gpu/drm/msm/Kconfig-110-\tselect DRM_DISPLAY_DSC_HELPER\n--\ndrivers/gpu/drm/msm/Kconfig-116-\ndrivers/gpu/drm/msm/Kconfig:117:config DRM_MSM_DP\ndrivers/gpu/drm/msm/Kconfig-118-\tbool \"Enable DisplayPort support in MSM DRM driver\"\ndrivers/gpu/drm/msm/Kconfig:119:\tdepends on DRM_MSM\ndrivers/gpu/drm/msm/Kconfig:120:\tdepends on DRM_MSM_KMS\ndrivers/gpu/drm/msm/Kconfig-121-\tselect DRM_DISPLAY_HDMI_AUDIO_HELPER\n--\ndrivers/gpu/drm/msm/Kconfig-130-\ndrivers/gpu/drm/msm/Kconfig:131:config DRM_MSM_DSI\ndrivers/gpu/drm/msm/Kconfig-132-\tbool \"Enable DSI support in MSM DRM driver\"\ndrivers/gpu/drm/msm/Kconfig:133:\tdepends on DRM_MSM\ndrivers/gpu/drm/msm/Kconfig:134:\tdepends on DRM_MSM_KMS\ndrivers/gpu/drm/msm/Kconfig-135-\tselect DRM_PANEL\n--\ndrivers/gpu/drm/msm/Kconfig-142-\ndrivers/gpu/drm/msm/Kconfig:143:config DRM_MSM_DSI_28NM_PHY\ndrivers/gpu/drm/msm/Kconfig-144-\tbool \"Enable DSI 28nm PHY driver in MSM DRM\"\ndrivers/gpu/drm/msm/Kconfig:145:\tdepends on DRM_MSM_DSI\ndrivers/gpu/drm/msm/Kconfig-146-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-149-\ndrivers/gpu/drm/msm/Kconfig:150:config DRM_MSM_DSI_20NM_PHY\ndrivers/gpu/drm/msm/Kconfig-151-\tbool \"Enable DSI 20nm PHY driver in MSM DRM\"\ndrivers/gpu/drm/msm/Kconfig:152:\tdepends on DRM_MSM_DSI\ndrivers/gpu/drm/msm/Kconfig-153-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-156-\ndrivers/gpu/drm/msm/Kconfig:157:config DRM_MSM_DSI_28NM_8960_PHY\ndrivers/gpu/drm/msm/Kconfig-158-\tbool \"Enable DSI 28nm 8960 PHY driver in MSM DRM\"\ndrivers/gpu/drm/msm/Kconfig:159:\tdepends on DRM_MSM_DSI\ndrivers/gpu/drm/msm/Kconfig-160-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-164-\ndrivers/gpu/drm/msm/Kconfig:165:config DRM_MSM_DSI_14NM_PHY\ndrivers/gpu/drm/msm/Kconfig-166-\tbool \"Enable DSI 14nm PHY driver in MSM DRM (used by MSM8996/APQ8096)\"\ndrivers/gpu/drm/msm/Kconfig:167:\tdepends on DRM_MSM_DSI\ndrivers/gpu/drm/msm/Kconfig-168-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-171-\ndrivers/gpu/drm/msm/Kconfig:172:config DRM_MSM_DSI_10NM_PHY\ndrivers/gpu/drm/msm/Kconfig-173-\tbool \"Enable DSI 10nm PHY driver in MSM DRM (used by SDM845)\"\ndrivers/gpu/drm/msm/Kconfig:174:\tdepends on DRM_MSM_DSI\ndrivers/gpu/drm/msm/Kconfig-175-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-178-\ndrivers/gpu/drm/msm/Kconfig:179:config DRM_MSM_DSI_7NM_PHY\ndrivers/gpu/drm/msm/Kconfig-180-\tbool \"Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM\"\ndrivers/gpu/drm/msm/Kconfig:181:\tdepends on DRM_MSM_DSI\ndrivers/gpu/drm/msm/Kconfig-182-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-186-\ndrivers/gpu/drm/msm/Kconfig:187:config DRM_MSM_HDMI\ndrivers/gpu/drm/msm/Kconfig-188-\tbool \"Enable HDMI support in MSM DRM driver\"\ndrivers/gpu/drm/msm/Kconfig:189:\tdepends on DRM_MSM\ndrivers/gpu/drm/msm/Kconfig:190:\tdepends on DRM_MSM_KMS\ndrivers/gpu/drm/msm/Kconfig-191-\tdefault y\n--\ndrivers/gpu/drm/msm/Kconfig-199-\ndrivers/gpu/drm/msm/Kconfig:200:config DRM_MSM_HDMI_HDCP\ndrivers/gpu/drm/msm/Kconfig-201-\tbool \"Enable HDMI HDCP support in MSM DRM driver\"\ndrivers/gpu/drm/msm/Kconfig:202:\tdepends on DRM_MSM \u0026\u0026 DRM_MSM_HDMI\ndrivers/gpu/drm/msm/Kconfig-203-\tdefault y\n--\ndrivers/gpu/drm/msm/Makefile=4=ccflags-y += -I $(src)/disp/dpu1\ndrivers/gpu/drm/msm/Makefile:5:ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(src)/dsi\ndrivers/gpu/drm/msm/Makefile:6:ccflags-$(CONFIG_DRM_MSM_DP) += -I $(src)/dp\ndrivers/gpu/drm/msm/Makefile-7-\n--\ndrivers/gpu/drm/msm/Makefile=30=adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \\\ndrivers/gpu/drm/msm/Makefile-31-\ndrivers/gpu/drm/msm/Makefile:32:adreno-$(CONFIG_DRM_MSM_GPU_STATE)\t+= adreno/a6xx_gpu_state.o\ndrivers/gpu/drm/msm/Makefile-33-\ndrivers/gpu/drm/msm/Makefile:34:msm-display-$(CONFIG_DRM_MSM_HDMI) += \\\ndrivers/gpu/drm/msm/Makefile-35-\thdmi/hdmi.o \\\n--\ndrivers/gpu/drm/msm/Makefile-47-\ndrivers/gpu/drm/msm/Makefile:48:msm-display-$(CONFIG_DRM_MSM_MDP4) += \\\ndrivers/gpu/drm/msm/Makefile-49-\tdisp/mdp4/mdp4_crtc.o \\\n--\ndrivers/gpu/drm/msm/Makefile-57-\ndrivers/gpu/drm/msm/Makefile:58:msm-display-$(CONFIG_DRM_MSM_MDP5) += \\\ndrivers/gpu/drm/msm/Makefile-59-\tdisp/mdp5/mdp5_cfg.o \\\n--\ndrivers/gpu/drm/msm/Makefile-70-\ndrivers/gpu/drm/msm/Makefile:71:msm-display-$(CONFIG_DRM_MSM_DPU) += \\\ndrivers/gpu/drm/msm/Makefile-72-\tdisp/dpu1/dpu_core_perf.o \\\n--\ndrivers/gpu/drm/msm/Makefile-102-\ndrivers/gpu/drm/msm/Makefile:103:msm-display-$(CONFIG_DRM_MSM_MDSS) += \\\ndrivers/gpu/drm/msm/Makefile-104-\tmsm_mdss.o \\\ndrivers/gpu/drm/msm/Makefile-105-\ndrivers/gpu/drm/msm/Makefile:106:msm-display-$(CONFIG_DRM_MSM_KMS) += \\\ndrivers/gpu/drm/msm/Makefile-107-\tdisp/mdp_format.o \\\n--\ndrivers/gpu/drm/msm/Makefile=112=msm-y += \\\n--\ndrivers/gpu/drm/msm/Makefile-131-\ndrivers/gpu/drm/msm/Makefile:132:msm-$(CONFIG_DRM_MSM_KMS) += \\\ndrivers/gpu/drm/msm/Makefile-133-\tmsm_atomic.o \\\n--\ndrivers/gpu/drm/msm/Makefile-137-\ndrivers/gpu/drm/msm/Makefile:138:msm-$(CONFIG_DRM_MSM_KMS_FBDEV) += msm_fbdev.o\ndrivers/gpu/drm/msm/Makefile-139-\ndrivers/gpu/drm/msm/Makefile:140:msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \\\ndrivers/gpu/drm/msm/Makefile-141-\tdp/dp_ctrl.o \\\n--\ndrivers/gpu/drm/msm/Makefile-149-\ndrivers/gpu/drm/msm/Makefile:150:msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o\ndrivers/gpu/drm/msm/Makefile-151-\ndrivers/gpu/drm/msm/Makefile:152:msm-display-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \\\ndrivers/gpu/drm/msm/Makefile-153-\t\t\tdsi/dsi_cfg.o \\\n--\ndrivers/gpu/drm/msm/Makefile-157-\ndrivers/gpu/drm/msm/Makefile:158:msm-display-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o\ndrivers/gpu/drm/msm/Makefile:159:msm-display-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o\ndrivers/gpu/drm/msm/Makefile:160:msm-display-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o\ndrivers/gpu/drm/msm/Makefile:161:msm-display-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o\ndrivers/gpu/drm/msm/Makefile:162:msm-display-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o\ndrivers/gpu/drm/msm/Makefile:163:msm-display-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o\ndrivers/gpu/drm/msm/Makefile-164-\ndrivers/gpu/drm/msm/Makefile=165=msm-y += $(adreno-y)\ndrivers/gpu/drm/msm/Makefile:166:msm-$(CONFIG_DRM_MSM_KMS) += $(msm-display-y)\ndrivers/gpu/drm/msm/Makefile-167-\ndrivers/gpu/drm/msm/Makefile:168:obj-$(CONFIG_DRM_MSM)\t+= msm.o\ndrivers/gpu/drm/msm/Makefile-169-\ndrivers/gpu/drm/msm/Makefile:170:ifeq (y,$(CONFIG_DRM_MSM_VALIDATE_XML))\ndrivers/gpu/drm/msm/Makefile-171-\theadergen-opts += --validate\n--\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c=12=static const struct adreno_info a2xx_gpus[] = {\n--\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c-21-\t\t.gmem  = SZ_256K,\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c:22:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c-23-\t\t.funcs = \u0026a2xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c-32-\t\t.gmem  = SZ_128K,\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c:33:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c-34-\t\t.funcs = \u0026a2xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c-43-\t\t.gmem  = SZ_512K,\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c:44:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c-45-\t\t.funcs = \u0026a2xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c-55-\t\t.gmem  = SZ_512K,\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c:56:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a2xx_catalog.c-57-\t\t.funcs = \u0026a2xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c=12=static const struct adreno_info a3xx_gpus[] = {\n--\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-20-\t\t.gmem  = SZ_128K,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c:21:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-22-\t\t.funcs = \u0026a3xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-31-\t\t.gmem  = SZ_256K,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c:32:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-33-\t\t.funcs = \u0026a3xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-42-\t\t.gmem  = SZ_128K,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c:43:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-44-\t\t.funcs = \u0026a3xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-53-\t\t.gmem = SZ_128K,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c:54:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-55-\t\t.funcs = \u0026a3xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-68-\t\t.gmem  = SZ_512K,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c:69:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-70-\t\t.funcs = \u0026a3xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-83-\t\t.gmem  = SZ_1M,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c:84:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a3xx_catalog.c-85-\t\t.funcs = \u0026a3xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c=12=static const struct adreno_info a4xx_gpus[] = {\n--\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c-21-\t\t.gmem  = SZ_256K,\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c:22:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c-23-\t\t.funcs = \u0026a4xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c-32-\t\t.gmem  = (SZ_1M + SZ_512K),\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c:33:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c-34-\t\t.funcs = \u0026a4xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c-43-\t\t.gmem  = (SZ_1M + SZ_512K),\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c:44:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a4xx_catalog.c-45-\t\t.funcs = \u0026a4xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a5xx_catalog.c=12=static const struct adreno_info a5xx_gpus[] = {\n--\ndrivers/gpu/drm/msm/adreno/a5xx_catalog.c-21-\t\t.gmem = (SZ_128K + SZ_8K),\ndrivers/gpu/drm/msm/adreno/a5xx_catalog.c:22:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a5xx_catalog.c-23-\t\t.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |\n--\ndrivers/gpu/drm/msm/adreno/a5xx_gpu.c=127=static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)\n--\ndrivers/gpu/drm/msm/adreno/a5xx_gpu.c-135-\ndrivers/gpu/drm/msm/adreno/a5xx_gpu.c:136:\tif (IS_ENABLED(CONFIG_DRM_MSM_GPU_SUDO) \u0026\u0026 submit-\u003ein_rb) {\ndrivers/gpu/drm/msm/adreno/a5xx_gpu.c-137-\t\tring-\u003ecur_ctx_seqno = 0;\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c=681=static const struct adreno_info a6xx_gpus[] = {\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-690-\t\t.quirks = ADRENO_QUIRK_4GB_VA,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:691:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-692-\t\t.funcs = \u0026a6xx_gmuwrapper_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-722-\t\t.gmem = (SZ_128K + SZ_4K),\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:723:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-724-\t\t.funcs = \u0026a6xx_gmuwrapper_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-740-\t\t.quirks = ADRENO_QUIRK_4GB_VA,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:741:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-742-\t\t.funcs = \u0026a6xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-769-\t\t.gmem = SZ_512K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:770:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-771-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-796-\t\t.gmem = SZ_512K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:797:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-798-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-821-\t\t.quirks = ADRENO_QUIRK_4GB_VA,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:822:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-823-\t\t.funcs = \u0026a6xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-846-\t\t.quirks = ADRENO_QUIRK_4GB_VA,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:847:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-848-\t\t.funcs = \u0026a6xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-871-\t\t\t  ADRENO_QUIRK_4GB_VA,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:872:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-873-\t\t.funcs = \u0026a6xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-895-\t\t.gmem = SZ_512K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:896:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-897-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-919-\t\t.gmem = SZ_512K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:920:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-921-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-959-\t\t\t  ADRENO_QUIRK_4GB_VA,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:960:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-961-\t\t.funcs = \u0026a6xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-979-\t\t\t  ADRENO_QUIRK_4GB_VA,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:980:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-981-\t\t.funcs = \u0026a6xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1001-\t\t.gmem = SZ_1M + SZ_128K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1002:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1003-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1028-\t\t.gmem = SZ_1M + SZ_512K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1029:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1030-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1048-\t\t.gmem = SZ_1M + SZ_512K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1049:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1050-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1072-\t\t.gmem = SZ_512K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1073:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1074-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1102-\t\t\t  ADRENO_QUIRK_4GB_VA,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1103:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1104-\t\t.funcs = \u0026a6xx_gpu_funcs,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1119-\t\t.gmem = SZ_4M,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1120:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1121-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c=1455=static const struct adreno_info a7xx_gpus[] = {\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1462-\t\t.gmem = SZ_128K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1463:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1464-\t\t.quirks = ADRENO_QUIRK_HAS_HW_APRIV,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1487-\t\t.gmem = SZ_2M,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1488:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1489-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1510-\t\t.gmem = SZ_1M,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1511:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1512-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1544-\t\t.gmem = 3 * SZ_1M,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1545:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1546-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1579-\t\t.gmem = 3 * SZ_1M,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1580:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1581-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1622-\t\t.gmem = 3 * SZ_1M,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1623:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1624-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1658-\t\t.gmem = SZ_1M + SZ_512K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:1659:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-1660-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c=2400=static const struct adreno_info a8xx_gpus[] = {\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-2408-\t\t.gmem = 21 * SZ_1M,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:2409:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-2410-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-2450-\t\t.gmem = 18 * SZ_1M,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:2451:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-2452-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-2492-\t\t.gmem = SZ_512K + SZ_64K,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c:2493:\t\t.inactive_period = DRM_MSM_INACTIVE_PERIOD,\ndrivers/gpu/drm/msm/adreno/a6xx_catalog.c-2494-\t\t.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c=2789=const struct adreno_gpu_funcs a6xx_gpu_funcs = {\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2801-\t\t.destroy = a6xx_destroy,\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c:2802:#if defined(CONFIG_DRM_MSM_GPU_STATE)\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2803-\t\t.show = a6xx_show,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2807-\t\t.gpu_set_freq = a6xx_gpu_set_freq,\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c:2808:#if defined(CONFIG_DRM_MSM_GPU_STATE)\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2809-\t\t.gpu_state_get = a6xx_gpu_state_get,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c=2826=const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = {\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2838-\t\t.destroy = a6xx_destroy,\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c:2839:#if defined(CONFIG_DRM_MSM_GPU_STATE)\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2840-\t\t.show = a6xx_show,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2842-\t\t.gpu_busy = a6xx_gpu_busy,\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c:2843:#if defined(CONFIG_DRM_MSM_GPU_STATE)\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2844-\t\t.gpu_state_get = a6xx_gpu_state_get,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c=2860=const struct adreno_gpu_funcs a7xx_gpu_funcs = {\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2872-\t\t.destroy = a6xx_destroy,\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c:2873:#if defined(CONFIG_DRM_MSM_GPU_STATE)\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2874-\t\t.show = a6xx_show,\n--\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2878-\t\t.gpu_set_freq = a6xx_gpu_set_freq,\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c:2879:#if defined(CONFIG_DRM_MSM_GPU_STATE)\ndrivers/gpu/drm/msm/adreno/a6xx_gpu.c-2880-\t\t.gpu_state_get = a6xx_gpu_state_get,\n--\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c-13-\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c:14:#ifdef CONFIG_DRM_MSM_DSI\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c-15-\n--\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c=137=struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)\n--\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c-152-}\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c:153:#endif /* CONFIG_DRM_MSM_DSI */\n--\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h=194=struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev);\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h-195-\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h:196:#ifdef CONFIG_DRM_MSM_DSI\ndrivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h-197-struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev);\n--\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c-10-\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c:11:#ifdef CONFIG_DRM_MSM_DSI\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c-12-\n--\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c=142=void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)\n--\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c-160-}\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c:161:#endif /* CONFIG_DRM_MSM_DSI */\n--\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h=295=u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h-296-\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h:297:#ifdef CONFIG_DRM_MSM_DSI\ndrivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h-298-void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,\n--\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c=516=static const struct of_device_id dsi_phy_dt_match[] = {\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c:517:#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-518-\t{ .compatible = \"qcom,dsi-phy-28nm-hpm\",\n--\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-528-#endif\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c:529:#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-530-\t{ .compatible = \"qcom,dsi-phy-20nm\",\n--\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-532-#endif\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c:533:#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-534-\t{ .compatible = \"qcom,dsi-phy-28nm-8960\",\n--\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-536-#endif\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c:537:#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-538-\t{ .compatible = \"qcom,dsi-phy-14nm\",\n--\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-550-#endif\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c:551:#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-552-\t{ .compatible = \"qcom,dsi-phy-10nm\",\n--\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-556-#endif\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c:557:#ifdef CONFIG_DRM_MSM_DSI_7NM_PHY\ndrivers/gpu/drm/msm/dsi/phy/dsi_phy.c-558-\t{ .compatible = \"qcom,dsi-phy-7nm\",\n--\ndrivers/gpu/drm/msm/hdmi/hdmi.h=247=struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi);\n--\ndrivers/gpu/drm/msm/hdmi/hdmi.h-251- */\ndrivers/gpu/drm/msm/hdmi/hdmi.h:252:#ifdef CONFIG_DRM_MSM_HDMI_HDCP\ndrivers/gpu/drm/msm/hdmi/hdmi.h-253-struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi);\n--\ndrivers/gpu/drm/msm/msm_debugfs.c=112=static const struct file_operations msm_gpu_fops = {\n--\ndrivers/gpu/drm/msm/msm_debugfs.c-119-\ndrivers/gpu/drm/msm/msm_debugfs.c:120:#ifdef CONFIG_DRM_MSM_KMS\ndrivers/gpu/drm/msm/msm_debugfs.c-121-static int msm_fb_show(struct seq_file *m, void *arg)\n--\ndrivers/gpu/drm/msm/msm_debugfs.c=213=static void msm_debugfs_kms_init(struct drm_minor *minor)\n--\ndrivers/gpu/drm/msm/msm_debugfs.c-227-}\ndrivers/gpu/drm/msm/msm_debugfs.c:228:#else /* ! CONFIG_DRM_MSM_KMS */\ndrivers/gpu/drm/msm/msm_debugfs.c-229-static void msm_debugfs_kms_init(struct drm_minor *minor)\n--\ndrivers/gpu/drm/msm/msm_drv.c=918=static int add_mdp_components(struct device *master_dev,\n--\ndrivers/gpu/drm/msm/msm_drv.c-962-\ndrivers/gpu/drm/msm/msm_drv.c:963:#if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU)\ndrivers/gpu/drm/msm/msm_drv.c-964-bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)\n--\ndrivers/gpu/drm/msm/msm_drv.h=261=struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,\n--\ndrivers/gpu/drm/msm/msm_drv.h-264-\ndrivers/gpu/drm/msm/msm_drv.h:265:#ifdef CONFIG_DRM_MSM_KMS_FBDEV\ndrivers/gpu/drm/msm/msm_drv.h-266-int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper,\n--\ndrivers/gpu/drm/msm/msm_drv.h=275=struct hdmi;\ndrivers/gpu/drm/msm/msm_drv.h:276:#ifdef CONFIG_DRM_MSM_HDMI\ndrivers/gpu/drm/msm/msm_drv.h-277-int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,\n--\ndrivers/gpu/drm/msm/msm_drv.h=291=struct msm_dsi;\ndrivers/gpu/drm/msm/msm_drv.h:292:#ifdef CONFIG_DRM_MSM_DSI\ndrivers/gpu/drm/msm/msm_drv.h-293-int dsi_dev_attach(struct platform_device *pdev);\n--\ndrivers/gpu/drm/msm/msm_drv.h=350=struct msm_dp;\ndrivers/gpu/drm/msm/msm_drv.h:351:#ifdef CONFIG_DRM_MSM_DP\ndrivers/gpu/drm/msm/msm_drv.h-352-int __init msm_dp_register(void);\n--\n\n"
}

gemini-3.8-flash

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							input: 17325
							output: 37
							thoughts: 29
						

Here's my thinking process:

**Diving into the MSM DRM Driver Configuration**

Okay, so I need to understand the dependencies of `DRM_MSM`. My first instinct is to dive into the Kconfig file for that specific driver. `drivers/gpu/drm/msm/Kconfig` is the obvious place to find this configuration information. It's the standard location for driver configuration in the Linux kernel, so I'm expecting to find the `depends on` clauses, any `select` statements, and potentially even some default values that will shed light on what needs to be enabled or present for this driver to function correctly. This will give me the information I need to understand its relationship to other components of the system, which will assist me with troubleshooting or further configuration.

{
  "File": "drivers/gpu/drm/msm/Kconfig",
  "FirstLine": 1,
  "LineCount": 40
}

{
  "Contents": "   1:\t# SPDX-License-Identifier: GPL-2.0-only\n   2:\t\n   3:\tconfig DRM_MSM\n   4:\t\ttristate \"MSM DRM\"\n   5:\t\tdepends on DRM\n   6:\t\tdepends on ARCH_QCOM || SOC_IMX5 || COMPILE_TEST\n   7:\t\tdepends on COMMON_CLK\n   8:\t\tdepends on IOMMU_SUPPORT\n   9:\t\tdepends on OF\n  10:\t\tdepends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n\n  11:\t\tdepends on QCOM_OCMEM || QCOM_OCMEM=n\n  12:\t\tdepends on QCOM_LLCC || QCOM_LLCC=n\n  13:\t\tdepends on QCOM_COMMAND_DB || QCOM_COMMAND_DB=n\n  14:\t\tdepends on QCOM_SMEM || QCOM_SMEM=n\n  15:\t\tdepends on PM\n  16:\t\tselect IOMMU_IO_PGTABLE\n  17:\t\tselect QCOM_MDT_LOADER if ARCH_QCOM\n  18:\t\tselect REGULATOR\n  19:\t\tselect DRM_EXEC\n  20:\t\tselect DRM_GPUVM\n  21:\t\tselect DRM_SCHED\n  22:\t\tselect SHMEM\n  23:\t\tselect TMPFS\n  24:\t\tselect QCOM_SCM\n  25:\t\tselect QCOM_PAS\n  26:\t\tselect QCOM_UBWC_CONFIG if ARCH_QCOM \u0026\u0026 QCOM_SMEM\n  27:\t\tselect WANT_DEV_COREDUMP\n  28:\t\tselect SND_SOC_HDMI_CODEC if SND_SOC\n  29:\t\tselect SYNC_FILE\n  30:\t\tselect PM_OPP\n  31:\t\tselect NVMEM\n  32:\t\tselect PM_GENERIC_DOMAINS\n  33:\t\tselect TRACE_GPU_MEM\n  34:\t\thelp\n  35:\t\t  DRM/KMS driver for MSM/snapdragon.\n  36:\t\n  37:\tconfig DRM_MSM_GPU_STATE\n  38:\t\tbool\n  39:\t\tdepends on DRM_MSM \u0026\u0026 (DEBUG_FS || DEV_COREDUMP)\n  40:\t\tdefault y\n"
}

gemini-3.8-flash

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							input: 18119
							output: 46
							thoughts: 62
						

**Analyzing a Device Driver Probe**

Okay, so I'm looking at this configuration dependency: `depends on ARCH_QCOM || SOC_IMX5 || COMPILE_TEST`. It looks like this specific function or driver is only enabled if the architecture is Qualcomm, an i.MX5 system-on-a-chip, or for a compilation test. It's a conditional compilation. Now, I need to understand what this `msm_hdmi_phy_probe` is all about. Based on the name I'm guessing this might be the probe function for a HDMI physical layer? Right, that's what `phy` suggests. Let's dig into the code itself. Time to dive into the `drivers/gpu/drm/msm/hdmi/hdmi_phy.c` file and see what's actually going on in there.

{
  "File": "drivers/gpu/drm/msm/hdmi/hdmi_phy.c",
  "FirstLine": 140,
  "LineCount": 80
}

{
  "Contents": " 140:\t\n 141:\tstatic int msm_hdmi_phy_probe(struct platform_device *pdev)\n 142:\t{\n 143:\t\tstruct device *dev = \u0026pdev-\u003edev;\n 144:\t\tstruct hdmi_phy *phy;\n 145:\t\tint ret;\n 146:\t\n 147:\t\tphy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);\n 148:\t\tif (!phy)\n 149:\t\t\treturn -ENODEV;\n 150:\t\n 151:\t\tphy-\u003ecfg = (struct hdmi_phy_cfg *)of_device_get_match_data(dev);\n 152:\t\tif (!phy-\u003ecfg)\n 153:\t\t\treturn -ENODEV;\n 154:\t\n 155:\t\tphy-\u003emmio = msm_ioremap(pdev, \"hdmi_phy\");\n 156:\t\tif (IS_ERR(phy-\u003emmio)) {\n 157:\t\t\tDRM_DEV_ERROR(dev, \"%s: failed to map phy base\\n\", __func__);\n 158:\t\t\treturn -ENOMEM;\n 159:\t\t}\n 160:\t\n 161:\t\tphy-\u003epdev = pdev;\n 162:\t\n 163:\t\tret = msm_hdmi_phy_resource_init(phy);\n 164:\t\tif (ret)\n 165:\t\t\treturn ret;\n 166:\t\n 167:\t\tpm_runtime_enable(\u0026pdev-\u003edev);\n 168:\t\n 169:\t\tret = msm_hdmi_phy_resource_enable(phy);\n 170:\t\tif (ret)\n 171:\t\t\tgoto err_pm_disable;\n 172:\t\n 173:\t\tret = msm_hdmi_phy_pll_init(pdev, phy-\u003ecfg-\u003etype);\n 174:\t\tif (ret) {\n 175:\t\t\tDRM_DEV_ERROR(dev, \"couldn't init PLL\\n\");\n 176:\t\t\tmsm_hdmi_phy_resource_disable(phy);\n 177:\t\t\tgoto err_pm_disable;\n 178:\t\t}\n 179:\t\n 180:\t\tmsm_hdmi_phy_resource_disable(phy);\n 181:\t\n 182:\t\tplatform_set_drvdata(pdev, phy);\n 183:\t\n 184:\t\treturn 0;\n 185:\t\n 186:\terr_pm_disable:\n 187:\t\tpm_runtime_disable(dev);\n 188:\t\treturn ret;\n 189:\t}\n 190:\t\n 191:\tstatic void msm_hdmi_phy_remove(struct platform_device *pdev)\n 192:\t{\n 193:\t\tpm_runtime_disable(\u0026pdev-\u003edev);\n 194:\t}\n 195:\t\n 196:\tstatic const struct of_device_id msm_hdmi_phy_dt_match[] = {\n 197:\t\t{ .compatible = \"qcom,hdmi-phy-8660\",\n 198:\t\t  .data = \u0026msm_hdmi_phy_8x60_cfg },\n 199:\t\t{ .compatible = \"qcom,hdmi-phy-8960\",\n 200:\t\t  .data = \u0026msm_hdmi_phy_8960_cfg },\n 201:\t\t{ .compatible = \"qcom,hdmi-phy-8974\",\n 202:\t\t  .data = \u0026msm_hdmi_phy_8x74_cfg },\n 203:\t\t{ .compatible = \"qcom,hdmi-phy-8084\",\n 204:\t\t  .data = \u0026msm_hdmi_phy_8x74_cfg },\n 205:\t\t{ .compatible = \"qcom,hdmi-phy-8996\",\n 206:\t\t  .data = \u0026msm_hdmi_phy_8996_cfg },\n 207:\t\t{ .compatible = \"qcom,hdmi-phy-8998\",\n 208:\t\t  .data = \u0026msm_hdmi_phy_8998_cfg },\n 209:\t\t{}\n 210:\t};\n 211:\tMODULE_DEVICE_TABLE(of, msm_hdmi_phy_dt_match);\n 212:\t\n 213:\tstatic struct platform_driver msm_hdmi_phy_platform_driver = {\n 214:\t\t.probe      = msm_hdmi_phy_probe,\n 215:\t\t.remove     = msm_hdmi_phy_remove,\n 216:\t\t.driver     = {\n 217:\t\t\t.name   = \"msm_hdmi_phy\",\n 218:\t\t\t.of_match_table = msm_hdmi_phy_dt_match,\n 219:\t\t},\n"
}

gemini-3.8-flash

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							input: 19729
							output: 133
							thoughts: 1364
						

**Unreachable Code Path Analysis: msm_hdmi_phy_platform_driver**

Okay, let's break this down. My initial assessment is based on the `msm_hdmi_phy_platform_driver`. It's a platform driver, identified via Device Tree (`of_match_table`), with a specific set of compatible strings tied to Qualcomm Snapdragon SoCs (MSM8660, 8960, 8974, 8084, 8996, 8998). And this is all happening on the amd64 architecture, which raises a red flag immediately.

The fuzzing instructions are crystal clear. Reachability is key. They explicitly state that code unreachable in standard virtualized environments (like GCE or QEMU) should *not* be fuzzed. Section 2 further elaborates on the negative criteria, specifically highlighting structurally unreachable hardware and execution paths.

Considering that the target architecture is amd64, I need to confirm if this `msm_hdmi_phy_platform_driver` is ever instantiated on this architecture. The driver uses Device Tree, which, on amd64 (x86_64), is typically not the way Snapdragon SoCs are used. The Qualcomm HDMI PHY hardware has requirements for specific Qualcomm MMIO, clocks, and regulators, etc. My focus is on determining if `msm_hdmi_phy_probe()` could ever execute under these conditions.

Looking at the patch itself, it's modifying error handling within `msm_hdmi_phy_probe()`. This means the code only executes when an MSM HDMI PHY platform device is actually probed. Can that happen on amd64 within a QEMU/GCE environment? No. Qualcomm's MSM/Snapdragon is an ARM/ARM64 SoC. Even if `CONFIG_COMPILE_TEST` is enabled, the driver is *only* compile-tested on amd64, there are no MSM HDMI PHY devices on x86_64. Even on ARM, the specific hardware is required.

I need to confirm the conditions for the probe further. I need to make sure I'm not missing any Device Tree overlays or anything that *could* trigger this code. Syzkaller, which would be the likely environment for fuzzing this, runs on amd64 in a standard QEMU/GCE VM. There are no Qualcomm SoC hardware or Device Tree nodes for an MSM HDMI PHY.

The instructions specifically exclude vendor-specific hardware requiring physical ASICs or PCIe cards not emulated in standard QEMU. They also exclude code paths exclusive to different architectures, and the Qualcomm MSM DRM driver is an ARM/ARM64 SoC GPU/display driver. I've also checked syzkaller for mock platform devices or anything that might lead to `msm_hdmi_phy` being probed in this scenario. There are none.

In summary, the modified code is *structurally unreachable* on the target architecture (amd64). It requires specific hardware that is not emulated in standard QEMU/GCE environments.

Therefore, `WorthFuzzing` is `false`. `EnableConfigs` should be empty or null (or DRM_MSM, DRM_MSM_HDMI). `FocusSymbols` should also be empty. The reasoning is solid: The patch affects error handling within `msm_hdmi_phy_probe()`, which is a key part of the Qualcomm Snapdragon DRM driver on ARM/ARM64 SoCs. This specific platform driver depends on Qualcomm hardware not found in standard amd64 environments, rendering the code unreachable.

Time to call `set-results`.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies error handling in msm_hdmi_phy_probe() within the Qualcomm MSM DRM HDMI PHY driver. This driver is designed for Qualcomm Snapdragon ARM/ARM64 SoCs and binds via Device Tree to physical Qualcomm SoC hardware (e.g., MSM8996/MSM8998) not emulated in standard amd64 QEMU/GCE environments. Consequently, the modified probe error path is structurally unreachable on the target architecture (amd64).",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies error handling in msm_hdmi_phy_probe() within the Qualcomm MSM DRM HDMI PHY driver. This driver is designed for Qualcomm Snapdragon ARM/ARM64 SoCs and binds via Device Tree to physical Qualcomm SoC hardware (e.g., MSM8996/MSM8998) not emulated in standard amd64 QEMU/GCE environments. Consequently, the modified probe error path is structurally unreachable on the target architecture (amd64).",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

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