AI Trajectory

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies `mvneta_swbm_rx_frame()` in `drivers/net/ethernet/marvell/mvneta.c`, which is a driver for Marvell Armada 370/38x/XP/37xx SoC network interfaces (depends on ARCH_MVEBU or COMPILE_TEST). The driver targets specific ARM-based Marvell SoC hardware via Device Tree and is structurally unreachable on the amd64 target architecture in standard virtualized environments (QEMU/GCE). Furthermore, the modified function is part of the hardware packet reception path. Therefore, this change is not worth fuzzing.",
  "WorthFuzzing": false
}

null

{
  "PatchDiff": "commit 451b52a82563728674c30422f714102ba31d2048\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Tue Sep 22 11:18:51 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c\nindex 543e566425c1e..32416999f3d6b 100644\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -2341,6 +2341,7 @@ mvneta_swbm_rx_frame(struct mvneta_port *pp,\n \t/* Prefetch header */\n \tprefetch(data);\n \txdp_buff_clear_frags_flag(xdp);\n+\txdp_buff_clear_frag_pfmemalloc(xdp);\n \txdp_prepare_buff(xdp, data, pp-\u003erx_offset_correction + MVNETA_MH_SIZE,\n \t\t\t data_len, true);\n }\n"
}

core

null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies `mvneta_swbm_rx_frame()` in `drivers/net/ethernet/marvell/mvneta.c`, which is a driver for Marvell Armada 370/38x/XP/37xx SoC network interfaces (depends on ARCH_MVEBU or COMPILE_TEST). The driver targets specific ARM-based Marvell SoC hardware via Device Tree and is structurally unreachable on the amd64 target architecture in standard virtualized environments (QEMU/GCE). Furthermore, the modified function is part of the hardware packet reception path. Therefore, this change is not worth fuzzing.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit 451b52a82563728674c30422f714102ba31d2048
Author: syz-cluster <triage@syzkaller.com>
Date:   Tue Sep 22 11:18:51 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 543e566425c1e..32416999f3d6b 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2341,6 +2341,7 @@ mvneta_swbm_rx_frame(struct mvneta_port *pp,
 	/* Prefetch header */
 	prefetch(data);
 	xdp_buff_clear_frags_flag(xdp);
+	xdp_buff_clear_frag_pfmemalloc(xdp);
 	xdp_prepare_buff(xdp, data, pp->rx_offset_correction + MVNETA_MH_SIZE,
 			 data_len, true);
 }

gemini-3.8-flash

null

null

							input: 2903
							output: 35
							thoughts: 238
						

**Analyzing a Network Driver Patch**

Okay, so I'm looking at this diff in `drivers/net/ethernet/marvell/mvneta.c`. Seems like a straightforward addition: `xdp_buff_clear_frag_pfmemalloc(xdp);` is being added to `mvneta_swbm_rx_frame`. I need to understand the context.

My immediate thought is to figure out what this `mvneta` driver is all about. Which specific Marvell hardware or platform is it designed for? To get a handle on that, I should dig into the Kconfig file first.  I'll either use a tool like `grepper` to search through `drivers/net/ethernet/marvell/Kconfig`, or just read the file directly. Alternatively, a quick inspection of `mvneta.c` itself might give me some clues about the targeted hardware and any dependencies.  Knowing the target will help me understand why this `xdp_buff_clear_frag_pfmemalloc` is necessary. I need to understand the memory allocation and fragmentation scheme related to this XDP buffer.

no matches

{
  "Expression": "config NET_MVNETA",
  "PathPrefix": "drivers/net/ethernet/marvell"
}

{
  "error": "no matches"
}

gemini-3.8-flash

null

null

							input: 3427
							output: 27
							thoughts: 17
						

Here's my attempt at summarizing the thought process, tailored for an expert audience:

**Hunting for the Marvell Ethernet Kconfig**

Okay, so I need to configure something related to Marvell Ethernet drivers. Given the structure of the kernel source, I'm pretty certain the Kconfig file for this module will be under the `drivers/net/ethernet/marvell` directory. I'm operating on the assumption that this directory follows standard practices, so I'll find a Kconfig or similar configuration file there. Let's head over to that location and start digging. I'm expecting this to be the right place; it's the obvious logical location.

{
  "Dir": "drivers/net/ethernet/marvell"
}

{
  "Files": [
    "mv643xx_eth.c",
    "mvmdio.c",
    "mvneta.c",
    "mvneta_bm.c",
    "mvneta_bm.h",
    "pxa168_eth.c",
    "skge.c",
    "skge.h",
    "sky2.c",
    "sky2.h"
  ],
  "Subdirs": [
    "mvpp2",
    "octeon_ep",
    "octeon_ep_vf",
    "octeontx2",
    "prestera"
  ]
}

gemini-3.8-flash

null

null

							input: 3750
							output: 26
							thoughts: 17
						

Here's my thought process, as if I were the one thinking it:

**Digging into the `mvneta` Conundrum**

Okay, so I need to understand how `mvneta` is configured within the kernel. My best bet, given my experience, is to start with the Kconfig files. They're the source of truth for build-time configuration, and that's where I should be able to track down how this particular driver is handled. My instinct is to use `grep`. I'll run `grep` and look for the string `mvneta` across the Kconfig files. This will quickly show me where the relevant options are defined, their dependencies, and any other relevant configurations. That'll be the starting point to get my head around how `mvneta` is integrated.

{
  "Expression": "MVNETA",
  "PathPrefix": "drivers/net"
}

{
  "Output": "\nFull output is too long, showing 500 out of 2284 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/marvell/Kconfig=34=config MVMDIO\n--\ndrivers/net/ethernet/marvell/Kconfig-42-\ndrivers/net/ethernet/marvell/Kconfig:43:\t  This driver is used by the MV643XX_ETH and MVNETA drivers.\ndrivers/net/ethernet/marvell/Kconfig-44-\ndrivers/net/ethernet/marvell/Kconfig:45:config MVNETA_BM_ENABLE\ndrivers/net/ethernet/marvell/Kconfig-46-\ttristate \"Marvell Armada 38x/XP network interface BM support\"\ndrivers/net/ethernet/marvell/Kconfig:47:\tdepends on MVNETA\ndrivers/net/ethernet/marvell/Kconfig-48-\tdepends on !64BIT\n--\ndrivers/net/ethernet/marvell/Kconfig-58-\ndrivers/net/ethernet/marvell/Kconfig:59:config MVNETA\ndrivers/net/ethernet/marvell/Kconfig-60-\ttristate \"Marvell Armada 370/38x/XP/37xx network interface support\"\n--\ndrivers/net/ethernet/marvell/Kconfig-74-\ndrivers/net/ethernet/marvell/Kconfig:75:config MVNETA_BM\ndrivers/net/ethernet/marvell/Kconfig-76-\ttristate\ndrivers/net/ethernet/marvell/Kconfig-77-\tdepends on !64BIT\ndrivers/net/ethernet/marvell/Kconfig:78:\tdefault y if MVNETA=y \u0026\u0026 MVNETA_BM_ENABLE!=n\ndrivers/net/ethernet/marvell/Kconfig:79:\tdefault MVNETA_BM_ENABLE\ndrivers/net/ethernet/marvell/Kconfig-80-\tselect HWBM\n--\ndrivers/net/ethernet/marvell/Kconfig-82-\thelp\ndrivers/net/ethernet/marvell/Kconfig:83:\t  MVNETA_BM must not be 'm' if MVNETA=y, so this symbol ensures\ndrivers/net/ethernet/marvell/Kconfig-84-\t  that all dependencies are met.\n--\ndrivers/net/ethernet/marvell/Makefile=7=obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o\ndrivers/net/ethernet/marvell/Makefile:8:obj-$(CONFIG_MVNETA_BM) += mvneta_bm.o\ndrivers/net/ethernet/marvell/Makefile:9:obj-$(CONFIG_MVNETA) += mvneta.o\ndrivers/net/ethernet/marvell/Makefile-10-obj-$(CONFIG_MVPP2) += mvpp2/\n--\ndrivers/net/ethernet/marvell/mvneta.c-44-/* Registers */\ndrivers/net/ethernet/marvell/mvneta.c:45:#define MVNETA_RXQ_CONFIG_REG(q)                (0x1400 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:46:#define      MVNETA_RXQ_HW_BUF_ALLOC            BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:47:#define      MVNETA_RXQ_SHORT_POOL_ID_SHIFT\t4\ndrivers/net/ethernet/marvell/mvneta.c:48:#define      MVNETA_RXQ_SHORT_POOL_ID_MASK\t0x30\ndrivers/net/ethernet/marvell/mvneta.c:49:#define      MVNETA_RXQ_LONG_POOL_ID_SHIFT\t6\ndrivers/net/ethernet/marvell/mvneta.c:50:#define      MVNETA_RXQ_LONG_POOL_ID_MASK\t0xc0\ndrivers/net/ethernet/marvell/mvneta.c:51:#define      MVNETA_RXQ_PKT_OFFSET_ALL_MASK     (0xf    \u003c\u003c 8)\ndrivers/net/ethernet/marvell/mvneta.c:52:#define      MVNETA_RXQ_PKT_OFFSET_MASK(offs)   ((offs) \u003c\u003c 8)\ndrivers/net/ethernet/marvell/mvneta.c:53:#define MVNETA_RXQ_THRESHOLD_REG(q)             (0x14c0 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:54:#define      MVNETA_RXQ_NON_OCCUPIED(v)         ((v) \u003c\u003c 16)\ndrivers/net/ethernet/marvell/mvneta.c:55:#define MVNETA_RXQ_BASE_ADDR_REG(q)             (0x1480 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:56:#define MVNETA_RXQ_SIZE_REG(q)                  (0x14a0 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:57:#define      MVNETA_RXQ_BUF_SIZE_SHIFT          19\ndrivers/net/ethernet/marvell/mvneta.c:58:#define      MVNETA_RXQ_BUF_SIZE_MASK           (0x1fff \u003c\u003c 19)\ndrivers/net/ethernet/marvell/mvneta.c:59:#define MVNETA_RXQ_STATUS_REG(q)                (0x14e0 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:60:#define      MVNETA_RXQ_OCCUPIED_ALL_MASK       0x3fff\ndrivers/net/ethernet/marvell/mvneta.c:61:#define MVNETA_RXQ_STATUS_UPDATE_REG(q)         (0x1500 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:62:#define      MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT  16\ndrivers/net/ethernet/marvell/mvneta.c:63:#define      MVNETA_RXQ_ADD_NON_OCCUPIED_MAX    255\ndrivers/net/ethernet/marvell/mvneta.c:64:#define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool)\t(0x1700 + ((pool) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:65:#define      MVNETA_PORT_POOL_BUFFER_SZ_SHIFT\t3\ndrivers/net/ethernet/marvell/mvneta.c:66:#define      MVNETA_PORT_POOL_BUFFER_SZ_MASK\t0xfff8\ndrivers/net/ethernet/marvell/mvneta.c:67:#define MVNETA_PORT_RX_RESET                    0x1cc0\ndrivers/net/ethernet/marvell/mvneta.c:68:#define      MVNETA_PORT_RX_DMA_RESET           BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:69:#define MVNETA_PHY_ADDR                         0x2000\ndrivers/net/ethernet/marvell/mvneta.c:70:#define      MVNETA_PHY_ADDR_MASK               0x1f\ndrivers/net/ethernet/marvell/mvneta.c:71:#define MVNETA_MBUS_RETRY                       0x2010\ndrivers/net/ethernet/marvell/mvneta.c:72:#define MVNETA_UNIT_INTR_CAUSE                  0x2080\ndrivers/net/ethernet/marvell/mvneta.c:73:#define MVNETA_UNIT_CONTROL                     0x20B0\ndrivers/net/ethernet/marvell/mvneta.c:74:#define      MVNETA_PHY_POLLING_ENABLE          BIT(1)\ndrivers/net/ethernet/marvell/mvneta.c:75:#define MVNETA_WIN_BASE(w)                      (0x2200 + ((w) \u003c\u003c 3))\ndrivers/net/ethernet/marvell/mvneta.c:76:#define MVNETA_WIN_SIZE(w)                      (0x2204 + ((w) \u003c\u003c 3))\ndrivers/net/ethernet/marvell/mvneta.c:77:#define MVNETA_WIN_REMAP(w)                     (0x2280 + ((w) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:78:#define MVNETA_BASE_ADDR_ENABLE                 0x2290\ndrivers/net/ethernet/marvell/mvneta.c:79:#define      MVNETA_AC5_CNM_DDR_TARGET\t\t0x2\ndrivers/net/ethernet/marvell/mvneta.c:80:#define      MVNETA_AC5_CNM_DDR_ATTR\t\t0xb\ndrivers/net/ethernet/marvell/mvneta.c:81:#define MVNETA_ACCESS_PROTECT_ENABLE            0x2294\ndrivers/net/ethernet/marvell/mvneta.c:82:#define MVNETA_PORT_CONFIG                      0x2400\ndrivers/net/ethernet/marvell/mvneta.c:83:#define      MVNETA_UNI_PROMISC_MODE            BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:84:#define      MVNETA_DEF_RXQ(q)                  ((q) \u003c\u003c 1)\ndrivers/net/ethernet/marvell/mvneta.c:85:#define      MVNETA_DEF_RXQ_ARP(q)              ((q) \u003c\u003c 4)\ndrivers/net/ethernet/marvell/mvneta.c:86:#define      MVNETA_TX_UNSET_ERR_SUM            BIT(12)\ndrivers/net/ethernet/marvell/mvneta.c:87:#define      MVNETA_DEF_RXQ_TCP(q)              ((q) \u003c\u003c 16)\ndrivers/net/ethernet/marvell/mvneta.c:88:#define      MVNETA_DEF_RXQ_UDP(q)              ((q) \u003c\u003c 19)\ndrivers/net/ethernet/marvell/mvneta.c:89:#define      MVNETA_DEF_RXQ_BPDU(q)             ((q) \u003c\u003c 22)\ndrivers/net/ethernet/marvell/mvneta.c:90:#define      MVNETA_RX_CSUM_WITH_PSEUDO_HDR     BIT(25)\ndrivers/net/ethernet/marvell/mvneta.c:91:#define      MVNETA_PORT_CONFIG_DEFL_VALUE(q)   (MVNETA_DEF_RXQ(q)       | \\\ndrivers/net/ethernet/marvell/mvneta.c:92:\t\t\t\t\t\t MVNETA_DEF_RXQ_ARP(q)\t | \\\ndrivers/net/ethernet/marvell/mvneta.c:93:\t\t\t\t\t\t MVNETA_DEF_RXQ_TCP(q)\t | \\\ndrivers/net/ethernet/marvell/mvneta.c:94:\t\t\t\t\t\t MVNETA_DEF_RXQ_UDP(q)\t | \\\ndrivers/net/ethernet/marvell/mvneta.c:95:\t\t\t\t\t\t MVNETA_DEF_RXQ_BPDU(q)\t | \\\ndrivers/net/ethernet/marvell/mvneta.c:96:\t\t\t\t\t\t MVNETA_TX_UNSET_ERR_SUM | \\\ndrivers/net/ethernet/marvell/mvneta.c:97:\t\t\t\t\t\t MVNETA_RX_CSUM_WITH_PSEUDO_HDR)\ndrivers/net/ethernet/marvell/mvneta.c:98:#define MVNETA_PORT_CONFIG_EXTEND                0x2404\ndrivers/net/ethernet/marvell/mvneta.c:99:#define MVNETA_MAC_ADDR_LOW                      0x2414\ndrivers/net/ethernet/marvell/mvneta.c:100:#define MVNETA_MAC_ADDR_HIGH                     0x2418\ndrivers/net/ethernet/marvell/mvneta.c:101:#define MVNETA_SDMA_CONFIG                       0x241c\ndrivers/net/ethernet/marvell/mvneta.c:102:#define      MVNETA_SDMA_BRST_SIZE_16            4\ndrivers/net/ethernet/marvell/mvneta.c:103:#define      MVNETA_RX_BRST_SZ_MASK(burst)       ((burst) \u003c\u003c 1)\ndrivers/net/ethernet/marvell/mvneta.c:104:#define      MVNETA_RX_NO_DATA_SWAP              BIT(4)\ndrivers/net/ethernet/marvell/mvneta.c:105:#define      MVNETA_TX_NO_DATA_SWAP              BIT(5)\ndrivers/net/ethernet/marvell/mvneta.c:106:#define      MVNETA_DESC_SWAP                    BIT(6)\ndrivers/net/ethernet/marvell/mvneta.c:107:#define      MVNETA_TX_BRST_SZ_MASK(burst)       ((burst) \u003c\u003c 22)\ndrivers/net/ethernet/marvell/mvneta.c:108:#define\tMVNETA_VLAN_PRIO_TO_RXQ\t\t\t 0x2440\ndrivers/net/ethernet/marvell/mvneta.c:109:#define      MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) \u003c\u003c ((prio) * 3))\ndrivers/net/ethernet/marvell/mvneta.c:110:#define MVNETA_PORT_STATUS                       0x2444\ndrivers/net/ethernet/marvell/mvneta.c:111:#define      MVNETA_TX_IN_PRGRS                  BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:112:#define      MVNETA_TX_FIFO_EMPTY                BIT(8)\ndrivers/net/ethernet/marvell/mvneta.c:113:#define MVNETA_RX_MIN_FRAME_SIZE                 0x247c\ndrivers/net/ethernet/marvell/mvneta.c-114-/* Only exists on Armada XP and Armada 370 */\ndrivers/net/ethernet/marvell/mvneta.c:115:#define MVNETA_SERDES_CFG\t\t\t 0x24A0\ndrivers/net/ethernet/marvell/mvneta.c:116:#define      MVNETA_SGMII_SERDES_PROTO\t\t 0x0cc7\ndrivers/net/ethernet/marvell/mvneta.c:117:#define      MVNETA_QSGMII_SERDES_PROTO\t\t 0x0667\ndrivers/net/ethernet/marvell/mvneta.c:118:#define      MVNETA_HSGMII_SERDES_PROTO\t\t 0x1107\ndrivers/net/ethernet/marvell/mvneta.c:119:#define MVNETA_TYPE_PRIO                         0x24bc\ndrivers/net/ethernet/marvell/mvneta.c:120:#define      MVNETA_FORCE_UNI                    BIT(21)\ndrivers/net/ethernet/marvell/mvneta.c:121:#define MVNETA_TXQ_CMD_1                         0x24e4\ndrivers/net/ethernet/marvell/mvneta.c:122:#define MVNETA_TXQ_CMD                           0x2448\ndrivers/net/ethernet/marvell/mvneta.c:123:#define      MVNETA_TXQ_DISABLE_SHIFT            8\ndrivers/net/ethernet/marvell/mvneta.c:124:#define      MVNETA_TXQ_ENABLE_MASK              0x000000ff\ndrivers/net/ethernet/marvell/mvneta.c:125:#define MVNETA_RX_DISCARD_FRAME_COUNT\t\t 0x2484\ndrivers/net/ethernet/marvell/mvneta.c:126:#define MVNETA_OVERRUN_FRAME_COUNT\t\t 0x2488\ndrivers/net/ethernet/marvell/mvneta.c:127:#define MVNETA_GMAC_CLOCK_DIVIDER                0x24f4\ndrivers/net/ethernet/marvell/mvneta.c:128:#define      MVNETA_GMAC_1MS_CLOCK_ENABLE        BIT(31)\ndrivers/net/ethernet/marvell/mvneta.c:129:#define MVNETA_ACC_MODE                          0x2500\ndrivers/net/ethernet/marvell/mvneta.c:130:#define MVNETA_BM_ADDRESS                        0x2504\ndrivers/net/ethernet/marvell/mvneta.c:131:#define MVNETA_CPU_MAP(cpu)                      (0x2540 + ((cpu) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:132:#define      MVNETA_CPU_RXQ_ACCESS_ALL_MASK      0x000000ff\ndrivers/net/ethernet/marvell/mvneta.c:133:#define      MVNETA_CPU_TXQ_ACCESS_ALL_MASK      0x0000ff00\ndrivers/net/ethernet/marvell/mvneta.c:134:#define      MVNETA_CPU_RXQ_ACCESS(rxq)\t\t BIT(rxq)\ndrivers/net/ethernet/marvell/mvneta.c:135:#define      MVNETA_CPU_TXQ_ACCESS(txq)\t\t BIT(txq + 8)\ndrivers/net/ethernet/marvell/mvneta.c:136:#define MVNETA_RXQ_TIME_COAL_REG(q)              (0x2580 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c-137-\n--\ndrivers/net/ethernet/marvell/mvneta.c-145-\ndrivers/net/ethernet/marvell/mvneta.c:146:#define MVNETA_INTR_NEW_CAUSE                    0x25a0\ndrivers/net/ethernet/marvell/mvneta.c:147:#define MVNETA_INTR_NEW_MASK                     0x25a4\ndrivers/net/ethernet/marvell/mvneta.c-148-\n--\ndrivers/net/ethernet/marvell/mvneta.c-155- */\ndrivers/net/ethernet/marvell/mvneta.c:156:#define      MVNETA_TX_INTR_MASK(nr_txqs)        (((1 \u003c\u003c nr_txqs) - 1) \u003c\u003c 0)\ndrivers/net/ethernet/marvell/mvneta.c:157:#define      MVNETA_TX_INTR_MASK_ALL             (0xff \u003c\u003c 0)\ndrivers/net/ethernet/marvell/mvneta.c:158:#define      MVNETA_RX_INTR_MASK(nr_rxqs)        (((1 \u003c\u003c nr_rxqs) - 1) \u003c\u003c 8)\ndrivers/net/ethernet/marvell/mvneta.c:159:#define      MVNETA_RX_INTR_MASK_ALL             (0xff \u003c\u003c 8)\ndrivers/net/ethernet/marvell/mvneta.c:160:#define      MVNETA_MISCINTR_INTR_MASK           BIT(31)\ndrivers/net/ethernet/marvell/mvneta.c-161-\ndrivers/net/ethernet/marvell/mvneta.c:162:#define MVNETA_INTR_OLD_CAUSE                    0x25a8\ndrivers/net/ethernet/marvell/mvneta.c:163:#define MVNETA_INTR_OLD_MASK                     0x25ac\ndrivers/net/ethernet/marvell/mvneta.c-164-\ndrivers/net/ethernet/marvell/mvneta.c-165-/* Data Path Port/Queue Cause Register */\ndrivers/net/ethernet/marvell/mvneta.c:166:#define MVNETA_INTR_MISC_CAUSE                   0x25b0\ndrivers/net/ethernet/marvell/mvneta.c:167:#define MVNETA_INTR_MISC_MASK                    0x25b4\ndrivers/net/ethernet/marvell/mvneta.c-168-\ndrivers/net/ethernet/marvell/mvneta.c:169:#define      MVNETA_CAUSE_PHY_STATUS_CHANGE      BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:170:#define      MVNETA_CAUSE_LINK_CHANGE            BIT(1)\ndrivers/net/ethernet/marvell/mvneta.c:171:#define      MVNETA_CAUSE_PTP                    BIT(4)\ndrivers/net/ethernet/marvell/mvneta.c-172-\ndrivers/net/ethernet/marvell/mvneta.c:173:#define      MVNETA_CAUSE_INTERNAL_ADDR_ERR      BIT(7)\ndrivers/net/ethernet/marvell/mvneta.c:174:#define      MVNETA_CAUSE_RX_OVERRUN             BIT(8)\ndrivers/net/ethernet/marvell/mvneta.c:175:#define      MVNETA_CAUSE_RX_CRC_ERROR           BIT(9)\ndrivers/net/ethernet/marvell/mvneta.c:176:#define      MVNETA_CAUSE_RX_LARGE_PKT           BIT(10)\ndrivers/net/ethernet/marvell/mvneta.c:177:#define      MVNETA_CAUSE_TX_UNDERUN             BIT(11)\ndrivers/net/ethernet/marvell/mvneta.c:178:#define      MVNETA_CAUSE_PRBS_ERR               BIT(12)\ndrivers/net/ethernet/marvell/mvneta.c:179:#define      MVNETA_CAUSE_PSC_SYNC_CHANGE        BIT(13)\ndrivers/net/ethernet/marvell/mvneta.c:180:#define      MVNETA_CAUSE_SERDES_SYNC_ERR        BIT(14)\ndrivers/net/ethernet/marvell/mvneta.c-181-\ndrivers/net/ethernet/marvell/mvneta.c:182:#define      MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT    16\ndrivers/net/ethernet/marvell/mvneta.c:183:#define      MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK   (0xF \u003c\u003c MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)\ndrivers/net/ethernet/marvell/mvneta.c:184:#define      MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 \u003c\u003c (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))\ndrivers/net/ethernet/marvell/mvneta.c-185-\ndrivers/net/ethernet/marvell/mvneta.c:186:#define      MVNETA_CAUSE_TXQ_ERROR_SHIFT        24\ndrivers/net/ethernet/marvell/mvneta.c:187:#define      MVNETA_CAUSE_TXQ_ERROR_ALL_MASK     (0xFF \u003c\u003c MVNETA_CAUSE_TXQ_ERROR_SHIFT)\ndrivers/net/ethernet/marvell/mvneta.c:188:#define      MVNETA_CAUSE_TXQ_ERROR_MASK(q)      (1 \u003c\u003c (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))\ndrivers/net/ethernet/marvell/mvneta.c-189-\ndrivers/net/ethernet/marvell/mvneta.c:190:#define MVNETA_INTR_ENABLE                       0x25b8\ndrivers/net/ethernet/marvell/mvneta.c:191:#define      MVNETA_TXQ_INTR_ENABLE_ALL_MASK     0x0000ff00\ndrivers/net/ethernet/marvell/mvneta.c:192:#define      MVNETA_RXQ_INTR_ENABLE_ALL_MASK     0x000000ff\ndrivers/net/ethernet/marvell/mvneta.c-193-\ndrivers/net/ethernet/marvell/mvneta.c:194:#define MVNETA_RXQ_CMD                           0x2680\ndrivers/net/ethernet/marvell/mvneta.c:195:#define      MVNETA_RXQ_DISABLE_SHIFT            8\ndrivers/net/ethernet/marvell/mvneta.c:196:#define      MVNETA_RXQ_ENABLE_MASK              0x000000ff\ndrivers/net/ethernet/marvell/mvneta.c-197-#define MVETH_TXQ_TOKEN_COUNT_REG(q)             (0x2700 + ((q) \u003c\u003c 4))\ndrivers/net/ethernet/marvell/mvneta.c-198-#define MVETH_TXQ_TOKEN_CFG_REG(q)               (0x2704 + ((q) \u003c\u003c 4))\ndrivers/net/ethernet/marvell/mvneta.c:199:#define MVNETA_GMAC_CTRL_0                       0x2c00\ndrivers/net/ethernet/marvell/mvneta.c:200:#define      MVNETA_GMAC_MAX_RX_SIZE_SHIFT       2\ndrivers/net/ethernet/marvell/mvneta.c:201:#define      MVNETA_GMAC_MAX_RX_SIZE_MASK        0x7ffc\ndrivers/net/ethernet/marvell/mvneta.c:202:#define      MVNETA_GMAC0_PORT_1000BASE_X        BIT(1)\ndrivers/net/ethernet/marvell/mvneta.c:203:#define      MVNETA_GMAC0_PORT_ENABLE            BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:204:#define MVNETA_GMAC_CTRL_2                       0x2c08\ndrivers/net/ethernet/marvell/mvneta.c:205:#define      MVNETA_GMAC2_INBAND_AN_ENABLE       BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:206:#define      MVNETA_GMAC2_PCS_ENABLE             BIT(3)\ndrivers/net/ethernet/marvell/mvneta.c:207:#define      MVNETA_GMAC2_PORT_RGMII             BIT(4)\ndrivers/net/ethernet/marvell/mvneta.c:208:#define      MVNETA_GMAC2_PORT_RESET             BIT(6)\ndrivers/net/ethernet/marvell/mvneta.c:209:#define MVNETA_GMAC_STATUS                       0x2c10\ndrivers/net/ethernet/marvell/mvneta.c:210:#define      MVNETA_GMAC_LINK_UP                 BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:211:#define      MVNETA_GMAC_SPEED_1000              BIT(1)\ndrivers/net/ethernet/marvell/mvneta.c:212:#define      MVNETA_GMAC_SPEED_100               BIT(2)\ndrivers/net/ethernet/marvell/mvneta.c:213:#define      MVNETA_GMAC_FULL_DUPLEX             BIT(3)\ndrivers/net/ethernet/marvell/mvneta.c:214:#define      MVNETA_GMAC_RX_FLOW_CTRL_ENABLE     BIT(4)\ndrivers/net/ethernet/marvell/mvneta.c:215:#define      MVNETA_GMAC_TX_FLOW_CTRL_ENABLE     BIT(5)\ndrivers/net/ethernet/marvell/mvneta.c:216:#define      MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE     BIT(6)\ndrivers/net/ethernet/marvell/mvneta.c:217:#define      MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE     BIT(7)\ndrivers/net/ethernet/marvell/mvneta.c:218:#define      MVNETA_GMAC_AN_COMPLETE             BIT(11)\ndrivers/net/ethernet/marvell/mvneta.c:219:#define      MVNETA_GMAC_SYNC_OK                 BIT(14)\ndrivers/net/ethernet/marvell/mvneta.c:220:#define MVNETA_GMAC_AUTONEG_CONFIG               0x2c0c\ndrivers/net/ethernet/marvell/mvneta.c:221:#define      MVNETA_GMAC_FORCE_LINK_DOWN         BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:222:#define      MVNETA_GMAC_FORCE_LINK_PASS         BIT(1)\ndrivers/net/ethernet/marvell/mvneta.c:223:#define      MVNETA_GMAC_INBAND_AN_ENABLE        BIT(2)\ndrivers/net/ethernet/marvell/mvneta.c:224:#define      MVNETA_GMAC_AN_BYPASS_ENABLE        BIT(3)\ndrivers/net/ethernet/marvell/mvneta.c:225:#define      MVNETA_GMAC_INBAND_RESTART_AN       BIT(4)\ndrivers/net/ethernet/marvell/mvneta.c:226:#define      MVNETA_GMAC_CONFIG_MII_SPEED        BIT(5)\ndrivers/net/ethernet/marvell/mvneta.c:227:#define      MVNETA_GMAC_CONFIG_GMII_SPEED       BIT(6)\ndrivers/net/ethernet/marvell/mvneta.c:228:#define      MVNETA_GMAC_AN_SPEED_EN             BIT(7)\ndrivers/net/ethernet/marvell/mvneta.c:229:#define      MVNETA_GMAC_CONFIG_FLOW_CTRL        BIT(8)\ndrivers/net/ethernet/marvell/mvneta.c:230:#define      MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL    BIT(9)\ndrivers/net/ethernet/marvell/mvneta.c:231:#define      MVNETA_GMAC_AN_FLOW_CTRL_EN         BIT(11)\ndrivers/net/ethernet/marvell/mvneta.c:232:#define      MVNETA_GMAC_CONFIG_FULL_DUPLEX      BIT(12)\ndrivers/net/ethernet/marvell/mvneta.c:233:#define      MVNETA_GMAC_AN_DUPLEX_EN            BIT(13)\ndrivers/net/ethernet/marvell/mvneta.c:234:#define MVNETA_GMAC_CTRL_4                       0x2c90\ndrivers/net/ethernet/marvell/mvneta.c:235:#define      MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE  BIT(1)\ndrivers/net/ethernet/marvell/mvneta.c:236:#define MVNETA_MIB_COUNTERS_BASE                 0x3000\ndrivers/net/ethernet/marvell/mvneta.c:237:#define      MVNETA_MIB_LATE_COLLISION           0x7c\ndrivers/net/ethernet/marvell/mvneta.c:238:#define MVNETA_DA_FILT_SPEC_MCAST                0x3400\ndrivers/net/ethernet/marvell/mvneta.c:239:#define MVNETA_DA_FILT_OTH_MCAST                 0x3500\ndrivers/net/ethernet/marvell/mvneta.c:240:#define MVNETA_DA_FILT_UCAST_BASE                0x3600\ndrivers/net/ethernet/marvell/mvneta.c:241:#define MVNETA_TXQ_BASE_ADDR_REG(q)              (0x3c00 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:242:#define MVNETA_TXQ_SIZE_REG(q)                   (0x3c20 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:243:#define      MVNETA_TXQ_SENT_THRESH_ALL_MASK     0x3fff0000\ndrivers/net/ethernet/marvell/mvneta.c:244:#define      MVNETA_TXQ_SENT_THRESH_MASK(coal)   ((coal) \u003c\u003c 16)\ndrivers/net/ethernet/marvell/mvneta.c:245:#define MVNETA_TXQ_UPDATE_REG(q)                 (0x3c60 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:246:#define      MVNETA_TXQ_DEC_SENT_SHIFT           16\ndrivers/net/ethernet/marvell/mvneta.c:247:#define      MVNETA_TXQ_DEC_SENT_MASK            0xff\ndrivers/net/ethernet/marvell/mvneta.c:248:#define MVNETA_TXQ_STATUS_REG(q)                 (0x3c40 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:249:#define      MVNETA_TXQ_SENT_DESC_SHIFT          16\ndrivers/net/ethernet/marvell/mvneta.c:250:#define      MVNETA_TXQ_SENT_DESC_MASK           0x3fff0000\ndrivers/net/ethernet/marvell/mvneta.c:251:#define MVNETA_PORT_TX_RESET                     0x3cf0\ndrivers/net/ethernet/marvell/mvneta.c:252:#define      MVNETA_PORT_TX_DMA_RESET            BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:253:#define MVNETA_TXQ_CMD1_REG\t\t\t 0x3e00\ndrivers/net/ethernet/marvell/mvneta.c:254:#define      MVNETA_TXQ_CMD1_BW_LIM_SEL_V1\t BIT(3)\ndrivers/net/ethernet/marvell/mvneta.c:255:#define      MVNETA_TXQ_CMD1_BW_LIM_EN\t\t BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:256:#define MVNETA_REFILL_NUM_CLK_REG\t\t 0x3e08\ndrivers/net/ethernet/marvell/mvneta.c:257:#define      MVNETA_REFILL_MAX_NUM_CLK\t\t 0x0000ffff\ndrivers/net/ethernet/marvell/mvneta.c:258:#define MVNETA_TX_MTU                            0x3e0c\ndrivers/net/ethernet/marvell/mvneta.c:259:#define MVNETA_TX_TOKEN_SIZE                     0x3e14\ndrivers/net/ethernet/marvell/mvneta.c:260:#define      MVNETA_TX_TOKEN_SIZE_MAX            0xffffffff\ndrivers/net/ethernet/marvell/mvneta.c:261:#define MVNETA_TXQ_BUCKET_REFILL_REG(q)\t\t (0x3e20 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:262:#define      MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK\t0x3ff00000\ndrivers/net/ethernet/marvell/mvneta.c:263:#define      MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT\t20\ndrivers/net/ethernet/marvell/mvneta.c:264:#define      MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX\t 0x0007ffff\ndrivers/net/ethernet/marvell/mvneta.c:265:#define MVNETA_TXQ_TOKEN_SIZE_REG(q)             (0x3e40 + ((q) \u003c\u003c 2))\ndrivers/net/ethernet/marvell/mvneta.c:266:#define      MVNETA_TXQ_TOKEN_SIZE_MAX           0x7fffffff\ndrivers/net/ethernet/marvell/mvneta.c-267-\n--\ndrivers/net/ethernet/marvell/mvneta.c-273-/* Base period for the rate limit algorithm */\ndrivers/net/ethernet/marvell/mvneta.c:274:#define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS\t100\ndrivers/net/ethernet/marvell/mvneta.c-275-\ndrivers/net/ethernet/marvell/mvneta.c-276-/* Number of Base Period to wait between each bucket refill */\ndrivers/net/ethernet/marvell/mvneta.c:277:#define MVNETA_TXQ_BUCKET_REFILL_PERIOD\t1000\ndrivers/net/ethernet/marvell/mvneta.c-278-\n--\ndrivers/net/ethernet/marvell/mvneta.c-281- */\ndrivers/net/ethernet/marvell/mvneta.c:282:#define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \\\ndrivers/net/ethernet/marvell/mvneta.c:283:\t\t\t\t\t (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \\\ndrivers/net/ethernet/marvell/mvneta.c:284:\t\t\t\t\t  MVNETA_TXQ_BUCKET_REFILL_PERIOD))\ndrivers/net/ethernet/marvell/mvneta.c-285-\ndrivers/net/ethernet/marvell/mvneta.c:286:#define MVNETA_LPI_CTRL_0                        0x2cc0\ndrivers/net/ethernet/marvell/mvneta.c:287:#define      MVNETA_LPI_CTRL_0_TS                (0xff \u003c\u003c 8)\ndrivers/net/ethernet/marvell/mvneta.c:288:#define MVNETA_LPI_CTRL_1                        0x2cc4\ndrivers/net/ethernet/marvell/mvneta.c:289:#define      MVNETA_LPI_CTRL_1_REQUEST_ENABLE    BIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:290:#define      MVNETA_LPI_CTRL_1_REQUEST_FORCE     BIT(1)\ndrivers/net/ethernet/marvell/mvneta.c:291:#define      MVNETA_LPI_CTRL_1_MANUAL_MODE       BIT(2)\ndrivers/net/ethernet/marvell/mvneta.c:292:#define      MVNETA_LPI_CTRL_1_TW                (0xfff \u003c\u003c 4)\ndrivers/net/ethernet/marvell/mvneta.c:293:#define MVNETA_LPI_CTRL_2                        0x2cc8\ndrivers/net/ethernet/marvell/mvneta.c:294:#define MVNETA_LPI_STATUS                        0x2ccc\ndrivers/net/ethernet/marvell/mvneta.c-295-\ndrivers/net/ethernet/marvell/mvneta.c:296:#define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK\t 0xff\ndrivers/net/ethernet/marvell/mvneta.c-297-\ndrivers/net/ethernet/marvell/mvneta.c-298-/* Descriptor ring Macros */\ndrivers/net/ethernet/marvell/mvneta.c:299:#define MVNETA_QUEUE_NEXT_DESC(q, index)\t\\\ndrivers/net/ethernet/marvell/mvneta.c-300-\t(((index) \u003c (q)-\u003elast_desc) ? ((index) + 1) : 0)\n--\ndrivers/net/ethernet/marvell/mvneta.c-304-/* Coalescing */\ndrivers/net/ethernet/marvell/mvneta.c:305:#define MVNETA_TXDONE_COAL_PKTS\t\t0\t/* interrupt per packet */\ndrivers/net/ethernet/marvell/mvneta.c:306:#define MVNETA_RX_COAL_PKTS\t\t32\ndrivers/net/ethernet/marvell/mvneta.c:307:#define MVNETA_RX_COAL_USEC\t\t100\ndrivers/net/ethernet/marvell/mvneta.c-308-\n--\ndrivers/net/ethernet/marvell/mvneta.c-316- */\ndrivers/net/ethernet/marvell/mvneta.c:317:#define MVNETA_MH_SIZE\t\t\t2\ndrivers/net/ethernet/marvell/mvneta.c-318-\ndrivers/net/ethernet/marvell/mvneta.c:319:#define MVNETA_VLAN_TAG_LEN             4\ndrivers/net/ethernet/marvell/mvneta.c-320-\ndrivers/net/ethernet/marvell/mvneta.c:321:#define MVNETA_TX_CSUM_DEF_SIZE\t\t1600\ndrivers/net/ethernet/marvell/mvneta.c:322:#define MVNETA_TX_CSUM_MAX_SIZE\t\t9800\ndrivers/net/ethernet/marvell/mvneta.c:323:#define MVNETA_ACC_MODE_EXT1\t\t1\ndrivers/net/ethernet/marvell/mvneta.c:324:#define MVNETA_ACC_MODE_EXT2\t\t2\ndrivers/net/ethernet/marvell/mvneta.c-325-\ndrivers/net/ethernet/marvell/mvneta.c:326:#define MVNETA_MAX_DECODE_WIN\t\t6\ndrivers/net/ethernet/marvell/mvneta.c-327-\ndrivers/net/ethernet/marvell/mvneta.c-328-/* Timeout constants */\ndrivers/net/ethernet/marvell/mvneta.c:329:#define MVNETA_TX_DISABLE_TIMEOUT_MSEC\t1000\ndrivers/net/ethernet/marvell/mvneta.c:330:#define MVNETA_RX_DISABLE_TIMEOUT_MSEC\t1000\ndrivers/net/ethernet/marvell/mvneta.c:331:#define MVNETA_TX_FIFO_EMPTY_TIMEOUT\t10000\ndrivers/net/ethernet/marvell/mvneta.c-332-\ndrivers/net/ethernet/marvell/mvneta.c:333:#define MVNETA_TX_MTU_MAX\t\t0x3ffff\ndrivers/net/ethernet/marvell/mvneta.c-334-\n--\ndrivers/net/ethernet/marvell/mvneta.c-337- */\ndrivers/net/ethernet/marvell/mvneta.c:338:#define MVNETA_RSS_LU_TABLE_SIZE\t1\ndrivers/net/ethernet/marvell/mvneta.c-339-\ndrivers/net/ethernet/marvell/mvneta.c-340-/* Max number of Rx descriptors */\ndrivers/net/ethernet/marvell/mvneta.c:341:#define MVNETA_MAX_RXD 512\ndrivers/net/ethernet/marvell/mvneta.c-342-\ndrivers/net/ethernet/marvell/mvneta.c-343-/* Max number of Tx descriptors */\ndrivers/net/ethernet/marvell/mvneta.c:344:#define MVNETA_MAX_TXD 1024\ndrivers/net/ethernet/marvell/mvneta.c-345-\ndrivers/net/ethernet/marvell/mvneta.c-346-/* Max number of allowed TCP segments for software TSO */\ndrivers/net/ethernet/marvell/mvneta.c:347:#define MVNETA_MAX_TSO_SEGS 100\ndrivers/net/ethernet/marvell/mvneta.c-348-\ndrivers/net/ethernet/marvell/mvneta.c:349:#define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)\ndrivers/net/ethernet/marvell/mvneta.c-350-\ndrivers/net/ethernet/marvell/mvneta.c-351-/* The size of a TSO header page */\ndrivers/net/ethernet/marvell/mvneta.c:352:#define MVNETA_TSO_PAGE_SIZE (2 * PAGE_SIZE)\ndrivers/net/ethernet/marvell/mvneta.c-353-\ndrivers/net/ethernet/marvell/mvneta.c-354-/* Number of TSO headers per page. This should be a power of 2 */\ndrivers/net/ethernet/marvell/mvneta.c:355:#define MVNETA_TSO_PER_PAGE (MVNETA_TSO_PAGE_SIZE / TSO_HEADER_SIZE)\ndrivers/net/ethernet/marvell/mvneta.c-356-\ndrivers/net/ethernet/marvell/mvneta.c-357-/* Maximum number of TSO header pages */\ndrivers/net/ethernet/marvell/mvneta.c:358:#define MVNETA_MAX_TSO_PAGES (MVNETA_MAX_TXD / MVNETA_TSO_PER_PAGE)\ndrivers/net/ethernet/marvell/mvneta.c-359-\ndrivers/net/ethernet/marvell/mvneta.c-360-/* descriptor aligned size */\ndrivers/net/ethernet/marvell/mvneta.c:361:#define MVNETA_DESC_ALIGNED_SIZE\t32\ndrivers/net/ethernet/marvell/mvneta.c-362-\n--\ndrivers/net/ethernet/marvell/mvneta.c-364- * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet\ndrivers/net/ethernet/marvell/mvneta.c:365: * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.\ndrivers/net/ethernet/marvell/mvneta.c-366- */\ndrivers/net/ethernet/marvell/mvneta.c:367:#define MVNETA_RX_PKT_OFFSET_CORRECTION\t\t64\ndrivers/net/ethernet/marvell/mvneta.c-368-\ndrivers/net/ethernet/marvell/mvneta.c:369:#define MVNETA_RX_PKT_SIZE(mtu) \\\ndrivers/net/ethernet/marvell/mvneta.c:370:\tALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \\\ndrivers/net/ethernet/marvell/mvneta.c-371-\t      ETH_HLEN + ETH_FCS_LEN,\t\t\t     \\\n--\ndrivers/net/ethernet/marvell/mvneta.c-374-/* Driver assumes that the last 3 bits are 0 */\ndrivers/net/ethernet/marvell/mvneta.c:375:#define MVNETA_SKB_HEADROOM\tALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8)\ndrivers/net/ethernet/marvell/mvneta.c:376:#define MVNETA_SKB_PAD\t(SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \\\ndrivers/net/ethernet/marvell/mvneta.c:377:\t\t\t MVNETA_SKB_HEADROOM))\ndrivers/net/ethernet/marvell/mvneta.c:378:#define MVNETA_MAX_RX_BUF_SIZE\t(PAGE_SIZE - MVNETA_SKB_PAD)\ndrivers/net/ethernet/marvell/mvneta.c-379-\ndrivers/net/ethernet/marvell/mvneta.c:380:#define MVNETA_RX_GET_BM_POOL_ID(rxd) \\\ndrivers/net/ethernet/marvell/mvneta.c:381:\t(((rxd)-\u003estatus \u0026 MVNETA_RXD_BM_POOL_MASK) \u003e\u003e MVNETA_RXD_BM_POOL_SHIFT)\ndrivers/net/ethernet/marvell/mvneta.c-382-\n--\ndrivers/net/ethernet/marvell/mvneta.c=397=struct mvneta_statistic {\n--\ndrivers/net/ethernet/marvell/mvneta.c-406-\ndrivers/net/ethernet/marvell/mvneta.c:407:#define MVNETA_XDP_PASS\t\t0\ndrivers/net/ethernet/marvell/mvneta.c:408:#define MVNETA_XDP_DROPPED\tBIT(0)\ndrivers/net/ethernet/marvell/mvneta.c:409:#define MVNETA_XDP_TX\t\tBIT(1)\ndrivers/net/ethernet/marvell/mvneta.c:410:#define MVNETA_XDP_REDIR\tBIT(2)\ndrivers/net/ethernet/marvell/mvneta.c-411-\n--\ndrivers/net/ethernet/marvell/mvneta.c=497=enum {\ndrivers/net/ethernet/marvell/mvneta.c:498:\t__MVNETA_DOWN,\ndrivers/net/ethernet/marvell/mvneta.c-499-};\n--\ndrivers/net/ethernet/marvell/mvneta.c=501=struct mvneta_port {\n--\ndrivers/net/ethernet/marvell/mvneta.c-549-\ndrivers/net/ethernet/marvell/mvneta.c:550:\tu32 indir[MVNETA_RSS_LU_TABLE_SIZE];\ndrivers/net/ethernet/marvell/mvneta.c-551-\n--\ndrivers/net/ethernet/marvell/mvneta.c-563-\ndrivers/net/ethernet/marvell/mvneta.c:564:#define MVNETA_TX_L3_OFF_SHIFT\t0\ndrivers/net/ethernet/marvell/mvneta.c:565:#define MVNETA_TX_IP_HLEN_SHIFT\t8\ndrivers/net/ethernet/marvell/mvneta.c:566:#define MVNETA_TX_L4_UDP\tBIT(16)\ndrivers/net/ethernet/marvell/mvneta.c:567:#define MVNETA_TX_L3_IP6\tBIT(17)\ndrivers/net/ethernet/marvell/mvneta.c:568:#define MVNETA_TXD_IP_CSUM\tBIT(18)\ndrivers/net/ethernet/marvell/mvneta.c:569:#define MVNETA_TXD_Z_PAD\tBIT(19)\ndrivers/net/ethernet/marvell/mvneta.c:570:#define MVNETA_TXD_L_DESC\tBIT(20)\ndrivers/net/ethernet/marvell/mvneta.c:571:#define MVNETA_TXD_F_DESC\tBIT(21)\ndrivers/net/ethernet/marvell/mvneta.c:572:#define MVNETA_TXD_FLZ_DESC\t(MVNETA_TXD_Z_PAD  | \\\ndrivers/net/ethernet/marvell/mvneta.c:573:\t\t\t\t MVNETA_TXD_L_DESC | \\\ndrivers/net/ethernet/marvell/mvneta.c:574:\t\t\t\t MVNETA_TXD_F_DESC)\ndrivers/net/ethernet/marvell/mvneta.c:575:#define MVNETA_TX_L4_CSUM_FULL\tBIT(30)\ndrivers/net/ethernet/marvell/mvneta.c:576:#define MVNETA_TX_L4_CSUM_NOT\tBIT(31)\ndrivers/net/ethernet/marvell/mvneta.c-577-\ndrivers/net/ethernet/marvell/mvneta.c:578:#define MVNETA_RXD_ERR_CRC\t\t0x0\ndrivers/net/ethernet/marvell/mvneta.c:579:#define MVNETA_RXD_BM_POOL_SHIFT\t13\ndrivers/net/ethernet/marvell/mvneta.c:580:#define MVNETA_RXD_BM_POOL_MASK\t\t(BIT(13) | BIT(14))\ndrivers/net/ethernet/marvell/mvneta.c:581:#define MVNETA_RXD_ERR_SUMMARY\t\tBIT(16)\ndrivers/net/ethernet/marvell/mvneta.c:582:#define MVNETA_RXD_ERR_OVERRUN\t\tBIT(17)\ndrivers/net/ethernet/marvell/mvneta.c:583:#define MVNETA_RXD_ERR_LEN\t\tBIT(18)\ndrivers/net/ethernet/marvell/mvneta.c:584:#define MVNETA_RXD_ERR_RESOURCE\t\t(BIT(17) | BIT(18))\ndrivers/net/ethernet/marvell/mvneta.c:585:#define MVNETA_RXD_ERR_CODE_MASK\t(BIT(17) | BIT(18))\ndrivers/net/ethernet/marvell/mvneta.c:586:#define MVNETA_RXD_L3_IP4\t\tBIT(25)\ndrivers/net/ethernet/marvell/mvneta.c:587:#define MVNETA_RXD_LAST_DESC\t\tBIT(26)\ndrivers/net/ethernet/marvell/mvneta.c:588:#define MVNETA_RXD_FIRST_DESC\t\tBIT(27)\ndrivers/net/ethernet/marvell/mvneta.c:589:#define MVNETA_RXD_FIRST_LAST_DESC\t(MVNETA_RXD_FIRST_DESC | \\\ndrivers/net/ethernet/marvell/mvneta.c:590:\t\t\t\t\t MVNETA_RXD_LAST_DESC)\ndrivers/net/ethernet/marvell/mvneta.c:591:#define MVNETA_RXD_L4_CSUM_OK\t\tBIT(30)\ndrivers/net/ethernet/marvell/mvneta.c-592-\n--\ndrivers/net/ethernet/marvell/mvneta.c=645=enum mvneta_tx_buf_type {\ndrivers/net/ethernet/marvell/mvneta.c:646:\tMVNETA_TYPE_TSO,\ndrivers/net/ethernet/marvell/mvneta.c:647:\tMVNETA_TYPE_SKB,\ndrivers/net/ethernet/marvell/mvneta.c:648:\tMVNETA_TYPE_XDP_TX,\ndrivers/net/ethernet/marvell/mvneta.c:649:\tMVNETA_TYPE_XDP_NDO,\ndrivers/net/ethernet/marvell/mvneta.c-650-};\n--\ndrivers/net/ethernet/marvell/mvneta.c=660=struct mvneta_tx_queue {\n--\ndrivers/net/ethernet/marvell/mvneta.c-698-\t/* DMA buffers for TSO headers */\ndrivers/net/ethernet/marvell/mvneta.c:699:\tchar *tso_hdrs[MVNETA_MAX_TSO_PAGES];\ndrivers/net/ethernet/marvell/mvneta.c-700-\ndrivers/net/ethernet/marvell/mvneta.c-701-\t/* DMA address of TSO headers */\ndrivers/net/ethernet/marvell/mvneta.c:702:\tdma_addr_t tso_hdrs_phys[MVNETA_MAX_TSO_PAGES];\ndrivers/net/ethernet/marvell/mvneta.c-703-\n--\ndrivers/net/ethernet/marvell/mvneta.c=754=static int global_port_id;\ndrivers/net/ethernet/marvell/mvneta.c-755-\ndrivers/net/ethernet/marvell/mvneta.c:756:#define MVNETA_DRIVER_NAME \"mvneta\"\ndrivers/net/ethernet/marvell/mvneta.c:757:#define MVNETA_DRIVER_VERSION \"1.0\"\ndrivers/net/ethernet/marvell/mvneta.c-758-\n--\ndrivers/net/ethernet/marvell/mvneta.c=791=static void mvneta_mib_counters_clear(struct mvneta_port *pp)\n--\ndrivers/net/ethernet/marvell/mvneta.c-795-\t/* Perform dummy reads from MIB counters */\ndrivers/net/ethernet/marvell/mvneta.c:796:\tfor (i = 0; i \u003c MVNETA_MIB_LATE_COLLISION; i += 4)\ndrivers/net/ethernet/marvell/mvneta.c:797:\t\tmvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));\ndrivers/net/ethernet/marvell/mvneta.c:798:\tmvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);\ndrivers/net/ethernet/marvell/mvneta.c:799:\tmvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);\ndrivers/net/ethernet/marvell/mvneta.c-800-}\n--\ndrivers/net/ethernet/marvell/mvneta.c=849=static int mvneta_rxq_desc_is_first_last(u32 status)\ndrivers/net/ethernet/marvell/mvneta.c-850-{\ndrivers/net/ethernet/marvell/mvneta.c:851:\treturn (status \u0026 MVNETA_RXD_FIRST_LAST_DESC) ==\ndrivers/net/ethernet/marvell/mvneta.c:852:\t\tMVNETA_RXD_FIRST_LAST_DESC;\ndrivers/net/ethernet/marvell/mvneta.c-853-}\n--\ndrivers/net/ethernet/marvell/mvneta.c=856=static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,\n--\ndrivers/net/ethernet/marvell/mvneta.c-859-{\ndrivers/net/ethernet/marvell/mvneta.c:860:\t/* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can\ndrivers/net/ethernet/marvell/mvneta.c-861-\t * be added at once\ndrivers/net/ethernet/marvell/mvneta.c-862-\t */\ndrivers/net/ethernet/marvell/mvneta.c:863:\twhile (ndescs \u003e MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {\ndrivers/net/ethernet/marvell/mvneta.c:864:\t\tmvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq-\u003eid),\ndrivers/net/ethernet/marvell/mvneta.c:865:\t\t\t    (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX \u003c\u003c\ndrivers/net/ethernet/marvell/mvneta.c:866:\t\t\t     MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));\ndrivers/net/ethernet/marvell/mvneta.c:867:\t\tndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;\ndrivers/net/ethernet/marvell/mvneta.c-868-\t}\ndrivers/net/ethernet/marvell/mvneta.c-869-\ndrivers/net/ethernet/marvell/mvneta.c:870:\tmvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq-\u003eid),\ndrivers/net/ethernet/marvell/mvneta.c:871:\t\t    (ndescs \u003c\u003c MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));\ndrivers/net/ethernet/marvell/mvneta.c-872-}\n--\ndrivers/net/ethernet/marvell/mvneta.c=875=static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,\n--\ndrivers/net/ethernet/marvell/mvneta.c-879-\ndrivers/net/ethernet/marvell/mvneta.c:880:\tval = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq-\u003eid));\ndrivers/net/ethernet/marvell/mvneta.c:881:\treturn val \u0026 MVNETA_RXQ_OCCUPIED_ALL_MASK;\ndrivers/net/ethernet/marvell/mvneta.c-882-}\n--\ndrivers/net/ethernet/marvell/mvneta.c=887=static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,\n--\ndrivers/net/ethernet/marvell/mvneta.c-894-\t\tval = rx_done |\ndrivers/net/ethernet/marvell/mvneta.c:895:\t\t  (rx_filled \u003c\u003c MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);\ndrivers/net/ethernet/marvell/mvneta.c:896:\t\tmvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq-\u003eid), val);\ndrivers/net/ethernet/marvell/mvneta.c-897-\t\treturn;\n--\ndrivers/net/ethernet/marvell/mvneta.c-909-\t\tif (rx_filled \u003c= 0xff) {\ndrivers/net/ethernet/marvell/mvneta.c:910:\t\t\tval |= rx_filled \u003c\u003c MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;\ndrivers/net/ethernet/marvell/mvneta.c-911-\t\t\trx_filled = 0;\ndrivers/net/ethernet/marvell/mvneta.c-912-\t\t} else {\ndrivers/net/ethernet/marvell/mvneta.c:913:\t\t\tval |= 0xff \u003c\u003c MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;\ndrivers/net/ethernet/marvell/mvneta.c-914-\t\t\trx_filled -= 0xff;\ndrivers/net/ethernet/marvell/mvneta.c-915-\t\t}\ndrivers/net/ethernet/marvell/mvneta.c:916:\t\tmvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq-\u003eid), val);\ndrivers/net/ethernet/marvell/mvneta.c-917-\t}\n--\ndrivers/net/ethernet/marvell/mvneta.c=922=mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)\n--\ndrivers/net/ethernet/marvell/mvneta.c-925-\ndrivers/net/ethernet/marvell/mvneta.c:926:\trxq-\u003enext_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);\ndrivers/net/ethernet/marvell/mvneta.c-927-\tprefetch(rxq-\u003edescs + rxq-\u003enext_desc_to_proc);\n--\ndrivers/net/ethernet/marvell/mvneta.c=932=static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)\n--\ndrivers/net/ethernet/marvell/mvneta.c-935-\ndrivers/net/ethernet/marvell/mvneta.c:936:\tval =  mvreg_read(pp, MVNETA_GMAC_CTRL_0);\ndrivers/net/ethernet/marvell/mvneta.c:937:\tval \u0026= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;\ndrivers/net/ethernet/marvell/mvneta.c:938:\tval |= ((max_rx_size - MVNETA_MH_SIZE) / 2) \u003c\u003c\ndrivers/net/ethernet/marvell/mvneta.c:939:\t\tMVNETA_GMAC_MAX_RX_SIZE_SHIFT;\ndrivers/net/ethernet/marvell/mvneta.c:940:\tmvreg_write(pp, MVNETA_GMAC_CTRL_0, val);\ndrivers/net/ethernet/marvell/mvneta.c-941-}\n--\ndrivers/net/ethernet/marvell/mvneta.c=945=static void mvneta_rxq_offset_set(struct mvneta_port *pp,\n--\ndrivers/net/ethernet/marvell/mvneta.c-950-\ndrivers/net/ethernet/marvell/mvneta.c:951:\tval = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq-\u003eid));\ndrivers/net/ethernet/marvell/mvneta.c:952:\tval \u0026= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;\ndrivers/net/ethernet/marvell/mvneta.c-953-\ndrivers/net/ethernet/marvell/mvneta.c-954-\t/* Offset is in */\ndrivers/net/ethernet/marvell/mvneta.c:955:\tval |= MVNETA_RXQ_PKT_OFFSET_MASK(offset \u003e\u003e 3);\ndrivers/net/ethernet/marvell/mvneta.c:956:\tmvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq-\u003eid), val);\ndrivers/net/ethernet/marvell/mvneta.c-957-}\n--\n\n"
}

gemini-3.8-flash

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							input: 20422
							output: 39
							thoughts: 39
						

**Investigating the MVNETA Kconfig Definition**

Okay, let's dive into this. My initial thought is to zero in on the `MVNETA` definition within the Kconfig system. I need to understand its configuration options, dependencies, and default settings. A quick check of the Kconfig files is the best first step.

Specifically, I’ll need to examine the `drivers/net/ethernet/marvell/Kconfig` file, likely around line 59. That's where I would expect to find the relevant section for Marvell network adapters, and hopefully the configuration for `MVNETA` itself. Understanding this file is key to understanding how the kernel configures support for this device.

{
  "File": "drivers/net/ethernet/marvell/Kconfig",
  "FirstLine": 40,
  "LineCount": 45
}

{
  "Contents": "  40:\t\t  interface units of the Marvell EBU SoCs (Kirkwood, Orion5x,\n  41:\t\t  Dove, Armada 370 and Armada XP).\n  42:\t\n  43:\t\t  This driver is used by the MV643XX_ETH and MVNETA drivers.\n  44:\t\n  45:\tconfig MVNETA_BM_ENABLE\n  46:\t\ttristate \"Marvell Armada 38x/XP network interface BM support\"\n  47:\t\tdepends on MVNETA\n  48:\t\tdepends on !64BIT\n  49:\t\thelp\n  50:\t\t  This driver supports auxiliary block of the network\n  51:\t\t  interface units in the Marvell ARMADA XP and ARMADA 38x SoC\n  52:\t\t  family, which is called buffer manager.\n  53:\t\n  54:\t\t  This driver, when enabled, strictly cooperates with mvneta\n  55:\t\t  driver and is common for all network ports of the devices,\n  56:\t\t  even for Armada 370 SoC, which doesn't support hardware\n  57:\t\t  buffer management.\n  58:\t\n  59:\tconfig MVNETA\n  60:\t\ttristate \"Marvell Armada 370/38x/XP/37xx network interface support\"\n  61:\t\tdepends on ARCH_MVEBU || COMPILE_TEST\n  62:\t\tselect MVMDIO\n  63:\t\tselect PHYLINK\n  64:\t\tselect PAGE_POOL\n  65:\t\tselect PAGE_POOL_STATS\n  66:\t\thelp\n  67:\t\t  This driver supports the network interface units in the\n  68:\t\t  Marvell ARMADA XP, ARMADA 370, ARMADA 38x and\n  69:\t\t  ARMADA 37xx SoC family.\n  70:\t\n  71:\t\t  Note that this driver is distinct from the mv643xx_eth\n  72:\t\t  driver, which should be used for the older Marvell SoCs\n  73:\t\t  (Dove, Orion, Discovery, Kirkwood).\n  74:\t\n  75:\tconfig MVNETA_BM\n  76:\t\ttristate\n  77:\t\tdepends on !64BIT\n  78:\t\tdefault y if MVNETA=y \u0026\u0026 MVNETA_BM_ENABLE!=n\n  79:\t\tdefault MVNETA_BM_ENABLE\n  80:\t\tselect HWBM\n  81:\t\tselect GENERIC_ALLOCATOR\n  82:\t\thelp\n  83:\t\t  MVNETA_BM must not be 'm' if MVNETA=y, so this symbol ensures\n  84:\t\t  that all dependencies are met.\n"
}

gemini-3.8-flash

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							input: 21328
							output: 45
							thoughts: 112
						

**Analyzing the Network Driver Configuration**

Okay, let's dive into this `config MVNETA` entry. It looks like the network interface support for Marvell's Armada SoCs - specifically the 370, 38x, XP, and 37xx families - is tied to either `ARCH_MVEBU` or `COMPILE_TEST`. Good, a dependency I can check quickly. These are all ARM-based systems, either ARMv7 or ARM64, as I recall. Now, the real question is, what kind of driver is `mvneta`? I need to understand its initialization sequence. I'll need to figure out how it registers itself with the kernel or, more precisely, how the probing is handled. Let's see how it operates. That's the key to understanding how this all hangs together. I need to look at the registration and probe mechanisms.

{
  "Expression": "module_platform_driver|platform_driver_register",
  "PathPrefix": "drivers/net/ethernet/marvell/mvneta.c"
}

{
  "Output": "drivers/net/ethernet/marvell/mvneta.c=5950=static int __init mvneta_driver_init(void)\n--\ndrivers/net/ethernet/marvell/mvneta.c-5966-\ndrivers/net/ethernet/marvell/mvneta.c:5967:\tret = platform_driver_register(\u0026mvneta_driver);\ndrivers/net/ethernet/marvell/mvneta.c-5968-\tif (ret)\n"
}

gemini-3.8-flash

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							input: 21806
							output: 39
							thoughts: 17
						

Here's my thought process, summarized as you requested:

**Diving into the `mvneta` Driver**

Okay, so I need to get a handle on the `mvneta` driver, specifically the code within `mvneta.c`. I'm probably looking for a specific function, data structure, or some critical piece of logic that's giving me trouble, or that I need to understand better for my current task. The name `mvneta` itself suggests it's likely related to Marvell's Ethernet technology, and given my expertise, I probably have a good idea of what I'm expecting to find in this driver. Now, let's open that file and get to work.

{
  "Expression": "mvneta_driver =",
  "PathPrefix": "drivers/net/ethernet/marvell/mvneta.c"
}

{
  "Output": "drivers/net/ethernet/marvell/mvneta.c=5938=MODULE_DEVICE_TABLE(of, mvneta_match);\ndrivers/net/ethernet/marvell/mvneta.c-5939-\ndrivers/net/ethernet/marvell/mvneta.c:5940:static struct platform_driver mvneta_driver = {\ndrivers/net/ethernet/marvell/mvneta.c-5941-\t.probe = mvneta_probe,\n"
}

gemini-3.8-flash

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							input: 22139
							output: 38
							thoughts: 10
						

Okay, here's my interpretation of that thought process, assuming I'm deeply familiar with the relevant technology:

**Analyzing the `mvneta_match` Function**

Alright, time to dive into this. "Let's check `mvneta_match`." That's a clear directive, and the context suggests it's a critical piece of code. This probably refers to a function, module, or perhaps even a script related to some form of network matching or maybe even a data processing routine utilizing Maven and related technologies (hence the `mvn` prefix). My initial thought is to ensure it's functioning as intended, perhaps optimize it, or possibly troubleshoot an issue. Given the brevity, I'm probably looking at a specific aspect or bug report. I’m zeroing in on this piece of code because it's relevant to the current task. Let's see what's what.

{
  "Expression": "mvneta_match",
  "PathPrefix": "drivers/net/ethernet/marvell/mvneta.c"
}

{
  "Output": "drivers/net/ethernet/marvell/mvneta.c=5929=static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);\ndrivers/net/ethernet/marvell/mvneta.c-5930-\ndrivers/net/ethernet/marvell/mvneta.c:5931:static const struct of_device_id mvneta_match[] = {\ndrivers/net/ethernet/marvell/mvneta.c-5932-\t{ .compatible = \"marvell,armada-370-neta\" },\n--\ndrivers/net/ethernet/marvell/mvneta.c-5937-};\ndrivers/net/ethernet/marvell/mvneta.c:5938:MODULE_DEVICE_TABLE(of, mvneta_match);\ndrivers/net/ethernet/marvell/mvneta.c-5939-\ndrivers/net/ethernet/marvell/mvneta.c=5940=static struct platform_driver mvneta_driver = {\n--\ndrivers/net/ethernet/marvell/mvneta.c-5944-\t\t.name = MVNETA_DRIVER_NAME,\ndrivers/net/ethernet/marvell/mvneta.c:5945:\t\t.of_match_table = mvneta_match,\ndrivers/net/ethernet/marvell/mvneta.c-5946-\t\t.pm = \u0026mvneta_pm_ops,\n"
}

gemini-3.8-flash

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null

							input: 22746
							output: 43
							thoughts: 546
						

**My Assessment of the `mvneta_driver` Patch**

Okay, let's break this down. The code change involves the `mvneta_driver`, which is a platform driver that relies on Device Tree entries for matching. Specifically, it uses the `marvell,armada-370-neta` compatible string and others like it. The target architecture is amd64. My initial thought is that this isn't relevant for fuzzing, but I need to be sure.

Let me quickly review Section 2 of the guidelines on when to set `WorthFuzzing` to `false`. It says to do that if the changes fall *exclusively* into certain categories. The key ones here are "Structurally unreachable hardware" and "Unreachable execution paths."

The first red flag is: Can `mvneta` even *probe* on amd64? No, it can't. `mvneta` is for Marvell Armada (MVEBU) SoCs, which are ARM/ARM64. The build configuration (`ARCH_MVEBU`) is not enabled on amd64. Even if `COMPILE_TEST` is set, there's no way a device tree node for `marvell,armada-370-neta` would be present on amd64. I'm thinking here about standard virtualized environments like GCE or QEMU. There's no emulation of Marvell Armada SoCs or `mvneta` in those environments.

Could QEMU emulate that? Even if someone was running a QEMU instance for ARM, my understanding is that the standard syzkaller targets are amd64, based on the prompt. So the assumption is amd64. How would `mvneta` *ever* probe on amd64? It's an OF/platform device, which means it relies on a device tree to instantiate. That's not happening from userspace, and it's certainly not probing on amd64.

Just to be absolutely sure, I should check a function like `mvneta_swbm_rx_frame`, which is in the `drivers/net/ethernet/marvell/mvneta.c` source code. It doesn't seem relevant. The critical factor is that the device matching conditions themselves are invalid for the target architecture. This code modification is definitely not going to be triggered in the target environment.

Therefore, because this code is unreachable on amd64, I can confidently set `WorthFuzzing = false`.

{
  "File": "drivers/net/ethernet/marvell/mvneta.c",
  "FirstLine": 2330,
  "LineCount": 40
}

{
  "Contents": "2330:\t\t\tdata_len += len - ETH_FCS_LEN;\n2331:\t\t}\n2332:\t\t*size = *size - len;\n2333:\t\n2334:\t\tdma_dir = page_pool_get_dma_dir(rxq-\u003epage_pool);\n2335:\t\tdma_sync_single_for_cpu(dev-\u003edev.parent,\n2336:\t\t\t\t\trx_desc-\u003ebuf_phys_addr,\n2337:\t\t\t\t\tlen, dma_dir);\n2338:\t\n2339:\t\trx_desc-\u003ebuf_phys_addr = 0;\n2340:\t\n2341:\t\t/* Prefetch header */\n2342:\t\tprefetch(data);\n2343:\t\txdp_buff_clear_frags_flag(xdp);\n2344:\t\txdp_buff_clear_frag_pfmemalloc(xdp);\n2345:\t\txdp_prepare_buff(xdp, data, pp-\u003erx_offset_correction + MVNETA_MH_SIZE,\n2346:\t\t\t\t data_len, true);\n2347:\t}\n2348:\t\n2349:\tstatic void\n2350:\tmvneta_swbm_add_rx_fragment(struct mvneta_port *pp,\n2351:\t\t\t\t    struct mvneta_rx_desc *rx_desc,\n2352:\t\t\t\t    struct mvneta_rx_queue *rxq,\n2353:\t\t\t\t    struct xdp_buff *xdp, int *size,\n2354:\t\t\t\t    struct page *page)\n2355:\t{\n2356:\t\tstruct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);\n2357:\t\tstruct net_device *dev = pp-\u003edev;\n2358:\t\tenum dma_data_direction dma_dir;\n2359:\t\tint data_len, len;\n2360:\t\n2361:\t\tif (*size \u003e MVNETA_MAX_RX_BUF_SIZE) {\n2362:\t\t\tlen = MVNETA_MAX_RX_BUF_SIZE;\n2363:\t\t\tdata_len = len;\n2364:\t\t} else {\n2365:\t\t\tlen = *size;\n2366:\t\t\tdata_len = len - ETH_FCS_LEN;\n2367:\t\t}\n2368:\t\tdma_dir = page_pool_get_dma_dir(rxq-\u003epage_pool);\n2369:\t\tdma_sync_single_for_cpu(dev-\u003edev.parent,\n"
}

gemini-3.8-flash

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							input: 24550
							output: 43
							thoughts: 50
						

Here's my take on the situation:

**Investigating the Data Flow in mvneta_swbm_rx_frame**

Okay, so I'm knee-deep in this network driver, and I've traced the execution to `mvneta_swbm_rx_frame`. This function, I know, is critical during packet reception, specifically within the NAPI receive polling mechanism, the `mvneta_rx_swbm` function. That's the entry point, the first place the packets are handled. Now, I need to understand the surrounding context of this function. To get a better grasp on the overall flow, my immediate next move is to identify all the call sites of `mvneta_swbm_rx_frame`. I need to figure out *who* is calling it, *when*, and *why*. This is my first step. By going up the call stack, I'll build the initial flow and identify where the packets are coming from before they go into `mvneta_swbm_rx_frame`. This helps me immensely, to see what steps are necessary for packet reception.

{
  "Expression": "mvneta_swbm_rx_frame",
  "PathPrefix": "drivers/net/ethernet/marvell/mvneta.c"
}

{
  "Output": "drivers/net/ethernet/marvell/mvneta.c=2313=static void\ndrivers/net/ethernet/marvell/mvneta.c:2314:mvneta_swbm_rx_frame(struct mvneta_port *pp,\ndrivers/net/ethernet/marvell/mvneta.c-2315-\t\t     struct mvneta_rx_desc *rx_desc,\n--\ndrivers/net/ethernet/marvell/mvneta.c=2428=static int mvneta_rx_swbm(struct napi_struct *napi,\n--\ndrivers/net/ethernet/marvell/mvneta.c-2471-\ndrivers/net/ethernet/marvell/mvneta.c:2472:\t\t\tmvneta_swbm_rx_frame(pp, rx_desc, rxq, \u0026xdp_buf,\ndrivers/net/ethernet/marvell/mvneta.c-2473-\t\t\t\t\t     \u0026size, page);\n"
}

gemini-3.8-flash

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							input: 25124
							output: 163
							thoughts: 1213
						

**Analysis of Patch for Fuzzing Eligibility**

Okay, so I've been given a patch that modifies the `mvneta_swbm_rx_frame` function within the `drivers/net/ethernet/marvell/mvneta.c` file. My task is to determine if this change warrants fuzzing.

My initial thought is that `mvneta_swbm_rx_frame` is called by `mvneta_rx_swbm`, which, as the name suggests, is the NAPI poll function for incoming network packets on the Marvell MVNETA hardware. This immediately sets off some alarms, so I need to verify:

1.  **Architecture Dependency:** First, I check the architecture. The target is amd64, while the `MVNETA` driver depends on either `ARCH_MVEBU` or `COMPILE_TEST`.  `ARCH_MVEBU` is for ARM-based Marvell Armada SoCs. On amd64, `ARCH_MVEBU` is *not* defined. Even if compiled under `COMPILE_TEST`, it still relies on platform-specific Device Tree nodes and SoC memory-mapped registers for Marvell Armada SoCs. This is already a red flag.

2.  **Hardware Reachability:** The `mvneta` driver is a platform driver specifically for certain Marvell Armada SoCs. I see there's no PCI ID, USB ID, or virtual bus associated with it. This means it's tightly bound to the specific hardware. Crucially, standard QEMU or GCE amd64 environments *do not* emulate this Marvell SoC or its ethernet controller. Even if the device *could* be instantiated somehow, `mvneta_swbm_rx_frame` is in the RX data path. It's handling *physical* network packet reception, which requires DMA interrupts from the hardware.  This is a significant hurdle.

Now, I revisit the guidelines carefully, because two negative criteria seem to apply here.

*   **"Structurally unreachable hardware:"** This driver depends on specific Marvell Armada SoCs, and is *not* emulated in standard QEMU/GCE amd64 environments. The hardware simply isn't present in the target fuzzing environment.
*   **"Code paths exclusive to architectures other than the target architecture:"** The driver is primarily designed for ARM architectures (`ARCH_MVEBU`), not amd64. While it *might* be compiled under `COMPILE_TEST`, it relies on hardware that is *not* present.

Therefore, the modified code is both structurally unreachable and associated with an architecture that is not the target. Thus, `WorthFuzzing` should be `false`.

To be absolutely certain, I double-check for any other modified files by looking at the git log. The patch only touches `drivers/net/ethernet/marvell/mvneta.c`, and only modifies one line in `mvneta_swbm_rx_frame`. This confirms my initial assessment.

Regarding `FocusSymbols` and `EnableConfigs`, since `WorthFuzzing` is `false`, empty lists or null values are usually appropriate.  I'll verify the field types to be sure they accept a null value, but it is typically the case.

Finally, I summarize my reasoning. The patch modifies `mvneta_swbm_rx_frame` within the Marvell `mvneta` driver for Armada SoCs. This driver is designed for specific Marvell hardware, which is *not* emulated in standard syzkaller amd64 environments, and relies on an ARM-based architecture that isn't the target. Furthermore, the modified code is in the RX data path, requiring actual hardware packet reception, making it structurally unreachable. Therefore, `WorthFuzzing=false`.

I'm confident in this assessment. I'll proceed to call `set-results`.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies `mvneta_swbm_rx_frame()` in `drivers/net/ethernet/marvell/mvneta.c`, which is a driver for Marvell Armada 370/38x/XP/37xx SoC network interfaces (depends on ARCH_MVEBU or COMPILE_TEST). The driver targets specific ARM-based Marvell SoC hardware via Device Tree and is structurally unreachable on the amd64 target architecture in standard virtualized environments (QEMU/GCE). Furthermore, the modified function is part of the hardware packet reception path. Therefore, this change is not worth fuzzing.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies `mvneta_swbm_rx_frame()` in `drivers/net/ethernet/marvell/mvneta.c`, which is a driver for Marvell Armada 370/38x/XP/37xx SoC network interfaces (depends on ARCH_MVEBU or COMPILE_TEST). The driver targets specific ARM-based Marvell SoC hardware via Device Tree and is structurally unreachable on the amd64 target architecture in standard virtualized environments (QEMU/GCE). Furthermore, the modified function is part of the hardware packet reception path. Therefore, this change is not worth fuzzing.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

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