AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/09/19 04:04	flow	patch-triage	1m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The modified code belongs to the Xilinx AXI Ethernet driver (drivers/net/ethernet/xilinx/xilinx_axienet_main.c), an OF/Device Tree platform driver for Xilinx FPGA/SoC soft IP cores (such as Zynq or MicroBlaze). On the target architecture (amd64), this hardware cannot be probed or initialized in standard QEMU or GCE virtual environments, rendering the code structurally unreachable for fuzzing.", "WorthFuzzing": false }
1/1	2026/09/19 04:04	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit ae03c9c30232143c86fb4d732c69a105e445ba90\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Sat Sep 19 04:04:39 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h\nindex fcd3aaef27fc3..7c75e313dd33a 100644\n--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h\n+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h\n@@ -523,8 +523,9 @@ struct skbuf_dma_descriptor {\n * @stats_work: Work for reading the hardware statistics counters often enough\n * to catch overflows.\n * @dma_err_task: Work structure to process Axi DMA errors\n- * @stopping: Set when @dma_err_task shouldn't do anything because we are\n- * about to stop the device.\n+ * @stopping: Set when we are about to stop the device: makes @dma_err_task\n+ * a no-op (legacy DMA path) and fences RX descriptor\n+ * resubmission in axienet_dma_rx_cb() (dmaengine path).\n * @tx_irq:\tAxidma TX IRQ number\n * @rx_irq:\tAxidma RX IRQ number\n * @eth_irq:\tEthernet core IRQ number\ndiff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c\nindex 782f903d318f3..36a487f791a29 100644\n--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c\n+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c\n@@ -881,6 +881,7 @@ static void axienet_dma_tx_cb(void data, const struct dmaengine_result result)\n \tu64_stats_update_end(\u0026lp-\u003etx_stat_sync);\n \tdma_unmap_sg(lp-\u003edev, skbuf_dma-\u003esgl, skbuf_dma-\u003esg_len, DMA_TO_DEVICE);\n \tdev_consume_skb_any(skbuf_dma-\u003eskb);\n+\tskbuf_dma-\u003eskb = NULL;\n \tnetif_txq_completed_wake(txq, 1, len,\n \t\t\t\t CIRC_SPACE(lp-\u003etx_ring_head, lp-\u003etx_ring_tail, TX_BD_NUM_MAX),\n \t\t\t\t 2);\n@@ -1171,6 +1172,7 @@ static void axienet_dma_rx_cb(void data, const struct dmaengine_result result)\n \t\t\t\t\t\t \u0026meta_max_len);\n \tdma_unmap_single(lp-\u003edev, skbuf_dma-\u003edma_address, lp-\u003emax_frm_size,\n \t\t\t DMA_FROM_DEVICE);\n+\tskbuf_dma-\u003eskb = NULL;\n \n \tif (IS_ERR(app_metadata)) {\n \t\tif (net_ratelimit())\n@@ -1193,6 +1195,12 @@ static void axienet_dma_rx_cb(void data, const struct dmaengine_result result)\n \tu64_stats_update_end(\u0026lp-\u003erx_stat_sync);\n \n rx_submit:\n+\t/* Do not re-arm the RX ring while a stop is in progress, or the\n+\t * teardown could free a buffer still handed to the engine.\n+\t /\n+\tif (READ_ONCE(lp-\u003estopping))\n+\t\treturn;\n+\n \tfor (i = 0; i \u003c CIRC_SPACE(lp-\u003erx_ring_head, lp-\u003erx_ring_tail,\n \t\t\t\t RX_BUF_NUM_DEFAULT); i++)\n \t\taxienet_rx_submit_desc(lp-\u003endev);\n@@ -1541,6 +1549,7 @@ static int axienet_init_dmaengine(struct net_device ndev)\n \tlp-\u003etx_ring_head = 0;\n \tlp-\u003erx_ring_tail = 0;\n \tlp-\u003erx_ring_head = 0;\n+\tlp-\u003estopping = false;\n \tlp-\u003etx_skb_ring = kzalloc_objs(lp-\u003etx_skb_ring, TX_BD_NUM_MAX);\n \tif (!lp-\u003etx_skb_ring) {\n \t\tret = -ENOMEM;\n@@ -1752,20 +1761,43 @@ static int axienet_stop(struct net_device ndev)\n \t\tfree_irq(lp-\u003erx_irq, ndev);\n \t\taxienet_dma_bd_release(ndev);\n \t} else {\n+\t\tstruct skbuf_dma_descriptor skbuf_dma;\n+\n+\t\tWRITE_ONCE(lp-\u003estopping, true);\n \t\tdmaengine_terminate_sync(lp-\u003etx_chan);\n-\t\tdmaengine_synchronize(lp-\u003etx_chan);\n \t\tdmaengine_terminate_sync(lp-\u003erx_chan);\n-\t\tdmaengine_synchronize(lp-\u003erx_chan);\n-\n-\t\tfor (i = 0; i \u003c TX_BD_NUM_MAX; i++)\n-\t\t\tkfree(lp-\u003etx_skb_ring[i]);\n-\t\tkfree(lp-\u003etx_skb_ring);\n-\t\tfor (i = 0; i \u003c RX_BUF_NUM_DEFAULT; i++)\n-\t\t\tkfree(lp-\u003erx_skb_ring[i]);\n-\t\tkfree(lp-\u003erx_skb_ring);\n \n+\t\t/ Release the channels before freeing the rings, so the DMA is\n+\t\t * fully torn down before the memory its descriptors reference is\n+\t\t * freed.\n+\t\t /\n \t\tdma_release_channel(lp-\u003erx_chan);\n \t\tdma_release_channel(lp-\u003etx_chan);\n+\n+\t\t/ Unmap and free any buffer the terminate did not reclaim, so it\n+\t\t * is not leaked; a non-NULL skb marks such a slot.\n+\t\t */\n+\t\tfor (i = 0; i \u003c TX_BD_NUM_MAX; i++) {\n+\t\t\tskbuf_dma = lp-\u003etx_skb_ring[i];\n+\t\t\tif (skbuf_dma \u0026\u0026 skbuf_dma-\u003eskb) {\n+\t\t\t\tdma_unmap_sg(lp-\u003edev, skbuf_dma-\u003esgl,\n+\t\t\t\t\t skbuf_dma-\u003esg_len, DMA_TO_DEVICE);\n+\t\t\t\tdev_kfree_skb_any(skbuf_dma-\u003eskb);\n+\t\t\t}\n+\t\t\tkfree(skbuf_dma);\n+\t\t}\n+\t\tkfree(lp-\u003etx_skb_ring);\n+\n+\t\tfor (i = 0; i \u003c RX_BUF_NUM_DEFAULT; i++) {\n+\t\t\tskbuf_dma = lp-\u003erx_skb_ring[i];\n+\t\t\tif (skbuf_dma \u0026\u0026 skbuf_dma-\u003eskb) {\n+\t\t\t\tdma_unmap_single(lp-\u003edev, skbuf_dma-\u003edma_address,\n+\t\t\t\t\t\t lp-\u003emax_frm_size, DMA_FROM_DEVICE);\n+\t\t\t\tdev_kfree_skb_any(skbuf_dma-\u003eskb);\n+\t\t\t}\n+\t\t\tkfree(skbuf_dma);\n+\t\t}\n+\t\tkfree(lp-\u003erx_skb_ring);\n \t}\n \n \tnetdev_reset_queue(ndev);\n" }
2/1	2026/09/19 04:04	agent	patch-evaluator	1m Model: core Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The modified code belongs to the Xilinx AXI Ethernet driver (drivers/net/ethernet/xilinx/xilinx_axienet_main.c), an OF/Device Tree platform driver for Xilinx FPGA/SoC soft IP cores (such as Zynq or MicroBlaze). On the target architecture (amd64), this hardware cannot be probed or initialized in standard QEMU or GCE virtual environments, rendering the code structurally unreachable for fuzzing.", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer and security engineer. Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on internal assumptions. You must actively use your code access tools to inspect the actual source code, callers, and surrounding context. ================================================================================ 1. CORE TRIAGE PHILOSOPHY ================================================================================ The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs, and newly triggered assertions introduced by the patch series. - REACHABILITY IS THE PRIMARY GATE: Fuzzing can only discover bugs in code that can actually execute in standard virtualized environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap). If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed, regardless of whether it adds assertions or complex logic. - DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS: Patch authors routinely label changes as "cleanups", "refactorings", or state "No functional change intended". Do NOT take these claims at face value. Code refactorings that rearrange logic, introduce helper functions, or alter state management in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs. If reachable executable code is modified or refactored, it MUST be fuzzed. - NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED: When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON, VM_WARN_ON, BUG_ON, lockdep_assert) in reachable code paths, it enforces new or stricter invariants. Even if the author believes the invariant always holds, fuzzing is essential to verify whether an unusual sequence of operations can violate it. ================================================================================ 2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA) ================================================================================ Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories: - Non-kernel and non-executable changes: * Modifications to Documentation/, comments, or spelling fixes. * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/) that do not affect the compiled kernel image (vmlinux) or kernel modules. * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints that do not alter control flow or data structures. * Build system or Kconfig changes that do not alter compiled C logic. - Structurally unreachable hardware: * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU. - Unreachable execution paths: * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during physical PCI hot-unplug or manual sysfs driver unbinding. * Code paths exclusive to architectures other than the target architecture. ================================================================================ 3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA) ================================================================================ Return WorthFuzzing=true whenever the patch touches reachable executable code, including: - Core Subsystems: * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/), BPF, scheduler, core networking, VFS, or syscall handling. - Refactorings and Code Cleanups: * Any restructuring of reachable data structures, helper abstractions, or algorithm flows. - Runtime Assertions and Defensive Checks: * Any introduction or alteration of assertions (WARN_ON, VM_WARN_ON, BUG_ON, etc.) in reachable paths. - Reachable Drivers and Protocols: Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.). ================================================================================ 4. EXTRACTING FocusSymbols (PREVENTING DILUTION) ================================================================================ When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer: - AVOID UBIQUITOUS LIFECYCLE HOT-PATHS: Do NOT list generic, ubiquitous functions called by almost every program in the corpus (including, but not limited to: general memory allocators and deallocators, page fault and trap handlers, or core synchronization primitives; this is not an exhaustive list). Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused", which severely dilutes fuzzing effort away from the actual changes. - TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS: List functions that specifically implement the logic being added or altered, or direct API entrypoints for the subsystem feature under review. - HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h): Compiler-inlined static functions (such as static inlines in mm/.h or include/linux/.h) lack distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters. If the changes are primarily in static inline helpers, identify non-static, feature-specific caller functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers). ================================================================================ 5. IDENTIFYING EnableConfigs ================================================================================ Identify any specific CONFIG_ options required to properly compile and reach the modified code: - Inspect Kconfig files and #ifdef guards; do not make assumptions. - Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed. - Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: Target architecture: amd64 For your convenience, here is the diff of the changes: commit ae03c9c30232143c86fb4d732c69a105e445ba90 Author: syz-cluster <triage@syzkaller.com> Date: Sat Sep 19 04:04:39 2026 +0000 syz-cluster: applied patch under review diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h index fcd3aaef27fc3..7c75e313dd33a 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -523,8 +523,9 @@ struct skbuf_dma_descriptor { * @stats_work: Work for reading the hardware statistics counters often enough * to catch overflows. * @dma_err_task: Work structure to process Axi DMA errors - * @stopping: Set when @dma_err_task shouldn't do anything because we are - * about to stop the device. + * @stopping: Set when we are about to stop the device: makes @dma_err_task + * a no-op (legacy DMA path) and fences RX descriptor + * resubmission in axienet_dma_rx_cb() (dmaengine path). * @tx_irq: Axidma TX IRQ number * @rx_irq: Axidma RX IRQ number * @eth_irq: Ethernet core IRQ number diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index 782f903d318f3..36a487f791a29 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -881,6 +881,7 @@ static void axienet_dma_tx_cb(void data, const struct dmaengine_result result) u64_stats_update_end(&lp->tx_stat_sync); dma_unmap_sg(lp->dev, skbuf_dma->sgl, skbuf_dma->sg_len, DMA_TO_DEVICE); dev_consume_skb_any(skbuf_dma->skb); + skbuf_dma->skb = NULL; netif_txq_completed_wake(txq, 1, len, CIRC_SPACE(lp->tx_ring_head, lp->tx_ring_tail, TX_BD_NUM_MAX), 2); @@ -1171,6 +1172,7 @@ static void axienet_dma_rx_cb(void data, const struct dmaengine_result result) &meta_max_len); dma_unmap_single(lp->dev, skbuf_dma->dma_address, lp->max_frm_size, DMA_FROM_DEVICE); + skbuf_dma->skb = NULL; if (IS_ERR(app_metadata)) { if (net_ratelimit()) @@ -1193,6 +1195,12 @@ static void axienet_dma_rx_cb(void data, const struct dmaengine_result result) u64_stats_update_end(&lp->rx_stat_sync); rx_submit: + /* Do not re-arm the RX ring while a stop is in progress, or the + * teardown could free a buffer still handed to the engine. + / + if (READ_ONCE(lp->stopping)) + return; + for (i = 0; i < CIRC_SPACE(lp->rx_ring_head, lp->rx_ring_tail, RX_BUF_NUM_DEFAULT); i++) axienet_rx_submit_desc(lp->ndev); @@ -1541,6 +1549,7 @@ static int axienet_init_dmaengine(struct net_device ndev) lp->tx_ring_head = 0; lp->rx_ring_tail = 0; lp->rx_ring_head = 0; + lp->stopping = false; lp->tx_skb_ring = kzalloc_objs(lp->tx_skb_ring, TX_BD_NUM_MAX); if (!lp->tx_skb_ring) { ret = -ENOMEM; @@ -1752,20 +1761,43 @@ static int axienet_stop(struct net_device ndev) free_irq(lp->rx_irq, ndev); axienet_dma_bd_release(ndev); } else { + struct skbuf_dma_descriptor skbuf_dma; + + WRITE_ONCE(lp->stopping, true); dmaengine_terminate_sync(lp->tx_chan); - dmaengine_synchronize(lp->tx_chan); dmaengine_terminate_sync(lp->rx_chan); - dmaengine_synchronize(lp->rx_chan); - - for (i = 0; i < TX_BD_NUM_MAX; i++) - kfree(lp->tx_skb_ring[i]); - kfree(lp->tx_skb_ring); - for (i = 0; i < RX_BUF_NUM_DEFAULT; i++) - kfree(lp->rx_skb_ring[i]); - kfree(lp->rx_skb_ring); + / Release the channels before freeing the rings, so the DMA is + * fully torn down before the memory its descriptors reference is + * freed. + / dma_release_channel(lp->rx_chan); dma_release_channel(lp->tx_chan); + + / Unmap and free any buffer the terminate did not reclaim, so it + * is not leaked; a non-NULL skb marks such a slot. + */ + for (i = 0; i < TX_BD_NUM_MAX; i++) { + skbuf_dma = lp->tx_skb_ring[i]; + if (skbuf_dma && skbuf_dma->skb) { + dma_unmap_sg(lp->dev, skbuf_dma->sgl, + skbuf_dma->sg_len, DMA_TO_DEVICE); + dev_kfree_skb_any(skbuf_dma->skb); + } + kfree(skbuf_dma); + } + kfree(lp->tx_skb_ring); + + for (i = 0; i < RX_BUF_NUM_DEFAULT; i++) { + skbuf_dma = lp->rx_skb_ring[i]; + if (skbuf_dma && skbuf_dma->skb) { + dma_unmap_single(lp->dev, skbuf_dma->dma_address, + lp->max_frm_size, DMA_FROM_DEVICE); + dev_kfree_skb_any(skbuf_dma->skb); + } + kfree(skbuf_dma); + } + kfree(lp->rx_skb_ring); } netdev_reset_queue(ndev);
3/2	2026/09/19 04:04	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 4582 output: 36 thoughts: 128 Thoughts: Analyzing a Network Driver Patch Okay, so I've got a patch here that's caught my eye. First things first, let's see exactly what's being modified. It looks like we're dealing with the `xilinx_axienet` driver, specifically header and main C files within the `drivers/net/ethernet/xilinx/` directory. Hmm, `xilinx_axienet`... I need to refresh my memory on this one. What's the core functionality? What kind of bus or platform is it designed for? Time to check the driver definition itself. I'll need to look at its Kconfig entries and relevant dependencies to get a good handle on its architecture. Good, the target here is amd64, so it's a platform I'm familiar with. Now, instead of getting bogged down in line-by-line code reviews just yet, let's leverage `grepper` to quickly pinpoint key configuration options or any relevant relationships within the `drivers/net/ethernet/xilinx/Kconfig` file or related configurations. This should give me a solid high-level overview of the driver's role and any potential impact this patch might have.
4/2	2026/09/19 04:04	tool	grepper	0m Args: { "Expression": "config XILINX", "PathPrefix": "drivers/net/ethernet/xilinx/" } Results: { "Output": "drivers/net/ethernet/xilinx/Kconfig=17=if NET_VENDOR_XILINX\ndrivers/net/ethernet/xilinx/Kconfig-18-\ndrivers/net/ethernet/xilinx/Kconfig:19:config XILINX_EMACLITE\ndrivers/net/ethernet/xilinx/Kconfig-20-\ttristate \"Xilinx 10/100 Ethernet Lite support\"\n--\ndrivers/net/ethernet/xilinx/Kconfig-25-\ndrivers/net/ethernet/xilinx/Kconfig:26:config XILINX_AXI_EMAC\ndrivers/net/ethernet/xilinx/Kconfig-27-\ttristate \"Xilinx 10/100/1000 AXI Ethernet support\"\n--\ndrivers/net/ethernet/xilinx/Kconfig-35-\ndrivers/net/ethernet/xilinx/Kconfig:36:config XILINX_LL_TEMAC\ndrivers/net/ethernet/xilinx/Kconfig-37-\ttristate \"Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver\"\n" }
5/2	2026/09/19 04:04	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 5308 output: 40 thoughts: 35 Thoughts: Okay, here's my interpretation of that thought process, assuming I'm already quite familiar with embedded networking and Linux kernel configuration: Diving into the Xilinx Ethernet Driver Configuration Right, let's get down to brass tacks. I need to understand the dependencies for `XILINX_AXI_EMAC`. A quick look at the Kconfig file in the `drivers/net/ethernet/xilinx/` directory is the most direct way to achieve this. I want to see what other options need to be enabled, what hardware is expected, and perhaps any platform-specific configurations that might be required before I even consider enabling the AXI Ethernet MAC. Knowing the dependencies is crucial for a clean and correct integration, and prevents future headaches. This Kconfig file will be my starting point.
6/2	2026/09/19 04:04	tool	read-file	0m Args: { "File": "drivers/net/ethernet/xilinx/Kconfig", "FirstLine": 15, "LineCount": 40 } Results: { "Contents": " 15:\t\t for your specific card in the following questions.\n 16:\t\n 17:\tif NET_VENDOR_XILINX\n 18:\t\n 19:\tconfig XILINX_EMACLITE\n 20:\t\ttristate \"Xilinx 10/100 Ethernet Lite support\"\n 21:\t\tdepends on HAS_IOMEM\n 22:\t\tselect PHYLIB\n 23:\t\thelp\n 24:\t\t This driver supports the 10/100 Ethernet Lite from Xilinx.\n 25:\t\n 26:\tconfig XILINX_AXI_EMAC\n 27:\t\ttristate \"Xilinx 10/100/1000 AXI Ethernet support\"\n 28:\t\tdepends on HAS_IOMEM\n 29:\t\tdepends on XILINX_DMA\n 30:\t\tselect PHYLINK\n 31:\t\tselect DIMLIB\n 32:\t\thelp\n 33:\t\t This driver supports the 10/100/1000 Ethernet from Xilinx for the\n 34:\t\t AXI bus interface used in Xilinx Virtex FPGAs and Soc's.\n 35:\t\n 36:\tconfig XILINX_LL_TEMAC\n 37:\t\ttristate \"Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver\"\n 38:\t\tdepends on HAS_IOMEM\n 39:\t\tselect PHYLIB\n 40:\t\thelp\n 41:\t\t This driver supports the Xilinx 10/100/1000 LocalLink TEMAC\n 42:\t\t core used in Xilinx Spartan and Virtex FPGAs\n 43:\t\n 44:\tendif # NET_VENDOR_XILINX\n" }
7/2	2026/09/19 04:04	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 6016 output: 51 thoughts: 31 Thoughts: Here's my attempt at summarizing the thought process, tailored for an expert audience: Analyzing the xilinx_axienet Probe Sequence Alright, let's dive into how the `xilinx_axienet` driver is probed. My immediate focus is on its registration method – is it utilizing the platform driver framework, an OF (device tree) based approach, or perhaps something else entirely? I need to quickly identify the mechanism it's using to attach itself to the hardware and initialize. Knowing the probe method will tell me a lot about the expected device tree bindings, resource allocation strategies, and the overall driver architecture. Understanding the probe path is critical to understanding the dependency chain, and I'll need to follow how it handles device discovery, resource acquisition, and any potential deferred probe mechanisms. Any insights into error handling during this process will also be useful.
8/2	2026/09/19 04:04	tool	grepper	0m Args: { "Expression": "module_platform_driver\|platform_driver", "PathPrefix": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c" } Results: { "Output": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c=3248=static DEFINE_SIMPLE_DEV_PM_OPS(axienet_pm_ops,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3250-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3251:static struct platform_driver axienet_driver = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3252-\t.probe = axienet_probe,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3261-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3262:module_platform_driver(axienet_driver);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3263-\n" }
9/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 6552 output: 49 thoughts: 35 Thoughts: Okay, let's dive into this. Here's how I'd approach that driver code: Diving into the Xilinx AXI Ethernet Driver Alright, so the first thing I want to do is get a handle on the probe function and the match tables. I need to understand how the system identifies and initializes this Xilinx AXI Ethernet controller. I'm going to navigate to `drivers/net/ethernet/xilinx/xilinx_axienet_main.c`. That's where the core logic usually resides for this kind of device. Specifically, I'm focusing on those two key elements – the probe routine, which likely handles hardware detection and resource allocation, and the match tables, which define what hardware IDs this driver is responsible for handling. I need to quickly grasp how the driver associates itself with specific AXI Ethernet hardware configurations. Knowing the probe process and the device matching criteria is fundamental to troubleshooting and customization down the line. It tells me the very foundation of how the driver knows it's the right one for the job.
10/2	2026/09/19 04:05	tool	grepper	0m Args: { "Expression": "axienet_of_match", "PathPrefix": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c" } Results: { "Output": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c=66=static void axienet_rx_submit_desc(struct net_device ndev);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-68-/ Match table for of_platform binding */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:69:static const struct of_device_id axienet_of_match[] = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-70-\t{ .compatible = \"xlnx,axi-ethernet-1.00.a\", },\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-75-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:76:MODULE_DEVICE_TABLE(of, axienet_of_match);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-77-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c=3251=static struct platform_driver axienet_driver = {\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3257-\t\t .pm = \u0026axienet_pm_ops,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3258:\t\t .of_match_table = axienet_of_match,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3259-\t},\n" }
11/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 7315 output: 21 thoughts: 87 Thoughts: Analyzing the Device Driver Configuration Okay, hold on a second! My initial understanding is that `axienet_driver` is strictly an OF (Device Tree) based platform driver. This is evident from the fact that its `of_match_table` is explicitly configured for OF matching. My thought process now is to confirm my initial assumption. I need to make sure that there isn't an ACPI or `platform_device_id` fallback, or some other mechanism that could bypass the Device Tree requirement. And I should also confirm my understanding of that build-in `XILINX_DMA`. Therefore, my next step is to quickly search the kernel's Kconfig files for a definition of `XILINX_DMA` to figure out what it represents and if it's relevant to this driver's configuration. This will give me a clear picture of how this driver is integrated and dependent.
12/2	2026/09/19 04:05	tool	grepper	0m Args: { "Expression": "config XILINX_DMA" } Results: { "Output": "drivers/dma/Kconfig=674=config XGENE_DMA\n--\ndrivers/dma/Kconfig-682-\ndrivers/dma/Kconfig:683:config XILINX_DMA\ndrivers/dma/Kconfig-684-\ttristate \"Xilinx AXI DMAS Engine\"\n" }
13/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 7709 output: 35 thoughts: 20 Thoughts: Here's my summary, as if I were thinking these thoughts: Analyzing DMA Configuration Options Okay, time to dive into the DMA configuration. I need to refresh my memory on the current state of things, so I'm going to jump into `drivers/dma/Kconfig`. Specifically, I want to zero in on the relevant section, and I'm pretty sure it's around line 683. Hopefully, that's where I can get a good overview of the key configuration options and dependencies we're working with here. I need to understand the current architecture and get a handle on the DMA settings. Let's get to it.
14/2	2026/09/19 04:05	tool	read-file	0m Args: { "File": "drivers/dma/Kconfig", "FirstLine": 680, "LineCount": 25 } Results: { "Contents": " 680:\t\thelp\n 681:\t\t Enable support for the APM X-Gene SoC DMA engine.\n 682:\t\n 683:\tconfig XILINX_DMA\n 684:\t\ttristate \"Xilinx AXI DMAS Engine\"\n 685:\t\tdepends on HAS_IOMEM\n 686:\t\tselect DMA_ENGINE\n 687:\t\thelp\n 688:\t\t Enable support for Xilinx AXI VDMA Soft IP.\n 689:\t\n 690:\t\t AXI VDMA engine provides high-bandwidth direct memory access\n 691:\t\t between memory and AXI4-Stream video type target\n 692:\t\t peripherals including peripherals which support AXI4-\n 693:\t\t Stream Video Protocol. It has two stream interfaces/\n 694:\t\t channels, Memory Mapped to Stream (MM2S) and Stream to\n 695:\t\t Memory Mapped (S2MM) for the data transfers.\n 696:\t\t AXI CDMA engine provides high-bandwidth direct memory access\n 697:\t\t between a memory-mapped source address and a memory-mapped\n 698:\t\t destination address.\n 699:\t\t AXI DMA engine provides high-bandwidth one dimensional direct\n 700:\t\t memory access between memory and AXI4-Stream target peripherals.\n 701:\t\t AXI MCDMA engine provides high-bandwidth direct memory access\n 702:\t\t between memory and AXI4-Stream target peripherals. It provides\n 703:\t\t the scatter gather interface with multiple channels independent\n 704:\t\t configuration support.\n" }
15/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 8326 output: 51 thoughts: 54 Thoughts: Here's my summary, as if I were thinking it: AXIENET Probe Dive Okay, so I need to quickly refresh my memory on the AXI Ethernet driver. I'm going to jump into the `axienet_probe` function within `drivers/net/ethernet/xilinx/xilinx_axienet_main.c`. The key question I've got right now is how the initialization works, and more specifically, whether I can trigger a probe event without needing a fully defined hardware setup or device tree entry just yet. I'm hoping I can at least get the core logic down and then think about the hardware dependencies later. Let's see if this probe function holds the answers I'm looking for.
16/2	2026/09/19 04:05	tool	read-file	0m Args: { "File": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c", "FirstLine": 2950, "LineCount": 80 } Results: { "Contents": "2950:\t\t\t\tlp-\u003ephy_mode = PHY_INTERFACE_MODE_GMII;\n2951:\t\t\t\tbreak;\n2952:\t\t\tcase XAE_PHY_TYPE_RGMII_2_0:\n2953:\t\t\t\tlp-\u003ephy_mode = PHY_INTERFACE_MODE_RGMII_ID;\n2954:\t\t\t\tbreak;\n2955:\t\t\tcase XAE_PHY_TYPE_SGMII:\n2956:\t\t\t\tlp-\u003ephy_mode = PHY_INTERFACE_MODE_SGMII;\n2957:\t\t\t\tbreak;\n2958:\t\t\tcase XAE_PHY_TYPE_1000BASE_X:\n2959:\t\t\t\tlp-\u003ephy_mode = PHY_INTERFACE_MODE_1000BASEX;\n2960:\t\t\t\tbreak;\n2961:\t\t\tdefault:\n2962:\t\t\t\treturn -EINVAL;\n2963:\t\t\t}\n2964:\t\t} else {\n2965:\t\t\tret = of_get_phy_mode(pdev-\u003edev.of_node, \u0026lp-\u003ephy_mode);\n2966:\t\t\tif (ret)\n2967:\t\t\t\treturn ret;\n2968:\t\t}\n2969:\t\tif (lp-\u003eswitch_x_sgmii \u0026\u0026 lp-\u003ephy_mode != PHY_INTERFACE_MODE_SGMII \u0026\u0026\n2970:\t\t lp-\u003ephy_mode != PHY_INTERFACE_MODE_1000BASEX) {\n2971:\t\t\tdev_err(\u0026pdev-\u003edev, \"xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\\n\");\n2972:\t\t\treturn -EINVAL;\n2973:\t\t}\n2974:\t\n2975:\t\tif (!of_property_present(pdev-\u003edev.of_node, \"dmas\")) {\n2976:\t\t\t/* Find the DMA node, map the DMA registers, and decode the DMA IRQs /\n2977:\t\t\tnp = of_parse_phandle(pdev-\u003edev.of_node, \"axistream-connected\", 0);\n2978:\t\n2979:\t\t\tif (np) {\n2980:\t\t\t\tstruct resource dmares;\n2981:\t\n2982:\t\t\t\tret = of_address_to_resource(np, 0, \u0026dmares);\n2983:\t\t\t\tif (ret) {\n2984:\t\t\t\t\tdev_err(\u0026pdev-\u003edev,\n2985:\t\t\t\t\t\t\"unable to get DMA resource\\n\");\n2986:\t\t\t\t\tof_node_put(np);\n2987:\t\t\t\t\treturn ret;\n2988:\t\t\t\t}\n2989:\t\t\t\tlp-\u003edma_regs = devm_ioremap_resource(\u0026pdev-\u003edev,\n2990:\t\t\t\t\t\t\t\t \u0026dmares);\n2991:\t\t\t\tlp-\u003erx_irq = irq_of_parse_and_map(np, 1);\n2992:\t\t\t\tlp-\u003etx_irq = irq_of_parse_and_map(np, 0);\n2993:\t\t\t\tof_node_put(np);\n2994:\t\t\t\tlp-\u003eeth_irq = platform_get_irq_optional(pdev, 0);\n2995:\t\t\t} else {\n2996:\t\t\t\t/ Check for these resources directly on the Ethernet node. /\n2997:\t\t\t\tlp-\u003edma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);\n2998:\t\t\t\tlp-\u003erx_irq = platform_get_irq(pdev, 1);\n2999:\t\t\t\tlp-\u003etx_irq = platform_get_irq(pdev, 0);\n3000:\t\t\t\tlp-\u003eeth_irq = platform_get_irq_optional(pdev, 2);\n3001:\t\t\t}\n3002:\t\t\tif (IS_ERR(lp-\u003edma_regs)) {\n3003:\t\t\t\tdev_err(\u0026pdev-\u003edev, \"could not map DMA regs\\n\");\n3004:\t\t\t\treturn PTR_ERR(lp-\u003edma_regs);\n3005:\t\t\t}\n3006:\t\t\tif (!lp-\u003erx_irq \|\| !lp-\u003etx_irq) {\n3007:\t\t\t\tdev_err(\u0026pdev-\u003edev, \"could not determine irqs\\n\");\n3008:\t\t\t\treturn -EINVAL;\n3009:\t\t\t}\n3010:\t\t\tif (lp-\u003erx_irq \u003c 0)\n3011:\t\t\t\treturn lp-\u003erx_irq;\n3012:\t\t\tif (lp-\u003etx_irq \u003c 0)\n3013:\t\t\t\treturn lp-\u003etx_irq;\n3014:\t\t\tif (lp-\u003eeth_irq \u003c 0 \u0026\u0026 lp-\u003eeth_irq != -ENXIO)\n3015:\t\t\t\treturn lp-\u003eeth_irq;\n3016:\t\n3017:\t\t\t/ Reset core now that clocks are enabled, prior to accessing MDIO /\n3018:\t\t\tret = __axienet_device_reset(lp);\n3019:\t\t\tif (ret)\n3020:\t\t\t\treturn ret;\n3021:\t\n3022:\t\t\t/ Autodetect the need for 64-bit DMA pointers.\n3023:\t\t\t * When the IP is configured for a bus width bigger than 32 bits,\n3024:\t\t\t * writing the MSB registers is mandatory, even if they are all 0.\n3025:\t\t\t * We can detect this case by writing all 1's to one such register\n3026:\t\t\t * and see if that sticks: when the IP is configured for 32 bits\n3027:\t\t\t * only, those registers are RES0.\n3028:\t\t\t * Those MSB registers were introduced in IP v7.1, which we check first.\n3029:\t\t\t */\n" }
17/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 10066 output: 51 thoughts: 61 Thoughts: Diving into the AXI Ethernet Driver Okay, so I'm digging into this `xilinx_axienet_main.c` file – that's where the heart of the Xilinx AXI Ethernet driver lives, right? My focus right now is on understanding the `axienet_probe` function. I need to get a really good grasp of what happens during the probe process. Let's drill down into lines 2800 through 2950. That should give me a solid chunk of the routine to analyze. I'm expecting to see things like device resource allocation, initialization of the hardware, perhaps some interrupt setup, and the basic configuration that's necessary for the driver to get the AXI Ethernet core up and running. I'll be looking for how the driver interacts with the hardware, how it maps registers, and how it handles the device's specific capabilities. I'm hoping to understand the complete boot path here. Time to get to work!
18/2	2026/09/19 04:05	tool	read-file	0m Args: { "File": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c", "FirstLine": 2850, "LineCount": 80 } Results: { "Contents": "2850:\t\n2851:\t\tlp = netdev_priv(ndev);\n2852:\t\tlp-\u003endev = ndev;\n2853:\t\tlp-\u003edev = \u0026pdev-\u003edev;\n2854:\t\tlp-\u003eoptions = XAE_OPTION_DEFAULTS;\n2855:\t\tlp-\u003erx_bd_num = RX_BD_NUM_DEFAULT;\n2856:\t\tlp-\u003etx_bd_num = TX_BD_NUM_DEFAULT;\n2857:\t\n2858:\t\tu64_stats_init(\u0026lp-\u003erx_stat_sync);\n2859:\t\tu64_stats_init(\u0026lp-\u003etx_stat_sync);\n2860:\t\n2861:\t\tmutex_init(\u0026lp-\u003estats_lock);\n2862:\t\tseqcount_mutex_init(\u0026lp-\u003ehw_stats_seqcount, \u0026lp-\u003estats_lock);\n2863:\t\tINIT_DEFERRABLE_WORK(\u0026lp-\u003estats_work, axienet_refresh_stats);\n2864:\t\n2865:\t\tlp-\u003eaxi_clk = devm_clk_get_optional_enabled(\u0026pdev-\u003edev,\n2866:\t\t\t\t\t\t\t \"s_axi_lite_clk\");\n2867:\t\tif (!lp-\u003eaxi_clk) {\n2868:\t\t\t/* For backward compatibility, if named AXI clock is not present,\n2869:\t\t\t * treat the first clock specified as the AXI clock.\n2870:\t\t\t /\n2871:\t\t\tlp-\u003eaxi_clk = devm_clk_get_optional_enabled(\u0026pdev-\u003edev, NULL);\n2872:\t\t}\n2873:\t\tif (IS_ERR(lp-\u003eaxi_clk))\n2874:\t\t\treturn dev_err_probe(\u0026pdev-\u003edev, PTR_ERR(lp-\u003eaxi_clk),\n2875:\t\t\t\t\t \"could not get AXI clock\\n\");\n2876:\t\n2877:\t\tlp-\u003emisc_clks[0].id = \"axis_clk\";\n2878:\t\tlp-\u003emisc_clks[1].id = \"ref_clk\";\n2879:\t\tlp-\u003emisc_clks[2].id = \"mgt_clk\";\n2880:\t\n2881:\t\tret = devm_clk_bulk_get_optional_enable(\u0026pdev-\u003edev, XAE_NUM_MISC_CLOCKS,\n2882:\t\t\t\t\t\t\tlp-\u003emisc_clks);\n2883:\t\tif (ret)\n2884:\t\t\treturn dev_err_probe(\u0026pdev-\u003edev, ret,\n2885:\t\t\t\t\t \"could not get/enable misc. clocks\\n\");\n2886:\t\n2887:\t\t/ Map device registers /\n2888:\t\tlp-\u003eregs = devm_platform_get_and_ioremap_resource(pdev, 0, \u0026ethres);\n2889:\t\tif (IS_ERR(lp-\u003eregs))\n2890:\t\t\treturn PTR_ERR(lp-\u003eregs);\n2891:\t\tlp-\u003eregs_start = ethres-\u003estart;\n2892:\t\n2893:\t\t/ Setup checksum offload, but default to off if not specified /\n2894:\t\tlp-\u003efeatures = 0;\n2895:\t\n2896:\t\tif (axienet_ior(lp, XAE_ABILITY_OFFSET) \u0026 XAE_ABILITY_STATS)\n2897:\t\t\tlp-\u003efeatures \|= XAE_FEATURE_STATS;\n2898:\t\n2899:\t\tret = of_property_read_u32(pdev-\u003edev.of_node, \"xlnx,txcsum\", \u0026value);\n2900:\t\tif (!ret) {\n2901:\t\t\tswitch (value) {\n2902:\t\t\tcase 1:\n2903:\t\t\t\tlp-\u003efeatures \|= XAE_FEATURE_PARTIAL_TX_CSUM;\n2904:\t\t\t\t/ Can checksum any contiguous range /\n2905:\t\t\t\tndev-\u003efeatures \|= NETIF_F_HW_CSUM;\n2906:\t\t\t\tbreak;\n2907:\t\t\tcase 2:\n2908:\t\t\t\tlp-\u003efeatures \|= XAE_FEATURE_FULL_TX_CSUM;\n2909:\t\t\t\t/ Can checksum TCP/UDP over IPv4. /\n2910:\t\t\t\tndev-\u003efeatures \|= NETIF_F_IP_CSUM;\n2911:\t\t\t\tbreak;\n2912:\t\t\t}\n2913:\t\t}\n2914:\t\tret = of_property_read_u32(pdev-\u003edev.of_node, \"xlnx,rxcsum\", \u0026value);\n2915:\t\tif (!ret) {\n2916:\t\t\tswitch (value) {\n2917:\t\t\tcase 1:\n2918:\t\t\t\tlp-\u003efeatures \|= XAE_FEATURE_PARTIAL_RX_CSUM;\n2919:\t\t\t\tndev-\u003efeatures \|= NETIF_F_RXCSUM;\n2920:\t\t\t\tbreak;\n2921:\t\t\tcase 2:\n2922:\t\t\t\tlp-\u003efeatures \|= XAE_FEATURE_FULL_RX_CSUM;\n2923:\t\t\t\tndev-\u003efeatures \|= NETIF_F_RXCSUM;\n2924:\t\t\t\tbreak;\n2925:\t\t\t}\n2926:\t\t}\n2927:\t\t/ For supporting jumbo frames, the Axi Ethernet hardware must have\n2928:\t\t * a larger Rx/Tx Memory. Typically, the size must be large so that\n2929:\t\t * we can enable jumbo option and start supporting jumbo frames.\n" }
19/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 11798 output: 25 thoughts: 393 Thoughts: My Assessment of axienet_probe and Reachability for Fuzzing Okay, let's break this down. I'm looking at `axienet_probe` and it's immediately clear this is a fairly involved device driver. It needs an OF node, device registers, clocks, DMA channels, and PHY configuration – the usual suspects for a network interface controller. The critical question here, and the core of my current analysis, is whether this driver is even reachable in a standard virtualized environment like GCE or QEMU, specifically on an amd64 architecture. That's the gatekeeper for fuzzing, according to the methodology. Let's see: the target architecture is amd64, so that's fine. But is Xilinx AXI Ethernet emulated in QEMU or GCE on amd64? That's the real crux of it. I know QEMU has Zynq/MicroBlaze machine emulation, but that's for ARM/MicroBlaze targets. I'm on amd64, and the question is whether the Xilinx AXI Ethernet part is accessible. The instructions are clear on reachability. Section 1 and 2 say: code has to execute in these environments, and structurally unreachable code shouldn't be fuzzed. That makes sense; it's a waste of resources otherwise. They give examples of unreachable hardware: vendor-specific PCIe stuff that requires a real ASIC or PCIe card, and that's not emulated. On the flip side, reachable drivers are those accessible via virtual buses like virtio, USB gadget, loopback, etc. That's a good distinction. Now I'm wondering if `xilinx_axienet` could be a PCI device, if it has any PCI glue, or if it's purely a platform driver. That would change the game! So I need to expand the search and look for the driver in the whole tree, and see what the device model is. I need to figure out how it connects to the system, so that I can determine how reachable it really is.
20/2	2026/09/19 04:05	tool	grepper	0m Args: { "Expression": "axienet", "PathPrefix": "drivers/" } Results: { "Output": "\nFull output is too long, showing 500 out of 1727 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/xilinx/Makefile=8=obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o\ndrivers/net/ethernet/xilinx/Makefile:9:xilinx_emac-objs := xilinx_axienet_main.o xilinx_axienet_mdio.o\ndrivers/net/ethernet/xilinx/Makefile-10-obj-$(CONFIG_XILINX_AXI_EMAC) += xilinx_emac.o\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h=462=struct skbuf_dma_descriptor {\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-470-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:471: struct axienet_local - axienet private per device data\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-472- * @ndev:\tPointer for net_device to which it will be attached.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-482- * @mii_clk_div: MII bus clock divider value\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:483: * @regs_start: Resource start for axienet device addresses\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:484: * @regs:\tBase address for the axienet_local device address space\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-485- * @dma_regs:\tBase address for the axidma device address space\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-527- * a no-op (legacy DMA path) and fences RX descriptor\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:528: * resubmission in axienet_dma_rx_cb() (dmaengine path).\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-529- * @tx_irq:\tAxidma TX IRQ number\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-533- * @options:\tAxiEthernet option word\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:534: * @features:\tStores the extended features supported by the axienet hw\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-535- * @max_frm_size: Stores the maximum size of the frame that can be that\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-549- /\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:550:struct axienet_local {\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-551-\tstruct net_device ndev;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-632-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:633: struct axienet_option - Used to set axi ethernet hardware options\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-634- * @opt:\tOption to be set.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-637- /\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:638:struct axienet_option {\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-639-\tu32 opt;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-644-/\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:645: axienet_ior - Memory mapped Axi Ethernet register read\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:646: * @lp: Pointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-647- * @offset: Address offset from the base address of Axi Ethernet core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-652- /\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:653:static inline u32 axienet_ior(struct axienet_local lp, off_t offset)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-654-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-657-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:658:static inline u32 axinet_ior_read_mcr(struct axienet_local lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-659-{\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:660:\treturn axienet_ior(lp, XAE_MDIO_MCR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-661-}\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-662-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:663:static inline void axienet_lock_mii(struct axienet_local lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-664-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-668-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:669:static inline void axienet_unlock_mii(struct axienet_local lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-670-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-675-/\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:676: axienet_iow - Memory mapped Axi Ethernet register write\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:677: * @lp: Pointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-678- * @offset: Address offset from the base address of Axi Ethernet core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-683- /\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:684:static inline void axienet_iow(struct axienet_local lp, off_t offset,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-685-\t\t\t u32 value)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-690-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:691: axienet_dma_out32 - Memory mapped Axi DMA register write.\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:692: * @lp:\t\tPointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-693- * @reg:\tAddress offset from the base address of the Axi DMA core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-699-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:700:static inline void axienet_dma_out32(struct axienet_local lp,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-701-\t\t\t\t off_t reg, u32 value)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-707-/\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:708: axienet_dma_out64 - Memory mapped Axi DMA register write.\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:709: * @lp:\t\tPointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-710- * @reg:\tAddress offset from the base address of the Axi DMA core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-715- /\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:716:static inline void axienet_dma_out64(struct axienet_local lp,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-717-\t\t\t\t off_t reg, u64 value)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-721-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:722:static inline void axienet_dma_out_addr(struct axienet_local lp, off_t reg,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-723-\t\t\t\t\tdma_addr_t addr)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-725-\tif (lp-\u003efeatures \u0026 XAE_FEATURE_DMA_64BIT)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:726:\t\taxienet_dma_out64(lp, reg, addr);\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-727-\telse\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:728:\t\taxienet_dma_out32(lp, reg, lower_32_bits(addr));\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-729-}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-732-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:733:static inline void axienet_dma_out_addr(struct axienet_local lp, off_t reg,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-734-\t\t\t\t\tdma_addr_t addr)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-735-{\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:736:\taxienet_dma_out32(lp, reg, lower_32_bits(addr));\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-737-}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-740-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:741:/* Function prototypes visible in xilinx_axienet_mdio.c for other files /\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:742:int axienet_mdio_setup(struct axienet_local lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:743:void axienet_mdio_teardown(struct axienet_local lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-744-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-46-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:47:#include \"xilinx_axienet.h\"\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-48-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-59-/ Must be shorter than length of ethtool_drvinfo.driver field to fit /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:60:#define DRIVER_NAME\t\t\"xaxienet\"\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-61-#define DRIVER_DESCRIPTION\t\"Xilinx Axi Ethernet driver\"\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-65-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:66:static void axienet_rx_submit_desc(struct net_device ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-67-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-68-/* Match table for of_platform binding /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:69:static const struct of_device_id axienet_of_match[] = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-70-\t{ .compatible = \"xlnx,axi-ethernet-1.00.a\", },\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-75-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:76:MODULE_DEVICE_TABLE(of, axienet_of_match);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-77-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-78-/ Option table for setting up Axi Ethernet hardware options /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:79:static struct axienet_option axienet_options[] = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-80-\t/ Turn on jumbo packet support for both Rx and Tx /\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-132-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:133:static struct skbuf_dma_descriptor axienet_get_rx_desc(struct axienet_local lp, int i)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-134-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-137-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:138:static struct skbuf_dma_descriptor axienet_get_tx_desc(struct axienet_local lp, int i)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-139-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-143-/\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:144: axienet_dma_in32 - Memory mapped Axi DMA register read\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:145: * @lp:\t\tPointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-146- * @reg:\tAddress offset from the base address of the Axi DMA core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-151- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:152:static inline u32 axienet_dma_in32(struct axienet_local lp, off_t reg)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-153-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-156-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:157:static void desc_set_phys_addr(struct axienet_local lp, dma_addr_t addr,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-158-\t\t\t struct axidma_bd desc)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-164-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:165:static dma_addr_t desc_get_phys_addr(struct axienet_local lp,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-166-\t\t\t\t struct axidma_bd desc)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-176-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:177: axienet_dma_bd_release - Release buffer descriptor rings\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-178- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-180- * This function is used to release the descriptors allocated in\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:181: * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-182- * driver stop api is called.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-183- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:184:static void axienet_dma_bd_release(struct net_device ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-185-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-186-\tint i;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:187:\tstruct axienet_local lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-188-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-225-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:226:static u64 axienet_dma_rate(struct axienet_local lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-227-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-233-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:234: axienet_calc_cr() - Calculate control register value\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-235- * @lp: Device private data\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-243- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:244:static u32 axienet_calc_cr(struct axienet_local lp, u32 count, u32 usec)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-245-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-253-\tif (count \u003e 1) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:254:\t\tu64 clk_rate = axienet_dma_rate(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-255-\t\tu32 timer;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-269-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:270: axienet_coalesce_params() - Extract coalesce parameters from the CR\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-271- * @lp: Device private data\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-275- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:276:static void axienet_coalesce_params(struct axienet_local lp, u32 cr,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-277-\t\t\t\t u32 count, u32 usec)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-278-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:279:\tu64 clk_rate = axienet_dma_rate(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-280-\tu64 timer = FIELD_GET(XAXIDMA_DELAY_MASK, cr);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-286-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:287: axienet_dma_start - Set up DMA registers and start DMA operation\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:288: * @lp:\t\tPointer to the axienet_local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-289- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:290:static void axienet_dma_start(struct axienet_local lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-291-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-295-\tlp-\u003erx_dma_cr \u0026= ~XAXIDMA_CR_RUNSTOP_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:296:\taxienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp-\u003erx_dma_cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-297-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-300-\t /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:301:\taxienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp-\u003erx_bd_p);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-302-\tlp-\u003erx_dma_cr \|= XAXIDMA_CR_RUNSTOP_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:303:\taxienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp-\u003erx_dma_cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:304:\taxienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp-\u003erx_bd_p +\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-305-\t\t\t (sizeof(lp-\u003erx_bd_v) * (lp-\u003erx_bd_num - 1)));\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-312-\tlp-\u003etx_dma_cr \u0026= ~XAXIDMA_CR_RUNSTOP_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:313:\taxienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp-\u003etx_dma_cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-314-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-318-\t /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:319:\taxienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp-\u003etx_bd_p);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-320-\tlp-\u003etx_dma_cr \|= XAXIDMA_CR_RUNSTOP_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:321:\taxienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp-\u003etx_dma_cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-322-\tlp-\u003etx_dma_started = true;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-327-/\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:328: axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-329- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-336- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:337:static int axienet_dma_bd_init(struct net_device ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-338-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-340-\tstruct sk_buff skb;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:341:\tstruct axienet_local lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-342-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-395-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:396:\taxienet_dma_start(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-397-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-399-out:\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:400:\taxienet_dma_bd_release(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-401-\treturn -ENOMEM;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-404-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:405: axienet_set_mac_address - Write the MAC address\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-406- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-411- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:412:static void axienet_set_mac_address(struct net_device ndev,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-413-\t\t\t\t const void address)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-414-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:415:\tstruct axienet_local lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-416-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-422-\t/* Set up unicast MAC address filter set its mac address /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:423:\taxienet_iow(lp, XAE_UAW0_OFFSET,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-424-\t\t (ndev-\u003edev_addr[0]) \|\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-427-\t\t (ndev-\u003edev_addr[3] \u003c\u003c 24));\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:428:\taxienet_iow(lp, XAE_UAW1_OFFSET,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:429:\t\t (((axienet_ior(lp, XAE_UAW1_OFFSET)) \u0026\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-430-\t\t ~XAE_UAW1_UNICASTADDR_MASK) \|\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-442- This function is called to initialize the MAC address of the Axi Ethernet\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:443: * core. It calls the core specific axienet_set_mac_address. This is the\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-444- * function that goes into net_device_ops structure entry ndo_set_mac_address.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c=446=static int netdev_set_mac_address(struct net_device ndev, void p)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-449-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:450:\taxienet_set_mac_address(ndev, addr-\u003esa_data);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-451-\treturn 0;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-454-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:455: axienet_set_multicast_list - Prepare the multicast table\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-456- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-464- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:465:static void axienet_set_multicast_list(struct net_device ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-466-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-468-\tu32 reg, af0reg, af1reg;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:469:\tstruct axienet_local lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-470-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:471:\treg = axienet_ior(lp, XAE_FMI_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-472-\treg \u0026= ~XAE_FMI_PM_MASK;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-476-\t\treg \u0026= ~XAE_FMI_PM_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:477:\taxienet_iow(lp, XAE_FMI_OFFSET, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-478-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-481-\t\treg \u0026= 0xFFFFFF00;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:482:\t\taxienet_iow(lp, XAE_FMI_OFFSET, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:483:\t\taxienet_iow(lp, XAE_AF0_OFFSET, 1); / Multicast bit /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:484:\t\taxienet_iow(lp, XAE_AF1_OFFSET, 0);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:485:\t\taxienet_iow(lp, XAE_AM0_OFFSET, 1); / ditto /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:486:\t\taxienet_iow(lp, XAE_AM1_OFFSET, 0);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:487:\t\taxienet_iow(lp, XAE_FFE_OFFSET, 1);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-488-\t\ti = 1;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-506-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:507:\t\t\taxienet_iow(lp, XAE_FMI_OFFSET, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:508:\t\t\taxienet_iow(lp, XAE_AF0_OFFSET, af0reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:509:\t\t\taxienet_iow(lp, XAE_AF1_OFFSET, af1reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:510:\t\t\taxienet_iow(lp, XAE_AM0_OFFSET, 0xffffffff);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:511:\t\t\taxienet_iow(lp, XAE_AM1_OFFSET, 0x0000ffff);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:512:\t\t\taxienet_iow(lp, XAE_FFE_OFFSET, 1);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-513-\t\t\ti++;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-519-\t\treg \|= i;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:520:\t\taxienet_iow(lp, XAE_FMI_OFFSET, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:521:\t\taxienet_iow(lp, XAE_FFE_OFFSET, 0);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-522-\t}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-525-/\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:526: axienet_setoptions - Set an Axi Ethernet option\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-527- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-533- * these options in the Axi Ethernet hardware. This is done through\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:534: * axienet_option structure .\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-535- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:536:static void axienet_setoptions(struct net_device ndev, u32 options)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-537-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-538-\tint reg;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:539:\tstruct axienet_local lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:540:\tstruct axienet_option tp = \u0026axienet_options[0];\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-541-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-542-\twhile (tp-\u003eopt) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:543:\t\treg = ((axienet_ior(lp, tp-\u003ereg)) \u0026 ~(tp-\u003em_or));\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-544-\t\tif (options \u0026 tp-\u003eopt)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-545-\t\t\treg \|= tp-\u003em_or;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:546:\t\taxienet_iow(lp, tp-\u003ereg, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-547-\t\ttp++;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-552-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:553:static u64 axienet_stat(struct axienet_local lp, enum temac_stat stat)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-554-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-559-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:560:\tcounter = axienet_ior(lp, XAE_STATS_OFFSET + stat 8);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-561-\treturn lp-\u003ehw_stat_base[stat] + (counter - lp-\u003ehw_last_counter[stat]);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-563-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:564:static void axienet_stats_update(struct axienet_local lp, bool reset)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-565-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-570-\tfor (stat = 0; stat \u003c STAT_COUNT; stat++) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:571:\t\tu32 counter = axienet_ior(lp, XAE_STATS_OFFSET + stat 8);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-572-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-578-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:579:static void axienet_refresh_stats(struct work_struct work)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-580-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:581:\tstruct axienet_local lp = container_of(work, struct axienet_local,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-582-\t\t\t\t\t\tstats_work.work);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-584-\tmutex_lock(\u0026lp-\u003estats_lock);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:585:\taxienet_stats_update(lp, false);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-586-\tmutex_unlock(\u0026lp-\u003estats_lock);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-591-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:592:static int __axienet_device_reset(struct axienet_local lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-593-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-599-\tif (lp-\u003efeatures \u0026 XAE_FEATURE_STATS)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:600:\t\taxienet_stats_update(lp, true);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-601-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-608-\t /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:609:\taxienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:610:\tret = read_poll_timeout(axienet_dma_in32, value,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-611-\t\t\t\t!(value \u0026 XAXIDMA_CR_RESET_MASK),\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-619-\t/* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:620:\tret = read_poll_timeout(axienet_ior, value,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-621-\t\t\t\tvalue \u0026 XAE_INT_PHYRSTCMPLT_MASK,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-636-\t\t\tu32 counter =\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:637:\t\t\t\taxienet_ior(lp, XAE_STATS_OFFSET + stat 8);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-638-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-651-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:652: axienet_dma_stop - Stop DMA operation\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:653: * @lp:\t\tPointer to the axienet_local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-654- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:655:static void axienet_dma_stop(struct axienet_local lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-656-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-662-\tcr = lp-\u003erx_dma_cr \u0026 ~(XAXIDMA_CR_RUNSTOP_MASK \| XAXIDMA_IRQ_ALL_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:663:\taxienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-664-\tlp-\u003erx_dma_started = false;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-671-\tcr = lp-\u003etx_dma_cr \u0026 ~(XAXIDMA_CR_RUNSTOP_MASK \| XAXIDMA_IRQ_ALL_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:672:\taxienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-673-\tlp-\u003etx_dma_started = false;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-678-\t/* Give DMAs a chance to halt gracefully /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:679:\tsr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-680-\tfor (count = 0; !(sr \u0026 XAXIDMA_SR_HALT_MASK) \u0026\u0026 count \u003c 5; ++count) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-681-\t\tmsleep(20);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:682:\t\tsr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-683-\t}\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-684-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:685:\tsr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-686-\tfor (count = 0; !(sr \u0026 XAXIDMA_SR_HALT_MASK) \u0026\u0026 count \u003c 5; ++count) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-687-\t\tmsleep(20);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:688:\t\tsr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-689-\t}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-691-\t/ Do a reset to ensure DMA is really stopped /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:692:\taxienet_lock_mii(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:693:\t__axienet_device_reset(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:694:\taxienet_unlock_mii(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-695-}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-697-/\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:698: axienet_device_reset - Reset and initialize the Axi Ethernet hardware.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-699- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-709- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:710:static int axienet_device_reset(struct net_device ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-711-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:712:\tu32 axienet_status;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:713:\tstruct axienet_local lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-714-\tint ret;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-728-\tif (!lp-\u003euse_dmaengine) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:729:\t\tret = __axienet_device_reset(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-730-\t\tif (ret)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-732-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:733:\t\tret = axienet_dma_bd_init(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-734-\t\tif (ret) {\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-740-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:741:\taxienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:742:\taxienet_status \u0026= ~XAE_RCW1_RX_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:743:\taxienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-744-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:745:\taxienet_status = axienet_ior(lp, XAE_IP_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:746:\tif (axienet_status \u0026 XAE_INT_RXRJECT_MASK)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:747:\t\taxienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:748:\taxienet_iow(lp, XAE_IE_OFFSET, lp-\u003eeth_irq \u003e 0 ?\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-749-\t\t XAE_INT_RECV_ERROR_MASK : 0);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-750-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:751:\taxienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-752-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-755-\t /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:756:\taxienet_setoptions(ndev, lp-\u003eoptions \u0026\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-757-\t\t\t ~(XAE_OPTION_TXEN \| XAE_OPTION_RXEN));\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:758:\taxienet_set_mac_address(ndev, NULL);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:759:\taxienet_set_multicast_list(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:760:\taxienet_setoptions(ndev, lp-\u003eoptions);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-761-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-767-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:768: axienet_free_tx_chain - Clean up a series of linked TX descriptors.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:769: * @lp:\t\tPointer to the axienet_local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-770- * @first_bd:\tIndex of first descriptor to clean up\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-781- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:782:static int axienet_free_tx_chain(struct axienet_local lp, u32 first_bd,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-783-\t\t\t\t int nr_bds, bool force, u32 sizep, int budget)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-834-/\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:835: axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:836: * @lp:\t\tPointer to the axienet_local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-837- * @num_frag:\tThe number of BDs to check for\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-846- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:847:static inline int axienet_check_tx_bd_space(struct axienet_local lp,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-848-\t\t\t\t\t int num_frag)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-861-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:862: axienet_dma_tx_cb - DMA engine callback for TX channel.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:863: * @data: Pointer to the axienet_local structure.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-864- * @result: error reporting through dmaengine_result.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-867- /\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:868:static void axienet_dma_tx_cb(void data, const struct dmaengine_result result)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-869-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-870-\tstruct skbuf_dma_descriptor skbuf_dma;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:871:\tstruct axienet_local lp = data;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-872-\tstruct netdev_queue txq;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-874-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:875:\tskbuf_dma = axienet_get_tx_desc(lp, lp-\u003etx_ring_tail++);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-876-\tlen = skbuf_dma-\u003eskb-\u003elen;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-890-/*\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:891: axienet_start_xmit_dmaengine - Starts the transmission.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-892- * @skb: sk_buff pointer that contains data to be Txed.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c=905=static netdev_tx_t\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:906:axienet_start_xmit_dmaengine(struct sk_buff skb, struct net_device ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-907-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-908-\tstruct dma_async_tx_descriptor dma_tx_desc = NULL;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:909:\tstruct axienet_local lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-910-\tu32 app_metadata[DMA_NUM_APP_WORDS] = {0};\n\n" }
21/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 28951 output: 19 thoughts: 88 Thoughts: Here's my thought process, as if I were analyzing that code: Diving into the AXI Ethernet Driver Okay, hold on a second. I'm looking at the `xilinx_axienet_main.c` file and specifically focusing on the driver. My initial question is: Is this driver solely initialized through Device Tree? The code seems to suggest that the `of_device_id axienet_of_match` is the only way this thing gets probed. I need to confirm this. I'm not just going to take this at face value. I've seen drivers that use multiple probe methods. It could be DT, platform data, or even a module parameter. Let's see if there are any other references to the `axienet_driver` structure or any other probe functions. Time to break out the grepper! Let's see what the broader picture is. I'll search the code base for `axienet_driver` and see what comes up. That should give me a better understanding of how the driver is being used.
22/2	2026/09/19 04:05	tool	grepper	0m Args: { "Expression": "axienet_driver" } Results: { "Output": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c=3248=static DEFINE_SIMPLE_DEV_PM_OPS(axienet_pm_ops,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3250-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3251:static struct platform_driver axienet_driver = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3252-\t.probe = axienet_probe,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3261-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3262:module_platform_driver(axienet_driver);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3263-\n" }
23/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 29567 output: 27 thoughts: 258 Thoughts: My Initial Assessment of the `axienet_driver` and its Potential Compatibility Okay, let's take a look at this `axienet_driver` structure here: ```c static struct platform_driver axienet_driver = { .probe = axienet_probe, .remove_new = axienet_remove, .driver = { .name = DRIVER_NAME, .pm = &axienet_pm_ops, .of_match_table = axienet_of_match, }, }; module_platform_driver(axienet_driver); ``` Right away, I see the use of an OF (Device Tree) match table, `axienet_of_match`. That's the key. Now, the question that immediately pops into my head, given the context, is: can this type of device driver, one designed to work with an OF device tree, actually be instantiated on an amd64 system, particularly in an environment like QEMU when running a test generated by syzkaller? That's the real problem, isn't it? The real question becomes: Does syzkaller or QEMU's x86_64 setup even support Device Tree? Does x86 use ACPI instead? My concern is that these environments might lean towards ACPI for platform device description on x86-64, making this Device Tree driver essentially useless. I need to quickly figure out if Device Tree is even an option for platform devices on x86, particularly amd64. So I'm going to look at the kernel configuration. I need to know if `CONFIG_OF` is enabled, and if so, whether it's actually usable for platform devices. Let's check `CONFIG_OF` settings, specifically for x86. I need to determine if Device Tree is actually a thing on x86 at all. I will grep for `OF` within the `arch/x86/Kconfig` files. That should give me the answer.
24/2	2026/09/19 04:05	tool	grepper	0m Args: { "Expression": "select OF", "PathPrefix": "arch/x86" } Results: { "Output": "arch/x86/Kconfig=669=config X86_INTEL_CE\n--\narch/x86/Kconfig-676-\tselect X86_REBOOTFIXUPS\narch/x86/Kconfig:677:\tselect OF\narch/x86/Kconfig:678:\tselect OF_EARLY_FLATTREE\narch/x86/Kconfig-679-\thelp\n--\narch/x86/Kconfig=1509=config NUMA\n--\narch/x86/Kconfig-1513-\tselect USE_PERCPU_NUMA_NODE_ID\narch/x86/Kconfig:1514:\tselect OF_NUMA if OF\narch/x86/Kconfig-1515-\thelp\n--\narch/x86/Kconfig=2979=config OLPC\n--\narch/x86/Kconfig-2983-\tselect GPIOLIB_LEGACY\narch/x86/Kconfig:2984:\tselect OF\narch/x86/Kconfig:2985:\tselect OF_PROMTREE\narch/x86/Kconfig-2986-\tselect IRQ_DOMAIN\n" }
25/2	2026/09/19 04:05	llm	patch-evaluator	0m Model: gemini-3.8-flash Args: null Results: null Tokens: input: 30624 output: 133 thoughts: 2749 Thoughts: Analysis of Xilinx AXI Ethernet Driver Reachability on amd64 Okay, here's the breakdown. I'm looking at this `xilinx_axienet` driver and my immediate thought is, this is going to be a problem on `amd64`. Looking at the Kconfig, it's clear `OF` (Device Tree) is used for it, but not by default on standard amd64. Even if OF were somehow enabled, syzkaller doesn't do device tree injection, so that's out. Could it be bound via `sysfs bind`? Probably not. The `axienet_driver` uses `.probe = axienet_probe`. Let's assume a platform device named "xaxienet" somehow gets created. The driver has a `.driver = { .name = DRIVER_NAME, .of_match_table = axienet_of_match }`, but no `id_table`, so it is clearly reliant on device tree binding. Now, looking at `axienet_probe`, it needs I/O memory resource 0. User space creation won't provide this, and it must have `pdev->dev.of_node`. Crucially, it uses `of_property_read_u32` and `of_get_phy_mode` which will immediately fail with `-ENODEV` if `pdev->dev.of_node` is `NULL`. Alright, let's see if QEMU even emulates this. QEMU has `xilinx_ethlite` and `xilinx_axienet`, but they're for MicroBlaze and Zynq (ARM). QEMU `x86_64` targets PC machine types like i440fx, q35, and microvm, none of which have Xilinx AXI Ethernet. This is an FPGA IP block connected via AXI bus on Xilinx platforms, completely unreachable on an x86_64 PC, because it's not a standard device. We would need a special PCIe FPGA card with a custom bridge. Now, let's check the prompt guidelines. The key points are "Structurally unreachable hardware: Vendor-specific... drivers requiring physical ASIC/PCIe cards not emulated in standard QEMU" and "Code paths exclusive to architectures other than the target architecture." Bingo. We are specifically on amd64, and the code clearly relies on hardware (AXI bus, Xilinx DMA) and device tree configurations not present on amd64. Can `XILINX_AXI_EMAC` even be compiled? Yes, `HAS_IOMEM` is true on amd64, so it can be enabled. But can the driver run? No. No Xilinx AXI Ethernet or device tree on any standard QEMU x86_64 machines. ACPI, not Device Tree, boots amd64. The `axienet_probe` fails immediately. Those callbacks in the patch (`axienet_stop`, `axienet_dma_tx_cb`, `axienet_dma_rx_cb`, `axienet_init_dmaengine`) will never run. The patch itself modifies network device operations. But `axienet_stop` is only called when stopping an existing `xilinx_axienet` net_device. The DMA callbacks are for the Xilinx AXI DMA engine. This falls squarely under the "structurally unreachable hardware" and "code paths exclusive to architectures other than the target architecture" categories. The conclusion is, this is not worth fuzzing. The code will never execute in a standard environment. Therefore, `WorthFuzzing=false`. `EnableConfigs` and `FocusSymbols` are empty. The reasoning is: "The modified code is in the Xilinx AXI Ethernet driver which is an OF/Device Tree-based platform driver for Xilinx FPGA/SoC hardware (e.g., Zynq/MicroBlaze). It requires physical hardware or architecture-specific emulation not available in standard virtualized amd64 QEMU/GCE environments, making the driver structurally unreachable on amd64." There's no other driver in the codebase that can call this one.
26/2	2026/09/19 04:05	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The modified code belongs to the Xilinx AXI Ethernet driver (drivers/net/ethernet/xilinx/xilinx_axienet_main.c), an OF/Device Tree platform driver for Xilinx FPGA/SoC soft IP cores (such as Zynq or MicroBlaze). On the target architecture (amd64), this hardware cannot be probed or initialized in standard QEMU or GCE virtual environments, rendering the code structurally unreachable for fuzzing.", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The modified code belongs to the Xilinx AXI Ethernet driver (drivers/net/ethernet/xilinx/xilinx_axienet_main.c), an OF/Device Tree platform driver for Xilinx FPGA/SoC soft IP cores (such as Zynq or MicroBlaze). On the target architecture (amd64), this hardware cannot be probed or initialized in standard QEMU or GCE virtual environments, rendering the code structurally unreachable for fuzzing.", "WorthFuzzing": false }
27/1	2026/09/19 04:05	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The modified code belongs to the Xilinx AXI Ethernet driver (drivers/net/ethernet/xilinx/xilinx_axienet_main.c), an OF/Device Tree platform driver for Xilinx FPGA/SoC soft IP cores (such as Zynq or MicroBlaze). On the target architecture (amd64), this hardware cannot be probed or initialized in standard QEMU or GCE virtual environments, rendering the code structurally unreachable for fuzzing.",
  "WorthFuzzing": false
}

{
  "PatchDiff": "commit ae03c9c30232143c86fb4d732c69a105e445ba90\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Sat Sep 19 04:04:39 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h\nindex fcd3aaef27fc3..7c75e313dd33a 100644\n--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h\n+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h\n@@ -523,8 +523,9 @@ struct skbuf_dma_descriptor {\n  * @stats_work: Work for reading the hardware statistics counters often enough\n  *              to catch overflows.\n  * @dma_err_task: Work structure to process Axi DMA errors\n- * @stopping:   Set when @dma_err_task shouldn't do anything because we are\n- *              about to stop the device.\n+ * @stopping:   Set when we are about to stop the device: makes @dma_err_task\n+ *              a no-op (legacy DMA path) and fences RX descriptor\n+ *              resubmission in axienet_dma_rx_cb() (dmaengine path).\n  * @tx_irq:\tAxidma TX IRQ number\n  * @rx_irq:\tAxidma RX IRQ number\n  * @eth_irq:\tEthernet core IRQ number\ndiff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c\nindex 782f903d318f3..36a487f791a29 100644\n--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c\n+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c\n@@ -881,6 +881,7 @@ static void axienet_dma_tx_cb(void *data, const struct dmaengine_result *result)\n \tu64_stats_update_end(\u0026lp-\u003etx_stat_sync);\n \tdma_unmap_sg(lp-\u003edev, skbuf_dma-\u003esgl, skbuf_dma-\u003esg_len, DMA_TO_DEVICE);\n \tdev_consume_skb_any(skbuf_dma-\u003eskb);\n+\tskbuf_dma-\u003eskb = NULL;\n \tnetif_txq_completed_wake(txq, 1, len,\n \t\t\t\t CIRC_SPACE(lp-\u003etx_ring_head, lp-\u003etx_ring_tail, TX_BD_NUM_MAX),\n \t\t\t\t 2);\n@@ -1171,6 +1172,7 @@ static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *result)\n \t\t\t\t\t\t       \u0026meta_max_len);\n \tdma_unmap_single(lp-\u003edev, skbuf_dma-\u003edma_address, lp-\u003emax_frm_size,\n \t\t\t DMA_FROM_DEVICE);\n+\tskbuf_dma-\u003eskb = NULL;\n \n \tif (IS_ERR(app_metadata)) {\n \t\tif (net_ratelimit())\n@@ -1193,6 +1195,12 @@ static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *result)\n \tu64_stats_update_end(\u0026lp-\u003erx_stat_sync);\n \n rx_submit:\n+\t/* Do not re-arm the RX ring while a stop is in progress, or the\n+\t * teardown could free a buffer still handed to the engine.\n+\t */\n+\tif (READ_ONCE(lp-\u003estopping))\n+\t\treturn;\n+\n \tfor (i = 0; i \u003c CIRC_SPACE(lp-\u003erx_ring_head, lp-\u003erx_ring_tail,\n \t\t\t\t   RX_BUF_NUM_DEFAULT); i++)\n \t\taxienet_rx_submit_desc(lp-\u003endev);\n@@ -1541,6 +1549,7 @@ static int axienet_init_dmaengine(struct net_device *ndev)\n \tlp-\u003etx_ring_head = 0;\n \tlp-\u003erx_ring_tail = 0;\n \tlp-\u003erx_ring_head = 0;\n+\tlp-\u003estopping = false;\n \tlp-\u003etx_skb_ring = kzalloc_objs(*lp-\u003etx_skb_ring, TX_BD_NUM_MAX);\n \tif (!lp-\u003etx_skb_ring) {\n \t\tret = -ENOMEM;\n@@ -1752,20 +1761,43 @@ static int axienet_stop(struct net_device *ndev)\n \t\tfree_irq(lp-\u003erx_irq, ndev);\n \t\taxienet_dma_bd_release(ndev);\n \t} else {\n+\t\tstruct skbuf_dma_descriptor *skbuf_dma;\n+\n+\t\tWRITE_ONCE(lp-\u003estopping, true);\n \t\tdmaengine_terminate_sync(lp-\u003etx_chan);\n-\t\tdmaengine_synchronize(lp-\u003etx_chan);\n \t\tdmaengine_terminate_sync(lp-\u003erx_chan);\n-\t\tdmaengine_synchronize(lp-\u003erx_chan);\n-\n-\t\tfor (i = 0; i \u003c TX_BD_NUM_MAX; i++)\n-\t\t\tkfree(lp-\u003etx_skb_ring[i]);\n-\t\tkfree(lp-\u003etx_skb_ring);\n-\t\tfor (i = 0; i \u003c RX_BUF_NUM_DEFAULT; i++)\n-\t\t\tkfree(lp-\u003erx_skb_ring[i]);\n-\t\tkfree(lp-\u003erx_skb_ring);\n \n+\t\t/* Release the channels before freeing the rings, so the DMA is\n+\t\t * fully torn down before the memory its descriptors reference is\n+\t\t * freed.\n+\t\t */\n \t\tdma_release_channel(lp-\u003erx_chan);\n \t\tdma_release_channel(lp-\u003etx_chan);\n+\n+\t\t/* Unmap and free any buffer the terminate did not reclaim, so it\n+\t\t * is not leaked; a non-NULL skb marks such a slot.\n+\t\t */\n+\t\tfor (i = 0; i \u003c TX_BD_NUM_MAX; i++) {\n+\t\t\tskbuf_dma = lp-\u003etx_skb_ring[i];\n+\t\t\tif (skbuf_dma \u0026\u0026 skbuf_dma-\u003eskb) {\n+\t\t\t\tdma_unmap_sg(lp-\u003edev, skbuf_dma-\u003esgl,\n+\t\t\t\t\t     skbuf_dma-\u003esg_len, DMA_TO_DEVICE);\n+\t\t\t\tdev_kfree_skb_any(skbuf_dma-\u003eskb);\n+\t\t\t}\n+\t\t\tkfree(skbuf_dma);\n+\t\t}\n+\t\tkfree(lp-\u003etx_skb_ring);\n+\n+\t\tfor (i = 0; i \u003c RX_BUF_NUM_DEFAULT; i++) {\n+\t\t\tskbuf_dma = lp-\u003erx_skb_ring[i];\n+\t\t\tif (skbuf_dma \u0026\u0026 skbuf_dma-\u003eskb) {\n+\t\t\t\tdma_unmap_single(lp-\u003edev, skbuf_dma-\u003edma_address,\n+\t\t\t\t\t\t lp-\u003emax_frm_size, DMA_FROM_DEVICE);\n+\t\t\t\tdev_kfree_skb_any(skbuf_dma-\u003eskb);\n+\t\t\t}\n+\t\t\tkfree(skbuf_dma);\n+\t\t}\n+\t\tkfree(lp-\u003erx_skb_ring);\n \t}\n \n \tnetdev_reset_queue(ndev);\n"
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The modified code belongs to the Xilinx AXI Ethernet driver (drivers/net/ethernet/xilinx/xilinx_axienet_main.c), an OF/Device Tree platform driver for Xilinx FPGA/SoC soft IP cores (such as Zynq or MicroBlaze). On the target architecture (amd64), this hardware cannot be probed or initialized in standard QEMU or GCE virtual environments, rendering the code structurally unreachable for fuzzing.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit ae03c9c30232143c86fb4d732c69a105e445ba90
Author: syz-cluster <triage@syzkaller.com>
Date:   Sat Sep 19 04:04:39 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index fcd3aaef27fc3..7c75e313dd33a 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -523,8 +523,9 @@ struct skbuf_dma_descriptor {
  * @stats_work: Work for reading the hardware statistics counters often enough
  *              to catch overflows.
  * @dma_err_task: Work structure to process Axi DMA errors
- * @stopping:   Set when @dma_err_task shouldn't do anything because we are
- *              about to stop the device.
+ * @stopping:   Set when we are about to stop the device: makes @dma_err_task
+ *              a no-op (legacy DMA path) and fences RX descriptor
+ *              resubmission in axienet_dma_rx_cb() (dmaengine path).
  * @tx_irq:	Axidma TX IRQ number
  * @rx_irq:	Axidma RX IRQ number
  * @eth_irq:	Ethernet core IRQ number
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 782f903d318f3..36a487f791a29 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -881,6 +881,7 @@ static void axienet_dma_tx_cb(void *data, const struct dmaengine_result *result)
 	u64_stats_update_end(&lp->tx_stat_sync);
 	dma_unmap_sg(lp->dev, skbuf_dma->sgl, skbuf_dma->sg_len, DMA_TO_DEVICE);
 	dev_consume_skb_any(skbuf_dma->skb);
+	skbuf_dma->skb = NULL;
 	netif_txq_completed_wake(txq, 1, len,
 				 CIRC_SPACE(lp->tx_ring_head, lp->tx_ring_tail, TX_BD_NUM_MAX),
 				 2);
@@ -1171,6 +1172,7 @@ static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *result)
 						       &meta_max_len);
 	dma_unmap_single(lp->dev, skbuf_dma->dma_address, lp->max_frm_size,
 			 DMA_FROM_DEVICE);
+	skbuf_dma->skb = NULL;
 
 	if (IS_ERR(app_metadata)) {
 		if (net_ratelimit())
@@ -1193,6 +1195,12 @@ static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *result)
 	u64_stats_update_end(&lp->rx_stat_sync);
 
 rx_submit:
+	/* Do not re-arm the RX ring while a stop is in progress, or the
+	 * teardown could free a buffer still handed to the engine.
+	 */
+	if (READ_ONCE(lp->stopping))
+		return;
+
 	for (i = 0; i < CIRC_SPACE(lp->rx_ring_head, lp->rx_ring_tail,
 				   RX_BUF_NUM_DEFAULT); i++)
 		axienet_rx_submit_desc(lp->ndev);
@@ -1541,6 +1549,7 @@ static int axienet_init_dmaengine(struct net_device *ndev)
 	lp->tx_ring_head = 0;
 	lp->rx_ring_tail = 0;
 	lp->rx_ring_head = 0;
+	lp->stopping = false;
 	lp->tx_skb_ring = kzalloc_objs(*lp->tx_skb_ring, TX_BD_NUM_MAX);
 	if (!lp->tx_skb_ring) {
 		ret = -ENOMEM;
@@ -1752,20 +1761,43 @@ static int axienet_stop(struct net_device *ndev)
 		free_irq(lp->rx_irq, ndev);
 		axienet_dma_bd_release(ndev);
 	} else {
+		struct skbuf_dma_descriptor *skbuf_dma;
+
+		WRITE_ONCE(lp->stopping, true);
 		dmaengine_terminate_sync(lp->tx_chan);
-		dmaengine_synchronize(lp->tx_chan);
 		dmaengine_terminate_sync(lp->rx_chan);
-		dmaengine_synchronize(lp->rx_chan);
-
-		for (i = 0; i < TX_BD_NUM_MAX; i++)
-			kfree(lp->tx_skb_ring[i]);
-		kfree(lp->tx_skb_ring);
-		for (i = 0; i < RX_BUF_NUM_DEFAULT; i++)
-			kfree(lp->rx_skb_ring[i]);
-		kfree(lp->rx_skb_ring);
 
+		/* Release the channels before freeing the rings, so the DMA is
+		 * fully torn down before the memory its descriptors reference is
+		 * freed.
+		 */
 		dma_release_channel(lp->rx_chan);
 		dma_release_channel(lp->tx_chan);
+
+		/* Unmap and free any buffer the terminate did not reclaim, so it
+		 * is not leaked; a non-NULL skb marks such a slot.
+		 */
+		for (i = 0; i < TX_BD_NUM_MAX; i++) {
+			skbuf_dma = lp->tx_skb_ring[i];
+			if (skbuf_dma && skbuf_dma->skb) {
+				dma_unmap_sg(lp->dev, skbuf_dma->sgl,
+					     skbuf_dma->sg_len, DMA_TO_DEVICE);
+				dev_kfree_skb_any(skbuf_dma->skb);
+			}
+			kfree(skbuf_dma);
+		}
+		kfree(lp->tx_skb_ring);
+
+		for (i = 0; i < RX_BUF_NUM_DEFAULT; i++) {
+			skbuf_dma = lp->rx_skb_ring[i];
+			if (skbuf_dma && skbuf_dma->skb) {
+				dma_unmap_single(lp->dev, skbuf_dma->dma_address,
+						 lp->max_frm_size, DMA_FROM_DEVICE);
+				dev_kfree_skb_any(skbuf_dma->skb);
+			}
+			kfree(skbuf_dma);
+		}
+		kfree(lp->rx_skb_ring);
 	}
 
 	netdev_reset_queue(ndev);

							input: 4582
							output: 36
							thoughts: 128

**Analyzing a Network Driver Patch**

Okay, so I've got a patch here that's caught my eye. First things first, let's see exactly what's being modified. It looks like we're dealing with the `xilinx_axienet` driver, specifically header and main C files within the `drivers/net/ethernet/xilinx/` directory. Hmm, `xilinx_axienet`... I need to refresh my memory on this one. What's the core functionality? What kind of bus or platform is it designed for? Time to check the driver definition itself. I'll need to look at its Kconfig entries and relevant dependencies to get a good handle on its architecture. Good, the target here is amd64, so it's a platform I'm familiar with.

Now, instead of getting bogged down in line-by-line code reviews just yet, let's leverage `grepper` to quickly pinpoint key configuration options or any relevant relationships within the `drivers/net/ethernet/xilinx/Kconfig` file or related configurations. This should give me a solid high-level overview of the driver's role and any potential impact this patch might have.

{
  "Expression": "config XILINX",
  "PathPrefix": "drivers/net/ethernet/xilinx/"
}

{
  "Output": "drivers/net/ethernet/xilinx/Kconfig=17=if NET_VENDOR_XILINX\ndrivers/net/ethernet/xilinx/Kconfig-18-\ndrivers/net/ethernet/xilinx/Kconfig:19:config XILINX_EMACLITE\ndrivers/net/ethernet/xilinx/Kconfig-20-\ttristate \"Xilinx 10/100 Ethernet Lite support\"\n--\ndrivers/net/ethernet/xilinx/Kconfig-25-\ndrivers/net/ethernet/xilinx/Kconfig:26:config XILINX_AXI_EMAC\ndrivers/net/ethernet/xilinx/Kconfig-27-\ttristate \"Xilinx 10/100/1000 AXI Ethernet support\"\n--\ndrivers/net/ethernet/xilinx/Kconfig-35-\ndrivers/net/ethernet/xilinx/Kconfig:36:config XILINX_LL_TEMAC\ndrivers/net/ethernet/xilinx/Kconfig-37-\ttristate \"Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver\"\n"
}

							input: 5308
							output: 40
							thoughts: 35

Okay, here's my interpretation of that thought process, assuming I'm already quite familiar with embedded networking and Linux kernel configuration:

**Diving into the Xilinx Ethernet Driver Configuration**

Right, let's get down to brass tacks. I need to understand the dependencies for `XILINX_AXI_EMAC`. A quick look at the Kconfig file in the `drivers/net/ethernet/xilinx/` directory is the most direct way to achieve this. I want to see what other options need to be enabled, what hardware is expected, and perhaps any platform-specific configurations that might be required before I even consider enabling the AXI Ethernet MAC. Knowing the dependencies is crucial for a clean and correct integration, and prevents future headaches. This Kconfig file will be my starting point.

{
  "File": "drivers/net/ethernet/xilinx/Kconfig",
  "FirstLine": 15,
  "LineCount": 40
}

{
  "Contents": "  15:\t\t  for your specific card in the following questions.\n  16:\t\n  17:\tif NET_VENDOR_XILINX\n  18:\t\n  19:\tconfig XILINX_EMACLITE\n  20:\t\ttristate \"Xilinx 10/100 Ethernet Lite support\"\n  21:\t\tdepends on HAS_IOMEM\n  22:\t\tselect PHYLIB\n  23:\t\thelp\n  24:\t\t  This driver supports the 10/100 Ethernet Lite from Xilinx.\n  25:\t\n  26:\tconfig XILINX_AXI_EMAC\n  27:\t\ttristate \"Xilinx 10/100/1000 AXI Ethernet support\"\n  28:\t\tdepends on HAS_IOMEM\n  29:\t\tdepends on XILINX_DMA\n  30:\t\tselect PHYLINK\n  31:\t\tselect DIMLIB\n  32:\t\thelp\n  33:\t\t  This driver supports the 10/100/1000 Ethernet from Xilinx for the\n  34:\t\t  AXI bus interface used in Xilinx Virtex FPGAs and Soc's.\n  35:\t\n  36:\tconfig XILINX_LL_TEMAC\n  37:\t\ttristate \"Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver\"\n  38:\t\tdepends on HAS_IOMEM\n  39:\t\tselect PHYLIB\n  40:\t\thelp\n  41:\t\t  This driver supports the Xilinx 10/100/1000 LocalLink TEMAC\n  42:\t\t  core used in Xilinx Spartan and Virtex FPGAs\n  43:\t\n  44:\tendif # NET_VENDOR_XILINX\n"
}

							input: 6016
							output: 51
							thoughts: 31

Here's my attempt at summarizing the thought process, tailored for an expert audience:

**Analyzing the xilinx_axienet Probe Sequence**

Alright, let's dive into how the `xilinx_axienet` driver is probed. My immediate focus is on its registration method – is it utilizing the platform driver framework, an OF (device tree) based approach, or perhaps something else entirely? I need to quickly identify the mechanism it's using to attach itself to the hardware and initialize. Knowing the probe method will tell me a lot about the expected device tree bindings, resource allocation strategies, and the overall driver architecture. Understanding the probe path is critical to understanding the dependency chain, and I'll need to follow how it handles device discovery, resource acquisition, and any potential deferred probe mechanisms. Any insights into error handling during this process will also be useful.

{
  "Expression": "module_platform_driver|platform_driver",
  "PathPrefix": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c"
}

{
  "Output": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c=3248=static DEFINE_SIMPLE_DEV_PM_OPS(axienet_pm_ops,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3250-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3251:static struct platform_driver axienet_driver = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3252-\t.probe = axienet_probe,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3261-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3262:module_platform_driver(axienet_driver);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3263-\n"
}

							input: 6552
							output: 49
							thoughts: 35

Okay, let's dive into this. Here's how I'd approach that driver code:

**Diving into the Xilinx AXI Ethernet Driver**

Alright, so the first thing I want to do is get a handle on the probe function and the match tables. I need to understand how the system identifies and initializes this Xilinx AXI Ethernet controller. I'm going to navigate to `drivers/net/ethernet/xilinx/xilinx_axienet_main.c`. That's where the core logic usually resides for this kind of device. Specifically, I'm focusing on those two key elements – the probe routine, which likely handles hardware detection and resource allocation, and the match tables, which define what hardware IDs this driver is responsible for handling. I need to quickly grasp how the driver associates itself with specific AXI Ethernet hardware configurations. Knowing the probe process and the device matching criteria is fundamental to troubleshooting and customization down the line. It tells me the very foundation of how the driver knows it's the right one for the job.

{
  "Expression": "axienet_of_match",
  "PathPrefix": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c"
}

{
  "Output": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c=66=static void axienet_rx_submit_desc(struct net_device *ndev);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-68-/* Match table for of_platform binding */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:69:static const struct of_device_id axienet_of_match[] = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-70-\t{ .compatible = \"xlnx,axi-ethernet-1.00.a\", },\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-75-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:76:MODULE_DEVICE_TABLE(of, axienet_of_match);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-77-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c=3251=static struct platform_driver axienet_driver = {\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3257-\t\t .pm = \u0026axienet_pm_ops,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3258:\t\t .of_match_table = axienet_of_match,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3259-\t},\n"
}

							input: 7315
							output: 21
							thoughts: 87

**Analyzing the Device Driver Configuration**

Okay, hold on a second! My initial understanding is that `axienet_driver` is strictly an OF (Device Tree) based platform driver. This is evident from the fact that its `of_match_table` is explicitly configured for OF matching.

My thought process now is to confirm my initial assumption. I need to make sure that there isn't an ACPI or `platform_device_id` fallback, or some other mechanism that could bypass the Device Tree requirement. And I should also confirm my understanding of that build-in `XILINX_DMA`.

Therefore, my next step is to quickly search the kernel's Kconfig files for a definition of `XILINX_DMA` to figure out what it represents and if it's relevant to this driver's configuration. This will give me a clear picture of how this driver is integrated and dependent.

{
  "Expression": "config XILINX_DMA"
}

{
  "Output": "drivers/dma/Kconfig=674=config XGENE_DMA\n--\ndrivers/dma/Kconfig-682-\ndrivers/dma/Kconfig:683:config XILINX_DMA\ndrivers/dma/Kconfig-684-\ttristate \"Xilinx AXI DMAS Engine\"\n"
}

							input: 7709
							output: 35
							thoughts: 20

Here's my summary, as if I were thinking these thoughts:

**Analyzing DMA Configuration Options**

Okay, time to dive into the DMA configuration. I need to refresh my memory on the current state of things, so I'm going to jump into `drivers/dma/Kconfig`. Specifically, I want to zero in on the relevant section, and I'm pretty sure it's around line 683. Hopefully, that's where I can get a good overview of the key configuration options and dependencies we're working with here. I need to understand the current architecture and get a handle on the DMA settings. Let's get to it.

{
  "File": "drivers/dma/Kconfig",
  "FirstLine": 680,
  "LineCount": 25
}

{
  "Contents": " 680:\t\thelp\n 681:\t\t  Enable support for the APM X-Gene SoC DMA engine.\n 682:\t\n 683:\tconfig XILINX_DMA\n 684:\t\ttristate \"Xilinx AXI DMAS Engine\"\n 685:\t\tdepends on HAS_IOMEM\n 686:\t\tselect DMA_ENGINE\n 687:\t\thelp\n 688:\t\t  Enable support for Xilinx AXI VDMA Soft IP.\n 689:\t\n 690:\t\t  AXI VDMA engine provides high-bandwidth direct memory access\n 691:\t\t  between memory and AXI4-Stream video type target\n 692:\t\t  peripherals including peripherals which support AXI4-\n 693:\t\t  Stream Video Protocol.  It has two stream interfaces/\n 694:\t\t  channels, Memory Mapped to Stream (MM2S) and Stream to\n 695:\t\t  Memory Mapped (S2MM) for the data transfers.\n 696:\t\t  AXI CDMA engine provides high-bandwidth direct memory access\n 697:\t\t  between a memory-mapped source address and a memory-mapped\n 698:\t\t  destination address.\n 699:\t\t  AXI DMA engine provides high-bandwidth one dimensional direct\n 700:\t\t  memory access between memory and AXI4-Stream target peripherals.\n 701:\t\t  AXI MCDMA engine provides high-bandwidth direct memory access\n 702:\t\t  between memory and AXI4-Stream target peripherals. It provides\n 703:\t\t  the scatter gather interface with multiple channels independent\n 704:\t\t  configuration support.\n"
}

							input: 8326
							output: 51
							thoughts: 54

Here's my summary, as if I were thinking it:

**AXIENET Probe Dive**

Okay, so I need to quickly refresh my memory on the AXI Ethernet driver. I'm going to jump into the `axienet_probe` function within `drivers/net/ethernet/xilinx/xilinx_axienet_main.c`. The key question I've got right now is how the initialization works, and more specifically, whether I can trigger a probe event without needing a fully defined hardware setup or device tree entry just yet. I'm hoping I can at least get the core logic down and then think about the hardware dependencies later. Let's see if this probe function holds the answers I'm looking for.

{
  "File": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c",
  "FirstLine": 2950,
  "LineCount": 80
}

{
  "Contents": "2950:\t\t\t\tlp-\u003ephy_mode = PHY_INTERFACE_MODE_GMII;\n2951:\t\t\t\tbreak;\n2952:\t\t\tcase XAE_PHY_TYPE_RGMII_2_0:\n2953:\t\t\t\tlp-\u003ephy_mode = PHY_INTERFACE_MODE_RGMII_ID;\n2954:\t\t\t\tbreak;\n2955:\t\t\tcase XAE_PHY_TYPE_SGMII:\n2956:\t\t\t\tlp-\u003ephy_mode = PHY_INTERFACE_MODE_SGMII;\n2957:\t\t\t\tbreak;\n2958:\t\t\tcase XAE_PHY_TYPE_1000BASE_X:\n2959:\t\t\t\tlp-\u003ephy_mode = PHY_INTERFACE_MODE_1000BASEX;\n2960:\t\t\t\tbreak;\n2961:\t\t\tdefault:\n2962:\t\t\t\treturn -EINVAL;\n2963:\t\t\t}\n2964:\t\t} else {\n2965:\t\t\tret = of_get_phy_mode(pdev-\u003edev.of_node, \u0026lp-\u003ephy_mode);\n2966:\t\t\tif (ret)\n2967:\t\t\t\treturn ret;\n2968:\t\t}\n2969:\t\tif (lp-\u003eswitch_x_sgmii \u0026\u0026 lp-\u003ephy_mode != PHY_INTERFACE_MODE_SGMII \u0026\u0026\n2970:\t\t    lp-\u003ephy_mode != PHY_INTERFACE_MODE_1000BASEX) {\n2971:\t\t\tdev_err(\u0026pdev-\u003edev, \"xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\\n\");\n2972:\t\t\treturn -EINVAL;\n2973:\t\t}\n2974:\t\n2975:\t\tif (!of_property_present(pdev-\u003edev.of_node, \"dmas\")) {\n2976:\t\t\t/* Find the DMA node, map the DMA registers, and decode the DMA IRQs */\n2977:\t\t\tnp = of_parse_phandle(pdev-\u003edev.of_node, \"axistream-connected\", 0);\n2978:\t\n2979:\t\t\tif (np) {\n2980:\t\t\t\tstruct resource dmares;\n2981:\t\n2982:\t\t\t\tret = of_address_to_resource(np, 0, \u0026dmares);\n2983:\t\t\t\tif (ret) {\n2984:\t\t\t\t\tdev_err(\u0026pdev-\u003edev,\n2985:\t\t\t\t\t\t\"unable to get DMA resource\\n\");\n2986:\t\t\t\t\tof_node_put(np);\n2987:\t\t\t\t\treturn ret;\n2988:\t\t\t\t}\n2989:\t\t\t\tlp-\u003edma_regs = devm_ioremap_resource(\u0026pdev-\u003edev,\n2990:\t\t\t\t\t\t\t\t     \u0026dmares);\n2991:\t\t\t\tlp-\u003erx_irq = irq_of_parse_and_map(np, 1);\n2992:\t\t\t\tlp-\u003etx_irq = irq_of_parse_and_map(np, 0);\n2993:\t\t\t\tof_node_put(np);\n2994:\t\t\t\tlp-\u003eeth_irq = platform_get_irq_optional(pdev, 0);\n2995:\t\t\t} else {\n2996:\t\t\t\t/* Check for these resources directly on the Ethernet node. */\n2997:\t\t\t\tlp-\u003edma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);\n2998:\t\t\t\tlp-\u003erx_irq = platform_get_irq(pdev, 1);\n2999:\t\t\t\tlp-\u003etx_irq = platform_get_irq(pdev, 0);\n3000:\t\t\t\tlp-\u003eeth_irq = platform_get_irq_optional(pdev, 2);\n3001:\t\t\t}\n3002:\t\t\tif (IS_ERR(lp-\u003edma_regs)) {\n3003:\t\t\t\tdev_err(\u0026pdev-\u003edev, \"could not map DMA regs\\n\");\n3004:\t\t\t\treturn PTR_ERR(lp-\u003edma_regs);\n3005:\t\t\t}\n3006:\t\t\tif (!lp-\u003erx_irq || !lp-\u003etx_irq) {\n3007:\t\t\t\tdev_err(\u0026pdev-\u003edev, \"could not determine irqs\\n\");\n3008:\t\t\t\treturn -EINVAL;\n3009:\t\t\t}\n3010:\t\t\tif (lp-\u003erx_irq \u003c 0)\n3011:\t\t\t\treturn lp-\u003erx_irq;\n3012:\t\t\tif (lp-\u003etx_irq \u003c 0)\n3013:\t\t\t\treturn lp-\u003etx_irq;\n3014:\t\t\tif (lp-\u003eeth_irq \u003c 0 \u0026\u0026 lp-\u003eeth_irq != -ENXIO)\n3015:\t\t\t\treturn lp-\u003eeth_irq;\n3016:\t\n3017:\t\t\t/* Reset core now that clocks are enabled, prior to accessing MDIO */\n3018:\t\t\tret = __axienet_device_reset(lp);\n3019:\t\t\tif (ret)\n3020:\t\t\t\treturn ret;\n3021:\t\n3022:\t\t\t/* Autodetect the need for 64-bit DMA pointers.\n3023:\t\t\t * When the IP is configured for a bus width bigger than 32 bits,\n3024:\t\t\t * writing the MSB registers is mandatory, even if they are all 0.\n3025:\t\t\t * We can detect this case by writing all 1's to one such register\n3026:\t\t\t * and see if that sticks: when the IP is configured for 32 bits\n3027:\t\t\t * only, those registers are RES0.\n3028:\t\t\t * Those MSB registers were introduced in IP v7.1, which we check first.\n3029:\t\t\t */\n"
}

							input: 10066
							output: 51
							thoughts: 61

**Diving into the AXI Ethernet Driver**

Okay, so I'm digging into this `xilinx_axienet_main.c` file – that's where the heart of the Xilinx AXI Ethernet driver lives, right? My focus right now is on understanding the `axienet_probe` function. I need to get a really good grasp of what happens during the probe process.

Let's drill down into lines 2800 through 2950. That should give me a solid chunk of the routine to analyze. I'm expecting to see things like device resource allocation, initialization of the hardware, perhaps some interrupt setup, and the basic configuration that's necessary for the driver to get the AXI Ethernet core up and running. I'll be looking for how the driver interacts with the hardware, how it maps registers, and how it handles the device's specific capabilities. I'm hoping to understand the complete boot path here. Time to get to work!

{
  "File": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c",
  "FirstLine": 2850,
  "LineCount": 80
}

{
  "Contents": "2850:\t\n2851:\t\tlp = netdev_priv(ndev);\n2852:\t\tlp-\u003endev = ndev;\n2853:\t\tlp-\u003edev = \u0026pdev-\u003edev;\n2854:\t\tlp-\u003eoptions = XAE_OPTION_DEFAULTS;\n2855:\t\tlp-\u003erx_bd_num = RX_BD_NUM_DEFAULT;\n2856:\t\tlp-\u003etx_bd_num = TX_BD_NUM_DEFAULT;\n2857:\t\n2858:\t\tu64_stats_init(\u0026lp-\u003erx_stat_sync);\n2859:\t\tu64_stats_init(\u0026lp-\u003etx_stat_sync);\n2860:\t\n2861:\t\tmutex_init(\u0026lp-\u003estats_lock);\n2862:\t\tseqcount_mutex_init(\u0026lp-\u003ehw_stats_seqcount, \u0026lp-\u003estats_lock);\n2863:\t\tINIT_DEFERRABLE_WORK(\u0026lp-\u003estats_work, axienet_refresh_stats);\n2864:\t\n2865:\t\tlp-\u003eaxi_clk = devm_clk_get_optional_enabled(\u0026pdev-\u003edev,\n2866:\t\t\t\t\t\t\t    \"s_axi_lite_clk\");\n2867:\t\tif (!lp-\u003eaxi_clk) {\n2868:\t\t\t/* For backward compatibility, if named AXI clock is not present,\n2869:\t\t\t * treat the first clock specified as the AXI clock.\n2870:\t\t\t */\n2871:\t\t\tlp-\u003eaxi_clk = devm_clk_get_optional_enabled(\u0026pdev-\u003edev, NULL);\n2872:\t\t}\n2873:\t\tif (IS_ERR(lp-\u003eaxi_clk))\n2874:\t\t\treturn dev_err_probe(\u0026pdev-\u003edev, PTR_ERR(lp-\u003eaxi_clk),\n2875:\t\t\t\t\t     \"could not get AXI clock\\n\");\n2876:\t\n2877:\t\tlp-\u003emisc_clks[0].id = \"axis_clk\";\n2878:\t\tlp-\u003emisc_clks[1].id = \"ref_clk\";\n2879:\t\tlp-\u003emisc_clks[2].id = \"mgt_clk\";\n2880:\t\n2881:\t\tret = devm_clk_bulk_get_optional_enable(\u0026pdev-\u003edev, XAE_NUM_MISC_CLOCKS,\n2882:\t\t\t\t\t\t\tlp-\u003emisc_clks);\n2883:\t\tif (ret)\n2884:\t\t\treturn dev_err_probe(\u0026pdev-\u003edev, ret,\n2885:\t\t\t\t\t     \"could not get/enable misc. clocks\\n\");\n2886:\t\n2887:\t\t/* Map device registers */\n2888:\t\tlp-\u003eregs = devm_platform_get_and_ioremap_resource(pdev, 0, \u0026ethres);\n2889:\t\tif (IS_ERR(lp-\u003eregs))\n2890:\t\t\treturn PTR_ERR(lp-\u003eregs);\n2891:\t\tlp-\u003eregs_start = ethres-\u003estart;\n2892:\t\n2893:\t\t/* Setup checksum offload, but default to off if not specified */\n2894:\t\tlp-\u003efeatures = 0;\n2895:\t\n2896:\t\tif (axienet_ior(lp, XAE_ABILITY_OFFSET) \u0026 XAE_ABILITY_STATS)\n2897:\t\t\tlp-\u003efeatures |= XAE_FEATURE_STATS;\n2898:\t\n2899:\t\tret = of_property_read_u32(pdev-\u003edev.of_node, \"xlnx,txcsum\", \u0026value);\n2900:\t\tif (!ret) {\n2901:\t\t\tswitch (value) {\n2902:\t\t\tcase 1:\n2903:\t\t\t\tlp-\u003efeatures |= XAE_FEATURE_PARTIAL_TX_CSUM;\n2904:\t\t\t\t/* Can checksum any contiguous range */\n2905:\t\t\t\tndev-\u003efeatures |= NETIF_F_HW_CSUM;\n2906:\t\t\t\tbreak;\n2907:\t\t\tcase 2:\n2908:\t\t\t\tlp-\u003efeatures |= XAE_FEATURE_FULL_TX_CSUM;\n2909:\t\t\t\t/* Can checksum TCP/UDP over IPv4. */\n2910:\t\t\t\tndev-\u003efeatures |= NETIF_F_IP_CSUM;\n2911:\t\t\t\tbreak;\n2912:\t\t\t}\n2913:\t\t}\n2914:\t\tret = of_property_read_u32(pdev-\u003edev.of_node, \"xlnx,rxcsum\", \u0026value);\n2915:\t\tif (!ret) {\n2916:\t\t\tswitch (value) {\n2917:\t\t\tcase 1:\n2918:\t\t\t\tlp-\u003efeatures |= XAE_FEATURE_PARTIAL_RX_CSUM;\n2919:\t\t\t\tndev-\u003efeatures |= NETIF_F_RXCSUM;\n2920:\t\t\t\tbreak;\n2921:\t\t\tcase 2:\n2922:\t\t\t\tlp-\u003efeatures |= XAE_FEATURE_FULL_RX_CSUM;\n2923:\t\t\t\tndev-\u003efeatures |= NETIF_F_RXCSUM;\n2924:\t\t\t\tbreak;\n2925:\t\t\t}\n2926:\t\t}\n2927:\t\t/* For supporting jumbo frames, the Axi Ethernet hardware must have\n2928:\t\t * a larger Rx/Tx Memory. Typically, the size must be large so that\n2929:\t\t * we can enable jumbo option and start supporting jumbo frames.\n"
}

							input: 11798
							output: 25
							thoughts: 393

**My Assessment of axienet_probe and Reachability for Fuzzing**

Okay, let's break this down. I'm looking at `axienet_probe` and it's immediately clear this is a fairly involved device driver. It needs an OF node, device registers, clocks, DMA channels, and PHY configuration – the usual suspects for a network interface controller.

The critical question here, and the core of my current analysis, is whether this driver is even *reachable* in a standard virtualized environment like GCE or QEMU, specifically on an amd64 architecture. That's the gatekeeper for fuzzing, according to the methodology.

Let's see: the target architecture is amd64, so that's fine. But is Xilinx AXI Ethernet *emulated* in QEMU or GCE on amd64? That's the real crux of it. I know QEMU has Zynq/MicroBlaze machine emulation, but that's for ARM/MicroBlaze targets. I'm on amd64, and the question is whether the Xilinx AXI Ethernet part is accessible.

The instructions are clear on reachability. Section 1 and 2 say: code has to *execute* in these environments, and structurally unreachable code shouldn't be fuzzed. That makes sense; it's a waste of resources otherwise.

They give examples of unreachable hardware: vendor-specific PCIe stuff that requires a real ASIC or PCIe card, and that's *not* emulated. On the flip side, reachable drivers are those accessible via virtual buses like virtio, USB gadget, loopback, etc. That's a good distinction.

Now I'm wondering if `xilinx_axienet` could be a PCI device, if it has any PCI glue, or if it's purely a platform driver. That would change the game! So I need to expand the search and look for the driver in the whole tree, and see what the device model is. I need to figure out how it connects to the system, so that I can determine how reachable it really is.

{
  "Expression": "axienet",
  "PathPrefix": "drivers/"
}

{
  "Output": "\nFull output is too long, showing 500 out of 1727 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/xilinx/Makefile=8=obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o\ndrivers/net/ethernet/xilinx/Makefile:9:xilinx_emac-objs := xilinx_axienet_main.o xilinx_axienet_mdio.o\ndrivers/net/ethernet/xilinx/Makefile-10-obj-$(CONFIG_XILINX_AXI_EMAC) += xilinx_emac.o\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h=462=struct skbuf_dma_descriptor {\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-470-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:471: * struct axienet_local - axienet private per device data\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-472- * @ndev:\tPointer for net_device to which it will be attached.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-482- * @mii_clk_div: MII bus clock divider value\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:483: * @regs_start: Resource start for axienet device addresses\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:484: * @regs:\tBase address for the axienet_local device address space\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-485- * @dma_regs:\tBase address for the axidma device address space\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-527- *              a no-op (legacy DMA path) and fences RX descriptor\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:528: *              resubmission in axienet_dma_rx_cb() (dmaengine path).\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-529- * @tx_irq:\tAxidma TX IRQ number\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-533- * @options:\tAxiEthernet option word\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:534: * @features:\tStores the extended features supported by the axienet hw\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-535- * @max_frm_size: Stores the maximum size of the frame that can be that\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-549- */\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:550:struct axienet_local {\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-551-\tstruct net_device *ndev;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-632-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:633: * struct axienet_option - Used to set axi ethernet hardware options\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-634- * @opt:\tOption to be set.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-637- */\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:638:struct axienet_option {\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-639-\tu32 opt;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-644-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:645: * axienet_ior - Memory mapped Axi Ethernet register read\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:646: * @lp:         Pointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-647- * @offset:     Address offset from the base address of Axi Ethernet core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-652- */\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:653:static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-654-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-657-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:658:static inline u32 axinet_ior_read_mcr(struct axienet_local *lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-659-{\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:660:\treturn axienet_ior(lp, XAE_MDIO_MCR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-661-}\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-662-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:663:static inline void axienet_lock_mii(struct axienet_local *lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-664-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-668-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:669:static inline void axienet_unlock_mii(struct axienet_local *lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-670-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-675-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:676: * axienet_iow - Memory mapped Axi Ethernet register write\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:677: * @lp:         Pointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-678- * @offset:     Address offset from the base address of Axi Ethernet core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-683- */\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:684:static inline void axienet_iow(struct axienet_local *lp, off_t offset,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-685-\t\t\t       u32 value)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-690-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:691: * axienet_dma_out32 - Memory mapped Axi DMA register write.\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:692: * @lp:\t\tPointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-693- * @reg:\tAddress offset from the base address of the Axi DMA core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-699-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:700:static inline void axienet_dma_out32(struct axienet_local *lp,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-701-\t\t\t\t     off_t reg, u32 value)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-707-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:708: * axienet_dma_out64 - Memory mapped Axi DMA register write.\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:709: * @lp:\t\tPointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-710- * @reg:\tAddress offset from the base address of the Axi DMA core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-715- */\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:716:static inline void axienet_dma_out64(struct axienet_local *lp,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-717-\t\t\t\t     off_t reg, u64 value)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-721-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:722:static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-723-\t\t\t\t\tdma_addr_t addr)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-725-\tif (lp-\u003efeatures \u0026 XAE_FEATURE_DMA_64BIT)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:726:\t\taxienet_dma_out64(lp, reg, addr);\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-727-\telse\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:728:\t\taxienet_dma_out32(lp, reg, lower_32_bits(addr));\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-729-}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-732-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:733:static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-734-\t\t\t\t\tdma_addr_t addr)\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-735-{\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:736:\taxienet_dma_out32(lp, reg, lower_32_bits(addr));\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-737-}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-740-\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:741:/* Function prototypes visible in xilinx_axienet_mdio.c for other files */\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:742:int axienet_mdio_setup(struct axienet_local *lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet.h:743:void axienet_mdio_teardown(struct axienet_local *lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet.h-744-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-46-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:47:#include \"xilinx_axienet.h\"\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-48-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-59-/* Must be shorter than length of ethtool_drvinfo.driver field to fit */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:60:#define DRIVER_NAME\t\t\"xaxienet\"\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-61-#define DRIVER_DESCRIPTION\t\"Xilinx Axi Ethernet driver\"\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-65-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:66:static void axienet_rx_submit_desc(struct net_device *ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-67-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-68-/* Match table for of_platform binding */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:69:static const struct of_device_id axienet_of_match[] = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-70-\t{ .compatible = \"xlnx,axi-ethernet-1.00.a\", },\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-75-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:76:MODULE_DEVICE_TABLE(of, axienet_of_match);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-77-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-78-/* Option table for setting up Axi Ethernet hardware options */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:79:static struct axienet_option axienet_options[] = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-80-\t/* Turn on jumbo packet support for both Rx and Tx */\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-132-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:133:static struct skbuf_dma_descriptor *axienet_get_rx_desc(struct axienet_local *lp, int i)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-134-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-137-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:138:static struct skbuf_dma_descriptor *axienet_get_tx_desc(struct axienet_local *lp, int i)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-139-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-143-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:144: * axienet_dma_in32 - Memory mapped Axi DMA register read\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:145: * @lp:\t\tPointer to axienet local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-146- * @reg:\tAddress offset from the base address of the Axi DMA core\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-151- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:152:static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-153-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-156-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:157:static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-158-\t\t\t       struct axidma_bd *desc)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-164-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:165:static dma_addr_t desc_get_phys_addr(struct axienet_local *lp,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-166-\t\t\t\t     struct axidma_bd *desc)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-176-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:177: * axienet_dma_bd_release - Release buffer descriptor rings\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-178- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-180- * This function is used to release the descriptors allocated in\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:181: * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-182- * driver stop api is called.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-183- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:184:static void axienet_dma_bd_release(struct net_device *ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-185-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-186-\tint i;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:187:\tstruct axienet_local *lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-188-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-225-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:226:static u64 axienet_dma_rate(struct axienet_local *lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-227-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-233-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:234: * axienet_calc_cr() - Calculate control register value\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-235- * @lp: Device private data\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-243- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:244:static u32 axienet_calc_cr(struct axienet_local *lp, u32 count, u32 usec)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-245-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-253-\tif (count \u003e 1) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:254:\t\tu64 clk_rate = axienet_dma_rate(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-255-\t\tu32 timer;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-269-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:270: * axienet_coalesce_params() - Extract coalesce parameters from the CR\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-271- * @lp: Device private data\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-275- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:276:static void axienet_coalesce_params(struct axienet_local *lp, u32 cr,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-277-\t\t\t\t    u32 *count, u32 *usec)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-278-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:279:\tu64 clk_rate = axienet_dma_rate(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-280-\tu64 timer = FIELD_GET(XAXIDMA_DELAY_MASK, cr);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-286-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:287: * axienet_dma_start - Set up DMA registers and start DMA operation\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:288: * @lp:\t\tPointer to the axienet_local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-289- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:290:static void axienet_dma_start(struct axienet_local *lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-291-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-295-\tlp-\u003erx_dma_cr \u0026= ~XAXIDMA_CR_RUNSTOP_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:296:\taxienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp-\u003erx_dma_cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-297-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-300-\t */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:301:\taxienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp-\u003erx_bd_p);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-302-\tlp-\u003erx_dma_cr |= XAXIDMA_CR_RUNSTOP_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:303:\taxienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp-\u003erx_dma_cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:304:\taxienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp-\u003erx_bd_p +\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-305-\t\t\t     (sizeof(*lp-\u003erx_bd_v) * (lp-\u003erx_bd_num - 1)));\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-312-\tlp-\u003etx_dma_cr \u0026= ~XAXIDMA_CR_RUNSTOP_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:313:\taxienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp-\u003etx_dma_cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-314-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-318-\t */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:319:\taxienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp-\u003etx_bd_p);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-320-\tlp-\u003etx_dma_cr |= XAXIDMA_CR_RUNSTOP_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:321:\taxienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp-\u003etx_dma_cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-322-\tlp-\u003etx_dma_started = true;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-327-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:328: * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-329- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-336- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:337:static int axienet_dma_bd_init(struct net_device *ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-338-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-340-\tstruct sk_buff *skb;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:341:\tstruct axienet_local *lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-342-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-395-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:396:\taxienet_dma_start(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-397-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-399-out:\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:400:\taxienet_dma_bd_release(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-401-\treturn -ENOMEM;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-404-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:405: * axienet_set_mac_address - Write the MAC address\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-406- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-411- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:412:static void axienet_set_mac_address(struct net_device *ndev,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-413-\t\t\t\t    const void *address)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-414-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:415:\tstruct axienet_local *lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-416-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-422-\t/* Set up unicast MAC address filter set its mac address */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:423:\taxienet_iow(lp, XAE_UAW0_OFFSET,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-424-\t\t    (ndev-\u003edev_addr[0]) |\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-427-\t\t    (ndev-\u003edev_addr[3] \u003c\u003c 24));\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:428:\taxienet_iow(lp, XAE_UAW1_OFFSET,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:429:\t\t    (((axienet_ior(lp, XAE_UAW1_OFFSET)) \u0026\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-430-\t\t      ~XAE_UAW1_UNICASTADDR_MASK) |\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-442- * This function is called to initialize the MAC address of the Axi Ethernet\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:443: * core. It calls the core specific axienet_set_mac_address. This is the\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-444- * function that goes into net_device_ops structure entry ndo_set_mac_address.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c=446=static int netdev_set_mac_address(struct net_device *ndev, void *p)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-449-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:450:\taxienet_set_mac_address(ndev, addr-\u003esa_data);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-451-\treturn 0;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-454-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:455: * axienet_set_multicast_list - Prepare the multicast table\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-456- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-464- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:465:static void axienet_set_multicast_list(struct net_device *ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-466-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-468-\tu32 reg, af0reg, af1reg;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:469:\tstruct axienet_local *lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-470-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:471:\treg = axienet_ior(lp, XAE_FMI_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-472-\treg \u0026= ~XAE_FMI_PM_MASK;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-476-\t\treg \u0026= ~XAE_FMI_PM_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:477:\taxienet_iow(lp, XAE_FMI_OFFSET, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-478-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-481-\t\treg \u0026= 0xFFFFFF00;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:482:\t\taxienet_iow(lp, XAE_FMI_OFFSET, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:483:\t\taxienet_iow(lp, XAE_AF0_OFFSET, 1); /* Multicast bit */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:484:\t\taxienet_iow(lp, XAE_AF1_OFFSET, 0);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:485:\t\taxienet_iow(lp, XAE_AM0_OFFSET, 1); /* ditto */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:486:\t\taxienet_iow(lp, XAE_AM1_OFFSET, 0);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:487:\t\taxienet_iow(lp, XAE_FFE_OFFSET, 1);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-488-\t\ti = 1;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-506-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:507:\t\t\taxienet_iow(lp, XAE_FMI_OFFSET, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:508:\t\t\taxienet_iow(lp, XAE_AF0_OFFSET, af0reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:509:\t\t\taxienet_iow(lp, XAE_AF1_OFFSET, af1reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:510:\t\t\taxienet_iow(lp, XAE_AM0_OFFSET, 0xffffffff);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:511:\t\t\taxienet_iow(lp, XAE_AM1_OFFSET, 0x0000ffff);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:512:\t\t\taxienet_iow(lp, XAE_FFE_OFFSET, 1);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-513-\t\t\ti++;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-519-\t\treg |= i;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:520:\t\taxienet_iow(lp, XAE_FMI_OFFSET, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:521:\t\taxienet_iow(lp, XAE_FFE_OFFSET, 0);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-522-\t}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-525-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:526: * axienet_setoptions - Set an Axi Ethernet option\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-527- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-533- * these options in the Axi Ethernet hardware. This is done through\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:534: * axienet_option structure .\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-535- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:536:static void axienet_setoptions(struct net_device *ndev, u32 options)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-537-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-538-\tint reg;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:539:\tstruct axienet_local *lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:540:\tstruct axienet_option *tp = \u0026axienet_options[0];\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-541-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-542-\twhile (tp-\u003eopt) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:543:\t\treg = ((axienet_ior(lp, tp-\u003ereg)) \u0026 ~(tp-\u003em_or));\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-544-\t\tif (options \u0026 tp-\u003eopt)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-545-\t\t\treg |= tp-\u003em_or;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:546:\t\taxienet_iow(lp, tp-\u003ereg, reg);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-547-\t\ttp++;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-552-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:553:static u64 axienet_stat(struct axienet_local *lp, enum temac_stat stat)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-554-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-559-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:560:\tcounter = axienet_ior(lp, XAE_STATS_OFFSET + stat * 8);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-561-\treturn lp-\u003ehw_stat_base[stat] + (counter - lp-\u003ehw_last_counter[stat]);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-563-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:564:static void axienet_stats_update(struct axienet_local *lp, bool reset)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-565-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-570-\tfor (stat = 0; stat \u003c STAT_COUNT; stat++) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:571:\t\tu32 counter = axienet_ior(lp, XAE_STATS_OFFSET + stat * 8);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-572-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-578-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:579:static void axienet_refresh_stats(struct work_struct *work)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-580-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:581:\tstruct axienet_local *lp = container_of(work, struct axienet_local,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-582-\t\t\t\t\t\tstats_work.work);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-584-\tmutex_lock(\u0026lp-\u003estats_lock);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:585:\taxienet_stats_update(lp, false);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-586-\tmutex_unlock(\u0026lp-\u003estats_lock);\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-591-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:592:static int __axienet_device_reset(struct axienet_local *lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-593-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-599-\tif (lp-\u003efeatures \u0026 XAE_FEATURE_STATS)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:600:\t\taxienet_stats_update(lp, true);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-601-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-608-\t */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:609:\taxienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:610:\tret = read_poll_timeout(axienet_dma_in32, value,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-611-\t\t\t\t!(value \u0026 XAXIDMA_CR_RESET_MASK),\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-619-\t/* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:620:\tret = read_poll_timeout(axienet_ior, value,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-621-\t\t\t\tvalue \u0026 XAE_INT_PHYRSTCMPLT_MASK,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-636-\t\t\tu32 counter =\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:637:\t\t\t\taxienet_ior(lp, XAE_STATS_OFFSET + stat * 8);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-638-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-651-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:652: * axienet_dma_stop - Stop DMA operation\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:653: * @lp:\t\tPointer to the axienet_local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-654- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:655:static void axienet_dma_stop(struct axienet_local *lp)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-656-{\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-662-\tcr = lp-\u003erx_dma_cr \u0026 ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:663:\taxienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-664-\tlp-\u003erx_dma_started = false;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-671-\tcr = lp-\u003etx_dma_cr \u0026 ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:672:\taxienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-673-\tlp-\u003etx_dma_started = false;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-678-\t/* Give DMAs a chance to halt gracefully */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:679:\tsr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-680-\tfor (count = 0; !(sr \u0026 XAXIDMA_SR_HALT_MASK) \u0026\u0026 count \u003c 5; ++count) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-681-\t\tmsleep(20);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:682:\t\tsr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-683-\t}\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-684-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:685:\tsr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-686-\tfor (count = 0; !(sr \u0026 XAXIDMA_SR_HALT_MASK) \u0026\u0026 count \u003c 5; ++count) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-687-\t\tmsleep(20);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:688:\t\tsr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-689-\t}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-691-\t/* Do a reset to ensure DMA is really stopped */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:692:\taxienet_lock_mii(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:693:\t__axienet_device_reset(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:694:\taxienet_unlock_mii(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-695-}\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-697-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:698: * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-699- * @ndev:\tPointer to the net_device structure\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-709- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:710:static int axienet_device_reset(struct net_device *ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-711-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:712:\tu32 axienet_status;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:713:\tstruct axienet_local *lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-714-\tint ret;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-728-\tif (!lp-\u003euse_dmaengine) {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:729:\t\tret = __axienet_device_reset(lp);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-730-\t\tif (ret)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-732-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:733:\t\tret = axienet_dma_bd_init(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-734-\t\tif (ret) {\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-740-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:741:\taxienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:742:\taxienet_status \u0026= ~XAE_RCW1_RX_MASK;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:743:\taxienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-744-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:745:\taxienet_status = axienet_ior(lp, XAE_IP_OFFSET);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:746:\tif (axienet_status \u0026 XAE_INT_RXRJECT_MASK)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:747:\t\taxienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:748:\taxienet_iow(lp, XAE_IE_OFFSET, lp-\u003eeth_irq \u003e 0 ?\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-749-\t\t    XAE_INT_RECV_ERROR_MASK : 0);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-750-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:751:\taxienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-752-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-755-\t */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:756:\taxienet_setoptions(ndev, lp-\u003eoptions \u0026\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-757-\t\t\t   ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:758:\taxienet_set_mac_address(ndev, NULL);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:759:\taxienet_set_multicast_list(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:760:\taxienet_setoptions(ndev, lp-\u003eoptions);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-761-\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-767-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:768: * axienet_free_tx_chain - Clean up a series of linked TX descriptors.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:769: * @lp:\t\tPointer to the axienet_local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-770- * @first_bd:\tIndex of first descriptor to clean up\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-781- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:782:static int axienet_free_tx_chain(struct axienet_local *lp, u32 first_bd,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-783-\t\t\t\t int nr_bds, bool force, u32 *sizep, int budget)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-834-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:835: * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:836: * @lp:\t\tPointer to the axienet_local structure\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-837- * @num_frag:\tThe number of BDs to check for\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-846- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:847:static inline int axienet_check_tx_bd_space(struct axienet_local *lp,\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-848-\t\t\t\t\t    int num_frag)\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-861-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:862: * axienet_dma_tx_cb - DMA engine callback for TX channel.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:863: * @data:       Pointer to the axienet_local structure.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-864- * @result:     error reporting through dmaengine_result.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-867- */\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:868:static void axienet_dma_tx_cb(void *data, const struct dmaengine_result *result)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-869-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-870-\tstruct skbuf_dma_descriptor *skbuf_dma;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:871:\tstruct axienet_local *lp = data;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-872-\tstruct netdev_queue *txq;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-874-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:875:\tskbuf_dma = axienet_get_tx_desc(lp, lp-\u003etx_ring_tail++);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-876-\tlen = skbuf_dma-\u003eskb-\u003elen;\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-890-/**\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:891: * axienet_start_xmit_dmaengine - Starts the transmission.\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-892- * @skb:        sk_buff pointer that contains data to be Txed.\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c=905=static netdev_tx_t\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:906:axienet_start_xmit_dmaengine(struct sk_buff *skb, struct net_device *ndev)\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-907-{\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-908-\tstruct dma_async_tx_descriptor *dma_tx_desc = NULL;\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:909:\tstruct axienet_local *lp = netdev_priv(ndev);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-910-\tu32 app_metadata[DMA_NUM_APP_WORDS] = {0};\n\n"
}

							input: 28951
							output: 19
							thoughts: 88

Here's my thought process, as if I were analyzing that code:

**Diving into the AXI Ethernet Driver**

Okay, hold on a second. I'm looking at the `xilinx_axienet_main.c` file and specifically focusing on the driver. My initial question is: Is this driver *solely* initialized through Device Tree? The code seems to suggest that the `of_device_id axienet_of_match` is the only way this thing gets probed.

I need to confirm this. I'm not just going to take this at face value. I've seen drivers that use multiple probe methods. It could be DT, platform data, or even a module parameter. Let's see if there are *any* other references to the `axienet_driver` structure or any other probe functions. Time to break out the grepper! Let's see what the broader picture is. I'll search the code base for `axienet_driver` and see what comes up. That should give me a better understanding of how the driver is being used.

{
  "Expression": "axienet_driver"
}

{
  "Output": "drivers/net/ethernet/xilinx/xilinx_axienet_main.c=3248=static DEFINE_SIMPLE_DEV_PM_OPS(axienet_pm_ops,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3250-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3251:static struct platform_driver axienet_driver = {\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3252-\t.probe = axienet_probe,\n--\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3261-\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c:3262:module_platform_driver(axienet_driver);\ndrivers/net/ethernet/xilinx/xilinx_axienet_main.c-3263-\n"
}

							input: 29567
							output: 27
							thoughts: 258

**My Initial Assessment of the `axienet_driver` and its Potential Compatibility**

Okay, let's take a look at this `axienet_driver` structure here:

```c
static struct platform_driver axienet_driver = {
	.probe = axienet_probe,
	.remove_new = axienet_remove,
	.driver = {
		 .name = DRIVER_NAME,
		 .pm = &axienet_pm_ops,
		 .of_match_table = axienet_of_match,
	},
};
module_platform_driver(axienet_driver);
```

Right away, I see the use of an OF (Device Tree) match table, `axienet_of_match`. That's the key. Now, the question that *immediately* pops into my head, given the context, is: can this type of device driver, one designed to work with an OF device tree, actually be instantiated on an amd64 system, particularly in an environment like QEMU when running a test generated by syzkaller? That's the real problem, isn't it?

The real question becomes: Does syzkaller or QEMU's x86_64 setup even *support* Device Tree? Does x86 use ACPI instead? My concern is that these environments might lean towards ACPI for platform device description on x86-64, making this Device Tree driver essentially useless.

I need to quickly figure out if Device Tree is even an option for platform devices on x86, particularly amd64. So I'm going to look at the kernel configuration. I need to know if `CONFIG_OF` is enabled, and if so, whether it's actually usable for platform devices.

Let's check `CONFIG_OF` settings, specifically for x86. I need to determine if Device Tree is actually *a thing* on x86 at all. I will grep for `OF` within the `arch/x86/Kconfig` files. That should give me the answer.

{
  "Expression": "select OF",
  "PathPrefix": "arch/x86"
}

{
  "Output": "arch/x86/Kconfig=669=config X86_INTEL_CE\n--\narch/x86/Kconfig-676-\tselect X86_REBOOTFIXUPS\narch/x86/Kconfig:677:\tselect OF\narch/x86/Kconfig:678:\tselect OF_EARLY_FLATTREE\narch/x86/Kconfig-679-\thelp\n--\narch/x86/Kconfig=1509=config NUMA\n--\narch/x86/Kconfig-1513-\tselect USE_PERCPU_NUMA_NODE_ID\narch/x86/Kconfig:1514:\tselect OF_NUMA if OF\narch/x86/Kconfig-1515-\thelp\n--\narch/x86/Kconfig=2979=config OLPC\n--\narch/x86/Kconfig-2983-\tselect GPIOLIB_LEGACY\narch/x86/Kconfig:2984:\tselect OF\narch/x86/Kconfig:2985:\tselect OF_PROMTREE\narch/x86/Kconfig-2986-\tselect IRQ_DOMAIN\n"
}

							input: 30624
							output: 133
							thoughts: 2749

**Analysis of Xilinx AXI Ethernet Driver Reachability on amd64**

Okay, here's the breakdown. I'm looking at this `xilinx_axienet` driver and my immediate thought is, this is going to be a problem on `amd64`. Looking at the Kconfig, it's clear `OF` (Device Tree) is used for it, but not by default on standard amd64. Even if OF were somehow enabled, syzkaller doesn't do device tree injection, so that's out. Could it be bound via `sysfs bind`? Probably not.

The `axienet_driver` uses `.probe = axienet_probe`. Let's assume a platform device named "xaxienet" somehow gets created. The driver has a `.driver = { .name = DRIVER_NAME, .of_match_table = axienet_of_match }`, but no `id_table`, so it is clearly reliant on device tree binding.

Now, looking at `axienet_probe`, it needs I/O memory resource 0. User space creation won't provide this, and it *must* have `pdev->dev.of_node`. Crucially, it uses `of_property_read_u32` and `of_get_phy_mode` which will *immediately* fail with `-ENODEV` if `pdev->dev.of_node` is `NULL`.

Alright, let's see if QEMU even emulates this. QEMU has `xilinx_ethlite` and `xilinx_axienet`, but they're for MicroBlaze and Zynq (ARM). QEMU `x86_64` targets PC machine types like i440fx, q35, and microvm, none of which have Xilinx AXI Ethernet. This is an FPGA IP block connected via AXI bus on Xilinx platforms, completely unreachable on an x86_64 PC, because it's not a standard device. We would need a special PCIe FPGA card with a custom bridge.

Now, let's check the prompt guidelines. The key points are "Structurally unreachable hardware: Vendor-specific... drivers requiring physical ASIC/PCIe cards not emulated in standard QEMU" and "Code paths exclusive to architectures other than the target architecture." Bingo.

We are specifically on amd64, and the code clearly relies on hardware (AXI bus, Xilinx DMA) and device tree configurations not present on amd64.

Can `XILINX_AXI_EMAC` even be compiled? Yes, `HAS_IOMEM` is true on amd64, so it can be enabled. But can the driver *run*? No. No Xilinx AXI Ethernet or device tree on any standard QEMU x86_64 machines. ACPI, not Device Tree, boots amd64. The `axienet_probe` fails immediately. Those callbacks in the patch (`axienet_stop`, `axienet_dma_tx_cb`, `axienet_dma_rx_cb`, `axienet_init_dmaengine`) will *never* run.

The patch itself modifies network device operations. But `axienet_stop` is only called when stopping an existing `xilinx_axienet` net_device. The DMA callbacks are for the Xilinx AXI DMA engine.

This falls squarely under the "structurally unreachable hardware" and "code paths exclusive to architectures other than the target architecture" categories.

The conclusion is, this is not worth fuzzing. The code will never execute in a standard environment.

Therefore, `WorthFuzzing=false`. `EnableConfigs` and `FocusSymbols` are empty. The reasoning is: "The modified code is in the Xilinx AXI Ethernet driver which is an OF/Device Tree-based platform driver for Xilinx FPGA/SoC hardware (e.g., Zynq/MicroBlaze). It requires physical hardware or architecture-specific emulation not available in standard virtualized amd64 QEMU/GCE environments, making the driver structurally unreachable on amd64." There's no other driver in the codebase that can call this one.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The modified code belongs to the Xilinx AXI Ethernet driver (drivers/net/ethernet/xilinx/xilinx_axienet_main.c), an OF/Device Tree platform driver for Xilinx FPGA/SoC soft IP cores (such as Zynq or MicroBlaze). On the target architecture (amd64), this hardware cannot be probed or initialized in standard QEMU or GCE virtual environments, rendering the code structurally unreachable for fuzzing.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The modified code belongs to the Xilinx AXI Ethernet driver (drivers/net/ethernet/xilinx/xilinx_axienet_main.c), an OF/Device Tree platform driver for Xilinx FPGA/SoC soft IP cores (such as Zynq or MicroBlaze). On the target architecture (amd64), this hardware cannot be probed or initialized in standard QEMU or GCE virtual environments, rendering the code structurally unreachable for fuzzing.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

LLM Calls Summary:
Total Calls	Total Tokens	Avg Tokens	Total Duration (Seconds)	Avg Duration (Seconds)

Tool Calls Summary:
Total Calls	Total Duration (Seconds)	Avg Duration (Seconds)