AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/09/06 21:02	flow	patch-triage	0m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The patch updates Devicetree bindings documentation and adds MDIO bus clock frequency configuration support to the Realtek RTL838x/RTL839x/RTL930x/RTL931x MDIO controller driver (drivers/net/mdio/mdio-realtek-rtl9300.c). This driver is designed specifically for Realtek Otto MIPS switch SoCs (CONFIG_MACH_REALTEK_RTL), requires OF syscon parent nodes, suppresses manual driver binding via sysfs, and cannot be probed or executed in standard amd64 QEMU/GCE virtualization environments.", "WorthFuzzing": false }
1/1	2026/09/06 21:02	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit a87d01f2c8f5171ac540fcdf1e425d4a489eded5\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Sun Sep 6 21:02:22 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml\nindex 67e0b23a8470e..88502d017eedb 100644\n--- a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml\n+++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml\n@@ -56,6 +56,9 @@ patternProperties:\n reg:\n maxItems: 1\n \n+ clock-frequency:\n+ default: 2500000\n+\n required:\n - reg\n \n@@ -71,6 +74,43 @@ required:\n - compatible\n - reg\n \n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - realtek,rtl8380-mdio\n+ - realtek,rtl8381-mdio\n+ - realtek,rtl8382-mdio\n+ then:\n+ patternProperties:\n+ '^mdio-bus@[0-3]$':\n+ properties:\n+ clock-frequency:\n+ enum: [2500000, 10000000]\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - realtek,rtl8391-mdio\n+ - realtek,rtl8392-mdio\n+ - realtek,rtl8393-mdio\n+ - realtek,rtl9301-mdio\n+ - realtek,rtl9302b-mdio\n+ - realtek,rtl9302c-mdio\n+ - realtek,rtl9303-mdio\n+ - realtek,rtl9311-mdio\n+ - realtek,rtl9312-mdio\n+ - realtek,rtl9313-mdio\n+ then:\n+ patternProperties:\n+ '^mdio-bus@[0-3]$':\n+ properties:\n+ clock-frequency:\n+ enum: [1250000, 2500000, 5000000]\n+\n unevaluatedProperties: false\n \n examples:\ndiff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/mdio-realtek-rtl9300.c\nindex 11d078ef941cd..8edb0ba0bcdd1 100644\n--- a/drivers/net/mdio/mdio-realtek-rtl9300.c\n+++ b/drivers/net/mdio/mdio-realtek-rtl9300.c\n@@ -130,6 +130,7 @@\n #define RTL8380_NUM_PAGES\t\t\t4096\n #define RTL8380_NUM_PORTS\t\t\t28\n #define RTL8380_SMI_GLB_CTRL\t\t\t0xa100\n+#define RTL8380_SMI_FREQ_SEL\t\t\tBIT(1)\n #define RTL8380_SMI_PHY_PATCH_DONE\t\tBIT(15)\n #define RTL8380_SMI_ACCESS_PHY_CTRL_0\t\t0xa1b8\n #define RTL8380_SMI_ACCESS_PHY_CTRL_1\t\t0xa1bc\n@@ -169,12 +170,15 @@\n #define RTL8390_PHYREG_PORT_CTRL_LOW\t\t0x03e4\n #define RTL8390_PHYREG_PORT_CTRL_HIGH\t\t0x03e8\n #define RTL8390_SMI_PORT_POLLING_CTRL\t\t0x03fc\n+#define RTL8390_SMI_GLB_CTRL\t\t\t0x03f8\n+#define RTL8390_SMI_FREQ_SEL\t\t\tGENMASK(6, 5)\n \n #define RTL9300_NUM_BUSES\t\t\t4\n #define RTL9300_NUM_PAGES\t\t\t4096\n #define RTL9300_NUM_PORTS\t\t\t28\n #define RTL9300_SMI_GLB_CTRL\t\t\t0xca00\n #define RTL9300_GLB_CTRL_INTF_SEL(intf)\tBIT(16 + (intf))\n+#define RTL9300_SMI_FREQ_SEL(intf)\t\tGENMASK((intf) * 2 + 9, (intf) * 2 + 8)\n #define RTL9300_SMI_PORT0_15_POLLING_SEL\t0xca08\n #define RTL9300_SMI_ACCESS_PHY_CTRL_0\t\t0xcb70\n #define RTL9300_SMI_ACCESS_PHY_CTRL_1\t\t0xcb74\n@@ -196,6 +200,8 @@\n #define RTL9310_NUM_BUSES\t\t\t4\n #define RTL9310_NUM_PAGES\t\t\t8192\n #define RTL9310_NUM_PORTS\t\t\t56\n+#define RTL9310_SMI_GLB_CTRL0\t\t\t0x0cc0\n+#define RTL9310_SMI_FREQ_SEL(intf)\t\tGENMASK((intf) * 2 + 5, (intf) * 2 + 4)\n #define RTL9310_SMI_GLB_CTRL1\t\t\t0x0cbc\n #define RTL9310_SMI_GLB_FMT_SEL_C45(intf)\tBIT((intf) * 2 + 1)\n #define RTL9310_SMI_INDRT_ACCESS_CTRL_0\t\t0x0c00\n@@ -251,6 +257,7 @@ struct otto_emdio_priv {\n \tstruct regmap regmap;\n \tstruct mutex lock; / protect HW access /\n \tDECLARE_BITMAP(valid_ports, MAX_PORTS);\n+\tu32 global_freq;\n \tu16 page[MAX_PORTS];\n \tu8 smi_bus[MAX_PORTS];\n \tu8 smi_addr[MAX_PORTS];\n@@ -269,6 +276,7 @@ struct otto_emdio_info {\n \tu8 num_ports;\n \tu16 num_pages;\n \tu32 poll_ctrl;\n+\tint (set_bus_frequency)(struct mii_bus bus, u32 freq);\n \tint (setup_controller)(struct otto_emdio_priv priv);\n \tint (read_c22)(struct mii_bus bus, int port, int regnum, u32 value);\n \tint (read_c45)(struct mii_bus bus, int port, int dev_addr, int regnum, u32 value);\n@@ -740,6 +748,17 @@ static int otto_emdio_setup_topology(struct otto_emdio_priv priv)\n \treturn 0;\n }\n \n+static int otto_emdio_8380_set_bus_frequency(struct mii_bus bus, u32 freq)\n+{\n+\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\n+\n+\tif (freq != 2500000 \u0026\u0026 freq != 10000000)\n+\t\treturn -EINVAL;\n+\n+\treturn regmap_assign_bits(priv-\u003eregmap, RTL8380_SMI_GLB_CTRL,\n+\t\t\t\t RTL8380_SMI_FREQ_SEL, freq == 10000000);\n+}\n+\n static int otto_emdio_8380_setup_controller(struct otto_emdio_priv priv)\n {\n \t/\n@@ -749,6 +768,40 @@ static int otto_emdio_8380_setup_controller(struct otto_emdio_priv priv)\n \treturn regmap_set_bits(priv-\u003eregmap, RTL8380_SMI_GLB_CTRL, RTL8380_SMI_PHY_PATCH_DONE);\n }\n \n+static int otto_emdio_8390_set_bus_frequency(struct mii_bus bus, u32 freq)\n+{\n+\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\n+\tu32 val;\n+\tint err;\n+\n+\tif (freq != 1250000 \u0026\u0026 freq != 2500000 \u0026\u0026 freq != 5000000)\n+\t\treturn -EINVAL;\n+\tif (priv-\u003eglobal_freq)\n+\t\treturn freq == priv-\u003eglobal_freq ? 0 : -EINVAL;\n+\n+\tval = FIELD_PREP(RTL8390_SMI_FREQ_SEL, freq / 2500000);\n+\terr = regmap_update_bits(priv-\u003eregmap, RTL8390_SMI_GLB_CTRL, RTL8390_SMI_FREQ_SEL, val);\n+\tif (!err)\n+\t\tpriv-\u003eglobal_freq = freq;\n+\n+\treturn err;\n+}\n+\n+static int otto_emdio_9300_set_bus_frequency(struct mii_bus bus, u32 freq)\n+{\n+\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\n+\tstruct otto_emdio_chan chan = bus-\u003epriv;\n+\tu32 mask, val;\n+\n+\tif (freq != 1250000 \u0026\u0026 freq != 2500000 \u0026\u0026 freq != 5000000)\n+\t\treturn -EINVAL;\n+\n+\tmask = RTL9300_SMI_FREQ_SEL(chan-\u003emdio_bus);\n+\tval = field_prep(mask, freq / 2500000);\n+\n+\treturn regmap_update_bits(priv-\u003eregmap, RTL9300_SMI_GLB_CTRL, mask, val);\n+}\n+\n static int otto_emdio_9300_setup_controller(struct otto_emdio_priv priv)\n {\n \tu32 glb_ctrl_mask = 0, glb_ctrl_val = 0;\n@@ -769,6 +822,21 @@ static int otto_emdio_9300_setup_controller(struct otto_emdio_priv priv)\n \treturn 0;\n }\n \n+static int otto_emdio_9310_set_bus_frequency(struct mii_bus bus, u32 freq)\n+{\n+\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\n+\tstruct otto_emdio_chan chan = bus-\u003epriv;\n+\tu32 mask, val;\n+\n+\tif (freq != 1250000 \u0026\u0026 freq != 2500000 \u0026\u0026 freq != 5000000)\n+\t\treturn -EINVAL;\n+\n+\tmask = RTL9310_SMI_FREQ_SEL(chan-\u003emdio_bus);\n+\tval = field_prep(mask, freq / 2500000);\n+\n+\treturn regmap_update_bits(priv-\u003eregmap, RTL9310_SMI_GLB_CTRL0, mask, val);\n+}\n+\n static int otto_emdio_9310_setup_controller(struct otto_emdio_priv priv)\n {\n \tint i, err;\n@@ -831,14 +899,14 @@ static void otto_emdio_notify_phy_detach(struct phy_device phydev)\n }\n \n static int otto_emdio_probe_one(struct device dev, struct otto_emdio_priv priv,\n-\t\t\t\t struct fwnode_handle node)\n+\t\t\t\tstruct device_node node)\n {\n \tstruct otto_emdio_chan chan;\n \tstruct mii_bus bus;\n-\tu32 mdio_bus;\n+\tu32 mdio_bus, freq;\n \tint err;\n \n-\terr = fwnode_property_read_u32(node, \"reg\", \u0026mdio_bus);\n+\terr = of_property_read_u32(node, \"reg\", \u0026mdio_bus);\n \tif (err)\n \t\treturn dev_err_probe(dev, err, \"undefined smi bus number\\n\");\n \n@@ -865,7 +933,14 @@ static int otto_emdio_probe_one(struct device dev, struct otto_emdio_priv priv\n \n \tsnprintf(bus-\u003eid, MII_BUS_ID_SIZE, \"%s-%d\", dev_name(dev), mdio_bus);\n \n-\terr = devm_of_mdiobus_register(dev, bus, to_of_node(node));\n+\tif (of_property_read_u32(node, \"clock-frequency\", \u0026freq))\n+\t\tfreq = 2500000;\n+\terr = priv-\u003einfo-\u003eset_bus_frequency(bus, freq);\n+\tif (err)\n+\t\treturn dev_err_probe(dev, err, \"cannot set frequency %u for MDIO bus %d\\n\",\n+\t\t\t\t freq, mdio_bus);\n+\n+\terr = devm_of_mdiobus_register(dev, bus, node);\n \tif (err)\n \t\treturn dev_err_probe(dev, err, \"cannot register MDIO bus\\n\");\n \n@@ -1027,7 +1102,7 @@ static int otto_emdio_probe(struct platform_device pdev)\n \t\t\treturn dev_err_probe(dev, err, \"failed to setup MDIO bus controller\\n\");\n \t}\n \n-\tdevice_for_each_child_node_scoped(dev, child) {\n+\tfor_each_child_of_node_scoped(dev-\u003eof_node, child) {\n \t\terr = otto_emdio_probe_one(dev, priv, child);\n \t\tif (err)\n \t\t\treturn err;\n@@ -1051,6 +1126,7 @@ static const struct otto_emdio_info otto_emdio_8380_info = {\n \t.num_pages = RTL8380_NUM_PAGES,\n \t.num_ports = RTL8380_NUM_PORTS,\n \t.poll_ctrl = RTL8380_SMI_POLL_CTRL,\n+\t.set_bus_frequency = otto_emdio_8380_set_bus_frequency,\n \t.setup_controller = otto_emdio_8380_setup_controller,\n \t.read_c22 = otto_emdio_8380_read_c22,\n \t.read_c45 = otto_emdio_8380_read_c45,\n@@ -1075,6 +1151,7 @@ static const struct otto_emdio_info otto_emdio_8390_info = {\n \t.num_pages = RTL8390_NUM_PAGES,\n \t.num_ports = RTL8390_NUM_PORTS,\n \t.poll_ctrl = RTL8390_SMI_PORT_POLLING_CTRL,\n+\t.set_bus_frequency = otto_emdio_8390_set_bus_frequency,\n \t.read_c22 = otto_emdio_8390_read_c22,\n \t.read_c45 = otto_emdio_8390_read_c45,\n \t.write_c22 = otto_emdio_8390_write_c22,\n@@ -1097,6 +1174,7 @@ static const struct otto_emdio_info otto_emdio_9300_info = {\n \t.num_ports = RTL9300_NUM_PORTS,\n \t.num_pages = RTL9300_NUM_PAGES,\n \t.poll_ctrl = RTL9300_SMI_POLL_CTRL,\n+\t.set_bus_frequency = otto_emdio_9300_set_bus_frequency,\n \t.setup_controller = otto_emdio_9300_setup_controller,\n \t.read_c22 = otto_emdio_9300_read_c22,\n \t.read_c45 = otto_emdio_9300_read_c45,\n@@ -1123,6 +1201,7 @@ static const struct otto_emdio_info otto_emdio_9310_info = {\n \t.num_pages = RTL9310_NUM_PAGES,\n \t.num_ports = RTL9310_NUM_PORTS,\n \t.poll_ctrl = RTL9310_SMI_PORT_POLLING_CTRL,\n+\t.set_bus_frequency = otto_emdio_9310_set_bus_frequency,\n \t.setup_controller = otto_emdio_9310_setup_controller,\n \t.read_c22 = otto_emdio_9310_read_c22,\n \t.read_c45 = otto_emdio_9310_read_c45,\n" }
2/1	2026/09/06 21:02	agent	patch-evaluator	0m Model: core Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch updates Devicetree bindings documentation and adds MDIO bus clock frequency configuration support to the Realtek RTL838x/RTL839x/RTL930x/RTL931x MDIO controller driver (drivers/net/mdio/mdio-realtek-rtl9300.c). This driver is designed specifically for Realtek Otto MIPS switch SoCs (CONFIG_MACH_REALTEK_RTL), requires OF syscon parent nodes, suppresses manual driver binding via sysfs, and cannot be probed or executed in standard amd64 QEMU/GCE virtualization environments.", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer and security engineer. Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on internal assumptions. You must actively use your code access tools to inspect the actual source code, callers, and surrounding context. ================================================================================ 1. CORE TRIAGE PHILOSOPHY ================================================================================ The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs, and newly triggered assertions introduced by the patch series. - REACHABILITY IS THE PRIMARY GATE: Fuzzing can only discover bugs in code that can actually execute in standard virtualized environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap). If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed, regardless of whether it adds assertions or complex logic. - DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS: Patch authors routinely label changes as "cleanups", "refactorings", or state "No functional change intended". Do NOT take these claims at face value. Code refactorings that rearrange logic, introduce helper functions, or alter state management in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs. If reachable executable code is modified or refactored, it MUST be fuzzed. - NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED: When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON, VM_WARN_ON, BUG_ON, lockdep_assert) in reachable code paths, it enforces new or stricter invariants. Even if the author believes the invariant always holds, fuzzing is essential to verify whether an unusual sequence of operations can violate it. ================================================================================ 2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA) ================================================================================ Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories: - Non-kernel and non-executable changes: * Modifications to Documentation/, comments, or spelling fixes. * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/) that do not affect the compiled kernel image (vmlinux) or kernel modules. * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints that do not alter control flow or data structures. * Build system or Kconfig changes that do not alter compiled C logic. - Structurally unreachable hardware: * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU. - Unreachable execution paths: * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during physical PCI hot-unplug or manual sysfs driver unbinding. * Code paths exclusive to architectures other than the target architecture. ================================================================================ 3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA) ================================================================================ Return WorthFuzzing=true whenever the patch touches reachable executable code, including: - Core Subsystems: * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/), BPF, scheduler, core networking, VFS, or syscall handling. - Refactorings and Code Cleanups: * Any restructuring of reachable data structures, helper abstractions, or algorithm flows. - Runtime Assertions and Defensive Checks: * Any introduction or alteration of assertions (WARN_ON, VM_WARN_ON, BUG_ON, etc.) in reachable paths. - Reachable Drivers and Protocols: Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.). ================================================================================ 4. EXTRACTING FocusSymbols (PREVENTING DILUTION) ================================================================================ When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer: - AVOID UBIQUITOUS LIFECYCLE HOT-PATHS: Do NOT list generic, ubiquitous functions called by almost every program in the corpus (including, but not limited to: general memory allocators and deallocators, page fault and trap handlers, or core synchronization primitives; this is not an exhaustive list). Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused", which severely dilutes fuzzing effort away from the actual changes. - TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS: List functions that specifically implement the logic being added or altered, or direct API entrypoints for the subsystem feature under review. - HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h): Compiler-inlined static functions (such as static inlines in mm/.h or include/linux/.h) lack distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters. If the changes are primarily in static inline helpers, identify non-static, feature-specific caller functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers). ================================================================================ 5. IDENTIFYING EnableConfigs ================================================================================ Identify any specific CONFIG_ options required to properly compile and reach the modified code: - Inspect Kconfig files and #ifdef guards; do not make assumptions. - Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed. - Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: Target architecture: amd64 For your convenience, here is the diff of the changes: commit a87d01f2c8f5171ac540fcdf1e425d4a489eded5 Author: syz-cluster <triage@syzkaller.com> Date: Sun Sep 6 21:02:22 2026 +0000 syz-cluster: applied patch under review diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml index 67e0b23a8470e..88502d017eedb 100644 --- a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml @@ -56,6 +56,9 @@ patternProperties: reg: maxItems: 1 + clock-frequency: + default: 2500000 + required: - reg @@ -71,6 +74,43 @@ required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - realtek,rtl8380-mdio + - realtek,rtl8381-mdio + - realtek,rtl8382-mdio + then: + patternProperties: + '^mdio-bus@[0-3]$': + properties: + clock-frequency: + enum: [2500000, 10000000] + - if: + properties: + compatible: + contains: + enum: + - realtek,rtl8391-mdio + - realtek,rtl8392-mdio + - realtek,rtl8393-mdio + - realtek,rtl9301-mdio + - realtek,rtl9302b-mdio + - realtek,rtl9302c-mdio + - realtek,rtl9303-mdio + - realtek,rtl9311-mdio + - realtek,rtl9312-mdio + - realtek,rtl9313-mdio + then: + patternProperties: + '^mdio-bus@[0-3]$': + properties: + clock-frequency: + enum: [1250000, 2500000, 5000000] + unevaluatedProperties: false examples: diff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/mdio-realtek-rtl9300.c index 11d078ef941cd..8edb0ba0bcdd1 100644 --- a/drivers/net/mdio/mdio-realtek-rtl9300.c +++ b/drivers/net/mdio/mdio-realtek-rtl9300.c @@ -130,6 +130,7 @@ #define RTL8380_NUM_PAGES 4096 #define RTL8380_NUM_PORTS 28 #define RTL8380_SMI_GLB_CTRL 0xa100 +#define RTL8380_SMI_FREQ_SEL BIT(1) #define RTL8380_SMI_PHY_PATCH_DONE BIT(15) #define RTL8380_SMI_ACCESS_PHY_CTRL_0 0xa1b8 #define RTL8380_SMI_ACCESS_PHY_CTRL_1 0xa1bc @@ -169,12 +170,15 @@ #define RTL8390_PHYREG_PORT_CTRL_LOW 0x03e4 #define RTL8390_PHYREG_PORT_CTRL_HIGH 0x03e8 #define RTL8390_SMI_PORT_POLLING_CTRL 0x03fc +#define RTL8390_SMI_GLB_CTRL 0x03f8 +#define RTL8390_SMI_FREQ_SEL GENMASK(6, 5) #define RTL9300_NUM_BUSES 4 #define RTL9300_NUM_PAGES 4096 #define RTL9300_NUM_PORTS 28 #define RTL9300_SMI_GLB_CTRL 0xca00 #define RTL9300_GLB_CTRL_INTF_SEL(intf) BIT(16 + (intf)) +#define RTL9300_SMI_FREQ_SEL(intf) GENMASK((intf) * 2 + 9, (intf) * 2 + 8) #define RTL9300_SMI_PORT0_15_POLLING_SEL 0xca08 #define RTL9300_SMI_ACCESS_PHY_CTRL_0 0xcb70 #define RTL9300_SMI_ACCESS_PHY_CTRL_1 0xcb74 @@ -196,6 +200,8 @@ #define RTL9310_NUM_BUSES 4 #define RTL9310_NUM_PAGES 8192 #define RTL9310_NUM_PORTS 56 +#define RTL9310_SMI_GLB_CTRL0 0x0cc0 +#define RTL9310_SMI_FREQ_SEL(intf) GENMASK((intf) * 2 + 5, (intf) * 2 + 4) #define RTL9310_SMI_GLB_CTRL1 0x0cbc #define RTL9310_SMI_GLB_FMT_SEL_C45(intf) BIT((intf) * 2 + 1) #define RTL9310_SMI_INDRT_ACCESS_CTRL_0 0x0c00 @@ -251,6 +257,7 @@ struct otto_emdio_priv { struct regmap regmap; struct mutex lock; / protect HW access / DECLARE_BITMAP(valid_ports, MAX_PORTS); + u32 global_freq; u16 page[MAX_PORTS]; u8 smi_bus[MAX_PORTS]; u8 smi_addr[MAX_PORTS]; @@ -269,6 +276,7 @@ struct otto_emdio_info { u8 num_ports; u16 num_pages; u32 poll_ctrl; + int (set_bus_frequency)(struct mii_bus bus, u32 freq); int (setup_controller)(struct otto_emdio_priv priv); int (read_c22)(struct mii_bus bus, int port, int regnum, u32 value); int (read_c45)(struct mii_bus bus, int port, int dev_addr, int regnum, u32 value); @@ -740,6 +748,17 @@ static int otto_emdio_setup_topology(struct otto_emdio_priv priv) return 0; } +static int otto_emdio_8380_set_bus_frequency(struct mii_bus bus, u32 freq) +{ + struct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus); + + if (freq != 2500000 && freq != 10000000) + return -EINVAL; + + return regmap_assign_bits(priv->regmap, RTL8380_SMI_GLB_CTRL, + RTL8380_SMI_FREQ_SEL, freq == 10000000); +} + static int otto_emdio_8380_setup_controller(struct otto_emdio_priv priv) { / @@ -749,6 +768,40 @@ static int otto_emdio_8380_setup_controller(struct otto_emdio_priv priv) return regmap_set_bits(priv->regmap, RTL8380_SMI_GLB_CTRL, RTL8380_SMI_PHY_PATCH_DONE); } +static int otto_emdio_8390_set_bus_frequency(struct mii_bus bus, u32 freq) +{ + struct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus); + u32 val; + int err; + + if (freq != 1250000 && freq != 2500000 && freq != 5000000) + return -EINVAL; + if (priv->global_freq) + return freq == priv->global_freq ? 0 : -EINVAL; + + val = FIELD_PREP(RTL8390_SMI_FREQ_SEL, freq / 2500000); + err = regmap_update_bits(priv->regmap, RTL8390_SMI_GLB_CTRL, RTL8390_SMI_FREQ_SEL, val); + if (!err) + priv->global_freq = freq; + + return err; +} + +static int otto_emdio_9300_set_bus_frequency(struct mii_bus bus, u32 freq) +{ + struct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus); + struct otto_emdio_chan chan = bus->priv; + u32 mask, val; + + if (freq != 1250000 && freq != 2500000 && freq != 5000000) + return -EINVAL; + + mask = RTL9300_SMI_FREQ_SEL(chan->mdio_bus); + val = field_prep(mask, freq / 2500000); + + return regmap_update_bits(priv->regmap, RTL9300_SMI_GLB_CTRL, mask, val); +} + static int otto_emdio_9300_setup_controller(struct otto_emdio_priv priv) { u32 glb_ctrl_mask = 0, glb_ctrl_val = 0; @@ -769,6 +822,21 @@ static int otto_emdio_9300_setup_controller(struct otto_emdio_priv priv) return 0; } +static int otto_emdio_9310_set_bus_frequency(struct mii_bus bus, u32 freq) +{ + struct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus); + struct otto_emdio_chan chan = bus->priv; + u32 mask, val; + + if (freq != 1250000 && freq != 2500000 && freq != 5000000) + return -EINVAL; + + mask = RTL9310_SMI_FREQ_SEL(chan->mdio_bus); + val = field_prep(mask, freq / 2500000); + + return regmap_update_bits(priv->regmap, RTL9310_SMI_GLB_CTRL0, mask, val); +} + static int otto_emdio_9310_setup_controller(struct otto_emdio_priv priv) { int i, err; @@ -831,14 +899,14 @@ static void otto_emdio_notify_phy_detach(struct phy_device phydev) } static int otto_emdio_probe_one(struct device dev, struct otto_emdio_priv priv, - struct fwnode_handle node) + struct device_node node) { struct otto_emdio_chan chan; struct mii_bus bus; - u32 mdio_bus; + u32 mdio_bus, freq; int err; - err = fwnode_property_read_u32(node, "reg", &mdio_bus); + err = of_property_read_u32(node, "reg", &mdio_bus); if (err) return dev_err_probe(dev, err, "undefined smi bus number\n"); @@ -865,7 +933,14 @@ static int otto_emdio_probe_one(struct device dev, struct otto_emdio_priv priv snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", dev_name(dev), mdio_bus); - err = devm_of_mdiobus_register(dev, bus, to_of_node(node)); + if (of_property_read_u32(node, "clock-frequency", &freq)) + freq = 2500000; + err = priv->info->set_bus_frequency(bus, freq); + if (err) + return dev_err_probe(dev, err, "cannot set frequency %u for MDIO bus %d\n", + freq, mdio_bus); + + err = devm_of_mdiobus_register(dev, bus, node); if (err) return dev_err_probe(dev, err, "cannot register MDIO bus\n"); @@ -1027,7 +1102,7 @@ static int otto_emdio_probe(struct platform_device pdev) return dev_err_probe(dev, err, "failed to setup MDIO bus controller\n"); } - device_for_each_child_node_scoped(dev, child) { + for_each_child_of_node_scoped(dev->of_node, child) { err = otto_emdio_probe_one(dev, priv, child); if (err) return err; @@ -1051,6 +1126,7 @@ static const struct otto_emdio_info otto_emdio_8380_info = { .num_pages = RTL8380_NUM_PAGES, .num_ports = RTL8380_NUM_PORTS, .poll_ctrl = RTL8380_SMI_POLL_CTRL, + .set_bus_frequency = otto_emdio_8380_set_bus_frequency, .setup_controller = otto_emdio_8380_setup_controller, .read_c22 = otto_emdio_8380_read_c22, .read_c45 = otto_emdio_8380_read_c45, @@ -1075,6 +1151,7 @@ static const struct otto_emdio_info otto_emdio_8390_info = { .num_pages = RTL8390_NUM_PAGES, .num_ports = RTL8390_NUM_PORTS, .poll_ctrl = RTL8390_SMI_PORT_POLLING_CTRL, + .set_bus_frequency = otto_emdio_8390_set_bus_frequency, .read_c22 = otto_emdio_8390_read_c22, .read_c45 = otto_emdio_8390_read_c45, .write_c22 = otto_emdio_8390_write_c22, @@ -1097,6 +1174,7 @@ static const struct otto_emdio_info otto_emdio_9300_info = { .num_ports = RTL9300_NUM_PORTS, .num_pages = RTL9300_NUM_PAGES, .poll_ctrl = RTL9300_SMI_POLL_CTRL, + .set_bus_frequency = otto_emdio_9300_set_bus_frequency, .setup_controller = otto_emdio_9300_setup_controller, .read_c22 = otto_emdio_9300_read_c22, .read_c45 = otto_emdio_9300_read_c45, @@ -1123,6 +1201,7 @@ static const struct otto_emdio_info otto_emdio_9310_info = { .num_pages = RTL9310_NUM_PAGES, .num_ports = RTL9310_NUM_PORTS, .poll_ctrl = RTL9310_SMI_PORT_POLLING_CTRL, + .set_bus_frequency = otto_emdio_9310_set_bus_frequency, .setup_controller = otto_emdio_9310_setup_controller, .read_c22 = otto_emdio_9310_read_c22, .read_c45 = otto_emdio_9310_read_c45,
3/2	2026/09/06 21:02	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 7090 output: 39 thoughts: 131 Thoughts: Analyzing the Patch for Fuzzing Potential Okay, let's dive into this. My initial assessment hinges on whether this patch presents a compelling case for fuzzing, so I need to weigh the potential attack surface. Let's start by breaking down the patch's components. First, I see the modifications involve two files: `Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml` and `drivers/net/mdio/mdio-realtek-rtl9300.c`. The YAML file typically indicates changes to Device Tree bindings, which could involve subtle logic changes influencing device configuration or data interpretation – worth noting, but not necessarily a fuzzing gold mine on its own. Now, the `mdio-realtek-rtl9300.c` file is where things get interesting. I need to understand what this driver does. I'm going to quickly check its Kconfig entry. I need to get a clear picture of the driver's role. Is it a core network interface driver? Does it interact with hardware in a way that handles external data? Is it targeted at a particular architecture or hardware component? That's going to inform me whether it's worth the time to even probe the surface for fuzzing opportunities. The probing/instantiation method is also crucial - how the driver initializes, receives data, and sets up communication channels provides great indicators as to where and how fuzzing can be effective.
4/2	2026/09/06 21:02	tool	grepper	0m Args: { "Expression": "MDIO_REALTEK_RTL9300", "PathPrefix": "drivers/net/mdio" } Results: { "Output": "drivers/net/mdio/Kconfig=166=config MDIO_IPQ8064\n--\ndrivers/net/mdio/Kconfig-173-\ndrivers/net/mdio/Kconfig:174:config MDIO_REALTEK_RTL9300\ndrivers/net/mdio/Kconfig-175-\ttristate \"Realtek RTL83xx/RTL93xx MDIO interface support\"\n--\ndrivers/net/mdio/Makefile=23=obj-$(CONFIG_MDIO_PIC64HPSC)\t\t+= mdio-pic64hpsc.o\ndrivers/net/mdio/Makefile:24:obj-$(CONFIG_MDIO_REALTEK_RTL9300)\t+= mdio-realtek-rtl9300.o\ndrivers/net/mdio/Makefile-25-obj-$(CONFIG_MDIO_REGMAP)\t\t+= mdio-regmap.o\n" }
5/2	2026/09/06 21:02	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 7817 output: 37 thoughts: 22 Thoughts: Here's my attempt at summarizing the thought process, tailored for an expert audience and written in the first person: Analyzing the MDIO_REALTEK_RTL9300 Kconfig Okay, so I'm diving into the Kconfig for the MDIO_REALTEK_RTL9300 driver. My initial goal is to understand how this specific hardware support is configured within the broader build system. What are the key dependencies? What options are exposed to the user, and how granular are they? I’m looking for the essential knobs, the ones that truly matter. For example, are there optional features controlled by tristates or just bools? What are the implications of enabling this driver -- which dependencies will I pull in and is this driver required for other core functionalities? Are there any potentially problematic defaults that I need to be aware of? I'll be checking if the driver's configuration is clean or if it needs improvement. Understanding the configuration options gives me insight into the driver's capabilities and its suitability for different use cases. Ultimately, I need to know the implications of enabling this driver in my system configuration, both in terms of code footprint and potential conflicts with other modules.
6/2	2026/09/06 21:02	tool	read-file	0m Args: { "File": "drivers/net/mdio/Kconfig", "FirstLine": 170, "LineCount": 25 } Results: { "Contents": " 170:\t\thelp\n 171:\t\t This driver supports the MDIO interface found in the network\n 172:\t\t interface units of the IPQ8064 SoC\n 173:\t\n 174:\tconfig MDIO_REALTEK_RTL9300\n 175:\t\ttristate \"Realtek RTL83xx/RTL93xx MDIO interface support\"\n 176:\t\tdepends on MACH_REALTEK_RTL \|\| COMPILE_TEST\n 177:\t\thelp\n 178:\t\t This driver supports the MDIO interface found in the Realtek\n 179:\t\t RTL83xx/RTL93xx family of Ethernet switches with integrated SoC.\n 180:\t\n 181:\tconfig MDIO_REGMAP\n 182:\t\ttristate\n 183:\t\thelp\n 184:\t\t This driver allows using MDIO devices that are not sitting on a\n 185:\t\t regular MDIO bus, but still exposes the standard 802.3 register\n 186:\t\t layout. It's regmap-based so that it can be used on integrated,\n 187:\t\t memory-mapped PHYs, SPI PHYs and so on. A new virtual MDIO bus is\n 188:\t\t created, and its read/write operations are mapped to the underlying\n 189:\t\t regmap. Users willing to use this driver must explicitly select\n 190:\t\t REGMAP.\n 191:\t\n 192:\tconfig MDIO_THUNDER\n 193:\t\ttristate \"ThunderX SOCs MDIO buses\"\n 194:\t\tdepends on 64BIT\n" }
7/2	2026/09/06 21:02	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 8564 output: 45 thoughts: 83 Thoughts: Analyzing the mdio-realtek-rtl9300.c Driver Okay, let's dive into this `mdio-realtek-rtl9300.c` driver. I need to understand its probing mechanism. First, I'll identify the bus it's tied to. Then, I need to figure out if this is strictly a platform driver, specifically for that Realtek MIPS SoC, the `MACH_REALTEK_RTL` architecture, or if there's some device tree (DT) overlay configuration or alternative approach that allows it to be accessed via other configurations. Essentially, I need to get the big picture of this driver and how it's integrated. Let's start with a thorough review of the `mdio-realtek-rtl9300.c` file itself.
8/2	2026/09/06 21:02	tool	grepper	0m Args: { "Expression": "otto_emdio_", "PathPrefix": "drivers/net/mdio/mdio-realtek-rtl9300.c" } Results: { "Output": "drivers/net/mdio/mdio-realtek-rtl9300.c-243-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:244:struct otto_emdio_cmd_regs {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-245-\tu32 c22_data;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-254-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:255:struct otto_emdio_priv {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:256:\tconst struct otto_emdio_info info;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-257-\tstruct regmap regmap;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-267-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:268:struct otto_emdio_info {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-269-\tu32 addr_map_base;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-273-\tu32 cmd_write;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:274:\tstruct otto_emdio_cmd_regs cmd_regs;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-275-\tu8 num_buses;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-279-\tint (set_bus_frequency)(struct mii_bus bus, u32 freq);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:280:\tint (setup_controller)(struct otto_emdio_priv priv);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-281-\tint (read_c22)(struct mii_bus bus, int port, int regnum, u32 value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-286-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:287:struct otto_emdio_chan {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:288:\tstruct otto_emdio_priv priv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-289-\tu8 mdio_bus;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-291-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:292:static int otto_emdio_phy_to_port(struct mii_bus bus, int phy_id)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-293-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:294:\tstruct otto_emdio_chan chan = bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:295:\tstruct otto_emdio_priv priv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-296-\tint i;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-307-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:308:static struct otto_emdio_priv otto_emdio_bus_to_priv(struct mii_bus bus)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-309-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:310:\tstruct otto_emdio_chan chan = bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-311-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-314-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:315:static int otto_emdio_set_port_polling(struct otto_emdio_priv priv, int port, bool active)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-316-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-320-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:321:static int otto_emdio_run_cmd(struct mii_bus bus, u32 cmd,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:322:\t\t\t struct otto_emdio_cmd_regs cmd_data)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-323-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:324:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:325:\tconst struct otto_emdio_info info = priv-\u003einfo;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-326-\tu32 cmdstate;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-377-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:378:static int otto_emdio_read_cmd(struct mii_bus bus, u32 cmd,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:379:\t\t\t struct otto_emdio_cmd_regs cmd_data, u32 mask, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-380-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:381:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-382-\tint ret;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-384-\tlockdep_assert_held(\u0026priv-\u003elock);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:385:\tret = otto_emdio_run_cmd(bus, cmd \| priv-\u003einfo-\u003ecmd_read, cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-386-\tif (ret)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-397-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:398:static int otto_emdio_write_cmd(struct mii_bus bus, u32 cmd,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:399:\t\t\t\tstruct otto_emdio_cmd_regs cmd_data)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-400-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:401:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-402-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-404-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:405:\treturn otto_emdio_run_cmd(bus, cmd \| priv-\u003einfo-\u003ecmd_write, cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-406-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-407-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:408:static int otto_emdio_8380_read_c22(struct mii_bus bus, int port, int regnum, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-409-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:410:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:411:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-412-\t\t.c22_data\t= FIELD_PREP(RTL8380_PHY_CTRL_REG_ADDR, regnum) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-417-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:418:\treturn otto_emdio_read_cmd(bus, RTL8380_PHY_CTRL_TYPE_C22, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-419-\t\t\t\t RTL8380_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-421-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:422:static int otto_emdio_8380_write_c22(struct mii_bus bus, int port, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-423-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:424:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:425:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-426-\t\t.c22_data\t= FIELD_PREP(RTL8380_PHY_CTRL_REG_ADDR, regnum) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-432-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:433:\treturn otto_emdio_write_cmd(bus, RTL8380_PHY_CTRL_TYPE_C22, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-434-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-435-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:436:static int otto_emdio_8380_read_c45(struct mii_bus bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-437-\t\t\t\t int dev_addr, int regnum, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-438-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:439:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-440-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-444-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:445:\treturn otto_emdio_read_cmd(bus, RTL8380_PHY_CTRL_TYPE_C45, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-446-\t\t\t\t RTL8380_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-448-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:449:static int otto_emdio_8380_write_c45(struct mii_bus bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-450-\t\t\t\t int dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-451-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:452:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-453-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-458-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:459:\treturn otto_emdio_write_cmd(bus, RTL8380_PHY_CTRL_TYPE_C45, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-460-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-461-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:462:static int otto_emdio_8390_read_c22(struct mii_bus bus, int port, int regnum, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-463-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:464:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:465:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-466-\t\t.c22_data\t= FIELD_PREP(RTL8390_PHY_CTRL_REG_ADDR, regnum) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-471-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:472:\treturn otto_emdio_read_cmd(bus, RTL8390_PHY_CTRL_TYPE_C22, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-473-\t\t\t\t RTL8390_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-475-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:476:static int otto_emdio_8390_write_c22(struct mii_bus bus, int port, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-477-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:478:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:479:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-480-\t\t.c22_data\t= FIELD_PREP(RTL8390_PHY_CTRL_REG_ADDR, regnum) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-487-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:488:\treturn otto_emdio_write_cmd(bus, RTL8390_PHY_CTRL_TYPE_C22, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-489-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-490-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:491:static int otto_emdio_8390_read_c45(struct mii_bus bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-492-\t\t\t\t int dev_addr, int regnum, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-493-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:494:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-495-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-499-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:500:\treturn otto_emdio_read_cmd(bus, RTL8390_PHY_CTRL_TYPE_C45, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-501-\t\t\t\t RTL8390_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-503-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:504:static int otto_emdio_8390_write_c45(struct mii_bus bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-505-\t\t\t\t int dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-506-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:507:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-508-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-514-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:515:\treturn otto_emdio_write_cmd(bus, RTL8390_PHY_CTRL_TYPE_C45, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-516-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-517-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:518:static int otto_emdio_9300_read_c22(struct mii_bus bus, int port, int regnum, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-519-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:520:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:521:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-522-\t\t.c22_data\t= FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-527-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:528:\treturn otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-529-\t\t\t\t RTL9300_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-531-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:532:static int otto_emdio_9300_write_c22(struct mii_bus bus, int port, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-533-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:534:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:535:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-536-\t\t.c22_data\t= FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-542-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:543:\treturn otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-544-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-545-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:546:static int otto_emdio_9300_read_c45(struct mii_bus bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-547-\t\t\t\t int dev_addr, int regnum, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-548-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:549:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-550-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-554-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:555:\treturn otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-556-\t\t\t\t RTL9300_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-558-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:559:static int otto_emdio_9300_write_c45(struct mii_bus bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-560-\t\t\t\t int dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-561-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:562:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-563-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-568-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:569:\treturn otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-570-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-571-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:572:static int otto_emdio_9310_read_c22(struct mii_bus bus, int port, int regnum, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-573-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:574:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:575:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-576-\t\t.broadcast\t= FIELD_PREP(RTL9310_BC_PORT_ID, port),\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-580-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:581:\treturn otto_emdio_read_cmd(bus, RTL9310_PHY_CTRL_TYPE_C22, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-582-\t\t\t\t RTL9310_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-584-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:585:static int otto_emdio_9310_write_c22(struct mii_bus bus, int port, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-586-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:587:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:588:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-589-\t\t.c22_data\t= FIELD_PREP(RTL9310_PHY_CTRL_REG_ADDR, regnum) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-595-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:596:\treturn otto_emdio_write_cmd(bus, RTL9310_PHY_CTRL_TYPE_C22, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-597-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-598-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:599:static int otto_emdio_9310_read_c45(struct mii_bus bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-600-\t\t\t\t int dev_addr, int regnum, u32 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-601-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:602:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-603-\t\t.broadcast\t= FIELD_PREP(RTL9310_BC_PORT_ID, port),\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-607-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:608:\treturn otto_emdio_read_cmd(bus, RTL9310_PHY_CTRL_TYPE_C45, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-609-\t\t\t\t RTL9310_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-611-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:612:static int otto_emdio_9310_write_c45(struct mii_bus bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-613-\t\t\t\t int dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-614-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:615:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-616-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) \|\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-622-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:623:\treturn otto_emdio_write_cmd(bus, RTL9310_PHY_CTRL_TYPE_C45, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-624-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-625-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:626:static int otto_emdio_read_c22(struct mii_bus bus, int phy_id, int regnum)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-627-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:628:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-629-\tint ret, port;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-637-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:638:\tport = otto_emdio_phy_to_port(bus, phy_id);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-639-\tif (port \u003c 0)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-651-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:652:static int otto_emdio_write_c22(struct mii_bus bus, int phy_id, int regnum,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-653-\t\t\t\tu16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-654-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:655:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-656-\tint ret, port;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-663-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:664:\tport = otto_emdio_phy_to_port(bus, phy_id);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-665-\tif (port \u003c 0)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-682-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:683:static int otto_emdio_read_c45(struct mii_bus bus, int phy_id, int dev_addr, int regnum)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-684-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:685:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-686-\tint ret, port;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-688-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:689:\tport = otto_emdio_phy_to_port(bus, phy_id);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-690-\tif (port \u003c 0)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-698-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:699:static int otto_emdio_write_c45(struct mii_bus bus, int phy_id,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-700-\t\t\t\tint dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-701-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:702:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-703-\tint ret, port;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-704-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:705:\tport = otto_emdio_phy_to_port(bus, phy_id);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-706-\tif (port \u003c 0)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-714-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:715:static int otto_emdio_write_mapping(struct otto_emdio_priv priv, u32 base, u32 port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-716-\t\t\t\t u32 vals_per_reg, u32 bits_per_val, u32 value)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-724-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:725:static int otto_emdio_setup_topology(struct otto_emdio_priv priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-726-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:727:\tconst struct otto_emdio_info info = priv-\u003einfo;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-728-\tu32 port;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-732-\t\tif (info-\u003ebus_map_base) {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:733:\t\t\tret = otto_emdio_write_mapping(priv, info-\u003ebus_map_base, port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-734-\t\t\t\t\t\t MAP_BUSES_PER_REG, MAP_BITS_PER_BUS,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-739-\t\tif (info-\u003eaddr_map_base) {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:740:\t\t\tret = otto_emdio_write_mapping(priv, info-\u003eaddr_map_base, port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-741-\t\t\t\t\t\t MAP_ADDRS_PER_REG, MAP_BITS_PER_ADDR,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-750-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:751:static int otto_emdio_8380_set_bus_frequency(struct mii_bus bus, u32 freq)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-752-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:753:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-754-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-761-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:762:static int otto_emdio_8380_setup_controller(struct otto_emdio_priv priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-763-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-770-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:771:static int otto_emdio_8390_set_bus_frequency(struct mii_bus bus, u32 freq)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-772-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:773:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-774-\tu32 val;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-789-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:790:static int otto_emdio_9300_set_bus_frequency(struct mii_bus bus, u32 freq)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-791-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:792:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:793:\tstruct otto_emdio_chan chan = bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-794-\tu32 mask, val;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-804-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:805:static int otto_emdio_9300_setup_controller(struct otto_emdio_priv priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-806-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-824-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:825:static int otto_emdio_9310_set_bus_frequency(struct mii_bus bus, u32 freq)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-826-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:827:\tstruct otto_emdio_priv priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:828:\tstruct otto_emdio_chan chan = bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-829-\tu32 mask, val;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-839-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:840:static int otto_emdio_9310_setup_controller(struct otto_emdio_priv priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-841-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-855-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:856:static int otto_emdio_notify_phy_attach(struct phy_device phydev)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-857-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:858:\tint port = otto_emdio_phy_to_port(phydev-\u003emdio.bus, phydev-\u003emdio.addr);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:859:\tstruct otto_emdio_chan chan = phydev-\u003emdio.bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:860:\tstruct otto_emdio_priv priv = chan-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-861-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-877-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:878:\treturn otto_emdio_set_port_polling(priv, port, true);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-879-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-880-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:881:static void otto_emdio_notify_phy_detach(struct phy_device phydev)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-882-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c-883-\tstruct mii_bus bus = phydev-\u003emdio.bus;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:884:\tstruct otto_emdio_priv priv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-885-\tint port;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-886-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:887:\tpriv = otto_emdio_bus_to_priv(phydev-\u003emdio.bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:888:\tport = otto_emdio_phy_to_port(phydev-\u003emdio.bus, phydev-\u003emdio.addr);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-889-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-896-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:897:\tif (otto_emdio_set_port_polling(priv, port, false))\ndrivers/net/mdio/mdio-realtek-rtl9300.c-898-\t\tdev_err(bus-\u003eparent, \"failed to disable polling for port %d\\n\", port);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-900-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:901:static int otto_emdio_probe_one(struct device dev, struct otto_emdio_priv priv,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-902-\t\t\t\tstruct device_node node)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-903-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:904:\tstruct otto_emdio_chan chan;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-905-\tstruct mii_bus bus;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-921-\tbus-\u003ename = \"Realtek Switch MDIO Bus\";\ndrivers/net/mdio/mdio-realtek-rtl9300.c:922:\tbus-\u003eread_c45 = otto_emdio_read_c45;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:923:\tbus-\u003ewrite_c45 = otto_emdio_write_c45;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:924:\tbus-\u003eread = otto_emdio_read_c22;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:925:\tbus-\u003ewrite = otto_emdio_write_c22;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-926-\tbus-\u003eparent = dev;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:927:\tbus-\u003enotify_phy_attach = otto_emdio_notify_phy_attach;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:928:\tbus-\u003enotify_phy_detach = otto_emdio_notify_phy_detach;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-929-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-949-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:950:static struct device_node otto_emdio_get_bus_node(struct device_node dn)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-951-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-968- /\ndrivers/net/mdio/mdio-realtek-rtl9300.c:969:static int otto_emdio_map_ports(struct device dev)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-970-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c-971-\tstruct device_node ports_dn, phy_dn, bus_dn, ctrl_dn;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:972:\tstruct otto_emdio_priv priv = dev_get_drvdata(dev);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-973-\tstruct device parent = dev-\u003eparent;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-989-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:990:\t\tbus_dn = otto_emdio_get_bus_node(phy_dn);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-991-\t\tif (!bus_dn)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1052-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1053:static int otto_emdio_init_polling(struct otto_emdio_priv priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1054-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1057-\tfor (int port = 0; port \u003c priv-\u003einfo-\u003enum_ports; port++) {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1058:\t\terr = otto_emdio_set_port_polling(priv, port, false);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1059-\t\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1065-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1066:static int otto_emdio_probe(struct platform_device pdev)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1067-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1068-\tstruct device dev = \u0026pdev-\u003edev;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1069:\tstruct otto_emdio_priv *priv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1070-\tint err;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1084-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1085:\terr = otto_emdio_init_polling(priv);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1086-\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1090-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1091:\terr = otto_emdio_map_ports(dev);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1092-\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1094-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1095:\terr = otto_emdio_setup_topology(priv);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1096-\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1105-\tfor_each_child_of_node_scoped(dev-\u003eof_node, child) {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1106:\t\terr = otto_emdio_probe_one(dev, priv, child);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1107-\t\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1113-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1114:static const struct otto_emdio_info otto_emdio_8380_info = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1115-\t.addr_map_base = RTL8380_SMI_PORT0_5_ADDR_CTRL,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1128-\t.poll_ctrl = RTL8380_SMI_POLL_CTRL,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1129:\t.set_bus_frequency = otto_emdio_8380_set_bus_frequency,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1130:\t.setup_controller = otto_emdio_8380_setup_controller,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1131:\t.read_c22 = otto_emdio_8380_read_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1132:\t.read_c45 = otto_emdio_8380_read_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1133:\t.write_c22 = otto_emdio_8380_write_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1134:\t.write_c45 = otto_emdio_8380_write_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1135-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1136-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1137:static const struct otto_emdio_info otto_emdio_8390_info = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1138-\t.cmd_fail = RTL8390_PHY_CTRL_FAIL,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1153-\t.poll_ctrl = RTL8390_SMI_PORT_POLLING_CTRL,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1154:\t.set_bus_frequency = otto_emdio_8390_set_bus_frequency,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1155:\t.read_c22 = otto_emdio_8390_read_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1156:\t.read_c45 = otto_emdio_8390_read_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1157:\t.write_c22 = otto_emdio_8390_write_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1158:\t.write_c45 = otto_emdio_8390_write_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1159-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1160-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1161:static const struct otto_emdio_info otto_emdio_9300_info = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1162-\t.addr_map_base = RTL9300_SMI_PORT0_5_ADDR_CTRL,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1176-\t.poll_ctrl = RTL9300_SMI_POLL_CTRL,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1177:\t.set_bus_frequency = otto_emdio_9300_set_bus_frequency,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1178:\t.setup_controller = otto_emdio_9300_setup_controller,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1179:\t.read_c22 = otto_emdio_9300_read_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1180:\t.read_c45 = otto_emdio_9300_read_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1181:\t.write_c22 = otto_emdio_9300_write_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1182:\t.write_c45 = otto_emdio_9300_write_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1183-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1184-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1185:static const struct otto_emdio_info otto_emdio_9310_info = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1186-\t.addr_map_base = RTL9310_SMI_PORT_ADDR_CTRL,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1203-\t.poll_ctrl = RTL9310_SMI_PORT_POLLING_CTRL,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1204:\t.set_bus_frequency = otto_emdio_9310_set_bus_frequency,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1205:\t.setup_controller = otto_emdio_9310_setup_controller,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1206:\t.read_c22 = otto_emdio_9310_read_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1207:\t.read_c45 = otto_emdio_9310_read_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1208:\t.write_c22 = otto_emdio_9310_write_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1209:\t.write_c45 = otto_emdio_9310_write_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1210-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1211-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1212:static const struct of_device_id otto_emdio_ids[] = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1213:\t{ .compatible = \"realtek,rtl8380-mdio\", .data = \u0026otto_emdio_8380_info },\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1214:\t{ .compatible = \"realtek,rtl8391-mdio\", .data = \u0026otto_emdio_8390_info },\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1215:\t{ .compatible = \"realtek,rtl9301-mdio\", .data = \u0026otto_emdio_9300_info },\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1216:\t{ .compatible = \"realtek,rtl9311-mdio\", .data = \u0026otto_emdio_9310_info },\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1217-\t{}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1218-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1219:MODULE_DEVICE_TABLE(of, otto_emdio_ids);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1220-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1221:static struct platform_driver otto_emdio_driver = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1222:\t.probe = otto_emdio_probe,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1223-\t.driver = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1224-\t\t.name = \"mdio-rtl9300\",\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1225:\t\t.of_match_table = otto_emdio_ids,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1226-\t\t.suppress_bind_attrs = true,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1229-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1230:module_platform_driver(otto_emdio_driver);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1231-\n" }
9/2	2026/09/06 21:02	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 25647 output: 49 thoughts: 60 Thoughts: Diving into the Realtek RTL9300 MDIO Driver Probe Alright, let's get down to brass tacks. I need to refresh my memory on the `mdio-realtek-rtl9300.c` driver, specifically the probe function and how it handles the regmap and parent device setup. I know the general architecture, but I need a refresher on the implementation details. Time to go back and check the code. Okay, let's jump straight to lines 1065 through 1115. That's where the heart of the probe is likely located, the core device initialization. I'll be looking for how the regmap is created and initialized, how the parent device is assigned, and any specific initialization sequences for this Realtek switch. Gotta make sure everything is in order.
10/2	2026/09/06 21:02	tool	read-file	0m Args: { "File": "drivers/net/mdio/mdio-realtek-rtl9300.c", "FirstLine": 1065, "LineCount": 55 } Results: { "Contents": "1065:\t\n1066:\tstatic int otto_emdio_probe(struct platform_device pdev)\n1067:\t{\n1068:\t\tstruct device dev = \u0026pdev-\u003edev;\n1069:\t\tstruct otto_emdio_priv priv;\n1070:\t\tint err;\n1071:\t\n1072:\t\tpriv = devm_kzalloc(dev, sizeof(priv), GFP_KERNEL);\n1073:\t\tif (!priv)\n1074:\t\t\treturn -ENOMEM;\n1075:\t\n1076:\t\terr = devm_mutex_init(dev, \u0026priv-\u003elock);\n1077:\t\tif (err)\n1078:\t\t\treturn err;\n1079:\t\n1080:\t\tpriv-\u003einfo = device_get_match_data(dev);\n1081:\t\tpriv-\u003eregmap = syscon_node_to_regmap(dev-\u003eparent-\u003eof_node);\n1082:\t\tif (IS_ERR(priv-\u003eregmap))\n1083:\t\t\treturn PTR_ERR(priv-\u003eregmap);\n1084:\t\n1085:\t\terr = otto_emdio_init_polling(priv);\n1086:\t\tif (err)\n1087:\t\t\treturn err;\n1088:\t\n1089:\t\tplatform_set_drvdata(pdev, priv);\n1090:\t\n1091:\t\terr = otto_emdio_map_ports(dev);\n1092:\t\tif (err)\n1093:\t\t\treturn err;\n1094:\t\n1095:\t\terr = otto_emdio_setup_topology(priv);\n1096:\t\tif (err)\n1097:\t\t\treturn err;\n1098:\t\n1099:\t\tif (priv-\u003einfo-\u003esetup_controller) {\n1100:\t\t\terr = priv-\u003einfo-\u003esetup_controller(priv);\n1101:\t\t\tif (err)\n1102:\t\t\t\treturn dev_err_probe(dev, err, \"failed to setup MDIO bus controller\\n\");\n1103:\t\t}\n1104:\t\n1105:\t\tfor_each_child_of_node_scoped(dev-\u003eof_node, child) {\n1106:\t\t\terr = otto_emdio_probe_one(dev, priv, child);\n1107:\t\t\tif (err)\n1108:\t\t\t\treturn err;\n1109:\t\t}\n1110:\t\n1111:\t\treturn 0;\n1112:\t}\n1113:\t\n1114:\tstatic const struct otto_emdio_info otto_emdio_8380_info = {\n1115:\t\t.addr_map_base = RTL8380_SMI_PORT0_5_ADDR_CTRL,\n1116:\t\t.cmd_fail = RTL8380_PHY_CTRL_FAIL,\n1117:\t\t.cmd_read = RTL8380_PHY_CTRL_READ,\n1118:\t\t.cmd_write = RTL8380_PHY_CTRL_WRITE,\n1119:\t\t.cmd_regs = {\n" }
11/2	2026/09/06 21:02	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 26760 output: 22 thoughts: 168 Thoughts: Analyzing the `otto_emdio_driver` Okay, let's break this down. `otto_emdio_driver` has `.suppress_bind_attrs = true;` – that's the first thing to note. It's triggered by the `otto_emdio_ids` of the OF. This driver is for those Realtek switches: RTL838x/RTL839x/RTL930x/RTL931x. Essentially, a platform driver for these MIPS-based Otto architecture MACH_REALTEK_RTL SoCs. Now, hold on... the target architecture is `amd64`. That's a red flag. I need to figure out if `MACH_REALTEK_RTL` is strictly MIPS, or if it's potentially cross-compilable. Can this even exist on an amd64 system, or a standard QEMU VM setup? I need to quickly determine where `MACH_REALTEK_RTL` is actually defined, so I can understand the architectural assumptions being made. This feels like an architectural mismatch I need to reconcile.
12/2	2026/09/06 21:02	tool	grepper	0m Args: { "Expression": "MACH_REALTEK_RTL" } Results: { "Output": "arch/mips/Kconfig=681=config RALINK\n--\narch/mips/Kconfig-698-\narch/mips/Kconfig:699:config MACH_REALTEK_RTL\narch/mips/Kconfig-700-\tbool \"Realtek RTL838x/RTL839x based machines\"\n--\narch/mips/boot/dts/realtek/Makefile-1-# SPDX-License-Identifier: GPL-2.0\narch/mips/boot/dts/realtek/Makefile:2:dtb-$(CONFIG_MACH_REALTEK_RTL)\t+= cisco_sg220-26.dtb\narch/mips/boot/dts/realtek/Makefile:3:dtb-$(CONFIG_MACH_REALTEK_RTL)\t+= cameo-rtl9302c-2x-rtl8224-2xge.dtb\n--\narch/mips/generic/Makefile=15=obj-$(CONFIG_VIRT_BOARD_RANCHU)\t\t+= board-ranchu.o\narch/mips/generic/Makefile:16:obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= board-realtek.o\n--\ndrivers/gpio/Kconfig=625=config GPIO_REALTEK_OTTO\ndrivers/gpio/Kconfig-626-\ttristate \"Realtek Otto GPIO support\"\ndrivers/gpio/Kconfig:627:\tdepends on MACH_REALTEK_RTL \|\| COMPILE_TEST\ndrivers/gpio/Kconfig:628:\tdefault MACH_REALTEK_RTL\ndrivers/gpio/Kconfig-629-\tselect GPIO_GENERIC\n--\ndrivers/i2c/busses/Kconfig=1103=config I2C_RTL9300\ndrivers/i2c/busses/Kconfig-1104-\ttristate \"Realtek RTL9300 I2C controller\"\ndrivers/i2c/busses/Kconfig:1105:\tdepends on MACH_REALTEK_RTL \|\| COMPILE_TEST\ndrivers/i2c/busses/Kconfig-1106-\thelp\n--\ndrivers/irqchip/Makefile=130=obj-$(CONFIG_SL28CPLD_INTC)\t\t+= irq-sl28cpld.o\ndrivers/irqchip/Makefile:131:obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= irq-realtek-rtl.o\ndrivers/irqchip/Makefile-132-obj-$(CONFIG_WPCM450_AIC)\t\t+= irq-wpcm450-aic.o\n--\ndrivers/mtd/nand/Kconfig=64=config MTD_NAND_ECC_REALTEK\n--\ndrivers/mtd/nand/Kconfig-66- depends on HAS_IOMEM \u0026\u0026 HAS_DMA\ndrivers/mtd/nand/Kconfig:67: depends on MACH_REALTEK_RTL \|\| COMPILE_TEST\ndrivers/mtd/nand/Kconfig-68- select MTD_NAND_ECC\n--\ndrivers/net/mdio/Kconfig=174=config MDIO_REALTEK_RTL9300\ndrivers/net/mdio/Kconfig-175-\ttristate \"Realtek RTL83xx/RTL93xx MDIO interface support\"\ndrivers/net/mdio/Kconfig:176:\tdepends on MACH_REALTEK_RTL \|\| COMPILE_TEST\ndrivers/net/mdio/Kconfig-177-\thelp\n--\ndrivers/spi/Kconfig=916=config SPI_REALTEK_SNAND\ndrivers/spi/Kconfig-917-\ttristate \"Realtek SPI-NAND Flash Controller\"\ndrivers/spi/Kconfig:918:\tdepends on MACH_REALTEK_RTL \|\| COMPILE_TEST\ndrivers/spi/Kconfig-919-\tselect REGMAP\n--\ndrivers/spi/Makefile=131=obj-$(CONFIG_SPI_RB4XX)\t\t\t+= spi-rb4xx.o\ndrivers/spi/Makefile:132:obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= spi-realtek-rtl.o\ndrivers/spi/Makefile-133-obj-$(CONFIG_SPI_REALTEK_SNAND)\t\t+= spi-realtek-rtl-snand.o\n--\ndrivers/watchdog/Kconfig=1113=config REALTEK_OTTO_WDT\ndrivers/watchdog/Kconfig-1114-\ttristate \"Realtek Otto MIPS watchdog support\"\ndrivers/watchdog/Kconfig:1115:\tdepends on MACH_REALTEK_RTL \|\| COMPILE_TEST\ndrivers/watchdog/Kconfig-1116-\tdepends on COMMON_CLK\n--\ndrivers/watchdog/Kconfig-1118-\tselect REGMAP_MMIO\ndrivers/watchdog/Kconfig:1119:\tdefault MACH_REALTEK_RTL\ndrivers/watchdog/Kconfig-1120-\thelp\n" }
13/2	2026/09/06 21:02	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 28453 output: 166 thoughts: 893 Thoughts: Reachability Analysis: WorthFuzzing=false Okay, let's break this down. My goal is to determine if this patch is worth fuzzing, and the primary gate is reachability. I'm targeting the amd64 architecture, so I need to assess if the modified code is actually executable in standard virtualized environments like QEMU or GCE. First, I identified some negative criteria. Specifically, I'm looking for "structurally unreachable hardware" – code tied to hardware not emulated in standard environments or architecture-exclusive code. I need to confirm if this `mdio-realtek-rtl9300` driver is actually reachable. My initial thought is it's an MDIO controller driver for Realtek RTL838x/93xx MIPS SoCs, which immediately raises a red flag. I dove into `mdio-realtek-rtl9300.c` itself. It’s a platform driver, so it’s linked to specific hardware. Critically, `suppress_bind_attrs = true` means I can't even manually force it to bind. It relies on a syscon node, obtained via `syscon_node_to_regmap`, meaning its tied to specific hardware. And it's for Realtek's MIPS SoC architecture. The target is amd64. Therefore, it's structurally unreachable. It's an arch-exclusive MIPS SoC driver that can't be used on amd64 in any standard environment. Let's double-check the triage guidelines. They're crystal clear: "If the modified code is structurally unreachable… it MUST NOT be fuzzed." The guidelines specifically mention vendor-specific PCIe switches and architecture-exclusive code paths as examples. That is exactly what I have. So, the files affected are: documentation and the driver. The driver, `mdio-realtek-rtl9300.c`, is the critical element. It's for a specific Realtek MIPS SoC and is not reachable on amd64. Based on this, I'm setting `WorthFuzzing` to `false`. The reasoning is straightforward: the driver targets a specific Realtek MIPS SoC. It cannot execute in any standard amd64 environment. The `FocusSymbols` and `EnableConfigs` are irrelevant here. Time to submit this.
14/2	2026/09/06 21:02	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The patch updates Devicetree bindings documentation and adds MDIO bus clock frequency configuration support to the Realtek RTL838x/RTL839x/RTL930x/RTL931x MDIO controller driver (drivers/net/mdio/mdio-realtek-rtl9300.c). This driver is designed specifically for Realtek Otto MIPS switch SoCs (CONFIG_MACH_REALTEK_RTL), requires OF syscon parent nodes, suppresses manual driver binding via sysfs, and cannot be probed or executed in standard amd64 QEMU/GCE virtualization environments.", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch updates Devicetree bindings documentation and adds MDIO bus clock frequency configuration support to the Realtek RTL838x/RTL839x/RTL930x/RTL931x MDIO controller driver (drivers/net/mdio/mdio-realtek-rtl9300.c). This driver is designed specifically for Realtek Otto MIPS switch SoCs (CONFIG_MACH_REALTEK_RTL), requires OF syscon parent nodes, suppresses manual driver binding via sysfs, and cannot be probed or executed in standard amd64 QEMU/GCE virtualization environments.", "WorthFuzzing": false }
15/1	2026/09/06 21:02	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch updates Devicetree bindings documentation and adds MDIO bus clock frequency configuration support to the Realtek RTL838x/RTL839x/RTL930x/RTL931x MDIO controller driver (drivers/net/mdio/mdio-realtek-rtl9300.c). This driver is designed specifically for Realtek Otto MIPS switch SoCs (CONFIG_MACH_REALTEK_RTL), requires OF syscon parent nodes, suppresses manual driver binding via sysfs, and cannot be probed or executed in standard amd64 QEMU/GCE virtualization environments.",
  "WorthFuzzing": false
}

{
  "PatchDiff": "commit a87d01f2c8f5171ac540fcdf1e425d4a489eded5\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Sun Sep 6 21:02:22 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml\nindex 67e0b23a8470e..88502d017eedb 100644\n--- a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml\n+++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml\n@@ -56,6 +56,9 @@ patternProperties:\n       reg:\n         maxItems: 1\n \n+      clock-frequency:\n+        default: 2500000\n+\n     required:\n       - reg\n \n@@ -71,6 +74,43 @@ required:\n   - compatible\n   - reg\n \n+allOf:\n+  - if:\n+      properties:\n+        compatible:\n+          contains:\n+            enum:\n+              - realtek,rtl8380-mdio\n+              - realtek,rtl8381-mdio\n+              - realtek,rtl8382-mdio\n+    then:\n+      patternProperties:\n+        '^mdio-bus@[0-3]$':\n+          properties:\n+            clock-frequency:\n+              enum: [2500000, 10000000]\n+  - if:\n+      properties:\n+        compatible:\n+          contains:\n+            enum:\n+              - realtek,rtl8391-mdio\n+              - realtek,rtl8392-mdio\n+              - realtek,rtl8393-mdio\n+              - realtek,rtl9301-mdio\n+              - realtek,rtl9302b-mdio\n+              - realtek,rtl9302c-mdio\n+              - realtek,rtl9303-mdio\n+              - realtek,rtl9311-mdio\n+              - realtek,rtl9312-mdio\n+              - realtek,rtl9313-mdio\n+    then:\n+      patternProperties:\n+        '^mdio-bus@[0-3]$':\n+          properties:\n+            clock-frequency:\n+              enum: [1250000, 2500000, 5000000]\n+\n unevaluatedProperties: false\n \n examples:\ndiff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/mdio-realtek-rtl9300.c\nindex 11d078ef941cd..8edb0ba0bcdd1 100644\n--- a/drivers/net/mdio/mdio-realtek-rtl9300.c\n+++ b/drivers/net/mdio/mdio-realtek-rtl9300.c\n@@ -130,6 +130,7 @@\n #define RTL8380_NUM_PAGES\t\t\t4096\n #define RTL8380_NUM_PORTS\t\t\t28\n #define RTL8380_SMI_GLB_CTRL\t\t\t0xa100\n+#define   RTL8380_SMI_FREQ_SEL\t\t\tBIT(1)\n #define   RTL8380_SMI_PHY_PATCH_DONE\t\tBIT(15)\n #define RTL8380_SMI_ACCESS_PHY_CTRL_0\t\t0xa1b8\n #define RTL8380_SMI_ACCESS_PHY_CTRL_1\t\t0xa1bc\n@@ -169,12 +170,15 @@\n #define RTL8390_PHYREG_PORT_CTRL_LOW\t\t0x03e4\n #define RTL8390_PHYREG_PORT_CTRL_HIGH\t\t0x03e8\n #define RTL8390_SMI_PORT_POLLING_CTRL\t\t0x03fc\n+#define RTL8390_SMI_GLB_CTRL\t\t\t0x03f8\n+#define   RTL8390_SMI_FREQ_SEL\t\t\tGENMASK(6, 5)\n \n #define RTL9300_NUM_BUSES\t\t\t4\n #define RTL9300_NUM_PAGES\t\t\t4096\n #define RTL9300_NUM_PORTS\t\t\t28\n #define RTL9300_SMI_GLB_CTRL\t\t\t0xca00\n #define   RTL9300_GLB_CTRL_INTF_SEL(intf)\tBIT(16 + (intf))\n+#define   RTL9300_SMI_FREQ_SEL(intf)\t\tGENMASK((intf) * 2 + 9, (intf) * 2 + 8)\n #define RTL9300_SMI_PORT0_15_POLLING_SEL\t0xca08\n #define RTL9300_SMI_ACCESS_PHY_CTRL_0\t\t0xcb70\n #define RTL9300_SMI_ACCESS_PHY_CTRL_1\t\t0xcb74\n@@ -196,6 +200,8 @@\n #define RTL9310_NUM_BUSES\t\t\t4\n #define RTL9310_NUM_PAGES\t\t\t8192\n #define RTL9310_NUM_PORTS\t\t\t56\n+#define RTL9310_SMI_GLB_CTRL0\t\t\t0x0cc0\n+#define   RTL9310_SMI_FREQ_SEL(intf)\t\tGENMASK((intf) * 2 + 5, (intf) * 2 + 4)\n #define RTL9310_SMI_GLB_CTRL1\t\t\t0x0cbc\n #define   RTL9310_SMI_GLB_FMT_SEL_C45(intf)\tBIT((intf) * 2 + 1)\n #define RTL9310_SMI_INDRT_ACCESS_CTRL_0\t\t0x0c00\n@@ -251,6 +257,7 @@ struct otto_emdio_priv {\n \tstruct regmap *regmap;\n \tstruct mutex lock; /* protect HW access */\n \tDECLARE_BITMAP(valid_ports, MAX_PORTS);\n+\tu32 global_freq;\n \tu16 page[MAX_PORTS];\n \tu8 smi_bus[MAX_PORTS];\n \tu8 smi_addr[MAX_PORTS];\n@@ -269,6 +276,7 @@ struct otto_emdio_info {\n \tu8 num_ports;\n \tu16 num_pages;\n \tu32 poll_ctrl;\n+\tint (*set_bus_frequency)(struct mii_bus *bus, u32 freq);\n \tint (*setup_controller)(struct otto_emdio_priv *priv);\n \tint (*read_c22)(struct mii_bus *bus, int port, int regnum, u32 *value);\n \tint (*read_c45)(struct mii_bus *bus, int port, int dev_addr, int regnum, u32 *value);\n@@ -740,6 +748,17 @@ static int otto_emdio_setup_topology(struct otto_emdio_priv *priv)\n \treturn 0;\n }\n \n+static int otto_emdio_8380_set_bus_frequency(struct mii_bus *bus, u32 freq)\n+{\n+\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\n+\n+\tif (freq != 2500000 \u0026\u0026 freq != 10000000)\n+\t\treturn -EINVAL;\n+\n+\treturn regmap_assign_bits(priv-\u003eregmap, RTL8380_SMI_GLB_CTRL,\n+\t\t\t\t  RTL8380_SMI_FREQ_SEL, freq == 10000000);\n+}\n+\n static int otto_emdio_8380_setup_controller(struct otto_emdio_priv *priv)\n {\n \t/*\n@@ -749,6 +768,40 @@ static int otto_emdio_8380_setup_controller(struct otto_emdio_priv *priv)\n \treturn regmap_set_bits(priv-\u003eregmap, RTL8380_SMI_GLB_CTRL, RTL8380_SMI_PHY_PATCH_DONE);\n }\n \n+static int otto_emdio_8390_set_bus_frequency(struct mii_bus *bus, u32 freq)\n+{\n+\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\n+\tu32 val;\n+\tint err;\n+\n+\tif (freq != 1250000 \u0026\u0026 freq != 2500000 \u0026\u0026 freq != 5000000)\n+\t\treturn -EINVAL;\n+\tif (priv-\u003eglobal_freq)\n+\t\treturn freq == priv-\u003eglobal_freq ? 0 : -EINVAL;\n+\n+\tval = FIELD_PREP(RTL8390_SMI_FREQ_SEL, freq / 2500000);\n+\terr = regmap_update_bits(priv-\u003eregmap, RTL8390_SMI_GLB_CTRL, RTL8390_SMI_FREQ_SEL, val);\n+\tif (!err)\n+\t\tpriv-\u003eglobal_freq = freq;\n+\n+\treturn err;\n+}\n+\n+static int otto_emdio_9300_set_bus_frequency(struct mii_bus *bus, u32 freq)\n+{\n+\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\n+\tstruct otto_emdio_chan *chan = bus-\u003epriv;\n+\tu32 mask, val;\n+\n+\tif (freq != 1250000 \u0026\u0026 freq != 2500000 \u0026\u0026 freq != 5000000)\n+\t\treturn -EINVAL;\n+\n+\tmask = RTL9300_SMI_FREQ_SEL(chan-\u003emdio_bus);\n+\tval = field_prep(mask, freq / 2500000);\n+\n+\treturn regmap_update_bits(priv-\u003eregmap, RTL9300_SMI_GLB_CTRL, mask, val);\n+}\n+\n static int otto_emdio_9300_setup_controller(struct otto_emdio_priv *priv)\n {\n \tu32 glb_ctrl_mask = 0, glb_ctrl_val = 0;\n@@ -769,6 +822,21 @@ static int otto_emdio_9300_setup_controller(struct otto_emdio_priv *priv)\n \treturn 0;\n }\n \n+static int otto_emdio_9310_set_bus_frequency(struct mii_bus *bus, u32 freq)\n+{\n+\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\n+\tstruct otto_emdio_chan *chan = bus-\u003epriv;\n+\tu32 mask, val;\n+\n+\tif (freq != 1250000 \u0026\u0026 freq != 2500000 \u0026\u0026 freq != 5000000)\n+\t\treturn -EINVAL;\n+\n+\tmask = RTL9310_SMI_FREQ_SEL(chan-\u003emdio_bus);\n+\tval = field_prep(mask, freq / 2500000);\n+\n+\treturn regmap_update_bits(priv-\u003eregmap, RTL9310_SMI_GLB_CTRL0, mask, val);\n+}\n+\n static int otto_emdio_9310_setup_controller(struct otto_emdio_priv *priv)\n {\n \tint i, err;\n@@ -831,14 +899,14 @@ static void otto_emdio_notify_phy_detach(struct phy_device *phydev)\n }\n \n static int otto_emdio_probe_one(struct device *dev, struct otto_emdio_priv *priv,\n-\t\t\t\t struct fwnode_handle *node)\n+\t\t\t\tstruct device_node *node)\n {\n \tstruct otto_emdio_chan *chan;\n \tstruct mii_bus *bus;\n-\tu32 mdio_bus;\n+\tu32 mdio_bus, freq;\n \tint err;\n \n-\terr = fwnode_property_read_u32(node, \"reg\", \u0026mdio_bus);\n+\terr = of_property_read_u32(node, \"reg\", \u0026mdio_bus);\n \tif (err)\n \t\treturn dev_err_probe(dev, err, \"undefined smi bus number\\n\");\n \n@@ -865,7 +933,14 @@ static int otto_emdio_probe_one(struct device *dev, struct otto_emdio_priv *priv\n \n \tsnprintf(bus-\u003eid, MII_BUS_ID_SIZE, \"%s-%d\", dev_name(dev), mdio_bus);\n \n-\terr = devm_of_mdiobus_register(dev, bus, to_of_node(node));\n+\tif (of_property_read_u32(node, \"clock-frequency\", \u0026freq))\n+\t\tfreq = 2500000;\n+\terr = priv-\u003einfo-\u003eset_bus_frequency(bus, freq);\n+\tif (err)\n+\t\treturn dev_err_probe(dev, err, \"cannot set frequency %u for MDIO bus %d\\n\",\n+\t\t\t\t     freq, mdio_bus);\n+\n+\terr = devm_of_mdiobus_register(dev, bus, node);\n \tif (err)\n \t\treturn dev_err_probe(dev, err, \"cannot register MDIO bus\\n\");\n \n@@ -1027,7 +1102,7 @@ static int otto_emdio_probe(struct platform_device *pdev)\n \t\t\treturn dev_err_probe(dev, err, \"failed to setup MDIO bus controller\\n\");\n \t}\n \n-\tdevice_for_each_child_node_scoped(dev, child) {\n+\tfor_each_child_of_node_scoped(dev-\u003eof_node, child) {\n \t\terr = otto_emdio_probe_one(dev, priv, child);\n \t\tif (err)\n \t\t\treturn err;\n@@ -1051,6 +1126,7 @@ static const struct otto_emdio_info otto_emdio_8380_info = {\n \t.num_pages = RTL8380_NUM_PAGES,\n \t.num_ports = RTL8380_NUM_PORTS,\n \t.poll_ctrl = RTL8380_SMI_POLL_CTRL,\n+\t.set_bus_frequency = otto_emdio_8380_set_bus_frequency,\n \t.setup_controller = otto_emdio_8380_setup_controller,\n \t.read_c22 = otto_emdio_8380_read_c22,\n \t.read_c45 = otto_emdio_8380_read_c45,\n@@ -1075,6 +1151,7 @@ static const struct otto_emdio_info otto_emdio_8390_info = {\n \t.num_pages = RTL8390_NUM_PAGES,\n \t.num_ports = RTL8390_NUM_PORTS,\n \t.poll_ctrl = RTL8390_SMI_PORT_POLLING_CTRL,\n+\t.set_bus_frequency = otto_emdio_8390_set_bus_frequency,\n \t.read_c22 = otto_emdio_8390_read_c22,\n \t.read_c45 = otto_emdio_8390_read_c45,\n \t.write_c22 = otto_emdio_8390_write_c22,\n@@ -1097,6 +1174,7 @@ static const struct otto_emdio_info otto_emdio_9300_info = {\n \t.num_ports = RTL9300_NUM_PORTS,\n \t.num_pages = RTL9300_NUM_PAGES,\n \t.poll_ctrl = RTL9300_SMI_POLL_CTRL,\n+\t.set_bus_frequency = otto_emdio_9300_set_bus_frequency,\n \t.setup_controller = otto_emdio_9300_setup_controller,\n \t.read_c22 = otto_emdio_9300_read_c22,\n \t.read_c45 = otto_emdio_9300_read_c45,\n@@ -1123,6 +1201,7 @@ static const struct otto_emdio_info otto_emdio_9310_info = {\n \t.num_pages = RTL9310_NUM_PAGES,\n \t.num_ports = RTL9310_NUM_PORTS,\n \t.poll_ctrl = RTL9310_SMI_PORT_POLLING_CTRL,\n+\t.set_bus_frequency = otto_emdio_9310_set_bus_frequency,\n \t.setup_controller = otto_emdio_9310_setup_controller,\n \t.read_c22 = otto_emdio_9310_read_c22,\n \t.read_c45 = otto_emdio_9310_read_c45,\n"
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch updates Devicetree bindings documentation and adds MDIO bus clock frequency configuration support to the Realtek RTL838x/RTL839x/RTL930x/RTL931x MDIO controller driver (drivers/net/mdio/mdio-realtek-rtl9300.c). This driver is designed specifically for Realtek Otto MIPS switch SoCs (CONFIG_MACH_REALTEK_RTL), requires OF syscon parent nodes, suppresses manual driver binding via sysfs, and cannot be probed or executed in standard amd64 QEMU/GCE virtualization environments.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit a87d01f2c8f5171ac540fcdf1e425d4a489eded5
Author: syz-cluster <triage@syzkaller.com>
Date:   Sun Sep 6 21:02:22 2026 +0000

    syz-cluster: applied patch under review

diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml
index 67e0b23a8470e..88502d017eedb 100644
--- a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml
+++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml
@@ -56,6 +56,9 @@ patternProperties:
       reg:
         maxItems: 1
 
+      clock-frequency:
+        default: 2500000
+
     required:
       - reg
 
@@ -71,6 +74,43 @@ required:
   - compatible
   - reg
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - realtek,rtl8380-mdio
+              - realtek,rtl8381-mdio
+              - realtek,rtl8382-mdio
+    then:
+      patternProperties:
+        '^mdio-bus@[0-3]$':
+          properties:
+            clock-frequency:
+              enum: [2500000, 10000000]
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - realtek,rtl8391-mdio
+              - realtek,rtl8392-mdio
+              - realtek,rtl8393-mdio
+              - realtek,rtl9301-mdio
+              - realtek,rtl9302b-mdio
+              - realtek,rtl9302c-mdio
+              - realtek,rtl9303-mdio
+              - realtek,rtl9311-mdio
+              - realtek,rtl9312-mdio
+              - realtek,rtl9313-mdio
+    then:
+      patternProperties:
+        '^mdio-bus@[0-3]$':
+          properties:
+            clock-frequency:
+              enum: [1250000, 2500000, 5000000]
+
 unevaluatedProperties: false
 
 examples:
diff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/mdio-realtek-rtl9300.c
index 11d078ef941cd..8edb0ba0bcdd1 100644
--- a/drivers/net/mdio/mdio-realtek-rtl9300.c
+++ b/drivers/net/mdio/mdio-realtek-rtl9300.c
@@ -130,6 +130,7 @@
 #define RTL8380_NUM_PAGES			4096
 #define RTL8380_NUM_PORTS			28
 #define RTL8380_SMI_GLB_CTRL			0xa100
+#define   RTL8380_SMI_FREQ_SEL			BIT(1)
 #define   RTL8380_SMI_PHY_PATCH_DONE		BIT(15)
 #define RTL8380_SMI_ACCESS_PHY_CTRL_0		0xa1b8
 #define RTL8380_SMI_ACCESS_PHY_CTRL_1		0xa1bc
@@ -169,12 +170,15 @@
 #define RTL8390_PHYREG_PORT_CTRL_LOW		0x03e4
 #define RTL8390_PHYREG_PORT_CTRL_HIGH		0x03e8
 #define RTL8390_SMI_PORT_POLLING_CTRL		0x03fc
+#define RTL8390_SMI_GLB_CTRL			0x03f8
+#define   RTL8390_SMI_FREQ_SEL			GENMASK(6, 5)
 
 #define RTL9300_NUM_BUSES			4
 #define RTL9300_NUM_PAGES			4096
 #define RTL9300_NUM_PORTS			28
 #define RTL9300_SMI_GLB_CTRL			0xca00
 #define   RTL9300_GLB_CTRL_INTF_SEL(intf)	BIT(16 + (intf))
+#define   RTL9300_SMI_FREQ_SEL(intf)		GENMASK((intf) * 2 + 9, (intf) * 2 + 8)
 #define RTL9300_SMI_PORT0_15_POLLING_SEL	0xca08
 #define RTL9300_SMI_ACCESS_PHY_CTRL_0		0xcb70
 #define RTL9300_SMI_ACCESS_PHY_CTRL_1		0xcb74
@@ -196,6 +200,8 @@
 #define RTL9310_NUM_BUSES			4
 #define RTL9310_NUM_PAGES			8192
 #define RTL9310_NUM_PORTS			56
+#define RTL9310_SMI_GLB_CTRL0			0x0cc0
+#define   RTL9310_SMI_FREQ_SEL(intf)		GENMASK((intf) * 2 + 5, (intf) * 2 + 4)
 #define RTL9310_SMI_GLB_CTRL1			0x0cbc
 #define   RTL9310_SMI_GLB_FMT_SEL_C45(intf)	BIT((intf) * 2 + 1)
 #define RTL9310_SMI_INDRT_ACCESS_CTRL_0		0x0c00
@@ -251,6 +257,7 @@ struct otto_emdio_priv {
 	struct regmap *regmap;
 	struct mutex lock; /* protect HW access */
 	DECLARE_BITMAP(valid_ports, MAX_PORTS);
+	u32 global_freq;
 	u16 page[MAX_PORTS];
 	u8 smi_bus[MAX_PORTS];
 	u8 smi_addr[MAX_PORTS];
@@ -269,6 +276,7 @@ struct otto_emdio_info {
 	u8 num_ports;
 	u16 num_pages;
 	u32 poll_ctrl;
+	int (*set_bus_frequency)(struct mii_bus *bus, u32 freq);
 	int (*setup_controller)(struct otto_emdio_priv *priv);
 	int (*read_c22)(struct mii_bus *bus, int port, int regnum, u32 *value);
 	int (*read_c45)(struct mii_bus *bus, int port, int dev_addr, int regnum, u32 *value);
@@ -740,6 +748,17 @@ static int otto_emdio_setup_topology(struct otto_emdio_priv *priv)
 	return 0;
 }
 
+static int otto_emdio_8380_set_bus_frequency(struct mii_bus *bus, u32 freq)
+{
+	struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
+
+	if (freq != 2500000 && freq != 10000000)
+		return -EINVAL;
+
+	return regmap_assign_bits(priv->regmap, RTL8380_SMI_GLB_CTRL,
+				  RTL8380_SMI_FREQ_SEL, freq == 10000000);
+}
+
 static int otto_emdio_8380_setup_controller(struct otto_emdio_priv *priv)
 {
 	/*
@@ -749,6 +768,40 @@ static int otto_emdio_8380_setup_controller(struct otto_emdio_priv *priv)
 	return regmap_set_bits(priv->regmap, RTL8380_SMI_GLB_CTRL, RTL8380_SMI_PHY_PATCH_DONE);
 }
 
+static int otto_emdio_8390_set_bus_frequency(struct mii_bus *bus, u32 freq)
+{
+	struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
+	u32 val;
+	int err;
+
+	if (freq != 1250000 && freq != 2500000 && freq != 5000000)
+		return -EINVAL;
+	if (priv->global_freq)
+		return freq == priv->global_freq ? 0 : -EINVAL;
+
+	val = FIELD_PREP(RTL8390_SMI_FREQ_SEL, freq / 2500000);
+	err = regmap_update_bits(priv->regmap, RTL8390_SMI_GLB_CTRL, RTL8390_SMI_FREQ_SEL, val);
+	if (!err)
+		priv->global_freq = freq;
+
+	return err;
+}
+
+static int otto_emdio_9300_set_bus_frequency(struct mii_bus *bus, u32 freq)
+{
+	struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
+	struct otto_emdio_chan *chan = bus->priv;
+	u32 mask, val;
+
+	if (freq != 1250000 && freq != 2500000 && freq != 5000000)
+		return -EINVAL;
+
+	mask = RTL9300_SMI_FREQ_SEL(chan->mdio_bus);
+	val = field_prep(mask, freq / 2500000);
+
+	return regmap_update_bits(priv->regmap, RTL9300_SMI_GLB_CTRL, mask, val);
+}
+
 static int otto_emdio_9300_setup_controller(struct otto_emdio_priv *priv)
 {
 	u32 glb_ctrl_mask = 0, glb_ctrl_val = 0;
@@ -769,6 +822,21 @@ static int otto_emdio_9300_setup_controller(struct otto_emdio_priv *priv)
 	return 0;
 }
 
+static int otto_emdio_9310_set_bus_frequency(struct mii_bus *bus, u32 freq)
+{
+	struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
+	struct otto_emdio_chan *chan = bus->priv;
+	u32 mask, val;
+
+	if (freq != 1250000 && freq != 2500000 && freq != 5000000)
+		return -EINVAL;
+
+	mask = RTL9310_SMI_FREQ_SEL(chan->mdio_bus);
+	val = field_prep(mask, freq / 2500000);
+
+	return regmap_update_bits(priv->regmap, RTL9310_SMI_GLB_CTRL0, mask, val);
+}
+
 static int otto_emdio_9310_setup_controller(struct otto_emdio_priv *priv)
 {
 	int i, err;
@@ -831,14 +899,14 @@ static void otto_emdio_notify_phy_detach(struct phy_device *phydev)
 }
 
 static int otto_emdio_probe_one(struct device *dev, struct otto_emdio_priv *priv,
-				 struct fwnode_handle *node)
+				struct device_node *node)
 {
 	struct otto_emdio_chan *chan;
 	struct mii_bus *bus;
-	u32 mdio_bus;
+	u32 mdio_bus, freq;
 	int err;
 
-	err = fwnode_property_read_u32(node, "reg", &mdio_bus);
+	err = of_property_read_u32(node, "reg", &mdio_bus);
 	if (err)
 		return dev_err_probe(dev, err, "undefined smi bus number\n");
 
@@ -865,7 +933,14 @@ static int otto_emdio_probe_one(struct device *dev, struct otto_emdio_priv *priv
 
 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", dev_name(dev), mdio_bus);
 
-	err = devm_of_mdiobus_register(dev, bus, to_of_node(node));
+	if (of_property_read_u32(node, "clock-frequency", &freq))
+		freq = 2500000;
+	err = priv->info->set_bus_frequency(bus, freq);
+	if (err)
+		return dev_err_probe(dev, err, "cannot set frequency %u for MDIO bus %d\n",
+				     freq, mdio_bus);
+
+	err = devm_of_mdiobus_register(dev, bus, node);
 	if (err)
 		return dev_err_probe(dev, err, "cannot register MDIO bus\n");
 
@@ -1027,7 +1102,7 @@ static int otto_emdio_probe(struct platform_device *pdev)
 			return dev_err_probe(dev, err, "failed to setup MDIO bus controller\n");
 	}
 
-	device_for_each_child_node_scoped(dev, child) {
+	for_each_child_of_node_scoped(dev->of_node, child) {
 		err = otto_emdio_probe_one(dev, priv, child);
 		if (err)
 			return err;
@@ -1051,6 +1126,7 @@ static const struct otto_emdio_info otto_emdio_8380_info = {
 	.num_pages = RTL8380_NUM_PAGES,
 	.num_ports = RTL8380_NUM_PORTS,
 	.poll_ctrl = RTL8380_SMI_POLL_CTRL,
+	.set_bus_frequency = otto_emdio_8380_set_bus_frequency,
 	.setup_controller = otto_emdio_8380_setup_controller,
 	.read_c22 = otto_emdio_8380_read_c22,
 	.read_c45 = otto_emdio_8380_read_c45,
@@ -1075,6 +1151,7 @@ static const struct otto_emdio_info otto_emdio_8390_info = {
 	.num_pages = RTL8390_NUM_PAGES,
 	.num_ports = RTL8390_NUM_PORTS,
 	.poll_ctrl = RTL8390_SMI_PORT_POLLING_CTRL,
+	.set_bus_frequency = otto_emdio_8390_set_bus_frequency,
 	.read_c22 = otto_emdio_8390_read_c22,
 	.read_c45 = otto_emdio_8390_read_c45,
 	.write_c22 = otto_emdio_8390_write_c22,
@@ -1097,6 +1174,7 @@ static const struct otto_emdio_info otto_emdio_9300_info = {
 	.num_ports = RTL9300_NUM_PORTS,
 	.num_pages = RTL9300_NUM_PAGES,
 	.poll_ctrl = RTL9300_SMI_POLL_CTRL,
+	.set_bus_frequency = otto_emdio_9300_set_bus_frequency,
 	.setup_controller = otto_emdio_9300_setup_controller,
 	.read_c22 = otto_emdio_9300_read_c22,
 	.read_c45 = otto_emdio_9300_read_c45,
@@ -1123,6 +1201,7 @@ static const struct otto_emdio_info otto_emdio_9310_info = {
 	.num_pages = RTL9310_NUM_PAGES,
 	.num_ports = RTL9310_NUM_PORTS,
 	.poll_ctrl = RTL9310_SMI_PORT_POLLING_CTRL,
+	.set_bus_frequency = otto_emdio_9310_set_bus_frequency,
 	.setup_controller = otto_emdio_9310_setup_controller,
 	.read_c22 = otto_emdio_9310_read_c22,
 	.read_c45 = otto_emdio_9310_read_c45,

							input: 7090
							output: 39
							thoughts: 131

**Analyzing the Patch for Fuzzing Potential**

Okay, let's dive into this. My initial assessment hinges on whether this patch presents a compelling case for fuzzing, so I need to weigh the potential attack surface. Let's start by breaking down the patch's components.

First, I see the modifications involve two files: `Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml` and `drivers/net/mdio/mdio-realtek-rtl9300.c`. The YAML file typically indicates changes to Device Tree bindings, which *could* involve subtle logic changes influencing device configuration or data interpretation – worth noting, but not necessarily a fuzzing gold mine on its own.

Now, the `mdio-realtek-rtl9300.c` file is where things get interesting. I need to understand what this driver does. I'm going to quickly check its Kconfig entry. I need to get a clear picture of the driver's role. Is it a core network interface driver? Does it interact with hardware in a way that handles external data? Is it targeted at a particular architecture or hardware component? That's going to inform me whether it's worth the time to even probe the surface for fuzzing opportunities. The probing/instantiation method is also crucial - how the driver initializes, receives data, and sets up communication channels provides great indicators as to where and how fuzzing can be effective.

{
  "Expression": "MDIO_REALTEK_RTL9300",
  "PathPrefix": "drivers/net/mdio"
}

{
  "Output": "drivers/net/mdio/Kconfig=166=config MDIO_IPQ8064\n--\ndrivers/net/mdio/Kconfig-173-\ndrivers/net/mdio/Kconfig:174:config MDIO_REALTEK_RTL9300\ndrivers/net/mdio/Kconfig-175-\ttristate \"Realtek RTL83xx/RTL93xx MDIO interface support\"\n--\ndrivers/net/mdio/Makefile=23=obj-$(CONFIG_MDIO_PIC64HPSC)\t\t+= mdio-pic64hpsc.o\ndrivers/net/mdio/Makefile:24:obj-$(CONFIG_MDIO_REALTEK_RTL9300)\t+= mdio-realtek-rtl9300.o\ndrivers/net/mdio/Makefile-25-obj-$(CONFIG_MDIO_REGMAP)\t\t+= mdio-regmap.o\n"
}

							input: 7817
							output: 37
							thoughts: 22

Here's my attempt at summarizing the thought process, tailored for an expert audience and written in the first person:

**Analyzing the MDIO_REALTEK_RTL9300 Kconfig**

Okay, so I'm diving into the Kconfig for the MDIO_REALTEK_RTL9300 driver. My initial goal is to understand how this specific hardware support is configured within the broader build system. What are the key dependencies? What options are exposed to the user, and how granular are they? I’m looking for the essential knobs, the ones that truly matter. For example, are there optional features controlled by tristates or just bools? What are the implications of enabling this driver -- which dependencies will I pull in and is this driver required for other core functionalities? Are there any potentially problematic defaults that I need to be aware of? I'll be checking if the driver's configuration is clean or if it needs improvement. Understanding the configuration options gives me insight into the driver's capabilities and its suitability for different use cases. Ultimately, I need to know the implications of enabling this driver in my system configuration, both in terms of code footprint and potential conflicts with other modules.

{
  "File": "drivers/net/mdio/Kconfig",
  "FirstLine": 170,
  "LineCount": 25
}

{
  "Contents": " 170:\t\thelp\n 171:\t\t  This driver supports the MDIO interface found in the network\n 172:\t\t  interface units of the IPQ8064 SoC\n 173:\t\n 174:\tconfig MDIO_REALTEK_RTL9300\n 175:\t\ttristate \"Realtek RTL83xx/RTL93xx MDIO interface support\"\n 176:\t\tdepends on MACH_REALTEK_RTL || COMPILE_TEST\n 177:\t\thelp\n 178:\t\t  This driver supports the MDIO interface found in the Realtek\n 179:\t\t  RTL83xx/RTL93xx family of Ethernet switches with integrated SoC.\n 180:\t\n 181:\tconfig MDIO_REGMAP\n 182:\t\ttristate\n 183:\t\thelp\n 184:\t\t  This driver allows using MDIO devices that are not sitting on a\n 185:\t\t  regular MDIO bus, but still exposes the standard 802.3 register\n 186:\t\t  layout. It's regmap-based so that it can be used on integrated,\n 187:\t\t  memory-mapped PHYs, SPI PHYs and so on. A new virtual MDIO bus is\n 188:\t\t  created, and its read/write operations are mapped to the underlying\n 189:\t\t  regmap. Users willing to use this driver must explicitly select\n 190:\t\t  REGMAP.\n 191:\t\n 192:\tconfig MDIO_THUNDER\n 193:\t\ttristate \"ThunderX SOCs MDIO buses\"\n 194:\t\tdepends on 64BIT\n"
}

							input: 8564
							output: 45
							thoughts: 83

**Analyzing the mdio-realtek-rtl9300.c Driver**

Okay, let's dive into this `mdio-realtek-rtl9300.c` driver. I need to understand its probing mechanism. First, I'll identify the bus it's tied to. Then, I need to figure out if this is strictly a platform driver, specifically for that Realtek MIPS SoC, the `MACH_REALTEK_RTL` architecture, or if there's some device tree (DT) overlay configuration or alternative approach that allows it to be accessed via other configurations. Essentially, I need to get the big picture of this driver and how it's integrated. Let's start with a thorough review of the `mdio-realtek-rtl9300.c` file itself.

{
  "Expression": "otto_emdio_",
  "PathPrefix": "drivers/net/mdio/mdio-realtek-rtl9300.c"
}

{
  "Output": "drivers/net/mdio/mdio-realtek-rtl9300.c-243-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:244:struct otto_emdio_cmd_regs {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-245-\tu32 c22_data;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-254-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:255:struct otto_emdio_priv {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:256:\tconst struct otto_emdio_info *info;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-257-\tstruct regmap *regmap;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-267-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:268:struct otto_emdio_info {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-269-\tu32 addr_map_base;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-273-\tu32 cmd_write;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:274:\tstruct otto_emdio_cmd_regs cmd_regs;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-275-\tu8 num_buses;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-279-\tint (*set_bus_frequency)(struct mii_bus *bus, u32 freq);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:280:\tint (*setup_controller)(struct otto_emdio_priv *priv);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-281-\tint (*read_c22)(struct mii_bus *bus, int port, int regnum, u32 *value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-286-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:287:struct otto_emdio_chan {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:288:\tstruct otto_emdio_priv *priv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-289-\tu8 mdio_bus;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-291-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:292:static int otto_emdio_phy_to_port(struct mii_bus *bus, int phy_id)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-293-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:294:\tstruct otto_emdio_chan *chan = bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:295:\tstruct otto_emdio_priv *priv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-296-\tint i;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-307-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:308:static struct otto_emdio_priv *otto_emdio_bus_to_priv(struct mii_bus *bus)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-309-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:310:\tstruct otto_emdio_chan *chan = bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-311-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-314-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:315:static int otto_emdio_set_port_polling(struct otto_emdio_priv *priv, int port, bool active)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-316-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-320-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:321:static int otto_emdio_run_cmd(struct mii_bus *bus, u32 cmd,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:322:\t\t\t      struct otto_emdio_cmd_regs *cmd_data)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-323-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:324:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:325:\tconst struct otto_emdio_info *info = priv-\u003einfo;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-326-\tu32 cmdstate;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-377-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:378:static int otto_emdio_read_cmd(struct mii_bus *bus, u32 cmd,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:379:\t\t\t       struct otto_emdio_cmd_regs *cmd_data, u32 mask, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-380-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:381:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-382-\tint ret;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-384-\tlockdep_assert_held(\u0026priv-\u003elock);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:385:\tret = otto_emdio_run_cmd(bus, cmd | priv-\u003einfo-\u003ecmd_read, cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-386-\tif (ret)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-397-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:398:static int otto_emdio_write_cmd(struct mii_bus *bus, u32 cmd,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:399:\t\t\t\tstruct otto_emdio_cmd_regs *cmd_data)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-400-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:401:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-402-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-404-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:405:\treturn otto_emdio_run_cmd(bus, cmd | priv-\u003einfo-\u003ecmd_write, cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-406-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-407-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:408:static int otto_emdio_8380_read_c22(struct mii_bus *bus, int port, int regnum, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-409-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:410:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:411:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-412-\t\t.c22_data\t= FIELD_PREP(RTL8380_PHY_CTRL_REG_ADDR, regnum) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-417-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:418:\treturn otto_emdio_read_cmd(bus, RTL8380_PHY_CTRL_TYPE_C22, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-419-\t\t\t\t   RTL8380_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-421-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:422:static int otto_emdio_8380_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-423-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:424:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:425:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-426-\t\t.c22_data\t= FIELD_PREP(RTL8380_PHY_CTRL_REG_ADDR, regnum) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-432-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:433:\treturn otto_emdio_write_cmd(bus, RTL8380_PHY_CTRL_TYPE_C22, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-434-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-435-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:436:static int otto_emdio_8380_read_c45(struct mii_bus *bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-437-\t\t\t\t    int dev_addr, int regnum, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-438-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:439:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-440-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-444-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:445:\treturn otto_emdio_read_cmd(bus, RTL8380_PHY_CTRL_TYPE_C45, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-446-\t\t\t\t   RTL8380_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-448-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:449:static int otto_emdio_8380_write_c45(struct mii_bus *bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-450-\t\t\t\t     int dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-451-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:452:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-453-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-458-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:459:\treturn otto_emdio_write_cmd(bus, RTL8380_PHY_CTRL_TYPE_C45, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-460-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-461-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:462:static int otto_emdio_8390_read_c22(struct mii_bus *bus, int port, int regnum, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-463-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:464:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:465:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-466-\t\t.c22_data\t= FIELD_PREP(RTL8390_PHY_CTRL_REG_ADDR, regnum) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-471-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:472:\treturn otto_emdio_read_cmd(bus, RTL8390_PHY_CTRL_TYPE_C22, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-473-\t\t\t\t   RTL8390_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-475-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:476:static int otto_emdio_8390_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-477-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:478:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:479:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-480-\t\t.c22_data\t= FIELD_PREP(RTL8390_PHY_CTRL_REG_ADDR, regnum) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-487-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:488:\treturn otto_emdio_write_cmd(bus, RTL8390_PHY_CTRL_TYPE_C22, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-489-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-490-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:491:static int otto_emdio_8390_read_c45(struct mii_bus *bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-492-\t\t\t\t    int dev_addr, int regnum, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-493-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:494:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-495-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-499-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:500:\treturn otto_emdio_read_cmd(bus, RTL8390_PHY_CTRL_TYPE_C45, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-501-\t\t\t\t   RTL8390_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-503-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:504:static int otto_emdio_8390_write_c45(struct mii_bus *bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-505-\t\t\t\t     int dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-506-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:507:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-508-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-514-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:515:\treturn otto_emdio_write_cmd(bus, RTL8390_PHY_CTRL_TYPE_C45, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-516-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-517-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:518:static int otto_emdio_9300_read_c22(struct mii_bus *bus, int port, int regnum, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-519-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:520:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:521:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-522-\t\t.c22_data\t= FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-527-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:528:\treturn otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-529-\t\t\t\t   RTL9300_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-531-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:532:static int otto_emdio_9300_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-533-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:534:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:535:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-536-\t\t.c22_data\t= FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-542-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:543:\treturn otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-544-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-545-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:546:static int otto_emdio_9300_read_c45(struct mii_bus *bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-547-\t\t\t\t    int dev_addr, int regnum, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-548-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:549:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-550-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-554-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:555:\treturn otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-556-\t\t\t\t   RTL9300_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-558-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:559:static int otto_emdio_9300_write_c45(struct mii_bus *bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-560-\t\t\t\t     int dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-561-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:562:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-563-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-568-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:569:\treturn otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-570-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-571-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:572:static int otto_emdio_9310_read_c22(struct mii_bus *bus, int port, int regnum, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-573-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:574:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:575:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-576-\t\t.broadcast\t= FIELD_PREP(RTL9310_BC_PORT_ID, port),\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-580-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:581:\treturn otto_emdio_read_cmd(bus, RTL9310_PHY_CTRL_TYPE_C22, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-582-\t\t\t\t   RTL9310_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-584-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:585:static int otto_emdio_9310_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-586-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:587:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:588:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-589-\t\t.c22_data\t= FIELD_PREP(RTL9310_PHY_CTRL_REG_ADDR, regnum) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-595-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:596:\treturn otto_emdio_write_cmd(bus, RTL9310_PHY_CTRL_TYPE_C22, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-597-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-598-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:599:static int otto_emdio_9310_read_c45(struct mii_bus *bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-600-\t\t\t\t    int dev_addr, int regnum, u32 *value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-601-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:602:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-603-\t\t.broadcast\t= FIELD_PREP(RTL9310_BC_PORT_ID, port),\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-607-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:608:\treturn otto_emdio_read_cmd(bus, RTL9310_PHY_CTRL_TYPE_C45, \u0026cmd_data,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-609-\t\t\t\t   RTL9310_PHY_CTRL_DATA, value);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-611-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:612:static int otto_emdio_9310_write_c45(struct mii_bus *bus, int port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-613-\t\t\t\t     int dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-614-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:615:\tstruct otto_emdio_cmd_regs cmd_data = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-616-\t\t.c45_data\t= FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-622-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:623:\treturn otto_emdio_write_cmd(bus, RTL9310_PHY_CTRL_TYPE_C45, \u0026cmd_data);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-624-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-625-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:626:static int otto_emdio_read_c22(struct mii_bus *bus, int phy_id, int regnum)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-627-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:628:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-629-\tint ret, port;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-637-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:638:\tport = otto_emdio_phy_to_port(bus, phy_id);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-639-\tif (port \u003c 0)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-651-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:652:static int otto_emdio_write_c22(struct mii_bus *bus, int phy_id, int regnum,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-653-\t\t\t\tu16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-654-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:655:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-656-\tint ret, port;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-663-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:664:\tport = otto_emdio_phy_to_port(bus, phy_id);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-665-\tif (port \u003c 0)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-682-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:683:static int otto_emdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-684-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:685:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-686-\tint ret, port;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-688-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:689:\tport = otto_emdio_phy_to_port(bus, phy_id);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-690-\tif (port \u003c 0)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-698-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:699:static int otto_emdio_write_c45(struct mii_bus *bus, int phy_id,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-700-\t\t\t\tint dev_addr, int regnum, u16 value)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-701-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:702:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-703-\tint ret, port;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-704-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:705:\tport = otto_emdio_phy_to_port(bus, phy_id);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-706-\tif (port \u003c 0)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-714-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:715:static int otto_emdio_write_mapping(struct otto_emdio_priv *priv, u32 base, u32 port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-716-\t\t\t\t    u32 vals_per_reg, u32 bits_per_val, u32 value)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-724-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:725:static int otto_emdio_setup_topology(struct otto_emdio_priv *priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-726-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:727:\tconst struct otto_emdio_info *info = priv-\u003einfo;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-728-\tu32 port;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-732-\t\tif (info-\u003ebus_map_base) {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:733:\t\t\tret = otto_emdio_write_mapping(priv, info-\u003ebus_map_base, port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-734-\t\t\t\t\t\t       MAP_BUSES_PER_REG, MAP_BITS_PER_BUS,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-739-\t\tif (info-\u003eaddr_map_base) {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:740:\t\t\tret = otto_emdio_write_mapping(priv, info-\u003eaddr_map_base, port,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-741-\t\t\t\t\t\t       MAP_ADDRS_PER_REG, MAP_BITS_PER_ADDR,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-750-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:751:static int otto_emdio_8380_set_bus_frequency(struct mii_bus *bus, u32 freq)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-752-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:753:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-754-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-761-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:762:static int otto_emdio_8380_setup_controller(struct otto_emdio_priv *priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-763-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-770-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:771:static int otto_emdio_8390_set_bus_frequency(struct mii_bus *bus, u32 freq)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-772-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:773:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-774-\tu32 val;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-789-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:790:static int otto_emdio_9300_set_bus_frequency(struct mii_bus *bus, u32 freq)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-791-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:792:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:793:\tstruct otto_emdio_chan *chan = bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-794-\tu32 mask, val;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-804-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:805:static int otto_emdio_9300_setup_controller(struct otto_emdio_priv *priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-806-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-824-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:825:static int otto_emdio_9310_set_bus_frequency(struct mii_bus *bus, u32 freq)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-826-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:827:\tstruct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:828:\tstruct otto_emdio_chan *chan = bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-829-\tu32 mask, val;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-839-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:840:static int otto_emdio_9310_setup_controller(struct otto_emdio_priv *priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-841-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-855-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:856:static int otto_emdio_notify_phy_attach(struct phy_device *phydev)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-857-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:858:\tint port = otto_emdio_phy_to_port(phydev-\u003emdio.bus, phydev-\u003emdio.addr);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:859:\tstruct otto_emdio_chan *chan = phydev-\u003emdio.bus-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:860:\tstruct otto_emdio_priv *priv = chan-\u003epriv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-861-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-877-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:878:\treturn otto_emdio_set_port_polling(priv, port, true);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-879-}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-880-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:881:static void otto_emdio_notify_phy_detach(struct phy_device *phydev)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-882-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c-883-\tstruct mii_bus *bus = phydev-\u003emdio.bus;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:884:\tstruct otto_emdio_priv *priv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-885-\tint port;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-886-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:887:\tpriv = otto_emdio_bus_to_priv(phydev-\u003emdio.bus);\ndrivers/net/mdio/mdio-realtek-rtl9300.c:888:\tport = otto_emdio_phy_to_port(phydev-\u003emdio.bus, phydev-\u003emdio.addr);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-889-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-896-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:897:\tif (otto_emdio_set_port_polling(priv, port, false))\ndrivers/net/mdio/mdio-realtek-rtl9300.c-898-\t\tdev_err(bus-\u003eparent, \"failed to disable polling for port %d\\n\", port);\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-900-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:901:static int otto_emdio_probe_one(struct device *dev, struct otto_emdio_priv *priv,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-902-\t\t\t\tstruct device_node *node)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-903-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c:904:\tstruct otto_emdio_chan *chan;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-905-\tstruct mii_bus *bus;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-921-\tbus-\u003ename = \"Realtek Switch MDIO Bus\";\ndrivers/net/mdio/mdio-realtek-rtl9300.c:922:\tbus-\u003eread_c45 = otto_emdio_read_c45;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:923:\tbus-\u003ewrite_c45 = otto_emdio_write_c45;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:924:\tbus-\u003eread = otto_emdio_read_c22;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:925:\tbus-\u003ewrite = otto_emdio_write_c22;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-926-\tbus-\u003eparent = dev;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:927:\tbus-\u003enotify_phy_attach = otto_emdio_notify_phy_attach;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:928:\tbus-\u003enotify_phy_detach = otto_emdio_notify_phy_detach;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-929-\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-949-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:950:static struct device_node *otto_emdio_get_bus_node(struct device_node *dn)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-951-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-968- */\ndrivers/net/mdio/mdio-realtek-rtl9300.c:969:static int otto_emdio_map_ports(struct device *dev)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-970-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c-971-\tstruct device_node *ports_dn, *phy_dn, *bus_dn, *ctrl_dn;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:972:\tstruct otto_emdio_priv *priv = dev_get_drvdata(dev);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-973-\tstruct device *parent = dev-\u003eparent;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-989-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:990:\t\tbus_dn = otto_emdio_get_bus_node(phy_dn);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-991-\t\tif (!bus_dn)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1052-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1053:static int otto_emdio_init_polling(struct otto_emdio_priv *priv)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1054-{\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1057-\tfor (int port = 0; port \u003c priv-\u003einfo-\u003enum_ports; port++) {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1058:\t\terr = otto_emdio_set_port_polling(priv, port, false);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1059-\t\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1065-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1066:static int otto_emdio_probe(struct platform_device *pdev)\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1067-{\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1068-\tstruct device *dev = \u0026pdev-\u003edev;\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1069:\tstruct otto_emdio_priv *priv;\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1070-\tint err;\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1084-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1085:\terr = otto_emdio_init_polling(priv);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1086-\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1090-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1091:\terr = otto_emdio_map_ports(dev);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1092-\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1094-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1095:\terr = otto_emdio_setup_topology(priv);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1096-\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1105-\tfor_each_child_of_node_scoped(dev-\u003eof_node, child) {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1106:\t\terr = otto_emdio_probe_one(dev, priv, child);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1107-\t\tif (err)\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1113-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1114:static const struct otto_emdio_info otto_emdio_8380_info = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1115-\t.addr_map_base = RTL8380_SMI_PORT0_5_ADDR_CTRL,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1128-\t.poll_ctrl = RTL8380_SMI_POLL_CTRL,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1129:\t.set_bus_frequency = otto_emdio_8380_set_bus_frequency,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1130:\t.setup_controller = otto_emdio_8380_setup_controller,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1131:\t.read_c22 = otto_emdio_8380_read_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1132:\t.read_c45 = otto_emdio_8380_read_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1133:\t.write_c22 = otto_emdio_8380_write_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1134:\t.write_c45 = otto_emdio_8380_write_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1135-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1136-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1137:static const struct otto_emdio_info otto_emdio_8390_info = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1138-\t.cmd_fail = RTL8390_PHY_CTRL_FAIL,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1153-\t.poll_ctrl = RTL8390_SMI_PORT_POLLING_CTRL,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1154:\t.set_bus_frequency = otto_emdio_8390_set_bus_frequency,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1155:\t.read_c22 = otto_emdio_8390_read_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1156:\t.read_c45 = otto_emdio_8390_read_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1157:\t.write_c22 = otto_emdio_8390_write_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1158:\t.write_c45 = otto_emdio_8390_write_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1159-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1160-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1161:static const struct otto_emdio_info otto_emdio_9300_info = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1162-\t.addr_map_base = RTL9300_SMI_PORT0_5_ADDR_CTRL,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1176-\t.poll_ctrl = RTL9300_SMI_POLL_CTRL,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1177:\t.set_bus_frequency = otto_emdio_9300_set_bus_frequency,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1178:\t.setup_controller = otto_emdio_9300_setup_controller,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1179:\t.read_c22 = otto_emdio_9300_read_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1180:\t.read_c45 = otto_emdio_9300_read_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1181:\t.write_c22 = otto_emdio_9300_write_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1182:\t.write_c45 = otto_emdio_9300_write_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1183-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1184-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1185:static const struct otto_emdio_info otto_emdio_9310_info = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1186-\t.addr_map_base = RTL9310_SMI_PORT_ADDR_CTRL,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1203-\t.poll_ctrl = RTL9310_SMI_PORT_POLLING_CTRL,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1204:\t.set_bus_frequency = otto_emdio_9310_set_bus_frequency,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1205:\t.setup_controller = otto_emdio_9310_setup_controller,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1206:\t.read_c22 = otto_emdio_9310_read_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1207:\t.read_c45 = otto_emdio_9310_read_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1208:\t.write_c22 = otto_emdio_9310_write_c22,\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1209:\t.write_c45 = otto_emdio_9310_write_c45,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1210-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1211-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1212:static const struct of_device_id otto_emdio_ids[] = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1213:\t{ .compatible = \"realtek,rtl8380-mdio\", .data = \u0026otto_emdio_8380_info },\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1214:\t{ .compatible = \"realtek,rtl8391-mdio\", .data = \u0026otto_emdio_8390_info },\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1215:\t{ .compatible = \"realtek,rtl9301-mdio\", .data = \u0026otto_emdio_9300_info },\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1216:\t{ .compatible = \"realtek,rtl9311-mdio\", .data = \u0026otto_emdio_9310_info },\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1217-\t{}\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1218-};\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1219:MODULE_DEVICE_TABLE(of, otto_emdio_ids);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1220-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1221:static struct platform_driver otto_emdio_driver = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1222:\t.probe = otto_emdio_probe,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1223-\t.driver = {\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1224-\t\t.name = \"mdio-rtl9300\",\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1225:\t\t.of_match_table = otto_emdio_ids,\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1226-\t\t.suppress_bind_attrs = true,\n--\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1229-\ndrivers/net/mdio/mdio-realtek-rtl9300.c:1230:module_platform_driver(otto_emdio_driver);\ndrivers/net/mdio/mdio-realtek-rtl9300.c-1231-\n"
}

							input: 25647
							output: 49
							thoughts: 60

**Diving into the Realtek RTL9300 MDIO Driver Probe**

Alright, let's get down to brass tacks. I need to refresh my memory on the `mdio-realtek-rtl9300.c` driver, specifically the probe function and how it handles the regmap and parent device setup. I know the general architecture, but I need a refresher on the implementation details. Time to go back and check the code.

Okay, let's jump straight to lines 1065 through 1115. That's where the heart of the probe is likely located, the core device initialization. I'll be looking for how the regmap is created and initialized, how the parent device is assigned, and any specific initialization sequences for this Realtek switch. Gotta make sure everything is in order.

{
  "File": "drivers/net/mdio/mdio-realtek-rtl9300.c",
  "FirstLine": 1065,
  "LineCount": 55
}

{
  "Contents": "1065:\t\n1066:\tstatic int otto_emdio_probe(struct platform_device *pdev)\n1067:\t{\n1068:\t\tstruct device *dev = \u0026pdev-\u003edev;\n1069:\t\tstruct otto_emdio_priv *priv;\n1070:\t\tint err;\n1071:\t\n1072:\t\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n1073:\t\tif (!priv)\n1074:\t\t\treturn -ENOMEM;\n1075:\t\n1076:\t\terr = devm_mutex_init(dev, \u0026priv-\u003elock);\n1077:\t\tif (err)\n1078:\t\t\treturn err;\n1079:\t\n1080:\t\tpriv-\u003einfo = device_get_match_data(dev);\n1081:\t\tpriv-\u003eregmap = syscon_node_to_regmap(dev-\u003eparent-\u003eof_node);\n1082:\t\tif (IS_ERR(priv-\u003eregmap))\n1083:\t\t\treturn PTR_ERR(priv-\u003eregmap);\n1084:\t\n1085:\t\terr = otto_emdio_init_polling(priv);\n1086:\t\tif (err)\n1087:\t\t\treturn err;\n1088:\t\n1089:\t\tplatform_set_drvdata(pdev, priv);\n1090:\t\n1091:\t\terr = otto_emdio_map_ports(dev);\n1092:\t\tif (err)\n1093:\t\t\treturn err;\n1094:\t\n1095:\t\terr = otto_emdio_setup_topology(priv);\n1096:\t\tif (err)\n1097:\t\t\treturn err;\n1098:\t\n1099:\t\tif (priv-\u003einfo-\u003esetup_controller) {\n1100:\t\t\terr = priv-\u003einfo-\u003esetup_controller(priv);\n1101:\t\t\tif (err)\n1102:\t\t\t\treturn dev_err_probe(dev, err, \"failed to setup MDIO bus controller\\n\");\n1103:\t\t}\n1104:\t\n1105:\t\tfor_each_child_of_node_scoped(dev-\u003eof_node, child) {\n1106:\t\t\terr = otto_emdio_probe_one(dev, priv, child);\n1107:\t\t\tif (err)\n1108:\t\t\t\treturn err;\n1109:\t\t}\n1110:\t\n1111:\t\treturn 0;\n1112:\t}\n1113:\t\n1114:\tstatic const struct otto_emdio_info otto_emdio_8380_info = {\n1115:\t\t.addr_map_base = RTL8380_SMI_PORT0_5_ADDR_CTRL,\n1116:\t\t.cmd_fail = RTL8380_PHY_CTRL_FAIL,\n1117:\t\t.cmd_read = RTL8380_PHY_CTRL_READ,\n1118:\t\t.cmd_write = RTL8380_PHY_CTRL_WRITE,\n1119:\t\t.cmd_regs = {\n"
}

							input: 26760
							output: 22
							thoughts: 168

**Analyzing the `otto_emdio_driver`**

Okay, let's break this down. `otto_emdio_driver` has `.suppress_bind_attrs = true;` – that's the first thing to note. It's triggered by the `otto_emdio_ids` of the OF. This driver is for those Realtek switches: RTL838x/RTL839x/RTL930x/RTL931x. Essentially, a platform driver for these MIPS-based Otto architecture MACH_REALTEK_RTL SoCs.

Now, hold on... the target architecture is `amd64`. That's a red flag. I need to figure out if `MACH_REALTEK_RTL` is strictly MIPS, or if it's potentially cross-compilable. Can this even *exist* on an amd64 system, or a standard QEMU VM setup? I need to quickly determine where `MACH_REALTEK_RTL` is actually defined, so I can understand the architectural assumptions being made. This feels like an architectural mismatch I need to reconcile.

{
  "Expression": "MACH_REALTEK_RTL"
}

{
  "Output": "arch/mips/Kconfig=681=config RALINK\n--\narch/mips/Kconfig-698-\narch/mips/Kconfig:699:config MACH_REALTEK_RTL\narch/mips/Kconfig-700-\tbool \"Realtek RTL838x/RTL839x based machines\"\n--\narch/mips/boot/dts/realtek/Makefile-1-# SPDX-License-Identifier: GPL-2.0\narch/mips/boot/dts/realtek/Makefile:2:dtb-$(CONFIG_MACH_REALTEK_RTL)\t+= cisco_sg220-26.dtb\narch/mips/boot/dts/realtek/Makefile:3:dtb-$(CONFIG_MACH_REALTEK_RTL)\t+= cameo-rtl9302c-2x-rtl8224-2xge.dtb\n--\narch/mips/generic/Makefile=15=obj-$(CONFIG_VIRT_BOARD_RANCHU)\t\t+= board-ranchu.o\narch/mips/generic/Makefile:16:obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= board-realtek.o\n--\ndrivers/gpio/Kconfig=625=config GPIO_REALTEK_OTTO\ndrivers/gpio/Kconfig-626-\ttristate \"Realtek Otto GPIO support\"\ndrivers/gpio/Kconfig:627:\tdepends on MACH_REALTEK_RTL || COMPILE_TEST\ndrivers/gpio/Kconfig:628:\tdefault MACH_REALTEK_RTL\ndrivers/gpio/Kconfig-629-\tselect GPIO_GENERIC\n--\ndrivers/i2c/busses/Kconfig=1103=config I2C_RTL9300\ndrivers/i2c/busses/Kconfig-1104-\ttristate \"Realtek RTL9300 I2C controller\"\ndrivers/i2c/busses/Kconfig:1105:\tdepends on MACH_REALTEK_RTL || COMPILE_TEST\ndrivers/i2c/busses/Kconfig-1106-\thelp\n--\ndrivers/irqchip/Makefile=130=obj-$(CONFIG_SL28CPLD_INTC)\t\t+= irq-sl28cpld.o\ndrivers/irqchip/Makefile:131:obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= irq-realtek-rtl.o\ndrivers/irqchip/Makefile-132-obj-$(CONFIG_WPCM450_AIC)\t\t+= irq-wpcm450-aic.o\n--\ndrivers/mtd/nand/Kconfig=64=config MTD_NAND_ECC_REALTEK\n--\ndrivers/mtd/nand/Kconfig-66-        depends on HAS_IOMEM \u0026\u0026 HAS_DMA\ndrivers/mtd/nand/Kconfig:67:        depends on MACH_REALTEK_RTL || COMPILE_TEST\ndrivers/mtd/nand/Kconfig-68-        select MTD_NAND_ECC\n--\ndrivers/net/mdio/Kconfig=174=config MDIO_REALTEK_RTL9300\ndrivers/net/mdio/Kconfig-175-\ttristate \"Realtek RTL83xx/RTL93xx MDIO interface support\"\ndrivers/net/mdio/Kconfig:176:\tdepends on MACH_REALTEK_RTL || COMPILE_TEST\ndrivers/net/mdio/Kconfig-177-\thelp\n--\ndrivers/spi/Kconfig=916=config SPI_REALTEK_SNAND\ndrivers/spi/Kconfig-917-\ttristate \"Realtek SPI-NAND Flash Controller\"\ndrivers/spi/Kconfig:918:\tdepends on MACH_REALTEK_RTL || COMPILE_TEST\ndrivers/spi/Kconfig-919-\tselect REGMAP\n--\ndrivers/spi/Makefile=131=obj-$(CONFIG_SPI_RB4XX)\t\t\t+= spi-rb4xx.o\ndrivers/spi/Makefile:132:obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= spi-realtek-rtl.o\ndrivers/spi/Makefile-133-obj-$(CONFIG_SPI_REALTEK_SNAND)\t\t+= spi-realtek-rtl-snand.o\n--\ndrivers/watchdog/Kconfig=1113=config REALTEK_OTTO_WDT\ndrivers/watchdog/Kconfig-1114-\ttristate \"Realtek Otto MIPS watchdog support\"\ndrivers/watchdog/Kconfig:1115:\tdepends on MACH_REALTEK_RTL || COMPILE_TEST\ndrivers/watchdog/Kconfig-1116-\tdepends on COMMON_CLK\n--\ndrivers/watchdog/Kconfig-1118-\tselect REGMAP_MMIO\ndrivers/watchdog/Kconfig:1119:\tdefault MACH_REALTEK_RTL\ndrivers/watchdog/Kconfig-1120-\thelp\n"
}

							input: 28453
							output: 166
							thoughts: 893

**Reachability Analysis: WorthFuzzing=false**

Okay, let's break this down. My goal is to determine if this patch is worth fuzzing, and the primary gate is reachability. I'm targeting the amd64 architecture, so I need to assess if the modified code is actually *executable* in standard virtualized environments like QEMU or GCE.

First, I identified some negative criteria. Specifically, I'm looking for "structurally unreachable hardware" – code tied to hardware not emulated in standard environments or architecture-exclusive code.

I need to confirm if this `mdio-realtek-rtl9300` driver is actually *reachable*. My initial thought is it's an MDIO controller driver for Realtek RTL838x/93xx MIPS SoCs, which immediately raises a red flag.

I dove into `mdio-realtek-rtl9300.c` itself. It’s a platform driver, so it’s linked to specific hardware. Critically, `suppress_bind_attrs = true` means I can't even manually force it to bind. It relies on a syscon node, obtained via `syscon_node_to_regmap`, meaning its tied to specific hardware. And it's for Realtek's MIPS SoC architecture. The target is amd64. Therefore, it's structurally unreachable. It's an arch-exclusive MIPS SoC driver that can't be used on amd64 in any standard environment.

Let's double-check the triage guidelines. They're crystal clear: "If the modified code is structurally unreachable… it MUST NOT be fuzzed." The guidelines specifically mention vendor-specific PCIe switches and architecture-exclusive code paths as examples. That is exactly what I have.

So, the files affected are: documentation and the driver. The driver, `mdio-realtek-rtl9300.c`, is the critical element. It's for a specific Realtek MIPS SoC and is not reachable on amd64.

Based on this, I'm setting `WorthFuzzing` to `false`. The reasoning is straightforward: the driver targets a specific Realtek MIPS SoC. It cannot execute in any standard amd64 environment. The `FocusSymbols` and `EnableConfigs` are irrelevant here. Time to submit this.

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch updates Devicetree bindings documentation and adds MDIO bus clock frequency configuration support to the Realtek RTL838x/RTL839x/RTL930x/RTL931x MDIO controller driver (drivers/net/mdio/mdio-realtek-rtl9300.c). This driver is designed specifically for Realtek Otto MIPS switch SoCs (CONFIG_MACH_REALTEK_RTL), requires OF syscon parent nodes, suppresses manual driver binding via sysfs, and cannot be probed or executed in standard amd64 QEMU/GCE virtualization environments.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch updates Devicetree bindings documentation and adds MDIO bus clock frequency configuration support to the Realtek RTL838x/RTL839x/RTL930x/RTL931x MDIO controller driver (drivers/net/mdio/mdio-realtek-rtl9300.c). This driver is designed specifically for Realtek Otto MIPS switch SoCs (CONFIG_MACH_REALTEK_RTL), requires OF syscon parent nodes, suppresses manual driver binding via sysfs, and cannot be probed or executed in standard amd64 QEMU/GCE virtualization environments.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

LLM Calls Summary:
Total Calls	Total Tokens	Avg Tokens	Total Duration (Seconds)	Avg Duration (Seconds)

Tool Calls Summary:
Total Calls	Total Duration (Seconds)	Avg Duration (Seconds)