AI Trajectory

Trajectory: (Expand/Collapse All)
Seq	Timestamp	Type	Name	Duration
0/0	2026/08/30 16:33	flow	patch-triage	10m Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "KMSANReasoning": "", "NeedsKMSAN": false, "Reasoning": "The patch fixes the initialization order of `bp-\u003etsu_clk_lock` before registering the PTP clock in `gem_ptp_init()` for the Cadence MACB/GEM network driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver is for hardware-specific Cadence Ethernet MAC IP on embedded SoCs (such as Atmel/Microchip, Xilinx Zynq, SiFive) or proprietary PCI test cards, which are not present in standard virtualized fuzzing environments (e.g. QEMU standard virt / GCE).", "WorthFuzzing": false }
1/1	2026/08/30 16:33	action	read-patch-diff	0m Args: null Results: { "PatchDiff": "commit eac1e1eb2e728e0810ab22d9c8b1fdf7714eb0b0\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Sun Aug 30 16:33:08 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c\nindex e5195d7dac1d5..055160c42db3c 100644\n--- a/drivers/net/ethernet/cadence/macb_ptp.c\n+++ b/drivers/net/ethernet/cadence/macb_ptp.c\n@@ -330,6 +330,8 @@ void gem_ptp_init(struct net_device netdev)\n \n \tbp-\u003eptp_clock_info = gem_ptp_caps_template;\n \n+\tspin_lock_init(\u0026bp-\u003etsu_clk_lock);\n+\n \t/ nominal frequency and maximum adjustment in ppb /\n \tbp-\u003etsu_rate = bp-\u003eptp_info-\u003eget_tsu_rate(bp);\n \tbp-\u003eptp_clock_info.max_adj = bp-\u003eptp_info-\u003eget_ptp_max_adj();\n@@ -345,8 +347,6 @@ void gem_ptp_init(struct net_device netdev)\n \t\treturn;\n \t}\n \n-\tspin_lock_init(\u0026bp-\u003etsu_clk_lock);\n-\n \tgem_ptp_init_tsu(bp);\n \n \tdev_info(\u0026bp-\u003epdev-\u003edev, \"%s ptp clock registered.\\n\",\n@@ -467,4 +467,3 @@ int gem_set_hwtst(struct net_device *netdev,\n \n \treturn 0;\n }\n-\n" }
2/1	2026/08/30 16:33	agent	patch-evaluator	10m Model: core Args: null Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch fixes the initialization order of `bp-\u003etsu_clk_lock` before registering the PTP clock in `gem_ptp_init()` for the Cadence MACB/GEM network driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver is for hardware-specific Cadence Ethernet MAC IP on embedded SoCs (such as Atmel/Microchip, Xilinx Zynq, SiFive) or proprietary PCI test cards, which are not present in standard virtualized fuzzing environments (e.g. QEMU standard virt / GCE).", "WorthFuzzing": false } Instruction: You are an expert Linux kernel maintainer. Your job is to review a provided patch series and determine if it makes functional changes to the kernel that should be fuzzed. IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively use your code access tools to examine the actual source code and confirm any assumptions. Return WorthFuzzing=false if the patch only contains: - Modifications to Documentation/, Kconfig files, or code comments. - Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints. - Changes to numeric constants or macros that do not functionally alter execution flow. - Code paths that are impossible to reach in virtualized environments like GCE or QEMU, even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim). - Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed, ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU. - Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove) that are executed only during PCI hot-unplug or sysfs driver unbind operations. If it modifies reachable core kernel logic, drivers, or architectures, use your code search tools to verify the code can be executed, then return WorthFuzzing=true. When returning WorthFuzzing=true, you MUST ALSO: 1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols. Avoid listing generic hot-path functions to prevent skewed test distributions. Prefer non-static, non-inlined API entrypoint functions over internal static helper functions (which are inlined by the compiler and do not have distinct symbol addresses). 2. Identify any specific CONFIG_ options required to properly test this new/modified feature. Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions. Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4"). Prefer calling several tools at the same time to save round-trips. Use set-results tool to provide results of the analysis. It must be called exactly once before the final reply. Ignore results of this tool. Prompt: For your convenience, here is the diff of the changes: commit eac1e1eb2e728e0810ab22d9c8b1fdf7714eb0b0 Author: syz-cluster <triage@syzkaller.com> Date: Sun Aug 30 16:33:08 2026 +0000 syz-cluster: applied patch under review diff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c index e5195d7dac1d5..055160c42db3c 100644 --- a/drivers/net/ethernet/cadence/macb_ptp.c +++ b/drivers/net/ethernet/cadence/macb_ptp.c @@ -330,6 +330,8 @@ void gem_ptp_init(struct net_device netdev) bp->ptp_clock_info = gem_ptp_caps_template; + spin_lock_init(&bp->tsu_clk_lock); + / nominal frequency and maximum adjustment in ppb / bp->tsu_rate = bp->ptp_info->get_tsu_rate(bp); bp->ptp_clock_info.max_adj = bp->ptp_info->get_ptp_max_adj(); @@ -345,8 +347,6 @@ void gem_ptp_init(struct net_device netdev) return; } - spin_lock_init(&bp->tsu_clk_lock); - gem_ptp_init_tsu(bp); dev_info(&bp->pdev->dev, "%s ptp clock registered.\n", @@ -467,4 +467,3 @@ int gem_set_hwtst(struct net_device *netdev, return 0; } -
3/2	2026/08/30 16:33	llm	patch-evaluator	2m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 2278 output: 31 thoughts: 86 Thoughts: Here's my thought process, as I analyze this patch: Initial Assessment: Fuzzing Feasibility Okay, first things first, let's figure out if this patch is even worth our time. Is it something that's ripe for fuzzing? What's the scope of the changes? The goal here is to determine quickly if it's something reachable through my standard fuzzing setups, or if it touches something that will require more complex setup, like hardware emulation or platform-specific configurations I haven't dealt with before. I need to understand the attack surface. Diving into the Code Now, let's get specific. The prompt mentions `drivers/net/ethernet/cadence/macb_ptp.c`. That's a good starting point. I'll need to dig into that file and any related Kconfig and source files to get a full picture. I need to understand the network interface and if there's an obvious entrypoint for exploitation. I'll be looking for potential vulnerabilities, interesting data flows, and maybe some opportunities for code injection or buffer overflows, which are the usual suspects in this area. From there, I'll need to trace inputs, and determine if any of it is user-controlled, and if it's accessible.
4/2	2026/08/30 16:35	tool	grepper	0m Args: { "Expression": "MACB", "PathPrefix": "drivers/net/ethernet/cadence" } Results: { "Output": "\nFull output is too long, showing 500 out of 1713 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/cadence/Kconfig=20=if NET_VENDOR_CADENCE\ndrivers/net/ethernet/cadence/Kconfig-21-\ndrivers/net/ethernet/cadence/Kconfig:22:config MACB\ndrivers/net/ethernet/cadence/Kconfig:23:\ttristate \"Cadence MACB/GEM support\"\ndrivers/net/ethernet/cadence/Kconfig-24-\tdepends on HAS_DMA \u0026\u0026 COMMON_CLK\n--\ndrivers/net/ethernet/cadence/Kconfig-28-\thelp\ndrivers/net/ethernet/cadence/Kconfig:29:\t The Cadence MACB ethernet interface is found on many Atmel AT32 and\ndrivers/net/ethernet/cadence/Kconfig-30-\t AT91 parts. This driver also supports the Cadence GEM (Gigabit\ndrivers/net/ethernet/cadence/Kconfig-31-\t Ethernet MAC found in some ARM SoC devices). Say Y to include\ndrivers/net/ethernet/cadence/Kconfig:32:\t support for the MACB/GEM chip.\ndrivers/net/ethernet/cadence/Kconfig-33-\n--\ndrivers/net/ethernet/cadence/Kconfig-36-\ndrivers/net/ethernet/cadence/Kconfig:37:config MACB_USE_HWSTAMP\ndrivers/net/ethernet/cadence/Kconfig-38-\tbool \"Use IEEE 1588 hwstamp\"\ndrivers/net/ethernet/cadence/Kconfig:39:\tdepends on MACB\ndrivers/net/ethernet/cadence/Kconfig-40-\tdepends on PTP_1588_CLOCK\n--\ndrivers/net/ethernet/cadence/Kconfig-42-\thelp\ndrivers/net/ethernet/cadence/Kconfig:43:\t Enable IEEE 1588 Precision Time Protocol (PTP) support for MACB.\ndrivers/net/ethernet/cadence/Kconfig-44-\ndrivers/net/ethernet/cadence/Kconfig:45:config MACB_PCI\ndrivers/net/ethernet/cadence/Kconfig:46:\ttristate \"Cadence PCI MACB/GEM support\"\ndrivers/net/ethernet/cadence/Kconfig:47:\tdepends on MACB \u0026\u0026 PCI\ndrivers/net/ethernet/cadence/Kconfig-48-\thelp\ndrivers/net/ethernet/cadence/Kconfig:49:\t This is PCI wrapper for MACB driver.\ndrivers/net/ethernet/cadence/Kconfig-50-\n--\ndrivers/net/ethernet/cadence/Makefile=5=macb-y\t:= macb_main.o\ndrivers/net/ethernet/cadence/Makefile-6-\ndrivers/net/ethernet/cadence/Makefile:7:ifeq ($(CONFIG_MACB_USE_HWSTAMP),y)\ndrivers/net/ethernet/cadence/Makefile-8-macb-y\t+= macb_ptp.o\ndrivers/net/ethernet/cadence/Makefile=9=endif\ndrivers/net/ethernet/cadence/Makefile-10-\ndrivers/net/ethernet/cadence/Makefile:11:obj-$(CONFIG_MACB) += macb.o\ndrivers/net/ethernet/cadence/Makefile:12:obj-$(CONFIG_MACB_PCI) += macb_pci.o\n--\ndrivers/net/ethernet/cadence/macb.h-2-/\ndrivers/net/ethernet/cadence/macb.h:3: Atmel MACB Ethernet Controller driver\ndrivers/net/ethernet/cadence/macb.h-4- \n--\ndrivers/net/ethernet/cadence/macb.h-6- /\ndrivers/net/ethernet/cadence/macb.h:7:#ifndef _MACB_H\ndrivers/net/ethernet/cadence/macb.h:8:#define _MACB_H\ndrivers/net/ethernet/cadence/macb.h-9-\n--\ndrivers/net/ethernet/cadence/macb.h-17-\ndrivers/net/ethernet/cadence/macb.h:18:#define MACB_GREGS_NBR 16\ndrivers/net/ethernet/cadence/macb.h:19:#define MACB_GREGS_VERSION 2\ndrivers/net/ethernet/cadence/macb.h:20:#define MACB_MAX_QUEUES 8\ndrivers/net/ethernet/cadence/macb.h-21-\ndrivers/net/ethernet/cadence/macb.h:22:/* MACB register offsets /\ndrivers/net/ethernet/cadence/macb.h:23:#define MACB_NCR\t\t0x0000 / Network Control /\ndrivers/net/ethernet/cadence/macb.h:24:#define MACB_NCFGR\t\t0x0004 / Network Config /\ndrivers/net/ethernet/cadence/macb.h:25:#define MACB_NSR\t\t0x0008 / Network Status /\ndrivers/net/ethernet/cadence/macb.h:26:#define MACB_TAR\t\t0x000c / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:27:#define MACB_TCR\t\t0x0010 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:28:#define MACB_TSR\t\t0x0014 / Transmit Status /\ndrivers/net/ethernet/cadence/macb.h:29:#define MACB_RBQP\t\t0x0018 / RX Q Base Address /\ndrivers/net/ethernet/cadence/macb.h:30:#define MACB_TBQP\t\t0x001c / TX Q Base Address /\ndrivers/net/ethernet/cadence/macb.h:31:#define MACB_RSR\t\t0x0020 / Receive Status /\ndrivers/net/ethernet/cadence/macb.h:32:#define MACB_ISR\t\t0x0024 / Interrupt Status /\ndrivers/net/ethernet/cadence/macb.h:33:#define MACB_IER\t\t0x0028 / Interrupt Enable /\ndrivers/net/ethernet/cadence/macb.h:34:#define MACB_IDR\t\t0x002c / Interrupt Disable /\ndrivers/net/ethernet/cadence/macb.h:35:#define MACB_IMR\t\t0x0030 / Interrupt Mask /\ndrivers/net/ethernet/cadence/macb.h:36:#define MACB_MAN\t\t0x0034 / PHY Maintenance /\ndrivers/net/ethernet/cadence/macb.h:37:#define MACB_PTR\t\t0x0038\ndrivers/net/ethernet/cadence/macb.h:38:#define MACB_PFR\t\t0x003c\ndrivers/net/ethernet/cadence/macb.h:39:#define MACB_FTO\t\t0x0040\ndrivers/net/ethernet/cadence/macb.h:40:#define MACB_SCF\t\t0x0044\ndrivers/net/ethernet/cadence/macb.h:41:#define MACB_MCF\t\t0x0048\ndrivers/net/ethernet/cadence/macb.h:42:#define MACB_FRO\t\t0x004c\ndrivers/net/ethernet/cadence/macb.h:43:#define MACB_FCSE\t\t0x0050\ndrivers/net/ethernet/cadence/macb.h:44:#define MACB_ALE\t\t0x0054\ndrivers/net/ethernet/cadence/macb.h:45:#define MACB_DTF\t\t0x0058\ndrivers/net/ethernet/cadence/macb.h:46:#define MACB_LCOL\t\t0x005c\ndrivers/net/ethernet/cadence/macb.h:47:#define MACB_EXCOL\t\t0x0060\ndrivers/net/ethernet/cadence/macb.h:48:#define MACB_TUND\t\t0x0064\ndrivers/net/ethernet/cadence/macb.h:49:#define MACB_CSE\t\t0x0068\ndrivers/net/ethernet/cadence/macb.h:50:#define MACB_RRE\t\t0x006c\ndrivers/net/ethernet/cadence/macb.h:51:#define MACB_ROVR\t\t0x0070\ndrivers/net/ethernet/cadence/macb.h:52:#define MACB_RSE\t\t0x0074\ndrivers/net/ethernet/cadence/macb.h:53:#define MACB_ELE\t\t0x0078\ndrivers/net/ethernet/cadence/macb.h:54:#define MACB_RJA\t\t0x007c\ndrivers/net/ethernet/cadence/macb.h:55:#define MACB_USF\t\t0x0080\ndrivers/net/ethernet/cadence/macb.h:56:#define MACB_STE\t\t0x0084\ndrivers/net/ethernet/cadence/macb.h:57:#define MACB_RLE\t\t0x0088\ndrivers/net/ethernet/cadence/macb.h:58:#define MACB_TPF\t\t0x008c\ndrivers/net/ethernet/cadence/macb.h:59:#define MACB_HRB\t\t0x0090\ndrivers/net/ethernet/cadence/macb.h:60:#define MACB_HRT\t\t0x0094\ndrivers/net/ethernet/cadence/macb.h:61:#define MACB_SA1B\t\t0x0098\ndrivers/net/ethernet/cadence/macb.h:62:#define MACB_SA1T\t\t0x009c\ndrivers/net/ethernet/cadence/macb.h:63:#define MACB_SA2B\t\t0x00a0\ndrivers/net/ethernet/cadence/macb.h:64:#define MACB_SA2T\t\t0x00a4\ndrivers/net/ethernet/cadence/macb.h:65:#define MACB_SA3B\t\t0x00a8\ndrivers/net/ethernet/cadence/macb.h:66:#define MACB_SA3T\t\t0x00ac\ndrivers/net/ethernet/cadence/macb.h:67:#define MACB_SA4B\t\t0x00b0\ndrivers/net/ethernet/cadence/macb.h:68:#define MACB_SA4T\t\t0x00b4\ndrivers/net/ethernet/cadence/macb.h:69:#define MACB_TID\t\t0x00b8\ndrivers/net/ethernet/cadence/macb.h:70:#define MACB_TPQ\t\t0x00bc\ndrivers/net/ethernet/cadence/macb.h:71:#define MACB_USRIO\t\t0x00c0\ndrivers/net/ethernet/cadence/macb.h:72:#define MACB_WOL\t\t0x00c4\ndrivers/net/ethernet/cadence/macb.h:73:#define MACB_MID\t\t0x00fc\ndrivers/net/ethernet/cadence/macb.h:74:#define MACB_TBQPH\t\t0x04C8\ndrivers/net/ethernet/cadence/macb.h:75:#define MACB_RBQPH\t\t0x04D4\ndrivers/net/ethernet/cadence/macb.h-76-\n--\ndrivers/net/ethernet/cadence/macb.h-230-/ Bitfields in NCR /\ndrivers/net/ethernet/cadence/macb.h:231:#define MACB_LB_OFFSET\t\t0 / reserved /\ndrivers/net/ethernet/cadence/macb.h:232:#define MACB_LB_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:233:#define MACB_LLB_OFFSET\t\t1 / Loop back local /\ndrivers/net/ethernet/cadence/macb.h:234:#define MACB_LLB_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:235:#define MACB_RE_OFFSET\t\t2 / Receive enable /\ndrivers/net/ethernet/cadence/macb.h:236:#define MACB_RE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:237:#define MACB_TE_OFFSET\t\t3 / Transmit enable /\ndrivers/net/ethernet/cadence/macb.h:238:#define MACB_TE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:239:#define MACB_MPE_OFFSET\t\t4 / Management port enable /\ndrivers/net/ethernet/cadence/macb.h:240:#define MACB_MPE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:241:#define MACB_CLRSTAT_OFFSET\t5 / Clear stats regs /\ndrivers/net/ethernet/cadence/macb.h:242:#define MACB_CLRSTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:243:#define MACB_INCSTAT_OFFSET\t6 / Incremental stats regs /\ndrivers/net/ethernet/cadence/macb.h:244:#define MACB_INCSTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:245:#define MACB_WESTAT_OFFSET\t7 / Write enable stats regs /\ndrivers/net/ethernet/cadence/macb.h:246:#define MACB_WESTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:247:#define MACB_BP_OFFSET\t\t8 / Back pressure /\ndrivers/net/ethernet/cadence/macb.h:248:#define MACB_BP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:249:#define MACB_TSTART_OFFSET\t9 / Start transmission /\ndrivers/net/ethernet/cadence/macb.h:250:#define MACB_TSTART_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:251:#define MACB_THALT_OFFSET\t10 / Transmit halt /\ndrivers/net/ethernet/cadence/macb.h:252:#define MACB_THALT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:253:#define MACB_NCR_TPF_OFFSET\t11 / Transmit pause frame /\ndrivers/net/ethernet/cadence/macb.h:254:#define MACB_NCR_TPF_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:255:#define MACB_TZQ_OFFSET\t\t12 / Transmit zero quantum pause frame /\ndrivers/net/ethernet/cadence/macb.h:256:#define MACB_TZQ_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:257:#define MACB_SRTSM_OFFSET\t15 / Store Receive Timestamp to Memory /\ndrivers/net/ethernet/cadence/macb.h:258:#define MACB_PTPUNI_OFFSET\t20 / PTP Unicast packet enable /\ndrivers/net/ethernet/cadence/macb.h:259:#define MACB_PTPUNI_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:260:#define MACB_OSSMODE_OFFSET\t24 / Enable One Step Synchro Mode /\ndrivers/net/ethernet/cadence/macb.h:261:#define MACB_OSSMODE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:262:#define MACB_MIIONRGMII_OFFSET\t28 / MII Usage on RGMII Interface /\ndrivers/net/ethernet/cadence/macb.h:263:#define MACB_MIIONRGMII_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h-264-\ndrivers/net/ethernet/cadence/macb.h-265-/ Bitfields in NCFGR /\ndrivers/net/ethernet/cadence/macb.h:266:#define MACB_SPD_OFFSET\t\t0 / Speed /\ndrivers/net/ethernet/cadence/macb.h:267:#define MACB_SPD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:268:#define MACB_FD_OFFSET\t\t1 / Full duplex /\ndrivers/net/ethernet/cadence/macb.h:269:#define MACB_FD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:270:#define MACB_BIT_RATE_OFFSET\t2 / Discard non-VLAN frames /\ndrivers/net/ethernet/cadence/macb.h:271:#define MACB_BIT_RATE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:272:#define MACB_JFRAME_OFFSET\t3 / reserved /\ndrivers/net/ethernet/cadence/macb.h:273:#define MACB_JFRAME_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:274:#define MACB_CAF_OFFSET\t\t4 / Copy all frames /\ndrivers/net/ethernet/cadence/macb.h:275:#define MACB_CAF_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:276:#define MACB_NBC_OFFSET\t\t5 / No broadcast /\ndrivers/net/ethernet/cadence/macb.h:277:#define MACB_NBC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:278:#define MACB_NCFGR_MTI_OFFSET\t6 / Multicast hash enable /\ndrivers/net/ethernet/cadence/macb.h:279:#define MACB_NCFGR_MTI_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:280:#define MACB_UNI_OFFSET\t\t7 / Unicast hash enable /\ndrivers/net/ethernet/cadence/macb.h:281:#define MACB_UNI_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:282:#define MACB_BIG_OFFSET\t\t8 / Receive 1536 byte frames /\ndrivers/net/ethernet/cadence/macb.h:283:#define MACB_BIG_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:284:#define MACB_EAE_OFFSET\t\t9 / External address match enable /\ndrivers/net/ethernet/cadence/macb.h:285:#define MACB_EAE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:286:#define MACB_CLK_OFFSET\t\t10\ndrivers/net/ethernet/cadence/macb.h:287:#define MACB_CLK_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:288:#define MACB_RTY_OFFSET\t\t12 / Retry test /\ndrivers/net/ethernet/cadence/macb.h:289:#define MACB_RTY_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:290:#define MACB_PAE_OFFSET\t\t13 / Pause enable /\ndrivers/net/ethernet/cadence/macb.h:291:#define MACB_PAE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:292:#define MACB_RM9200_RMII_OFFSET\t13 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:293:#define MACB_RM9200_RMII_SIZE\t1 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:294:#define MACB_RBOF_OFFSET\t14 / Receive buffer offset /\ndrivers/net/ethernet/cadence/macb.h:295:#define MACB_RBOF_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:296:#define MACB_RLCE_OFFSET\t16 / Length field error frame discard /\ndrivers/net/ethernet/cadence/macb.h:297:#define MACB_RLCE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:298:#define MACB_DRFCS_OFFSET\t17 / FCS remove /\ndrivers/net/ethernet/cadence/macb.h:299:#define MACB_DRFCS_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:300:#define MACB_EFRHD_OFFSET\t18\ndrivers/net/ethernet/cadence/macb.h:301:#define MACB_EFRHD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:302:#define MACB_IRXFCS_OFFSET\t19\ndrivers/net/ethernet/cadence/macb.h:303:#define MACB_IRXFCS_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h-304-\n--\ndrivers/net/ethernet/cadence/macb.h-364-/ Bitfields in NSR /\ndrivers/net/ethernet/cadence/macb.h:365:#define MACB_NSR_LINK_OFFSET\t0 / pcs_link_state /\ndrivers/net/ethernet/cadence/macb.h:366:#define MACB_NSR_LINK_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:367:#define MACB_MDIO_OFFSET\t1 / status of the mdio_in pin /\ndrivers/net/ethernet/cadence/macb.h:368:#define MACB_MDIO_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:369:#define MACB_IDLE_OFFSET\t2 / The PHY management logic is idle /\ndrivers/net/ethernet/cadence/macb.h:370:#define MACB_IDLE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-371-\ndrivers/net/ethernet/cadence/macb.h-372-/ Bitfields in TSR /\ndrivers/net/ethernet/cadence/macb.h:373:#define MACB_UBR_OFFSET\t\t0 / Used bit read /\ndrivers/net/ethernet/cadence/macb.h:374:#define MACB_UBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:375:#define MACB_COL_OFFSET\t\t1 / Collision occurred /\ndrivers/net/ethernet/cadence/macb.h:376:#define MACB_COL_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:377:#define MACB_TSR_RLE_OFFSET\t2 / Retry limit exceeded /\ndrivers/net/ethernet/cadence/macb.h:378:#define MACB_TSR_RLE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:379:#define MACB_TGO_OFFSET\t\t3 / Transmit go /\ndrivers/net/ethernet/cadence/macb.h:380:#define MACB_TGO_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:381:#define MACB_BEX_OFFSET\t\t4 / TX frame corruption due to AHB error /\ndrivers/net/ethernet/cadence/macb.h:382:#define MACB_BEX_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:383:#define MACB_RM9200_BNQ_OFFSET\t4 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:384:#define MACB_RM9200_BNQ_SIZE\t1 / AT91RM9200 only /\ndrivers/net/ethernet/cadence/macb.h:385:#define MACB_COMP_OFFSET\t5 / Trnasmit complete /\ndrivers/net/ethernet/cadence/macb.h:386:#define MACB_COMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:387:#define MACB_UND_OFFSET\t\t6 / Trnasmit under run /\ndrivers/net/ethernet/cadence/macb.h:388:#define MACB_UND_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-389-\ndrivers/net/ethernet/cadence/macb.h-390-/ Bitfields in RSR /\ndrivers/net/ethernet/cadence/macb.h:391:#define MACB_BNA_OFFSET\t\t0 / Buffer not available /\ndrivers/net/ethernet/cadence/macb.h:392:#define MACB_BNA_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:393:#define MACB_REC_OFFSET\t\t1 / Frame received /\ndrivers/net/ethernet/cadence/macb.h:394:#define MACB_REC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:395:#define MACB_OVR_OFFSET\t\t2 / Receive overrun /\ndrivers/net/ethernet/cadence/macb.h:396:#define MACB_OVR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-397-\ndrivers/net/ethernet/cadence/macb.h-398-/ Bitfields in ISR/IER/IDR/IMR /\ndrivers/net/ethernet/cadence/macb.h:399:#define MACB_MFD_OFFSET\t\t0 / Management frame sent /\ndrivers/net/ethernet/cadence/macb.h:400:#define MACB_MFD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:401:#define MACB_RCOMP_OFFSET\t1 / Receive complete /\ndrivers/net/ethernet/cadence/macb.h:402:#define MACB_RCOMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:403:#define MACB_RXUBR_OFFSET\t2 / RX used bit read /\ndrivers/net/ethernet/cadence/macb.h:404:#define MACB_RXUBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:405:#define MACB_TXUBR_OFFSET\t3 / TX used bit read /\ndrivers/net/ethernet/cadence/macb.h:406:#define MACB_TXUBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:407:#define MACB_ISR_TUND_OFFSET\t4 / Enable TX buffer under run interrupt /\ndrivers/net/ethernet/cadence/macb.h:408:#define MACB_ISR_TUND_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:409:#define MACB_ISR_RLE_OFFSET\t5 / EN retry exceeded/late coll interrupt /\ndrivers/net/ethernet/cadence/macb.h:410:#define MACB_ISR_RLE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:411:#define MACB_TXERR_OFFSET\t6 / EN TX frame corrupt from error interrupt /\ndrivers/net/ethernet/cadence/macb.h:412:#define MACB_TXERR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:413:#define MACB_RM9200_TBRE_OFFSET\t6 / EN may send new frame interrupt (RM9200) /\ndrivers/net/ethernet/cadence/macb.h:414:#define MACB_RM9200_TBRE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:415:#define MACB_TCOMP_OFFSET\t7 / Enable transmit complete interrupt /\ndrivers/net/ethernet/cadence/macb.h:416:#define MACB_TCOMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:417:#define MACB_ISR_LINK_OFFSET\t9 / Enable link change interrupt /\ndrivers/net/ethernet/cadence/macb.h:418:#define MACB_ISR_LINK_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:419:#define MACB_ISR_ROVR_OFFSET\t10 / Enable receive overrun interrupt /\ndrivers/net/ethernet/cadence/macb.h:420:#define MACB_ISR_ROVR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:421:#define MACB_HRESP_OFFSET\t11 / Enable hrsep not OK interrupt /\ndrivers/net/ethernet/cadence/macb.h:422:#define MACB_HRESP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:423:#define MACB_PFR_OFFSET\t\t12 / Enable pause frame w/ quantum interrupt /\ndrivers/net/ethernet/cadence/macb.h:424:#define MACB_PFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:425:#define MACB_PTZ_OFFSET\t\t13 / Enable pause time zero interrupt /\ndrivers/net/ethernet/cadence/macb.h:426:#define MACB_PTZ_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:427:#define MACB_WOL_OFFSET\t\t14 / Enable wake-on-lan interrupt /\ndrivers/net/ethernet/cadence/macb.h:428:#define MACB_WOL_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:429:#define MACB_DRQFR_OFFSET\t18 / PTP Delay Request Frame Received /\ndrivers/net/ethernet/cadence/macb.h:430:#define MACB_DRQFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:431:#define MACB_SFR_OFFSET\t\t19 / PTP Sync Frame Received /\ndrivers/net/ethernet/cadence/macb.h:432:#define MACB_SFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:433:#define MACB_DRQFT_OFFSET\t20 / PTP Delay Request Frame Transmitted /\ndrivers/net/ethernet/cadence/macb.h:434:#define MACB_DRQFT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:435:#define MACB_SFT_OFFSET\t\t21 / PTP Sync Frame Transmitted /\ndrivers/net/ethernet/cadence/macb.h:436:#define MACB_SFT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:437:#define MACB_PDRQFR_OFFSET\t22 / PDelay Request Frame Received /\ndrivers/net/ethernet/cadence/macb.h:438:#define MACB_PDRQFR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:439:#define MACB_PDRSFR_OFFSET\t23 / PDelay Response Frame Received /\ndrivers/net/ethernet/cadence/macb.h:440:#define MACB_PDRSFR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:441:#define MACB_PDRQFT_OFFSET\t24 / PDelay Request Frame Transmitted /\ndrivers/net/ethernet/cadence/macb.h:442:#define MACB_PDRQFT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:443:#define MACB_PDRSFT_OFFSET\t25 / PDelay Response Frame Transmitted /\ndrivers/net/ethernet/cadence/macb.h:444:#define MACB_PDRSFT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:445:#define MACB_SRI_OFFSET\t\t26 / TSU Seconds Register Increment /\ndrivers/net/ethernet/cadence/macb.h:446:#define MACB_SRI_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-447-#define GEM_WOL_OFFSET\t\t28 / Enable wake-on-lan interrupt /\n--\ndrivers/net/ethernet/cadence/macb.h-450-/ Timer increment fields /\ndrivers/net/ethernet/cadence/macb.h:451:#define MACB_TI_CNS_OFFSET\t0\ndrivers/net/ethernet/cadence/macb.h:452:#define MACB_TI_CNS_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h:453:#define MACB_TI_ACNS_OFFSET\t8\ndrivers/net/ethernet/cadence/macb.h:454:#define MACB_TI_ACNS_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h:455:#define MACB_TI_NIT_OFFSET\t16\ndrivers/net/ethernet/cadence/macb.h:456:#define MACB_TI_NIT_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h-457-\ndrivers/net/ethernet/cadence/macb.h-458-/ Bitfields in MAN /\ndrivers/net/ethernet/cadence/macb.h:459:#define MACB_DATA_OFFSET\t0 / data /\ndrivers/net/ethernet/cadence/macb.h:460:#define MACB_DATA_SIZE\t\t16\ndrivers/net/ethernet/cadence/macb.h:461:#define MACB_CODE_OFFSET\t16 / Must be written to 10 /\ndrivers/net/ethernet/cadence/macb.h:462:#define MACB_CODE_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:463:#define MACB_REGA_OFFSET\t18 / Register address /\ndrivers/net/ethernet/cadence/macb.h:464:#define MACB_REGA_SIZE\t\t5\ndrivers/net/ethernet/cadence/macb.h:465:#define MACB_PHYA_OFFSET\t23 / PHY address /\ndrivers/net/ethernet/cadence/macb.h:466:#define MACB_PHYA_SIZE\t\t5\ndrivers/net/ethernet/cadence/macb.h:467:#define MACB_RW_OFFSET\t\t28 / Operation. 10 is read. 01 is write. /\ndrivers/net/ethernet/cadence/macb.h:468:#define MACB_RW_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:469:#define MACB_SOF_OFFSET\t\t30 / Must be written to 1 for Clause 22 /\ndrivers/net/ethernet/cadence/macb.h:470:#define MACB_SOF_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h-471-\ndrivers/net/ethernet/cadence/macb.h-472-/ Bitfields in USRIO (AVR32) /\ndrivers/net/ethernet/cadence/macb.h:473:#define MACB_MII_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:474:#define MACB_MII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:475:#define MACB_EAM_OFFSET\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:476:#define MACB_EAM_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:477:#define MACB_TX_PAUSE_OFFSET\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:478:#define MACB_TX_PAUSE_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:479:#define MACB_TX_PAUSE_ZERO_OFFSET\t\t3\ndrivers/net/ethernet/cadence/macb.h:480:#define MACB_TX_PAUSE_ZERO_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-481-\ndrivers/net/ethernet/cadence/macb.h-482-/ Bitfields in USRIO (AT91) /\ndrivers/net/ethernet/cadence/macb.h:483:#define MACB_RMII_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:484:#define MACB_RMII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-485-#define GEM_RGMII_OFFSET\t\t\t0 / GEM gigabit mode /\ndrivers/net/ethernet/cadence/macb.h-486-#define GEM_RGMII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:487:#define MACB_CLKEN_OFFSET\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:488:#define MACB_CLKEN_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-489-\ndrivers/net/ethernet/cadence/macb.h-490-/ Bitfields in WOL /\ndrivers/net/ethernet/cadence/macb.h:491:#define MACB_IP_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:492:#define MACB_IP_SIZE\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:493:#define MACB_MAG_OFFSET\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:494:#define MACB_MAG_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:495:#define MACB_ARP_OFFSET\t\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:496:#define MACB_ARP_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:497:#define MACB_SA1_OFFSET\t\t\t\t18\ndrivers/net/ethernet/cadence/macb.h:498:#define MACB_SA1_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:499:#define MACB_WOL_MTI_OFFSET\t\t\t19\ndrivers/net/ethernet/cadence/macb.h:500:#define MACB_WOL_MTI_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-501-\ndrivers/net/ethernet/cadence/macb.h-502-/ Bitfields in MID /\ndrivers/net/ethernet/cadence/macb.h:503:#define MACB_IDNUM_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:504:#define MACB_IDNUM_SIZE\t\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:505:#define MACB_REV_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:506:#define MACB_REV_SIZE\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h-507-\n--\ndrivers/net/ethernet/cadence/macb.h-678-/ Bitfields in queue pointer registers /\ndrivers/net/ethernet/cadence/macb.h:679:#define MACB_QUEUE_DISABLE_OFFSET\t\t0 / disable queue /\ndrivers/net/ethernet/cadence/macb.h:680:#define MACB_QUEUE_DISABLE_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-681-\n--\ndrivers/net/ethernet/cadence/macb.h-729-/ Constants for CLK /\ndrivers/net/ethernet/cadence/macb.h:730:#define MACB_CLK_DIV8\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:731:#define MACB_CLK_DIV16\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:732:#define MACB_CLK_DIV32\t\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:733:#define MACB_CLK_DIV64\t\t\t\t3\ndrivers/net/ethernet/cadence/macb.h-734-\n--\ndrivers/net/ethernet/cadence/macb.h-745-/ Constants for MAN register /\ndrivers/net/ethernet/cadence/macb.h:746:#define MACB_MAN_C22_SOF\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:747:#define MACB_MAN_C22_WRITE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:748:#define MACB_MAN_C22_READ\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:749:#define MACB_MAN_C22_CODE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h-750-\ndrivers/net/ethernet/cadence/macb.h:751:#define MACB_MAN_C45_SOF\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:752:#define MACB_MAN_C45_ADDR\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:753:#define MACB_MAN_C45_WRITE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:754:#define MACB_MAN_C45_POST_READ_INCR\t\t2\ndrivers/net/ethernet/cadence/macb.h:755:#define MACB_MAN_C45_READ\t\t\t3\ndrivers/net/ethernet/cadence/macb.h:756:#define MACB_MAN_C45_CODE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h-757-\ndrivers/net/ethernet/cadence/macb.h-758-/ Capability mask bits /\ndrivers/net/ethernet/cadence/macb.h:759:#define MACB_CAPS_ISR_CLEAR_ON_WRITE\t\tBIT(0)\ndrivers/net/ethernet/cadence/macb.h:760:#define MACB_CAPS_USRIO_HAS_CLKEN\t\tBIT(1)\ndrivers/net/ethernet/cadence/macb.h:761:#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII\tBIT(2)\ndrivers/net/ethernet/cadence/macb.h:762:#define MACB_CAPS_NO_GIGABIT_HALF\t\tBIT(3)\ndrivers/net/ethernet/cadence/macb.h:763:#define MACB_CAPS_USRIO_DISABLED\t\tBIT(4)\ndrivers/net/ethernet/cadence/macb.h:764:#define MACB_CAPS_JUMBO\t\t\t\tBIT(5)\ndrivers/net/ethernet/cadence/macb.h:765:#define MACB_CAPS_GEM_HAS_PTP\t\t\tBIT(6)\ndrivers/net/ethernet/cadence/macb.h:766:#define MACB_CAPS_BD_RD_PREFETCH\t\tBIT(7)\ndrivers/net/ethernet/cadence/macb.h:767:#define MACB_CAPS_NEEDS_RSTONUBR\t\tBIT(8)\ndrivers/net/ethernet/cadence/macb.h:768:#define MACB_CAPS_MIIONRGMII\t\t\tBIT(9)\ndrivers/net/ethernet/cadence/macb.h:769:#define MACB_CAPS_NEED_TSUCLK\t\t\tBIT(10)\ndrivers/net/ethernet/cadence/macb.h:770:#define MACB_CAPS_QUEUE_DISABLE\t\t\tBIT(11)\ndrivers/net/ethernet/cadence/macb.h:771:#define MACB_CAPS_QBV\t\t\t\tBIT(12)\ndrivers/net/ethernet/cadence/macb.h:772:#define MACB_CAPS_PCS\t\t\t\tBIT(13)\ndrivers/net/ethernet/cadence/macb.h:773:#define MACB_CAPS_HIGH_SPEED\t\t\tBIT(14)\ndrivers/net/ethernet/cadence/macb.h:774:#define MACB_CAPS_CLK_HW_CHG\t\t\tBIT(15)\ndrivers/net/ethernet/cadence/macb.h:775:#define MACB_CAPS_MACB_IS_EMAC\t\t\tBIT(16)\ndrivers/net/ethernet/cadence/macb.h:776:#define MACB_CAPS_FIFO_MODE\t\t\tBIT(17)\ndrivers/net/ethernet/cadence/macb.h:777:#define MACB_CAPS_GIGABIT_MODE_AVAILABLE\tBIT(18)\ndrivers/net/ethernet/cadence/macb.h:778:#define MACB_CAPS_SG_DISABLED\t\t\tBIT(19)\ndrivers/net/ethernet/cadence/macb.h:779:#define MACB_CAPS_MACB_IS_GEM\t\t\tBIT(20)\ndrivers/net/ethernet/cadence/macb.h:780:#define MACB_CAPS_DMA_64B\t\t\tBIT(21)\ndrivers/net/ethernet/cadence/macb.h:781:#define MACB_CAPS_DMA_PTP\t\t\tBIT(22)\ndrivers/net/ethernet/cadence/macb.h:782:#define MACB_CAPS_RSC\t\t\t\tBIT(23)\ndrivers/net/ethernet/cadence/macb.h:783:#define MACB_CAPS_NO_LSO\t\t\tBIT(24)\ndrivers/net/ethernet/cadence/macb.h:784:#define MACB_CAPS_EEE\t\t\t\tBIT(25)\ndrivers/net/ethernet/cadence/macb.h:785:#define MACB_CAPS_USRIO_HAS_MII\t\t\tBIT(26)\ndrivers/net/ethernet/cadence/macb.h:786:#define MACB_CAPS_USRIO_HAS_REFCLK_SOURCE\tBIT(27)\ndrivers/net/ethernet/cadence/macb.h:787:#define MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE\tBIT(28)\ndrivers/net/ethernet/cadence/macb.h-788-\ndrivers/net/ethernet/cadence/macb.h-789-/ LSO settings /\ndrivers/net/ethernet/cadence/macb.h:790:#define MACB_LSO_UFO_ENABLE\t\t\t0x01\ndrivers/net/ethernet/cadence/macb.h:791:#define MACB_LSO_TSO_ENABLE\t\t\t0x02\ndrivers/net/ethernet/cadence/macb.h-792-\ndrivers/net/ethernet/cadence/macb.h-793-/ Bit manipulation macros /\ndrivers/net/ethernet/cadence/macb.h:794:#define MACB_BIT(name)\t\t\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:795:\t(1 \u003c\u003c MACB_##name##_OFFSET)\ndrivers/net/ethernet/cadence/macb.h:796:#define MACB_BF(name,value)\t\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:797:\t(((value) \u0026 ((1 \u003c\u003c MACB_##name##_SIZE) - 1))\t\\\ndrivers/net/ethernet/cadence/macb.h:798:\t \u003c\u003c MACB_##name##_OFFSET)\ndrivers/net/ethernet/cadence/macb.h:799:#define MACB_BFEXT(name,value)\\\ndrivers/net/ethernet/cadence/macb.h:800:\t(((value) \u003e\u003e MACB_##name##_OFFSET)\t\t\\\ndrivers/net/ethernet/cadence/macb.h:801:\t \u0026 ((1 \u003c\u003c MACB_##name##_SIZE) - 1))\ndrivers/net/ethernet/cadence/macb.h:802:#define MACB_BFINS(name,value,old)\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:803:\t(((old) \u0026 ~(((1 \u003c\u003c MACB_##name##_SIZE) - 1)\t\\\ndrivers/net/ethernet/cadence/macb.h:804:\t\t \u003c\u003c MACB_##name##_OFFSET))\t\t\\\ndrivers/net/ethernet/cadence/macb.h:805:\t \| MACB_BF(name,value))\ndrivers/net/ethernet/cadence/macb.h-806-\n--\ndrivers/net/ethernet/cadence/macb.h-820-/ Register access macros /\ndrivers/net/ethernet/cadence/macb.h:821:#define macb_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), MACB_##reg)\ndrivers/net/ethernet/cadence/macb.h:822:#define macb_writel(port, reg, value)\t(port)-\u003emacb_reg_writel((port), MACB_##reg, (value))\ndrivers/net/ethernet/cadence/macb.h-823-#define gem_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), GEM_##reg)\n--\ndrivers/net/ethernet/cadence/macb.h-829-\ndrivers/net/ethernet/cadence/macb.h:830:/ Conditional GEM/MACB macros. These perform the operation to the correct\ndrivers/net/ethernet/cadence/macb.h:831: * register dependent on whether the device is a GEM or a MACB. For registers\ndrivers/net/ethernet/cadence/macb.h-832- * and bitfields that are common across both devices, use macb_{read,write}l\n--\ndrivers/net/ethernet/cadence/macb.h-852-\ndrivers/net/ethernet/cadence/macb.h:853:#define MACB_READ_NSR(bp)\tmacb_readl(bp, NSR)\ndrivers/net/ethernet/cadence/macb.h-854-\n--\ndrivers/net/ethernet/cadence/macb.h=869=struct macb_dma_desc_ptp {\n--\ndrivers/net/ethernet/cadence/macb.h-874-/* DMA descriptor bitfields /\ndrivers/net/ethernet/cadence/macb.h:875:#define MACB_RX_USED_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:876:#define MACB_RX_USED_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:877:#define MACB_RX_WRAP_OFFSET\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:878:#define MACB_RX_WRAP_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:879:#define MACB_RX_WADDR_OFFSET\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:880:#define MACB_RX_WADDR_SIZE\t\t\t30\ndrivers/net/ethernet/cadence/macb.h-881-\ndrivers/net/ethernet/cadence/macb.h:882:#define MACB_RX_FRMLEN_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:883:#define MACB_RX_FRMLEN_SIZE\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:884:#define MACB_RX_OFFSET_OFFSET\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:885:#define MACB_RX_OFFSET_SIZE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:886:#define MACB_RX_SOF_OFFSET\t\t\t14\ndrivers/net/ethernet/cadence/macb.h:887:#define MACB_RX_SOF_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:888:#define MACB_RX_EOF_OFFSET\t\t\t15\ndrivers/net/ethernet/cadence/macb.h:889:#define MACB_RX_EOF_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:890:#define MACB_RX_CFI_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:891:#define MACB_RX_CFI_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:892:#define MACB_RX_VLAN_PRI_OFFSET\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:893:#define MACB_RX_VLAN_PRI_SIZE\t\t\t3\ndrivers/net/ethernet/cadence/macb.h:894:#define MACB_RX_PRI_TAG_OFFSET\t\t\t20\ndrivers/net/ethernet/cadence/macb.h:895:#define MACB_RX_PRI_TAG_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:896:#define MACB_RX_VLAN_TAG_OFFSET\t\t\t21\ndrivers/net/ethernet/cadence/macb.h:897:#define MACB_RX_VLAN_TAG_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:898:#define MACB_RX_TYPEID_MATCH_OFFSET\t\t22\ndrivers/net/ethernet/cadence/macb.h:899:#define MACB_RX_TYPEID_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:900:#define MACB_RX_SA4_MATCH_OFFSET\t\t23\ndrivers/net/ethernet/cadence/macb.h:901:#define MACB_RX_SA4_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:902:#define MACB_RX_SA3_MATCH_OFFSET\t\t24\ndrivers/net/ethernet/cadence/macb.h:903:#define MACB_RX_SA3_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:904:#define MACB_RX_SA2_MATCH_OFFSET\t\t25\ndrivers/net/ethernet/cadence/macb.h:905:#define MACB_RX_SA2_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:906:#define MACB_RX_SA1_MATCH_OFFSET\t\t26\ndrivers/net/ethernet/cadence/macb.h:907:#define MACB_RX_SA1_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:908:#define MACB_RX_EXT_MATCH_OFFSET\t\t28\ndrivers/net/ethernet/cadence/macb.h:909:#define MACB_RX_EXT_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:910:#define MACB_RX_UHASH_MATCH_OFFSET\t\t29\ndrivers/net/ethernet/cadence/macb.h:911:#define MACB_RX_UHASH_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:912:#define MACB_RX_MHASH_MATCH_OFFSET\t\t30\ndrivers/net/ethernet/cadence/macb.h:913:#define MACB_RX_MHASH_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:914:#define MACB_RX_BROADCAST_OFFSET\t\t31\ndrivers/net/ethernet/cadence/macb.h:915:#define MACB_RX_BROADCAST_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-916-\ndrivers/net/ethernet/cadence/macb.h:917:#define MACB_RX_FRMLEN_MASK\t\t\t0xFFF\ndrivers/net/ethernet/cadence/macb.h:918:#define MACB_RX_JFRMLEN_MASK\t\t\t0x3FFF\ndrivers/net/ethernet/cadence/macb.h-919-\n--\ndrivers/net/ethernet/cadence/macb.h-927-\ndrivers/net/ethernet/cadence/macb.h:928:#define MACB_TX_FRMLEN_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:929:#define MACB_TX_FRMLEN_SIZE\t\t\t11\ndrivers/net/ethernet/cadence/macb.h:930:#define MACB_TX_LAST_OFFSET\t\t\t15\ndrivers/net/ethernet/cadence/macb.h:931:#define MACB_TX_LAST_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:932:#define MACB_TX_NOCRC_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:933:#define MACB_TX_NOCRC_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:934:#define MACB_MSS_MFS_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:935:#define MACB_MSS_MFS_SIZE\t\t\t14\ndrivers/net/ethernet/cadence/macb.h:936:#define MACB_TX_LSO_OFFSET\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:937:#define MACB_TX_LSO_SIZE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:938:#define MACB_TX_TCP_SEQ_SRC_OFFSET\t\t19\ndrivers/net/ethernet/cadence/macb.h:939:#define MACB_TX_TCP_SEQ_SRC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:940:#define MACB_TX_BUF_EXHAUSTED_OFFSET\t\t27\ndrivers/net/ethernet/cadence/macb.h:941:#define MACB_TX_BUF_EXHAUSTED_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:942:#define MACB_TX_UNDERRUN_OFFSET\t\t\t28\ndrivers/net/ethernet/cadence/macb.h:943:#define MACB_TX_UNDERRUN_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:944:#define MACB_TX_ERROR_OFFSET\t\t\t29\ndrivers/net/ethernet/cadence/macb.h:945:#define MACB_TX_ERROR_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:946:#define MACB_TX_WRAP_OFFSET\t\t\t30\ndrivers/net/ethernet/cadence/macb.h:947:#define MACB_TX_WRAP_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:948:#define MACB_TX_USED_OFFSET\t\t\t31\ndrivers/net/ethernet/cadence/macb.h:949:#define MACB_TX_USED_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-950-\n--\ndrivers/net/ethernet/cadence/macb.h=1194=struct macb_or_gem_ops {\n--\ndrivers/net/ethernet/cadence/macb.h-1201-\ndrivers/net/ethernet/cadence/macb.h:1202:/ MACB-PTP interface: adapt to platform needs. */\ndrivers/net/ethernet/cadence/macb.h-1203-struct macb_ptp_info {\n--\ndrivers/net/ethernet/cadence/macb.h=1298=struct macb {\n--\ndrivers/net/ethernet/cadence/macb.h-1313-\tunsigned int\t\tnum_queues;\n\n" }
5/2	2026/08/30 16:35	llm	patch-evaluator	1m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 18000 output: 44 thoughts: 155 Thoughts: My Line of Inquiry Okay, so I'm diving into this `macb` situation. First things first, let's take a look at `macb_pci.c` and understand the probing process for these devices. I'm wondering, is the MACB actually emulated within QEMU? And that leads to a bigger question: Does QEMU even provide any emulation for the Cadence GEM or MACB architecture? Aha, wait a minute! I seem to recall that QEMU does emulate Cadence GEM, like for the Xilinx Zynq platform, implemented in `cadence_gem.c`, specifically under the `arm-softmmu` section. But is this relevant to the standard syzkaller / QEMU x86_64 or arm64 environments? Or is `macb_pci` even present in that configuration? Right, back to the source. I need to re-examine `macb_pci.c` and specifically pinpoint where `gem_ptp_init` gets called. This is key.
6/2	2026/08/30 16:37	tool	read-file	0m Args: { "File": "drivers/net/ethernet/cadence/macb_pci.c", "FirstLine": 1, "LineCount": 100 } Results: { "Contents": " 1:\t// SPDX-License-Identifier: GPL-2.0-only\n 2:\t/\n 3:\t DOC: Cadence GEM PCI wrapper.\n 4:\t \n 5:\t Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com\n 6:\t \n 7:\t Authors: Rafal Ozieblo \u003crafalo@cadence.com\u003e\n 8:\t \t Bartosz Folta \u003cbfolta@cadence.com\u003e\n 9:\t /\n 10:\t\n 11:\t#include \u003clinux/clk.h\u003e\n 12:\t#include \u003clinux/clk-provider.h\u003e\n 13:\t#include \u003clinux/etherdevice.h\u003e\n 14:\t#include \u003clinux/module.h\u003e\n 15:\t#include \u003clinux/pci.h\u003e\n 16:\t#include \u003clinux/platform_device.h\u003e\n 17:\t#include \"macb.h\"\n 18:\t\n 19:\t#define PCI_DRIVER_NAME \"macb_pci\"\n 20:\t#define PLAT_DRIVER_NAME \"macb\"\n 21:\t\n 22:\t#define PCI_DEVICE_ID_CDNS_MACB 0xe007\n 23:\t\n 24:\t#define GEM_PCLK_RATE 50000000\n 25:\t#define GEM_HCLK_RATE 50000000\n 26:\t\n 27:\tstatic int macb_probe(struct pci_dev pci, const struct pci_device_id id)\n 28:\t{\n 29:\t\tint err;\n 30:\t\tstruct platform_device pdev;\n 31:\t\tstruct platform_device_info plat_info;\n 32:\t\tstruct macb_platform_data plat_data;\n 33:\t\tstruct resource res[2];\n 34:\t\n 35:\t\t/ enable pci device /\n 36:\t\terr = pcim_enable_device(pci);\n 37:\t\tif (err \u003c 0) {\n 38:\t\t\tdev_err(\u0026pci-\u003edev, \"Enabling PCI device has failed: %d\", err);\n 39:\t\t\treturn err;\n 40:\t\t}\n 41:\t\n 42:\t\tpci_set_master(pci);\n 43:\t\n 44:\t\t/ set up resources /\n 45:\t\tmemset(res, 0x00, sizeof(struct resource) ARRAY_SIZE(res));\n 46:\t\tres[0].start = pci_resource_start(pci, 0);\n 47:\t\tres[0].end = pci_resource_end(pci, 0);\n 48:\t\tres[0].name = PCI_DRIVER_NAME;\n 49:\t\tres[0].flags = IORESOURCE_MEM;\n 50:\t\tres[1].start = pci_irq_vector(pci, 0);\n 51:\t\tres[1].name = PCI_DRIVER_NAME;\n 52:\t\tres[1].flags = IORESOURCE_IRQ;\n 53:\t\n 54:\t\tdev_info(\u0026pci-\u003edev, \"EMAC physical base addr: %pa\\n\",\n 55:\t\t\t \u0026res[0].start);\n 56:\t\n 57:\t\t/* set up macb platform data /\n 58:\t\tmemset(\u0026plat_data, 0, sizeof(plat_data));\n 59:\t\n 60:\t\t/ initialize clocks /\n 61:\t\tplat_data.pclk = clk_register_fixed_rate(\u0026pci-\u003edev, \"pclk\", NULL, 0,\n 62:\t\t\t\t\t\t\t GEM_PCLK_RATE);\n 63:\t\tif (IS_ERR(plat_data.pclk)) {\n 64:\t\t\terr = PTR_ERR(plat_data.pclk);\n 65:\t\t\tgoto err_pclk_register;\n 66:\t\t}\n 67:\t\n 68:\t\tplat_data.hclk = clk_register_fixed_rate(\u0026pci-\u003edev, \"hclk\", NULL, 0,\n 69:\t\t\t\t\t\t\t GEM_HCLK_RATE);\n 70:\t\tif (IS_ERR(plat_data.hclk)) {\n 71:\t\t\terr = PTR_ERR(plat_data.hclk);\n 72:\t\t\tgoto err_hclk_register;\n 73:\t\t}\n 74:\t\n 75:\t\t/ set up platform device info /\n 76:\t\tmemset(\u0026plat_info, 0, sizeof(plat_info));\n 77:\t\tplat_info.parent = \u0026pci-\u003edev;\n 78:\t\tplat_info.fwnode = pci-\u003edev.fwnode;\n 79:\t\tplat_info.name = PLAT_DRIVER_NAME;\n 80:\t\tplat_info.id = pci-\u003edevfn;\n 81:\t\tplat_info.res = res;\n 82:\t\tplat_info.num_res = ARRAY_SIZE(res);\n 83:\t\tplat_info.data = \u0026plat_data;\n 84:\t\tplat_info.size_data = sizeof(plat_data);\n 85:\t\tplat_info.dma_mask = pci-\u003edma_mask;\n 86:\t\n 87:\t\t/ register platform device */\n 88:\t\tpdev = platform_device_register_full(\u0026plat_info);\n 89:\t\tif (IS_ERR(pdev)) {\n 90:\t\t\terr = PTR_ERR(pdev);\n 91:\t\t\tgoto err_plat_dev_register;\n 92:\t\t}\n 93:\t\n 94:\t\tpci_set_drvdata(pci, pdev);\n 95:\t\n 96:\t\treturn 0;\n 97:\t\n 98:\terr_plat_dev_register:\n 99:\t\tclk_unregister_fixed_rate(plat_data.hclk);\n 100:\t\n" }
7/2	2026/08/30 16:37	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 19960 output: 45 thoughts: 50 Thoughts: Okay, let's dive into this. Here's what I'm thinking as I approach this patch: Analyzing the `gem_ptp_init` Function Alright, I'm going to get right to the heart of the matter. I need to understand what this patch is doing, and that starts with the `gem_ptp_init` function. The first thing I'm doing is loading up the patch. It's time to read through it. Specifically, I'm going to zero in on the implementation of `gem_ptp_init`. I'm going to look at the details within the patch. I'm going to look at the differences to see what's changed and try to understand the rationale of the change. Then, let's zero in on `drivers/net/ethernet/cadence/macb_ptp.c` around line 330. I'm going to examine the code around that specific line. I have a feeling that's where the core of the change or the related functionality is implemented. Understanding what's happening in that immediate context is key to grasping the overall impact of the patch. Let's see if this is an update, a bugfix, or something entirely new.
8/2	2026/08/30 16:38	tool	read-file	0m Args: { "File": "drivers/net/ethernet/cadence/macb_ptp.c", "FirstLine": 310, "LineCount": 80 } Results: { "Contents": " 310:\t\tdesc_ptp = macb_ptp_desc(bp, desc);\n 311:\t\t/* Unlikely but check /\n 312:\t\tif (!desc_ptp) {\n 313:\t\t\tdev_warn_ratelimited(\u0026bp-\u003epdev-\u003edev,\n 314:\t\t\t\t\t \"Timestamp not supported in BD\\n\");\n 315:\t\t\treturn;\n 316:\t\t}\n 317:\t\n 318:\t\t/ ensure ts_1/ts_2 is loaded after ctrl (TX_USED check) /\n 319:\t\tdma_rmb();\n 320:\t\tgem_hw_timestamp(bp, desc_ptp-\u003ets_1, desc_ptp-\u003ets_2, \u0026ts);\n 321:\t\n 322:\t\tmemset(\u0026shhwtstamps, 0, sizeof(shhwtstamps));\n 323:\t\tshhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);\n 324:\t\tskb_tstamp_tx(skb, \u0026shhwtstamps);\n 325:\t}\n 326:\t\n 327:\tvoid gem_ptp_init(struct net_device netdev)\n 328:\t{\n 329:\t\tstruct macb bp = netdev_priv(netdev);\n 330:\t\n 331:\t\tbp-\u003eptp_clock_info = gem_ptp_caps_template;\n 332:\t\n 333:\t\tspin_lock_init(\u0026bp-\u003etsu_clk_lock);\n 334:\t\n 335:\t\t/ nominal frequency and maximum adjustment in ppb /\n 336:\t\tbp-\u003etsu_rate = bp-\u003eptp_info-\u003eget_tsu_rate(bp);\n 337:\t\tbp-\u003eptp_clock_info.max_adj = bp-\u003eptp_info-\u003eget_ptp_max_adj();\n 338:\t\tgem_ptp_init_timer(bp);\n 339:\t\tbp-\u003eptp_clock = ptp_clock_register(\u0026bp-\u003eptp_clock_info, \u0026netdev-\u003edev);\n 340:\t\tif (IS_ERR(bp-\u003eptp_clock)) {\n 341:\t\t\tpr_err(\"ptp clock register failed: %ld\\n\",\n 342:\t\t\t\tPTR_ERR(bp-\u003eptp_clock));\n 343:\t\t\tbp-\u003eptp_clock = NULL;\n 344:\t\t\treturn;\n 345:\t\t} else if (bp-\u003eptp_clock == NULL) {\n 346:\t\t\tpr_err(\"ptp clock register failed\\n\");\n 347:\t\t\treturn;\n 348:\t\t}\n 349:\t\n 350:\t\tgem_ptp_init_tsu(bp);\n 351:\t\n 352:\t\tdev_info(\u0026bp-\u003epdev-\u003edev, \"%s ptp clock registered.\\n\",\n 353:\t\t\t GEM_PTP_TIMER_NAME);\n 354:\t}\n 355:\t\n 356:\tvoid gem_ptp_remove(struct net_device netdev)\n 357:\t{\n 358:\t\tstruct macb bp = netdev_priv(netdev);\n 359:\t\n 360:\t\tif (bp-\u003eptp_clock) {\n 361:\t\t\tptp_clock_unregister(bp-\u003eptp_clock);\n 362:\t\t\tbp-\u003eptp_clock = NULL;\n 363:\t\t}\n 364:\t\n 365:\t\tgem_ptp_clear_timer(bp);\n 366:\t\n 367:\t\tdev_info(\u0026bp-\u003epdev-\u003edev, \"%s ptp clock unregistered.\\n\",\n 368:\t\t\t GEM_PTP_TIMER_NAME);\n 369:\t}\n 370:\t\n 371:\tstatic int gem_ptp_set_ts_mode(struct macb bp,\n 372:\t\t\t\t enum macb_bd_control tx_bd_control,\n 373:\t\t\t\t enum macb_bd_control rx_bd_control)\n 374:\t{\n 375:\t\tgem_writel(bp, TXBDCTRL, GEM_BF(TXTSMODE, tx_bd_control));\n 376:\t\tgem_writel(bp, RXBDCTRL, GEM_BF(RXTSMODE, rx_bd_control));\n 377:\t\n 378:\t\treturn 0;\n 379:\t}\n 380:\t\n 381:\tint gem_get_hwtst(struct net_device netdev,\n 382:\t\t\t struct kernel_hwtstamp_config tstamp_config)\n 383:\t{\n 384:\t\tstruct macb bp = netdev_priv(netdev);\n 385:\t\n 386:\t\ttstamp_config = bp-\u003etstamp_config;\n 387:\t\tif (!macb_dma_ptp(bp))\n 388:\t\t\treturn -EOPNOTSUPP;\n 389:\t\n" }
9/2	2026/08/30 16:38	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 21652 output: 35 thoughts: 133 Thoughts: Debugging a Potential Race Condition Okay, let's break this down. It looks like we have a potential race condition in `gem_ptp_init`. Specifically, `gem_ptp_init_timer(bp)` is being called before the `spin_lock_init(&bp->tsu_clk_lock)`. Now, that immediately raises a red flag. We need to know if `gem_ptp_init_timer` or, for that matter, `ptp_clock_register` (since they could be related) are touching `bp->tsu_clk_lock`. I'll go search the code. Looks like I will need to search for `tsu_clk_lock` in `macb_ptp.c` to see how it's being used.
10/2	2026/08/30 16:38	tool	grepper	0m Args: { "Expression": "tsu_clk_lock", "PathPrefix": "drivers/net/ethernet/cadence" } Results: { "Output": "drivers/net/ethernet/cadence/macb.h=1298=struct macb {\n--\ndrivers/net/ethernet/cadence/macb.h-1362-\ndrivers/net/ethernet/cadence/macb.h:1363:\tspinlock_t tsu_clk_lock; /* gem tsu clock locking /\ndrivers/net/ethernet/cadence/macb.h-1364-\tunsigned int tsu_rate;\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=43=static int gem_tsu_get_time(struct ptp_clock_info ptp, struct timespec64 ts,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-50-\ndrivers/net/ethernet/cadence/macb_ptp.c:51:\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-52-\tptp_read_system_prets(sts);\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-72-\ndrivers/net/ethernet/cadence/macb_ptp.c:73:\tspin_unlock_irqrestore(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-74-\tts-\u003etv_sec = (((u64)sech \u003c\u003c GEM_TSL_SIZE) \| secl)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=79=static int gem_tsu_set_time(struct ptp_clock_info ptp,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-89-\ndrivers/net/ethernet/cadence/macb_ptp.c:90:\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-91-\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-98-\ndrivers/net/ethernet/cadence/macb_ptp.c:99:\tspin_unlock_irqrestore(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-100-\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=104=static int gem_tsu_incr_set(struct macb bp, struct tsu_incr incr_spec)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-112-\t /\ndrivers/net/ethernet/cadence/macb_ptp.c:113:\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-114-\t/ RegBit[15:0] = Subns[23:8]; RegBit[31:24] = Subns[7:0] /\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-118-\tgem_writel(bp, TI, GEM_BF(NSINCR, incr_spec-\u003ens));\ndrivers/net/ethernet/cadence/macb_ptp.c:119:\tspin_unlock_irqrestore(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-120-\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=327=void gem_ptp_init(struct net_device netdev)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-332-\ndrivers/net/ethernet/cadence/macb_ptp.c:333:\tspin_lock_init(\u0026bp-\u003etsu_clk_lock);\ndrivers/net/ethernet/cadence/macb_ptp.c-334-\n" }
11/2	2026/08/30 16:38	llm	patch-evaluator	2m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 23037 output: 45 thoughts: 71 Thoughts: Here's my analysis of what's going on: Dissecting the `gem_tsu_incr_set` Function Call Okay, so I'm tracking this function call, `gem_tsu_incr_set`, and it looks like it's being initiated from within `gem_ptp_init_timer(bp)`. That's my starting point. Now, to understand the context of the call, I need to dive deeper into `gem_ptp_init_timer(bp)`. The code suggests the function is located in `macb_ptp.c`, lines 100 to 250 seem the relevant area for this deeper look. I'll focus my attention on that section to see what's leading up to the `gem_tsu_incr_set` call and what's happening immediately after. That should give me the insights I need to understand the role of `gem_tsu_incr_set` in the larger PTP initialization flow.
12/2	2026/08/30 16:41	tool	read-file	0m Args: { "File": "drivers/net/ethernet/cadence/macb_ptp.c", "FirstLine": 100, "LineCount": 80 } Results: { "Contents": " 100:\t\n 101:\t\treturn 0;\n 102:\t}\n 103:\t\n 104:\tstatic int gem_tsu_incr_set(struct macb bp, struct tsu_incr incr_spec)\n 105:\t{\n 106:\t\tunsigned long flags;\n 107:\t\n 108:\t\t/* tsu_timer_incr register must be written after\n 109:\t\t * the tsu_timer_incr_sub_ns register and the write operation\n 110:\t\t * will cause the value written to the tsu_timer_incr_sub_ns register\n 111:\t\t * to take effect.\n 112:\t\t /\n 113:\t\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\n 114:\t\t/ RegBit[15:0] = Subns[23:8]; RegBit[31:24] = Subns[7:0] /\n 115:\t\tgem_writel(bp, TISUBN, GEM_BF(SUBNSINCRL, incr_spec-\u003esub_ns) \|\n 116:\t\t\t GEM_BF(SUBNSINCRH, (incr_spec-\u003esub_ns \u003e\u003e\n 117:\t\t\t\t GEM_SUBNSINCRL_SIZE)));\n 118:\t\tgem_writel(bp, TI, GEM_BF(NSINCR, incr_spec-\u003ens));\n 119:\t\tspin_unlock_irqrestore(\u0026bp-\u003etsu_clk_lock, flags);\n 120:\t\n 121:\t\treturn 0;\n 122:\t}\n 123:\t\n 124:\tstatic int gem_ptp_adjfine(struct ptp_clock_info ptp, long scaled_ppm)\n 125:\t{\n 126:\t\tstruct macb bp = container_of(ptp, struct macb, ptp_clock_info);\n 127:\t\tstruct tsu_incr incr_spec;\n 128:\t\tbool neg_adj = false;\n 129:\t\tu32 word;\n 130:\t\tu64 adj;\n 131:\t\n 132:\t\tif (scaled_ppm \u003c 0) {\n 133:\t\t\tneg_adj = true;\n 134:\t\t\tscaled_ppm = -scaled_ppm;\n 135:\t\t}\n 136:\t\n 137:\t\t/ Adjustment is relative to base frequency /\n 138:\t\tincr_spec.sub_ns = bp-\u003etsu_incr.sub_ns;\n 139:\t\tincr_spec.ns = bp-\u003etsu_incr.ns;\n 140:\t\n 141:\t\t/ scaling: unused(8bit) \| ns(8bit) \| fractions(16bit) /\n 142:\t\tword = ((u64)incr_spec.ns \u003c\u003c GEM_SUBNSINCR_SIZE) + incr_spec.sub_ns;\n 143:\t\tadj = (u64)scaled_ppm word;\n 144:\t\t/* Divide with rounding, equivalent to floating dividing:\n 145:\t\t * (temp / USEC_PER_SEC) + 0.5\n 146:\t\t /\n 147:\t\tadj += (USEC_PER_SEC \u003e\u003e 1);\n 148:\t\tadj \u003e\u003e= PPM_FRACTION; / remove fractions /\n 149:\t\tadj = div_u64(adj, USEC_PER_SEC);\n 150:\t\tadj = neg_adj ? (word - adj) : (word + adj);\n 151:\t\n 152:\t\tincr_spec.ns = (adj \u003e\u003e GEM_SUBNSINCR_SIZE)\n 153:\t\t\t\t\u0026 ((1 \u003c\u003c GEM_NSINCR_SIZE) - 1);\n 154:\t\tincr_spec.sub_ns = adj \u0026 ((1 \u003c\u003c GEM_SUBNSINCR_SIZE) - 1);\n 155:\t\tgem_tsu_incr_set(bp, \u0026incr_spec);\n 156:\t\treturn 0;\n 157:\t}\n 158:\t\n 159:\tstatic int gem_ptp_adjtime(struct ptp_clock_info ptp, s64 delta)\n 160:\t{\n 161:\t\tstruct macb bp = container_of(ptp, struct macb, ptp_clock_info);\n 162:\t\tstruct timespec64 now, then = ns_to_timespec64(delta);\n 163:\t\tu32 adj, sign = 0;\n 164:\t\n 165:\t\tif (delta \u003c 0) {\n 166:\t\t\tsign = 1;\n 167:\t\t\tdelta = -delta;\n 168:\t\t}\n 169:\t\n 170:\t\tif (delta \u003e TSU_NSEC_MAX_VAL) {\n 171:\t\t\tgem_tsu_get_time(\u0026bp-\u003eptp_clock_info, \u0026now, NULL);\n 172:\t\t\tnow = timespec64_add(now, then);\n 173:\t\n 174:\t\t\tgem_tsu_set_time(\u0026bp-\u003eptp_clock_info,\n 175:\t\t\t\t\t (const struct timespec64 )\u0026now);\n 176:\t\t} else {\n 177:\t\t\tadj = (sign \u003c\u003c GEM_ADDSUB_OFFSET) \| delta;\n 178:\t\n 179:\t\t\tgem_writel(bp, TA, adj);\n" }
13/2	2026/08/30 16:41	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 24784 output: 45 thoughts: 40 Thoughts: Here's my take on the thought process, as requested: Deconstructing `gem_ptp_init_timer` Alright, let's dive into this `gem_ptp_init_timer` function. I need to understand its role within this PTP implementation, so I'm going to start by running through the code block from lines 200 to 300. This should give me a solid grasp of what this timer initialization routine is actually doing. My focus will be on the critical parts for synchronization.
14/2	2026/08/30 16:41	tool	read-file	0m Args: { "File": "drivers/net/ethernet/cadence/macb_ptp.c", "FirstLine": 200, "LineCount": 60 } Results: { "Contents": " 200:\t\t.adjfine\t= gem_ptp_adjfine,\n 201:\t\t.adjtime\t= gem_ptp_adjtime,\n 202:\t\t.gettimex64\t= gem_tsu_get_time,\n 203:\t\t.settime64\t= gem_tsu_set_time,\n 204:\t\t.enable\t\t= gem_ptp_enable,\n 205:\t};\n 206:\t\n 207:\tstatic void gem_ptp_init_timer(struct macb bp)\n 208:\t{\n 209:\t\tu32 rem = 0;\n 210:\t\tu64 adj;\n 211:\t\n 212:\t\tbp-\u003etsu_incr.ns = div_u64_rem(NSEC_PER_SEC, bp-\u003etsu_rate, \u0026rem);\n 213:\t\tif (rem) {\n 214:\t\t\tadj = rem;\n 215:\t\t\tadj \u003c\u003c= GEM_SUBNSINCR_SIZE;\n 216:\t\t\tbp-\u003etsu_incr.sub_ns = div_u64(adj, bp-\u003etsu_rate);\n 217:\t\t} else {\n 218:\t\t\tbp-\u003etsu_incr.sub_ns = 0;\n 219:\t\t}\n 220:\t}\n 221:\t\n 222:\tstatic void gem_ptp_init_tsu(struct macb bp)\n 223:\t{\n 224:\t\tstruct timespec64 ts;\n 225:\t\n 226:\t\t/* 1. get current system time /\n 227:\t\tts = ns_to_timespec64(ktime_to_ns(ktime_get_real()));\n 228:\t\n 229:\t\t/ 2. set ptp timer /\n 230:\t\tgem_tsu_set_time(\u0026bp-\u003eptp_clock_info, \u0026ts);\n 231:\t\n 232:\t\t/ 3. set PTP timer increment value to BASE_INCREMENT /\n 233:\t\tgem_tsu_incr_set(bp, \u0026bp-\u003etsu_incr);\n 234:\t\n 235:\t\tgem_writel(bp, TA, 0);\n 236:\t}\n 237:\t\n 238:\tstatic void gem_ptp_clear_timer(struct macb bp)\n 239:\t{\n 240:\t\tbp-\u003etsu_incr.sub_ns = 0;\n 241:\t\tbp-\u003etsu_incr.ns = 0;\n 242:\t\n 243:\t\tgem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, 0));\n 244:\t\tgem_writel(bp, TI, GEM_BF(NSINCR, 0));\n 245:\t\tgem_writel(bp, TA, 0);\n 246:\t}\n 247:\t\n 248:\tstatic int gem_hw_timestamp(struct macb bp, u32 dma_desc_ts_1,\n 249:\t\t\t\t u32 dma_desc_ts_2, struct timespec64 ts)\n 250:\t{\n 251:\t\tstruct timespec64 tsu;\n 252:\t\n 253:\t\tts-\u003etv_sec = (GEM_BFEXT(DMA_SECH, dma_desc_ts_2) \u003c\u003c GEM_DMA_SECL_SIZE) \|\n 254:\t\t\t\tGEM_BFEXT(DMA_SECL, dma_desc_ts_1);\n 255:\t\tts-\u003etv_nsec = GEM_BFEXT(DMA_NSEC, dma_desc_ts_1);\n 256:\t\n 257:\t\t/* TSU overlapping workaround\n 258:\t\t * The timestamp only contains lower few bits of seconds,\n 259:\t\t * so add value from 1588 timer\n" }
15/2	2026/08/30 16:41	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 26021 output: 34 thoughts: 571 Thoughts: My Analysis of a Potential Spinlock Bug Fix Okay, so I'm looking at this patch for `gem_ptp_init`. It seems like there's a potential concurrency issue with the spinlock `bp->tsu_clk_lock`. The core of the problem is the order of operations in this function. We're registering the PTP clock using `ptp_clock_register(&bp->ptp_clock_info, &netdev->dev);`. The key thing is that immediately after `ptp_clock_register` completes, user space or kernel threads can start interacting with the PTP clock device. They might be calling things like `clock_adjtime`, `gem_tsu_get_time`, or `gem_tsu_set_time` - all of which use that `bp->tsu_clk_lock`! The potential bug arises because the spinlock `spin_lock_init(&bp->tsu_clk_lock)` was being called after the registration. This means the lock could have been uninitialized during the critical window when the PTP clock was already accessible. The proposed fix, moving the `spin_lock_init` call earlier, makes perfect sense to resolve the race condition. Now, the next step is crucial. Can this fix be fuzzed? I need to apply the fuzzing guidelines meticulously. Let me recall the "WorthFuzzing=false" criteria from memory. We need to rule out: * Documentation, Kconfig, or comment-only changes. Nope, this is a code change. * Purely decorative logging. Definitely not the case here. * Numeric constant changes that don't alter execution. Not relevant. * Unreachable code in virtualized environments. This is a real concern! I'll need to research what MACB/GEM actually is. * Vendor-specific hardware drivers that are hard to emulate. Probably not, but I need to be sure. * Teardown callbacks during PCI hot-unplug. Nope, that's not what this is. So, the biggest question is whether this code is reachable in a standard QEMU environment. We need to figure out what kind of device MACB/GEM is. Is it a platform device or a PCI device? How are these devices typically instantiated? I need to dig into `macb_main.c` and `macb_pci.c` to understand the device initialization and connection mechanism. Only then can I decide if this fix is worth fuzzing.
16/2	2026/08/30 16:41	tool	grepper	0m Args: { "Expression": "MODULE_DEVICE_TABLE", "PathPrefix": "drivers/net/ethernet/cadence" } Results: { "Output": "drivers/net/ethernet/cadence/macb_main.c=5727=static const struct of_device_id macb_dt_ids[] = {\n--\ndrivers/net/ethernet/cadence/macb_main.c-5754-};\ndrivers/net/ethernet/cadence/macb_main.c:5755:MODULE_DEVICE_TABLE(of, macb_dt_ids);\ndrivers/net/ethernet/cadence/macb_main.c-5756-\n--\ndrivers/net/ethernet/cadence/macb_pci.c=132=module_pci_driver(macb_pci_driver);\ndrivers/net/ethernet/cadence/macb_pci.c:133:MODULE_DEVICE_TABLE(pci, dev_id_table);\ndrivers/net/ethernet/cadence/macb_pci.c-134-MODULE_LICENSE(\"GPL\");\n" }
17/2	2026/08/30 16:41	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 27426 output: 34 thoughts: 21 Thoughts: Here's my thought process, as it stands: Checking `dev_id_table` in `macb_pci.c` Okay, so I need to understand how the driver in `macb_pci.c` identifies the specific hardware it's supposed to handle. That probably means the first thing to look at is the `dev_id_table`. I'm expecting this is where the driver defines the PCI device IDs it's compatible with. This will likely be a list or array of structures, each containing the vendor ID and device ID that this driver recognizes. I'll need to see how the driver uses this table during initialization, specifically how it probes for compatible devices during the PCI probe function. I'm anticipating some form of loop to iterate through the table and compare the hardware ID with what the system presents to it during probe. Time to dive into the code and confirm my hunch!
18/2	2026/08/30 16:41	tool	grepper	0m Args: { "Expression": "dev_id_table", "PathPrefix": "drivers/net/ethernet/cadence" } Results: { "Output": "drivers/net/ethernet/cadence/macb_pci.c=108=static void macb_remove(struct pci_dev *pci)\n--\ndrivers/net/ethernet/cadence/macb_pci.c-119-\ndrivers/net/ethernet/cadence/macb_pci.c:120:static const struct pci_device_id dev_id_table[] = {\ndrivers/net/ethernet/cadence/macb_pci.c-121-\t{ PCI_VDEVICE(CDNS, PCI_DEVICE_ID_CDNS_MACB) },\n--\ndrivers/net/ethernet/cadence/macb_pci.c=125=static struct pci_driver macb_pci_driver = {\ndrivers/net/ethernet/cadence/macb_pci.c-126-\t.name = PCI_DRIVER_NAME,\ndrivers/net/ethernet/cadence/macb_pci.c:127:\t.id_table = dev_id_table,\ndrivers/net/ethernet/cadence/macb_pci.c-128-\t.probe = macb_probe,\n--\ndrivers/net/ethernet/cadence/macb_pci.c=132=module_pci_driver(macb_pci_driver);\ndrivers/net/ethernet/cadence/macb_pci.c:133:MODULE_DEVICE_TABLE(pci, dev_id_table);\ndrivers/net/ethernet/cadence/macb_pci.c-134-MODULE_LICENSE(\"GPL\");\n" }
19/2	2026/08/30 16:41	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 28087 output: 45 thoughts: 80 Thoughts: Here's my take on those thoughts: Analyzing a Cadence MACB Driver Okay, so I'm looking at a Cadence PCI device, specifically identified by vendor ID `0x17cd` and device ID `0xe007` – that's `PCI_VENDOR_ID_CDNS` and `PCI_DEVICE_ID_CDNS_MACB`, right? I'm pretty sure that's a Cadence MACB. Now, where does this fit in the driver landscape? Ah, yes, `macb_main.c`. That file's usually a good indicator. It looks like this is an Open Firmware (OF) or platform driver implementation. Time to confirm the device identifiers used by the driver. Let me dig into `macb_dt_ids` and cross-reference. I'll see what the device tree bindings are to confirm and understand how this device is meant to be configured.
20/2	2026/08/30 16:41	tool	read-file	0m Args: { "File": "drivers/net/ethernet/cadence/macb_main.c", "FirstLine": 5727, "LineCount": 35 } Results: { "Contents": "5727:\tstatic const struct of_device_id macb_dt_ids[] = {\n5728:\t\t{ .compatible = \"cdns,at91sam9260-macb\", .data = \u0026at91sam9260_config },\n5729:\t\t{ .compatible = \"cdns,macb\" },\n5730:\t\t{ .compatible = \"cdns,np4-macb\", .data = \u0026np4_config },\n5731:\t\t{ .compatible = \"cdns,pc302-gem\", .data = \u0026pc302gem_config },\n5732:\t\t{ .compatible = \"cdns,gem\", .data = \u0026pc302gem_config },\n5733:\t\t{ .compatible = \"cdns,sam9x60-macb\", .data = \u0026at91sam9260_config },\n5734:\t\t{ .compatible = \"atmel,sama5d2-gem\", .data = \u0026sama5d2_config },\n5735:\t\t{ .compatible = \"atmel,sama5d29-gem\", .data = \u0026sama5d29_config },\n5736:\t\t{ .compatible = \"atmel,sama5d3-gem\", .data = \u0026sama5d3_config },\n5737:\t\t{ .compatible = \"atmel,sama5d3-macb\", .data = \u0026sama5d3macb_config },\n5738:\t\t{ .compatible = \"atmel,sama5d4-gem\", .data = \u0026sama5d4_config },\n5739:\t\t{ .compatible = \"cdns,at91rm9200-emac\", .data = \u0026emac_config },\n5740:\t\t{ .compatible = \"cdns,emac\", .data = \u0026emac_config },\n5741:\t\t{ .compatible = \"cdns,zynqmp-gem\", .data = \u0026zynqmp_config}, /* deprecated /\n5742:\t\t{ .compatible = \"cdns,zynq-gem\", .data = \u0026zynq_config }, / deprecated /\n5743:\t\t{ .compatible = \"sifive,fu540-c000-gem\", .data = \u0026fu540_c000_config },\n5744:\t\t{ .compatible = \"microchip,mpfs-macb\", .data = \u0026mpfs_config },\n5745:\t\t{ .compatible = \"microchip,pic64hpsc-gem\", .data = \u0026pic64hpsc_config},\n5746:\t\t{ .compatible = \"microchip,sama7g5-gem\", .data = \u0026sama7g5_gem_config },\n5747:\t\t{ .compatible = \"microchip,sama7g5-emac\", .data = \u0026sama7g5_emac_config },\n5748:\t\t{ .compatible = \"mobileye,eyeq5-gem\", .data = \u0026eyeq5_config },\n5749:\t\t{ .compatible = \"raspberrypi,rp1-gem\", .data = \u0026raspberrypi_rp1_config },\n5750:\t\t{ .compatible = \"xlnx,zynqmp-gem\", .data = \u0026zynqmp_config},\n5751:\t\t{ .compatible = \"xlnx,zynq-gem\", .data = \u0026zynq_config },\n5752:\t\t{ .compatible = \"xlnx,versal-gem\", .data = \u0026versal_config},\n5753:\t\t{ / sentinel */ }\n5754:\t};\n5755:\tMODULE_DEVICE_TABLE(of, macb_dt_ids);\n5756:\t\n5757:\tstatic const struct macb_config default_gem_config = {\n5758:\t\t.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE \|\n5759:\t\t\tMACB_CAPS_JUMBO \|\n5760:\t\t\tMACB_CAPS_GEM_HAS_PTP,\n5761:\t\t.dma_burst_length = 16,\n" }
21/2	2026/08/30 16:41	llm	patch-evaluator	1m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 29426 output: 32 thoughts: 936 Thoughts: Analyzing the Fuzzing Potential of the Cadence GEM (MACB) Driver Okay, let's break this down. I'm looking at potential candidates for fuzzing, and the Cadence GEM (MACB) driver is on the list. First, let me recall the common SoCs this driver is associated with: SiFive, Xilinx Zynq/ZynqMP/Versal, Cadence, and Atmel. I need to quickly determine if any of these are emulated in standard QEMU or used within virtualized environments, which is crucial for Syzkaller's effectiveness. Right, QEMU has machine types. I remember `xlnx-zcu102`, `xlnx-versal-virt`, `xilinx-zynq-a9`, `sifive_u`, `microchip-icicle-kit`. But Syzkaller primarily targets x86_64 and arm64, specifically virtual machines with virtio, or gVisor. So, what standard devices are typically found in QEMU or GCE for fuzzing? That's the key. Now, I have to consider the instructions. The crucial criteria I need to use to determine if a patch is WorthFuzzing is the following. A patch should return "WorthFuzzing=false" if it only contains: - documentation changes - config file modifications - code comments - decorative changes such as logging or tracepoints - changes to constants or macros that doesn't alter execution flow - unreachable code in virtualized environments, such as usb gadget or mac80211_hwsim - vendor-specific PCIe switch, SmartNIC, or GPU drivers that require physical PCIe hardware cards not emulated in standard QEMU - driver .remove, .shutdown, or pci_unregister_driver teardown callbacks that are executed only during PCI hot-unplug or sysfs driver unbind operations. Otherwise it's "WorthFuzzing=true" if a patch modifies reachable core kernel logic, drivers, or architectures. I need to verify that code can be executed using code search tools. So, is `macb` or `gem_ptp` a vendor-specific hardware driver? Does it require specific board DT not present in standard fuzzing environments (x86/arm64 virt)? I must investigate. Let's check. Can `macb` be instantiated via PCI in standard QEMU? Specifically, does QEMU have a PCI Cadence MACB device? No, QEMU's `cadence_gem` is a SysBusDevice, memory mapped I/O on Zynq / Versal / SiFive U SoC, not a PCI device. What about `macb_pci`? The PCI ID 0x17cd:0xe007 points to Cadence's PCI testboard / FPGA card, which isn't emulated in QEMU. What about platform devices? In standard QEMU x86_64 (q35 / pc) and ARM64 (`-M virt`), there's no Cadence GEM / MACB node defined in the device tree or ACPI. Can Syzkaller instantiate platform devices via Device Tree overlays or configfs? No, it runs on standard QEMU or GCE VMs, where kernel devices are ACPI, PCI, USB, or software pseudo devices. Time to look at other network and SoC ethernet drivers. I need to understand how those are handled. I will perform a search in the repo or check similar drivers. Is `drivers/net/ethernet/cadence` reachable? Finally, let's explore if there are any mock or test frameworks for macb, or if it is tied to specific embedded SoCs and PCI test cards. Is there a standard way to instantiate MACB? That's the critical question I need to answer.
22/2	2026/08/30 16:42	tool	grepper	0m Args: { "Expression": "macb_", "PathPrefix": "drivers/net/ethernet/cadence" } Results: { "Output": "\nFull output is too long, showing 500 out of 2598 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/cadence/Kconfig=45=config MACB_PCI\n--\ndrivers/net/ethernet/cadence/Kconfig-51-\t To compile this driver as a module, choose M here: the module\ndrivers/net/ethernet/cadence/Kconfig:52:\t will be called macb_pci.\ndrivers/net/ethernet/cadence/Kconfig-53-\n--\ndrivers/net/ethernet/cadence/Makefile-4-#\ndrivers/net/ethernet/cadence/Makefile:5:macb-y\t:= macb_main.o\ndrivers/net/ethernet/cadence/Makefile-6-\ndrivers/net/ethernet/cadence/Makefile=7=ifeq ($(CONFIG_MACB_USE_HWSTAMP),y)\ndrivers/net/ethernet/cadence/Makefile:8:macb-y\t+= macb_ptp.o\ndrivers/net/ethernet/cadence/Makefile-9-endif\n--\ndrivers/net/ethernet/cadence/Makefile=11=obj-$(CONFIG_MACB) += macb.o\ndrivers/net/ethernet/cadence/Makefile:12:obj-$(CONFIG_MACB_PCI) += macb_pci.o\n--\ndrivers/net/ethernet/cadence/macb.h-820-/* Register access macros /\ndrivers/net/ethernet/cadence/macb.h:821:#define macb_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), MACB_##reg)\ndrivers/net/ethernet/cadence/macb.h:822:#define macb_writel(port, reg, value)\t(port)-\u003emacb_reg_writel((port), MACB_##reg, (value))\ndrivers/net/ethernet/cadence/macb.h:823:#define gem_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), GEM_##reg)\ndrivers/net/ethernet/cadence/macb.h:824:#define gem_writel(port, reg, value)\t(port)-\u003emacb_reg_writel((port), GEM_##reg, (value))\ndrivers/net/ethernet/cadence/macb.h:825:#define queue_readl(queue, reg)\t\t(queue)-\u003ebp-\u003emacb_reg_readl((queue)-\u003ebp, (queue)-\u003ereg)\ndrivers/net/ethernet/cadence/macb.h:826:#define queue_writel(queue, reg, value)\t(queue)-\u003ebp-\u003emacb_reg_writel((queue)-\u003ebp, (queue)-\u003ereg, (value))\ndrivers/net/ethernet/cadence/macb.h:827:#define gem_readl_n(port, reg, idx)\t\t(port)-\u003emacb_reg_readl((port), GEM_##reg + idx 4)\ndrivers/net/ethernet/cadence/macb.h:828:#define gem_writel_n(port, reg, idx, value)\t(port)-\u003emacb_reg_writel((port), GEM_##reg + idx * 4, (value))\ndrivers/net/ethernet/cadence/macb.h-829-\n--\ndrivers/net/ethernet/cadence/macb.h-831- * register dependent on whether the device is a GEM or a MACB. For registers\ndrivers/net/ethernet/cadence/macb.h:832: * and bitfields that are common across both devices, use macb_{read,write}l\ndrivers/net/ethernet/cadence/macb.h-833- * to avoid the cost of the conditional.\ndrivers/net/ethernet/cadence/macb.h-834- /\ndrivers/net/ethernet/cadence/macb.h:835:#define macb_or_gem_writel(__bp, __reg, __value) \\\ndrivers/net/ethernet/cadence/macb.h-836-\t({ \\\ndrivers/net/ethernet/cadence/macb.h:837:\t\tif (macb_is_gem((__bp))) \\\ndrivers/net/ethernet/cadence/macb.h-838-\t\t\tgem_writel((__bp), __reg, __value); \\\ndrivers/net/ethernet/cadence/macb.h-839-\t\telse \\\ndrivers/net/ethernet/cadence/macb.h:840:\t\t\tmacb_writel((__bp), __reg, __value); \\\ndrivers/net/ethernet/cadence/macb.h-841-\t})\ndrivers/net/ethernet/cadence/macb.h-842-\ndrivers/net/ethernet/cadence/macb.h:843:#define macb_or_gem_readl(__bp, __reg) \\\ndrivers/net/ethernet/cadence/macb.h-844-\t({ \\\ndrivers/net/ethernet/cadence/macb.h-845-\t\tu32 __v; \\\ndrivers/net/ethernet/cadence/macb.h:846:\t\tif (macb_is_gem((__bp))) \\\ndrivers/net/ethernet/cadence/macb.h-847-\t\t\t__v = gem_readl((__bp), __reg); \\\ndrivers/net/ethernet/cadence/macb.h-848-\t\telse \\\ndrivers/net/ethernet/cadence/macb.h:849:\t\t\t__v = macb_readl((__bp), __reg); \\\ndrivers/net/ethernet/cadence/macb.h-850-\t\t__v; \\\n--\ndrivers/net/ethernet/cadence/macb.h-852-\ndrivers/net/ethernet/cadence/macb.h:853:#define MACB_READ_NSR(bp)\tmacb_readl(bp, NSR)\ndrivers/net/ethernet/cadence/macb.h-854-\ndrivers/net/ethernet/cadence/macb.h:855:/ struct macb_dma_desc - Hardware DMA descriptor\ndrivers/net/ethernet/cadence/macb.h-856- * @addr: DMA address of data buffer\n--\ndrivers/net/ethernet/cadence/macb.h-858- /\ndrivers/net/ethernet/cadence/macb.h:859:struct macb_dma_desc {\ndrivers/net/ethernet/cadence/macb.h-860-\tu32\taddr;\n--\ndrivers/net/ethernet/cadence/macb.h-863-\ndrivers/net/ethernet/cadence/macb.h:864:struct macb_dma_desc_64 {\ndrivers/net/ethernet/cadence/macb.h-865-\tu32 addrh;\n--\ndrivers/net/ethernet/cadence/macb.h-868-\ndrivers/net/ethernet/cadence/macb.h:869:struct macb_dma_desc_ptp {\ndrivers/net/ethernet/cadence/macb.h-870-\tu32\tts_1;\n--\ndrivers/net/ethernet/cadence/macb.h-965-\ndrivers/net/ethernet/cadence/macb.h:966:/ struct macb_tx_skb - data about an skb which is being transmitted\ndrivers/net/ethernet/cadence/macb.h-967- * @skb: skb currently being transmitted, only set for the last buffer\n--\ndrivers/net/ethernet/cadence/macb.h-973- /\ndrivers/net/ethernet/cadence/macb.h:974:struct macb_tx_skb {\ndrivers/net/ethernet/cadence/macb.h-975-\tstruct sk_buff\t\tskb;\n--\ndrivers/net/ethernet/cadence/macb.h-983- /\ndrivers/net/ethernet/cadence/macb.h:984:struct macb_stats {\ndrivers/net/ethernet/cadence/macb.h-985-\tu64\trx_pause_frames;\n--\ndrivers/net/ethernet/cadence/macb.h=1191=struct macb;\ndrivers/net/ethernet/cadence/macb.h:1192:struct macb_queue;\ndrivers/net/ethernet/cadence/macb.h-1193-\ndrivers/net/ethernet/cadence/macb.h:1194:struct macb_or_gem_ops {\ndrivers/net/ethernet/cadence/macb.h-1195-\tint\t(mog_alloc_rx_buffers)(struct macb bp);\n--\ndrivers/net/ethernet/cadence/macb.h-1197-\tvoid\t(mog_init_rings)(struct macb bp);\ndrivers/net/ethernet/cadence/macb.h:1198:\tint\t(mog_rx)(struct macb_queue queue, struct napi_struct napi,\ndrivers/net/ethernet/cadence/macb.h-1199-\t\t\t int budget);\n--\ndrivers/net/ethernet/cadence/macb.h-1202-/* MACB-PTP interface: adapt to platform needs. /\ndrivers/net/ethernet/cadence/macb.h:1203:struct macb_ptp_info {\ndrivers/net/ethernet/cadence/macb.h-1204-\tvoid (ptp_init)(struct net_device netdev);\n--\ndrivers/net/ethernet/cadence/macb.h-1216-\ndrivers/net/ethernet/cadence/macb.h:1217:struct macb_pm_data {\ndrivers/net/ethernet/cadence/macb.h-1218-\tu32 scrt2;\n--\ndrivers/net/ethernet/cadence/macb.h-1221-\ndrivers/net/ethernet/cadence/macb.h:1222:struct macb_usrio_config {\ndrivers/net/ethernet/cadence/macb.h-1223-\tu32 mii;\n--\ndrivers/net/ethernet/cadence/macb.h-1232-\ndrivers/net/ethernet/cadence/macb.h:1233:struct macb_config {\ndrivers/net/ethernet/cadence/macb.h-1234-\tu32\t\t\tcaps;\n--\ndrivers/net/ethernet/cadence/macb.h-1241-\tint\tjumbo_max_len;\ndrivers/net/ethernet/cadence/macb.h:1242:\tconst struct macb_usrio_config usrio;\ndrivers/net/ethernet/cadence/macb.h-1243-};\n--\ndrivers/net/ethernet/cadence/macb.h=1245=struct tsu_incr {\n--\ndrivers/net/ethernet/cadence/macb.h-1249-\ndrivers/net/ethernet/cadence/macb.h:1250:struct macb_queue {\ndrivers/net/ethernet/cadence/macb.h-1251-\tstruct macb\t\tbp;\n--\ndrivers/net/ethernet/cadence/macb.h-1269-\tunsigned int\t\ttx_head, tx_tail;\ndrivers/net/ethernet/cadence/macb.h:1270:\tstruct macb_dma_desc\ttx_ring;\ndrivers/net/ethernet/cadence/macb.h:1271:\tstruct macb_tx_skb\ttx_skb;\ndrivers/net/ethernet/cadence/macb.h-1272-\tdma_addr_t\t\ttx_ring_dma;\n--\ndrivers/net/ethernet/cadence/macb.h-1280-\tunsigned int\t\trx_prepared_head;\ndrivers/net/ethernet/cadence/macb.h:1281:\tstruct macb_dma_desc\trx_ring;\ndrivers/net/ethernet/cadence/macb.h-1282-\tstruct sk_buff\t\t*rx_skbuff;\n--\ndrivers/net/ethernet/cadence/macb.h=1298=struct macb {\n--\ndrivers/net/ethernet/cadence/macb.h-1302-\t/ hardware IO accessors /\ndrivers/net/ethernet/cadence/macb.h:1303:\tu32\t(macb_reg_readl)(struct macb bp, int offset);\ndrivers/net/ethernet/cadence/macb.h:1304:\tvoid\t(macb_reg_writel)(struct macb bp, int offset, u32 value);\ndrivers/net/ethernet/cadence/macb.h-1305-\ndrivers/net/ethernet/cadence/macb.h:1306:\tstruct macb_dma_desc\trx_ring_tieoff;\ndrivers/net/ethernet/cadence/macb.h-1307-\tdma_addr_t\t\trx_ring_tieoff_dma;\n--\ndrivers/net/ethernet/cadence/macb.h-1313-\tunsigned int\t\tnum_queues;\ndrivers/net/ethernet/cadence/macb.h:1314:\tstruct macb_queue\tqueues[MACB_MAX_QUEUES];\ndrivers/net/ethernet/cadence/macb.h-1315-\n--\ndrivers/net/ethernet/cadence/macb.h-1326-\tunion {\ndrivers/net/ethernet/cadence/macb.h:1327:\t\tstruct macb_stats\tmacb;\ndrivers/net/ethernet/cadence/macb.h-1328-\t\tstruct gem_stats\tgem;\n--\ndrivers/net/ethernet/cadence/macb.h-1330-\ndrivers/net/ethernet/cadence/macb.h:1331:\tstruct macb_or_gem_ops\tmacbgem_ops;\ndrivers/net/ethernet/cadence/macb.h-1332-\n--\ndrivers/net/ethernet/cadence/macb.h-1344-\t/* AT91RM9200 transmit queue (1 on wire + 1 queued) /\ndrivers/net/ethernet/cadence/macb.h:1345:\tstruct macb_tx_skb\trm9200_txq[2];\ndrivers/net/ethernet/cadence/macb.h-1346-\tunsigned int\t\tmax_tx_length;\n--\ndrivers/net/ethernet/cadence/macb.h-1358-\ndrivers/net/ethernet/cadence/macb.h:1359:\tstruct macb_ptp_info\tptp_info;\t/* macb-ptp interface /\ndrivers/net/ethernet/cadence/macb.h-1360-\n--\ndrivers/net/ethernet/cadence/macb.h-1386-\ndrivers/net/ethernet/cadence/macb.h:1387:\tstruct macb_pm_data pm_data;\ndrivers/net/ethernet/cadence/macb.h:1388:\tconst struct macb_usrio_config usrio;\ndrivers/net/ethernet/cadence/macb.h-1389-};\n--\ndrivers/net/ethernet/cadence/macb.h-1395-\ndrivers/net/ethernet/cadence/macb.h:1396:enum macb_bd_control {\ndrivers/net/ethernet/cadence/macb.h-1397-\tTSTAMP_DISABLED,\n--\ndrivers/net/ethernet/cadence/macb.h=1404=void gem_ptp_remove(struct net_device netdev);\ndrivers/net/ethernet/cadence/macb.h:1405:void gem_ptp_txstamp(struct macb bp, struct sk_buff skb, struct macb_dma_desc desc);\ndrivers/net/ethernet/cadence/macb.h:1406:void gem_ptp_rxstamp(struct macb bp, struct sk_buff skb, struct macb_dma_desc desc);\ndrivers/net/ethernet/cadence/macb.h:1407:static inline void gem_ptp_do_txstamp(struct macb bp, struct sk_buff skb, struct macb_dma_desc desc)\ndrivers/net/ethernet/cadence/macb.h-1408-{\n--\ndrivers/net/ethernet/cadence/macb.h-1414-\ndrivers/net/ethernet/cadence/macb.h:1415:static inline void gem_ptp_do_rxstamp(struct macb bp, struct sk_buff skb, struct macb_dma_desc desc)\ndrivers/net/ethernet/cadence/macb.h-1416-{\n--\ndrivers/net/ethernet/cadence/macb.h=1430=static inline void gem_ptp_remove(struct net_device netdev) { }\ndrivers/net/ethernet/cadence/macb.h-1431-\ndrivers/net/ethernet/cadence/macb.h:1432:static inline void gem_ptp_do_txstamp(struct macb bp, struct sk_buff skb, struct macb_dma_desc desc) { }\ndrivers/net/ethernet/cadence/macb.h:1433:static inline void gem_ptp_do_rxstamp(struct macb bp, struct sk_buff skb, struct macb_dma_desc desc) { }\ndrivers/net/ethernet/cadence/macb.h-1434-#endif\ndrivers/net/ethernet/cadence/macb.h-1435-\ndrivers/net/ethernet/cadence/macb.h:1436:static inline bool macb_is_gem(struct macb bp)\ndrivers/net/ethernet/cadence/macb.h-1437-{\n--\ndrivers/net/ethernet/cadence/macb.h=1453=static inline u64 enst_max_hw_interval(u32 speed_mbps)\n--\ndrivers/net/ethernet/cadence/macb.h-1458-\ndrivers/net/ethernet/cadence/macb.h:1459:static inline bool macb_dma64(struct macb bp)\ndrivers/net/ethernet/cadence/macb.h-1460-{\n--\ndrivers/net/ethernet/cadence/macb.h-1464-\ndrivers/net/ethernet/cadence/macb.h:1465:static inline bool macb_dma_ptp(struct macb bp)\ndrivers/net/ethernet/cadence/macb.h-1466-{\n--\ndrivers/net/ethernet/cadence/macb.h-1470-\ndrivers/net/ethernet/cadence/macb.h:1471:static inline void macb_queue_isr_clear(struct macb bp,\ndrivers/net/ethernet/cadence/macb.h:1472:\t\t\t\t\tstruct macb_queue queue, u32 value)\ndrivers/net/ethernet/cadence/macb.h-1473-{\n--\ndrivers/net/ethernet/cadence/macb.h-1478-/\ndrivers/net/ethernet/cadence/macb.h:1479: struct macb_platform_data - platform data for MACB Ethernet used for PCI registration\ndrivers/net/ethernet/cadence/macb.h-1480- * @pclk:\t\tplatform clock\n--\ndrivers/net/ethernet/cadence/macb.h-1482- /\ndrivers/net/ethernet/cadence/macb.h:1483:struct macb_platform_data {\ndrivers/net/ethernet/cadence/macb.h-1484-\tstruct clk\tpclk;\n--\ndrivers/net/ethernet/cadence/macb.h-1488-/*\ndrivers/net/ethernet/cadence/macb.h:1489: struct macb_queue_enst_config - Configuration for Enhanced Scheduled Traffic\ndrivers/net/ethernet/cadence/macb.h-1490- * @start_time_mask: Bitmask representing the start time for the queue\n--\ndrivers/net/ethernet/cadence/macb.h-1497- /\ndrivers/net/ethernet/cadence/macb.h:1498:struct macb_queue_enst_config {\ndrivers/net/ethernet/cadence/macb.h-1499-\tu32 start_time_mask;\n--\ndrivers/net/ethernet/cadence/macb_main.c-44-/ This structure is only used for MACB on SiFive FU540 devices /\ndrivers/net/ethernet/cadence/macb_main.c:45:struct sifive_fu540_macb_mgmt {\ndrivers/net/ethernet/cadence/macb_main.c-46-\tvoid __iomem reg;\n--\ndrivers/net/ethernet/cadence/macb_main.c-128- /\ndrivers/net/ethernet/cadence/macb_main.c:129:static unsigned int macb_dma_desc_get_size(struct macb bp)\ndrivers/net/ethernet/cadence/macb_main.c-130-{\ndrivers/net/ethernet/cadence/macb_main.c:131:\tunsigned int desc_size = sizeof(struct macb_dma_desc);\ndrivers/net/ethernet/cadence/macb_main.c-132-\ndrivers/net/ethernet/cadence/macb_main.c:133:\tif (macb_dma64(bp))\ndrivers/net/ethernet/cadence/macb_main.c:134:\t\tdesc_size += sizeof(struct macb_dma_desc_64);\ndrivers/net/ethernet/cadence/macb_main.c:135:\tif (macb_dma_ptp(bp))\ndrivers/net/ethernet/cadence/macb_main.c:136:\t\tdesc_size += sizeof(struct macb_dma_desc_ptp);\ndrivers/net/ethernet/cadence/macb_main.c-137-\n--\ndrivers/net/ethernet/cadence/macb_main.c-140-\ndrivers/net/ethernet/cadence/macb_main.c:141:static unsigned int macb_adj_dma_desc_idx(struct macb bp, unsigned int desc_idx)\ndrivers/net/ethernet/cadence/macb_main.c-142-{\ndrivers/net/ethernet/cadence/macb_main.c:143:\treturn desc_idx (1 + macb_dma64(bp) + macb_dma_ptp(bp));\ndrivers/net/ethernet/cadence/macb_main.c-144-}\ndrivers/net/ethernet/cadence/macb_main.c-145-\ndrivers/net/ethernet/cadence/macb_main.c:146:static struct macb_dma_desc_64 macb_64b_desc(struct macb bp, struct macb_dma_desc desc)\ndrivers/net/ethernet/cadence/macb_main.c-147-{\ndrivers/net/ethernet/cadence/macb_main.c:148:\treturn (struct macb_dma_desc_64 )((void )desc\ndrivers/net/ethernet/cadence/macb_main.c:149:\t\t+ sizeof(struct macb_dma_desc));\ndrivers/net/ethernet/cadence/macb_main.c-150-}\n--\ndrivers/net/ethernet/cadence/macb_main.c-152-/ Ring buffer accessors /\ndrivers/net/ethernet/cadence/macb_main.c:153:static unsigned int macb_tx_ring_wrap(struct macb bp, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-154-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-157-\ndrivers/net/ethernet/cadence/macb_main.c:158:static struct macb_dma_desc macb_tx_desc(struct macb_queue queue,\ndrivers/net/ethernet/cadence/macb_main.c-159-\t\t\t\t\t unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-160-{\ndrivers/net/ethernet/cadence/macb_main.c:161:\tindex = macb_tx_ring_wrap(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c:162:\tindex = macb_adj_dma_desc_idx(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c-163-\treturn \u0026queue-\u003etx_ring[index];\n--\ndrivers/net/ethernet/cadence/macb_main.c-165-\ndrivers/net/ethernet/cadence/macb_main.c:166:static struct macb_tx_skb macb_tx_skb(struct macb_queue queue,\ndrivers/net/ethernet/cadence/macb_main.c-167-\t\t\t\t unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-168-{\ndrivers/net/ethernet/cadence/macb_main.c:169:\treturn \u0026queue-\u003etx_skb[macb_tx_ring_wrap(queue-\u003ebp, index)];\ndrivers/net/ethernet/cadence/macb_main.c-170-}\ndrivers/net/ethernet/cadence/macb_main.c-171-\ndrivers/net/ethernet/cadence/macb_main.c:172:static dma_addr_t macb_tx_dma(struct macb_queue queue, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-173-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-175-\ndrivers/net/ethernet/cadence/macb_main.c:176:\toffset = macb_tx_ring_wrap(queue-\u003ebp, index) \ndrivers/net/ethernet/cadence/macb_main.c:177:\t\t\tmacb_dma_desc_get_size(queue-\u003ebp);\ndrivers/net/ethernet/cadence/macb_main.c-178-\n--\ndrivers/net/ethernet/cadence/macb_main.c-181-\ndrivers/net/ethernet/cadence/macb_main.c:182:static unsigned int macb_rx_ring_wrap(struct macb bp, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-183-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-186-\ndrivers/net/ethernet/cadence/macb_main.c:187:static struct macb_dma_desc macb_rx_desc(struct macb_queue queue, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-188-{\ndrivers/net/ethernet/cadence/macb_main.c:189:\tindex = macb_rx_ring_wrap(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c:190:\tindex = macb_adj_dma_desc_idx(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c-191-\treturn \u0026queue-\u003erx_ring[index];\n--\ndrivers/net/ethernet/cadence/macb_main.c-193-\ndrivers/net/ethernet/cadence/macb_main.c:194:static void macb_rx_buffer(struct macb_queue queue, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-195-{\ndrivers/net/ethernet/cadence/macb_main.c-196-\treturn queue-\u003erx_buffers + queue-\u003ebp-\u003erx_buffer_size \ndrivers/net/ethernet/cadence/macb_main.c:197:\t macb_rx_ring_wrap(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c-198-}\n--\ndrivers/net/ethernet/cadence/macb_main.c=238=static bool hw_is_gem(void __iomem addr, bool native_io)\n--\ndrivers/net/ethernet/cadence/macb_main.c-249-\ndrivers/net/ethernet/cadence/macb_main.c:250:static void macb_set_hwaddr(struct macb bp)\ndrivers/net/ethernet/cadence/macb_main.c-251-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-255-\tbottom = get_unaligned_le32(bp-\u003enetdev-\u003edev_addr);\ndrivers/net/ethernet/cadence/macb_main.c:256:\tmacb_or_gem_writel(bp, SA1B, bottom);\ndrivers/net/ethernet/cadence/macb_main.c-257-\ttop = get_unaligned_le16(bp-\u003enetdev-\u003edev_addr + 4);\ndrivers/net/ethernet/cadence/macb_main.c:258:\tmacb_or_gem_writel(bp, SA1T, top);\ndrivers/net/ethernet/cadence/macb_main.c-259-\n--\ndrivers/net/ethernet/cadence/macb_main.c-265-\t/* Clear unused address register sets /\ndrivers/net/ethernet/cadence/macb_main.c:266:\tmacb_or_gem_writel(bp, SA2B, 0);\ndrivers/net/ethernet/cadence/macb_main.c:267:\tmacb_or_gem_writel(bp, SA2T, 0);\ndrivers/net/ethernet/cadence/macb_main.c:268:\tmacb_or_gem_writel(bp, SA3B, 0);\ndrivers/net/ethernet/cadence/macb_main.c:269:\tmacb_or_gem_writel(bp, SA3T, 0);\ndrivers/net/ethernet/cadence/macb_main.c:270:\tmacb_or_gem_writel(bp, SA4B, 0);\ndrivers/net/ethernet/cadence/macb_main.c:271:\tmacb_or_gem_writel(bp, SA4T, 0);\ndrivers/net/ethernet/cadence/macb_main.c-272-}\ndrivers/net/ethernet/cadence/macb_main.c-273-\ndrivers/net/ethernet/cadence/macb_main.c:274:static void macb_get_hwaddr(struct macb bp)\ndrivers/net/ethernet/cadence/macb_main.c-275-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-282-\tfor (i = 0; i \u003c 4; i++) {\ndrivers/net/ethernet/cadence/macb_main.c:283:\t\tbottom = macb_or_gem_readl(bp, SA1B + i * 8);\ndrivers/net/ethernet/cadence/macb_main.c:284:\t\ttop = macb_or_gem_readl(bp, SA1T + i * 8);\ndrivers/net/ethernet/cadence/macb_main.c-285-\n--\ndrivers/net/ethernet/cadence/macb_main.c-302-\ndrivers/net/ethernet/cadence/macb_main.c:303:static int macb_mdio_wait_for_idle(struct macb bp)\ndrivers/net/ethernet/cadence/macb_main.c-304-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-310-\ndrivers/net/ethernet/cadence/macb_main.c:311:static int macb_mdio_read_c22(struct mii_bus bus, int mii_id, int regnum)\ndrivers/net/ethernet/cadence/macb_main.c-312-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-319-\ndrivers/net/ethernet/cadence/macb_main.c:320:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-321-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-323-\ndrivers/net/ethernet/cadence/macb_main.c:324:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-325-\t\t\t \| MACB_BF(RW, MACB_MAN_C22_READ)\n--\ndrivers/net/ethernet/cadence/macb_main.c-329-\ndrivers/net/ethernet/cadence/macb_main.c:330:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-331-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-333-\ndrivers/net/ethernet/cadence/macb_main.c:334:\tstatus = MACB_BFEXT(DATA, macb_readl(bp, MAN));\ndrivers/net/ethernet/cadence/macb_main.c-335-\n--\ndrivers/net/ethernet/cadence/macb_main.c-341-\ndrivers/net/ethernet/cadence/macb_main.c:342:static int macb_mdio_read_c45(struct mii_bus bus, int mii_id, int devad,\ndrivers/net/ethernet/cadence/macb_main.c-343-\t\t\t int regnum)\n--\ndrivers/net/ethernet/cadence/macb_main.c-353-\ndrivers/net/ethernet/cadence/macb_main.c:354:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-355-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-357-\ndrivers/net/ethernet/cadence/macb_main.c:358:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-359-\t\t\t \| MACB_BF(RW, MACB_MAN_C45_ADDR)\n--\ndrivers/net/ethernet/cadence/macb_main.c-364-\ndrivers/net/ethernet/cadence/macb_main.c:365:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-366-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-368-\ndrivers/net/ethernet/cadence/macb_main.c:369:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-370-\t\t\t \| MACB_BF(RW, MACB_MAN_C45_READ)\n--\ndrivers/net/ethernet/cadence/macb_main.c-374-\ndrivers/net/ethernet/cadence/macb_main.c:375:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-376-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-378-\ndrivers/net/ethernet/cadence/macb_main.c:379:\tstatus = MACB_BFEXT(DATA, macb_readl(bp, MAN));\ndrivers/net/ethernet/cadence/macb_main.c-380-\n--\ndrivers/net/ethernet/cadence/macb_main.c-386-\ndrivers/net/ethernet/cadence/macb_main.c:387:static int macb_mdio_write_c22(struct mii_bus bus, int mii_id, int regnum,\ndrivers/net/ethernet/cadence/macb_main.c-388-\t\t\t u16 value)\n--\ndrivers/net/ethernet/cadence/macb_main.c-396-\ndrivers/net/ethernet/cadence/macb_main.c:397:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-398-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-400-\ndrivers/net/ethernet/cadence/macb_main.c:401:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-402-\t\t\t \| MACB_BF(RW, MACB_MAN_C22_WRITE)\n--\ndrivers/net/ethernet/cadence/macb_main.c-407-\ndrivers/net/ethernet/cadence/macb_main.c:408:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-409-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-417-\ndrivers/net/ethernet/cadence/macb_main.c:418:static int macb_mdio_write_c45(struct mii_bus bus, int mii_id,\ndrivers/net/ethernet/cadence/macb_main.c-419-\t\t\t int devad, int regnum,\n--\ndrivers/net/ethernet/cadence/macb_main.c-430-\ndrivers/net/ethernet/cadence/macb_main.c:431:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-432-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-434-\ndrivers/net/ethernet/cadence/macb_main.c:435:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-436-\t\t\t \| MACB_BF(RW, MACB_MAN_C45_ADDR)\n--\ndrivers/net/ethernet/cadence/macb_main.c-441-\ndrivers/net/ethernet/cadence/macb_main.c:442:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-443-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-445-\ndrivers/net/ethernet/cadence/macb_main.c:446:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-447-\t\t\t \| MACB_BF(RW, MACB_MAN_C45_WRITE)\n--\ndrivers/net/ethernet/cadence/macb_main.c-452-\ndrivers/net/ethernet/cadence/macb_main.c:453:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-454-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-462-\ndrivers/net/ethernet/cadence/macb_main.c:463:static void macb_init_buffers(struct macb bp)\ndrivers/net/ethernet/cadence/macb_main.c-464-{\ndrivers/net/ethernet/cadence/macb_main.c:465:\tstruct macb_queue queue;\ndrivers/net/ethernet/cadence/macb_main.c-466-\tunsigned int q;\n--\ndrivers/net/ethernet/cadence/macb_main.c-468-\t/ Single register for all queues' high 32 bits. /\ndrivers/net/ethernet/cadence/macb_main.c:469:\tif (macb_dma64(bp)) {\ndrivers/net/ethernet/cadence/macb_main.c:470:\t\tmacb_writel(bp, RBQPH,\ndrivers/net/ethernet/cadence/macb_main.c-471-\t\t\t upper_32_bits(bp-\u003equeues[0].rx_ring_dma));\ndrivers/net/ethernet/cadence/macb_main.c:472:\t\tmacb_writel(bp, TBQPH,\ndrivers/net/ethernet/cadence/macb_main.c-473-\t\t\t upper_32_bits(bp-\u003equeues[0].tx_ring_dma));\n--\ndrivers/net/ethernet/cadence/macb_main.c-482-/\ndrivers/net/ethernet/cadence/macb_main.c:483: macb_set_tx_clk() - Set a clock to a new frequency\ndrivers/net/ethernet/cadence/macb_main.c-484- * @bp:\t\tpointer to struct macb\n--\ndrivers/net/ethernet/cadence/macb_main.c-486- /\ndrivers/net/ethernet/cadence/macb_main.c:487:static void macb_set_tx_clk(struct macb bp, int speed)\ndrivers/net/ethernet/cadence/macb_main.c-488-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-519-\ndrivers/net/ethernet/cadence/macb_main.c:520:static void macb_usx_pcs_link_up(struct phylink_pcs pcs, unsigned int neg_mode,\ndrivers/net/ethernet/cadence/macb_main.c-521-\t\t\t\t phy_interface_t interface, int speed,\n--\ndrivers/net/ethernet/cadence/macb_main.c-534-\ndrivers/net/ethernet/cadence/macb_main.c:535:static void macb_usx_pcs_get_state(struct phylink_pcs pcs,\ndrivers/net/ethernet/cadence/macb_main.c-536-\t\t\t\t unsigned int neg_mode,\n--\ndrivers/net/ethernet/cadence/macb_main.c-552-\ndrivers/net/ethernet/cadence/macb_main.c:553:static int macb_usx_pcs_config(struct phylink_pcs pcs,\ndrivers/net/ethernet/cadence/macb_main.c-554-\t\t\t unsigned int neg_mode,\n--\ndrivers/net/ethernet/cadence/macb_main.c-566-\ndrivers/net/ethernet/cadence/macb_main.c:567:static unsigned int macb_pcs_inband_caps(struct phylink_pcs pcs,\ndrivers/net/ethernet/cadence/macb_main.c-568-\t\t\t\t\t phy_interface_t interface)\n--\ndrivers/net/ethernet/cadence/macb_main.c-572-\ndrivers/net/ethernet/cadence/macb_main.c:573:static void macb_pcs_get_state(struct phylink_pcs pcs, unsigned int neg_mode,\ndrivers/net/ethernet/cadence/macb_main.c-574-\t\t\t struct phylink_link_state state)\n--\ndrivers/net/ethernet/cadence/macb_main.c-583-\ndrivers/net/ethernet/cadence/macb_main.c:584:static void macb_pcs_an_restart(struct phylink_pcs pcs)\ndrivers/net/ethernet/cadence/macb_main.c-585-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-588-\ndrivers/net/ethernet/cadence/macb_main.c:589:static int macb_pcs_config(struct phylink_pcs pcs,\ndrivers/net/ethernet/cadence/macb_main.c-590-\t\t\t unsigned int neg_mode,\n--\ndrivers/net/ethernet/cadence/macb_main.c-604-\t * Must be written after PCSSEL is set in NCFGR which is done in\ndrivers/net/ethernet/cadence/macb_main.c:605:\t * macb_mac_config(), otherwise writes will not take effect.\ndrivers/net/ethernet/cadence/macb_main.c-606-\t /\n--\ndrivers/net/ethernet/cadence/macb_main.c-617-\ndrivers/net/ethernet/cadence/macb_main.c:618:static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {\ndrivers/net/ethernet/cadence/macb_main.c:619:\t.pcs_get_state = macb_usx_pcs_get_state,\ndrivers/net/ethernet/cadence/macb_main.c:620:\t.pcs_config = macb_usx_pcs_config,\ndrivers/net/ethernet/cadence/macb_main.c:621:\t.pcs_link_up = macb_usx_pcs_link_up,\ndrivers/net/ethernet/cadence/macb_main.c-622-};\ndrivers/net/ethernet/cadence/macb_main.c-623-\ndrivers/net/ethernet/cadence/macb_main.c:624:static const struct phylink_pcs_ops macb_phylink_pcs_ops = {\ndrivers/net/ethernet/cadence/macb_main.c:625:\t.pcs_inband_caps = macb_pcs_inband_caps,\ndrivers/net/ethernet/cadence/macb_main.c:626:\t.pcs_get_state = macb_pcs_get_state,\ndrivers/net/ethernet/cadence/macb_main.c:627:\t.pcs_an_restart = macb_pcs_an_restart,\ndrivers/net/ethernet/cadence/macb_main.c:628:\t.pcs_config = macb_pcs_config,\ndrivers/net/ethernet/cadence/macb_main.c-629-};\ndrivers/net/ethernet/cadence/macb_main.c-630-\ndrivers/net/ethernet/cadence/macb_main.c:631:static bool macb_tx_lpi_set(struct macb bp, bool enable)\ndrivers/net/ethernet/cadence/macb_main.c-632-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-636-\ndrivers/net/ethernet/cadence/macb_main.c:637:\tncr = macb_readl(bp, NCR);\ndrivers/net/ethernet/cadence/macb_main.c-638-\told = ncr;\n--\ndrivers/net/ethernet/cadence/macb_main.c-643-\tif (old != ncr)\ndrivers/net/ethernet/cadence/macb_main.c:644:\t\tmacb_writel(bp, NCR, ncr);\ndrivers/net/ethernet/cadence/macb_main.c-645-\n--\ndrivers/net/ethernet/cadence/macb_main.c-648-\ndrivers/net/ethernet/cadence/macb_main.c:649:static bool macb_tx_all_queues_idle(struct macb bp)\ndrivers/net/ethernet/cadence/macb_main.c-650-{\ndrivers/net/ethernet/cadence/macb_main.c:651:\tstruct macb_queue queue;\ndrivers/net/ethernet/cadence/macb_main.c-652-\tunsigned int q;\n--\ndrivers/net/ethernet/cadence/macb_main.c-660-\ndrivers/net/ethernet/cadence/macb_main.c:661:static void macb_tx_lpi_work_fn(struct work_struct work)\ndrivers/net/ethernet/cadence/macb_main.c-662-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-666-\tspin_lock_irqsave(\u0026bp-\u003elock, flags);\ndrivers/net/ethernet/cadence/macb_main.c:667:\tif (bp-\u003eeee_active \u0026\u0026 macb_tx_all_queues_idle(bp))\ndrivers/net/ethernet/cadence/macb_main.c:668:\t\tmacb_tx_lpi_set(bp, true);\ndrivers/net/ethernet/cadence/macb_main.c-669-\tspin_unlock_irqrestore(\u0026bp-\u003elock, flags);\n--\ndrivers/net/ethernet/cadence/macb_main.c-671-\ndrivers/net/ethernet/cadence/macb_main.c:672:static void macb_tx_lpi_schedule(struct macb bp)\ndrivers/net/ethernet/cadence/macb_main.c-673-{\n\n" }
23/2	2026/08/30 16:42	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 44372 output: 35 thoughts: 40 Thoughts: Here's my summary, as though I'm thinking through this process: Tracing the PTP Initialization Okay, so I'm digging into how Precision Time Protocol (PTP) is initialized within this driver. The initial clue is that `gem_ptp_init` gets called, and from what I remember, I believe it's happening within `macb_main.c`. Now, the next logical step is to pinpoint exactly where that function call lives within the code. Let's fire up the search tools and see what we can find. I need to understand the call stack and how this PTP initialization fits into the overall MACB driver's startup sequence. That will tell me everything I need to know about the device.
24/2	2026/08/30 16:42	tool	grepper	0m Args: { "Expression": "gem_ptp_init", "PathPrefix": "drivers/net/ethernet/cadence" } Results: { "Output": "drivers/net/ethernet/cadence/macb.h=1396=enum macb_bd_control {\n--\ndrivers/net/ethernet/cadence/macb.h-1402-\ndrivers/net/ethernet/cadence/macb.h:1403:void gem_ptp_init(struct net_device netdev);\ndrivers/net/ethernet/cadence/macb.h-1404-void gem_ptp_remove(struct net_device netdev);\n--\ndrivers/net/ethernet/cadence/macb.h=1425=int gem_set_hwtst(struct net_device netdev,\n--\ndrivers/net/ethernet/cadence/macb.h-1428-#else\ndrivers/net/ethernet/cadence/macb.h:1429:static inline void gem_ptp_init(struct net_device netdev) { }\ndrivers/net/ethernet/cadence/macb.h-1430-static inline void gem_ptp_remove(struct net_device netdev) { }\n--\ndrivers/net/ethernet/cadence/macb_main.c=3775=static struct macb_ptp_info gem_ptp_info = {\ndrivers/net/ethernet/cadence/macb_main.c:3776:\t.ptp_init\t = gem_ptp_init,\ndrivers/net/ethernet/cadence/macb_main.c-3777-\t.ptp_remove\t = gem_ptp_remove,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=191=static const struct ptp_clock_info gem_ptp_caps_template = {\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-206-\ndrivers/net/ethernet/cadence/macb_ptp.c:207:static void gem_ptp_init_timer(struct macb bp)\ndrivers/net/ethernet/cadence/macb_ptp.c-208-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-221-\ndrivers/net/ethernet/cadence/macb_ptp.c:222:static void gem_ptp_init_tsu(struct macb bp)\ndrivers/net/ethernet/cadence/macb_ptp.c-223-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=297=void gem_ptp_txstamp(struct macb bp, struct sk_buff skb,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-326-\ndrivers/net/ethernet/cadence/macb_ptp.c:327:void gem_ptp_init(struct net_device netdev)\ndrivers/net/ethernet/cadence/macb_ptp.c-328-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-337-\tbp-\u003eptp_clock_info.max_adj = bp-\u003eptp_info-\u003eget_ptp_max_adj();\ndrivers/net/ethernet/cadence/macb_ptp.c:338:\tgem_ptp_init_timer(bp);\ndrivers/net/ethernet/cadence/macb_ptp.c-339-\tbp-\u003eptp_clock = ptp_clock_register(\u0026bp-\u003eptp_clock_info, \u0026netdev-\u003edev);\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-349-\ndrivers/net/ethernet/cadence/macb_ptp.c:350:\tgem_ptp_init_tsu(bp);\ndrivers/net/ethernet/cadence/macb_ptp.c-351-\n" }
25/2	2026/08/30 16:42	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 45591 output: 33 thoughts: 29 Thoughts: Okay, here's my take on those thoughts, tailored for an expert audience: Tracing the PTP Initialization in macb_main.c Alright, let's dive into this. I need to understand how the PTP initialization routine, specifically `gem_ptp_info.ptp_init`, is being called within `macb_main.c`. My immediate thought is to track down the callers – which other functions within that file are invoking `gem_ptp_info.ptp_init`? This is the crucial starting point for understanding the overall initialization sequence and the role of PTP within the broader MACB driver context. I'll need to use my usual methods, likely a combination of static analysis (grepping or using an IDE's cross-referencing capabilities) and perhaps even some dynamic tracing if the static analysis proves insufficient or if I suspect conditional calls that are not immediately obvious from the source code. The goal is a clear understanding of the initialization flow.
26/2	2026/08/30 16:43	tool	grepper	0m Args: { "Expression": "ptp_init", "PathPrefix": "drivers/net/ethernet/cadence" } Results: { "Output": "drivers/net/ethernet/cadence/macb.h=1203=struct macb_ptp_info {\ndrivers/net/ethernet/cadence/macb.h:1204:\tvoid (ptp_init)(struct net_device netdev);\ndrivers/net/ethernet/cadence/macb.h-1205-\tvoid (ptp_remove)(struct net_device netdev);\n--\ndrivers/net/ethernet/cadence/macb.h=1396=enum macb_bd_control {\n--\ndrivers/net/ethernet/cadence/macb.h-1402-\ndrivers/net/ethernet/cadence/macb.h:1403:void gem_ptp_init(struct net_device netdev);\ndrivers/net/ethernet/cadence/macb.h-1404-void gem_ptp_remove(struct net_device netdev);\n--\ndrivers/net/ethernet/cadence/macb.h=1425=int gem_set_hwtst(struct net_device netdev,\n--\ndrivers/net/ethernet/cadence/macb.h-1428-#else\ndrivers/net/ethernet/cadence/macb.h:1429:static inline void gem_ptp_init(struct net_device netdev) { }\ndrivers/net/ethernet/cadence/macb.h-1430-static inline void gem_ptp_remove(struct net_device netdev) { }\n--\ndrivers/net/ethernet/cadence/macb_main.c=3129=static int macb_open(struct net_device netdev)\n--\ndrivers/net/ethernet/cadence/macb_main.c-3177-\tif (bp-\u003eptp_info)\ndrivers/net/ethernet/cadence/macb_main.c:3178:\t\tbp-\u003eptp_info-\u003eptp_init(netdev);\ndrivers/net/ethernet/cadence/macb_main.c-3179-\n--\ndrivers/net/ethernet/cadence/macb_main.c=3775=static struct macb_ptp_info gem_ptp_info = {\ndrivers/net/ethernet/cadence/macb_main.c:3776:\t.ptp_init\t = gem_ptp_init,\ndrivers/net/ethernet/cadence/macb_main.c-3777-\t.ptp_remove\t = gem_ptp_remove,\n--\ndrivers/net/ethernet/cadence/macb_main.c=6133=static int __maybe_unused macb_resume(struct device dev)\n--\ndrivers/net/ethernet/cadence/macb_main.c-6207-\tif (bp-\u003eptp_info)\ndrivers/net/ethernet/cadence/macb_main.c:6208:\t\tbp-\u003eptp_info-\u003eptp_init(netdev);\ndrivers/net/ethernet/cadence/macb_main.c-6209-\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=191=static const struct ptp_clock_info gem_ptp_caps_template = {\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-206-\ndrivers/net/ethernet/cadence/macb_ptp.c:207:static void gem_ptp_init_timer(struct macb bp)\ndrivers/net/ethernet/cadence/macb_ptp.c-208-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-221-\ndrivers/net/ethernet/cadence/macb_ptp.c:222:static void gem_ptp_init_tsu(struct macb bp)\ndrivers/net/ethernet/cadence/macb_ptp.c-223-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=297=void gem_ptp_txstamp(struct macb bp, struct sk_buff skb,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-326-\ndrivers/net/ethernet/cadence/macb_ptp.c:327:void gem_ptp_init(struct net_device netdev)\ndrivers/net/ethernet/cadence/macb_ptp.c-328-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-337-\tbp-\u003eptp_clock_info.max_adj = bp-\u003eptp_info-\u003eget_ptp_max_adj();\ndrivers/net/ethernet/cadence/macb_ptp.c:338:\tgem_ptp_init_timer(bp);\ndrivers/net/ethernet/cadence/macb_ptp.c-339-\tbp-\u003eptp_clock = ptp_clock_register(\u0026bp-\u003eptp_clock_info, \u0026netdev-\u003edev);\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-349-\ndrivers/net/ethernet/cadence/macb_ptp.c:350:\tgem_ptp_init_tsu(bp);\ndrivers/net/ethernet/cadence/macb_ptp.c-351-\n" }
27/2	2026/08/30 16:43	llm	patch-evaluator	0m Model: gemini-3.7-flash Args: null Results: null Tokens: input: 47227 output: 158 thoughts: 1377 Thoughts: WorthFuzzing Assessment: Cadence MACB/GEM Driver Okay, let's break this down. First, `gem_ptp_init` is called by `macb_open`, which is `ndo_open`, got it. Now, the key question is whether this Cadence MACB driver can be instantiated in standard QEMU or GCE fuzzing environments. We need to be meticulous. Let's revisit the rules. The criteria stipulate that we return `WorthFuzzing=false` if the patch concerns modifications to documentation, Kconfig, comments, cosmetic changes, non-functional numeric constants/macros, or unreachable code paths in standard virtualized environments. Specifically, the rules exclude code paths that are inaccessible in QEMU/GCE, even with software-emulated hardware. This also applies to vendor-specific PCIe switch, SmartNIC, or GPU drivers requiring physical PCIe hardware not emulated in standard QEMU. Finally, teardown callbacks are also uninteresting in this context. Right, so, is the Cadence MACB/GEM a hardware-specific SoC/PCI driver not reachable in standard virtualized environments? Let's check. How is Cadence MACB probed? It's probed via DT (Device Tree) with compatible strings like `cdns,at91sam9260-macb`, `cdns,macb`, `cdns,gem`, `xlnx,zynq-gem`, `sifive,fu540-c000-gem`, and also via PCI with ID 0x17cd:0xe007 (Cadence PCI GEM). Now, is this Cadence GEM emulated in standard QEMU x86_64 or ARM64 virt machines? No! Standard QEMU x86_64 uses e1000, e1000e, rtl8139, virtio-net-pci, etc., and standard ARM64 virt uses virtio-net-pci. Cadence GEM in QEMU is only available if running specific machine boards like `xlnx-zcu102`, `zynq-a9`, or `sifive_u`. GCE or standard QEMU (x86_64 or ARM64 virt) do not offer Cadence GEM hardware or PCI devices. Okay, what about syzkaller? Can syzkaller run on instances testing these drivers? Standard Linux fuzzing in syzkaller is x86_64 and arm64 virt. The rules are clear: code paths that are impossible to reach in virtualized environments like GCE or QEMU are excluded, along with vendor-specific PCIe switch, SmartNIC, or GPU drivers requiring physical PCIe hardware. So, `drivers/net/ethernet/cadence/`... Is Cadence MACB a vendor-specific hardware driver? Yes! It's an Ethernet MAC driver for Cadence IP found on Atmel/Microchip AT91/SAMA5, Xilinx Zynq, SiFive FU540, and Cadence's internal PCI FPGA prototype board. It's unreachable without that specific physical hardware or specialized embedded SoC emulation. There's no software device/mock/virtual device or USB interface that uses macb. MACB is purely an MMIO platform driver or a CDNS PCI wrapper for the Cadence IP core. It's inaccessible in standard fuzzing environments. Let's confirm the `WorthFuzzing` should be false based on the criteria: "Return WorthFuzzing=false if... code paths that are impossible to reach in virtualized environments like GCE or QEMU... Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers that require physical PCIe hardware cards not emulated in standard QEMU." Indeed, the Cadence MACB / GEM ethernet driver (`drivers/net/ethernet/cadence/macb_ptp.c`) requires specific physical hardware (Atmel / Microchip SoC, Xilinx Zynq, SiFive RISC-V SoC, or Cadence PCI FPGA test device) that is not available or emulated in standard virtualized fuzzing environments (QEMU virt/GCE). Therefore, the conclusion is: `WorthFuzzing = false`. `EnableConfigs = []`. `FocusSymbols = []`. The reasoning: The patch fixes the initialization order of the spinlock `tsu_clk_lock` in `gem_ptp_init` within the Cadence MACB/GEM network driver. This driver targets embedded SoCs (Atmel/Microchip, Xilinx Zynq, SiFive) and Cadence PCI test hardware that are not present in standard virtualized fuzzing environments like QEMU virt/GCE. Quick
28/2	2026/08/30 16:43	tool	set-results	0m Args: { "EnableConfigs": [], "FocusSymbols": [], "Reasoning": "The patch fixes the initialization order of `bp-\u003etsu_clk_lock` before registering the PTP clock in `gem_ptp_init()` for the Cadence MACB/GEM network driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver is for hardware-specific Cadence Ethernet MAC IP on embedded SoCs (such as Atmel/Microchip, Xilinx Zynq, SiFive) or proprietary PCI test cards, which are not present in standard virtualized fuzzing environments (e.g. QEMU standard virt / GCE).", "WorthFuzzing": false } Results: { "EnableConfigs": null, "FocusSymbols": [], "Reasoning": "The patch fixes the initialization order of `bp-\u003etsu_clk_lock` before registering the PTP clock in `gem_ptp_init()` for the Cadence MACB/GEM network driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver is for hardware-specific Cadence Ethernet MAC IP on embedded SoCs (such as Atmel/Microchip, Xilinx Zynq, SiFive) or proprietary PCI test cards, which are not present in standard virtualized fuzzing environments (e.g. QEMU standard virt / GCE).", "WorthFuzzing": false }
29/1	2026/08/30 16:43	action	If	0m Args: { "WorthFuzzing": false } Results: null

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch fixes the initialization order of `bp-\u003etsu_clk_lock` before registering the PTP clock in `gem_ptp_init()` for the Cadence MACB/GEM network driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver is for hardware-specific Cadence Ethernet MAC IP on embedded SoCs (such as Atmel/Microchip, Xilinx Zynq, SiFive) or proprietary PCI test cards, which are not present in standard virtualized fuzzing environments (e.g. QEMU standard virt / GCE).",
  "WorthFuzzing": false
}

{
  "PatchDiff": "commit eac1e1eb2e728e0810ab22d9c8b1fdf7714eb0b0\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Sun Aug 30 16:33:08 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c\nindex e5195d7dac1d5..055160c42db3c 100644\n--- a/drivers/net/ethernet/cadence/macb_ptp.c\n+++ b/drivers/net/ethernet/cadence/macb_ptp.c\n@@ -330,6 +330,8 @@ void gem_ptp_init(struct net_device *netdev)\n \n \tbp-\u003eptp_clock_info = gem_ptp_caps_template;\n \n+\tspin_lock_init(\u0026bp-\u003etsu_clk_lock);\n+\n \t/* nominal frequency and maximum adjustment in ppb */\n \tbp-\u003etsu_rate = bp-\u003eptp_info-\u003eget_tsu_rate(bp);\n \tbp-\u003eptp_clock_info.max_adj = bp-\u003eptp_info-\u003eget_ptp_max_adj();\n@@ -345,8 +347,6 @@ void gem_ptp_init(struct net_device *netdev)\n \t\treturn;\n \t}\n \n-\tspin_lock_init(\u0026bp-\u003etsu_clk_lock);\n-\n \tgem_ptp_init_tsu(bp);\n \n \tdev_info(\u0026bp-\u003epdev-\u003edev, \"%s ptp clock registered.\\n\",\n@@ -467,4 +467,3 @@ int gem_set_hwtst(struct net_device *netdev,\n \n \treturn 0;\n }\n-\n"
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch fixes the initialization order of `bp-\u003etsu_clk_lock` before registering the PTP clock in `gem_ptp_init()` for the Cadence MACB/GEM network driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver is for hardware-specific Cadence Ethernet MAC IP on embedded SoCs (such as Atmel/Microchip, Xilinx Zynq, SiFive) or proprietary PCI test cards, which are not present in standard virtualized fuzzing environments (e.g. QEMU standard virt / GCE).",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer.
Your job is to review a provided patch series and determine
if it makes functional changes to the kernel that should be fuzzed.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on your internal knowledge of the kernel. You must actively
use your code access tools to examine the actual source code and confirm any assumptions.

Return WorthFuzzing=false if the patch only contains:
- Modifications to Documentation/, Kconfig files, or code comments.
- Purely decorative changes, such as logging (e.g., pr_err, printk) or tracepoints.
- Changes to numeric constants or macros that do not functionally alter execution flow.
- Code paths that are impossible to reach in virtualized environments like GCE or QEMU,
  even when utilizing software-emulated hardware (e.g., usb gadget, mac80211_hwsim).
- Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers (e.g., mlxsw, pds_core, qed,
  ionic, amdgpu) that require physical PCIe hardware cards not emulated in standard QEMU.
- Driver .remove, .shutdown, or pci_unregister_driver teardown callbacks (e.g., igb_remove)
  that are executed only during PCI hot-unplug or sysfs driver unbind operations.

If it modifies reachable core kernel logic, drivers, or architectures, use your code search
tools to verify the code can be executed, then return WorthFuzzing=true.

When returning WorthFuzzing=true, you MUST ALSO:
1. Extract any specific kernel functions that should be heavily fuzzed into FocusSymbols.
   Avoid listing generic hot-path functions to prevent skewed test distributions.
   Prefer non-static, non-inlined API entrypoint functions over internal static helper functions
   (which are inlined by the compiler and do not have distinct symbol addresses).
2. Identify any specific CONFIG_ options required to properly test this new/modified feature.
   Go and look into the Kconfig files and check for ifdefs around the code, do not make assumptions.
   Also check "depends on" lines in Kconfig to include any non-standard parent subsystem configs
   needed for Kbuild to compile the code statically into vmlinux. List them in the EnableConfigs
   output array, and DO NOT add a 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

For your convenience, here is the diff of the changes:
commit eac1e1eb2e728e0810ab22d9c8b1fdf7714eb0b0
Author: syz-cluster <triage@syzkaller.com>
Date:   Sun Aug 30 16:33:08 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c
index e5195d7dac1d5..055160c42db3c 100644
--- a/drivers/net/ethernet/cadence/macb_ptp.c
+++ b/drivers/net/ethernet/cadence/macb_ptp.c
@@ -330,6 +330,8 @@ void gem_ptp_init(struct net_device *netdev)
 
 	bp->ptp_clock_info = gem_ptp_caps_template;
 
+	spin_lock_init(&bp->tsu_clk_lock);
+
 	/* nominal frequency and maximum adjustment in ppb */
 	bp->tsu_rate = bp->ptp_info->get_tsu_rate(bp);
 	bp->ptp_clock_info.max_adj = bp->ptp_info->get_ptp_max_adj();
@@ -345,8 +347,6 @@ void gem_ptp_init(struct net_device *netdev)
 		return;
 	}
 
-	spin_lock_init(&bp->tsu_clk_lock);
-
 	gem_ptp_init_tsu(bp);
 
 	dev_info(&bp->pdev->dev, "%s ptp clock registered.\n",
@@ -467,4 +467,3 @@ int gem_set_hwtst(struct net_device *netdev,
 
 	return 0;
 }
-

							input: 2278
							output: 31
							thoughts: 86

Here's my thought process, as I analyze this patch:

**Initial Assessment: Fuzzing Feasibility**

Okay, first things first, let's figure out if this patch is even worth our time. Is it something that's ripe for fuzzing? What's the scope of the changes? The goal here is to determine quickly if it's something reachable through my standard fuzzing setups, or if it touches something that will require more complex setup, like hardware emulation or platform-specific configurations I haven't dealt with before. I need to understand the attack surface.

**Diving into the Code**

Now, let's get specific. The prompt mentions `drivers/net/ethernet/cadence/macb_ptp.c`. That's a good starting point. I'll need to dig into that file and any related Kconfig and source files to get a full picture. I need to understand the network interface and if there's an obvious entrypoint for exploitation. I'll be looking for potential vulnerabilities, interesting data flows, and maybe some opportunities for code injection or buffer overflows, which are the usual suspects in this area. From there, I'll need to trace inputs, and determine if any of it is user-controlled, and if it's accessible.

{
  "Expression": "MACB",
  "PathPrefix": "drivers/net/ethernet/cadence"
}

{
  "Output": "\nFull output is too long, showing 500 out of 1713 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/cadence/Kconfig=20=if NET_VENDOR_CADENCE\ndrivers/net/ethernet/cadence/Kconfig-21-\ndrivers/net/ethernet/cadence/Kconfig:22:config MACB\ndrivers/net/ethernet/cadence/Kconfig:23:\ttristate \"Cadence MACB/GEM support\"\ndrivers/net/ethernet/cadence/Kconfig-24-\tdepends on HAS_DMA \u0026\u0026 COMMON_CLK\n--\ndrivers/net/ethernet/cadence/Kconfig-28-\thelp\ndrivers/net/ethernet/cadence/Kconfig:29:\t  The Cadence MACB ethernet interface is found on many Atmel AT32 and\ndrivers/net/ethernet/cadence/Kconfig-30-\t  AT91 parts.  This driver also supports the Cadence GEM (Gigabit\ndrivers/net/ethernet/cadence/Kconfig-31-\t  Ethernet MAC found in some ARM SoC devices).  Say Y to include\ndrivers/net/ethernet/cadence/Kconfig:32:\t  support for the MACB/GEM chip.\ndrivers/net/ethernet/cadence/Kconfig-33-\n--\ndrivers/net/ethernet/cadence/Kconfig-36-\ndrivers/net/ethernet/cadence/Kconfig:37:config MACB_USE_HWSTAMP\ndrivers/net/ethernet/cadence/Kconfig-38-\tbool \"Use IEEE 1588 hwstamp\"\ndrivers/net/ethernet/cadence/Kconfig:39:\tdepends on MACB\ndrivers/net/ethernet/cadence/Kconfig-40-\tdepends on PTP_1588_CLOCK\n--\ndrivers/net/ethernet/cadence/Kconfig-42-\thelp\ndrivers/net/ethernet/cadence/Kconfig:43:\t  Enable IEEE 1588 Precision Time Protocol (PTP) support for MACB.\ndrivers/net/ethernet/cadence/Kconfig-44-\ndrivers/net/ethernet/cadence/Kconfig:45:config MACB_PCI\ndrivers/net/ethernet/cadence/Kconfig:46:\ttristate \"Cadence PCI MACB/GEM support\"\ndrivers/net/ethernet/cadence/Kconfig:47:\tdepends on MACB \u0026\u0026 PCI\ndrivers/net/ethernet/cadence/Kconfig-48-\thelp\ndrivers/net/ethernet/cadence/Kconfig:49:\t  This is PCI wrapper for MACB driver.\ndrivers/net/ethernet/cadence/Kconfig-50-\n--\ndrivers/net/ethernet/cadence/Makefile=5=macb-y\t:= macb_main.o\ndrivers/net/ethernet/cadence/Makefile-6-\ndrivers/net/ethernet/cadence/Makefile:7:ifeq ($(CONFIG_MACB_USE_HWSTAMP),y)\ndrivers/net/ethernet/cadence/Makefile-8-macb-y\t+= macb_ptp.o\ndrivers/net/ethernet/cadence/Makefile=9=endif\ndrivers/net/ethernet/cadence/Makefile-10-\ndrivers/net/ethernet/cadence/Makefile:11:obj-$(CONFIG_MACB) += macb.o\ndrivers/net/ethernet/cadence/Makefile:12:obj-$(CONFIG_MACB_PCI) += macb_pci.o\n--\ndrivers/net/ethernet/cadence/macb.h-2-/*\ndrivers/net/ethernet/cadence/macb.h:3: * Atmel MACB Ethernet Controller driver\ndrivers/net/ethernet/cadence/macb.h-4- *\n--\ndrivers/net/ethernet/cadence/macb.h-6- */\ndrivers/net/ethernet/cadence/macb.h:7:#ifndef _MACB_H\ndrivers/net/ethernet/cadence/macb.h:8:#define _MACB_H\ndrivers/net/ethernet/cadence/macb.h-9-\n--\ndrivers/net/ethernet/cadence/macb.h-17-\ndrivers/net/ethernet/cadence/macb.h:18:#define MACB_GREGS_NBR 16\ndrivers/net/ethernet/cadence/macb.h:19:#define MACB_GREGS_VERSION 2\ndrivers/net/ethernet/cadence/macb.h:20:#define MACB_MAX_QUEUES 8\ndrivers/net/ethernet/cadence/macb.h-21-\ndrivers/net/ethernet/cadence/macb.h:22:/* MACB register offsets */\ndrivers/net/ethernet/cadence/macb.h:23:#define MACB_NCR\t\t0x0000 /* Network Control */\ndrivers/net/ethernet/cadence/macb.h:24:#define MACB_NCFGR\t\t0x0004 /* Network Config */\ndrivers/net/ethernet/cadence/macb.h:25:#define MACB_NSR\t\t0x0008 /* Network Status */\ndrivers/net/ethernet/cadence/macb.h:26:#define MACB_TAR\t\t0x000c /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:27:#define MACB_TCR\t\t0x0010 /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:28:#define MACB_TSR\t\t0x0014 /* Transmit Status */\ndrivers/net/ethernet/cadence/macb.h:29:#define MACB_RBQP\t\t0x0018 /* RX Q Base Address */\ndrivers/net/ethernet/cadence/macb.h:30:#define MACB_TBQP\t\t0x001c /* TX Q Base Address */\ndrivers/net/ethernet/cadence/macb.h:31:#define MACB_RSR\t\t0x0020 /* Receive Status */\ndrivers/net/ethernet/cadence/macb.h:32:#define MACB_ISR\t\t0x0024 /* Interrupt Status */\ndrivers/net/ethernet/cadence/macb.h:33:#define MACB_IER\t\t0x0028 /* Interrupt Enable */\ndrivers/net/ethernet/cadence/macb.h:34:#define MACB_IDR\t\t0x002c /* Interrupt Disable */\ndrivers/net/ethernet/cadence/macb.h:35:#define MACB_IMR\t\t0x0030 /* Interrupt Mask */\ndrivers/net/ethernet/cadence/macb.h:36:#define MACB_MAN\t\t0x0034 /* PHY Maintenance */\ndrivers/net/ethernet/cadence/macb.h:37:#define MACB_PTR\t\t0x0038\ndrivers/net/ethernet/cadence/macb.h:38:#define MACB_PFR\t\t0x003c\ndrivers/net/ethernet/cadence/macb.h:39:#define MACB_FTO\t\t0x0040\ndrivers/net/ethernet/cadence/macb.h:40:#define MACB_SCF\t\t0x0044\ndrivers/net/ethernet/cadence/macb.h:41:#define MACB_MCF\t\t0x0048\ndrivers/net/ethernet/cadence/macb.h:42:#define MACB_FRO\t\t0x004c\ndrivers/net/ethernet/cadence/macb.h:43:#define MACB_FCSE\t\t0x0050\ndrivers/net/ethernet/cadence/macb.h:44:#define MACB_ALE\t\t0x0054\ndrivers/net/ethernet/cadence/macb.h:45:#define MACB_DTF\t\t0x0058\ndrivers/net/ethernet/cadence/macb.h:46:#define MACB_LCOL\t\t0x005c\ndrivers/net/ethernet/cadence/macb.h:47:#define MACB_EXCOL\t\t0x0060\ndrivers/net/ethernet/cadence/macb.h:48:#define MACB_TUND\t\t0x0064\ndrivers/net/ethernet/cadence/macb.h:49:#define MACB_CSE\t\t0x0068\ndrivers/net/ethernet/cadence/macb.h:50:#define MACB_RRE\t\t0x006c\ndrivers/net/ethernet/cadence/macb.h:51:#define MACB_ROVR\t\t0x0070\ndrivers/net/ethernet/cadence/macb.h:52:#define MACB_RSE\t\t0x0074\ndrivers/net/ethernet/cadence/macb.h:53:#define MACB_ELE\t\t0x0078\ndrivers/net/ethernet/cadence/macb.h:54:#define MACB_RJA\t\t0x007c\ndrivers/net/ethernet/cadence/macb.h:55:#define MACB_USF\t\t0x0080\ndrivers/net/ethernet/cadence/macb.h:56:#define MACB_STE\t\t0x0084\ndrivers/net/ethernet/cadence/macb.h:57:#define MACB_RLE\t\t0x0088\ndrivers/net/ethernet/cadence/macb.h:58:#define MACB_TPF\t\t0x008c\ndrivers/net/ethernet/cadence/macb.h:59:#define MACB_HRB\t\t0x0090\ndrivers/net/ethernet/cadence/macb.h:60:#define MACB_HRT\t\t0x0094\ndrivers/net/ethernet/cadence/macb.h:61:#define MACB_SA1B\t\t0x0098\ndrivers/net/ethernet/cadence/macb.h:62:#define MACB_SA1T\t\t0x009c\ndrivers/net/ethernet/cadence/macb.h:63:#define MACB_SA2B\t\t0x00a0\ndrivers/net/ethernet/cadence/macb.h:64:#define MACB_SA2T\t\t0x00a4\ndrivers/net/ethernet/cadence/macb.h:65:#define MACB_SA3B\t\t0x00a8\ndrivers/net/ethernet/cadence/macb.h:66:#define MACB_SA3T\t\t0x00ac\ndrivers/net/ethernet/cadence/macb.h:67:#define MACB_SA4B\t\t0x00b0\ndrivers/net/ethernet/cadence/macb.h:68:#define MACB_SA4T\t\t0x00b4\ndrivers/net/ethernet/cadence/macb.h:69:#define MACB_TID\t\t0x00b8\ndrivers/net/ethernet/cadence/macb.h:70:#define MACB_TPQ\t\t0x00bc\ndrivers/net/ethernet/cadence/macb.h:71:#define MACB_USRIO\t\t0x00c0\ndrivers/net/ethernet/cadence/macb.h:72:#define MACB_WOL\t\t0x00c4\ndrivers/net/ethernet/cadence/macb.h:73:#define MACB_MID\t\t0x00fc\ndrivers/net/ethernet/cadence/macb.h:74:#define MACB_TBQPH\t\t0x04C8\ndrivers/net/ethernet/cadence/macb.h:75:#define MACB_RBQPH\t\t0x04D4\ndrivers/net/ethernet/cadence/macb.h-76-\n--\ndrivers/net/ethernet/cadence/macb.h-230-/* Bitfields in NCR */\ndrivers/net/ethernet/cadence/macb.h:231:#define MACB_LB_OFFSET\t\t0 /* reserved */\ndrivers/net/ethernet/cadence/macb.h:232:#define MACB_LB_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:233:#define MACB_LLB_OFFSET\t\t1 /* Loop back local */\ndrivers/net/ethernet/cadence/macb.h:234:#define MACB_LLB_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:235:#define MACB_RE_OFFSET\t\t2 /* Receive enable */\ndrivers/net/ethernet/cadence/macb.h:236:#define MACB_RE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:237:#define MACB_TE_OFFSET\t\t3 /* Transmit enable */\ndrivers/net/ethernet/cadence/macb.h:238:#define MACB_TE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:239:#define MACB_MPE_OFFSET\t\t4 /* Management port enable */\ndrivers/net/ethernet/cadence/macb.h:240:#define MACB_MPE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:241:#define MACB_CLRSTAT_OFFSET\t5 /* Clear stats regs */\ndrivers/net/ethernet/cadence/macb.h:242:#define MACB_CLRSTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:243:#define MACB_INCSTAT_OFFSET\t6 /* Incremental stats regs */\ndrivers/net/ethernet/cadence/macb.h:244:#define MACB_INCSTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:245:#define MACB_WESTAT_OFFSET\t7 /* Write enable stats regs */\ndrivers/net/ethernet/cadence/macb.h:246:#define MACB_WESTAT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:247:#define MACB_BP_OFFSET\t\t8 /* Back pressure */\ndrivers/net/ethernet/cadence/macb.h:248:#define MACB_BP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:249:#define MACB_TSTART_OFFSET\t9 /* Start transmission */\ndrivers/net/ethernet/cadence/macb.h:250:#define MACB_TSTART_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:251:#define MACB_THALT_OFFSET\t10 /* Transmit halt */\ndrivers/net/ethernet/cadence/macb.h:252:#define MACB_THALT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:253:#define MACB_NCR_TPF_OFFSET\t11 /* Transmit pause frame */\ndrivers/net/ethernet/cadence/macb.h:254:#define MACB_NCR_TPF_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:255:#define MACB_TZQ_OFFSET\t\t12 /* Transmit zero quantum pause frame */\ndrivers/net/ethernet/cadence/macb.h:256:#define MACB_TZQ_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:257:#define MACB_SRTSM_OFFSET\t15 /* Store Receive Timestamp to Memory */\ndrivers/net/ethernet/cadence/macb.h:258:#define MACB_PTPUNI_OFFSET\t20 /* PTP Unicast packet enable */\ndrivers/net/ethernet/cadence/macb.h:259:#define MACB_PTPUNI_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:260:#define MACB_OSSMODE_OFFSET\t24 /* Enable One Step Synchro Mode */\ndrivers/net/ethernet/cadence/macb.h:261:#define MACB_OSSMODE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:262:#define MACB_MIIONRGMII_OFFSET\t28 /* MII Usage on RGMII Interface */\ndrivers/net/ethernet/cadence/macb.h:263:#define MACB_MIIONRGMII_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h-264-\ndrivers/net/ethernet/cadence/macb.h-265-/* Bitfields in NCFGR */\ndrivers/net/ethernet/cadence/macb.h:266:#define MACB_SPD_OFFSET\t\t0 /* Speed */\ndrivers/net/ethernet/cadence/macb.h:267:#define MACB_SPD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:268:#define MACB_FD_OFFSET\t\t1 /* Full duplex */\ndrivers/net/ethernet/cadence/macb.h:269:#define MACB_FD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:270:#define MACB_BIT_RATE_OFFSET\t2 /* Discard non-VLAN frames */\ndrivers/net/ethernet/cadence/macb.h:271:#define MACB_BIT_RATE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:272:#define MACB_JFRAME_OFFSET\t3 /* reserved */\ndrivers/net/ethernet/cadence/macb.h:273:#define MACB_JFRAME_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:274:#define MACB_CAF_OFFSET\t\t4 /* Copy all frames */\ndrivers/net/ethernet/cadence/macb.h:275:#define MACB_CAF_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:276:#define MACB_NBC_OFFSET\t\t5 /* No broadcast */\ndrivers/net/ethernet/cadence/macb.h:277:#define MACB_NBC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:278:#define MACB_NCFGR_MTI_OFFSET\t6 /* Multicast hash enable */\ndrivers/net/ethernet/cadence/macb.h:279:#define MACB_NCFGR_MTI_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:280:#define MACB_UNI_OFFSET\t\t7 /* Unicast hash enable */\ndrivers/net/ethernet/cadence/macb.h:281:#define MACB_UNI_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:282:#define MACB_BIG_OFFSET\t\t8 /* Receive 1536 byte frames */\ndrivers/net/ethernet/cadence/macb.h:283:#define MACB_BIG_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:284:#define MACB_EAE_OFFSET\t\t9 /* External address match enable */\ndrivers/net/ethernet/cadence/macb.h:285:#define MACB_EAE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:286:#define MACB_CLK_OFFSET\t\t10\ndrivers/net/ethernet/cadence/macb.h:287:#define MACB_CLK_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:288:#define MACB_RTY_OFFSET\t\t12 /* Retry test */\ndrivers/net/ethernet/cadence/macb.h:289:#define MACB_RTY_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:290:#define MACB_PAE_OFFSET\t\t13 /* Pause enable */\ndrivers/net/ethernet/cadence/macb.h:291:#define MACB_PAE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:292:#define MACB_RM9200_RMII_OFFSET\t13 /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:293:#define MACB_RM9200_RMII_SIZE\t1  /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:294:#define MACB_RBOF_OFFSET\t14 /* Receive buffer offset */\ndrivers/net/ethernet/cadence/macb.h:295:#define MACB_RBOF_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:296:#define MACB_RLCE_OFFSET\t16 /* Length field error frame discard */\ndrivers/net/ethernet/cadence/macb.h:297:#define MACB_RLCE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:298:#define MACB_DRFCS_OFFSET\t17 /* FCS remove */\ndrivers/net/ethernet/cadence/macb.h:299:#define MACB_DRFCS_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:300:#define MACB_EFRHD_OFFSET\t18\ndrivers/net/ethernet/cadence/macb.h:301:#define MACB_EFRHD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:302:#define MACB_IRXFCS_OFFSET\t19\ndrivers/net/ethernet/cadence/macb.h:303:#define MACB_IRXFCS_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h-304-\n--\ndrivers/net/ethernet/cadence/macb.h-364-/* Bitfields in NSR */\ndrivers/net/ethernet/cadence/macb.h:365:#define MACB_NSR_LINK_OFFSET\t0 /* pcs_link_state */\ndrivers/net/ethernet/cadence/macb.h:366:#define MACB_NSR_LINK_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:367:#define MACB_MDIO_OFFSET\t1 /* status of the mdio_in pin */\ndrivers/net/ethernet/cadence/macb.h:368:#define MACB_MDIO_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:369:#define MACB_IDLE_OFFSET\t2 /* The PHY management logic is idle */\ndrivers/net/ethernet/cadence/macb.h:370:#define MACB_IDLE_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-371-\ndrivers/net/ethernet/cadence/macb.h-372-/* Bitfields in TSR */\ndrivers/net/ethernet/cadence/macb.h:373:#define MACB_UBR_OFFSET\t\t0 /* Used bit read */\ndrivers/net/ethernet/cadence/macb.h:374:#define MACB_UBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:375:#define MACB_COL_OFFSET\t\t1 /* Collision occurred */\ndrivers/net/ethernet/cadence/macb.h:376:#define MACB_COL_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:377:#define MACB_TSR_RLE_OFFSET\t2 /* Retry limit exceeded */\ndrivers/net/ethernet/cadence/macb.h:378:#define MACB_TSR_RLE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:379:#define MACB_TGO_OFFSET\t\t3 /* Transmit go */\ndrivers/net/ethernet/cadence/macb.h:380:#define MACB_TGO_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:381:#define MACB_BEX_OFFSET\t\t4 /* TX frame corruption due to AHB error */\ndrivers/net/ethernet/cadence/macb.h:382:#define MACB_BEX_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:383:#define MACB_RM9200_BNQ_OFFSET\t4 /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:384:#define MACB_RM9200_BNQ_SIZE\t1 /* AT91RM9200 only */\ndrivers/net/ethernet/cadence/macb.h:385:#define MACB_COMP_OFFSET\t5 /* Trnasmit complete */\ndrivers/net/ethernet/cadence/macb.h:386:#define MACB_COMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:387:#define MACB_UND_OFFSET\t\t6 /* Trnasmit under run */\ndrivers/net/ethernet/cadence/macb.h:388:#define MACB_UND_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-389-\ndrivers/net/ethernet/cadence/macb.h-390-/* Bitfields in RSR */\ndrivers/net/ethernet/cadence/macb.h:391:#define MACB_BNA_OFFSET\t\t0 /* Buffer not available */\ndrivers/net/ethernet/cadence/macb.h:392:#define MACB_BNA_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:393:#define MACB_REC_OFFSET\t\t1 /* Frame received */\ndrivers/net/ethernet/cadence/macb.h:394:#define MACB_REC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:395:#define MACB_OVR_OFFSET\t\t2 /* Receive overrun */\ndrivers/net/ethernet/cadence/macb.h:396:#define MACB_OVR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-397-\ndrivers/net/ethernet/cadence/macb.h-398-/* Bitfields in ISR/IER/IDR/IMR */\ndrivers/net/ethernet/cadence/macb.h:399:#define MACB_MFD_OFFSET\t\t0 /* Management frame sent */\ndrivers/net/ethernet/cadence/macb.h:400:#define MACB_MFD_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:401:#define MACB_RCOMP_OFFSET\t1 /* Receive complete */\ndrivers/net/ethernet/cadence/macb.h:402:#define MACB_RCOMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:403:#define MACB_RXUBR_OFFSET\t2 /* RX used bit read */\ndrivers/net/ethernet/cadence/macb.h:404:#define MACB_RXUBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:405:#define MACB_TXUBR_OFFSET\t3 /* TX used bit read */\ndrivers/net/ethernet/cadence/macb.h:406:#define MACB_TXUBR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:407:#define MACB_ISR_TUND_OFFSET\t4 /* Enable TX buffer under run interrupt */\ndrivers/net/ethernet/cadence/macb.h:408:#define MACB_ISR_TUND_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:409:#define MACB_ISR_RLE_OFFSET\t5 /* EN retry exceeded/late coll interrupt */\ndrivers/net/ethernet/cadence/macb.h:410:#define MACB_ISR_RLE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:411:#define MACB_TXERR_OFFSET\t6 /* EN TX frame corrupt from error interrupt */\ndrivers/net/ethernet/cadence/macb.h:412:#define MACB_TXERR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:413:#define MACB_RM9200_TBRE_OFFSET\t6 /* EN may send new frame interrupt (RM9200) */\ndrivers/net/ethernet/cadence/macb.h:414:#define MACB_RM9200_TBRE_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:415:#define MACB_TCOMP_OFFSET\t7 /* Enable transmit complete interrupt */\ndrivers/net/ethernet/cadence/macb.h:416:#define MACB_TCOMP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:417:#define MACB_ISR_LINK_OFFSET\t9 /* Enable link change interrupt */\ndrivers/net/ethernet/cadence/macb.h:418:#define MACB_ISR_LINK_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:419:#define MACB_ISR_ROVR_OFFSET\t10 /* Enable receive overrun interrupt */\ndrivers/net/ethernet/cadence/macb.h:420:#define MACB_ISR_ROVR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:421:#define MACB_HRESP_OFFSET\t11 /* Enable hrsep not OK interrupt */\ndrivers/net/ethernet/cadence/macb.h:422:#define MACB_HRESP_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:423:#define MACB_PFR_OFFSET\t\t12 /* Enable pause frame w/ quantum interrupt */\ndrivers/net/ethernet/cadence/macb.h:424:#define MACB_PFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:425:#define MACB_PTZ_OFFSET\t\t13 /* Enable pause time zero interrupt */\ndrivers/net/ethernet/cadence/macb.h:426:#define MACB_PTZ_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:427:#define MACB_WOL_OFFSET\t\t14 /* Enable wake-on-lan interrupt */\ndrivers/net/ethernet/cadence/macb.h:428:#define MACB_WOL_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:429:#define MACB_DRQFR_OFFSET\t18 /* PTP Delay Request Frame Received */\ndrivers/net/ethernet/cadence/macb.h:430:#define MACB_DRQFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:431:#define MACB_SFR_OFFSET\t\t19 /* PTP Sync Frame Received */\ndrivers/net/ethernet/cadence/macb.h:432:#define MACB_SFR_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:433:#define MACB_DRQFT_OFFSET\t20 /* PTP Delay Request Frame Transmitted */\ndrivers/net/ethernet/cadence/macb.h:434:#define MACB_DRQFT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:435:#define MACB_SFT_OFFSET\t\t21 /* PTP Sync Frame Transmitted */\ndrivers/net/ethernet/cadence/macb.h:436:#define MACB_SFT_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:437:#define MACB_PDRQFR_OFFSET\t22 /* PDelay Request Frame Received */\ndrivers/net/ethernet/cadence/macb.h:438:#define MACB_PDRQFR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:439:#define MACB_PDRSFR_OFFSET\t23 /* PDelay Response Frame Received */\ndrivers/net/ethernet/cadence/macb.h:440:#define MACB_PDRSFR_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:441:#define MACB_PDRQFT_OFFSET\t24 /* PDelay Request Frame Transmitted */\ndrivers/net/ethernet/cadence/macb.h:442:#define MACB_PDRQFT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:443:#define MACB_PDRSFT_OFFSET\t25 /* PDelay Response Frame Transmitted */\ndrivers/net/ethernet/cadence/macb.h:444:#define MACB_PDRSFT_SIZE\t1\ndrivers/net/ethernet/cadence/macb.h:445:#define MACB_SRI_OFFSET\t\t26 /* TSU Seconds Register Increment */\ndrivers/net/ethernet/cadence/macb.h:446:#define MACB_SRI_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h-447-#define GEM_WOL_OFFSET\t\t28 /* Enable wake-on-lan interrupt */\n--\ndrivers/net/ethernet/cadence/macb.h-450-/* Timer increment fields */\ndrivers/net/ethernet/cadence/macb.h:451:#define MACB_TI_CNS_OFFSET\t0\ndrivers/net/ethernet/cadence/macb.h:452:#define MACB_TI_CNS_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h:453:#define MACB_TI_ACNS_OFFSET\t8\ndrivers/net/ethernet/cadence/macb.h:454:#define MACB_TI_ACNS_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h:455:#define MACB_TI_NIT_OFFSET\t16\ndrivers/net/ethernet/cadence/macb.h:456:#define MACB_TI_NIT_SIZE\t8\ndrivers/net/ethernet/cadence/macb.h-457-\ndrivers/net/ethernet/cadence/macb.h-458-/* Bitfields in MAN */\ndrivers/net/ethernet/cadence/macb.h:459:#define MACB_DATA_OFFSET\t0 /* data */\ndrivers/net/ethernet/cadence/macb.h:460:#define MACB_DATA_SIZE\t\t16\ndrivers/net/ethernet/cadence/macb.h:461:#define MACB_CODE_OFFSET\t16 /* Must be written to 10 */\ndrivers/net/ethernet/cadence/macb.h:462:#define MACB_CODE_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:463:#define MACB_REGA_OFFSET\t18 /* Register address */\ndrivers/net/ethernet/cadence/macb.h:464:#define MACB_REGA_SIZE\t\t5\ndrivers/net/ethernet/cadence/macb.h:465:#define MACB_PHYA_OFFSET\t23 /* PHY address */\ndrivers/net/ethernet/cadence/macb.h:466:#define MACB_PHYA_SIZE\t\t5\ndrivers/net/ethernet/cadence/macb.h:467:#define MACB_RW_OFFSET\t\t28 /* Operation. 10 is read. 01 is write. */\ndrivers/net/ethernet/cadence/macb.h:468:#define MACB_RW_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h:469:#define MACB_SOF_OFFSET\t\t30 /* Must be written to 1 for Clause 22 */\ndrivers/net/ethernet/cadence/macb.h:470:#define MACB_SOF_SIZE\t\t2\ndrivers/net/ethernet/cadence/macb.h-471-\ndrivers/net/ethernet/cadence/macb.h-472-/* Bitfields in USRIO (AVR32) */\ndrivers/net/ethernet/cadence/macb.h:473:#define MACB_MII_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:474:#define MACB_MII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:475:#define MACB_EAM_OFFSET\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:476:#define MACB_EAM_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:477:#define MACB_TX_PAUSE_OFFSET\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:478:#define MACB_TX_PAUSE_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:479:#define MACB_TX_PAUSE_ZERO_OFFSET\t\t3\ndrivers/net/ethernet/cadence/macb.h:480:#define MACB_TX_PAUSE_ZERO_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-481-\ndrivers/net/ethernet/cadence/macb.h-482-/* Bitfields in USRIO (AT91) */\ndrivers/net/ethernet/cadence/macb.h:483:#define MACB_RMII_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:484:#define MACB_RMII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-485-#define GEM_RGMII_OFFSET\t\t\t0 /* GEM gigabit mode */\ndrivers/net/ethernet/cadence/macb.h-486-#define GEM_RGMII_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:487:#define MACB_CLKEN_OFFSET\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:488:#define MACB_CLKEN_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-489-\ndrivers/net/ethernet/cadence/macb.h-490-/* Bitfields in WOL */\ndrivers/net/ethernet/cadence/macb.h:491:#define MACB_IP_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:492:#define MACB_IP_SIZE\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:493:#define MACB_MAG_OFFSET\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:494:#define MACB_MAG_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:495:#define MACB_ARP_OFFSET\t\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:496:#define MACB_ARP_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:497:#define MACB_SA1_OFFSET\t\t\t\t18\ndrivers/net/ethernet/cadence/macb.h:498:#define MACB_SA1_SIZE\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:499:#define MACB_WOL_MTI_OFFSET\t\t\t19\ndrivers/net/ethernet/cadence/macb.h:500:#define MACB_WOL_MTI_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-501-\ndrivers/net/ethernet/cadence/macb.h-502-/* Bitfields in MID */\ndrivers/net/ethernet/cadence/macb.h:503:#define MACB_IDNUM_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:504:#define MACB_IDNUM_SIZE\t\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:505:#define MACB_REV_OFFSET\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:506:#define MACB_REV_SIZE\t\t\t\t16\ndrivers/net/ethernet/cadence/macb.h-507-\n--\ndrivers/net/ethernet/cadence/macb.h-678-/* Bitfields in queue pointer registers */\ndrivers/net/ethernet/cadence/macb.h:679:#define MACB_QUEUE_DISABLE_OFFSET\t\t0 /* disable queue */\ndrivers/net/ethernet/cadence/macb.h:680:#define MACB_QUEUE_DISABLE_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-681-\n--\ndrivers/net/ethernet/cadence/macb.h-729-/* Constants for CLK */\ndrivers/net/ethernet/cadence/macb.h:730:#define MACB_CLK_DIV8\t\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:731:#define MACB_CLK_DIV16\t\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:732:#define MACB_CLK_DIV32\t\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:733:#define MACB_CLK_DIV64\t\t\t\t3\ndrivers/net/ethernet/cadence/macb.h-734-\n--\ndrivers/net/ethernet/cadence/macb.h-745-/* Constants for MAN register */\ndrivers/net/ethernet/cadence/macb.h:746:#define MACB_MAN_C22_SOF\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:747:#define MACB_MAN_C22_WRITE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:748:#define MACB_MAN_C22_READ\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:749:#define MACB_MAN_C22_CODE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h-750-\ndrivers/net/ethernet/cadence/macb.h:751:#define MACB_MAN_C45_SOF\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:752:#define MACB_MAN_C45_ADDR\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:753:#define MACB_MAN_C45_WRITE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:754:#define MACB_MAN_C45_POST_READ_INCR\t\t2\ndrivers/net/ethernet/cadence/macb.h:755:#define MACB_MAN_C45_READ\t\t\t3\ndrivers/net/ethernet/cadence/macb.h:756:#define MACB_MAN_C45_CODE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h-757-\ndrivers/net/ethernet/cadence/macb.h-758-/* Capability mask bits */\ndrivers/net/ethernet/cadence/macb.h:759:#define MACB_CAPS_ISR_CLEAR_ON_WRITE\t\tBIT(0)\ndrivers/net/ethernet/cadence/macb.h:760:#define MACB_CAPS_USRIO_HAS_CLKEN\t\tBIT(1)\ndrivers/net/ethernet/cadence/macb.h:761:#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII\tBIT(2)\ndrivers/net/ethernet/cadence/macb.h:762:#define MACB_CAPS_NO_GIGABIT_HALF\t\tBIT(3)\ndrivers/net/ethernet/cadence/macb.h:763:#define MACB_CAPS_USRIO_DISABLED\t\tBIT(4)\ndrivers/net/ethernet/cadence/macb.h:764:#define MACB_CAPS_JUMBO\t\t\t\tBIT(5)\ndrivers/net/ethernet/cadence/macb.h:765:#define MACB_CAPS_GEM_HAS_PTP\t\t\tBIT(6)\ndrivers/net/ethernet/cadence/macb.h:766:#define MACB_CAPS_BD_RD_PREFETCH\t\tBIT(7)\ndrivers/net/ethernet/cadence/macb.h:767:#define MACB_CAPS_NEEDS_RSTONUBR\t\tBIT(8)\ndrivers/net/ethernet/cadence/macb.h:768:#define MACB_CAPS_MIIONRGMII\t\t\tBIT(9)\ndrivers/net/ethernet/cadence/macb.h:769:#define MACB_CAPS_NEED_TSUCLK\t\t\tBIT(10)\ndrivers/net/ethernet/cadence/macb.h:770:#define MACB_CAPS_QUEUE_DISABLE\t\t\tBIT(11)\ndrivers/net/ethernet/cadence/macb.h:771:#define MACB_CAPS_QBV\t\t\t\tBIT(12)\ndrivers/net/ethernet/cadence/macb.h:772:#define MACB_CAPS_PCS\t\t\t\tBIT(13)\ndrivers/net/ethernet/cadence/macb.h:773:#define MACB_CAPS_HIGH_SPEED\t\t\tBIT(14)\ndrivers/net/ethernet/cadence/macb.h:774:#define MACB_CAPS_CLK_HW_CHG\t\t\tBIT(15)\ndrivers/net/ethernet/cadence/macb.h:775:#define MACB_CAPS_MACB_IS_EMAC\t\t\tBIT(16)\ndrivers/net/ethernet/cadence/macb.h:776:#define MACB_CAPS_FIFO_MODE\t\t\tBIT(17)\ndrivers/net/ethernet/cadence/macb.h:777:#define MACB_CAPS_GIGABIT_MODE_AVAILABLE\tBIT(18)\ndrivers/net/ethernet/cadence/macb.h:778:#define MACB_CAPS_SG_DISABLED\t\t\tBIT(19)\ndrivers/net/ethernet/cadence/macb.h:779:#define MACB_CAPS_MACB_IS_GEM\t\t\tBIT(20)\ndrivers/net/ethernet/cadence/macb.h:780:#define MACB_CAPS_DMA_64B\t\t\tBIT(21)\ndrivers/net/ethernet/cadence/macb.h:781:#define MACB_CAPS_DMA_PTP\t\t\tBIT(22)\ndrivers/net/ethernet/cadence/macb.h:782:#define MACB_CAPS_RSC\t\t\t\tBIT(23)\ndrivers/net/ethernet/cadence/macb.h:783:#define MACB_CAPS_NO_LSO\t\t\tBIT(24)\ndrivers/net/ethernet/cadence/macb.h:784:#define MACB_CAPS_EEE\t\t\t\tBIT(25)\ndrivers/net/ethernet/cadence/macb.h:785:#define MACB_CAPS_USRIO_HAS_MII\t\t\tBIT(26)\ndrivers/net/ethernet/cadence/macb.h:786:#define MACB_CAPS_USRIO_HAS_REFCLK_SOURCE\tBIT(27)\ndrivers/net/ethernet/cadence/macb.h:787:#define MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE\tBIT(28)\ndrivers/net/ethernet/cadence/macb.h-788-\ndrivers/net/ethernet/cadence/macb.h-789-/* LSO settings */\ndrivers/net/ethernet/cadence/macb.h:790:#define MACB_LSO_UFO_ENABLE\t\t\t0x01\ndrivers/net/ethernet/cadence/macb.h:791:#define MACB_LSO_TSO_ENABLE\t\t\t0x02\ndrivers/net/ethernet/cadence/macb.h-792-\ndrivers/net/ethernet/cadence/macb.h-793-/* Bit manipulation macros */\ndrivers/net/ethernet/cadence/macb.h:794:#define MACB_BIT(name)\t\t\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:795:\t(1 \u003c\u003c MACB_##name##_OFFSET)\ndrivers/net/ethernet/cadence/macb.h:796:#define MACB_BF(name,value)\t\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:797:\t(((value) \u0026 ((1 \u003c\u003c MACB_##name##_SIZE) - 1))\t\\\ndrivers/net/ethernet/cadence/macb.h:798:\t \u003c\u003c MACB_##name##_OFFSET)\ndrivers/net/ethernet/cadence/macb.h:799:#define MACB_BFEXT(name,value)\\\ndrivers/net/ethernet/cadence/macb.h:800:\t(((value) \u003e\u003e MACB_##name##_OFFSET)\t\t\\\ndrivers/net/ethernet/cadence/macb.h:801:\t \u0026 ((1 \u003c\u003c MACB_##name##_SIZE) - 1))\ndrivers/net/ethernet/cadence/macb.h:802:#define MACB_BFINS(name,value,old)\t\t\t\\\ndrivers/net/ethernet/cadence/macb.h:803:\t(((old) \u0026 ~(((1 \u003c\u003c MACB_##name##_SIZE) - 1)\t\\\ndrivers/net/ethernet/cadence/macb.h:804:\t\t    \u003c\u003c MACB_##name##_OFFSET))\t\t\\\ndrivers/net/ethernet/cadence/macb.h:805:\t | MACB_BF(name,value))\ndrivers/net/ethernet/cadence/macb.h-806-\n--\ndrivers/net/ethernet/cadence/macb.h-820-/* Register access macros */\ndrivers/net/ethernet/cadence/macb.h:821:#define macb_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), MACB_##reg)\ndrivers/net/ethernet/cadence/macb.h:822:#define macb_writel(port, reg, value)\t(port)-\u003emacb_reg_writel((port), MACB_##reg, (value))\ndrivers/net/ethernet/cadence/macb.h-823-#define gem_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), GEM_##reg)\n--\ndrivers/net/ethernet/cadence/macb.h-829-\ndrivers/net/ethernet/cadence/macb.h:830:/* Conditional GEM/MACB macros.  These perform the operation to the correct\ndrivers/net/ethernet/cadence/macb.h:831: * register dependent on whether the device is a GEM or a MACB.  For registers\ndrivers/net/ethernet/cadence/macb.h-832- * and bitfields that are common across both devices, use macb_{read,write}l\n--\ndrivers/net/ethernet/cadence/macb.h-852-\ndrivers/net/ethernet/cadence/macb.h:853:#define MACB_READ_NSR(bp)\tmacb_readl(bp, NSR)\ndrivers/net/ethernet/cadence/macb.h-854-\n--\ndrivers/net/ethernet/cadence/macb.h=869=struct macb_dma_desc_ptp {\n--\ndrivers/net/ethernet/cadence/macb.h-874-/* DMA descriptor bitfields */\ndrivers/net/ethernet/cadence/macb.h:875:#define MACB_RX_USED_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:876:#define MACB_RX_USED_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:877:#define MACB_RX_WRAP_OFFSET\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:878:#define MACB_RX_WRAP_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:879:#define MACB_RX_WADDR_OFFSET\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:880:#define MACB_RX_WADDR_SIZE\t\t\t30\ndrivers/net/ethernet/cadence/macb.h-881-\ndrivers/net/ethernet/cadence/macb.h:882:#define MACB_RX_FRMLEN_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:883:#define MACB_RX_FRMLEN_SIZE\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:884:#define MACB_RX_OFFSET_OFFSET\t\t\t12\ndrivers/net/ethernet/cadence/macb.h:885:#define MACB_RX_OFFSET_SIZE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:886:#define MACB_RX_SOF_OFFSET\t\t\t14\ndrivers/net/ethernet/cadence/macb.h:887:#define MACB_RX_SOF_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:888:#define MACB_RX_EOF_OFFSET\t\t\t15\ndrivers/net/ethernet/cadence/macb.h:889:#define MACB_RX_EOF_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:890:#define MACB_RX_CFI_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:891:#define MACB_RX_CFI_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:892:#define MACB_RX_VLAN_PRI_OFFSET\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:893:#define MACB_RX_VLAN_PRI_SIZE\t\t\t3\ndrivers/net/ethernet/cadence/macb.h:894:#define MACB_RX_PRI_TAG_OFFSET\t\t\t20\ndrivers/net/ethernet/cadence/macb.h:895:#define MACB_RX_PRI_TAG_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:896:#define MACB_RX_VLAN_TAG_OFFSET\t\t\t21\ndrivers/net/ethernet/cadence/macb.h:897:#define MACB_RX_VLAN_TAG_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:898:#define MACB_RX_TYPEID_MATCH_OFFSET\t\t22\ndrivers/net/ethernet/cadence/macb.h:899:#define MACB_RX_TYPEID_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:900:#define MACB_RX_SA4_MATCH_OFFSET\t\t23\ndrivers/net/ethernet/cadence/macb.h:901:#define MACB_RX_SA4_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:902:#define MACB_RX_SA3_MATCH_OFFSET\t\t24\ndrivers/net/ethernet/cadence/macb.h:903:#define MACB_RX_SA3_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:904:#define MACB_RX_SA2_MATCH_OFFSET\t\t25\ndrivers/net/ethernet/cadence/macb.h:905:#define MACB_RX_SA2_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:906:#define MACB_RX_SA1_MATCH_OFFSET\t\t26\ndrivers/net/ethernet/cadence/macb.h:907:#define MACB_RX_SA1_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:908:#define MACB_RX_EXT_MATCH_OFFSET\t\t28\ndrivers/net/ethernet/cadence/macb.h:909:#define MACB_RX_EXT_MATCH_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:910:#define MACB_RX_UHASH_MATCH_OFFSET\t\t29\ndrivers/net/ethernet/cadence/macb.h:911:#define MACB_RX_UHASH_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:912:#define MACB_RX_MHASH_MATCH_OFFSET\t\t30\ndrivers/net/ethernet/cadence/macb.h:913:#define MACB_RX_MHASH_MATCH_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:914:#define MACB_RX_BROADCAST_OFFSET\t\t31\ndrivers/net/ethernet/cadence/macb.h:915:#define MACB_RX_BROADCAST_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-916-\ndrivers/net/ethernet/cadence/macb.h:917:#define MACB_RX_FRMLEN_MASK\t\t\t0xFFF\ndrivers/net/ethernet/cadence/macb.h:918:#define MACB_RX_JFRMLEN_MASK\t\t\t0x3FFF\ndrivers/net/ethernet/cadence/macb.h-919-\n--\ndrivers/net/ethernet/cadence/macb.h-927-\ndrivers/net/ethernet/cadence/macb.h:928:#define MACB_TX_FRMLEN_OFFSET\t\t\t0\ndrivers/net/ethernet/cadence/macb.h:929:#define MACB_TX_FRMLEN_SIZE\t\t\t11\ndrivers/net/ethernet/cadence/macb.h:930:#define MACB_TX_LAST_OFFSET\t\t\t15\ndrivers/net/ethernet/cadence/macb.h:931:#define MACB_TX_LAST_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:932:#define MACB_TX_NOCRC_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:933:#define MACB_TX_NOCRC_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:934:#define MACB_MSS_MFS_OFFSET\t\t\t16\ndrivers/net/ethernet/cadence/macb.h:935:#define MACB_MSS_MFS_SIZE\t\t\t14\ndrivers/net/ethernet/cadence/macb.h:936:#define MACB_TX_LSO_OFFSET\t\t\t17\ndrivers/net/ethernet/cadence/macb.h:937:#define MACB_TX_LSO_SIZE\t\t\t2\ndrivers/net/ethernet/cadence/macb.h:938:#define MACB_TX_TCP_SEQ_SRC_OFFSET\t\t19\ndrivers/net/ethernet/cadence/macb.h:939:#define MACB_TX_TCP_SEQ_SRC_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:940:#define MACB_TX_BUF_EXHAUSTED_OFFSET\t\t27\ndrivers/net/ethernet/cadence/macb.h:941:#define MACB_TX_BUF_EXHAUSTED_SIZE\t\t1\ndrivers/net/ethernet/cadence/macb.h:942:#define MACB_TX_UNDERRUN_OFFSET\t\t\t28\ndrivers/net/ethernet/cadence/macb.h:943:#define MACB_TX_UNDERRUN_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:944:#define MACB_TX_ERROR_OFFSET\t\t\t29\ndrivers/net/ethernet/cadence/macb.h:945:#define MACB_TX_ERROR_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:946:#define MACB_TX_WRAP_OFFSET\t\t\t30\ndrivers/net/ethernet/cadence/macb.h:947:#define MACB_TX_WRAP_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h:948:#define MACB_TX_USED_OFFSET\t\t\t31\ndrivers/net/ethernet/cadence/macb.h:949:#define MACB_TX_USED_SIZE\t\t\t1\ndrivers/net/ethernet/cadence/macb.h-950-\n--\ndrivers/net/ethernet/cadence/macb.h=1194=struct macb_or_gem_ops {\n--\ndrivers/net/ethernet/cadence/macb.h-1201-\ndrivers/net/ethernet/cadence/macb.h:1202:/* MACB-PTP interface: adapt to platform needs. */\ndrivers/net/ethernet/cadence/macb.h-1203-struct macb_ptp_info {\n--\ndrivers/net/ethernet/cadence/macb.h=1298=struct macb {\n--\ndrivers/net/ethernet/cadence/macb.h-1313-\tunsigned int\t\tnum_queues;\n\n"
}

							input: 18000
							output: 44
							thoughts: 155

**My Line of Inquiry**

Okay, so I'm diving into this `macb` situation. First things first, let's take a look at `macb_pci.c` and understand the probing process for these devices. I'm wondering, is the MACB actually emulated within QEMU? And that leads to a bigger question: Does QEMU even provide any emulation for the Cadence GEM or MACB architecture?

Aha, wait a minute! I seem to recall that QEMU *does* emulate Cadence GEM, like for the Xilinx Zynq platform, implemented in `cadence_gem.c`, specifically under the `arm-softmmu` section. But is this relevant to the standard syzkaller / QEMU x86_64 or arm64 environments? Or is `macb_pci` even present in that configuration?

Right, back to the source. I need to re-examine `macb_pci.c` and specifically pinpoint where `gem_ptp_init` gets called. This is key.

{
  "File": "drivers/net/ethernet/cadence/macb_pci.c",
  "FirstLine": 1,
  "LineCount": 100
}

{
  "Contents": "   1:\t// SPDX-License-Identifier: GPL-2.0-only\n   2:\t/*\n   3:\t * DOC: Cadence GEM PCI wrapper.\n   4:\t *\n   5:\t * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com\n   6:\t *\n   7:\t * Authors: Rafal Ozieblo \u003crafalo@cadence.com\u003e\n   8:\t *\t    Bartosz Folta \u003cbfolta@cadence.com\u003e\n   9:\t */\n  10:\t\n  11:\t#include \u003clinux/clk.h\u003e\n  12:\t#include \u003clinux/clk-provider.h\u003e\n  13:\t#include \u003clinux/etherdevice.h\u003e\n  14:\t#include \u003clinux/module.h\u003e\n  15:\t#include \u003clinux/pci.h\u003e\n  16:\t#include \u003clinux/platform_device.h\u003e\n  17:\t#include \"macb.h\"\n  18:\t\n  19:\t#define PCI_DRIVER_NAME \"macb_pci\"\n  20:\t#define PLAT_DRIVER_NAME \"macb\"\n  21:\t\n  22:\t#define PCI_DEVICE_ID_CDNS_MACB 0xe007\n  23:\t\n  24:\t#define GEM_PCLK_RATE 50000000\n  25:\t#define GEM_HCLK_RATE 50000000\n  26:\t\n  27:\tstatic int macb_probe(struct pci_dev *pci, const struct pci_device_id *id)\n  28:\t{\n  29:\t\tint err;\n  30:\t\tstruct platform_device *pdev;\n  31:\t\tstruct platform_device_info plat_info;\n  32:\t\tstruct macb_platform_data plat_data;\n  33:\t\tstruct resource res[2];\n  34:\t\n  35:\t\t/* enable pci device */\n  36:\t\terr = pcim_enable_device(pci);\n  37:\t\tif (err \u003c 0) {\n  38:\t\t\tdev_err(\u0026pci-\u003edev, \"Enabling PCI device has failed: %d\", err);\n  39:\t\t\treturn err;\n  40:\t\t}\n  41:\t\n  42:\t\tpci_set_master(pci);\n  43:\t\n  44:\t\t/* set up resources */\n  45:\t\tmemset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));\n  46:\t\tres[0].start = pci_resource_start(pci, 0);\n  47:\t\tres[0].end = pci_resource_end(pci, 0);\n  48:\t\tres[0].name = PCI_DRIVER_NAME;\n  49:\t\tres[0].flags = IORESOURCE_MEM;\n  50:\t\tres[1].start = pci_irq_vector(pci, 0);\n  51:\t\tres[1].name = PCI_DRIVER_NAME;\n  52:\t\tres[1].flags = IORESOURCE_IRQ;\n  53:\t\n  54:\t\tdev_info(\u0026pci-\u003edev, \"EMAC physical base addr: %pa\\n\",\n  55:\t\t\t \u0026res[0].start);\n  56:\t\n  57:\t\t/* set up macb platform data */\n  58:\t\tmemset(\u0026plat_data, 0, sizeof(plat_data));\n  59:\t\n  60:\t\t/* initialize clocks */\n  61:\t\tplat_data.pclk = clk_register_fixed_rate(\u0026pci-\u003edev, \"pclk\", NULL, 0,\n  62:\t\t\t\t\t\t\t GEM_PCLK_RATE);\n  63:\t\tif (IS_ERR(plat_data.pclk)) {\n  64:\t\t\terr = PTR_ERR(plat_data.pclk);\n  65:\t\t\tgoto err_pclk_register;\n  66:\t\t}\n  67:\t\n  68:\t\tplat_data.hclk = clk_register_fixed_rate(\u0026pci-\u003edev, \"hclk\", NULL, 0,\n  69:\t\t\t\t\t\t\t GEM_HCLK_RATE);\n  70:\t\tif (IS_ERR(plat_data.hclk)) {\n  71:\t\t\terr = PTR_ERR(plat_data.hclk);\n  72:\t\t\tgoto err_hclk_register;\n  73:\t\t}\n  74:\t\n  75:\t\t/* set up platform device info */\n  76:\t\tmemset(\u0026plat_info, 0, sizeof(plat_info));\n  77:\t\tplat_info.parent = \u0026pci-\u003edev;\n  78:\t\tplat_info.fwnode = pci-\u003edev.fwnode;\n  79:\t\tplat_info.name = PLAT_DRIVER_NAME;\n  80:\t\tplat_info.id = pci-\u003edevfn;\n  81:\t\tplat_info.res = res;\n  82:\t\tplat_info.num_res = ARRAY_SIZE(res);\n  83:\t\tplat_info.data = \u0026plat_data;\n  84:\t\tplat_info.size_data = sizeof(plat_data);\n  85:\t\tplat_info.dma_mask = pci-\u003edma_mask;\n  86:\t\n  87:\t\t/* register platform device */\n  88:\t\tpdev = platform_device_register_full(\u0026plat_info);\n  89:\t\tif (IS_ERR(pdev)) {\n  90:\t\t\terr = PTR_ERR(pdev);\n  91:\t\t\tgoto err_plat_dev_register;\n  92:\t\t}\n  93:\t\n  94:\t\tpci_set_drvdata(pci, pdev);\n  95:\t\n  96:\t\treturn 0;\n  97:\t\n  98:\terr_plat_dev_register:\n  99:\t\tclk_unregister_fixed_rate(plat_data.hclk);\n 100:\t\n"
}

							input: 19960
							output: 45
							thoughts: 50

Okay, let's dive into this. Here's what I'm thinking as I approach this patch:

**Analyzing the `gem_ptp_init` Function**

Alright, I'm going to get right to the heart of the matter. I need to understand what this patch is doing, and that starts with the `gem_ptp_init` function. The first thing I'm doing is loading up the patch. It's time to read through it. Specifically, I'm going to zero in on the implementation of `gem_ptp_init`. I'm going to look at the details within the patch. I'm going to look at the differences to see what's changed and try to understand the rationale of the change.
Then, let's zero in on `drivers/net/ethernet/cadence/macb_ptp.c` around line 330. I'm going to examine the code around that specific line. I have a feeling that's where the core of the change or the related functionality is implemented. Understanding what's happening in that immediate context is key to grasping the overall impact of the patch. Let's see if this is an update, a bugfix, or something entirely new.

{
  "File": "drivers/net/ethernet/cadence/macb_ptp.c",
  "FirstLine": 310,
  "LineCount": 80
}

{
  "Contents": " 310:\t\tdesc_ptp = macb_ptp_desc(bp, desc);\n 311:\t\t/* Unlikely but check */\n 312:\t\tif (!desc_ptp) {\n 313:\t\t\tdev_warn_ratelimited(\u0026bp-\u003epdev-\u003edev,\n 314:\t\t\t\t\t     \"Timestamp not supported in BD\\n\");\n 315:\t\t\treturn;\n 316:\t\t}\n 317:\t\n 318:\t\t/* ensure ts_1/ts_2 is loaded after ctrl (TX_USED check) */\n 319:\t\tdma_rmb();\n 320:\t\tgem_hw_timestamp(bp, desc_ptp-\u003ets_1, desc_ptp-\u003ets_2, \u0026ts);\n 321:\t\n 322:\t\tmemset(\u0026shhwtstamps, 0, sizeof(shhwtstamps));\n 323:\t\tshhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);\n 324:\t\tskb_tstamp_tx(skb, \u0026shhwtstamps);\n 325:\t}\n 326:\t\n 327:\tvoid gem_ptp_init(struct net_device *netdev)\n 328:\t{\n 329:\t\tstruct macb *bp = netdev_priv(netdev);\n 330:\t\n 331:\t\tbp-\u003eptp_clock_info = gem_ptp_caps_template;\n 332:\t\n 333:\t\tspin_lock_init(\u0026bp-\u003etsu_clk_lock);\n 334:\t\n 335:\t\t/* nominal frequency and maximum adjustment in ppb */\n 336:\t\tbp-\u003etsu_rate = bp-\u003eptp_info-\u003eget_tsu_rate(bp);\n 337:\t\tbp-\u003eptp_clock_info.max_adj = bp-\u003eptp_info-\u003eget_ptp_max_adj();\n 338:\t\tgem_ptp_init_timer(bp);\n 339:\t\tbp-\u003eptp_clock = ptp_clock_register(\u0026bp-\u003eptp_clock_info, \u0026netdev-\u003edev);\n 340:\t\tif (IS_ERR(bp-\u003eptp_clock)) {\n 341:\t\t\tpr_err(\"ptp clock register failed: %ld\\n\",\n 342:\t\t\t\tPTR_ERR(bp-\u003eptp_clock));\n 343:\t\t\tbp-\u003eptp_clock = NULL;\n 344:\t\t\treturn;\n 345:\t\t} else if (bp-\u003eptp_clock == NULL) {\n 346:\t\t\tpr_err(\"ptp clock register failed\\n\");\n 347:\t\t\treturn;\n 348:\t\t}\n 349:\t\n 350:\t\tgem_ptp_init_tsu(bp);\n 351:\t\n 352:\t\tdev_info(\u0026bp-\u003epdev-\u003edev, \"%s ptp clock registered.\\n\",\n 353:\t\t\t GEM_PTP_TIMER_NAME);\n 354:\t}\n 355:\t\n 356:\tvoid gem_ptp_remove(struct net_device *netdev)\n 357:\t{\n 358:\t\tstruct macb *bp = netdev_priv(netdev);\n 359:\t\n 360:\t\tif (bp-\u003eptp_clock) {\n 361:\t\t\tptp_clock_unregister(bp-\u003eptp_clock);\n 362:\t\t\tbp-\u003eptp_clock = NULL;\n 363:\t\t}\n 364:\t\n 365:\t\tgem_ptp_clear_timer(bp);\n 366:\t\n 367:\t\tdev_info(\u0026bp-\u003epdev-\u003edev, \"%s ptp clock unregistered.\\n\",\n 368:\t\t\t GEM_PTP_TIMER_NAME);\n 369:\t}\n 370:\t\n 371:\tstatic int gem_ptp_set_ts_mode(struct macb *bp,\n 372:\t\t\t\t       enum macb_bd_control tx_bd_control,\n 373:\t\t\t\t       enum macb_bd_control rx_bd_control)\n 374:\t{\n 375:\t\tgem_writel(bp, TXBDCTRL, GEM_BF(TXTSMODE, tx_bd_control));\n 376:\t\tgem_writel(bp, RXBDCTRL, GEM_BF(RXTSMODE, rx_bd_control));\n 377:\t\n 378:\t\treturn 0;\n 379:\t}\n 380:\t\n 381:\tint gem_get_hwtst(struct net_device *netdev,\n 382:\t\t\t  struct kernel_hwtstamp_config *tstamp_config)\n 383:\t{\n 384:\t\tstruct macb *bp = netdev_priv(netdev);\n 385:\t\n 386:\t\t*tstamp_config = bp-\u003etstamp_config;\n 387:\t\tif (!macb_dma_ptp(bp))\n 388:\t\t\treturn -EOPNOTSUPP;\n 389:\t\n"
}

							input: 21652
							output: 35
							thoughts: 133

**Debugging a Potential Race Condition**

Okay, let's break this down. It looks like we have a potential race condition in `gem_ptp_init`. Specifically, `gem_ptp_init_timer(bp)` is being called before the `spin_lock_init(&bp->tsu_clk_lock)`. Now, that immediately raises a red flag. We need to know if `gem_ptp_init_timer` or, for that matter, `ptp_clock_register` (since they could be related) are touching `bp->tsu_clk_lock`. I'll go search the code. Looks like I will need to search for `tsu_clk_lock` in `macb_ptp.c` to see how it's being used.

{
  "Expression": "tsu_clk_lock",
  "PathPrefix": "drivers/net/ethernet/cadence"
}

{
  "Output": "drivers/net/ethernet/cadence/macb.h=1298=struct macb {\n--\ndrivers/net/ethernet/cadence/macb.h-1362-\ndrivers/net/ethernet/cadence/macb.h:1363:\tspinlock_t tsu_clk_lock; /* gem tsu clock locking */\ndrivers/net/ethernet/cadence/macb.h-1364-\tunsigned int tsu_rate;\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=43=static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-50-\ndrivers/net/ethernet/cadence/macb_ptp.c:51:\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-52-\tptp_read_system_prets(sts);\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-72-\ndrivers/net/ethernet/cadence/macb_ptp.c:73:\tspin_unlock_irqrestore(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-74-\tts-\u003etv_sec = (((u64)sech \u003c\u003c GEM_TSL_SIZE) | secl)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=79=static int gem_tsu_set_time(struct ptp_clock_info *ptp,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-89-\ndrivers/net/ethernet/cadence/macb_ptp.c:90:\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-91-\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-98-\ndrivers/net/ethernet/cadence/macb_ptp.c:99:\tspin_unlock_irqrestore(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-100-\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=104=static int gem_tsu_incr_set(struct macb *bp, struct tsu_incr *incr_spec)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-112-\t */\ndrivers/net/ethernet/cadence/macb_ptp.c:113:\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-114-\t/* RegBit[15:0] = Subns[23:8]; RegBit[31:24] = Subns[7:0] */\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-118-\tgem_writel(bp, TI, GEM_BF(NSINCR, incr_spec-\u003ens));\ndrivers/net/ethernet/cadence/macb_ptp.c:119:\tspin_unlock_irqrestore(\u0026bp-\u003etsu_clk_lock, flags);\ndrivers/net/ethernet/cadence/macb_ptp.c-120-\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=327=void gem_ptp_init(struct net_device *netdev)\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-332-\ndrivers/net/ethernet/cadence/macb_ptp.c:333:\tspin_lock_init(\u0026bp-\u003etsu_clk_lock);\ndrivers/net/ethernet/cadence/macb_ptp.c-334-\n"
}

							input: 23037
							output: 45
							thoughts: 71

Here's my analysis of what's going on:

**Dissecting the `gem_tsu_incr_set` Function Call**

Okay, so I'm tracking this function call, `gem_tsu_incr_set`, and it looks like it's being initiated from within `gem_ptp_init_timer(bp)`.  That's my starting point. Now, to understand the context of the call, I need to dive deeper into `gem_ptp_init_timer(bp)`. The code suggests the function is located in `macb_ptp.c`, lines 100 to 250 seem the relevant area for this deeper look. I'll focus my attention on that section to see what's leading up to the `gem_tsu_incr_set` call and what's happening immediately after. That should give me the insights I need to understand the role of `gem_tsu_incr_set` in the larger PTP initialization flow.

{
  "File": "drivers/net/ethernet/cadence/macb_ptp.c",
  "FirstLine": 100,
  "LineCount": 80
}

{
  "Contents": " 100:\t\n 101:\t\treturn 0;\n 102:\t}\n 103:\t\n 104:\tstatic int gem_tsu_incr_set(struct macb *bp, struct tsu_incr *incr_spec)\n 105:\t{\n 106:\t\tunsigned long flags;\n 107:\t\n 108:\t\t/* tsu_timer_incr register must be written after\n 109:\t\t * the tsu_timer_incr_sub_ns register and the write operation\n 110:\t\t * will cause the value written to the tsu_timer_incr_sub_ns register\n 111:\t\t * to take effect.\n 112:\t\t */\n 113:\t\tspin_lock_irqsave(\u0026bp-\u003etsu_clk_lock, flags);\n 114:\t\t/* RegBit[15:0] = Subns[23:8]; RegBit[31:24] = Subns[7:0] */\n 115:\t\tgem_writel(bp, TISUBN, GEM_BF(SUBNSINCRL, incr_spec-\u003esub_ns) |\n 116:\t\t\t   GEM_BF(SUBNSINCRH, (incr_spec-\u003esub_ns \u003e\u003e\n 117:\t\t\t\t  GEM_SUBNSINCRL_SIZE)));\n 118:\t\tgem_writel(bp, TI, GEM_BF(NSINCR, incr_spec-\u003ens));\n 119:\t\tspin_unlock_irqrestore(\u0026bp-\u003etsu_clk_lock, flags);\n 120:\t\n 121:\t\treturn 0;\n 122:\t}\n 123:\t\n 124:\tstatic int gem_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)\n 125:\t{\n 126:\t\tstruct macb *bp = container_of(ptp, struct macb, ptp_clock_info);\n 127:\t\tstruct tsu_incr incr_spec;\n 128:\t\tbool neg_adj = false;\n 129:\t\tu32 word;\n 130:\t\tu64 adj;\n 131:\t\n 132:\t\tif (scaled_ppm \u003c 0) {\n 133:\t\t\tneg_adj = true;\n 134:\t\t\tscaled_ppm = -scaled_ppm;\n 135:\t\t}\n 136:\t\n 137:\t\t/* Adjustment is relative to base frequency */\n 138:\t\tincr_spec.sub_ns = bp-\u003etsu_incr.sub_ns;\n 139:\t\tincr_spec.ns = bp-\u003etsu_incr.ns;\n 140:\t\n 141:\t\t/* scaling: unused(8bit) | ns(8bit) | fractions(16bit) */\n 142:\t\tword = ((u64)incr_spec.ns \u003c\u003c GEM_SUBNSINCR_SIZE) + incr_spec.sub_ns;\n 143:\t\tadj = (u64)scaled_ppm * word;\n 144:\t\t/* Divide with rounding, equivalent to floating dividing:\n 145:\t\t * (temp / USEC_PER_SEC) + 0.5\n 146:\t\t */\n 147:\t\tadj += (USEC_PER_SEC \u003e\u003e 1);\n 148:\t\tadj \u003e\u003e= PPM_FRACTION; /* remove fractions */\n 149:\t\tadj = div_u64(adj, USEC_PER_SEC);\n 150:\t\tadj = neg_adj ? (word - adj) : (word + adj);\n 151:\t\n 152:\t\tincr_spec.ns = (adj \u003e\u003e GEM_SUBNSINCR_SIZE)\n 153:\t\t\t\t\u0026 ((1 \u003c\u003c GEM_NSINCR_SIZE) - 1);\n 154:\t\tincr_spec.sub_ns = adj \u0026 ((1 \u003c\u003c GEM_SUBNSINCR_SIZE) - 1);\n 155:\t\tgem_tsu_incr_set(bp, \u0026incr_spec);\n 156:\t\treturn 0;\n 157:\t}\n 158:\t\n 159:\tstatic int gem_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)\n 160:\t{\n 161:\t\tstruct macb *bp = container_of(ptp, struct macb, ptp_clock_info);\n 162:\t\tstruct timespec64 now, then = ns_to_timespec64(delta);\n 163:\t\tu32 adj, sign = 0;\n 164:\t\n 165:\t\tif (delta \u003c 0) {\n 166:\t\t\tsign = 1;\n 167:\t\t\tdelta = -delta;\n 168:\t\t}\n 169:\t\n 170:\t\tif (delta \u003e TSU_NSEC_MAX_VAL) {\n 171:\t\t\tgem_tsu_get_time(\u0026bp-\u003eptp_clock_info, \u0026now, NULL);\n 172:\t\t\tnow = timespec64_add(now, then);\n 173:\t\n 174:\t\t\tgem_tsu_set_time(\u0026bp-\u003eptp_clock_info,\n 175:\t\t\t\t\t (const struct timespec64 *)\u0026now);\n 176:\t\t} else {\n 177:\t\t\tadj = (sign \u003c\u003c GEM_ADDSUB_OFFSET) | delta;\n 178:\t\n 179:\t\t\tgem_writel(bp, TA, adj);\n"
}

							input: 24784
							output: 45
							thoughts: 40

Here's my take on the thought process, as requested:

**Deconstructing `gem_ptp_init_timer`**

Alright, let's dive into this `gem_ptp_init_timer` function. I need to understand its role within this PTP implementation, so I'm going to start by running through the code block from lines 200 to 300. This should give me a solid grasp of what this timer initialization routine is actually doing. My focus will be on the critical parts for synchronization.

{
  "File": "drivers/net/ethernet/cadence/macb_ptp.c",
  "FirstLine": 200,
  "LineCount": 60
}

{
  "Contents": " 200:\t\t.adjfine\t= gem_ptp_adjfine,\n 201:\t\t.adjtime\t= gem_ptp_adjtime,\n 202:\t\t.gettimex64\t= gem_tsu_get_time,\n 203:\t\t.settime64\t= gem_tsu_set_time,\n 204:\t\t.enable\t\t= gem_ptp_enable,\n 205:\t};\n 206:\t\n 207:\tstatic void gem_ptp_init_timer(struct macb *bp)\n 208:\t{\n 209:\t\tu32 rem = 0;\n 210:\t\tu64 adj;\n 211:\t\n 212:\t\tbp-\u003etsu_incr.ns = div_u64_rem(NSEC_PER_SEC, bp-\u003etsu_rate, \u0026rem);\n 213:\t\tif (rem) {\n 214:\t\t\tadj = rem;\n 215:\t\t\tadj \u003c\u003c= GEM_SUBNSINCR_SIZE;\n 216:\t\t\tbp-\u003etsu_incr.sub_ns = div_u64(adj, bp-\u003etsu_rate);\n 217:\t\t} else {\n 218:\t\t\tbp-\u003etsu_incr.sub_ns = 0;\n 219:\t\t}\n 220:\t}\n 221:\t\n 222:\tstatic void gem_ptp_init_tsu(struct macb *bp)\n 223:\t{\n 224:\t\tstruct timespec64 ts;\n 225:\t\n 226:\t\t/* 1. get current system time */\n 227:\t\tts = ns_to_timespec64(ktime_to_ns(ktime_get_real()));\n 228:\t\n 229:\t\t/* 2. set ptp timer */\n 230:\t\tgem_tsu_set_time(\u0026bp-\u003eptp_clock_info, \u0026ts);\n 231:\t\n 232:\t\t/* 3. set PTP timer increment value to BASE_INCREMENT */\n 233:\t\tgem_tsu_incr_set(bp, \u0026bp-\u003etsu_incr);\n 234:\t\n 235:\t\tgem_writel(bp, TA, 0);\n 236:\t}\n 237:\t\n 238:\tstatic void gem_ptp_clear_timer(struct macb *bp)\n 239:\t{\n 240:\t\tbp-\u003etsu_incr.sub_ns = 0;\n 241:\t\tbp-\u003etsu_incr.ns = 0;\n 242:\t\n 243:\t\tgem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, 0));\n 244:\t\tgem_writel(bp, TI, GEM_BF(NSINCR, 0));\n 245:\t\tgem_writel(bp, TA, 0);\n 246:\t}\n 247:\t\n 248:\tstatic int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1,\n 249:\t\t\t\t    u32 dma_desc_ts_2, struct timespec64 *ts)\n 250:\t{\n 251:\t\tstruct timespec64 tsu;\n 252:\t\n 253:\t\tts-\u003etv_sec = (GEM_BFEXT(DMA_SECH, dma_desc_ts_2) \u003c\u003c GEM_DMA_SECL_SIZE) |\n 254:\t\t\t\tGEM_BFEXT(DMA_SECL, dma_desc_ts_1);\n 255:\t\tts-\u003etv_nsec = GEM_BFEXT(DMA_NSEC, dma_desc_ts_1);\n 256:\t\n 257:\t\t/* TSU overlapping workaround\n 258:\t\t * The timestamp only contains lower few bits of seconds,\n 259:\t\t * so add value from 1588 timer\n"
}

							input: 26021
							output: 34
							thoughts: 571

**My Analysis of a Potential Spinlock Bug Fix**

Okay, so I'm looking at this patch for `gem_ptp_init`. It seems like there's a potential concurrency issue with the spinlock `bp->tsu_clk_lock`. The core of the problem is the order of operations in this function. We're registering the PTP clock using `ptp_clock_register(&bp->ptp_clock_info, &netdev->dev);`. The key thing is that *immediately* after `ptp_clock_register` completes, user space or kernel threads can start interacting with the PTP clock device. They might be calling things like `clock_adjtime`, `gem_tsu_get_time`, or `gem_tsu_set_time` - all of which use that `bp->tsu_clk_lock`! The potential bug arises because the spinlock `spin_lock_init(&bp->tsu_clk_lock)` *was* being called *after* the registration. This means the lock could have been uninitialized during the critical window when the PTP clock was already accessible. The proposed fix, moving the `spin_lock_init` call earlier, makes perfect sense to resolve the race condition.

Now, the next step is crucial. Can this fix be fuzzed? I need to apply the fuzzing guidelines meticulously. Let me recall the "WorthFuzzing=false" criteria from memory. We need to rule out:

* Documentation, Kconfig, or comment-only changes. Nope, this is a code change.
* Purely decorative logging. Definitely not the case here.
* Numeric constant changes that don't alter execution. Not relevant.
* Unreachable code in virtualized environments. This is a real concern! I'll need to research what MACB/GEM actually *is*.
* Vendor-specific hardware drivers that are hard to emulate. Probably not, but I need to be sure.
* Teardown callbacks during PCI hot-unplug. Nope, that's not what this is.

So, the biggest question is whether this code is *reachable* in a standard QEMU environment. We need to figure out what kind of device MACB/GEM is. Is it a platform device or a PCI device? How are these devices typically instantiated? I need to dig into `macb_main.c` and `macb_pci.c` to understand the device initialization and connection mechanism. Only then can I decide if this fix is worth fuzzing.

{
  "Expression": "MODULE_DEVICE_TABLE",
  "PathPrefix": "drivers/net/ethernet/cadence"
}

{
  "Output": "drivers/net/ethernet/cadence/macb_main.c=5727=static const struct of_device_id macb_dt_ids[] = {\n--\ndrivers/net/ethernet/cadence/macb_main.c-5754-};\ndrivers/net/ethernet/cadence/macb_main.c:5755:MODULE_DEVICE_TABLE(of, macb_dt_ids);\ndrivers/net/ethernet/cadence/macb_main.c-5756-\n--\ndrivers/net/ethernet/cadence/macb_pci.c=132=module_pci_driver(macb_pci_driver);\ndrivers/net/ethernet/cadence/macb_pci.c:133:MODULE_DEVICE_TABLE(pci, dev_id_table);\ndrivers/net/ethernet/cadence/macb_pci.c-134-MODULE_LICENSE(\"GPL\");\n"
}

							input: 27426
							output: 34
							thoughts: 21

Here's my thought process, as it stands:

**Checking `dev_id_table` in `macb_pci.c`**

Okay, so I need to understand how the driver in `macb_pci.c` identifies the specific hardware it's supposed to handle. That probably means the first thing to look at is the `dev_id_table`. I'm expecting this is where the driver defines the PCI device IDs it's compatible with. This will likely be a list or array of structures, each containing the vendor ID and device ID that this driver recognizes. I'll need to see how the driver uses this table during initialization, specifically how it probes for compatible devices during the PCI probe function. I'm anticipating some form of loop to iterate through the table and compare the hardware ID with what the system presents to it during probe. Time to dive into the code and confirm my hunch!

{
  "Expression": "dev_id_table",
  "PathPrefix": "drivers/net/ethernet/cadence"
}

{
  "Output": "drivers/net/ethernet/cadence/macb_pci.c=108=static void macb_remove(struct pci_dev *pci)\n--\ndrivers/net/ethernet/cadence/macb_pci.c-119-\ndrivers/net/ethernet/cadence/macb_pci.c:120:static const struct pci_device_id dev_id_table[] = {\ndrivers/net/ethernet/cadence/macb_pci.c-121-\t{ PCI_VDEVICE(CDNS, PCI_DEVICE_ID_CDNS_MACB) },\n--\ndrivers/net/ethernet/cadence/macb_pci.c=125=static struct pci_driver macb_pci_driver = {\ndrivers/net/ethernet/cadence/macb_pci.c-126-\t.name     = PCI_DRIVER_NAME,\ndrivers/net/ethernet/cadence/macb_pci.c:127:\t.id_table = dev_id_table,\ndrivers/net/ethernet/cadence/macb_pci.c-128-\t.probe    = macb_probe,\n--\ndrivers/net/ethernet/cadence/macb_pci.c=132=module_pci_driver(macb_pci_driver);\ndrivers/net/ethernet/cadence/macb_pci.c:133:MODULE_DEVICE_TABLE(pci, dev_id_table);\ndrivers/net/ethernet/cadence/macb_pci.c-134-MODULE_LICENSE(\"GPL\");\n"
}

							input: 28087
							output: 45
							thoughts: 80

Here's my take on those thoughts:

**Analyzing a Cadence MACB Driver**

Okay, so I'm looking at a Cadence PCI device, specifically identified by vendor ID `0x17cd` and device ID `0xe007` – that's `PCI_VENDOR_ID_CDNS` and `PCI_DEVICE_ID_CDNS_MACB`, right? I'm pretty sure that's a Cadence MACB. Now, where does this fit in the driver landscape? Ah, yes, `macb_main.c`. That file's usually a good indicator. It looks like this is an Open Firmware (OF) or platform driver implementation. Time to confirm the device identifiers used by the driver. Let me dig into `macb_dt_ids` and cross-reference. I'll see what the device tree bindings are to confirm and understand how this device is meant to be configured.

{
  "File": "drivers/net/ethernet/cadence/macb_main.c",
  "FirstLine": 5727,
  "LineCount": 35
}

{
  "Contents": "5727:\tstatic const struct of_device_id macb_dt_ids[] = {\n5728:\t\t{ .compatible = \"cdns,at91sam9260-macb\", .data = \u0026at91sam9260_config },\n5729:\t\t{ .compatible = \"cdns,macb\" },\n5730:\t\t{ .compatible = \"cdns,np4-macb\", .data = \u0026np4_config },\n5731:\t\t{ .compatible = \"cdns,pc302-gem\", .data = \u0026pc302gem_config },\n5732:\t\t{ .compatible = \"cdns,gem\", .data = \u0026pc302gem_config },\n5733:\t\t{ .compatible = \"cdns,sam9x60-macb\", .data = \u0026at91sam9260_config },\n5734:\t\t{ .compatible = \"atmel,sama5d2-gem\", .data = \u0026sama5d2_config },\n5735:\t\t{ .compatible = \"atmel,sama5d29-gem\", .data = \u0026sama5d29_config },\n5736:\t\t{ .compatible = \"atmel,sama5d3-gem\", .data = \u0026sama5d3_config },\n5737:\t\t{ .compatible = \"atmel,sama5d3-macb\", .data = \u0026sama5d3macb_config },\n5738:\t\t{ .compatible = \"atmel,sama5d4-gem\", .data = \u0026sama5d4_config },\n5739:\t\t{ .compatible = \"cdns,at91rm9200-emac\", .data = \u0026emac_config },\n5740:\t\t{ .compatible = \"cdns,emac\", .data = \u0026emac_config },\n5741:\t\t{ .compatible = \"cdns,zynqmp-gem\", .data = \u0026zynqmp_config}, /* deprecated */\n5742:\t\t{ .compatible = \"cdns,zynq-gem\", .data = \u0026zynq_config }, /* deprecated */\n5743:\t\t{ .compatible = \"sifive,fu540-c000-gem\", .data = \u0026fu540_c000_config },\n5744:\t\t{ .compatible = \"microchip,mpfs-macb\", .data = \u0026mpfs_config },\n5745:\t\t{ .compatible = \"microchip,pic64hpsc-gem\", .data = \u0026pic64hpsc_config},\n5746:\t\t{ .compatible = \"microchip,sama7g5-gem\", .data = \u0026sama7g5_gem_config },\n5747:\t\t{ .compatible = \"microchip,sama7g5-emac\", .data = \u0026sama7g5_emac_config },\n5748:\t\t{ .compatible = \"mobileye,eyeq5-gem\", .data = \u0026eyeq5_config },\n5749:\t\t{ .compatible = \"raspberrypi,rp1-gem\", .data = \u0026raspberrypi_rp1_config },\n5750:\t\t{ .compatible = \"xlnx,zynqmp-gem\", .data = \u0026zynqmp_config},\n5751:\t\t{ .compatible = \"xlnx,zynq-gem\", .data = \u0026zynq_config },\n5752:\t\t{ .compatible = \"xlnx,versal-gem\", .data = \u0026versal_config},\n5753:\t\t{ /* sentinel */ }\n5754:\t};\n5755:\tMODULE_DEVICE_TABLE(of, macb_dt_ids);\n5756:\t\n5757:\tstatic const struct macb_config default_gem_config = {\n5758:\t\t.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |\n5759:\t\t\tMACB_CAPS_JUMBO |\n5760:\t\t\tMACB_CAPS_GEM_HAS_PTP,\n5761:\t\t.dma_burst_length = 16,\n"
}

							input: 29426
							output: 32
							thoughts: 936

**Analyzing the Fuzzing Potential of the Cadence GEM (MACB) Driver**

Okay, let's break this down. I'm looking at potential candidates for fuzzing, and the Cadence GEM (MACB) driver is on the list. First, let me recall the common SoCs this driver is associated with: SiFive, Xilinx Zynq/ZynqMP/Versal, Cadence, and Atmel. I need to quickly determine if any of these are emulated in standard QEMU or used within virtualized environments, which is crucial for Syzkaller's effectiveness.

Right, QEMU has machine types. I remember `xlnx-zcu102`, `xlnx-versal-virt`, `xilinx-zynq-a9`, `sifive_u`, `microchip-icicle-kit`. But Syzkaller primarily targets x86_64 and arm64, specifically virtual machines with virtio, or gVisor. So, what standard devices are typically found in QEMU or GCE for fuzzing? That's the key.

Now, I have to consider the instructions. The crucial criteria I need to use to determine if a patch is WorthFuzzing is the following. A patch should return "WorthFuzzing=false" if it only contains:
- documentation changes
- config file modifications
- code comments
- decorative changes such as logging or tracepoints
- changes to constants or macros that doesn't alter execution flow
- unreachable code in virtualized environments, such as usb gadget or mac80211_hwsim
- vendor-specific PCIe switch, SmartNIC, or GPU drivers that require physical PCIe hardware cards not emulated in standard QEMU
- driver .remove, .shutdown, or pci_unregister_driver teardown callbacks that are executed only during PCI hot-unplug or sysfs driver unbind operations.

Otherwise it's "WorthFuzzing=true" if a patch modifies reachable core kernel logic, drivers, or architectures. I need to verify that code can be executed using code search tools.

So, is `macb` or `gem_ptp` a vendor-specific hardware driver? Does it require specific board DT not present in standard fuzzing environments (x86/arm64 virt)? I must investigate.

Let's check. Can `macb` be instantiated via PCI in standard QEMU? Specifically, does QEMU have a PCI Cadence MACB device? No, QEMU's `cadence_gem` is a SysBusDevice, memory mapped I/O on Zynq / Versal / SiFive U SoC, not a PCI device. What about `macb_pci`? The PCI ID 0x17cd:0xe007 points to Cadence's PCI testboard / FPGA card, which isn't emulated in QEMU. What about platform devices? In standard QEMU x86_64 (q35 / pc) and ARM64 (`-M virt`), there's no Cadence GEM / MACB node defined in the device tree or ACPI.

Can Syzkaller instantiate platform devices via Device Tree overlays or configfs? No, it runs on standard QEMU or GCE VMs, where kernel devices are ACPI, PCI, USB, or software pseudo devices.

Time to look at other network and SoC ethernet drivers. I need to understand how those are handled. I will perform a search in the repo or check similar drivers. Is `drivers/net/ethernet/cadence` reachable?

Finally, let's explore if there are any mock or test frameworks for macb, or if it is tied to specific embedded SoCs and PCI test cards. Is there a standard way to instantiate MACB? That's the critical question I need to answer.

{
  "Expression": "macb_",
  "PathPrefix": "drivers/net/ethernet/cadence"
}

{
  "Output": "\nFull output is too long, showing 500 out of 2598 lines.\nUse more precise expression if possible.\n\ndrivers/net/ethernet/cadence/Kconfig=45=config MACB_PCI\n--\ndrivers/net/ethernet/cadence/Kconfig-51-\t  To compile this driver as a module, choose M here: the module\ndrivers/net/ethernet/cadence/Kconfig:52:\t  will be called macb_pci.\ndrivers/net/ethernet/cadence/Kconfig-53-\n--\ndrivers/net/ethernet/cadence/Makefile-4-#\ndrivers/net/ethernet/cadence/Makefile:5:macb-y\t:= macb_main.o\ndrivers/net/ethernet/cadence/Makefile-6-\ndrivers/net/ethernet/cadence/Makefile=7=ifeq ($(CONFIG_MACB_USE_HWSTAMP),y)\ndrivers/net/ethernet/cadence/Makefile:8:macb-y\t+= macb_ptp.o\ndrivers/net/ethernet/cadence/Makefile-9-endif\n--\ndrivers/net/ethernet/cadence/Makefile=11=obj-$(CONFIG_MACB) += macb.o\ndrivers/net/ethernet/cadence/Makefile:12:obj-$(CONFIG_MACB_PCI) += macb_pci.o\n--\ndrivers/net/ethernet/cadence/macb.h-820-/* Register access macros */\ndrivers/net/ethernet/cadence/macb.h:821:#define macb_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), MACB_##reg)\ndrivers/net/ethernet/cadence/macb.h:822:#define macb_writel(port, reg, value)\t(port)-\u003emacb_reg_writel((port), MACB_##reg, (value))\ndrivers/net/ethernet/cadence/macb.h:823:#define gem_readl(port, reg)\t\t(port)-\u003emacb_reg_readl((port), GEM_##reg)\ndrivers/net/ethernet/cadence/macb.h:824:#define gem_writel(port, reg, value)\t(port)-\u003emacb_reg_writel((port), GEM_##reg, (value))\ndrivers/net/ethernet/cadence/macb.h:825:#define queue_readl(queue, reg)\t\t(queue)-\u003ebp-\u003emacb_reg_readl((queue)-\u003ebp, (queue)-\u003ereg)\ndrivers/net/ethernet/cadence/macb.h:826:#define queue_writel(queue, reg, value)\t(queue)-\u003ebp-\u003emacb_reg_writel((queue)-\u003ebp, (queue)-\u003ereg, (value))\ndrivers/net/ethernet/cadence/macb.h:827:#define gem_readl_n(port, reg, idx)\t\t(port)-\u003emacb_reg_readl((port), GEM_##reg + idx * 4)\ndrivers/net/ethernet/cadence/macb.h:828:#define gem_writel_n(port, reg, idx, value)\t(port)-\u003emacb_reg_writel((port), GEM_##reg + idx * 4, (value))\ndrivers/net/ethernet/cadence/macb.h-829-\n--\ndrivers/net/ethernet/cadence/macb.h-831- * register dependent on whether the device is a GEM or a MACB.  For registers\ndrivers/net/ethernet/cadence/macb.h:832: * and bitfields that are common across both devices, use macb_{read,write}l\ndrivers/net/ethernet/cadence/macb.h-833- * to avoid the cost of the conditional.\ndrivers/net/ethernet/cadence/macb.h-834- */\ndrivers/net/ethernet/cadence/macb.h:835:#define macb_or_gem_writel(__bp, __reg, __value) \\\ndrivers/net/ethernet/cadence/macb.h-836-\t({ \\\ndrivers/net/ethernet/cadence/macb.h:837:\t\tif (macb_is_gem((__bp))) \\\ndrivers/net/ethernet/cadence/macb.h-838-\t\t\tgem_writel((__bp), __reg, __value); \\\ndrivers/net/ethernet/cadence/macb.h-839-\t\telse \\\ndrivers/net/ethernet/cadence/macb.h:840:\t\t\tmacb_writel((__bp), __reg, __value); \\\ndrivers/net/ethernet/cadence/macb.h-841-\t})\ndrivers/net/ethernet/cadence/macb.h-842-\ndrivers/net/ethernet/cadence/macb.h:843:#define macb_or_gem_readl(__bp, __reg) \\\ndrivers/net/ethernet/cadence/macb.h-844-\t({ \\\ndrivers/net/ethernet/cadence/macb.h-845-\t\tu32 __v; \\\ndrivers/net/ethernet/cadence/macb.h:846:\t\tif (macb_is_gem((__bp))) \\\ndrivers/net/ethernet/cadence/macb.h-847-\t\t\t__v = gem_readl((__bp), __reg); \\\ndrivers/net/ethernet/cadence/macb.h-848-\t\telse \\\ndrivers/net/ethernet/cadence/macb.h:849:\t\t\t__v = macb_readl((__bp), __reg); \\\ndrivers/net/ethernet/cadence/macb.h-850-\t\t__v; \\\n--\ndrivers/net/ethernet/cadence/macb.h-852-\ndrivers/net/ethernet/cadence/macb.h:853:#define MACB_READ_NSR(bp)\tmacb_readl(bp, NSR)\ndrivers/net/ethernet/cadence/macb.h-854-\ndrivers/net/ethernet/cadence/macb.h:855:/* struct macb_dma_desc - Hardware DMA descriptor\ndrivers/net/ethernet/cadence/macb.h-856- * @addr: DMA address of data buffer\n--\ndrivers/net/ethernet/cadence/macb.h-858- */\ndrivers/net/ethernet/cadence/macb.h:859:struct macb_dma_desc {\ndrivers/net/ethernet/cadence/macb.h-860-\tu32\taddr;\n--\ndrivers/net/ethernet/cadence/macb.h-863-\ndrivers/net/ethernet/cadence/macb.h:864:struct macb_dma_desc_64 {\ndrivers/net/ethernet/cadence/macb.h-865-\tu32 addrh;\n--\ndrivers/net/ethernet/cadence/macb.h-868-\ndrivers/net/ethernet/cadence/macb.h:869:struct macb_dma_desc_ptp {\ndrivers/net/ethernet/cadence/macb.h-870-\tu32\tts_1;\n--\ndrivers/net/ethernet/cadence/macb.h-965-\ndrivers/net/ethernet/cadence/macb.h:966:/* struct macb_tx_skb - data about an skb which is being transmitted\ndrivers/net/ethernet/cadence/macb.h-967- * @skb: skb currently being transmitted, only set for the last buffer\n--\ndrivers/net/ethernet/cadence/macb.h-973- */\ndrivers/net/ethernet/cadence/macb.h:974:struct macb_tx_skb {\ndrivers/net/ethernet/cadence/macb.h-975-\tstruct sk_buff\t\t*skb;\n--\ndrivers/net/ethernet/cadence/macb.h-983- */\ndrivers/net/ethernet/cadence/macb.h:984:struct macb_stats {\ndrivers/net/ethernet/cadence/macb.h-985-\tu64\trx_pause_frames;\n--\ndrivers/net/ethernet/cadence/macb.h=1191=struct macb;\ndrivers/net/ethernet/cadence/macb.h:1192:struct macb_queue;\ndrivers/net/ethernet/cadence/macb.h-1193-\ndrivers/net/ethernet/cadence/macb.h:1194:struct macb_or_gem_ops {\ndrivers/net/ethernet/cadence/macb.h-1195-\tint\t(*mog_alloc_rx_buffers)(struct macb *bp);\n--\ndrivers/net/ethernet/cadence/macb.h-1197-\tvoid\t(*mog_init_rings)(struct macb *bp);\ndrivers/net/ethernet/cadence/macb.h:1198:\tint\t(*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,\ndrivers/net/ethernet/cadence/macb.h-1199-\t\t\t  int budget);\n--\ndrivers/net/ethernet/cadence/macb.h-1202-/* MACB-PTP interface: adapt to platform needs. */\ndrivers/net/ethernet/cadence/macb.h:1203:struct macb_ptp_info {\ndrivers/net/ethernet/cadence/macb.h-1204-\tvoid (*ptp_init)(struct net_device *netdev);\n--\ndrivers/net/ethernet/cadence/macb.h-1216-\ndrivers/net/ethernet/cadence/macb.h:1217:struct macb_pm_data {\ndrivers/net/ethernet/cadence/macb.h-1218-\tu32 scrt2;\n--\ndrivers/net/ethernet/cadence/macb.h-1221-\ndrivers/net/ethernet/cadence/macb.h:1222:struct macb_usrio_config {\ndrivers/net/ethernet/cadence/macb.h-1223-\tu32 mii;\n--\ndrivers/net/ethernet/cadence/macb.h-1232-\ndrivers/net/ethernet/cadence/macb.h:1233:struct macb_config {\ndrivers/net/ethernet/cadence/macb.h-1234-\tu32\t\t\tcaps;\n--\ndrivers/net/ethernet/cadence/macb.h-1241-\tint\tjumbo_max_len;\ndrivers/net/ethernet/cadence/macb.h:1242:\tconst struct macb_usrio_config *usrio;\ndrivers/net/ethernet/cadence/macb.h-1243-};\n--\ndrivers/net/ethernet/cadence/macb.h=1245=struct tsu_incr {\n--\ndrivers/net/ethernet/cadence/macb.h-1249-\ndrivers/net/ethernet/cadence/macb.h:1250:struct macb_queue {\ndrivers/net/ethernet/cadence/macb.h-1251-\tstruct macb\t\t*bp;\n--\ndrivers/net/ethernet/cadence/macb.h-1269-\tunsigned int\t\ttx_head, tx_tail;\ndrivers/net/ethernet/cadence/macb.h:1270:\tstruct macb_dma_desc\t*tx_ring;\ndrivers/net/ethernet/cadence/macb.h:1271:\tstruct macb_tx_skb\t*tx_skb;\ndrivers/net/ethernet/cadence/macb.h-1272-\tdma_addr_t\t\ttx_ring_dma;\n--\ndrivers/net/ethernet/cadence/macb.h-1280-\tunsigned int\t\trx_prepared_head;\ndrivers/net/ethernet/cadence/macb.h:1281:\tstruct macb_dma_desc\t*rx_ring;\ndrivers/net/ethernet/cadence/macb.h-1282-\tstruct sk_buff\t\t**rx_skbuff;\n--\ndrivers/net/ethernet/cadence/macb.h=1298=struct macb {\n--\ndrivers/net/ethernet/cadence/macb.h-1302-\t/* hardware IO accessors */\ndrivers/net/ethernet/cadence/macb.h:1303:\tu32\t(*macb_reg_readl)(struct macb *bp, int offset);\ndrivers/net/ethernet/cadence/macb.h:1304:\tvoid\t(*macb_reg_writel)(struct macb *bp, int offset, u32 value);\ndrivers/net/ethernet/cadence/macb.h-1305-\ndrivers/net/ethernet/cadence/macb.h:1306:\tstruct macb_dma_desc\t*rx_ring_tieoff;\ndrivers/net/ethernet/cadence/macb.h-1307-\tdma_addr_t\t\trx_ring_tieoff_dma;\n--\ndrivers/net/ethernet/cadence/macb.h-1313-\tunsigned int\t\tnum_queues;\ndrivers/net/ethernet/cadence/macb.h:1314:\tstruct macb_queue\tqueues[MACB_MAX_QUEUES];\ndrivers/net/ethernet/cadence/macb.h-1315-\n--\ndrivers/net/ethernet/cadence/macb.h-1326-\tunion {\ndrivers/net/ethernet/cadence/macb.h:1327:\t\tstruct macb_stats\tmacb;\ndrivers/net/ethernet/cadence/macb.h-1328-\t\tstruct gem_stats\tgem;\n--\ndrivers/net/ethernet/cadence/macb.h-1330-\ndrivers/net/ethernet/cadence/macb.h:1331:\tstruct macb_or_gem_ops\tmacbgem_ops;\ndrivers/net/ethernet/cadence/macb.h-1332-\n--\ndrivers/net/ethernet/cadence/macb.h-1344-\t/* AT91RM9200 transmit queue (1 on wire + 1 queued) */\ndrivers/net/ethernet/cadence/macb.h:1345:\tstruct macb_tx_skb\trm9200_txq[2];\ndrivers/net/ethernet/cadence/macb.h-1346-\tunsigned int\t\tmax_tx_length;\n--\ndrivers/net/ethernet/cadence/macb.h-1358-\ndrivers/net/ethernet/cadence/macb.h:1359:\tstruct macb_ptp_info\t*ptp_info;\t/* macb-ptp interface */\ndrivers/net/ethernet/cadence/macb.h-1360-\n--\ndrivers/net/ethernet/cadence/macb.h-1386-\ndrivers/net/ethernet/cadence/macb.h:1387:\tstruct macb_pm_data pm_data;\ndrivers/net/ethernet/cadence/macb.h:1388:\tconst struct macb_usrio_config *usrio;\ndrivers/net/ethernet/cadence/macb.h-1389-};\n--\ndrivers/net/ethernet/cadence/macb.h-1395-\ndrivers/net/ethernet/cadence/macb.h:1396:enum macb_bd_control {\ndrivers/net/ethernet/cadence/macb.h-1397-\tTSTAMP_DISABLED,\n--\ndrivers/net/ethernet/cadence/macb.h=1404=void gem_ptp_remove(struct net_device *netdev);\ndrivers/net/ethernet/cadence/macb.h:1405:void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);\ndrivers/net/ethernet/cadence/macb.h:1406:void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);\ndrivers/net/ethernet/cadence/macb.h:1407:static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)\ndrivers/net/ethernet/cadence/macb.h-1408-{\n--\ndrivers/net/ethernet/cadence/macb.h-1414-\ndrivers/net/ethernet/cadence/macb.h:1415:static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)\ndrivers/net/ethernet/cadence/macb.h-1416-{\n--\ndrivers/net/ethernet/cadence/macb.h=1430=static inline void gem_ptp_remove(struct net_device *netdev) { }\ndrivers/net/ethernet/cadence/macb.h-1431-\ndrivers/net/ethernet/cadence/macb.h:1432:static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }\ndrivers/net/ethernet/cadence/macb.h:1433:static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }\ndrivers/net/ethernet/cadence/macb.h-1434-#endif\ndrivers/net/ethernet/cadence/macb.h-1435-\ndrivers/net/ethernet/cadence/macb.h:1436:static inline bool macb_is_gem(struct macb *bp)\ndrivers/net/ethernet/cadence/macb.h-1437-{\n--\ndrivers/net/ethernet/cadence/macb.h=1453=static inline u64 enst_max_hw_interval(u32 speed_mbps)\n--\ndrivers/net/ethernet/cadence/macb.h-1458-\ndrivers/net/ethernet/cadence/macb.h:1459:static inline bool macb_dma64(struct macb *bp)\ndrivers/net/ethernet/cadence/macb.h-1460-{\n--\ndrivers/net/ethernet/cadence/macb.h-1464-\ndrivers/net/ethernet/cadence/macb.h:1465:static inline bool macb_dma_ptp(struct macb *bp)\ndrivers/net/ethernet/cadence/macb.h-1466-{\n--\ndrivers/net/ethernet/cadence/macb.h-1470-\ndrivers/net/ethernet/cadence/macb.h:1471:static inline void macb_queue_isr_clear(struct macb *bp,\ndrivers/net/ethernet/cadence/macb.h:1472:\t\t\t\t\tstruct macb_queue *queue, u32 value)\ndrivers/net/ethernet/cadence/macb.h-1473-{\n--\ndrivers/net/ethernet/cadence/macb.h-1478-/**\ndrivers/net/ethernet/cadence/macb.h:1479: * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration\ndrivers/net/ethernet/cadence/macb.h-1480- * @pclk:\t\tplatform clock\n--\ndrivers/net/ethernet/cadence/macb.h-1482- */\ndrivers/net/ethernet/cadence/macb.h:1483:struct macb_platform_data {\ndrivers/net/ethernet/cadence/macb.h-1484-\tstruct clk\t*pclk;\n--\ndrivers/net/ethernet/cadence/macb.h-1488-/**\ndrivers/net/ethernet/cadence/macb.h:1489: * struct macb_queue_enst_config - Configuration for Enhanced Scheduled Traffic\ndrivers/net/ethernet/cadence/macb.h-1490- * @start_time_mask:  Bitmask representing the start time for the queue\n--\ndrivers/net/ethernet/cadence/macb.h-1497- */\ndrivers/net/ethernet/cadence/macb.h:1498:struct macb_queue_enst_config {\ndrivers/net/ethernet/cadence/macb.h-1499-\tu32 start_time_mask;\n--\ndrivers/net/ethernet/cadence/macb_main.c-44-/* This structure is only used for MACB on SiFive FU540 devices */\ndrivers/net/ethernet/cadence/macb_main.c:45:struct sifive_fu540_macb_mgmt {\ndrivers/net/ethernet/cadence/macb_main.c-46-\tvoid __iomem *reg;\n--\ndrivers/net/ethernet/cadence/macb_main.c-128- */\ndrivers/net/ethernet/cadence/macb_main.c:129:static unsigned int macb_dma_desc_get_size(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_main.c-130-{\ndrivers/net/ethernet/cadence/macb_main.c:131:\tunsigned int desc_size = sizeof(struct macb_dma_desc);\ndrivers/net/ethernet/cadence/macb_main.c-132-\ndrivers/net/ethernet/cadence/macb_main.c:133:\tif (macb_dma64(bp))\ndrivers/net/ethernet/cadence/macb_main.c:134:\t\tdesc_size += sizeof(struct macb_dma_desc_64);\ndrivers/net/ethernet/cadence/macb_main.c:135:\tif (macb_dma_ptp(bp))\ndrivers/net/ethernet/cadence/macb_main.c:136:\t\tdesc_size += sizeof(struct macb_dma_desc_ptp);\ndrivers/net/ethernet/cadence/macb_main.c-137-\n--\ndrivers/net/ethernet/cadence/macb_main.c-140-\ndrivers/net/ethernet/cadence/macb_main.c:141:static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)\ndrivers/net/ethernet/cadence/macb_main.c-142-{\ndrivers/net/ethernet/cadence/macb_main.c:143:\treturn desc_idx * (1 + macb_dma64(bp) + macb_dma_ptp(bp));\ndrivers/net/ethernet/cadence/macb_main.c-144-}\ndrivers/net/ethernet/cadence/macb_main.c-145-\ndrivers/net/ethernet/cadence/macb_main.c:146:static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)\ndrivers/net/ethernet/cadence/macb_main.c-147-{\ndrivers/net/ethernet/cadence/macb_main.c:148:\treturn (struct macb_dma_desc_64 *)((void *)desc\ndrivers/net/ethernet/cadence/macb_main.c:149:\t\t+ sizeof(struct macb_dma_desc));\ndrivers/net/ethernet/cadence/macb_main.c-150-}\n--\ndrivers/net/ethernet/cadence/macb_main.c-152-/* Ring buffer accessors */\ndrivers/net/ethernet/cadence/macb_main.c:153:static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-154-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-157-\ndrivers/net/ethernet/cadence/macb_main.c:158:static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,\ndrivers/net/ethernet/cadence/macb_main.c-159-\t\t\t\t\t  unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-160-{\ndrivers/net/ethernet/cadence/macb_main.c:161:\tindex = macb_tx_ring_wrap(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c:162:\tindex = macb_adj_dma_desc_idx(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c-163-\treturn \u0026queue-\u003etx_ring[index];\n--\ndrivers/net/ethernet/cadence/macb_main.c-165-\ndrivers/net/ethernet/cadence/macb_main.c:166:static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,\ndrivers/net/ethernet/cadence/macb_main.c-167-\t\t\t\t       unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-168-{\ndrivers/net/ethernet/cadence/macb_main.c:169:\treturn \u0026queue-\u003etx_skb[macb_tx_ring_wrap(queue-\u003ebp, index)];\ndrivers/net/ethernet/cadence/macb_main.c-170-}\ndrivers/net/ethernet/cadence/macb_main.c-171-\ndrivers/net/ethernet/cadence/macb_main.c:172:static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-173-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-175-\ndrivers/net/ethernet/cadence/macb_main.c:176:\toffset = macb_tx_ring_wrap(queue-\u003ebp, index) *\ndrivers/net/ethernet/cadence/macb_main.c:177:\t\t\tmacb_dma_desc_get_size(queue-\u003ebp);\ndrivers/net/ethernet/cadence/macb_main.c-178-\n--\ndrivers/net/ethernet/cadence/macb_main.c-181-\ndrivers/net/ethernet/cadence/macb_main.c:182:static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-183-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-186-\ndrivers/net/ethernet/cadence/macb_main.c:187:static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-188-{\ndrivers/net/ethernet/cadence/macb_main.c:189:\tindex = macb_rx_ring_wrap(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c:190:\tindex = macb_adj_dma_desc_idx(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c-191-\treturn \u0026queue-\u003erx_ring[index];\n--\ndrivers/net/ethernet/cadence/macb_main.c-193-\ndrivers/net/ethernet/cadence/macb_main.c:194:static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)\ndrivers/net/ethernet/cadence/macb_main.c-195-{\ndrivers/net/ethernet/cadence/macb_main.c-196-\treturn queue-\u003erx_buffers + queue-\u003ebp-\u003erx_buffer_size *\ndrivers/net/ethernet/cadence/macb_main.c:197:\t       macb_rx_ring_wrap(queue-\u003ebp, index);\ndrivers/net/ethernet/cadence/macb_main.c-198-}\n--\ndrivers/net/ethernet/cadence/macb_main.c=238=static bool hw_is_gem(void __iomem *addr, bool native_io)\n--\ndrivers/net/ethernet/cadence/macb_main.c-249-\ndrivers/net/ethernet/cadence/macb_main.c:250:static void macb_set_hwaddr(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_main.c-251-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-255-\tbottom = get_unaligned_le32(bp-\u003enetdev-\u003edev_addr);\ndrivers/net/ethernet/cadence/macb_main.c:256:\tmacb_or_gem_writel(bp, SA1B, bottom);\ndrivers/net/ethernet/cadence/macb_main.c-257-\ttop = get_unaligned_le16(bp-\u003enetdev-\u003edev_addr + 4);\ndrivers/net/ethernet/cadence/macb_main.c:258:\tmacb_or_gem_writel(bp, SA1T, top);\ndrivers/net/ethernet/cadence/macb_main.c-259-\n--\ndrivers/net/ethernet/cadence/macb_main.c-265-\t/* Clear unused address register sets */\ndrivers/net/ethernet/cadence/macb_main.c:266:\tmacb_or_gem_writel(bp, SA2B, 0);\ndrivers/net/ethernet/cadence/macb_main.c:267:\tmacb_or_gem_writel(bp, SA2T, 0);\ndrivers/net/ethernet/cadence/macb_main.c:268:\tmacb_or_gem_writel(bp, SA3B, 0);\ndrivers/net/ethernet/cadence/macb_main.c:269:\tmacb_or_gem_writel(bp, SA3T, 0);\ndrivers/net/ethernet/cadence/macb_main.c:270:\tmacb_or_gem_writel(bp, SA4B, 0);\ndrivers/net/ethernet/cadence/macb_main.c:271:\tmacb_or_gem_writel(bp, SA4T, 0);\ndrivers/net/ethernet/cadence/macb_main.c-272-}\ndrivers/net/ethernet/cadence/macb_main.c-273-\ndrivers/net/ethernet/cadence/macb_main.c:274:static void macb_get_hwaddr(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_main.c-275-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-282-\tfor (i = 0; i \u003c 4; i++) {\ndrivers/net/ethernet/cadence/macb_main.c:283:\t\tbottom = macb_or_gem_readl(bp, SA1B + i * 8);\ndrivers/net/ethernet/cadence/macb_main.c:284:\t\ttop = macb_or_gem_readl(bp, SA1T + i * 8);\ndrivers/net/ethernet/cadence/macb_main.c-285-\n--\ndrivers/net/ethernet/cadence/macb_main.c-302-\ndrivers/net/ethernet/cadence/macb_main.c:303:static int macb_mdio_wait_for_idle(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_main.c-304-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-310-\ndrivers/net/ethernet/cadence/macb_main.c:311:static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)\ndrivers/net/ethernet/cadence/macb_main.c-312-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-319-\ndrivers/net/ethernet/cadence/macb_main.c:320:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-321-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-323-\ndrivers/net/ethernet/cadence/macb_main.c:324:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-325-\t\t\t      | MACB_BF(RW, MACB_MAN_C22_READ)\n--\ndrivers/net/ethernet/cadence/macb_main.c-329-\ndrivers/net/ethernet/cadence/macb_main.c:330:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-331-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-333-\ndrivers/net/ethernet/cadence/macb_main.c:334:\tstatus = MACB_BFEXT(DATA, macb_readl(bp, MAN));\ndrivers/net/ethernet/cadence/macb_main.c-335-\n--\ndrivers/net/ethernet/cadence/macb_main.c-341-\ndrivers/net/ethernet/cadence/macb_main.c:342:static int macb_mdio_read_c45(struct mii_bus *bus, int mii_id, int devad,\ndrivers/net/ethernet/cadence/macb_main.c-343-\t\t\t      int regnum)\n--\ndrivers/net/ethernet/cadence/macb_main.c-353-\ndrivers/net/ethernet/cadence/macb_main.c:354:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-355-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-357-\ndrivers/net/ethernet/cadence/macb_main.c:358:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-359-\t\t\t      | MACB_BF(RW, MACB_MAN_C45_ADDR)\n--\ndrivers/net/ethernet/cadence/macb_main.c-364-\ndrivers/net/ethernet/cadence/macb_main.c:365:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-366-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-368-\ndrivers/net/ethernet/cadence/macb_main.c:369:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-370-\t\t\t      | MACB_BF(RW, MACB_MAN_C45_READ)\n--\ndrivers/net/ethernet/cadence/macb_main.c-374-\ndrivers/net/ethernet/cadence/macb_main.c:375:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-376-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-378-\ndrivers/net/ethernet/cadence/macb_main.c:379:\tstatus = MACB_BFEXT(DATA, macb_readl(bp, MAN));\ndrivers/net/ethernet/cadence/macb_main.c-380-\n--\ndrivers/net/ethernet/cadence/macb_main.c-386-\ndrivers/net/ethernet/cadence/macb_main.c:387:static int macb_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,\ndrivers/net/ethernet/cadence/macb_main.c-388-\t\t\t       u16 value)\n--\ndrivers/net/ethernet/cadence/macb_main.c-396-\ndrivers/net/ethernet/cadence/macb_main.c:397:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-398-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-400-\ndrivers/net/ethernet/cadence/macb_main.c:401:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-402-\t\t\t      | MACB_BF(RW, MACB_MAN_C22_WRITE)\n--\ndrivers/net/ethernet/cadence/macb_main.c-407-\ndrivers/net/ethernet/cadence/macb_main.c:408:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-409-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-417-\ndrivers/net/ethernet/cadence/macb_main.c:418:static int macb_mdio_write_c45(struct mii_bus *bus, int mii_id,\ndrivers/net/ethernet/cadence/macb_main.c-419-\t\t\t       int devad, int regnum,\n--\ndrivers/net/ethernet/cadence/macb_main.c-430-\ndrivers/net/ethernet/cadence/macb_main.c:431:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-432-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-434-\ndrivers/net/ethernet/cadence/macb_main.c:435:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-436-\t\t\t      | MACB_BF(RW, MACB_MAN_C45_ADDR)\n--\ndrivers/net/ethernet/cadence/macb_main.c-441-\ndrivers/net/ethernet/cadence/macb_main.c:442:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-443-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-445-\ndrivers/net/ethernet/cadence/macb_main.c:446:\tmacb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)\ndrivers/net/ethernet/cadence/macb_main.c-447-\t\t\t      | MACB_BF(RW, MACB_MAN_C45_WRITE)\n--\ndrivers/net/ethernet/cadence/macb_main.c-452-\ndrivers/net/ethernet/cadence/macb_main.c:453:\tstatus = macb_mdio_wait_for_idle(bp);\ndrivers/net/ethernet/cadence/macb_main.c-454-\tif (status \u003c 0)\n--\ndrivers/net/ethernet/cadence/macb_main.c-462-\ndrivers/net/ethernet/cadence/macb_main.c:463:static void macb_init_buffers(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_main.c-464-{\ndrivers/net/ethernet/cadence/macb_main.c:465:\tstruct macb_queue *queue;\ndrivers/net/ethernet/cadence/macb_main.c-466-\tunsigned int q;\n--\ndrivers/net/ethernet/cadence/macb_main.c-468-\t/* Single register for all queues' high 32 bits. */\ndrivers/net/ethernet/cadence/macb_main.c:469:\tif (macb_dma64(bp)) {\ndrivers/net/ethernet/cadence/macb_main.c:470:\t\tmacb_writel(bp, RBQPH,\ndrivers/net/ethernet/cadence/macb_main.c-471-\t\t\t    upper_32_bits(bp-\u003equeues[0].rx_ring_dma));\ndrivers/net/ethernet/cadence/macb_main.c:472:\t\tmacb_writel(bp, TBQPH,\ndrivers/net/ethernet/cadence/macb_main.c-473-\t\t\t    upper_32_bits(bp-\u003equeues[0].tx_ring_dma));\n--\ndrivers/net/ethernet/cadence/macb_main.c-482-/**\ndrivers/net/ethernet/cadence/macb_main.c:483: * macb_set_tx_clk() - Set a clock to a new frequency\ndrivers/net/ethernet/cadence/macb_main.c-484- * @bp:\t\tpointer to struct macb\n--\ndrivers/net/ethernet/cadence/macb_main.c-486- */\ndrivers/net/ethernet/cadence/macb_main.c:487:static void macb_set_tx_clk(struct macb *bp, int speed)\ndrivers/net/ethernet/cadence/macb_main.c-488-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-519-\ndrivers/net/ethernet/cadence/macb_main.c:520:static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,\ndrivers/net/ethernet/cadence/macb_main.c-521-\t\t\t\t phy_interface_t interface, int speed,\n--\ndrivers/net/ethernet/cadence/macb_main.c-534-\ndrivers/net/ethernet/cadence/macb_main.c:535:static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,\ndrivers/net/ethernet/cadence/macb_main.c-536-\t\t\t\t   unsigned int neg_mode,\n--\ndrivers/net/ethernet/cadence/macb_main.c-552-\ndrivers/net/ethernet/cadence/macb_main.c:553:static int macb_usx_pcs_config(struct phylink_pcs *pcs,\ndrivers/net/ethernet/cadence/macb_main.c-554-\t\t\t       unsigned int neg_mode,\n--\ndrivers/net/ethernet/cadence/macb_main.c-566-\ndrivers/net/ethernet/cadence/macb_main.c:567:static unsigned int macb_pcs_inband_caps(struct phylink_pcs *pcs,\ndrivers/net/ethernet/cadence/macb_main.c-568-\t\t\t\t\t phy_interface_t interface)\n--\ndrivers/net/ethernet/cadence/macb_main.c-572-\ndrivers/net/ethernet/cadence/macb_main.c:573:static void macb_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,\ndrivers/net/ethernet/cadence/macb_main.c-574-\t\t\t       struct phylink_link_state *state)\n--\ndrivers/net/ethernet/cadence/macb_main.c-583-\ndrivers/net/ethernet/cadence/macb_main.c:584:static void macb_pcs_an_restart(struct phylink_pcs *pcs)\ndrivers/net/ethernet/cadence/macb_main.c-585-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-588-\ndrivers/net/ethernet/cadence/macb_main.c:589:static int macb_pcs_config(struct phylink_pcs *pcs,\ndrivers/net/ethernet/cadence/macb_main.c-590-\t\t\t   unsigned int neg_mode,\n--\ndrivers/net/ethernet/cadence/macb_main.c-604-\t * Must be written after PCSSEL is set in NCFGR which is done in\ndrivers/net/ethernet/cadence/macb_main.c:605:\t * macb_mac_config(), otherwise writes will not take effect.\ndrivers/net/ethernet/cadence/macb_main.c-606-\t */\n--\ndrivers/net/ethernet/cadence/macb_main.c-617-\ndrivers/net/ethernet/cadence/macb_main.c:618:static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {\ndrivers/net/ethernet/cadence/macb_main.c:619:\t.pcs_get_state = macb_usx_pcs_get_state,\ndrivers/net/ethernet/cadence/macb_main.c:620:\t.pcs_config = macb_usx_pcs_config,\ndrivers/net/ethernet/cadence/macb_main.c:621:\t.pcs_link_up = macb_usx_pcs_link_up,\ndrivers/net/ethernet/cadence/macb_main.c-622-};\ndrivers/net/ethernet/cadence/macb_main.c-623-\ndrivers/net/ethernet/cadence/macb_main.c:624:static const struct phylink_pcs_ops macb_phylink_pcs_ops = {\ndrivers/net/ethernet/cadence/macb_main.c:625:\t.pcs_inband_caps = macb_pcs_inband_caps,\ndrivers/net/ethernet/cadence/macb_main.c:626:\t.pcs_get_state = macb_pcs_get_state,\ndrivers/net/ethernet/cadence/macb_main.c:627:\t.pcs_an_restart = macb_pcs_an_restart,\ndrivers/net/ethernet/cadence/macb_main.c:628:\t.pcs_config = macb_pcs_config,\ndrivers/net/ethernet/cadence/macb_main.c-629-};\ndrivers/net/ethernet/cadence/macb_main.c-630-\ndrivers/net/ethernet/cadence/macb_main.c:631:static bool macb_tx_lpi_set(struct macb *bp, bool enable)\ndrivers/net/ethernet/cadence/macb_main.c-632-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-636-\ndrivers/net/ethernet/cadence/macb_main.c:637:\tncr = macb_readl(bp, NCR);\ndrivers/net/ethernet/cadence/macb_main.c-638-\told = ncr;\n--\ndrivers/net/ethernet/cadence/macb_main.c-643-\tif (old != ncr)\ndrivers/net/ethernet/cadence/macb_main.c:644:\t\tmacb_writel(bp, NCR, ncr);\ndrivers/net/ethernet/cadence/macb_main.c-645-\n--\ndrivers/net/ethernet/cadence/macb_main.c-648-\ndrivers/net/ethernet/cadence/macb_main.c:649:static bool macb_tx_all_queues_idle(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_main.c-650-{\ndrivers/net/ethernet/cadence/macb_main.c:651:\tstruct macb_queue *queue;\ndrivers/net/ethernet/cadence/macb_main.c-652-\tunsigned int q;\n--\ndrivers/net/ethernet/cadence/macb_main.c-660-\ndrivers/net/ethernet/cadence/macb_main.c:661:static void macb_tx_lpi_work_fn(struct work_struct *work)\ndrivers/net/ethernet/cadence/macb_main.c-662-{\n--\ndrivers/net/ethernet/cadence/macb_main.c-666-\tspin_lock_irqsave(\u0026bp-\u003elock, flags);\ndrivers/net/ethernet/cadence/macb_main.c:667:\tif (bp-\u003eeee_active \u0026\u0026 macb_tx_all_queues_idle(bp))\ndrivers/net/ethernet/cadence/macb_main.c:668:\t\tmacb_tx_lpi_set(bp, true);\ndrivers/net/ethernet/cadence/macb_main.c-669-\tspin_unlock_irqrestore(\u0026bp-\u003elock, flags);\n--\ndrivers/net/ethernet/cadence/macb_main.c-671-\ndrivers/net/ethernet/cadence/macb_main.c:672:static void macb_tx_lpi_schedule(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_main.c-673-{\n\n"
}

							input: 44372
							output: 35
							thoughts: 40

Here's my summary, as though I'm thinking through this process:

**Tracing the PTP Initialization**

Okay, so I'm digging into how Precision Time Protocol (PTP) is initialized within this driver. The initial clue is that `gem_ptp_init` gets called, and from what I remember, I believe it's happening within `macb_main.c`. Now, the next logical step is to pinpoint *exactly* where that function call lives within the code. Let's fire up the search tools and see what we can find. I need to understand the call stack and how this PTP initialization fits into the overall MACB driver's startup sequence. That will tell me everything I need to know about the device.

{
  "Expression": "gem_ptp_init",
  "PathPrefix": "drivers/net/ethernet/cadence"
}

{
  "Output": "drivers/net/ethernet/cadence/macb.h=1396=enum macb_bd_control {\n--\ndrivers/net/ethernet/cadence/macb.h-1402-\ndrivers/net/ethernet/cadence/macb.h:1403:void gem_ptp_init(struct net_device *netdev);\ndrivers/net/ethernet/cadence/macb.h-1404-void gem_ptp_remove(struct net_device *netdev);\n--\ndrivers/net/ethernet/cadence/macb.h=1425=int gem_set_hwtst(struct net_device *netdev,\n--\ndrivers/net/ethernet/cadence/macb.h-1428-#else\ndrivers/net/ethernet/cadence/macb.h:1429:static inline void gem_ptp_init(struct net_device *netdev) { }\ndrivers/net/ethernet/cadence/macb.h-1430-static inline void gem_ptp_remove(struct net_device *netdev) { }\n--\ndrivers/net/ethernet/cadence/macb_main.c=3775=static struct macb_ptp_info gem_ptp_info = {\ndrivers/net/ethernet/cadence/macb_main.c:3776:\t.ptp_init\t = gem_ptp_init,\ndrivers/net/ethernet/cadence/macb_main.c-3777-\t.ptp_remove\t = gem_ptp_remove,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=191=static const struct ptp_clock_info gem_ptp_caps_template = {\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-206-\ndrivers/net/ethernet/cadence/macb_ptp.c:207:static void gem_ptp_init_timer(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_ptp.c-208-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-221-\ndrivers/net/ethernet/cadence/macb_ptp.c:222:static void gem_ptp_init_tsu(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_ptp.c-223-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=297=void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-326-\ndrivers/net/ethernet/cadence/macb_ptp.c:327:void gem_ptp_init(struct net_device *netdev)\ndrivers/net/ethernet/cadence/macb_ptp.c-328-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-337-\tbp-\u003eptp_clock_info.max_adj = bp-\u003eptp_info-\u003eget_ptp_max_adj();\ndrivers/net/ethernet/cadence/macb_ptp.c:338:\tgem_ptp_init_timer(bp);\ndrivers/net/ethernet/cadence/macb_ptp.c-339-\tbp-\u003eptp_clock = ptp_clock_register(\u0026bp-\u003eptp_clock_info, \u0026netdev-\u003edev);\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-349-\ndrivers/net/ethernet/cadence/macb_ptp.c:350:\tgem_ptp_init_tsu(bp);\ndrivers/net/ethernet/cadence/macb_ptp.c-351-\n"
}

							input: 45591
							output: 33
							thoughts: 29

Okay, here's my take on those thoughts, tailored for an expert audience:

**Tracing the PTP Initialization in macb_main.c**

Alright, let's dive into this. I need to understand how the PTP initialization routine, specifically `gem_ptp_info.ptp_init`, is being called within `macb_main.c`. My immediate thought is to track down the callers – which other functions within that file are invoking `gem_ptp_info.ptp_init`? This is the crucial starting point for understanding the overall initialization sequence and the role of PTP within the broader MACB driver context. I'll need to use my usual methods, likely a combination of static analysis (grepping or using an IDE's cross-referencing capabilities) and perhaps even some dynamic tracing if the static analysis proves insufficient or if I suspect conditional calls that are not immediately obvious from the source code. The goal is a clear understanding of the initialization flow.

{
  "Expression": "ptp_init",
  "PathPrefix": "drivers/net/ethernet/cadence"
}

{
  "Output": "drivers/net/ethernet/cadence/macb.h=1203=struct macb_ptp_info {\ndrivers/net/ethernet/cadence/macb.h:1204:\tvoid (*ptp_init)(struct net_device *netdev);\ndrivers/net/ethernet/cadence/macb.h-1205-\tvoid (*ptp_remove)(struct net_device *netdev);\n--\ndrivers/net/ethernet/cadence/macb.h=1396=enum macb_bd_control {\n--\ndrivers/net/ethernet/cadence/macb.h-1402-\ndrivers/net/ethernet/cadence/macb.h:1403:void gem_ptp_init(struct net_device *netdev);\ndrivers/net/ethernet/cadence/macb.h-1404-void gem_ptp_remove(struct net_device *netdev);\n--\ndrivers/net/ethernet/cadence/macb.h=1425=int gem_set_hwtst(struct net_device *netdev,\n--\ndrivers/net/ethernet/cadence/macb.h-1428-#else\ndrivers/net/ethernet/cadence/macb.h:1429:static inline void gem_ptp_init(struct net_device *netdev) { }\ndrivers/net/ethernet/cadence/macb.h-1430-static inline void gem_ptp_remove(struct net_device *netdev) { }\n--\ndrivers/net/ethernet/cadence/macb_main.c=3129=static int macb_open(struct net_device *netdev)\n--\ndrivers/net/ethernet/cadence/macb_main.c-3177-\tif (bp-\u003eptp_info)\ndrivers/net/ethernet/cadence/macb_main.c:3178:\t\tbp-\u003eptp_info-\u003eptp_init(netdev);\ndrivers/net/ethernet/cadence/macb_main.c-3179-\n--\ndrivers/net/ethernet/cadence/macb_main.c=3775=static struct macb_ptp_info gem_ptp_info = {\ndrivers/net/ethernet/cadence/macb_main.c:3776:\t.ptp_init\t = gem_ptp_init,\ndrivers/net/ethernet/cadence/macb_main.c-3777-\t.ptp_remove\t = gem_ptp_remove,\n--\ndrivers/net/ethernet/cadence/macb_main.c=6133=static int __maybe_unused macb_resume(struct device *dev)\n--\ndrivers/net/ethernet/cadence/macb_main.c-6207-\tif (bp-\u003eptp_info)\ndrivers/net/ethernet/cadence/macb_main.c:6208:\t\tbp-\u003eptp_info-\u003eptp_init(netdev);\ndrivers/net/ethernet/cadence/macb_main.c-6209-\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=191=static const struct ptp_clock_info gem_ptp_caps_template = {\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-206-\ndrivers/net/ethernet/cadence/macb_ptp.c:207:static void gem_ptp_init_timer(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_ptp.c-208-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-221-\ndrivers/net/ethernet/cadence/macb_ptp.c:222:static void gem_ptp_init_tsu(struct macb *bp)\ndrivers/net/ethernet/cadence/macb_ptp.c-223-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c=297=void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb,\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-326-\ndrivers/net/ethernet/cadence/macb_ptp.c:327:void gem_ptp_init(struct net_device *netdev)\ndrivers/net/ethernet/cadence/macb_ptp.c-328-{\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-337-\tbp-\u003eptp_clock_info.max_adj = bp-\u003eptp_info-\u003eget_ptp_max_adj();\ndrivers/net/ethernet/cadence/macb_ptp.c:338:\tgem_ptp_init_timer(bp);\ndrivers/net/ethernet/cadence/macb_ptp.c-339-\tbp-\u003eptp_clock = ptp_clock_register(\u0026bp-\u003eptp_clock_info, \u0026netdev-\u003edev);\n--\ndrivers/net/ethernet/cadence/macb_ptp.c-349-\ndrivers/net/ethernet/cadence/macb_ptp.c:350:\tgem_ptp_init_tsu(bp);\ndrivers/net/ethernet/cadence/macb_ptp.c-351-\n"
}

							input: 47227
							output: 158
							thoughts: 1377

**WorthFuzzing Assessment: Cadence MACB/GEM Driver**

Okay, let's break this down. First, `gem_ptp_init` is called by `macb_open`, which is `ndo_open`, got it. Now, the key question is whether this Cadence MACB driver can be instantiated in standard QEMU or GCE fuzzing environments. We need to be meticulous. Let's revisit the rules. The criteria stipulate that we return `WorthFuzzing=false` if the patch concerns modifications to documentation, Kconfig, comments, cosmetic changes, non-functional numeric constants/macros, or unreachable code paths in standard virtualized environments. Specifically, the rules exclude code paths that are inaccessible in QEMU/GCE, even with software-emulated hardware. This also applies to vendor-specific PCIe switch, SmartNIC, or GPU drivers requiring physical PCIe hardware not emulated in standard QEMU. Finally, teardown callbacks are also uninteresting in this context.

Right, so, is the Cadence MACB/GEM a hardware-specific SoC/PCI driver not reachable in standard virtualized environments? Let's check. How is Cadence MACB probed? It's probed via DT (Device Tree) with compatible strings like `cdns,at91sam9260-macb`, `cdns,macb`, `cdns,gem`, `xlnx,zynq-gem`, `sifive,fu540-c000-gem`, and also via PCI with ID 0x17cd:0xe007 (Cadence PCI GEM). Now, is this Cadence GEM emulated in standard QEMU x86_64 or ARM64 virt machines? No! Standard QEMU x86_64 uses e1000, e1000e, rtl8139, virtio-net-pci, etc., and standard ARM64 virt uses virtio-net-pci. Cadence GEM in QEMU is only available if running specific machine boards like `xlnx-zcu102`, `zynq-a9`, or `sifive_u`. GCE or standard QEMU (x86_64 or ARM64 virt) do not offer Cadence GEM hardware or PCI devices.

Okay, what about syzkaller? Can syzkaller run on instances testing these drivers? Standard Linux fuzzing in syzkaller is x86_64 and arm64 virt. The rules are clear: code paths that are impossible to reach in virtualized environments like GCE or QEMU are excluded, along with vendor-specific PCIe switch, SmartNIC, or GPU drivers requiring physical PCIe hardware.

So, `drivers/net/ethernet/cadence/`... Is Cadence MACB a vendor-specific hardware driver? Yes! It's an Ethernet MAC driver for Cadence IP found on Atmel/Microchip AT91/SAMA5, Xilinx Zynq, SiFive FU540, and Cadence's internal PCI FPGA prototype board. It's unreachable without that specific physical hardware or specialized embedded SoC emulation. There's no software device/mock/virtual device or USB interface that uses macb. MACB is purely an MMIO platform driver or a CDNS PCI wrapper for the Cadence IP core. It's inaccessible in standard fuzzing environments.

Let's confirm the `WorthFuzzing` should be false based on the criteria: "Return WorthFuzzing=false if... code paths that are impossible to reach in virtualized environments like GCE or QEMU... Code in vendor-specific PCIe switch, SmartNIC, or GPU drivers that require physical PCIe hardware cards not emulated in standard QEMU."

Indeed, the Cadence MACB / GEM ethernet driver (`drivers/net/ethernet/cadence/macb_ptp.c`) requires specific physical hardware (Atmel / Microchip SoC, Xilinx Zynq, SiFive RISC-V SoC, or Cadence PCI FPGA test device) that is not available or emulated in standard virtualized fuzzing environments (QEMU virt/GCE).

Therefore, the conclusion is: `WorthFuzzing = false`. `EnableConfigs = []`. `FocusSymbols = []`. The reasoning: The patch fixes the initialization order of the spinlock `tsu_clk_lock` in `gem_ptp_init` within the Cadence MACB/GEM network driver. This driver targets embedded SoCs (Atmel/Microchip, Xilinx Zynq, SiFive) and Cadence PCI test hardware that are not present in standard virtualized fuzzing environments like QEMU virt/GCE.

Quick

{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch fixes the initialization order of `bp-\u003etsu_clk_lock` before registering the PTP clock in `gem_ptp_init()` for the Cadence MACB/GEM network driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver is for hardware-specific Cadence Ethernet MAC IP on embedded SoCs (such as Atmel/Microchip, Xilinx Zynq, SiFive) or proprietary PCI test cards, which are not present in standard virtualized fuzzing environments (e.g. QEMU standard virt / GCE).",
  "WorthFuzzing": false
}

{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch fixes the initialization order of `bp-\u003etsu_clk_lock` before registering the PTP clock in `gem_ptp_init()` for the Cadence MACB/GEM network driver (drivers/net/ethernet/cadence/macb_ptp.c). This driver is for hardware-specific Cadence Ethernet MAC IP on embedded SoCs (such as Atmel/Microchip, Xilinx Zynq, SiFive) or proprietary PCI test cards, which are not present in standard virtualized fuzzing environments (e.g. QEMU standard virt / GCE).",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

LLM Calls Summary:
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Tool Calls Summary:
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