AI Trajectory

null

{
  "EnableConfigs": [
    "AIR_EN8811H_PHY"
  ],
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies `air_write_buf` in `drivers/net/phy/air_en8811h.c`, which is a driver for the Airoha EN8811H and AN8811HB 2.5G Ethernet PHYs. This driver requires physical Airoha PHY hardware connected via MDIO, which is not emulated in standard virtualized fuzzing environments (QEMU/GCE). Therefore, the modified code is structurally unreachable.",
  "WorthFuzzing": false
}

null

{
  "PatchDiff": "commit c411ac84d7cb9d4609207dfcc05924d272afdcce\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Fri Sep 4 18:46:22 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c\nindex 0eeb7b9a4e260..34d2727e8222b 100644\n--- a/drivers/net/phy/air_en8811h.c\n+++ b/drivers/net/phy/air_en8811h.c\n@@ -312,6 +312,12 @@ static int air_write_buf(struct phy_device *phydev, u32 address,\n \tint saved_page;\n \tint ret = 0;\n \n+\tif (fw-\u003esize % 4) {\n+\t\tphydev_err(phydev, \"firmware size %zu is not a multiple of 4\\n\",\n+\t\t\t   fw-\u003esize);\n+\t\treturn -EINVAL;\n+\t}\n+\n \tsaved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);\n \n \tif (saved_page \u003e= 0) {\n"
}

core

null

{
  "EnableConfigs": [
    "AIR_EN8811H_PHY"
  ],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies `air_write_buf` in `drivers/net/phy/air_en8811h.c`, which is a driver for the Airoha EN8811H and AN8811HB 2.5G Ethernet PHYs. This driver requires physical Airoha PHY hardware connected via MDIO, which is not emulated in standard virtualized fuzzing environments (QEMU/GCE). Therefore, the modified code is structurally unreachable.",
  "WorthFuzzing": false
}

You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Target architecture: amd64

For your convenience, here is the diff of the changes:
commit c411ac84d7cb9d4609207dfcc05924d272afdcce
Author: syz-cluster <triage@syzkaller.com>
Date:   Fri Sep 4 18:46:22 2026 +0000

    syz-cluster: applied patch under review

diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 0eeb7b9a4e260..34d2727e8222b 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -312,6 +312,12 @@ static int air_write_buf(struct phy_device *phydev, u32 address,
 	int saved_page;
 	int ret = 0;
 
+	if (fw->size % 4) {
+		phydev_err(phydev, "firmware size %zu is not a multiple of 4\n",
+			   fw->size);
+		return -EINVAL;
+	}
+
 	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
 
 	if (saved_page >= 0) {

gemini-3.7-flash

null

null

							input: 2933
							output: 69
							thoughts: 123
						

**Analyzing a Network PHY Driver Patch**

Okay, so the patch is touching `drivers/net/phy/air_en8811h.c`. My first thought is, "What's this driver about?" I need to quickly understand what the `air_en8811h.c` driver is responsible for. Is it a common or niche PHY? Is it for a specific type of network interface?

I need to quickly figure out if this is something I can actually *test* effectively within my existing fuzzing setup. Is this accessible within QEMU or Google Compute Engine? Does it require some specialized hardware like an MDIO bus or a specific Ethernet PHY that I'd need to simulate or acquire physically? That's a critical first step.

Alright, time to get to work. I'll use either `read-file` or `grepper` to dive into the code itself, and importantly, its Kconfig entry. The Kconfig will tell me how this driver is configured, its dependencies, and any relevant options. That should give me the clues I need to determine its reachability and potential impact.

{
  "Expression": "AIR_",
  "PathPrefix": "drivers/net/phy"
}

{
  "Output": "\nFull output is too long, showing 500 out of 1134 lines.\nUse more precise expression if possible.\n\ndrivers/net/phy/Kconfig=81=config AS21XXX_PHY\n--\ndrivers/net/phy/Kconfig-92-\ndrivers/net/phy/Kconfig:93:config AIR_AN8801_PHY\ndrivers/net/phy/Kconfig-94-\ttristate \"Airoha AN8801 Gigabit PHY\"\ndrivers/net/phy/Kconfig:95:\tselect AIR_NET_PHYLIB\ndrivers/net/phy/Kconfig-96-\thelp\n--\ndrivers/net/phy/Kconfig-98-\ndrivers/net/phy/Kconfig:99:config AIR_EN8811H_PHY\ndrivers/net/phy/Kconfig-100-\ttristate \"Airoha EN8811H 2.5 Gigabit PHY\"\ndrivers/net/phy/Kconfig:101:\tselect AIR_NET_PHYLIB\ndrivers/net/phy/Kconfig-102-\tselect PHY_COMMON_PROPS\n--\ndrivers/net/phy/Kconfig-105-\ndrivers/net/phy/Kconfig:106:config AIR_NET_PHYLIB\ndrivers/net/phy/Kconfig-107-\ttristate\n--\ndrivers/net/phy/Makefile=32=obj-$(CONFIG_ADIN1140_PHY)\t+= adin1140-phy.o\ndrivers/net/phy/Makefile:33:obj-$(CONFIG_AIR_AN8801_PHY)\t+= air_an8801.o\ndrivers/net/phy/Makefile:34:obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o\ndrivers/net/phy/Makefile:35:obj-$(CONFIG_AIR_NET_PHYLIB)\t+= air_phy_lib.o\ndrivers/net/phy/Makefile-36-obj-$(CONFIG_AMD_PHY)\t\t+= amd.o\n--\ndrivers/net/phy/adin.c-61-#define ADIN1300_PHY_STATUS1\t\t\t0x001a\ndrivers/net/phy/adin.c:62:#define   ADIN1300_PAIR_01_SWAP\t\t\tBIT(11)\ndrivers/net/phy/adin.c-63-\n--\ndrivers/net/phy/adin.c=743=static int adin_mdix_update(struct phy_device *phydev)\n--\ndrivers/net/phy/adin.c-773-\ndrivers/net/phy/adin.c:774:\tswapped = !!(reg \u0026 ADIN1300_PAIR_01_SWAP);\ndrivers/net/phy/adin.c-775-\n--\ndrivers/net/phy/adin.c=977=static int adin_cable_test_report(struct phy_device *phydev)\n--\ndrivers/net/phy/adin.c-981-\ndrivers/net/phy/adin.c:982:\tfor (pair = ETHTOOL_A_CABLE_PAIR_A; pair \u003c= ETHTOOL_A_CABLE_PAIR_D; pair++) {\ndrivers/net/phy/adin.c-983-\t\tret = adin_cable_test_report_pair(phydev, pair);\n--\ndrivers/net/phy/air_an8801.c-124-/* MDIO_MMD_VEND1 Registers */\ndrivers/net/phy/air_an8801.c:125:#define AN8801_PHY_TX_PAIR_DLY_SEL_GBE\t0x13\ndrivers/net/phy/air_an8801.c:126:#define   AN8801_PHY_PAIR_DLY_SEL_A_GBE\tGENMASK(14, 12)\ndrivers/net/phy/air_an8801.c:127:#define   AN8801_PHY_PAIR_DLY_SEL_B_GBE\tGENMASK(10, 8)\ndrivers/net/phy/air_an8801.c:128:#define   AN8801_PHY_PAIR_DLY_SEL_C_GBE\tGENMASK(6, 4)\ndrivers/net/phy/air_an8801.c:129:#define   AN8801_PHY_PAIR_DLY_SEL_D_GBE\tGENMASK(2, 0)\ndrivers/net/phy/air_an8801.c-130-#define AN8801_PHY_RXADC_CTRL\t\t0xd8\n--\ndrivers/net/phy/air_an8801.c=902=static int an8801r_config_init(struct phy_device *phydev)\n--\ndrivers/net/phy/air_an8801.c-924-\t */\ndrivers/net/phy/air_an8801.c:925:\tret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1,\ndrivers/net/phy/air_an8801.c-926-\t\t\t      AN8801_EXT_REG_PHY,\n--\ndrivers/net/phy/air_an8801.c-958-\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1,\ndrivers/net/phy/air_an8801.c:959:\t\t\t    AN8801_PHY_TX_PAIR_DLY_SEL_GBE,\ndrivers/net/phy/air_an8801.c:960:\t\t\t    FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_A_GBE, 4) |\ndrivers/net/phy/air_an8801.c:961:\t\t\t    FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_C_GBE, 4));\ndrivers/net/phy/air_an8801.c-962-\tif (ret)\n--\ndrivers/net/phy/air_en8811h.c-34-\ndrivers/net/phy/air_en8811h.c:35:#define AIR_FW_ADDR_DM\t0x00000000\ndrivers/net/phy/air_en8811h.c:36:#define AIR_FW_ADDR_DSP\t0x00100000\ndrivers/net/phy/air_en8811h.c-37-\ndrivers/net/phy/air_en8811h.c-38-/* MII Registers */\ndrivers/net/phy/air_en8811h.c:39:#define AIR_AUX_CTRL_STATUS\t\t0x1d\ndrivers/net/phy/air_en8811h.c:40:#define   AIR_AUX_CTRL_STATUS_SPEED_MASK\tGENMASK(4, 2)\ndrivers/net/phy/air_en8811h.c:41:#define   AIR_AUX_CTRL_STATUS_SPEED_10\t\t0x0\ndrivers/net/phy/air_en8811h.c:42:#define   AIR_AUX_CTRL_STATUS_SPEED_100\t\t0x4\ndrivers/net/phy/air_en8811h.c:43:#define   AIR_AUX_CTRL_STATUS_SPEED_1000\t0x8\ndrivers/net/phy/air_en8811h.c:44:#define   AIR_AUX_CTRL_STATUS_SPEED_2500\t0xc\ndrivers/net/phy/air_en8811h.c-45-\n--\ndrivers/net/phy/air_en8811h.c-49-\ndrivers/net/phy/air_en8811h.c:50:#define AIR_PHY_MCU_CMD_0\t\t0x800b\ndrivers/net/phy/air_en8811h.c:51:#define AIR_PHY_MCU_CMD_1\t\t0x800c\ndrivers/net/phy/air_en8811h.c:52:#define AIR_PHY_MCU_CMD_1_MODE1\t\t\t0x0\ndrivers/net/phy/air_en8811h.c:53:#define AIR_PHY_MCU_CMD_2\t\t0x800d\ndrivers/net/phy/air_en8811h.c:54:#define AIR_PHY_MCU_CMD_2_MODE1\t\t\t0x0\ndrivers/net/phy/air_en8811h.c:55:#define AIR_PHY_MCU_CMD_3\t\t0x800e\ndrivers/net/phy/air_en8811h.c:56:#define AIR_PHY_MCU_CMD_3_MODE1\t\t\t0x1101\ndrivers/net/phy/air_en8811h.c:57:#define AIR_PHY_MCU_CMD_3_DOCMD\t\t\t0x1100\ndrivers/net/phy/air_en8811h.c:58:#define AIR_PHY_MCU_CMD_4\t\t0x800f\ndrivers/net/phy/air_en8811h.c:59:#define AIR_PHY_MCU_CMD_4_MODE1\t\t\t0x0002\ndrivers/net/phy/air_en8811h.c:60:#define AIR_PHY_MCU_CMD_4_CABLE_PAIR_A\t\t0x00d7\ndrivers/net/phy/air_en8811h.c:61:#define AIR_PHY_MCU_CMD_4_CABLE_PAIR_B\t\t0x00d8\ndrivers/net/phy/air_en8811h.c:62:#define AIR_PHY_MCU_CMD_4_CABLE_PAIR_C\t\t0x00d9\ndrivers/net/phy/air_en8811h.c:63:#define AIR_PHY_MCU_CMD_4_CABLE_PAIR_D\t\t0x00da\ndrivers/net/phy/air_en8811h.c:64:#define AIR_PHY_MCU_CMD_4_INTCLR\t\t0x00e4\ndrivers/net/phy/air_en8811h.c-65-\ndrivers/net/phy/air_en8811h.c-66-/* Registers on MDIO_MMD_VEND2 */\ndrivers/net/phy/air_en8811h.c:67:#define AIR_PHY_LED_BCR\t\t\t0x021\ndrivers/net/phy/air_en8811h.c:68:#define   AIR_PHY_LED_BCR_MODE_MASK\t\tGENMASK(1, 0)\ndrivers/net/phy/air_en8811h.c:69:#define   AIR_PHY_LED_BCR_TIME_TEST\t\tBIT(2)\ndrivers/net/phy/air_en8811h.c:70:#define   AIR_PHY_LED_BCR_CLK_EN\t\tBIT(3)\ndrivers/net/phy/air_en8811h.c:71:#define   AIR_PHY_LED_BCR_EXT_CTRL\t\tBIT(15)\ndrivers/net/phy/air_en8811h.c-72-\ndrivers/net/phy/air_en8811h.c:73:#define AIR_PHY_LED_DUR_ON\t\t0x022\ndrivers/net/phy/air_en8811h.c-74-\ndrivers/net/phy/air_en8811h.c:75:#define AIR_PHY_LED_DUR_BLINK\t\t0x023\ndrivers/net/phy/air_en8811h.c-76-\ndrivers/net/phy/air_en8811h.c:77:#define AIR_PHY_LED_ON(i)\t       (0x024 + ((i) * 2))\ndrivers/net/phy/air_en8811h.c:78:#define   AIR_PHY_LED_ON_MASK\t\t\t(GENMASK(6, 0) | BIT(8))\ndrivers/net/phy/air_en8811h.c:79:#define   AIR_PHY_LED_ON_LINK1000\t\tBIT(0)\ndrivers/net/phy/air_en8811h.c:80:#define   AIR_PHY_LED_ON_LINK100\t\tBIT(1)\ndrivers/net/phy/air_en8811h.c:81:#define   AIR_PHY_LED_ON_LINK10\t\t\tBIT(2)\ndrivers/net/phy/air_en8811h.c:82:#define   AIR_PHY_LED_ON_LINKDOWN\t\tBIT(3)\ndrivers/net/phy/air_en8811h.c:83:#define   AIR_PHY_LED_ON_FDX\t\t\tBIT(4) /* Full duplex */\ndrivers/net/phy/air_en8811h.c:84:#define   AIR_PHY_LED_ON_HDX\t\t\tBIT(5) /* Half duplex */\ndrivers/net/phy/air_en8811h.c:85:#define   AIR_PHY_LED_ON_FORCE_ON\t\tBIT(6)\ndrivers/net/phy/air_en8811h.c:86:#define   AIR_PHY_LED_ON_LINK2500\t\tBIT(8)\ndrivers/net/phy/air_en8811h.c:87:#define   AIR_PHY_LED_ON_POLARITY\t\tBIT(14)\ndrivers/net/phy/air_en8811h.c:88:#define   AIR_PHY_LED_ON_ENABLE\t\t\tBIT(15)\ndrivers/net/phy/air_en8811h.c-89-\ndrivers/net/phy/air_en8811h.c:90:#define AIR_PHY_LED_BLINK(i)\t       (0x025 + ((i) * 2))\ndrivers/net/phy/air_en8811h.c:91:#define   AIR_PHY_LED_BLINK_1000TX\t\tBIT(0)\ndrivers/net/phy/air_en8811h.c:92:#define   AIR_PHY_LED_BLINK_1000RX\t\tBIT(1)\ndrivers/net/phy/air_en8811h.c:93:#define   AIR_PHY_LED_BLINK_100TX\t\tBIT(2)\ndrivers/net/phy/air_en8811h.c:94:#define   AIR_PHY_LED_BLINK_100RX\t\tBIT(3)\ndrivers/net/phy/air_en8811h.c:95:#define   AIR_PHY_LED_BLINK_10TX\t\tBIT(4)\ndrivers/net/phy/air_en8811h.c:96:#define   AIR_PHY_LED_BLINK_10RX\t\tBIT(5)\ndrivers/net/phy/air_en8811h.c:97:#define   AIR_PHY_LED_BLINK_COLLISION\t\tBIT(6)\ndrivers/net/phy/air_en8811h.c:98:#define   AIR_PHY_LED_BLINK_RX_CRC_ERR\t\tBIT(7)\ndrivers/net/phy/air_en8811h.c:99:#define   AIR_PHY_LED_BLINK_RX_IDLE_ERR\t\tBIT(8)\ndrivers/net/phy/air_en8811h.c:100:#define   AIR_PHY_LED_BLINK_FORCE_BLINK\t\tBIT(9)\ndrivers/net/phy/air_en8811h.c:101:#define   AIR_PHY_LED_BLINK_2500TX\t\tBIT(10)\ndrivers/net/phy/air_en8811h.c:102:#define   AIR_PHY_LED_BLINK_2500RX\t\tBIT(11)\ndrivers/net/phy/air_en8811h.c-103-\ndrivers/net/phy/air_en8811h.c-104-/* Registers on BUCKPBUS */\ndrivers/net/phy/air_en8811h.c:105:#define AIR_PHY_CONTROL\t\t\t0x3a9c\ndrivers/net/phy/air_en8811h.c:106:#define   AIR_PHY_CONTROL_INTERNAL\t\tBIT(11)\ndrivers/net/phy/air_en8811h.c-107-\n--\ndrivers/net/phy/air_en8811h.c-165-/* MII register constants for PBUS access (PHY addr + 8) */\ndrivers/net/phy/air_en8811h.c:166:#define AIR_PBUS_ADDR_HIGH\t\t0x1c\ndrivers/net/phy/air_en8811h.c:167:#define AIR_PBUS_DATA_HIGH\t\t0x10\ndrivers/net/phy/air_en8811h.c:168:#define AIR_PBUS_REG_ADDR_HIGH_MASK\tGENMASK(15, 6)\ndrivers/net/phy/air_en8811h.c:169:#define AIR_PBUS_REG_ADDR_LOW_MASK\tGENMASK(5, 2)\ndrivers/net/phy/air_en8811h.c-170-\n--\ndrivers/net/phy/air_en8811h.c-180- */\ndrivers/net/phy/air_en8811h.c:181:#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK)      | \\\ndrivers/net/phy/air_en8811h.c-182-\t\t\t\t  BIT(TRIGGER_NETDEV_RX)        | \\\ndrivers/net/phy/air_en8811h.c-183-\t\t\t\t  BIT(TRIGGER_NETDEV_TX))\ndrivers/net/phy/air_en8811h.c:184:#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \\\ndrivers/net/phy/air_en8811h.c-185-\t\t\t\t  BIT(TRIGGER_NETDEV_LINK_1000))\ndrivers/net/phy/air_en8811h.c:186:#define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \\\ndrivers/net/phy/air_en8811h.c-187-\t\t\t\t  BIT(TRIGGER_NETDEV_LINK_100))\n--\ndrivers/net/phy/air_en8811h.c=207=enum {\ndrivers/net/phy/air_en8811h.c:208:\tAIR_PHY_LED_STATE_FORCE_ON,\ndrivers/net/phy/air_en8811h.c:209:\tAIR_PHY_LED_STATE_FORCE_BLINK,\ndrivers/net/phy/air_en8811h.c-210-};\n--\ndrivers/net/phy/air_en8811h.c=212=enum {\ndrivers/net/phy/air_en8811h.c:213:\tAIR_PHY_LED_DUR_BLINK_32MS,\ndrivers/net/phy/air_en8811h.c:214:\tAIR_PHY_LED_DUR_BLINK_64MS,\ndrivers/net/phy/air_en8811h.c:215:\tAIR_PHY_LED_DUR_BLINK_128MS,\ndrivers/net/phy/air_en8811h.c:216:\tAIR_PHY_LED_DUR_BLINK_256MS,\ndrivers/net/phy/air_en8811h.c:217:\tAIR_PHY_LED_DUR_BLINK_512MS,\ndrivers/net/phy/air_en8811h.c:218:\tAIR_PHY_LED_DUR_BLINK_1024MS,\ndrivers/net/phy/air_en8811h.c-219-};\n--\ndrivers/net/phy/air_en8811h.c=221=enum {\ndrivers/net/phy/air_en8811h.c:222:\tAIR_LED_DISABLE,\ndrivers/net/phy/air_en8811h.c:223:\tAIR_LED_ENABLE,\ndrivers/net/phy/air_en8811h.c-224-};\n--\ndrivers/net/phy/air_en8811h.c=226=enum {\ndrivers/net/phy/air_en8811h.c:227:\tAIR_ACTIVE_LOW,\ndrivers/net/phy/air_en8811h.c:228:\tAIR_ACTIVE_HIGH,\ndrivers/net/phy/air_en8811h.c-229-};\n--\ndrivers/net/phy/air_en8811h.c=231=enum {\ndrivers/net/phy/air_en8811h.c:232:\tAIR_LED_MODE_DISABLE,\ndrivers/net/phy/air_en8811h.c:233:\tAIR_LED_MODE_USER_DEFINE,\ndrivers/net/phy/air_en8811h.c-234-};\ndrivers/net/phy/air_en8811h.c-235-\ndrivers/net/phy/air_en8811h.c:236:#define AIR_PHY_LED_DUR_UNIT\t1024\ndrivers/net/phy/air_en8811h.c:237:#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT \u003c\u003c AIR_PHY_LED_DUR_BLINK_64MS)\ndrivers/net/phy/air_en8811h.c-238-\n--\ndrivers/net/phy/air_en8811h.c=248=static int __air_pbus_reg_write(struct mdio_device *mdiodev,\n--\ndrivers/net/phy/air_en8811h.c-252-\ndrivers/net/phy/air_en8811h.c:253:\tret = __mdiobus_write(mdiodev-\u003ebus, mdiodev-\u003eaddr, AIR_EXT_PAGE_ACCESS,\ndrivers/net/phy/air_en8811h.c-254-\t\t\t      upper_16_bits(pbus_reg));\n--\ndrivers/net/phy/air_en8811h.c-257-\ndrivers/net/phy/air_en8811h.c:258:\tret = __mdiobus_write(mdiodev-\u003ebus, mdiodev-\u003eaddr, AIR_PBUS_ADDR_HIGH,\ndrivers/net/phy/air_en8811h.c:259:\t\t\t      FIELD_GET(AIR_PBUS_REG_ADDR_HIGH_MASK, pbus_reg));\ndrivers/net/phy/air_en8811h.c-260-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-263-\tret = __mdiobus_write(mdiodev-\u003ebus, mdiodev-\u003eaddr,\ndrivers/net/phy/air_en8811h.c:264:\t\t\t      FIELD_GET(AIR_PBUS_REG_ADDR_LOW_MASK, pbus_reg),\ndrivers/net/phy/air_en8811h.c-265-\t\t\t      lower_16_bits(pbus_data));\n--\ndrivers/net/phy/air_en8811h.c-268-\ndrivers/net/phy/air_en8811h.c:269:\treturn __mdiobus_write(mdiodev-\u003ebus, mdiodev-\u003eaddr, AIR_PBUS_DATA_HIGH,\ndrivers/net/phy/air_en8811h.c-270-\t\t\t       upper_16_bits(pbus_data));\n--\ndrivers/net/phy/air_en8811h.c=273=static int __air_write_buf(struct phy_device *phydev, u32 address,\n--\ndrivers/net/phy/air_en8811h.c-279-\ndrivers/net/phy/air_en8811h.c:280:\tret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR);\ndrivers/net/phy/air_en8811h.c-281-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-283-\ndrivers/net/phy/air_en8811h.c:284:\tret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,\ndrivers/net/phy/air_en8811h.c-285-\t\t\t  upper_16_bits(address));\n--\ndrivers/net/phy/air_en8811h.c-288-\ndrivers/net/phy/air_en8811h.c:289:\tret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,\ndrivers/net/phy/air_en8811h.c-290-\t\t\t  lower_16_bits(address));\n--\ndrivers/net/phy/air_en8811h.c-295-\t\tval = get_unaligned_le16(\u0026fw-\u003edata[offset + 2]);\ndrivers/net/phy/air_en8811h.c:296:\t\tret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val);\ndrivers/net/phy/air_en8811h.c-297-\t\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-300-\t\tval = get_unaligned_le16(\u0026fw-\u003edata[offset]);\ndrivers/net/phy/air_en8811h.c:301:\t\tret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val);\ndrivers/net/phy/air_en8811h.c-302-\t\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c=309=static int air_write_buf(struct phy_device *phydev, u32 address,\n--\ndrivers/net/phy/air_en8811h.c-320-\ndrivers/net/phy/air_en8811h.c:321:\tsaved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);\ndrivers/net/phy/air_en8811h.c-322-\n--\ndrivers/net/phy/air_en8811h.c=468=static int an8811hb_load_firmware(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-484-\ndrivers/net/phy/air_en8811h.c:485:\tret = an8811hb_load_file(phydev, AN8811HB_MD32_DM, AIR_FW_ADDR_DM);\ndrivers/net/phy/air_en8811h.c-486-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-494-\ndrivers/net/phy/air_en8811h.c:495:\tret = an8811hb_load_file(phydev, AN8811HB_MD32_DSP, AIR_FW_ADDR_DSP);\ndrivers/net/phy/air_en8811h.c-496-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c=508=static int en8811h_load_firmware(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-532-\ndrivers/net/phy/air_en8811h.c:533:\tret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);\ndrivers/net/phy/air_en8811h.c-534-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-536-\ndrivers/net/phy/air_en8811h.c:537:\tret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);\ndrivers/net/phy/air_en8811h.c-538-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c=586=static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)\n--\ndrivers/net/phy/air_en8811h.c-594-\tif (on)\ndrivers/net/phy/air_en8811h.c:595:\t\tchanged = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,\ndrivers/net/phy/air_en8811h.c-596-\t\t\t\t\t    \u0026priv-\u003eled[index].state);\ndrivers/net/phy/air_en8811h.c-597-\telse\ndrivers/net/phy/air_en8811h.c:598:\t\tchanged = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,\ndrivers/net/phy/air_en8811h.c-599-\t\t\t\t\t       \u0026priv-\u003eled[index].state);\n--\ndrivers/net/phy/air_en8811h.c-608-\t\treturn phy_modify_mmd(phydev, MDIO_MMD_VEND2,\ndrivers/net/phy/air_en8811h.c:609:\t\t\t\t      AIR_PHY_LED_ON(index),\ndrivers/net/phy/air_en8811h.c:610:\t\t\t\t      AIR_PHY_LED_ON_MASK,\ndrivers/net/phy/air_en8811h.c:611:\t\t\t\t      on ? AIR_PHY_LED_ON_FORCE_ON : 0);\ndrivers/net/phy/air_en8811h.c-612-\n--\ndrivers/net/phy/air_en8811h.c=616=static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,\n--\ndrivers/net/phy/air_en8811h.c-625-\tif (blinking)\ndrivers/net/phy/air_en8811h.c:626:\t\tchanged = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,\ndrivers/net/phy/air_en8811h.c-627-\t\t\t\t\t    \u0026priv-\u003eled[index].state);\ndrivers/net/phy/air_en8811h.c-628-\telse\ndrivers/net/phy/air_en8811h.c:629:\t\tchanged = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,\ndrivers/net/phy/air_en8811h.c-630-\t\t\t\t\t       \u0026priv-\u003eled[index].state);\n--\ndrivers/net/phy/air_en8811h.c-635-\t\treturn phy_write_mmd(phydev, MDIO_MMD_VEND2,\ndrivers/net/phy/air_en8811h.c:636:\t\t\t\t     AIR_PHY_LED_BLINK(index),\ndrivers/net/phy/air_en8811h.c-637-\t\t\t\t     blinking ?\ndrivers/net/phy/air_en8811h.c:638:\t\t\t\t     AIR_PHY_LED_BLINK_FORCE_BLINK : 0);\ndrivers/net/phy/air_en8811h.c-639-\telse\n--\ndrivers/net/phy/air_en8811h.c=643=static int air_led_blink_set(struct phy_device *phydev, u8 index,\n--\ndrivers/net/phy/air_en8811h.c-669-\t/* hw-control is off*/\ndrivers/net/phy/air_en8811h.c:670:\tif (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, \u0026priv-\u003eled[index].state))\ndrivers/net/phy/air_en8811h.c-671-\t\tpriv-\u003eled[index].rules = 0;\n--\ndrivers/net/phy/air_en8811h.c=676=static int air_led_brightness_set(struct phy_device *phydev, u8 index,\n--\ndrivers/net/phy/air_en8811h.c-694-\t/* hw-control is off */\ndrivers/net/phy/air_en8811h.c:695:\tif (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, \u0026priv-\u003eled[index].state))\ndrivers/net/phy/air_en8811h.c-696-\t\tpriv-\u003eled[index].rules = 0;\n--\ndrivers/net/phy/air_en8811h.c=714=static int air_led_hw_control_set(struct phy_device *phydev, u8 index,\n--\ndrivers/net/phy/air_en8811h.c-726-\tif (rules \u0026 BIT(TRIGGER_NETDEV_FULL_DUPLEX))\ndrivers/net/phy/air_en8811h.c:727:\t\ton |= AIR_PHY_LED_ON_FDX;\ndrivers/net/phy/air_en8811h.c-728-\ndrivers/net/phy/air_en8811h.c-729-\tif (rules \u0026 (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))\ndrivers/net/phy/air_en8811h.c:730:\t\ton |= AIR_PHY_LED_ON_LINK10;\ndrivers/net/phy/air_en8811h.c-731-\ndrivers/net/phy/air_en8811h.c-732-\tif (rules \u0026 (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))\ndrivers/net/phy/air_en8811h.c:733:\t\ton |= AIR_PHY_LED_ON_LINK100;\ndrivers/net/phy/air_en8811h.c-734-\ndrivers/net/phy/air_en8811h.c-735-\tif (rules \u0026 (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))\ndrivers/net/phy/air_en8811h.c:736:\t\ton |= AIR_PHY_LED_ON_LINK1000;\ndrivers/net/phy/air_en8811h.c-737-\ndrivers/net/phy/air_en8811h.c-738-\tif (rules \u0026 (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))\ndrivers/net/phy/air_en8811h.c:739:\t\ton |= AIR_PHY_LED_ON_LINK2500;\ndrivers/net/phy/air_en8811h.c-740-\ndrivers/net/phy/air_en8811h.c-741-\tif (rules \u0026 BIT(TRIGGER_NETDEV_RX)) {\ndrivers/net/phy/air_en8811h.c:742:\t\tblink |= AIR_PHY_LED_BLINK_10RX   |\ndrivers/net/phy/air_en8811h.c:743:\t\t\t AIR_PHY_LED_BLINK_100RX  |\ndrivers/net/phy/air_en8811h.c:744:\t\t\t AIR_PHY_LED_BLINK_1000RX |\ndrivers/net/phy/air_en8811h.c:745:\t\t\t AIR_PHY_LED_BLINK_2500RX;\ndrivers/net/phy/air_en8811h.c-746-\t}\n--\ndrivers/net/phy/air_en8811h.c-748-\tif (rules \u0026 BIT(TRIGGER_NETDEV_TX)) {\ndrivers/net/phy/air_en8811h.c:749:\t\tblink |= AIR_PHY_LED_BLINK_10TX   |\ndrivers/net/phy/air_en8811h.c:750:\t\t\t AIR_PHY_LED_BLINK_100TX  |\ndrivers/net/phy/air_en8811h.c:751:\t\t\t AIR_PHY_LED_BLINK_1000TX |\ndrivers/net/phy/air_en8811h.c:752:\t\t\t AIR_PHY_LED_BLINK_2500TX;\ndrivers/net/phy/air_en8811h.c-753-\t}\n--\ndrivers/net/phy/air_en8811h.c-756-\t\t/* switch hw-control on, so led-on and led-blink are off */\ndrivers/net/phy/air_en8811h.c:757:\t\tclear_bit(AIR_PHY_LED_STATE_FORCE_ON,\ndrivers/net/phy/air_en8811h.c-758-\t\t\t  \u0026priv-\u003eled[index].state);\ndrivers/net/phy/air_en8811h.c:759:\t\tclear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,\ndrivers/net/phy/air_en8811h.c-760-\t\t\t  \u0026priv-\u003eled[index].state);\n--\ndrivers/net/phy/air_en8811h.c-764-\ndrivers/net/phy/air_en8811h.c:765:\tret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),\ndrivers/net/phy/air_en8811h.c:766:\t\t\t     AIR_PHY_LED_ON_MASK, on);\ndrivers/net/phy/air_en8811h.c-767-\n--\ndrivers/net/phy/air_en8811h.c-770-\ndrivers/net/phy/air_en8811h.c:771:\treturn phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),\ndrivers/net/phy/air_en8811h.c-772-\t\t\t     blink);\n--\ndrivers/net/phy/air_en8811h.c=775=static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)\n--\ndrivers/net/phy/air_en8811h.c-782-\ndrivers/net/phy/air_en8811h.c:783:\tif (state == AIR_LED_ENABLE)\ndrivers/net/phy/air_en8811h.c:784:\t\tval |= AIR_PHY_LED_ON_ENABLE;\ndrivers/net/phy/air_en8811h.c-785-\telse\ndrivers/net/phy/air_en8811h.c:786:\t\tval \u0026= ~AIR_PHY_LED_ON_ENABLE;\ndrivers/net/phy/air_en8811h.c-787-\ndrivers/net/phy/air_en8811h.c:788:\tif (pol == AIR_ACTIVE_HIGH)\ndrivers/net/phy/air_en8811h.c:789:\t\tval |= AIR_PHY_LED_ON_POLARITY;\ndrivers/net/phy/air_en8811h.c-790-\telse\ndrivers/net/phy/air_en8811h.c:791:\t\tval \u0026= ~AIR_PHY_LED_ON_POLARITY;\ndrivers/net/phy/air_en8811h.c-792-\ndrivers/net/phy/air_en8811h.c:793:\terr = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),\ndrivers/net/phy/air_en8811h.c:794:\t\t\t     AIR_PHY_LED_ON_ENABLE |\ndrivers/net/phy/air_en8811h.c:795:\t\t\t     AIR_PHY_LED_ON_POLARITY, val);\ndrivers/net/phy/air_en8811h.c-796-\n--\ndrivers/net/phy/air_en8811h.c=803=static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)\n--\ndrivers/net/phy/air_en8811h.c-807-\ndrivers/net/phy/air_en8811h.c:808:\tret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,\ndrivers/net/phy/air_en8811h.c-809-\t\t\t    dur);\n--\ndrivers/net/phy/air_en8811h.c-812-\ndrivers/net/phy/air_en8811h.c:813:\tret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,\ndrivers/net/phy/air_en8811h.c-814-\t\t\t    dur \u003e\u003e 1);\n--\ndrivers/net/phy/air_en8811h.c-818-\tswitch (mode) {\ndrivers/net/phy/air_en8811h.c:819:\tcase AIR_LED_MODE_DISABLE:\ndrivers/net/phy/air_en8811h.c:820:\t\tret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,\ndrivers/net/phy/air_en8811h.c:821:\t\t\t\t     AIR_PHY_LED_BCR_EXT_CTRL |\ndrivers/net/phy/air_en8811h.c:822:\t\t\t\t     AIR_PHY_LED_BCR_MODE_MASK, 0);\ndrivers/net/phy/air_en8811h.c-823-\t\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-825-\t\tbreak;\ndrivers/net/phy/air_en8811h.c:826:\tcase AIR_LED_MODE_USER_DEFINE:\ndrivers/net/phy/air_en8811h.c:827:\t\tret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,\ndrivers/net/phy/air_en8811h.c:828:\t\t\t\t     AIR_PHY_LED_BCR_EXT_CTRL |\ndrivers/net/phy/air_en8811h.c:829:\t\t\t\t     AIR_PHY_LED_BCR_CLK_EN,\ndrivers/net/phy/air_en8811h.c:830:\t\t\t\t     AIR_PHY_LED_BCR_EXT_CTRL |\ndrivers/net/phy/air_en8811h.c:831:\t\t\t\t     AIR_PHY_LED_BCR_CLK_EN);\ndrivers/net/phy/air_en8811h.c-832-\t\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-840-\tfor (i = 0; i \u003c num; ++i) {\ndrivers/net/phy/air_en8811h.c:841:\t\tret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);\ndrivers/net/phy/air_en8811h.c-842-\t\tif (ret \u003c 0) {\n--\ndrivers/net/phy/air_en8811h.c=1063=static int en8811h_leds_setup(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-1067-\ndrivers/net/phy/air_en8811h.c:1068:\tpriv-\u003eled[0].rules = AIR_DEFAULT_TRIGGER_LED0;\ndrivers/net/phy/air_en8811h.c:1069:\tpriv-\u003eled[1].rules = AIR_DEFAULT_TRIGGER_LED1;\ndrivers/net/phy/air_en8811h.c:1070:\tpriv-\u003eled[2].rules = AIR_DEFAULT_TRIGGER_LED2;\ndrivers/net/phy/air_en8811h.c-1071-\ndrivers/net/phy/air_en8811h.c:1072:\tret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,\ndrivers/net/phy/air_en8811h.c:1073:\t\t\t    AIR_LED_MODE_DISABLE);\ndrivers/net/phy/air_en8811h.c-1074-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c=1253=static int an8811hb_config_init(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-1271-\ndrivers/net/phy/air_en8811h.c:1272:\tret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,\ndrivers/net/phy/air_en8811h.c:1273:\t\t\t    AIR_LED_MODE_USER_DEFINE);\ndrivers/net/phy/air_en8811h.c-1274-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c=1280=static int en8811h_config_init(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-1297-\t */\ndrivers/net/phy/air_en8811h.c:1298:\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1,\ndrivers/net/phy/air_en8811h.c:1299:\t\t\t    AIR_PHY_MCU_CMD_1_MODE1);\ndrivers/net/phy/air_en8811h.c-1300-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c-1301-\t\treturn ret;\ndrivers/net/phy/air_en8811h.c:1302:\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2,\ndrivers/net/phy/air_en8811h.c:1303:\t\t\t    AIR_PHY_MCU_CMD_2_MODE1);\ndrivers/net/phy/air_en8811h.c-1304-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c-1305-\t\treturn ret;\ndrivers/net/phy/air_en8811h.c:1306:\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,\ndrivers/net/phy/air_en8811h.c:1307:\t\t\t    AIR_PHY_MCU_CMD_3_MODE1);\ndrivers/net/phy/air_en8811h.c-1308-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c-1309-\t\treturn ret;\ndrivers/net/phy/air_en8811h.c:1310:\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,\ndrivers/net/phy/air_en8811h.c:1311:\t\t\t    AIR_PHY_MCU_CMD_4_MODE1);\ndrivers/net/phy/air_en8811h.c-1312-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-1318-\ndrivers/net/phy/air_en8811h.c:1319:\tret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,\ndrivers/net/phy/air_en8811h.c:1320:\t\t\t    AIR_LED_MODE_USER_DEFINE);\ndrivers/net/phy/air_en8811h.c-1321-\tif (ret \u003c 0) {\n--\ndrivers/net/phy/air_en8811h.c=1378=static int en8811h_read_status(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-1428-\t/* Get real speed from vendor register */\ndrivers/net/phy/air_en8811h.c:1429:\tval = phy_read(phydev, AIR_AUX_CTRL_STATUS);\ndrivers/net/phy/air_en8811h.c-1430-\tif (val \u003c 0)\ndrivers/net/phy/air_en8811h.c-1431-\t\treturn val;\ndrivers/net/phy/air_en8811h.c:1432:\tswitch (val \u0026 AIR_AUX_CTRL_STATUS_SPEED_MASK) {\ndrivers/net/phy/air_en8811h.c:1433:\tcase AIR_AUX_CTRL_STATUS_SPEED_2500:\ndrivers/net/phy/air_en8811h.c-1434-\t\tphydev-\u003espeed = SPEED_2500;\ndrivers/net/phy/air_en8811h.c-1435-\t\tbreak;\ndrivers/net/phy/air_en8811h.c:1436:\tcase AIR_AUX_CTRL_STATUS_SPEED_1000:\ndrivers/net/phy/air_en8811h.c-1437-\t\tphydev-\u003espeed = SPEED_1000;\ndrivers/net/phy/air_en8811h.c-1438-\t\tbreak;\ndrivers/net/phy/air_en8811h.c:1439:\tcase AIR_AUX_CTRL_STATUS_SPEED_100:\ndrivers/net/phy/air_en8811h.c-1440-\t\tphydev-\u003espeed = SPEED_100;\ndrivers/net/phy/air_en8811h.c-1441-\t\tbreak;\ndrivers/net/phy/air_en8811h.c:1442:\tcase AIR_AUX_CTRL_STATUS_SPEED_10:\ndrivers/net/phy/air_en8811h.c-1443-\t\tphydev-\u003espeed = SPEED_10;\n--\ndrivers/net/phy/air_en8811h.c=1462=static int en8811h_clear_intr(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-1465-\ndrivers/net/phy/air_en8811h.c:1466:\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,\ndrivers/net/phy/air_en8811h.c:1467:\t\t\t    AIR_PHY_MCU_CMD_3_DOCMD);\ndrivers/net/phy/air_en8811h.c-1468-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-1470-\ndrivers/net/phy/air_en8811h.c:1471:\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,\ndrivers/net/phy/air_en8811h.c:1472:\t\t\t    AIR_PHY_MCU_CMD_4_INTCLR);\ndrivers/net/phy/air_en8811h.c-1473-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_phy_lib.c=17=static int __air_buckpbus_reg_read(struct phy_device *phydev,\n--\ndrivers/net/phy/air_phy_lib.c-22-\ndrivers/net/phy/air_phy_lib.c:23:\tret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);\ndrivers/net/phy/air_phy_lib.c-24-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_phy_lib.c-26-\ndrivers/net/phy/air_phy_lib.c:27:\tret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,\ndrivers/net/phy/air_phy_lib.c-28-\t\t\t  upper_16_bits(pbus_address));\n--\ndrivers/net/phy/air_phy_lib.c-31-\ndrivers/net/phy/air_phy_lib.c:32:\tret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,\ndrivers/net/phy/air_phy_lib.c-33-\t\t\t  lower_16_bits(pbus_address));\n--\ndrivers/net/phy/air_phy_lib.c-36-\ndrivers/net/phy/air_phy_lib.c:37:\tpbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);\ndrivers/net/phy/air_phy_lib.c-38-\tif (pbus_data_high \u003c 0)\n--\ndrivers/net/phy/air_phy_lib.c-40-\ndrivers/net/phy/air_phy_lib.c:41:\tpbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);\ndrivers/net/phy/air_phy_lib.c-42-\tif (pbus_data_low \u003c 0)\n--\ndrivers/net/phy/air_phy_lib.c=49=static int __air_buckpbus_reg_write(struct phy_device *phydev,\n--\ndrivers/net/phy/air_phy_lib.c-53-\ndrivers/net/phy/air_phy_lib.c:54:\tret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);\ndrivers/net/phy/air_phy_lib.c-55-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_phy_lib.c-57-\ndrivers/net/phy/air_phy_lib.c:58:\tret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,\ndrivers/net/phy/air_phy_lib.c-59-\t\t\t  upper_16_bits(pbus_address));\n--\ndrivers/net/phy/air_phy_lib.c-62-\ndrivers/net/phy/air_phy_lib.c:63:\tret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,\ndrivers/net/phy/air_phy_lib.c-64-\t\t\t  lower_16_bits(pbus_address));\n--\ndrivers/net/phy/air_phy_lib.c-67-\ndrivers/net/phy/air_phy_lib.c:68:\tret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,\ndrivers/net/phy/air_phy_lib.c-69-\t\t\t  upper_16_bits(pbus_data));\n--\ndrivers/net/phy/air_phy_lib.c-72-\ndrivers/net/phy/air_phy_lib.c:73:\tret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,\n\n"
}

{
  "File": "drivers/net/phy/air_en8811h.c",
  "FirstLine": 1,
  "LineCount": 50
}

{
  "Contents": "   1:\t// SPDX-License-Identifier: GPL-2.0+\n   2:\t/*\n   3:\t * Driver for the Airoha EN8811H and AN8811HB 2.5 Gigabit PHYs.\n   4:\t *\n   5:\t * Limitations:\n   6:\t * - Only full duplex supported\n   7:\t * - Forced speed (AN off) is not supported by hardware (100Mbps)\n   8:\t *\n   9:\t * Source originated from airoha's en8811h.c and en8811h.h v1.2.1\n  10:\t * with AN8811HB bits from air_an8811hb.c v0.0.4\n  11:\t *\n  12:\t * Copyright (C) 2023, 2026 Airoha Technology Corp.\n  13:\t */\n  14:\t\n  15:\t#include \u003clinux/clk.h\u003e\n  16:\t#include \u003clinux/clk-provider.h\u003e\n  17:\t#include \u003clinux/phy.h\u003e\n  18:\t#include \u003clinux/phy/phy-common-props.h\u003e\n  19:\t#include \u003clinux/firmware.h\u003e\n  20:\t#include \u003clinux/bitfield.h\u003e\n  21:\t#include \u003clinux/property.h\u003e\n  22:\t#include \u003clinux/wordpart.h\u003e\n  23:\t#include \u003clinux/unaligned.h\u003e\n  24:\t\n  25:\t#include \"air_phy_lib.h\"\n  26:\t\n  27:\t#define EN8811H_PHY_ID\t\t0x03a2a411\n  28:\t#define AN8811HB_PHY_ID\t\t0xc0ff04a0\n  29:\t\n  30:\t#define EN8811H_MD32_DM\t\t\"airoha/EthMD32.dm.bin\"\n  31:\t#define EN8811H_MD32_DSP\t\"airoha/EthMD32.DSP.bin\"\n  32:\t#define AN8811HB_MD32_DM\t\"airoha/an8811hb/EthMD32_CRC.DM.bin\"\n  33:\t#define AN8811HB_MD32_DSP\t\"airoha/an8811hb/EthMD32_CRC.DSP.bin\"\n  34:\t\n  35:\t#define AIR_FW_ADDR_DM\t0x00000000\n  36:\t#define AIR_FW_ADDR_DSP\t0x00100000\n  37:\t\n  38:\t/* MII Registers */\n  39:\t#define AIR_AUX_CTRL_STATUS\t\t0x1d\n  40:\t#define   AIR_AUX_CTRL_STATUS_SPEED_MASK\tGENMASK(4, 2)\n  41:\t#define   AIR_AUX_CTRL_STATUS_SPEED_10\t\t0x0\n  42:\t#define   AIR_AUX_CTRL_STATUS_SPEED_100\t\t0x4\n  43:\t#define   AIR_AUX_CTRL_STATUS_SPEED_1000\t0x8\n  44:\t#define   AIR_AUX_CTRL_STATUS_SPEED_2500\t0xc\n  45:\t\n  46:\t/* Registers on MDIO_MMD_VEND1 */\n  47:\t#define EN8811H_PHY_FW_STATUS\t\t0x8009\n  48:\t#define   EN8811H_PHY_READY\t\t\t0x02\n  49:\t\n  50:\t#define AIR_PHY_MCU_CMD_0\t\t0x800b\n"
}

gemini-3.7-flash

null

null

							input: 19027
							output: 44
							thoughts: 38
						

Here's my take on the thought process, as requested:

**Diving Deeper into the Air Interface Driver**

Okay, so I've been poking around in `air_en8811h.c` and specifically focusing on `air_write_buf`. I need to get a better handle on how this driver actually works. My immediate thought is to trace the execution and see the rest of the file surrounding this function. Specifically, I'm interested in how this driver is registered within the kernel, and then even more particularly how it's *bound* to specific hardware devices. Understanding the registration and binding processes is key to figuring out the overall architecture and how the low-level functions like `air_write_buf` fit into the grand scheme of things. It'll give me a clearer picture of the device's lifecycle and how it interacts with the rest of the system.

{
  "File": "drivers/net/phy/air_en8811h.c",
  "FirstLine": 300,
  "LineCount": 60
}

{
  "Contents": " 300:\t\t\tval = get_unaligned_le16(\u0026fw-\u003edata[offset]);\n 301:\t\t\tret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val);\n 302:\t\t\tif (ret \u003c 0)\n 303:\t\t\t\treturn ret;\n 304:\t\t}\n 305:\t\n 306:\t\treturn 0;\n 307:\t}\n 308:\t\n 309:\tstatic int air_write_buf(struct phy_device *phydev, u32 address,\n 310:\t\t\t\t const struct firmware *fw)\n 311:\t{\n 312:\t\tint saved_page;\n 313:\t\tint ret = 0;\n 314:\t\n 315:\t\tif (fw-\u003esize % 4) {\n 316:\t\t\tphydev_err(phydev, \"firmware size %zu is not a multiple of 4\\n\",\n 317:\t\t\t\t   fw-\u003esize);\n 318:\t\t\treturn -EINVAL;\n 319:\t\t}\n 320:\t\n 321:\t\tsaved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);\n 322:\t\n 323:\t\tif (saved_page \u003e= 0) {\n 324:\t\t\tret = __air_write_buf(phydev, address, fw);\n 325:\t\t\tif (ret \u003c 0)\n 326:\t\t\t\tphydev_err(phydev, \"%s 0x%08x failed: %d\\n\", __func__,\n 327:\t\t\t\t\t   address, ret);\n 328:\t\t}\n 329:\t\n 330:\t\treturn phy_restore_page(phydev, saved_page, ret);\n 331:\t}\n 332:\t\n 333:\tstatic int en8811h_wait_mcu_ready(struct phy_device *phydev)\n 334:\t{\n 335:\t\tint ret, reg_value;\n 336:\t\n 337:\t\tret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,\n 338:\t\t\t\t\t\t EN8811H_FW_CTRL_1_FINISH);\n 339:\t\tif (ret)\n 340:\t\t\treturn ret;\n 341:\t\n 342:\t\t/* Because of mdio-lock, may have to wait for multiple loads */\n 343:\t\tret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,\n 344:\t\t\t\t\t\tEN8811H_PHY_FW_STATUS, reg_value,\n 345:\t\t\t\t\t\treg_value == EN8811H_PHY_READY,\n 346:\t\t\t\t\t\t20000, 7500000, true);\n 347:\t\tif (ret) {\n 348:\t\t\tphydev_err(phydev, \"MCU not ready: 0x%x\\n\", reg_value);\n 349:\t\t\treturn -ENODEV;\n 350:\t\t}\n 351:\t\n 352:\t\treturn 0;\n 353:\t}\n 354:\t\n 355:\tstatic int an8811hb_check_crc(struct phy_device *phydev, u32 set1,\n 356:\t\t\t\t      u32 mon2, u32 mon3)\n 357:\t{\n 358:\t\tu32 pbus_value;\n 359:\t\tint retry = 25;\n"
}

gemini-3.7-flash

null

null

							input: 20251
							output: 45
							thoughts: 29
						

Here's my take on the thought process, as if it were my own:

**Looking for Phy Driver Registration**

Okay, so I need to understand how this PHY driver is being integrated into the system, specifically within the context of `air_en8811h.c`. The most direct route to that is to jump straight to the end of the file. That's where I should find the registration process for the PHY driver. I'm assuming, of course, that the code follows standard conventions and that's the typical location for this kind of thing. Let's see if that assumption holds true. I'm expecting to find a call, likely involving `module_init` or a similar macro, that sets everything up. Right, let's see what's there.

{
  "File": "drivers/net/phy/air_en8811h.c",
  "FirstLine": 1450,
  "LineCount": 80
}

{
  "Contents": "1450:\t\tif (priv-\u003efirmware_version \u003c 0x24011202) {\n1451:\t\t\tlinkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,\n1452:\t\t\t\t\t phydev-\u003elp_advertising,\n1453:\t\t\t\t\t phydev-\u003espeed == SPEED_2500);\n1454:\t\t}\n1455:\t\n1456:\t\t/* Only supports full duplex */\n1457:\t\tphydev-\u003eduplex = DUPLEX_FULL;\n1458:\t\n1459:\t\treturn 0;\n1460:\t}\n1461:\t\n1462:\tstatic int en8811h_clear_intr(struct phy_device *phydev)\n1463:\t{\n1464:\t\tint ret;\n1465:\t\n1466:\t\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,\n1467:\t\t\t\t    AIR_PHY_MCU_CMD_3_DOCMD);\n1468:\t\tif (ret \u003c 0)\n1469:\t\t\treturn ret;\n1470:\t\n1471:\t\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,\n1472:\t\t\t\t    AIR_PHY_MCU_CMD_4_INTCLR);\n1473:\t\tif (ret \u003c 0)\n1474:\t\t\treturn ret;\n1475:\t\n1476:\t\treturn 0;\n1477:\t}\n1478:\t\n1479:\tstatic irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)\n1480:\t{\n1481:\t\tint ret;\n1482:\t\n1483:\t\tret = en8811h_clear_intr(phydev);\n1484:\t\tif (ret \u003c 0) {\n1485:\t\t\tphy_error(phydev);\n1486:\t\t\treturn IRQ_NONE;\n1487:\t\t}\n1488:\t\n1489:\t\tphy_trigger_machine(phydev);\n1490:\t\n1491:\t\treturn IRQ_HANDLED;\n1492:\t}\n1493:\t\n1494:\tstatic int en8811h_resume(struct phy_device *phydev)\n1495:\t{\n1496:\t\tclk_restore_context();\n1497:\t\n1498:\t\treturn genphy_resume(phydev);\n1499:\t}\n1500:\t\n1501:\tstatic int en8811h_suspend(struct phy_device *phydev)\n1502:\t{\n1503:\t\tclk_save_context();\n1504:\t\n1505:\t\treturn genphy_suspend(phydev);\n1506:\t}\n1507:\t\n1508:\tstatic void an8811hb_remove(struct phy_device *phydev)\n1509:\t{\n1510:\t\tstruct en8811h_priv *priv = phydev-\u003epriv;\n1511:\t\n1512:\t\tif (priv-\u003epbusdev) {\n1513:\t\t\tmdio_device_remove(priv-\u003epbusdev);\n1514:\t\t\tmdio_device_free(priv-\u003epbusdev);\n1515:\t\t}\n1516:\t}\n1517:\t\n1518:\tstatic struct phy_driver en8811h_driver[] = {\n1519:\t{\n1520:\t\tPHY_ID_MATCH_MODEL(EN8811H_PHY_ID),\n1521:\t\t.name\t\t\t= \"Airoha EN8811H\",\n1522:\t\t.probe\t\t\t= en8811h_probe,\n1523:\t\t.get_features\t\t= en8811h_get_features,\n1524:\t\t.config_init\t\t= en8811h_config_init,\n1525:\t\t.get_rate_matching\t= en8811h_get_rate_matching,\n1526:\t\t.config_aneg\t\t= en8811h_config_aneg,\n1527:\t\t.read_status\t\t= en8811h_read_status,\n1528:\t\t.resume\t\t\t= en8811h_resume,\n1529:\t\t.suspend\t\t= en8811h_suspend,\n"
}

gemini-3.7-flash

null

null

							input: 21714
							output: 43
							thoughts: 314
						

**My Initial Assessment of the `air_en8811h.c` PHY Driver**

Okay, so I'm looking at `air_en8811h.c`, a PHY driver specifically for Airoha EN8811H and AN8811HB Ethernet PHYs. My immediate question, and the critical one for fuzzing applicability, is whether this type of Ethernet PHY is even *reachable* in a standard virtualized environment like QEMU or GCE. I need to be absolutely certain before I waste any time.

I remember the fuzzing guidelines very clearly: "REACHABILITY IS THE PRIMARY GATE." I can only fuzz code that *actually* executes in these emulated setups. If it's structurally unreachable, the fuzzing is a no-go, no matter how clever the code or complex the logic might be.

The guidelines are explicit about "Structurally unreachable hardware," mentioning vendor-specific PCIe switches, SmartNICs, GPU drivers (like mlxsw, qed, and amdgpu) that *require* physical ASIC/PCIe cards, not emulated ones. So, I need to check if these PHY devices (specifically MDIO phy drivers like `air_en8811h`) need physical hardware or the MDIO bus to work. I need to determine if they can be instantiated without it, or if they require the physical MDIO bus and PHY hardware.

Wait a second…can I emulate or instantiate MDIO PHY devices within QEMU? I need to know if there's any support for a virtual or mock MDIO bus in the Linux kernel or if syzkaller has any workarounds for it. Time to search the tree for "mdio mock" or "virtual mdio" buses. That's the key to making this fuzzable.

{
  "Expression": "mdio_gpio|mdio-gpio|mdio-netlink|dummy.*mdio",
  "PathPrefix": "drivers/net"
}

{
  "Output": "drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c=381=int stmmac_mdio_reset(struct mii_bus *bus)\n--\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-416-\t * It doesn't complete its reset until at least one clock cycle\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c:417:\t * on MDC, so perform a dummy mdio read. To be updated for GMAC4\ndrivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c-418-\t * if needed.\n--\ndrivers/net/mdio/Kconfig=90=config MDIO_GPIO\n--\ndrivers/net/mdio/Kconfig-97-\t  To compile this driver as a module, choose M here: the module\ndrivers/net/mdio/Kconfig:98:\t  will be called mdio-gpio.\ndrivers/net/mdio/Kconfig-99-\n--\ndrivers/net/mdio/Makefile=13=obj-$(CONFIG_MDIO_CAVIUM)\t\t+= mdio-cavium.o\ndrivers/net/mdio/Makefile:14:obj-$(CONFIG_MDIO_GPIO)\t\t\t+= mdio-gpio.o\ndrivers/net/mdio/Makefile-15-obj-$(CONFIG_MDIO_HISI_FEMAC)\t\t+= mdio-hisi-femac.o\n--\ndrivers/net/mdio/mdio-gpio.c-31-\ndrivers/net/mdio/mdio-gpio.c:32:struct mdio_gpio_info {\ndrivers/net/mdio/mdio-gpio.c-33-\tstruct mdiobb_ctrl ctrl;\n--\ndrivers/net/mdio/mdio-gpio.c-36-\ndrivers/net/mdio/mdio-gpio.c:37:static int mdio_gpio_get_data(struct device *dev,\ndrivers/net/mdio/mdio-gpio.c:38:\t\t\t      struct mdio_gpio_info *bitbang)\ndrivers/net/mdio/mdio-gpio.c-39-{\n--\ndrivers/net/mdio/mdio-gpio.c=55=static void mdio_dir(struct mdiobb_ctrl *ctrl, int dir)\ndrivers/net/mdio/mdio-gpio.c-56-{\ndrivers/net/mdio/mdio-gpio.c:57:\tstruct mdio_gpio_info *bitbang =\ndrivers/net/mdio/mdio-gpio.c:58:\t\tcontainer_of(ctrl, struct mdio_gpio_info, ctrl);\ndrivers/net/mdio/mdio-gpio.c-59-\n--\ndrivers/net/mdio/mdio-gpio.c=76=static int mdio_get(struct mdiobb_ctrl *ctrl)\ndrivers/net/mdio/mdio-gpio.c-77-{\ndrivers/net/mdio/mdio-gpio.c:78:\tstruct mdio_gpio_info *bitbang =\ndrivers/net/mdio/mdio-gpio.c:79:\t\tcontainer_of(ctrl, struct mdio_gpio_info, ctrl);\ndrivers/net/mdio/mdio-gpio.c-80-\n--\ndrivers/net/mdio/mdio-gpio.c=84=static void mdio_set(struct mdiobb_ctrl *ctrl, int what)\ndrivers/net/mdio/mdio-gpio.c-85-{\ndrivers/net/mdio/mdio-gpio.c:86:\tstruct mdio_gpio_info *bitbang =\ndrivers/net/mdio/mdio-gpio.c:87:\t\tcontainer_of(ctrl, struct mdio_gpio_info, ctrl);\ndrivers/net/mdio/mdio-gpio.c-88-\n--\ndrivers/net/mdio/mdio-gpio.c=95=static void mdc_set(struct mdiobb_ctrl *ctrl, int what)\ndrivers/net/mdio/mdio-gpio.c-96-{\ndrivers/net/mdio/mdio-gpio.c:97:\tstruct mdio_gpio_info *bitbang =\ndrivers/net/mdio/mdio-gpio.c:98:\t\tcontainer_of(ctrl, struct mdio_gpio_info, ctrl);\ndrivers/net/mdio/mdio-gpio.c-99-\n--\ndrivers/net/mdio/mdio-gpio.c-102-\ndrivers/net/mdio/mdio-gpio.c:103:static const struct mdiobb_ops mdio_gpio_ops = {\ndrivers/net/mdio/mdio-gpio.c-104-\t.owner = THIS_MODULE,\n--\ndrivers/net/mdio/mdio-gpio.c-110-\ndrivers/net/mdio/mdio-gpio.c:111:static struct mii_bus *mdio_gpio_bus_init(struct device *dev,\ndrivers/net/mdio/mdio-gpio.c:112:\t\t\t\t\t  struct mdio_gpio_info *bitbang,\ndrivers/net/mdio/mdio-gpio.c-113-\t\t\t\t\t  int bus_id)\n--\ndrivers/net/mdio/mdio-gpio.c-116-\ndrivers/net/mdio/mdio-gpio.c:117:\tbitbang-\u003ectrl.ops = \u0026mdio_gpio_ops;\ndrivers/net/mdio/mdio-gpio.c-118-\n--\ndrivers/net/mdio/mdio-gpio.c-141-\ndrivers/net/mdio/mdio-gpio.c:142:static void mdio_gpio_bus_deinit(struct device *dev)\ndrivers/net/mdio/mdio-gpio.c-143-{\n--\ndrivers/net/mdio/mdio-gpio.c-148-\ndrivers/net/mdio/mdio-gpio.c:149:static void mdio_gpio_bus_destroy(struct device *dev)\ndrivers/net/mdio/mdio-gpio.c-150-{\n--\ndrivers/net/mdio/mdio-gpio.c-153-\tmdiobus_unregister(bus);\ndrivers/net/mdio/mdio-gpio.c:154:\tmdio_gpio_bus_deinit(dev);\ndrivers/net/mdio/mdio-gpio.c-155-}\ndrivers/net/mdio/mdio-gpio.c-156-\ndrivers/net/mdio/mdio-gpio.c:157:static int mdio_gpio_probe(struct platform_device *pdev)\ndrivers/net/mdio/mdio-gpio.c-158-{\ndrivers/net/mdio/mdio-gpio.c:159:\tstruct mdio_gpio_info *bitbang;\ndrivers/net/mdio/mdio-gpio.c-160-\tstruct mii_bus *new_bus;\n--\ndrivers/net/mdio/mdio-gpio.c-166-\ndrivers/net/mdio/mdio-gpio.c:167:\tret = mdio_gpio_get_data(\u0026pdev-\u003edev, bitbang);\ndrivers/net/mdio/mdio-gpio.c-168-\tif (ret)\n--\ndrivers/net/mdio/mdio-gpio.c-171-\tif (pdev-\u003edev.of_node) {\ndrivers/net/mdio/mdio-gpio.c:172:\t\tbus_id = of_alias_get_id(pdev-\u003edev.of_node, \"mdio-gpio\");\ndrivers/net/mdio/mdio-gpio.c-173-\t\tif (bus_id \u003c 0) {\n--\ndrivers/net/mdio/mdio-gpio.c-180-\ndrivers/net/mdio/mdio-gpio.c:181:\tnew_bus = mdio_gpio_bus_init(\u0026pdev-\u003edev, bitbang, bus_id);\ndrivers/net/mdio/mdio-gpio.c-182-\tif (!new_bus)\n--\ndrivers/net/mdio/mdio-gpio.c-186-\tif (ret)\ndrivers/net/mdio/mdio-gpio.c:187:\t\tmdio_gpio_bus_deinit(\u0026pdev-\u003edev);\ndrivers/net/mdio/mdio-gpio.c-188-\n--\ndrivers/net/mdio/mdio-gpio.c-191-\ndrivers/net/mdio/mdio-gpio.c:192:static void mdio_gpio_remove(struct platform_device *pdev)\ndrivers/net/mdio/mdio-gpio.c-193-{\ndrivers/net/mdio/mdio-gpio.c:194:\tmdio_gpio_bus_destroy(\u0026pdev-\u003edev);\ndrivers/net/mdio/mdio-gpio.c-195-}\ndrivers/net/mdio/mdio-gpio.c-196-\ndrivers/net/mdio/mdio-gpio.c:197:static const struct of_device_id mdio_gpio_of_match[] = {\ndrivers/net/mdio/mdio-gpio.c:198:\t{ .compatible = \"virtual,mdio-gpio\", },\ndrivers/net/mdio/mdio-gpio.c-199-\t{ .compatible = \"microchip,mdio-smi0\" },\n--\ndrivers/net/mdio/mdio-gpio.c-201-};\ndrivers/net/mdio/mdio-gpio.c:202:MODULE_DEVICE_TABLE(of, mdio_gpio_of_match);\ndrivers/net/mdio/mdio-gpio.c-203-\ndrivers/net/mdio/mdio-gpio.c:204:static struct platform_driver mdio_gpio_driver = {\ndrivers/net/mdio/mdio-gpio.c:205:\t.probe = mdio_gpio_probe,\ndrivers/net/mdio/mdio-gpio.c:206:\t.remove = mdio_gpio_remove,\ndrivers/net/mdio/mdio-gpio.c-207-\t.driver\t\t= {\ndrivers/net/mdio/mdio-gpio.c:208:\t\t.name\t= \"mdio-gpio\",\ndrivers/net/mdio/mdio-gpio.c:209:\t\t.of_match_table = mdio_gpio_of_match,\ndrivers/net/mdio/mdio-gpio.c-210-\t},\n--\ndrivers/net/mdio/mdio-gpio.c-212-\ndrivers/net/mdio/mdio-gpio.c:213:module_platform_driver(mdio_gpio_driver);\ndrivers/net/mdio/mdio-gpio.c-214-\ndrivers/net/mdio/mdio-gpio.c:215:MODULE_ALIAS(\"platform:mdio-gpio\");\ndrivers/net/mdio/mdio-gpio.c-216-MODULE_AUTHOR(\"Laurent Pinchart, Paulius Zaleckas\");\n"
}

gemini-3.7-flash

null

null

							input: 25251
							output: 45
							thoughts: 56
						

**Analyzing the `air_en8811h` PHY Driver Probe Sequence**

Alright, let's dive into this `air_en8811h` PHY driver. I need to understand exactly how it's matched and ultimately probed within the system. My first thought is to zero in on the core of the matter: `air_en8811h.c` and its registration mechanism. I'll be targeting the `module_phy_driver` macro or a direct call to `phy_driver_register` within that source file. That's where the magic happens, where the driver announces its presence and capabilities to the broader PHY framework. Understanding the registration point will provide the critical linkage between the driver's definition and the system's ability to locate and utilize it. From there, I can trace the matching process and the eventual probe function execution.

{
  "File": "drivers/net/phy/air_en8811h.c",
  "FirstLine": 1520,
  "LineCount": 60
}

{
  "Contents": "1520:\t\tPHY_ID_MATCH_MODEL(EN8811H_PHY_ID),\n1521:\t\t.name\t\t\t= \"Airoha EN8811H\",\n1522:\t\t.probe\t\t\t= en8811h_probe,\n1523:\t\t.get_features\t\t= en8811h_get_features,\n1524:\t\t.config_init\t\t= en8811h_config_init,\n1525:\t\t.get_rate_matching\t= en8811h_get_rate_matching,\n1526:\t\t.config_aneg\t\t= en8811h_config_aneg,\n1527:\t\t.read_status\t\t= en8811h_read_status,\n1528:\t\t.resume\t\t\t= en8811h_resume,\n1529:\t\t.suspend\t\t= en8811h_suspend,\n1530:\t\t.config_intr\t\t= en8811h_clear_intr,\n1531:\t\t.handle_interrupt\t= en8811h_handle_interrupt,\n1532:\t\t.led_hw_is_supported\t= en8811h_led_hw_is_supported,\n1533:\t\t.read_page\t\t= air_phy_read_page,\n1534:\t\t.write_page\t\t= air_phy_write_page,\n1535:\t\t.led_blink_set\t\t= air_led_blink_set,\n1536:\t\t.led_brightness_set\t= air_led_brightness_set,\n1537:\t\t.led_hw_control_set\t= air_led_hw_control_set,\n1538:\t\t.led_hw_control_get\t= air_led_hw_control_get,\n1539:\t},\n1540:\t{\n1541:\t\tPHY_ID_MATCH_MODEL(AN8811HB_PHY_ID),\n1542:\t\t.name\t\t\t= \"Airoha AN8811HB\",\n1543:\t\t.probe\t\t\t= an8811hb_probe,\n1544:\t\t.remove\t\t\t= an8811hb_remove,\n1545:\t\t.get_features\t\t= en8811h_get_features,\n1546:\t\t.config_init\t\t= an8811hb_config_init,\n1547:\t\t.get_rate_matching\t= en8811h_get_rate_matching,\n1548:\t\t.config_aneg\t\t= en8811h_config_aneg,\n1549:\t\t.read_status\t\t= en8811h_read_status,\n1550:\t\t.resume\t\t\t= en8811h_resume,\n1551:\t\t.suspend\t\t= en8811h_suspend,\n1552:\t\t.config_intr\t\t= en8811h_clear_intr,\n1553:\t\t.handle_interrupt\t= en8811h_handle_interrupt,\n1554:\t\t.led_hw_is_supported\t= en8811h_led_hw_is_supported,\n1555:\t\t.read_page\t\t= air_phy_read_page,\n1556:\t\t.write_page\t\t= air_phy_write_page,\n1557:\t\t.led_blink_set\t\t= air_led_blink_set,\n1558:\t\t.led_brightness_set\t= air_led_brightness_set,\n1559:\t\t.led_hw_control_set\t= air_led_hw_control_set,\n1560:\t\t.led_hw_control_get\t= air_led_hw_control_get,\n1561:\t} };\n1562:\t\n1563:\tmodule_phy_driver(en8811h_driver);\n1564:\t\n1565:\tstatic const struct mdio_device_id __maybe_unused en8811h_tbl[] = {\n1566:\t\t{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },\n1567:\t\t{ PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID) },\n1568:\t\t{ }\n1569:\t};\n1570:\t\n1571:\tMODULE_DEVICE_TABLE(mdio, en8811h_tbl);\n1572:\tMODULE_FIRMWARE(EN8811H_MD32_DM);\n1573:\tMODULE_FIRMWARE(EN8811H_MD32_DSP);\n1574:\tMODULE_FIRMWARE(AN8811HB_MD32_DM);\n1575:\tMODULE_FIRMWARE(AN8811HB_MD32_DSP);\n1576:\t\n1577:\tMODULE_DESCRIPTION(\"Airoha EN8811H and AN8811HB PHY drivers\");\n1578:\tMODULE_AUTHOR(\"Airoha\");\n1579:\tMODULE_AUTHOR(\"Eric Woudstra \u003cericwouds@gmail.com\u003e\");\n"
}

gemini-3.7-flash

null

null

							input: 26864
							output: 41
							thoughts: 32
						

Here's my take:

**Investigating `air_write_buf` During Firmware Loading**

Okay, so `air_write_buf` pops up during the firmware loading process. That's interesting, and warrants a deeper dive. The first thing I need to do is map the call graph. Let's see who's actually *calling* this function. Knowing the context of those calls will be critical to understanding its purpose and potential implications. I need to trace the execution path and identify the points where data is being written, and why. This could be where the rubber meets the road in terms of flashing or initialization, or maybe it's just a diagnostic or logging function. Time to bust out the debugger and start digging!

{
  "Expression": "air_write_buf",
  "PathPrefix": "drivers/net/phy/air_en8811h.c"
}

{
  "Output": "drivers/net/phy/air_en8811h.c=248=static int __air_pbus_reg_write(struct mdio_device *mdiodev,\n--\ndrivers/net/phy/air_en8811h.c-272-\ndrivers/net/phy/air_en8811h.c:273:static int __air_write_buf(struct phy_device *phydev, u32 address,\ndrivers/net/phy/air_en8811h.c-274-\t\t\t   const struct firmware *fw)\n--\ndrivers/net/phy/air_en8811h.c-308-\ndrivers/net/phy/air_en8811h.c:309:static int air_write_buf(struct phy_device *phydev, u32 address,\ndrivers/net/phy/air_en8811h.c-310-\t\t\t const struct firmware *fw)\n--\ndrivers/net/phy/air_en8811h.c-323-\tif (saved_page \u003e= 0) {\ndrivers/net/phy/air_en8811h.c:324:\t\tret = __air_write_buf(phydev, address, fw);\ndrivers/net/phy/air_en8811h.c-325-\t\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c=403=static int an8811hb_load_file(struct phy_device *phydev, const char *name,\n--\ndrivers/net/phy/air_en8811h.c-413-\ndrivers/net/phy/air_en8811h.c:414:\tret = air_write_buf(phydev, address,  fw);\ndrivers/net/phy/air_en8811h.c-415-\trelease_firmware(fw);\n--\ndrivers/net/phy/air_en8811h.c=508=static int en8811h_load_firmware(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-532-\ndrivers/net/phy/air_en8811h.c:533:\tret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);\ndrivers/net/phy/air_en8811h.c-534-\tif (ret \u003c 0)\n--\ndrivers/net/phy/air_en8811h.c-536-\ndrivers/net/phy/air_en8811h.c:537:\tret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);\ndrivers/net/phy/air_en8811h.c-538-\tif (ret \u003c 0)\n"
}

gemini-3.7-flash

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							input: 27833
							output: 61
							thoughts: 34
						

**Tracing Function Calls: `an8811hb_load_file` and `en8811h_load_firmware`**

Okay, so I need to understand the execution flow surrounding `an8811hb_load_file` and `en8811h_load_firmware`. My immediate instinct is to identify every instance where these functions are *called* within the codebase. The goal here is to map out their dependencies and how they fit into the bigger picture. Are these core loading functions? Are they part of a larger firmware update process, or something else entirely? A simple call graph trace should provide those answers. From there, I'll be able to better understand the contexts these functions operate in and their potential implications. It's time to dig in and follow the breadcrumbs.

{
  "Expression": "(an8811hb_load_firmware|en8811h_load_firmware)",
  "PathPrefix": "drivers/net/phy/air_en8811h.c"
}

{
  "Output": "drivers/net/phy/air_en8811h.c=443=static int an8811hb_mcu_deassert(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-467-\ndrivers/net/phy/air_en8811h.c:468:static int an8811hb_load_firmware(struct phy_device *phydev)\ndrivers/net/phy/air_en8811h.c-469-{\n--\ndrivers/net/phy/air_en8811h.c-507-\ndrivers/net/phy/air_en8811h.c:508:static int en8811h_load_firmware(struct phy_device *phydev)\ndrivers/net/phy/air_en8811h.c-509-{\n--\ndrivers/net/phy/air_en8811h.c-519-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c:520:\t\tgoto en8811h_load_firmware_rel1;\ndrivers/net/phy/air_en8811h.c-521-\n--\ndrivers/net/phy/air_en8811h.c-524-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c:525:\t\tgoto en8811h_load_firmware_out;\ndrivers/net/phy/air_en8811h.c-526-\n--\ndrivers/net/phy/air_en8811h.c-530-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c:531:\t\tgoto en8811h_load_firmware_out;\ndrivers/net/phy/air_en8811h.c-532-\n--\ndrivers/net/phy/air_en8811h.c-534-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c:535:\t\tgoto en8811h_load_firmware_out;\ndrivers/net/phy/air_en8811h.c-536-\n--\ndrivers/net/phy/air_en8811h.c-538-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c:539:\t\tgoto en8811h_load_firmware_out;\ndrivers/net/phy/air_en8811h.c-540-\n--\ndrivers/net/phy/air_en8811h.c-543-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c:544:\t\tgoto en8811h_load_firmware_out;\ndrivers/net/phy/air_en8811h.c-545-\n--\ndrivers/net/phy/air_en8811h.c-547-\tif (ret \u003c 0)\ndrivers/net/phy/air_en8811h.c:548:\t\tgoto en8811h_load_firmware_out;\ndrivers/net/phy/air_en8811h.c-549-\n--\ndrivers/net/phy/air_en8811h.c-551-\ndrivers/net/phy/air_en8811h.c:552:en8811h_load_firmware_out:\ndrivers/net/phy/air_en8811h.c-553-\trelease_firmware(fw2);\ndrivers/net/phy/air_en8811h.c-554-\ndrivers/net/phy/air_en8811h.c:555:en8811h_load_firmware_rel1:\ndrivers/net/phy/air_en8811h.c-556-\trelease_firmware(fw1);\n--\ndrivers/net/phy/air_en8811h.c=1080=static int an8811hb_probe(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-1109-\ndrivers/net/phy/air_en8811h.c:1110:\tret = an8811hb_load_firmware(phydev);\ndrivers/net/phy/air_en8811h.c-1111-\tif (ret \u003c 0) {\n--\ndrivers/net/phy/air_en8811h.c=1151=static int en8811h_probe(struct phy_device *phydev)\n--\ndrivers/net/phy/air_en8811h.c-1161-\ndrivers/net/phy/air_en8811h.c:1162:\tret = en8811h_load_firmware(phydev);\ndrivers/net/phy/air_en8811h.c-1163-\tif (ret \u003c 0)\n"
}

gemini-3.7-flash

null

null

							input: 29448
							output: 146
							thoughts: 786
						

**Analysis of MDIO PHY Driver Reachability for Fuzzing**

Okay, let's break this down. The question is whether the `air_en8811h.c` driver, specifically the `AIR_EN8811H_PHY` component, is even *reachable* within standard virtualized environments. My immediate concern is this: does QEMU or Google Compute Engine, the go-to platforms for fuzzing, actually *emulate* the Airoha EN8811H / AN8811HB 2.5 Gigabit Ethernet PHY chip?

I'm thinking about the hardware requirements. This specific PHY chip relies on an MDIO bus for communication. I need to know if any virtual environment, like those used with syzkaller, has a virtual MDIO bus or emulates a device that would probe for this Airoha PHY with its specific ID (`0x03a2a411` or `0xc0ff04a0`).

From what I can tell, the answer is no. Standard QEMU setups use virtual network devices – e1000, virtio-net, etc. – but none of these even remotely resemble the Airoha EN8811H. This is a physical transceiver, a piece of actual hardware usually found on physical boards and routers, like those using MediaTek Filogic SoCs. Airoha, after all, is a MediaTek subsidiary and their chips are used in physical hardware.

Now, let's consult the triage guidelines on structurally unreachable hardware. It's clear: if the code *can't* execute in standard virtualized environments, it's a no-go for fuzzing. The guidelines explicitly mention vendor-specific hardware like PCIe switches, SmartNICs, or GPU drivers. This `air_en8811h.c` driver for a physical Ethernet PHY fits that description perfectly.

The fact is, this driver needs a physical Airoha PHY on an MDIO bus with a specific vendor ID. This is not something that is emulated in QEMU. That makes it structurally unreachable for our purposes.

I need to confirm this: I see that the patch modifies only the `air_en8811h.c` file and only the `air_write_buf()` function, where a check for `fw->size % 4` has been added. No other files are touched. The driver is enabled via `CONFIG_AIR_EN8811H_PHY`. The hardware dependency is the Airoha EN8811H/AN8811HB 2.5G Ethernet PHY. The key point is that its reachability is predicated on physical hardware on an MDIO bus, and therefore it is not reachable in QEMU.

Given all of this, the `WorthFuzzing` flag should absolutely be set to `false`. Let's prepare the reasoning, the required configs, and remember to leave the focus symbols empty, signaling that this isn't a fuzzing target.

Time to call `set-results`.

{
  "EnableConfigs": [
    "AIR_EN8811H_PHY"
  ],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies `air_write_buf` in `drivers/net/phy/air_en8811h.c`, which is a driver for the Airoha EN8811H and AN8811HB 2.5G Ethernet PHYs. This driver requires physical Airoha PHY hardware connected via MDIO, which is not emulated in standard virtualized fuzzing environments (QEMU/GCE). Therefore, the modified code is structurally unreachable.",
  "WorthFuzzing": false
}

{
  "EnableConfigs": [
    "AIR_EN8811H_PHY"
  ],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies `air_write_buf` in `drivers/net/phy/air_en8811h.c`, which is a driver for the Airoha EN8811H and AN8811HB 2.5G Ethernet PHYs. This driver requires physical Airoha PHY hardware connected via MDIO, which is not emulated in standard virtualized fuzzing environments (QEMU/GCE). Therefore, the modified code is structurally unreachable.",
  "WorthFuzzing": false
}

{
  "WorthFuzzing": false
}

null