| Seq | Timestamp | Type | Name | Duration |
|---|---|---|---|---|
| 0/0 | 2026/09/15 16:36 | flow | patch-triage |
3mArgs:null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"KMSANReasoning": "",
"NeedsKMSAN": false,
"Reasoning": "The patch series introduces driver support for the Airoha AN8855 Switch SoC (including MFD core over MDIO, internal PHY, and DSA switch platform driver) and refactors the MediaTek MT7530 DSA switch driver into a shared library (mt7530-lib.c). These drivers target physical network switch and PHY ASICs used on embedded networking hardware (probed via MDIO and Device Tree) which are not emulated in standard virtualized environments (QEMU/KVM or GCE). Consequently, the modified executable code is structurally unreachable for fuzzing.",
"WorthFuzzing": false
} |
| 1/1 | 2026/09/15 16:36 | action | read-patch-diff |
0mArgs:null Results: {
"PatchDiff": "commit 9c831e43060ed04707e416562042cde176308d6d\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate: Tue Sep 15 16:36:38 2026 +0000\n\n syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml\nnew file mode 100644\nindex 0000000000000..48127e956c965\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml\n@@ -0,0 +1,176 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Airoha AN8855 Switch SoC\n+\n+maintainers:\n+ - Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+\n+description: \u003e\n+ Airoha AN8855 Switch is a SoC that expose various peripherals like an\n+ Ethernet Switch, a NVMEM provider and Ethernet PHYs.\n+\n+ It does also support i2c and timers but those are not currently\n+ supported/used.\n+\n+properties:\n+ compatible:\n+ const: airoha,an8855\n+\n+ reg:\n+ maxItems: 1\n+\n+ reset-gpios:\n+ maxItems: 1\n+\n+ efuse:\n+ type: object\n+ $ref: /schemas/nvmem/airoha,an8855-efuse.yaml\n+ description: EFUSE exposed by the Airoha AN8855 SoC\n+\n+ ethernet-switch:\n+ type: object\n+ $ref: /schemas/net/dsa/airoha,an8855-switch.yaml\n+ description: Switch exposed by the Airoha AN8855 SoC\n+\n+ mdio:\n+ type: object\n+ $ref: /schemas/net/mdio.yaml#\n+ description: MDIO exposed by the Airoha AN8855 SoC\n+ unevaluatedProperties: false\n+\n+required:\n+ - compatible\n+ - reg\n+ - mdio\n+ - ethernet-switch\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include \u003cdt-bindings/gpio/gpio.h\u003e\n+\n+ mdio {\n+ #address-cells = \u003c1\u003e;\n+ #size-cells = \u003c0\u003e;\n+\n+ soc@1 {\n+ compatible = \"airoha,an8855\";\n+ reg = \u003c1\u003e;\n+\n+ reset-gpios = \u003c\u0026pio 39 GPIO_ACTIVE_HIGH\u003e;\n+\n+ efuse {\n+ compatible = \"airoha,an8855-efuse\";\n+\n+ #nvmem-cell-cells = \u003c0\u003e;\n+\n+ nvmem-layout {\n+ compatible = \"fixed-layout\";\n+ #address-cells = \u003c1\u003e;\n+ #size-cells = \u003c1\u003e;\n+\n+ shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {\n+ reg = \u003c0xc 0x4\u003e;\n+ };\n+\n+ shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {\n+ reg = \u003c0x10 0x4\u003e;\n+ };\n+\n+ shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {\n+ reg = \u003c0x14 0x4\u003e;\n+ };\n+\n+ shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {\n+ reg = \u003c0x18 0x4\u003e;\n+ };\n+\n+ shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {\n+ reg = \u003c0x1c 0x4\u003e;\n+ };\n+\n+ shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {\n+ reg = \u003c0x20 0x4\u003e;\n+ };\n+\n+ shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {\n+ reg = \u003c0x24 0x4\u003e;\n+ };\n+\n+ shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {\n+ reg = \u003c0x28 0x4\u003e;\n+ };\n+ };\n+ };\n+\n+ ethernet-switch {\n+ compatible = \"airoha,an8855-switch\";\n+\n+ ports {\n+ #address-cells = \u003c1\u003e;\n+ #size-cells = \u003c0\u003e;\n+\n+ port@0 {\n+ reg = \u003c0\u003e;\n+ label = \"lan1\";\n+ phy-mode = \"internal\";\n+ phy-handle = \u003c\u0026internal_phy1\u003e;\n+ };\n+\n+ port@1 {\n+ reg = \u003c1\u003e;\n+ label = \"lan2\";\n+ phy-mode = \"internal\";\n+ phy-handle = \u003c\u0026internal_phy2\u003e;\n+ };\n+\n+ port@5 {\n+ reg = \u003c5\u003e;\n+ label = \"cpu\";\n+ ethernet = \u003c\u0026gmac0\u003e;\n+ phy-mode = \"2500base-x\";\n+\n+ fixed-link {\n+ speed = \u003c2500\u003e;\n+ full-duplex;\n+ pause;\n+ };\n+ };\n+ };\n+ };\n+\n+ mdio {\n+ #address-cells = \u003c1\u003e;\n+ #size-cells = \u003c0\u003e;\n+\n+ internal_phy1: ethernet-phy@1 {\n+ compatible = \"ethernet-phy-idc0ff.0410\",\n+ \"ethernet-phy-ieee802.3-c22\";\n+ reg = \u003c1\u003e;\n+\n+ nvmem-cells = \u003c\u0026shift_sel_port0_tx_a\u003e,\n+ \u003c\u0026shift_sel_port0_tx_b\u003e,\n+ \u003c\u0026shift_sel_port0_tx_c\u003e,\n+ \u003c\u0026shift_sel_port0_tx_d\u003e;\n+ nvmem-cell-names = \"tx_a\", \"tx_b\", \"tx_c\", \"tx_d\";\n+ };\n+\n+ internal_phy2: ethernet-phy@2 {\n+ compatible = \"ethernet-phy-idc0ff.0410\",\n+ \"ethernet-phy-ieee802.3-c22\";\n+ reg = \u003c2\u003e;\n+\n+ nvmem-cells = \u003c\u0026shift_sel_port1_tx_a\u003e,\n+ \u003c\u0026shift_sel_port1_tx_b\u003e,\n+ \u003c\u0026shift_sel_port1_tx_c\u003e,\n+ \u003c\u0026shift_sel_port1_tx_d\u003e;\n+ nvmem-cell-names = \"tx_a\", \"tx_b\", \"tx_c\", \"tx_d\";\n+ };\n+ };\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml\nnew file mode 100644\nindex 0000000000000..d2f86116badf4\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml\n@@ -0,0 +1,83 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/airoha,an8855-phy.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Airoha AN8855 Switch Internal PHY\n+\n+maintainers:\n+ - Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+\n+description: \u003e\n+ Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal\n+ PHYs on the MDIO bus.\n+\n+ Each PHY might need to be calibrated to correctly work with the\n+ use of the eFUSE provided by the Switch SoC.\n+\n+allOf:\n+ - $ref: ethernet-phy.yaml#\n+\n+select:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - ethernet-phy-idc0ff.0410\n+ required:\n+ - compatible\n+\n+properties:\n+ reg:\n+ maxItems: 1\n+\n+ nvmem-cells:\n+ items:\n+ - description: phandle to SoC eFUSE tx_a\n+ - description: phandle to SoC eFUSE tx_b\n+ - description: phandle to SoC eFUSE tx_c\n+ - description: phandle to SoC eFUSE tx_d\n+\n+ nvmem-cell-names:\n+ items:\n+ - const: tx_a\n+ - const: tx_b\n+ - const: tx_c\n+ - const: tx_d\n+\n+required:\n+ - compatible\n+ - reg\n+\n+dependentRequired:\n+ nvmem-cells: [ nvmem-cell-names ]\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ mdio {\n+ #address-cells = \u003c1\u003e;\n+ #size-cells = \u003c0\u003e;\n+\n+ ethernet-phy@1 {\n+ compatible = \"ethernet-phy-idc0ff.0410\",\n+ \"ethernet-phy-ieee802.3-c45\";\n+\n+ reg = \u003c1\u003e;\n+ };\n+\n+ ethernet-phy@2 {\n+ compatible = \"ethernet-phy-idc0ff.0410\",\n+ \"ethernet-phy-ieee802.3-c45\";\n+\n+ reg = \u003c2\u003e;\n+\n+ nvmem-cells = \u003c\u0026shift_sel_port0_tx_a\u003e,\n+ \u003c\u0026shift_sel_port0_tx_b\u003e,\n+ \u003c\u0026shift_sel_port0_tx_c\u003e,\n+ \u003c\u0026shift_sel_port0_tx_d\u003e;\n+ nvmem-cell-names = \"tx_a\", \"tx_b\", \"tx_c\", \"tx_d\";\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml\nnew file mode 100644\nindex 0000000000000..5ad9b9e139831\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml\n@@ -0,0 +1,86 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Airoha AN8855 Gigabit Switch\n+\n+maintainers:\n+ - Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+\n+description: \u003e\n+ Airoha AN8855 is a 5-port Gigabit Switch.\n+\n+ It does expose the 5 Internal PHYs on the MDIO bus and each port\n+ can access the Switch register space by configuring the PHY page.\n+\n+$ref: dsa.yaml#/$defs/ethernet-ports\n+\n+properties:\n+ compatible:\n+ const: airoha,an8855-switch\n+\n+required:\n+ - compatible\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ ethernet-switch {\n+ compatible = \"airoha,an8855-switch\";\n+\n+ ports {\n+ #address-cells = \u003c1\u003e;\n+ #size-cells = \u003c0\u003e;\n+\n+ port@0 {\n+ reg = \u003c0\u003e;\n+ label = \"lan1\";\n+ phy-mode = \"internal\";\n+ phy-handle = \u003c\u0026internal_phy1\u003e;\n+ };\n+\n+ port@1 {\n+ reg = \u003c1\u003e;\n+ label = \"lan2\";\n+ phy-mode = \"internal\";\n+ phy-handle = \u003c\u0026internal_phy2\u003e;\n+ };\n+\n+ port@2 {\n+ reg = \u003c2\u003e;\n+ label = \"lan3\";\n+ phy-mode = \"internal\";\n+ phy-handle = \u003c\u0026internal_phy3\u003e;\n+ };\n+\n+ port@3 {\n+ reg = \u003c3\u003e;\n+ label = \"lan4\";\n+ phy-mode = \"internal\";\n+ phy-handle = \u003c\u0026internal_phy4\u003e;\n+ };\n+\n+ port@4 {\n+ reg = \u003c4\u003e;\n+ label = \"wan\";\n+ phy-mode = \"internal\";\n+ phy-handle = \u003c\u0026internal_phy5\u003e;\n+ };\n+\n+ port@5 {\n+ reg = \u003c5\u003e;\n+ label = \"cpu\";\n+ ethernet = \u003c\u0026gmac0\u003e;\n+ phy-mode = \"2500base-x\";\n+\n+ fixed-link {\n+ speed = \u003c2500\u003e;\n+ full-duplex;\n+ pause;\n+ };\n+ };\n+ };\n+ };\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex 0e04d92d1b098..afe9d363ddf4a 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -759,6 +759,22 @@ S:\tMaintained\n F:\tDocumentation/devicetree/bindings/net/airoha,en7581-eth.yaml\n F:\tdrivers/net/ethernet/airoha/\n \n+AIROHA AN8855 DSA DRIVER\n+M:\tChristian Marangi \u003cansuelsmth@gmail.com\u003e\n+L:\tlinux-arm-kernel@lists.infradead.org (moderated for non-subscribers)\n+L:\tlinux-mediatek@lists.infradead.org (moderated for non-subscribers)\n+L:\tnetdev@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml\n+F:\tDocumentation/devicetree/bindings/net/airoha,an8855-phy.yaml\n+F:\tDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml\n+F:\tDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml\n+F:\tdrivers/mfd/airoha-an8855.c\n+F:\tdrivers/net/dsa/an8855.c\n+F:\tdrivers/net/dsa/an8855.h\n+F:\tdrivers/net/phy/air_an8855.c\n+F:\tdrivers/nvmem/an8855-efuse.c\n+\n AIROHA PCIE PHY DRIVER\n M:\tLorenzo Bianconi \u003clorenzo@kernel.org\u003e\n L:\tlinux-arm-kernel@lists.infradead.org (moderated for non-subscribers)\ndiff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig\nindex e4fd4572472f9..afbdcec0fce8f 100644\n--- a/drivers/mfd/Kconfig\n+++ b/drivers/mfd/Kconfig\n@@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR\n \t using regmap_mmio accesses for ARM32 parts and SMC calls to\n \t EL3 for ARM64 parts.\n \n+config MFD_AIROHA_AN8855\n+\ttristate \"Airoha AN8855 Switch Core\"\n+\tselect MFD_CORE\n+\tselect REGMAP\n+\tselect PHYLIB\n+\tselect MDIO_REGMAP\n+\tdepends on NETDEVICES \u0026\u0026 OF\n+\thelp\n+\t Support for the Airoha AN8855 Switch Core. This is an SoC\n+\t that provides various peripherals, to count, i2c, an Ethrnet\n+\t Switch, a CPU timer, GPIO, eFUSE.\n+\n+\t Currently it provides a DSA switch and a NVMEM provider.\n+\n config MFD_ACT8945A\n \ttristate \"Active-semi ACT8945A\"\n \tselect MFD_CORE\ndiff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile\nindex 72d3944b0ad8e..484127dba2ad7 100644\n--- a/drivers/mfd/Makefile\n+++ b/drivers/mfd/Makefile\n@@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X)\t+= 88pm860x.o\n obj-$(CONFIG_MFD_88PM800)\t+= 88pm800.o 88pm80x.o\n obj-$(CONFIG_MFD_88PM805)\t+= 88pm805.o 88pm80x.o\n obj-$(CONFIG_MFD_88PM886_PMIC)\t+= 88pm886.o\n+obj-$(CONFIG_MFD_AIROHA_AN8855)\t+= airoha-an8855.o\n obj-$(CONFIG_MFD_ACT8945A)\t+= act8945a.o\n obj-$(CONFIG_MFD_SM501)\t\t+= sm501.o\n obj-$(CONFIG_ARCH_BCM2835)\t+= bcm2835-pm.o\ndiff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c\nnew file mode 100644\nindex 0000000000000..2b3b5f4a5a21e\n--- /dev/null\n+++ b/drivers/mfd/airoha-an8855.c\n@@ -0,0 +1,557 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Core driver for Airoha AN8855 Switch\n+ *\n+ * Copyright (C) 2024 Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+\n+#include \u003clinux/bitfield.h\u003e\n+#include \u003clinux/fwnode_mdio.h\u003e\n+#include \u003clinux/gpio/consumer.h\u003e\n+#include \u003clinux/mfd/core.h\u003e\n+#include \u003clinux/mdio.h\u003e\n+#include \u003clinux/mdio/mdio-regmap.h\u003e\n+#include \u003clinux/module.h\u003e\n+#include \u003clinux/of.h\u003e\n+#include \u003clinux/phy.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+\n+/* Register for HW trap status */\n+#define AN8855_HWTRAP\t\t\t0x1000009c\n+\n+/*\n+ * Register of the Switch ID\n+ * (called Project ID in Documentation)\n+ */\n+#define AN8855_CREV\t\t\t0x10005000\n+#define AN8855_ID\t\t\t0x8855 /* Switch ID */\n+\n+/* Register for GPHY Power Down\n+ * Used to Toggle the Gigabit PHY power and enable them.\n+ */\n+#define AN8855_RG_GPHY_AFE_PWD\t\t0x1028c840\n+\n+/* MII Registers */\n+#define AN8855_PHY_SELECT_PAGE\t\t0x1f\n+#define AN8855_PHY_PAGE\t\tGENMASK(2, 0)\n+#define AN8855_PHY_PAGE_STANDARD\tFIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)\n+#define AN8855_PHY_PAGE_EXTENDED_1\tFIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)\n+#define AN8855_PHY_PAGE_EXTENDED_4\tFIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)\n+\n+/* MII Registers Page 4 */\n+#define AN8855_PBUS_MODE\t\t0x10\n+#define AN8855_PBUS_MODE_ADDR_FIXED\t0x0\n+#define AN8855_PBUS_MODE_ADDR_INCR\tBIT(15)\n+#define AN8855_PBUS_WR_ADDR_HIGH\t0x11\n+#define AN8855_PBUS_WR_ADDR_LOW\t\t0x12\n+#define AN8855_PBUS_WR_DATA_HIGH\t0x13\n+#define AN8855_PBUS_WR_DATA_LOW\t\t0x14\n+#define AN8855_PBUS_RD_ADDR_HIGH\t0x15\n+#define AN8855_PBUS_RD_ADDR_LOW\t\t0x16\n+#define AN8855_PBUS_RD_DATA_HIGH\t0x17\n+#define AN8855_PBUS_RD_DATA_LOW\t\t0x18\n+\n+#define AN8855_MAX_PHY_PORT\t\t5\n+\n+struct an8855_core_priv {\n+\tstruct mii_bus *bus;\n+\tstruct mii_bus *phy_bus;\n+\tunsigned int switch_addr;\n+\tu16 current_page;\n+};\n+\n+struct an8855_phy_priv {\n+\tu8 addr;\n+\tstruct an8855_core_priv *core;\n+};\n+\n+struct an8855_phy_bus {\n+\tstruct mii_bus *bus;\n+\tstruct fwnode_handle *node;\n+\tu8 addr;\n+};\n+\n+static const struct mfd_cell an8855_cells[] = {\n+\tMFD_CELL_OF(\"an8855-efuse\", NULL, NULL, 0, 0,\n+\t\t \"airoha,an8855-efuse\"),\n+\tMFD_CELL_OF(\"an8855-switch\", NULL, NULL, 0, 0,\n+\t\t \"airoha,an8855-switch\"),\n+};\n+\n+static int an8855_mii_set_page(struct an8855_core_priv *priv, u8 addr,\n+\t\t\t u8 page) __must_hold(\u0026priv-\u003ebus-\u003emdio_lock)\n+{\n+\tstruct mii_bus *bus = priv-\u003ebus;\n+\tint ret;\n+\n+\tret = __mdiobus_write(bus, addr, AN8855_PHY_SELECT_PAGE, page);\n+\tif (ret) {\n+\t\tdev_err_ratelimited(\u0026bus-\u003edev, \"failed to set mii page\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Cache current page if next MII read/write is for Switch page */\n+\tpriv-\u003ecurrent_page = page;\n+\treturn 0;\n+}\n+\n+static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,\n+\t\t\t u32 *val) __must_hold(\u0026bus-\u003emdio_lock)\n+{\n+\tint lo, hi, ret;\n+\n+\tret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,\n+\t\t\t AN8855_PBUS_MODE_ADDR_FIXED);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,\n+\t\t\t upper_16_bits(reg));\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,\n+\t\t\t lower_16_bits(reg));\n+\tif (ret)\n+\t\tgoto err;\n+\n+\thi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);\n+\tif (hi \u003c 0) {\n+\t\tret = hi;\n+\t\tgoto err;\n+\t}\n+\n+\tlo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);\n+\tif (lo \u003c 0) {\n+\t\tret = lo;\n+\t\tgoto err;\n+\t}\n+\n+\t*val = ((u32)hi \u003c\u003c 16) | lo;\n+\n+\treturn 0;\n+err:\n+\tdev_err_ratelimited(\u0026bus-\u003edev, \"failed to read register\\n\");\n+\treturn ret;\n+}\n+\n+/*\n+ * Protect concurrent access to phy page if switch address also\n+ * expose a PHY.\n+ */\n+static void an8855_regmap_lock(struct an8855_core_priv *priv)\n+{\n+\tif (priv-\u003ephy_bus)\n+\t\tmutex_lock(\u0026priv-\u003ephy_bus-\u003emdio_lock);\n+\tmutex_lock_nested(\u0026priv-\u003ebus-\u003emdio_lock, MDIO_MUTEX_NESTED);\n+}\n+\n+static void an8855_regmap_unlock(struct an8855_core_priv *priv)\n+{\n+\tmutex_unlock(\u0026priv-\u003ebus-\u003emdio_lock);\n+\tif (priv-\u003ephy_bus)\n+\t\tmutex_unlock(\u0026priv-\u003ephy_bus-\u003emdio_lock);\n+}\n+\n+static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n+{\n+\tstruct an8855_core_priv *priv = ctx;\n+\tstruct mii_bus *bus = priv-\u003ebus;\n+\tu16 addr = priv-\u003eswitch_addr;\n+\tint ret;\n+\n+\tan8855_regmap_lock(priv);\n+\tret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);\n+\tif (ret \u003c 0)\n+\t\tgoto exit;\n+\n+\tret = an8855_mii_read32(bus, addr, reg, val);\n+\n+exit:\n+\tan8855_regmap_unlock(priv);\n+\n+\treturn ret \u003c 0 ? ret : 0;\n+}\n+\n+static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,\n+\t\t\t u32 val) __must_hold(\u0026bus-\u003emdio_lock)\n+{\n+\tint ret;\n+\n+\tret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,\n+\t\t\t AN8855_PBUS_MODE_ADDR_FIXED);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,\n+\t\t\t upper_16_bits(reg));\n+\tif (ret)\n+\t\tgoto err;\n+\tret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,\n+\t\t\t lower_16_bits(reg));\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,\n+\t\t\t upper_16_bits(val));\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,\n+\t\t\t lower_16_bits(val));\n+\tif (ret)\n+\t\tgoto err;\n+\n+\treturn 0;\n+err:\n+\tdev_err_ratelimited(\u0026bus-\u003edev,\n+\t\t\t \"failed to write an8855 register\\n\");\n+\treturn ret;\n+}\n+\n+static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)\n+{\n+\tstruct an8855_core_priv *priv = ctx;\n+\tstruct mii_bus *bus = priv-\u003ebus;\n+\tu16 addr = priv-\u003eswitch_addr;\n+\tint ret;\n+\n+\tan8855_regmap_lock(priv);\n+\tret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tret = an8855_mii_write32(bus, addr, reg, val);\n+\n+exit:\n+\tan8855_regmap_unlock(priv);\n+\n+\treturn ret \u003c 0 ? ret : 0;\n+}\n+\n+static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,\n+\t\t\t\t uint32_t write_val)\n+{\n+\tstruct an8855_core_priv *priv = ctx;\n+\tstruct mii_bus *bus = priv-\u003ebus;\n+\tu16 addr = priv-\u003eswitch_addr;\n+\tu32 val;\n+\tint ret;\n+\n+\tan8855_regmap_lock(priv);\n+\tret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tret = an8855_mii_read32(bus, addr, reg, \u0026val);\n+\tif (ret \u003c 0)\n+\t\tgoto exit;\n+\n+\tval \u0026= ~mask;\n+\tval |= write_val \u0026 mask;\n+\tret = an8855_mii_write32(bus, addr, reg, val);\n+\n+exit:\n+\tan8855_regmap_unlock(priv);\n+\n+\treturn ret \u003c 0 ? ret : 0;\n+}\n+\n+static const struct regmap_range an8855_readable_ranges[] = {\n+\tregmap_reg_range(0x10000000, 0x10000fff), /* SCU */\n+\tregmap_reg_range(0x10001000, 0x10001fff), /* RBUS */\n+\tregmap_reg_range(0x10002000, 0x10002fff), /* MCU */\n+\tregmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */\n+\tregmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */\n+\tregmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */\n+\tregmap_reg_range(0x10009000, 0x10009fff), /* PDMA */\n+\tregmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */\n+\tregmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */\n+\tregmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */\n+\tregmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */\n+\tregmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */\n+\tregmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */\n+\tregmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */\n+\tregmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */\n+\tregmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */\n+\tregmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */\n+\tregmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */\n+\tregmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */\n+\tregmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */\n+\tregmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */\n+\tregmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */\n+\tregmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */\n+\tregmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */\n+\tregmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */\n+\tregmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */\n+\tregmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */\n+};\n+\n+static const struct regmap_access_table an8855_readable_table = {\n+\t.yes_ranges = an8855_readable_ranges,\n+\t.n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),\n+};\n+\n+static const struct regmap_config an8855_regmap_config = {\n+\t.name = \"switch\",\n+\t.reg_bits = 32,\n+\t.val_bits = 32,\n+\t.reg_stride = 4,\n+\t.max_register = 0xbfffffff,\n+\t.reg_read = an8855_regmap_read,\n+\t.reg_write = an8855_regmap_write,\n+\t.reg_update_bits = an8855_regmap_update_bits,\n+\t.disable_locking = true,\n+\t.rd_table = \u0026an8855_readable_table,\n+};\n+\n+static int an8855_regmap_phy_reset_page(struct an8855_core_priv *priv,\n+\t\t\t\t\tint phy) __must_hold(\u0026priv-\u003ebus-\u003emdio_lock)\n+{\n+\t/* Check PHY page only for addr shared with switch */\n+\tif (phy != priv-\u003eswitch_addr)\n+\t\treturn 0;\n+\n+\t/* Don't restore page if it's not set to Switch page */\n+\tif (priv-\u003ecurrent_page != AN8855_PHY_PAGE_EXTENDED_4)\n+\t\treturn 0;\n+\n+\t/*\n+\t * Restore page to 0, PHY might change page right after but that\n+\t * will be ignored as it won't be a switch page.\n+\t */\n+\treturn an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);\n+}\n+\n+static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val)\n+{\n+\tstruct an8855_phy_priv *priv = ctx;\n+\tstruct an8855_core_priv *core_priv;\n+\tu32 addr = priv-\u003eaddr;\n+\tstruct mii_bus *bus;\n+\tint ret;\n+\n+\tcore_priv = priv-\u003ecore;\n+\tbus = core_priv-\u003ebus;\n+\n+\tmutex_lock_nested(\u0026bus-\u003emdio_lock, MDIO_MUTEX_NESTED);\n+\tret = an8855_regmap_phy_reset_page(core_priv, addr);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tret = __mdiobus_read(bus, addr, reg);\n+\tif (ret \u003e= 0)\n+\t\t*val = ret;\n+\n+exit:\n+\tmutex_unlock(\u0026bus-\u003emdio_lock);\n+\n+\treturn ret \u003c 0 ? ret : 0;\n+}\n+\n+static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val)\n+{\n+\tstruct an8855_phy_priv *priv = ctx;\n+\tstruct an8855_core_priv *core_priv;\n+\tu32 addr = priv-\u003eaddr;\n+\tstruct mii_bus *bus;\n+\tint ret;\n+\n+\tcore_priv = priv-\u003ecore;\n+\tbus = core_priv-\u003ebus;\n+\n+\tmutex_lock_nested(\u0026bus-\u003emdio_lock, MDIO_MUTEX_NESTED);\n+\tret = an8855_regmap_phy_reset_page(core_priv, addr);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tret = __mdiobus_write(bus, addr, reg, val);\n+\n+exit:\n+\tmutex_unlock(\u0026bus-\u003emdio_lock);\n+\n+\treturn ret;\n+}\n+\n+static const struct regmap_config an8855_phy_regmap_config = {\n+\t.reg_bits = 16,\n+\t.val_bits = 16,\n+\t.reg_read = an8855_regmap_phy_read,\n+\t.reg_write = an8855_regmap_phy_write,\n+\t.disable_locking = true,\n+\t.max_register = 0x1f,\n+};\n+\n+static int an8855_read_switch_id(struct device *dev, struct regmap *regmap)\n+{\n+\tu32 id;\n+\tint ret;\n+\n+\tret = regmap_read(regmap, AN8855_CREV, \u0026id);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (id != AN8855_ID) {\n+\t\tdev_err(dev, \"Detected Switch ID %x but %x was expected\\n\",\n+\t\t\tid, AN8855_ID);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int an8855_phy_bus_register(struct device *dev, struct an8855_core_priv *priv,\n+\t\t\t\t struct device_node *phy_np,\n+\t\t\t\t struct an8855_phy_bus *phy_bus_info)\n+{\n+\tstruct mdio_regmap_config mrc = { };\n+\tstruct an8855_phy_priv *phy_priv;\n+\tstruct regmap *regmap;\n+\tu32 addr, phy_offset;\n+\tstruct mii_bus *bus;\n+\tint ret;\n+\n+\tret = of_property_read_u32(phy_np, \"reg\", \u0026addr);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tphy_offset = addr - priv-\u003eswitch_addr;\n+\tif (phy_offset \u003e= AN8855_MAX_PHY_PORT)\n+\t\treturn -EINVAL;\n+\n+\tphy_priv = devm_kzalloc(dev, sizeof(*phy_priv), GFP_KERNEL);\n+\tif (!phy_priv)\n+\t\treturn -ENOMEM;\n+\n+\tphy_priv-\u003eaddr = addr;\n+\tphy_priv-\u003ecore = priv;\n+\n+\tregmap = devm_regmap_init(dev, NULL, phy_priv, \u0026an8855_phy_regmap_config);\n+\tif (IS_ERR(regmap))\n+\t\treturn dev_err_probe(dev, PTR_ERR(regmap),\n+\t\t\t\t \"phy%d regmap initialization failed\\n\",\n+\t\t\t\t addr);\n+\n+\tmrc.regmap = regmap;\n+\tmrc.parent = dev;\n+\tmrc.valid_addr = addr;\n+\tsnprintf(mrc.name, MII_BUS_ID_SIZE, \"%s-phy%d\", priv-\u003ebus-\u003eid, addr);\n+\n+\tbus = devm_mdio_regmap_register(dev, \u0026mrc);\n+\tif (IS_ERR(bus))\n+\t\treturn PTR_ERR(bus);\n+\n+\tif (addr == priv-\u003eswitch_addr)\n+\t\tpriv-\u003ephy_bus = bus;\n+\n+\tphy_bus_info-\u003ebus = bus;\n+\tphy_bus_info-\u003eaddr = addr;\n+\tphy_bus_info-\u003enode = of_fwnode_handle(phy_np);\n+\n+\treturn 0;\n+}\n+\n+static int an8855_mdio_register(struct device *dev, struct an8855_core_priv *priv,\n+\t\t\t\tstruct an8855_phy_bus *phy_bus_infos)\n+{\n+\tstruct device_node *mdio_np;\n+\tint ret = 0;\n+\tint i = 0;\n+\n+\tmdio_np = of_get_child_by_name(dev-\u003eof_node, \"mdio\");\n+\tif (!mdio_np)\n+\t\treturn -ENODEV;\n+\n+\tfor_each_available_child_of_node_scoped(mdio_np, phy_np) {\n+\t\tif (i \u003e= AN8855_MAX_PHY_PORT)\n+\t\t\treturn -EINVAL;\n+\n+\t\tret = an8855_phy_bus_register(dev, priv, phy_np,\n+\t\t\t\t\t \u0026phy_bus_infos[i]);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\ti++;\n+\t}\n+\n+\tof_node_put(mdio_np);\n+\treturn ret ? ret : i;\n+}\n+\n+static int an8855_core_probe(struct mdio_device *mdiodev)\n+{\n+\tstruct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { };\n+\tstruct device *dev = \u0026mdiodev-\u003edev;\n+\tstruct an8855_core_priv *priv;\n+\tstruct regmap *regmap;\n+\tint num_phys;\n+\tint i, ret;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv-\u003ebus = mdiodev-\u003ebus;\n+\tpriv-\u003eswitch_addr = mdiodev-\u003eaddr;\n+\t/* No DMA for mdiobus, mute warning for DMA mask not set */\n+\tdev-\u003edma_mask = \u0026dev-\u003ecoherent_dma_mask;\n+\n+\t/* Register virtual MDIO for each PHY */\n+\tnum_phys = an8855_mdio_register(dev, priv, phy_bus_infos);\n+\tif (num_phys \u003c 0)\n+\t\treturn num_phys;\n+\n+\tregmap = devm_regmap_init(dev, NULL, priv, \u0026an8855_regmap_config);\n+\tif (IS_ERR(regmap))\n+\t\treturn dev_err_probe(dev, PTR_ERR(regmap),\n+\t\t\t\t \"regmap initialization failed\\n\");\n+\n+\t/* Reset PHY page for switch address */\n+\tmutex_lock_nested(\u0026priv-\u003ebus-\u003emdio_lock, MDIO_MUTEX_NESTED);\n+\tret = an8855_mii_set_page(priv, priv-\u003eswitch_addr,\n+\t\t\t\t AN8855_PHY_PAGE_STANDARD);\n+\tmutex_unlock(\u0026priv-\u003ebus-\u003emdio_lock);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = an8855_read_switch_id(dev, regmap);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Release global PHY power down */\n+\tret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Register PHYs */\n+\tfor (i = 0; i \u003c num_phys; i++) {\n+\t\tret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,\n+\t\t\t\t\t\t phy_bus_infos[i].node,\n+\t\t\t\t\t\t phy_bus_infos[i].addr);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,\n+\t\t\t\t ARRAY_SIZE(an8855_cells), NULL, 0,\n+\t\t\t\t NULL);\n+}\n+\n+static const struct of_device_id an8855_core_of_match[] = {\n+\t{ .compatible = \"airoha,an8855\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, an8855_core_of_match);\n+\n+static struct mdio_driver an8855_core_driver = {\n+\t.probe = an8855_core_probe,\n+\t.mdiodrv.driver = {\n+\t\t.name = \"an8855\",\n+\t\t.of_match_table = an8855_core_of_match,\n+\t},\n+};\n+mdio_module_driver(an8855_core_driver);\n+\n+MODULE_AUTHOR(\"Christian Marangi \u003cansuelsmth@gmail.com\u003e\");\n+MODULE_DESCRIPTION(\"Driver for Airoha AN8855\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig\nindex 8d8edcf89f107..161331535061e 100644\n--- a/drivers/net/dsa/Kconfig\n+++ b/drivers/net/dsa/Kconfig\n@@ -24,12 +24,25 @@ config NET_DSA_LOOP\n \t This enables support for a fake mock-up switch chip which\n \t exercises the DSA APIs.\n \n+config NET_DSA_AN8855\n+\ttristate \"Airoha AN8855 Ethernet switch support\"\n+\tdepends on MFD_AIROHA_AN8855 || COMPILE_TEST\n+\tdepends on NET_DSA\n+\tselect NET_DSA_TAG_AIROHA\n+\thelp\n+\t This enables support for the Ethernet switch inside the\n+\t Airoha AN8855 chip.\n+\n source \"drivers/net/dsa/hirschmann/Kconfig\"\n \n source \"drivers/net/dsa/lantiq/Kconfig\"\n \n+config NET_DSA_MT7530_LIB\n+\ttristate\n+\n config NET_DSA_MT7530\n \ttristate \"MediaTek MT7530 and MT7531 Ethernet switch support\"\n+\tselect NET_DSA_MT7530_LIB\n \tselect NET_DSA_TAG_MTK\n \tselect REGMAP_IRQ\n \timply NET_DSA_MT7530_MDIO\ndiff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile\nindex df849cd0e640e..9ec109da3c414 100644\n--- a/drivers/net/dsa/Makefile\n+++ b/drivers/net/dsa/Makefile\n@@ -1,9 +1,11 @@\n # SPDX-License-Identifier: GPL-2.0\n+obj-$(CONFIG_NET_DSA_AN8855)\t+= an8855.o\n obj-$(CONFIG_NET_DSA_BCM_SF2)\t+= bcm-sf2.o\n bcm-sf2-objs\t\t\t:= bcm_sf2.o bcm_sf2_cfp.o\n obj-$(CONFIG_NET_DSA_LOOP)\t+= dsa_loop.o\n obj-$(CONFIG_NET_DSA_KS8995) \t+= ks8995.o\n obj-$(CONFIG_NET_DSA_MT7530)\t+= mt7530.o\n+obj-$(CONFIG_NET_DSA_MT7530_LIB) += mt7530-lib.o\n obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o\n obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o\n obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o\ndiff --git a/drivers/net/dsa/an8855.c b/drivers/net/dsa/an8855.c\nnew file mode 100644\nindex 0000000000000..e3cd4bd80c6aa\n--- /dev/null\n+++ b/drivers/net/dsa/an8855.c\n@@ -0,0 +1,1740 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Airoha AN8855 DSA Switch driver\n+ * Copyright (C) 2023 Min Yao \u003cmin.yao@airoha.com\u003e\n+ * Copyright (C) 2024 Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+#include \u003clinux/bitfield.h\u003e\n+#include \u003clinux/ethtool.h\u003e\n+#include \u003clinux/etherdevice.h\u003e\n+#include \u003clinux/if_bridge.h\u003e\n+#include \u003clinux/iopoll.h\u003e\n+#include \u003clinux/netdevice.h\u003e\n+#include \u003clinux/of_net.h\u003e\n+#include \u003clinux/of_platform.h\u003e\n+#include \u003clinux/phylink.h\u003e\n+#include \u003clinux/platform_device.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+#include \u003cnet/dsa.h\u003e\n+\n+#include \"an8855.h\"\n+#include \"mt7530-lib.h\"\n+\n+static const struct mt7530_reg_field an8855_fields[] = {\n+\t{ MT7530_BC_FFP, REG_FIELD(AN8855_BCF, 0, 7) },\n+\t{ MT7530_UNM_FFP, REG_FIELD(AN8855_UNMF, 0, 7) },\n+\t{ MT7530_UNU_FFP, REG_FIELD(AN8855_UNUF, 0, 7) },\n+\n+\t{ MT7530_CCR_MIB_ENABLE, REG_FIELD(AN8855_MIB_CCR, 31, 31) },\n+\t{ MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 7, 7) },\n+\t{ MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 6, 6) },\n+\t{ MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 5, 5) },\n+\t{ MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 4, 4) },\n+\n+\t{ MT7530_BPDU_EG_TAG, REG_FIELD(AN8855_BPC, 9, 11) },\n+\t{ MT7530_BPDU_PORT_FW, REG_FIELD(AN8855_BPC, 0, 2) },\n+\t{ MT7530_PAE_BPDU_FR, REG_FIELD(AN8855_PAC, 28, 28) },\n+\t{ MT7530_PAE_EG_TAG, REG_FIELD(AN8855_PAC, 25, 27) },\n+\t{ MT7530_PAE_PORT_FW, REG_FIELD(AN8855_PAC, 16, 18) },\n+\t{ MT7530_R01_BPDU_FR, REG_FIELD(AN8855_RGAC1, 12, 12) },\n+\t{ MT7530_R01_EG_TAG, REG_FIELD(AN8855_RGAC1, 9, 11) },\n+\t{ MT7530_R01_PORT_FW, REG_FIELD(AN8855_RGAC1, 0, 2) },\n+\t{ MT7530_R02_BPDU_FR, REG_FIELD(AN8855_RGAC1, 28, 28) },\n+\t{ MT7530_R02_EG_TAG, REG_FIELD(AN8855_RGAC1, 25, 27) },\n+\t{ MT7530_R02_PORT_FW, REG_FIELD(AN8855_RGAC1, 16, 18) },\n+\t{ MT7530_R03_BPDU_FR, REG_FIELD(AN8855_RGAC2, 12, 12) },\n+\t{ MT7530_R03_EG_TAG, REG_FIELD(AN8855_RGAC2, 9, 11) },\n+\t{ MT7530_R03_PORT_FW, REG_FIELD(AN8855_RGAC2, 0, 2) },\n+\t{ MT7530_R0E_BPDU_FR, REG_FIELD(AN8855_RGAC2, 28, 28) },\n+\t{ MT7530_R0E_EG_TAG, REG_FIELD(AN8855_RGAC2, 25, 27) },\n+\t{ MT7530_R0E_PORT_FW, REG_FIELD(AN8855_RGAC2, 16, 18) },\n+\n+\t{ MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) },\n+\t{ MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) },\n+\t{ MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) },\n+\t{ MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) },\n+\t{ MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) },\n+\t{ MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) },\n+\t{ __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) },\n+\n+\t{ MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) },\n+\t{ __MT7530_VAWD2, REG_FIELD(AN8855_VAWD1, 0, 31) },\n+\n+\t{ MT7530_VTCR_BUSY, REG_FIELD(AN8855_VTCR, 31, 31) },\n+\t{ MT7530_VTCR_FUNC, REG_FIELD(AN8855_VTCR, 12, 15) },\n+\t{ MT7530_VTCR_VID, REG_FIELD(AN8855_VTCR, 0, 11) },\n+\n+\t{ MT7530_ATWD_CVID, REG_FIELD(AN8855_ATWD, 16, 27), },\n+\t{ MT7530_ATWD_IVL, REG_FIELD(AN8855_ATWD, 15, 15), },\n+\t{ MT7530_ATWD_FID, REG_FIELD(AN8855_ATWD, 28, 31), },\n+\t{ MT7530_ATWD_AGE_TIMER, REG_FIELD(AN8855_ATA2, 0, 8), },\n+\t{ MT7530_ATWD_PORT_MAP, REG_FIELD(AN8855_ATWD2, 0, 7), },\n+\t{ AN8855_ATWD_TYPE, REG_FIELD(AN8855_ATA2, 9, 9), },\n+\t{ AN8855_ATWD_VLD, REG_FIELD(AN8855_ATWD, 0, 0), },\n+\t{ MT7530_ATWD_MAC_BYTE_5, REG_FIELD(AN8855_ATA2, 16, 23), },\n+\t{ MT7530_ATWD_MAC_BYTE_4, REG_FIELD(AN8855_ATA2, 24, 31), },\n+\t{ MT7530_ATWD_MAC_BYTE_3, REG_FIELD(AN8855_ATA1, 0, 7), },\n+\t{ MT7530_ATWD_MAC_BYTE_2, REG_FIELD(AN8855_ATA1, 8, 15), },\n+\t{ MT7530_ATWD_MAC_BYTE_1, REG_FIELD(AN8855_ATA1, 16, 23), },\n+\t{ MT7530_ATWD_MAC_BYTE_0, REG_FIELD(AN8855_ATA1, 24, 31), },\n+\n+\t{ __MT7530_ATWD1, REG_FIELD(AN8855_ATWD, 0, 31), },\n+\t{ __MT7530_ATWD2, REG_FIELD(AN8855_ATWD2, 0, 31), },\n+\t{ __MT7530_ATWD3, REG_FIELD(AN8855_ATA1, 0, 31), },\n+\t{ __MT7530_ATWD4, REG_FIELD(AN8855_ATA2, 0, 31), },\n+\n+\t{ MT7530_ATRD_CVID, REG_FIELD(AN8855_ATRD0, 10, 21), },\n+\t{ MT7530_ATRD_AGE_TIMER, REG_FIELD(AN8855_ATRD1, 3, 11), },\n+\t{ MT7530_ATRD_PORT_MAP, REG_FIELD(AN8855_ATRD3, 0, 7), },\n+\t{ AN8855_ATRD_ARP, REG_FIELD(AN8855_ATRD0, 1, 2), },\n+\t{ MT7530_ATRD_MAC_BYTE_5, REG_FIELD(AN8855_ATRD1, 16, 23), },\n+\t{ MT7530_ATRD_MAC_BYTE_4, REG_FIELD(AN8855_ATRD1, 24, 31), },\n+\t{ MT7530_ATRD_MAC_BYTE_3, REG_FIELD(AN8855_ATRD2, 0, 7), },\n+\t{ MT7530_ATRD_MAC_BYTE_2, REG_FIELD(AN8855_ATRD2, 8, 15), },\n+\t{ MT7530_ATRD_MAC_BYTE_1, REG_FIELD(AN8855_ATRD2, 16, 23), },\n+\t{ MT7530_ATRD_MAC_BYTE_0, REG_FIELD(AN8855_ATRD2, 24, 31), },\n+\n+\t{ MT7530_ATC_BUSY, REG_FIELD(AN8855_ATC, 31, 31), },\n+\t{ MT7530_ATC_MAT, REG_FIELD(AN8855_ATC, 7, 11), },\n+\t{ MT7530_ATC_CMD, REG_FIELD(AN8855_ATC, 0, 2), },\n+\t{ __MT7530_ATC, REG_FIELD(AN8855_ATC, 0, 31), },\n+\n+\t{ MT7530_MIRROR_EN, REG_FIELD(AN8855_MIR, 7, 7) },\n+\t{ MT7530_MIRROR_PORT, REG_FIELD(AN8855_MIR, 0, 4) },\n+\n+\t{ MT7530_SSP_FID_PST, REG_FIELD_ID(AN8855_SSP, 0, 15, AN8855_NUM_PORTS, 0x200) },\n+\n+\t{ MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(AN8855_PCR, 20, 20, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(AN8855_PCR, 16, 16, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_PCR_PORT_VLAN, REG_FIELD_ID(AN8855_PCR, 0, 1, AN8855_NUM_PORTS, 0x200) },\n+\n+\t{ MT7530_PCR_MATRIX, REG_FIELD_ID(AN8855_PORTMATRIX, 0, 5, AN8855_NUM_PORTS, 0x200) },\n+\n+\t{ MT7530_PSC_SA_DIS, REG_FIELD_ID(AN8855_PSC, 4, 4, AN8855_NUM_PORTS, 0x200) },\n+\n+\t{ MT7530_PVC_EG_TAG, REG_FIELD_ID(AN8855_PVC, 8, 10, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(AN8855_PVC, 6, 7, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_PVC_ACC_FRM, REG_FIELD_ID(AN8855_PVC, 0, 1, AN8855_NUM_PORTS, 0x200) },\n+\n+\t{ MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(AN8855_PPBV1, 0, 11, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_PVID_G0_PORT_VID, REG_FIELD_ID(AN8855_PVID, 0, 11, AN8855_NUM_PORTS, 0x200) },\n+\n+\t{ MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(AN8855_GMACCR, 4, 7) },\n+\t{ MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(AN8855_GMACCR, 0, 1) },\n+\n+\t{ MT7530_MIB_TX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_TX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_SINGLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(AN8855_PORT_MIB_TX_DEFERRED, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_LATE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_TX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_TX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_TX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_TX_OVERSIZE_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_OVERSIZE_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_TX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_FILTERING, REG_FIELD_ID(AN8855_PORT_MIB_RX_FILTERING, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_ALIGN_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_FRAG_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_OVER_SZ_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_JABBER_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_RX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_RX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_RX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_CTRL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_INGRESS_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_ARL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_FLOW_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_FLOW_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_WRED_DROP, REG_FIELD_ID(AN8855_PORT_MIB_WRED_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_MIRROR_DROP, REG_FIELD_ID(AN8855_PORT_MIB_MIRROR_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_RX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+\t{ AN8855_MIB_PORT_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_PORT_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },\n+};\n+\n+static const struct mt7530_mib_desc an8855_mib[] = {\n+\tMIB_DESC(MT7530_MIB_TX_DROP, -1, \"TxDrop\"),\n+\tMIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, \"TxCrcErr\"),\n+\tMIB_DESC(MT7530_MIB_TX_COLLISION, -1, \"TxCollision\"),\n+\tMIB_DESC(AN8855_MIB_TX_OVERSIZE_DROP, -1, \"TxOversizeDrop\"),\n+\tMIB_DESC(AN8855_MIB_TX_BAD_PKT_BYTES_LOW,\n+\t\t AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, \"TxBadPktBytes\"),\n+\tMIB_DESC(MT7530_MIB_RX_DROP, -1, \"RxDrop\"),\n+\tMIB_DESC(MT7530_MIB_RX_FILTERING, -1, \"RxFiltering\"),\n+\tMIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, \"RxCrcErr\"),\n+\tMIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, \"RxCtrlDrop\"),\n+\tMIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, \"RxIngressDrop\"),\n+\tMIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, \"RxArlDrop\"),\n+\tMIB_DESC(AN8855_MIB_FLOW_CONTROL_DROP, -1, \"FlowControlDrop\"),\n+\tMIB_DESC(AN8855_MIB_WRED_DROP, -1, \"WredDrop\"),\n+\tMIB_DESC(AN8855_MIB_MIRROR_DROP, -1, \"MirrorDrop\"),\n+\tMIB_DESC(AN8855_MIB_RX_BAD_PKT_BYTES_LOW,\n+\t\t AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, \"RxBadPktBytes\"),\n+\tMIB_DESC(AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, -1, \"RxsFlowSamplingPktDrop\"),\n+\tMIB_DESC(AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, -1, \"RxsFlowTotalPktDrop\"),\n+\tMIB_DESC(AN8855_MIB_PORT_CONTROL_DROP, -1, \"PortControlDrop\"),\n+};\n+\n+static void\n+an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)\n+{\n+\tstruct dsa_port *dp = dsa_to_port(ds, port);\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tbool learning = false;\n+\tint ret;\n+\n+\tmt7530_lib_stp_state_set(\u0026priv-\u003elib_priv, port, state);\n+\n+\tswitch (state) {\n+\tcase BR_STATE_LEARNING:\n+\tcase BR_STATE_FORWARDING:\n+\t\tlearning = dp-\u003elearning;\n+\t\tfallthrough;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PSC_P(port), AN8855_SA_DIS,\n+\t\t\t\t learning ? 0 : AN8855_SA_DIS);\n+\tif (ret)\n+\t\tdev_err(priv-\u003eds-\u003edev, \"failed to update learn reg: %d\\n\", ret);\n+}\n+\n+static void an8855_port_fast_age(struct dsa_switch *ds, int port)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tint ret;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\n+\t/* Set to clean Dynamic entry */\n+\tret = regmap_write(priv-\u003eregmap, AN8855_ATA2, AN8855_ATA2_TYPE);\n+\tif (ret) {\n+\t\tdev_err(priv-\u003eds-\u003edev, \"failed to update ATA2 reg: %d\\n\", ret);\n+\t\tgoto exit;\n+\t}\n+\n+\t/* Set Port */\n+\tret = regmap_write(priv-\u003eregmap, AN8855_ATWD2,\n+\t\t\t FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));\n+\tif (ret) {\n+\t\tdev_err(priv-\u003eds-\u003edev, \"failed to update ATWD2 reg: %d\\n\", ret);\n+\t\tgoto exit;\n+\t}\n+\n+\t/* Flush Dynamic entry at port */\n+\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_FLUSH,\n+\t\t\t\t AN8855_FDB_MAT_MAC_TYPE_PORT, NULL);\n+\tif (ret)\n+\t\tdev_err(priv-\u003eds-\u003edev, \"failed to send FDB cmd: %d\\n\", ret);\n+\n+exit:\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+}\n+\n+static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port,\n+\t\t\t\t\tstruct switchdev_brport_flags flags,\n+\t\t\t\t\tstruct netlink_ext_ack *extack)\n+{\n+\tif (flags.mask \u0026 ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |\n+\t\t\t BR_BCAST_FLOOD | BR_ISOLATED))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int an8855_port_bridge_flags(struct dsa_switch *ds, int port,\n+\t\t\t\t struct switchdev_brport_flags flags,\n+\t\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_bridge_flags(\u0026priv-\u003elib_priv, port, flags,\n+\t\t\t\t\t extack);\n+}\n+\n+static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tu32 age_count, age_unit, val;\n+\n+\t/* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */\n+\tval = msecs / AN8855_L2_AGING_MS_CONSTANT;\n+\n+\t/* Derive the count unit */\n+\tage_unit = DIV_ROUND_UP(val, FIELD_MAX(AN8855_AGE_CNT) + 1) - 1;\n+\tif (age_unit \u003e FIELD_MAX(AN8855_AGE_UNIT))\n+\t\tage_unit = FIELD_MAX(AN8855_AGE_UNIT);\n+\n+\t/* Get the count in unit, age_unit is always incremented by 1 internally */\n+\tage_count = DIV_ROUND_UP(val, age_unit + 1) - 1;\n+\n+\treturn regmap_update_bits(priv-\u003eregmap, AN8855_AAC,\n+\t\t\t\t AN8855_AGE_CNT | AN8855_AGE_UNIT,\n+\t\t\t\t FIELD_PREP(AN8855_AGE_CNT, age_count) |\n+\t\t\t\t FIELD_PREP(AN8855_AGE_UNIT, age_unit));\n+}\n+\n+static int an8855_port_bridge_join(struct dsa_switch *ds, int port,\n+\t\t\t\t struct dsa_bridge bridge,\n+\t\t\t\t bool *tx_fwd_offload,\n+\t\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_bridge_join(\u0026priv-\u003elib_priv, port, bridge,\n+\t\t\t\t\t tx_fwd_offload, extack);\n+}\n+\n+static void an8855_port_bridge_leave(struct dsa_switch *ds, int port,\n+\t\t\t\t struct dsa_bridge bridge)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_bridge_leave(\u0026priv-\u003elib_priv, port, bridge);\n+}\n+\n+static int an8855_port_fdb_add(struct dsa_switch *ds, int port,\n+\t\t\t const unsigned char *addr, u16 vid,\n+\t\t\t struct dsa_db db)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_fdb_add(\u0026priv-\u003elib_priv, port, addr, vid, db);\n+}\n+\n+static int an8855_port_fdb_del(struct dsa_switch *ds, int port,\n+\t\t\t const unsigned char *addr, u16 vid,\n+\t\t\t struct dsa_db db)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_fdb_del(\u0026priv-\u003elib_priv, port, addr, vid, db);\n+}\n+\n+static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,\n+\t\t\t\tdsa_fdb_dump_cb_t *cb, void *data)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tint banks, count = 0;\n+\tu32 rsp;\n+\tint ret;\n+\tint i;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\n+\t/* Load search port */\n+\tret = regmap_write(priv-\u003eregmap, AN8855_ATWD2,\n+\t\t\t FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));\n+\tif (ret)\n+\t\tgoto exit;\n+\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_START,\n+\t\t\t\t AN8855_FDB_MAT_MAC_PORT, \u0026rsp);\n+\tif (ret \u003c 0)\n+\t\tgoto exit;\n+\n+\tdo {\n+\t\t/* From response get the number of banks to read, exit if 0 */\n+\t\tbanks = FIELD_GET(AN8855_ATC_HIT, rsp);\n+\t\tif (!banks)\n+\t\t\tbreak;\n+\n+\t\t/* Each banks have 4 entry */\n+\t\tfor (i = 0; i \u003c 4; i++) {\n+\t\t\tstruct mt7530_fdb _fdb = { };\n+\n+\t\t\tcount++;\n+\n+\t\t\t/* Check if bank is present */\n+\t\t\tif (!(banks \u0026 BIT(i)))\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Select bank entry index */\n+\t\t\tret = regmap_write(priv-\u003eregmap, AN8855_ATRDS,\n+\t\t\t\t\t FIELD_PREP(AN8855_ATRD_SEL, i));\n+\t\t\tif (ret)\n+\t\t\t\tbreak;\n+\t\t\t/* wait 1ms for the bank entry to be filled */\n+\t\t\tusleep_range(1000, 1500);\n+\t\t\tmt7530_lib_fdb_read(\u0026priv-\u003elib_priv, \u0026_fdb);\n+\n+\t\t\tret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data);\n+\t\t\tif (ret \u003c 0)\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Stop if reached max FDB number */\n+\t\tif (ret \u003c 0 || count \u003e= AN8855_NUM_FDB_RECORDS)\n+\t\t\tbreak;\n+\n+\t\t/* Read next bank */\n+\t\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_NEXT,\n+\t\t\t\t\t AN8855_FDB_MAT_MAC_PORT, \u0026rsp);\n+\t\tif (ret \u003c 0)\n+\t\t\tbreak;\n+\t} while (true);\n+\n+exit:\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+\treturn ret;\n+}\n+\n+static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port,\n+\t\t\t\t bool vlan_filtering,\n+\t\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_vlan_filtering(\u0026priv-\u003elib_priv, port,\n+\t\t\t\t\t vlan_filtering,\n+\t\t\t\t\t extack);\n+}\n+\n+static int an8855_port_vlan_add(struct dsa_switch *ds, int port,\n+\t\t\t\tconst struct switchdev_obj_port_vlan *vlan,\n+\t\t\t\tstruct netlink_ext_ack *extack)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_vlan_add(\u0026priv-\u003elib_priv, port, vlan, extack);\n+}\n+\n+static int an8855_port_vlan_del(struct dsa_switch *ds, int port,\n+\t\t\t\tconst struct switchdev_obj_port_vlan *vlan)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_vlan_del(\u0026priv-\u003elib_priv, port, vlan);\n+}\n+\n+static int an8855_port_mdb_add(struct dsa_switch *ds, int port,\n+\t\t\t const struct switchdev_obj_port_mdb *mdb,\n+\t\t\t struct dsa_db db)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_mdb_add(\u0026priv-\u003elib_priv, port, mdb, db);\n+}\n+\n+static int an8855_port_mdb_del(struct dsa_switch *ds, int port,\n+\t\t\t const struct switchdev_obj_port_mdb *mdb,\n+\t\t\t struct dsa_db db)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_mdb_del(\u0026priv-\u003elib_priv, port, mdb, db);\n+}\n+\n+static int an8855_port_change_mtu(struct dsa_switch *ds, int port,\n+\t\t\t\t int new_mtu)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_change_mtu(\u0026priv-\u003elib_priv, port, new_mtu);\n+}\n+\n+static int an8855_port_max_mtu(struct dsa_switch *ds, int port)\n+{\n+\treturn AN8855_MAX_MTU;\n+}\n+\n+static void an8855_get_strings(struct dsa_switch *ds, int port,\n+\t\t\t u32 stringset, uint8_t *data)\n+{\n+\tint i;\n+\n+\tif (stringset != ETH_SS_STATS)\n+\t\treturn;\n+\n+\tfor (i = 0; i \u003c ARRAY_SIZE(an8855_mib); i++)\n+\t\tethtool_puts(\u0026data, an8855_mib[i].name);\n+}\n+\n+static void an8855_get_ethtool_stats(struct dsa_switch *ds, int port,\n+\t\t\t\t uint64_t *data)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tconst struct mt7530_mib_desc *mib;\n+\tstruct mt7530_lib_priv *lib_priv;\n+\tint i;\n+\n+\tlib_priv = \u0026priv-\u003elib_priv;\n+\tfor (i = 0; i \u003c ARRAY_SIZE(an8855_mib); i++) {\n+\t\tstruct regmap_field *high = NULL;\n+\n+\t\tmib = \u0026an8855_mib[i];\n+\t\tif (mib-\u003efield_high != -1)\n+\t\t\thigh = lib_priv-\u003efields[mib-\u003efield_high];\n+\n+\t\tmt7530_lib_read_port_stats(lib_priv-\u003efields[mib-\u003efield_low],\n+\t\t\t\t\t high, port, data + i);\n+\t}\n+}\n+\n+static int an8855_get_sset_count(struct dsa_switch *ds, int port,\n+\t\t\t\t int sset)\n+{\n+\tif (sset != ETH_SS_STATS)\n+\t\treturn -EOPNOTSUPP;\n+\n+\treturn ARRAY_SIZE(an8855_mib);\n+}\n+\n+static void an8855_get_eth_mac_stats(struct dsa_switch *ds, int port,\n+\t\t\t\t struct ethtool_eth_mac_stats *mac_stats)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_get_eth_mac_stats(\u0026priv-\u003elib_priv, port, mac_stats);\n+}\n+\n+static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {\n+\t{ 0, 64 },\n+\t{ 65, 127 },\n+\t{ 128, 255 },\n+\t{ 256, 511 },\n+\t{ 512, 1023 },\n+\t{ 1024, 1518 },\n+\t{ 1519, AN8855_MAX_MTU },\n+\t{}\n+};\n+\n+static const struct mt7530_rmon_hist an8855_rmon_hist_info = {\n+\t.ranges_fields = (unsigned int []){\n+\t\tMT7530_MIB_RX_PKT_SZ_64,\n+\t\tMT7530_MIB_RX_PKT_SZ_65_TO_127,\n+\t\tMT7530_MIB_RX_PKT_SZ_128_TO_255,\n+\t\tMT7530_MIB_RX_PKT_SZ_256_TO_511,\n+\t\tMT7530_MIB_RX_PKT_SZ_512_TO_1023,\n+\t\tAN8855_MIB_RX_PKT_SZ_1024_TO_1518,\n+\t\tAN8855_MIB_RX_PKT_SZ_1519_TO_MAX,\n+\t},\n+\t.ranges_tx_fields = (unsigned int []){\n+\t\tMT7530_MIB_TX_PKT_SZ_64,\n+\t\tMT7530_MIB_TX_PKT_SZ_65_TO_127,\n+\t\tMT7530_MIB_TX_PKT_SZ_128_TO_255,\n+\t\tMT7530_MIB_TX_PKT_SZ_256_TO_511,\n+\t\tMT7530_MIB_TX_PKT_SZ_512_TO_1023,\n+\t\tAN8855_MIB_TX_PKT_SZ_1024_TO_1518,\n+\t\tAN8855_MIB_TX_PKT_SZ_1519_TO_MAX,\n+\t},\n+\t.ranges = an8855_rmon_ranges,\n+\t.num_ranges = ARRAY_SIZE(an8855_rmon_ranges) - 1,\n+};\n+\n+static void an8855_get_rmon_stats(struct dsa_switch *ds, int port,\n+\t\t\t\t struct ethtool_rmon_stats *rmon_stats,\n+\t\t\t\t const struct ethtool_rmon_hist_range **ranges)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_get_rmon_stats(\u0026priv-\u003elib_priv, port, rmon_stats, ranges,\n+\t\t\t\t\t \u0026an8855_rmon_hist_info);\n+}\n+\n+static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port,\n+\t\t\t\t struct ethtool_eth_ctrl_stats *ctrl_stats)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\tmt7530_lib_get_eth_ctrl_stats(\u0026priv-\u003elib_priv, port, ctrl_stats);\n+}\n+\n+static int an8855_port_mirror_add(struct dsa_switch *ds, int port,\n+\t\t\t\t struct dsa_mall_mirror_tc_entry *mirror,\n+\t\t\t\t bool ingress,\n+\t\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\treturn mt7530_lib_port_mirror_add(\u0026priv-\u003elib_priv, port, mirror, ingress, extack);\n+}\n+\n+static void an8855_port_mirror_del(struct dsa_switch *ds, int port,\n+\t\t\t\t struct dsa_mall_mirror_tc_entry *mirror)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\n+\tmt7530_lib_port_mirror_del(\u0026priv-\u003elib_priv, port, mirror);\n+}\n+\n+static int an8855_port_enable(struct dsa_switch *ds, int port,\n+\t\t\t struct phy_device *phy)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tint ret;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\tpriv-\u003eports[port].enable = true;\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_PMCR_P(port),\n+\t\t\t AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+\n+\treturn ret;\n+}\n+\n+static void an8855_port_disable(struct dsa_switch *ds, int port)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tint ret;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\tpriv-\u003eports[port].enable = false;\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_PMCR_P(port),\n+\t\t\t\tAN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+\tif (ret)\n+\t\tdev_err(priv-\u003eds-\u003edev, \"failed to disable port: %d\\n\", ret);\n+}\n+\n+static int an8855_set_mac_eee(struct dsa_switch *ds, int port,\n+\t\t\t struct ethtool_keee *e)\n+{\n+\tif (e-\u003etx_lpi_timer \u003e 0xFFF)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static enum dsa_tag_protocol an8855_get_tag_protocol(struct dsa_switch *ds,\n+\t\t\t\t\t\t int port,\n+\t\t\t\t\t\t enum dsa_tag_protocol mp)\n+{\n+\treturn DSA_TAG_PROTO_AIROHA;\n+}\n+\n+static int an8855_setup(struct dsa_switch *ds)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tstruct dsa_port *dp;\n+\tint ret;\n+\n+\t/* Enable and reset MIB counters */\n+\tmt7530_lib_mib_reset(\u0026priv-\u003elib_priv);\n+\n+\tdsa_switch_for_each_user_port(dp, ds) {\n+\t\t/* Disable MAC by default on all user ports */\n+\t\tan8855_port_disable(ds, dp-\u003eindex);\n+\n+\t\t/* Individual user ports get connected to CPU port only */\n+\t\tret = regmap_write(priv-\u003eregmap, AN8855_PORTMATRIX_P(dp-\u003eindex),\n+\t\t\t\t FIELD_PREP(AN8855_PORTMATRIX_MASK, BIT(AN8855_CPU_PORT)));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/* Disable Broadcast Forward on user ports */\n+\t\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_BCF, BIT(dp-\u003eindex));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/* Disable Unknown Unicast Forward on user ports */\n+\t\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_UNUF, BIT(dp-\u003eindex));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/* Disable Unknown Multicast Forward on user ports */\n+\t\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_UNMF, BIT(dp-\u003eindex));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_UNIPMF, BIT(dp-\u003eindex));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/* Set default PVID to on all user ports */\n+\t\tmt7530_port_set_pvid(\u0026priv-\u003elib_priv, dp-\u003eindex, AN8855_PORT_VID_DEFAULT);\n+\t}\n+\n+\t/* Enable Airoha header mode on the cpu port */\n+\tret = regmap_write(priv-\u003eregmap, AN8855_PVC_P(AN8855_CPU_PORT),\n+\t\t\t AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Unknown multicast frame forwarding to the cpu port */\n+\tret = regmap_write(priv-\u003eregmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Set CPU port number */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_MFC,\n+\t\t\t\t AN8855_CPU_EN | AN8855_CPU_PORT_IDX,\n+\t\t\t\t AN8855_CPU_EN |\n+\t\t\t\t FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* CPU port gets connected to all user ports of\n+\t * the switch.\n+\t */\n+\tret = regmap_write(priv-\u003eregmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT),\n+\t\t\t FIELD_PREP(AN8855_PORTMATRIX_MASK, dsa_user_ports(ds)));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* CPU port is set to fallback mode to let untagged\n+\t * frames pass through.\n+\t */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PCR_P(AN8855_CPU_PORT),\n+\t\t\t\t AN8855_PORT_VLAN,\n+\t\t\t\t FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Enable Broadcast Forward on CPU port */\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_BCF, BIT(AN8855_CPU_PORT));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Enable Unknown Unicast Forward on CPU port */\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_UNUF, BIT(AN8855_CPU_PORT));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Enable Unknown Multicast Forward on CPU port */\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Setup Trap special frame to CPU rules */\n+\tmt7530_lib_trap_frames(\u0026priv-\u003elib_priv);\n+\n+\tdsa_switch_for_each_port(dp, ds) {\n+\t\t/* Disable Learning on all ports.\n+\t\t * Learning on CPU is disabled for fdb isolation and handled by\n+\t\t * assisted_learning_on_cpu_port.\n+\t\t */\n+\t\tret = regmap_set_bits(priv-\u003eregmap, AN8855_PSC_P(dp-\u003eindex),\n+\t\t\t\t AN8855_SA_DIS);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/* Enable consistent egress tag (for VLAN unware VLAN-passthrough) */\n+\t\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PVC_P(dp-\u003eindex),\n+\t\t\t\t\t AN8855_PVC_EG_TAG,\n+\t\t\t\t\t FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Setup VLAN for Default PVID */\n+\tret = mt7530_lib_setup_vlan0(\u0026priv-\u003elib_priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_CKGCR,\n+\t\t\t\tAN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Flush the FDB table */\n+\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_FLUSH,\n+\t\t\t\t AN8855_FDB_MAT_ALL, NULL);\n+\tif (ret \u003c 0)\n+\t\treturn ret;\n+\n+\t/* Set min a max ageing value supported */\n+\tds-\u003eageing_time_min = AN8855_L2_AGING_MS_CONSTANT;\n+\tds-\u003eageing_time_max = FIELD_MAX(AN8855_AGE_CNT) *\n+\t\t\t FIELD_MAX(AN8855_AGE_UNIT) *\n+\t\t\t AN8855_L2_AGING_MS_CONSTANT;\n+\n+\t/* User reported problem with WiFi roaming and\n+\t * ethernet port. Enabling assisted learning fix\n+\t * the issue.\n+\t */\n+\tds-\u003eassisted_learning_on_cpu_port = true;\n+\n+\treturn 0;\n+}\n+\n+static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_config *config,\n+\t\t\t\t\t\t\t phy_interface_t interface)\n+{\n+\tstruct dsa_port *dp = dsa_phylink_to_port(config);\n+\tstruct an8855_priv *priv = dp-\u003eds-\u003epriv;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\treturn \u0026priv-\u003epcs;\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+}\n+\n+static void an8855_phylink_mac_config(struct phylink_config *config,\n+\t\t\t\t unsigned int mode,\n+\t\t\t\t const struct phylink_link_state *state)\n+{\n+\tstruct dsa_port *dp = dsa_phylink_to_port(config);\n+\tstruct dsa_switch *ds = dp-\u003eds;\n+\tstruct an8855_priv *priv;\n+\tint port = dp-\u003eindex;\n+\n+\tpriv = ds-\u003epriv;\n+\n+\t/* Nothing to configure for internal ports */\n+\tif (port != 5)\n+\t\treturn;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\tregmap_update_bits(priv-\u003eregmap, AN8855_PMCR_P(port),\n+\t\t\t AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE |\n+\t\t\t AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN,\n+\t\t\t FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) |\n+\t\t\t AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN |\n+\t\t\t AN8855_PMCR_BACKPR_EN);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+}\n+\n+static void an8855_phylink_get_caps(struct dsa_switch *ds, int port,\n+\t\t\t\t struct phylink_config *config)\n+{\n+\tstruct an8855_priv *priv = ds-\u003epriv;\n+\tu32 reg = 0;\n+\tint ret;\n+\n+\tswitch (port) {\n+\tcase 0:\n+\tcase 1:\n+\tcase 2:\n+\tcase 3:\n+\tcase 4:\n+\t\t__set_bit(PHY_INTERFACE_MODE_GMII,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_INTERNAL,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\tbreak;\n+\tcase 5:\n+\t\tphy_interface_set_rgmii(config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_SGMII,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_2500BASEX,\n+\t\t\t config-\u003esupported_interfaces);\n+\t\tbreak;\n+\t}\n+\n+\tconfig-\u003emac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |\n+\t\t\t\t MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;\n+\n+\tret = regmap_read(priv-\u003eregmap, AN8855_CKGCR, \u0026reg);\n+\tif (ret)\n+\t\tdev_err(ds-\u003edev, \"failed to read EEE LPI timer\\n\");\n+\n+\tmemcpy(config-\u003elpi_interfaces, config-\u003esupported_interfaces,\n+\t sizeof(config-\u003elpi_interfaces));\n+\tconfig-\u003elpi_capabilities = MAC_100FD | MAC_1000FD;\n+\t/* Global LPI TXIDLE Threshold, default 60ms (unit 2us) */\n+\tconfig-\u003elpi_timer_default = FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) *\n+\t\t\t\t AN8855_TX_LPI_UNIT;\n+\n+\tconfig-\u003eeee_enabled_default = true;\n+}\n+\n+static void an8855_phylink_mac_link_down(struct phylink_config *config,\n+\t\t\t\t\t unsigned int mode,\n+\t\t\t\t\t phy_interface_t interface)\n+{\n+\tstruct dsa_port *dp = dsa_phylink_to_port(config);\n+\tstruct an8855_priv *priv = dp-\u003eds-\u003epriv;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\n+\t/* With autoneg just disable TX/RX else also force link down */\n+\tif (phylink_autoneg_inband(mode)) {\n+\t\tregmap_clear_bits(priv-\u003eregmap, AN8855_PMCR_P(dp-\u003eindex),\n+\t\t\t\t AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);\n+\t} else {\n+\t\tregmap_update_bits(priv-\u003eregmap, AN8855_PMCR_P(dp-\u003eindex),\n+\t\t\t\t AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN |\n+\t\t\t\t AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK,\n+\t\t\t\t AN8855_PMCR_FORCE_MODE);\n+\t}\n+\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+}\n+\n+static void an8855_phylink_mac_link_up(struct phylink_config *config,\n+\t\t\t\t struct phy_device *phydev, unsigned int mode,\n+\t\t\t\t phy_interface_t interface, int speed,\n+\t\t\t\t int duplex, bool tx_pause, bool rx_pause)\n+{\n+\tstruct dsa_port *dp = dsa_phylink_to_port(config);\n+\tstruct an8855_priv *priv = dp-\u003eds-\u003epriv;\n+\tint port = dp-\u003eindex;\n+\tu32 reg = 0;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\n+\tregmap_read(priv-\u003eregmap, AN8855_PMCR_P(port), \u0026reg);\n+\tif (phylink_autoneg_inband(mode)) {\n+\t\treg \u0026= ~AN8855_PMCR_FORCE_MODE;\n+\t} else {\n+\t\treg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK;\n+\n+\t\treg \u0026= ~AN8855_PMCR_FORCE_SPEED;\n+\t\tswitch (speed) {\n+\t\tcase SPEED_10:\n+\t\t\treg |= AN8855_PMCR_FORCE_SPEED_10;\n+\t\t\tbreak;\n+\t\tcase SPEED_100:\n+\t\t\treg |= AN8855_PMCR_FORCE_SPEED_100;\n+\t\t\tbreak;\n+\t\tcase SPEED_1000:\n+\t\t\treg |= AN8855_PMCR_FORCE_SPEED_1000;\n+\t\t\tbreak;\n+\t\tcase SPEED_2500:\n+\t\t\treg |= AN8855_PMCR_FORCE_SPEED_2500;\n+\t\t\tbreak;\n+\t\tcase SPEED_5000:\n+\t\t\tdev_err(priv-\u003eds-\u003edev, \"Missing support for 5G speed. Aborting...\\n\");\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\treg \u0026= ~AN8855_PMCR_FORCE_FDX;\n+\t\tif (duplex == DUPLEX_FULL)\n+\t\t\treg |= AN8855_PMCR_FORCE_FDX;\n+\n+\t\treg \u0026= ~AN8855_PMCR_RX_FC_EN;\n+\t\tif (rx_pause || dsa_port_is_cpu(dp))\n+\t\t\treg |= AN8855_PMCR_RX_FC_EN;\n+\n+\t\treg \u0026= ~AN8855_PMCR_TX_FC_EN;\n+\t\tif (tx_pause || dsa_port_is_cpu(dp))\n+\t\t\treg |= AN8855_PMCR_TX_FC_EN;\n+\t}\n+\n+\treg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN;\n+\n+\tregmap_write(priv-\u003eregmap, AN8855_PMCR_P(port), reg);\n+\n+exit:\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+}\n+\n+static void an8855_phylink_mac_disable_tx_lpi(struct phylink_config *config)\n+{\n+\tstruct dsa_port *dp = dsa_phylink_to_port(config);\n+\tstruct an8855_priv *priv = dp-\u003eds-\u003epriv;\n+\tint port = dp-\u003eindex;\n+\tint ret;\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_PMCR_P(port),\n+\t\t\t\tAN8855_PMCR_FORCE_EEE1G |\n+\t\t\t\tAN8855_PMCR_FORCE_EEE100);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+\tif (ret)\n+\t\tdev_err(dp-\u003eds-\u003edev, \"failed to disable EEE for port %d\\n\",\n+\t\t\tport);\n+\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_PMEEECR_P(port),\n+\t\t\t\tAN8855_LPI_MODE_EN);\n+\tif (ret)\n+\t\tdev_err(dp-\u003eds-\u003edev, \"failed to disable LPI for port %d\\n\",\n+\t\t\tport);\n+}\n+\n+static int an8855_phylink_mac_enable_tx_lpi(struct phylink_config *config,\n+\t\t\t\t\t u32 timer, bool tx_clock_stop)\n+{\n+\tstruct an8855_priv *priv;\n+\tstruct dsa_switch *ds;\n+\tstruct dsa_port *dp;\n+\tint port;\n+\tu32 val;\n+\tint ret;\n+\n+\tdp = dsa_phylink_to_port(config);\n+\tport = dp-\u003eindex;\n+\tds = dp-\u003eds;\n+\tpriv = ds-\u003epriv;\n+\n+\t/* TX LPI timer is global, find the highest timer\n+\t * across all port.\n+\t * If requested timer is 0, set to enter LPI immediately\n+\t * for the single port.\n+\t */\n+\tif (timer) {\n+\t\tint i;\n+\n+\t\t/* Save requested timer and search the highest one */\n+\t\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\t\tpriv-\u003etx_lpi_timer_ports[dp-\u003eindex] = timer;\n+\t\tfor (i = 0; i \u003c AN8855_NUM_PORTS; i++) {\n+\t\t\tif (!priv-\u003eports[i].enable)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (i == dp-\u003eindex)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (timer \u003c priv-\u003etx_lpi_timer_ports[i])\n+\t\t\t\ttimer = priv-\u003etx_lpi_timer_ports[i];\n+\t\t}\n+\t\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+\n+\t\ttimer /= AN8855_TX_LPI_UNIT;\n+\t\tif (FIELD_FIT(AN8855_LPI_TXIDLE_THD_MASK, timer))\n+\t\t\tval = FIELD_PREP(AN8855_LPI_TXIDLE_THD_MASK, timer);\n+\t\telse\n+\t\t\tval = AN8855_LPI_TXIDLE_THD_MASK;\n+\n+\t\tret = regmap_update_bits(priv-\u003eregmap, AN8855_CKGCR,\n+\t\t\t\t\t AN8855_LPI_TXIDLE_THD_MASK, val);\n+\t\tif (ret) {\n+\t\t\tdev_err(dp-\u003eds-\u003edev, \"failed to set global LPI timer\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t} else {\n+\t\tret = regmap_set_bits(priv-\u003eregmap, AN8855_PMEEECR_P(port),\n+\t\t\t\t AN8855_LPI_MODE_EN);\n+\t\tif (ret) {\n+\t\t\tdev_err(dp-\u003eds-\u003edev, \"failed to enable LPI for port %d\\n\",\n+\t\t\t\tport);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tmutex_lock(\u0026priv-\u003ereg_mutex);\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_PMCR_P(port),\n+\t\t\t AN8855_PMCR_FORCE_EEE1G |\n+\t\t\t AN8855_PMCR_FORCE_EEE100);\n+\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+\tif (ret)\n+\t\tdev_err(dp-\u003eds-\u003edev, \"failed to enable EEE for port %d\\n\",\n+\t\t\tport);\n+\n+\treturn ret;\n+}\n+\n+static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs,\n+\t\t\t\t\t phy_interface_t interface)\n+{\n+\t/* SGMII can be configured to use inband with AN result */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII)\n+\t\treturn LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;\n+\n+\t/* inband is not supported in 2500-baseX and must be disabled */\n+\treturn LINK_INBAND_DISABLE;\n+}\n+\n+static void an8855_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,\n+\t\t\t\t struct phylink_link_state *state)\n+{\n+\tstruct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);\n+\tu32 val;\n+\tint ret;\n+\n+\tret = regmap_read(priv-\u003eregmap, AN8855_PMSR_P(AN8855_CPU_PORT), \u0026val);\n+\tif (ret \u003c 0) {\n+\t\tstate-\u003elink = false;\n+\t\treturn;\n+\t}\n+\n+\tstate-\u003elink = !!(val \u0026 AN8855_PMSR_LNK);\n+\tstate-\u003ean_complete = state-\u003elink;\n+\tstate-\u003eduplex = (val \u0026 AN8855_PMSR_DPX) ? DUPLEX_FULL :\n+\t\t\t\t\t\t DUPLEX_HALF;\n+\n+\tswitch (val \u0026 AN8855_PMSR_SPEED) {\n+\tcase AN8855_PMSR_SPEED_10:\n+\t\tstate-\u003espeed = SPEED_10;\n+\t\tbreak;\n+\tcase AN8855_PMSR_SPEED_100:\n+\t\tstate-\u003espeed = SPEED_100;\n+\t\tbreak;\n+\tcase AN8855_PMSR_SPEED_1000:\n+\t\tstate-\u003espeed = SPEED_1000;\n+\t\tbreak;\n+\tcase AN8855_PMSR_SPEED_2500:\n+\t\tstate-\u003espeed = SPEED_2500;\n+\t\tbreak;\n+\tcase AN8855_PMSR_SPEED_5000:\n+\t\tdev_err(priv-\u003eds-\u003edev, \"Switch doesn't support 5G speed. Setting Unknown.\\n\");\n+\t\tfallthrough;\n+\tdefault:\n+\t\tstate-\u003espeed = SPEED_UNKNOWN;\n+\t\tbreak;\n+\t}\n+\n+\tif (val \u0026 AN8855_PMSR_RX_FC)\n+\t\tstate-\u003epause |= MLO_PAUSE_RX;\n+\tif (val \u0026 AN8855_PMSR_TX_FC)\n+\t\tstate-\u003epause |= MLO_PAUSE_TX;\n+}\n+\n+static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,\n+\t\t\t phy_interface_t interface,\n+\t\t\t const unsigned long *advertising,\n+\t\t\t bool permit_pause_to_mac)\n+{\n+\tstruct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);\n+\tu32 val;\n+\tint ret;\n+\n+\t/* TX FIR - improve TX EYE */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_INTF_CTRL_10,\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C2_SEL |\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C2_FORCE |\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C1_SEL |\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C1_FORCE,\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C2_SEL |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) |\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C1_SEL |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0x0;\n+\telse\n+\t\tval = 0xd;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_INTF_CTRL_11,\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C0B_SEL |\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C0B_FORCE,\n+\t\t\t\t AN8855_RG_DA_QP_TX_FIR_C0B_SEL |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* RX CDR - improve RX Jitter Tolerance */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0x5;\n+\telse\n+\t\tval = 0x6;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_CDR_LPF_BOT_LIM,\n+\t\t\t\t AN8855_RG_QP_CDR_LPF_KP_GAIN |\n+\t\t\t\t AN8855_RG_QP_CDR_LPF_KI_GAIN,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0x1;\n+\telse\n+\t\tval = 0x0;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_QP_DIG_MODE_CTRL_1,\n+\t\t\t\t AN8855_RG_TPHY_SPEED,\n+\t\t\t\t FIELD_PREP(AN8855_RG_TPHY_SPEED, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL - LPF */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PLL_CTRL_2,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_FBKSEL_INTF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_BR_INTF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_BPD_INTF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_BPA_INTF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_BC_INTF,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL - ICO */\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_PLL_CTRL_4,\n+\t\t\t AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_PLL_CTRL_2,\n+\t\t\t\tAN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL - CHP */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0x6;\n+\telse\n+\t\tval = 0x4;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PLL_CTRL_2,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_IR_INTF,\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL - PFD */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PLL_CTRL_2,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF,\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL - POSTDIV */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PLL_CTRL_2,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF |\n+\t\t\t\t AN8855_RG_DA_QP_PLL_PCK_SEL_INTF,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_PCK_SEL_INTF);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL - SDM */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PLL_CTRL_2,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));\n+\tif (ret)\n+\t\treturn ret;\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_PLL_CTRL_2,\n+\t\t\t\tAN8855_RG_DA_QP_PLL_SDM_IFM_INTF);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_SS_LCPLL_PWCTL_SETTING_2,\n+\t\t\t\t AN8855_RG_NCPO_ANA_MSB,\n+\t\t\t\t FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0x7a000000;\n+\telse\n+\t\tval = 0x48000000;\n+\tret = regmap_write(priv-\u003eregmap, AN8855_SS_LCPLL_TDC_FLT_2,\n+\t\t\t FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val));\n+\tif (ret)\n+\t\treturn ret;\n+\tret = regmap_write(priv-\u003eregmap, AN8855_SS_LCPLL_TDC_PCW_1,\n+\t\t\t FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_SS_LCPLL_TDC_FLT_5,\n+\t\t\t\tAN8855_RG_LCPLL_NCPO_CHG);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_PLL_CK_CTRL_0,\n+\t\t\t\tAN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL - SS */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PLL_CTRL_3,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF,\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0));\n+\tif (ret)\n+\t\treturn ret;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PLL_CTRL_4,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF,\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0));\n+\tif (ret)\n+\t\treturn ret;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PLL_CTRL_3,\n+\t\t\t\t AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF,\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PLL - TDC */\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_PLL_CK_CTRL_0,\n+\t\t\t\tAN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_RG_QP_PLL_SDM_ORD,\n+\t\t\t AN8855_RG_QP_PLL_SSC_TRI_EN);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_RG_QP_PLL_SDM_ORD,\n+\t\t\t AN8855_RG_QP_PLL_SSC_PHASE_INI);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_RX_DAC_EN,\n+\t\t\t\t AN8855_RG_QP_SIGDET_HF,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* TCL Disable (only for Co-SIM) */\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_PON_RXFEDIG_CTRL_0,\n+\t\t\t\tAN8855_RG_QP_EQ_RX500M_CK_SEL);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* TX Init */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0x4;\n+\telse\n+\t\tval = 0x0;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_TX_MODE,\n+\t\t\t\t AN8855_RG_QP_TX_RESERVE |\n+\t\t\t\t AN8855_RG_QP_TX_MODE_16B_EN,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* RX Control/Init */\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_RG_QP_RXAFE_RESERVE,\n+\t\t\t AN8855_RG_QP_CDR_PD_10B_EN);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0x1;\n+\telse\n+\t\tval = 0x2;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_CDR_LPF_MJV_LIM,\n+\t\t\t\t AN8855_RG_QP_CDR_LPF_RATIO,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_CDR_LPF_SETVALUE,\n+\t\t\t\t AN8855_RG_QP_CDR_PR_BUF_IN_SR |\n+\t\t\t\t AN8855_RG_QP_CDR_PR_BETA_SEL,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0xf;\n+\telse\n+\t\tval = 0xc;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,\n+\t\t\t\t AN8855_RG_QP_CDR_PR_DAC_BAND,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,\n+\t\t\t\t AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE |\n+\t\t\t\t AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF,\n+\t\t\t\t AN8855_RG_QP_CDR_PHYCK_SEL |\n+\t\t\t\t AN8855_RG_QP_CDR_PHYCK_RSTB |\n+\t\t\t\t AN8855_RG_QP_CDR_PHYCK_DIV,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,\n+\t\t\t\tAN8855_RG_QP_CDR_PR_XFICK_EN);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,\n+\t\t\t\t AN8855_RG_QP_CDR_PR_KBAND_DIV,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RX_CTRL_26,\n+\t\t\t\t AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |\n+\t\t\t\t AN8855_RG_LINK_NE_EN |\n+\t\t\t\t AN8855_RG_LINK_ERRO_EN,\n+\t\t\t\t AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |\n+\t\t\t\t AN8855_RG_LINK_ERRO_EN);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RX_DLY_0,\n+\t\t\t\t AN8855_RG_QP_RX_SAOSC_EN_H_DLY |\n+\t\t\t\t AN8855_RG_QP_RX_PI_CAL_EN_H_DLY,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RX_CTRL_42,\n+\t\t\t\t AN8855_RG_QP_EQ_EN_DLY,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RX_CTRL_2,\n+\t\t\t\t AN8855_RG_QP_RX_EQ_EN_H_DLY,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_PON_RXFEDIG_CTRL_9,\n+\t\t\t\t AN8855_RG_QP_EQ_LEQOSC_DLYCNT,\n+\t\t\t\t FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RX_CTRL_8,\n+\t\t\t\t AN8855_RG_DA_QP_SAOSC_DONE_TIME |\n+\t\t\t\t AN8855_RG_DA_QP_LEQOS_EN_TIME,\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) |\n+\t\t\t\t FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Frequency meter */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tval = 0x10;\n+\telse\n+\t\tval = 0x28;\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RX_CTRL_5,\n+\t\t\t\t AN8855_RG_FREDET_CHK_CYCLE,\n+\t\t\t\t FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RX_CTRL_6,\n+\t\t\t\t AN8855_RG_FREDET_GOLDEN_CYCLE,\n+\t\t\t\t FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RX_CTRL_7,\n+\t\t\t\t AN8855_RG_FREDET_TOLERATE_CYCLE,\n+\t\t\t\t FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_PLL_CTRL_0,\n+\t\t\t AN8855_RG_PHYA_AUTO_INIT);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* PCS Init */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII \u0026\u0026\n+\t neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) {\n+\t\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_QP_DIG_MODE_CTRL_0,\n+\t\t\t\t\tAN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_RG_HSGMII_PCS_CTROL_1,\n+\t\t\t\tAN8855_RG_TBI_10B_MODE);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\t/* Set AN Ability - Interrupt */\n+\t\tret = regmap_set_bits(priv-\u003eregmap, AN8855_SGMII_REG_AN_FORCE_CL37,\n+\t\t\t\t AN8855_RG_FORCE_AN_DONE);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = regmap_update_bits(priv-\u003eregmap, AN8855_SGMII_REG_AN_13,\n+\t\t\t\t\t AN8855_SGMII_REMOTE_FAULT_DIS |\n+\t\t\t\t\t AN8855_SGMII_IF_MODE,\n+\t\t\t\t\t AN8855_SGMII_REMOTE_FAULT_DIS |\n+\t\t\t\t\t FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Rate Adaption - GMII path config. */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t\tAN8855_RG_P0_DIS_MII_MODE);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t} else {\n+\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\t\tret = regmap_set_bits(priv-\u003eregmap, AN8855_MII_RA_AN_ENABLE,\n+\t\t\t\t\t AN8855_RG_P0_RA_AN_EN);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t} else {\n+\t\t\tret = regmap_update_bits(priv-\u003eregmap, AN8855_RG_AN_SGMII_MODE_FORCE,\n+\t\t\t\t\t\t AN8855_RG_FORCE_CUR_SGMII_MODE |\n+\t\t\t\t\t\t AN8855_RG_FORCE_CUR_SGMII_SEL,\n+\t\t\t\t\t\t AN8855_RG_FORCE_CUR_SGMII_SEL);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\n+\t\t\tret = regmap_clear_bits(priv-\u003eregmap, AN8855_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t\t\tAN8855_RG_P0_MII_RA_RX_EN |\n+\t\t\t\t\t\tAN8855_RG_P0_MII_RA_TX_EN |\n+\t\t\t\t\t\tAN8855_RG_P0_MII_RA_RX_MODE |\n+\t\t\t\t\t\tAN8855_RG_P0_MII_RA_TX_MODE);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = regmap_set_bits(priv-\u003eregmap, AN8855_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t AN8855_RG_P0_MII_MODE);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = regmap_set_bits(priv-\u003eregmap, AN8855_RG_RATE_ADAPT_CTRL_0,\n+\t\t\t AN8855_RG_RATE_ADAPT_RX_BYPASS |\n+\t\t\t AN8855_RG_RATE_ADAPT_TX_BYPASS |\n+\t\t\t AN8855_RG_RATE_ADAPT_RX_EN |\n+\t\t\t AN8855_RG_RATE_ADAPT_TX_EN);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Disable AN if not in autoneg */\n+\tret = regmap_update_bits(priv-\u003eregmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE,\n+\t\t\t\t neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE :\n+\t\t\t\t\t\t\t\t\t 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\t/* Follow SDK init flow with restarting AN after AN enable */\n+\t\tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\t\tret = regmap_set_bits(priv-\u003eregmap, AN8855_SGMII_REG_AN0,\n+\t\t\t\t\t BMCR_ANRESTART);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t} else {\n+\t\t\tret = regmap_set_bits(priv-\u003eregmap, AN8855_PHY_RX_FORCE_CTRL_0,\n+\t\t\t\t\t AN8855_RG_FORCE_TXC_SEL);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\t/* Force Speed with fixed-link or 2500base-x as doesn't support aneg */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX ||\n+\t neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {\n+\t\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\t\tval = AN8855_RG_LINK_MODE_P0_SPEED_2500;\n+\t\telse\n+\t\t\tval = AN8855_RG_LINK_MODE_P0_SPEED_1000;\n+\t\tret = regmap_update_bits(priv-\u003eregmap, AN8855_SGMII_STS_CTRL_0,\n+\t\t\t\t\t AN8855_RG_LINK_MODE_P0 |\n+\t\t\t\t\t AN8855_RG_FORCE_SPD_MODE_P0,\n+\t\t\t\t\t val | AN8855_RG_FORCE_SPD_MODE_P0);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* bypass flow control to MAC */\n+\tret = regmap_write(priv-\u003eregmap, AN8855_MSG_RX_LIK_STS_0,\n+\t\t\t AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 |\n+\t\t\t AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 |\n+\t\t\t AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = regmap_write(priv-\u003eregmap, AN8855_MSG_RX_LIK_STS_2,\n+\t\t\t AN8855_RG_RXFC_AN_BYPASS_P3 |\n+\t\t\t AN8855_RG_RXFC_AN_BYPASS_P2 |\n+\t\t\t AN8855_RG_RXFC_AN_BYPASS_P1 |\n+\t\t\t AN8855_RG_TXFC_AN_BYPASS_P3 |\n+\t\t\t AN8855_RG_TXFC_AN_BYPASS_P2 |\n+\t\t\t AN8855_RG_TXFC_AN_BYPASS_P1 |\n+\t\t\t AN8855_RG_DPX_AN_BYPASS_P3 |\n+\t\t\t AN8855_RG_DPX_AN_BYPASS_P2 |\n+\t\t\t AN8855_RG_DPX_AN_BYPASS_P1 |\n+\t\t\t AN8855_RG_DPX_AN_BYPASS_P0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static void an8855_pcs_an_restart(struct phylink_pcs *pcs)\n+{\n+}\n+\n+static const struct phylink_pcs_ops an8855_pcs_ops = {\n+\t.pcs_inband_caps = an8855_pcs_inband_caps,\n+\t.pcs_get_state = an8855_pcs_get_state,\n+\t.pcs_config = an8855_pcs_config,\n+\t.pcs_an_restart = an8855_pcs_an_restart,\n+};\n+\n+static const struct phylink_mac_ops an8855_phylink_mac_ops = {\n+\t.mac_select_pcs\t= an8855_phylink_mac_select_pcs,\n+\t.mac_config\t= an8855_phylink_mac_config,\n+\t.mac_link_down\t= an8855_phylink_mac_link_down,\n+\t.mac_link_up\t= an8855_phylink_mac_link_up,\n+\t.mac_disable_tx_lpi = an8855_phylink_mac_disable_tx_lpi,\n+\t.mac_enable_tx_lpi = an8855_phylink_mac_enable_tx_lpi,\n+};\n+\n+static const struct dsa_switch_ops an8855_switch_ops = {\n+\t.get_tag_protocol = an8855_get_tag_protocol,\n+\t.setup = an8855_setup,\n+\t.phylink_get_caps = an8855_phylink_get_caps,\n+\t.get_strings = an8855_get_strings,\n+\t.get_ethtool_stats = an8855_get_ethtool_stats,\n+\t.get_sset_count = an8855_get_sset_count,\n+\t.get_eth_mac_stats = an8855_get_eth_mac_stats,\n+\t.get_eth_ctrl_stats = an8855_get_eth_ctrl_stats,\n+\t.get_rmon_stats = an8855_get_rmon_stats,\n+\t.port_enable = an8855_port_enable,\n+\t.port_disable = an8855_port_disable,\n+\t.set_ageing_time = an8855_set_ageing_time,\n+\t.port_bridge_join = an8855_port_bridge_join,\n+\t.port_bridge_leave = an8855_port_bridge_leave,\n+\t.port_fast_age = an8855_port_fast_age,\n+\t.port_stp_state_set = an8855_port_stp_state_set,\n+\t.port_pre_bridge_flags = an8855_port_pre_bridge_flags,\n+\t.port_bridge_flags = an8855_port_bridge_flags,\n+\t.port_vlan_filtering = an8855_port_vlan_filtering,\n+\t.port_vlan_add = an8855_port_vlan_add,\n+\t.port_vlan_del = an8855_port_vlan_del,\n+\t.port_fdb_add = an8855_port_fdb_add,\n+\t.port_fdb_del = an8855_port_fdb_del,\n+\t.port_fdb_dump = an8855_port_fdb_dump,\n+\t.port_mdb_add = an8855_port_mdb_add,\n+\t.port_mdb_del = an8855_port_mdb_del,\n+\t.port_change_mtu = an8855_port_change_mtu,\n+\t.port_max_mtu = an8855_port_max_mtu,\n+\t.port_mirror_add = an8855_port_mirror_add,\n+\t.port_mirror_del = an8855_port_mirror_del,\n+\t.support_eee = dsa_supports_eee,\n+\t.set_mac_eee = an8855_set_mac_eee,\n+};\n+\n+static int an8855_setup_lib_priv(struct an8855_priv *priv)\n+{\n+\tstruct mt7530_lib_priv *lib_priv = \u0026priv-\u003elib_priv;\n+\tint i;\n+\n+\tlib_priv-\u003edev = priv-\u003eds-\u003edev;\n+\tlib_priv-\u003eds = priv-\u003eds;\n+\tlib_priv-\u003eregmap = priv-\u003eregmap;\n+\tlib_priv-\u003eports = priv-\u003eports;\n+\tlib_priv-\u003ereg_mutex = \u0026priv-\u003ereg_mutex;\n+\n+\tfor (i = 0; i \u003c ARRAY_SIZE(an8855_fields); i++) {\n+\t\tconst struct mt7530_reg_field *reg_field;\n+\t\tstruct regmap_field *field;\n+\n+\t\treg_field = \u0026an8855_fields[i];\n+\t\tfield = devm_regmap_field_alloc(priv-\u003eds-\u003edev, priv-\u003eregmap,\n+\t\t\t\t\t\treg_field-\u003efield);\n+\t\tif (IS_ERR(field))\n+\t\t\treturn PTR_ERR(field);\n+\n+\t\tlib_priv-\u003efields[reg_field-\u003eid] = field;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int an8855_switch_probe(struct platform_device *pdev)\n+{\n+\tstruct an8855_priv *priv;\n+\tint ret;\n+\n+\tpriv = devm_kzalloc(\u0026pdev-\u003edev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\t/* Get regmap from MFD */\n+\tpriv-\u003eregmap = dev_get_regmap(pdev-\u003edev.parent, NULL);\n+\tif (!priv-\u003eregmap)\n+\t\treturn -ENOENT;\n+\n+\tpriv-\u003eds = devm_kzalloc(\u0026pdev-\u003edev, sizeof(*priv-\u003eds), GFP_KERNEL);\n+\tif (!priv-\u003eds)\n+\t\treturn -ENOMEM;\n+\n+\tpriv-\u003eds-\u003edev = \u0026pdev-\u003edev;\n+\tpriv-\u003eds-\u003enum_ports = AN8855_NUM_PORTS;\n+\tpriv-\u003eds-\u003epriv = priv;\n+\tpriv-\u003eds-\u003eops = \u0026an8855_switch_ops;\n+\tret = devm_mutex_init(\u0026pdev-\u003edev, \u0026priv-\u003ereg_mutex);\n+\tif (ret)\n+\t\treturn ret;\n+\tpriv-\u003eds-\u003ephylink_mac_ops = \u0026an8855_phylink_mac_ops;\n+\n+\tpriv-\u003epcs.ops = \u0026an8855_pcs_ops;\n+\tpriv-\u003epcs.poll = true;\n+\n+\tret = an8855_setup_lib_priv(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdev_set_drvdata(\u0026pdev-\u003edev, priv);\n+\n+\treturn dsa_register_switch(priv-\u003eds);\n+}\n+\n+static void an8855_switch_remove(struct platform_device *pdev)\n+{\n+\tstruct an8855_priv *priv = dev_get_drvdata(\u0026pdev-\u003edev);\n+\n+\tif (!priv)\n+\t\treturn;\n+\n+\tdsa_unregister_switch(priv-\u003eds);\n+\n+\tdev_set_drvdata(\u0026pdev-\u003edev, NULL);\n+}\n+\n+static void an8855_switch_shutdown(struct platform_device *pdev)\n+{\n+\tstruct an8855_priv *priv = dev_get_drvdata(\u0026pdev-\u003edev);\n+\n+\tif (!priv)\n+\t\treturn;\n+\n+\tdsa_switch_shutdown(priv-\u003eds);\n+\n+\tdev_set_drvdata(\u0026pdev-\u003edev, NULL);\n+}\n+\n+static const struct of_device_id an8855_switch_of_match[] = {\n+\t{ .compatible = \"airoha,an8855-switch\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, an8855_switch_of_match);\n+\n+static struct platform_driver an8855_switch_driver = {\n+\t.probe = an8855_switch_probe,\n+\t.remove = an8855_switch_remove,\n+\t.shutdown = an8855_switch_shutdown,\n+\t.driver = {\n+\t\t.name = \"an8855-switch\",\n+\t\t.of_match_table = an8855_switch_of_match,\n+\t},\n+};\n+module_platform_driver(an8855_switch_driver);\n+\n+MODULE_AUTHOR(\"Min Yao \u003cmin.yao@airoha.com\u003e\");\n+MODULE_AUTHOR(\"Christian Marangi \u003cansuelsmth@gmail.com\u003e\");\n+MODULE_DESCRIPTION(\"Driver for Airoha AN8855 Switch\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/net/dsa/an8855.h b/drivers/net/dsa/an8855.h\nnew file mode 100644\nindex 0000000000000..85003e5684509\n--- /dev/null\n+++ b/drivers/net/dsa/an8855.h\n@@ -0,0 +1,755 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright (C) 2023 Min Yao \u003cmin.yao@airoha.com\u003e\n+ * Copyright (C) 2024 Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+\n+#ifndef __AN8855_H\n+#define __AN8855_H\n+\n+#include \u003clinux/bitfield.h\u003e\n+\n+#include \"mt7530-lib.h\"\n+\n+#define AN8855_NUM_PORTS\t\t6\n+#define AN8855_CPU_PORT\t\t\t5\n+#define AN8855_NUM_FDB_RECORDS\t\t2048\n+#define AN8855_GPHY_SMI_ADDR_DEFAULT\t1\n+#define AN8855_PORT_VID_DEFAULT\t\t0\n+\n+#define MTK_TAG_LEN\t\t\t4\n+#define AN8855_MAX_MTU\t\t\t(15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN)\n+\n+#define AN8855_L2_AGING_MS_CONSTANT\t1024\n+\n+#define AN8855_TX_LPI_UNIT\t\t2 /* us */\n+\n+/*\tAN8855_SCU\t\t\t0x10000000 */\n+#define AN8855_RG_GPIO_LED_MODE\t\t0x10000054\n+#define AN8855_RG_GPIO_LED_SEL(i)\t(0x10000000 + (0x0058 + ((i) * 4)))\n+#define AN8855_RG_INTB_MODE\t\t0x10000080\n+#define AN8855_RG_RGMII_TXCK_C\t\t0x100001d0\n+\n+#define AN8855_PKG_SEL\t\t\t0x10000094\n+#define AN8855_PAG_SEL_AN8855H\t0x2\n+\n+#define AN8855_RG_GPIO_L_INV\t\t0x10000010\n+#define AN8855_RG_GPIO_CTRL\t\t0x1000a300\n+#define AN8855_RG_GPIO_DATA\t\t0x1000a304\n+#define AN8855_RG_GPIO_OE\t\t0x1000a314\n+\n+/* Register for system reset */\n+#define AN8855_RST_CTRL\t\t\t0x100050c0\n+#define AN8855_SYS_CTRL_SYS_RST\tBIT(31)\n+\n+#define AN8855_INT_MASK\t\t\t0x100050f0\n+#define AN8855_INT_SYS\t\tBIT(15)\n+\n+#define AN8855_RG_CLK_CPU_ICG\t\t0x10005034\n+#define AN8855_MCU_ENABLE\t\tBIT(3)\n+\n+#define AN8855_RG_TIMER_CTL\t\t0x1000a100\n+#define AN8855_WDOG_ENABLE\t\tBIT(25)\n+\n+#define AN8855_RG_GDMP_RAM\t\t0x10010000\n+\n+/* Registers to mac forward control for unknown frames */\n+#define AN8855_MFC\t\t\t0x10200010\n+#define AN8855_CPU_EN\t\t\tBIT(15)\n+#define AN8855_CPU_PORT_IDX\t\tGENMASK(12, 8)\n+\n+#define AN8855_PAC\t\t\t0x10200024\n+#define AN8855_TAG_PAE_MANG_FR\tBIT(30)\n+#define AN8855_TAG_PAE_BPDU_FR\tBIT(28)\n+#define AN8855_TAG_PAE_EG_TAG\t\tGENMASK(27, 25)\n+#define AN8855_TAG_PAE_LKY_VLAN\tBIT(24)\n+#define AN8855_TAG_PAE_PRI_HIGH\tBIT(23)\n+#define AN8855_TAG_PAE_MIR\t\tGENMASK(20, 19)\n+#define AN8855_TAG_PAE_PORT_FW\tGENMASK(18, 16)\n+#define AN8855_PAE_MANG_FR\t\tBIT(14)\n+#define AN8855_PAE_BPDU_FR\t\tBIT(12)\n+#define AN8855_PAE_EG_TAG\t\tGENMASK(11, 9)\n+#define AN8855_PAE_LKY_VLAN\t\tBIT(8)\n+#define AN8855_PAE_PRI_HIGH\t\tBIT(7)\n+#define AN8855_PAE_MIR\t\tGENMASK(4, 3)\n+#define AN8855_PAE_PORT_FW\t\tGENMASK(2, 0)\n+\n+#define AN8855_RGAC1\t\t\t0x10200028\n+#define AN8855_R02_MANG_FR\t\tBIT(30)\n+#define AN8855_R02_BPDU_FR\t\tBIT(28)\n+#define AN8855_R02_EG_TAG\t\tGENMASK(27, 25)\n+#define AN8855_R02_LKY_VLAN\t\tBIT(24)\n+#define AN8855_R02_PRI_HIGH\t\tBIT(23)\n+#define AN8855_R02_MIR\t\tGENMASK(20, 19)\n+#define AN8855_R02_PORT_FW\t\tGENMASK(18, 16)\n+#define AN8855_R01_MANG_FR\t\tBIT(14)\n+#define AN8855_R01_BPDU_FR\t\tBIT(12)\n+#define AN8855_R01_EG_TAG\t\tGENMASK(11, 9)\n+#define AN8855_R01_LKY_VLAN\t\tBIT(8)\n+#define AN8855_R01_PRI_HIGH\t\tBIT(7)\n+#define AN8855_R01_MIR\t\tGENMASK(4, 3)\n+#define AN8855_R01_PORT_FW\t\tGENMASK(2, 0)\n+\n+#define AN8855_RGAC2\t\t\t0x1020002c\n+#define AN8855_R0E_MANG_FR\t\tBIT(30)\n+#define AN8855_R0E_BPDU_FR\t\tBIT(28)\n+#define AN8855_R0E_EG_TAG\t\tGENMASK(27, 25)\n+#define AN8855_R0E_LKY_VLAN\t\tBIT(24)\n+#define AN8855_R0E_PRI_HIGH\t\tBIT(23)\n+#define AN8855_R0E_MIR\t\tGENMASK(20, 19)\n+#define AN8855_R0E_PORT_FW\t\tGENMASK(18, 16)\n+#define AN8855_R03_MANG_FR\t\tBIT(14)\n+#define AN8855_R03_BPDU_FR\t\tBIT(12)\n+#define AN8855_R03_EG_TAG\t\tGENMASK(11, 9)\n+#define AN8855_R03_LKY_VLAN\t\tBIT(8)\n+#define AN8855_R03_PRI_HIGH\t\tBIT(7)\n+#define AN8855_R03_MIR\t\tGENMASK(4, 3)\n+#define AN8855_R03_PORT_FW\t\tGENMASK(2, 0)\n+\n+#define AN8855_AAC\t\t\t0x102000a0\n+#define AN8855_MAC_AUTO_FLUSH\t\tBIT(28)\n+/* Control Address Table Age time.\n+ * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT\n+ */\n+#define AN8855_AGE_CNT\t\tGENMASK(20, 12)\n+/* Value in seconds. Value is always incremented of 1 */\n+#define AN8855_AGE_UNIT\t\tGENMASK(10, 0)\n+\n+/* Registers for ARL Unknown Unicast Forward control */\n+#define AN8855_UNUF\t\t\t0x102000b4\n+\n+/* Registers for ARL Unknown Multicast Forward control */\n+#define AN8855_UNMF\t\t\t0x102000b8\n+\n+/* Registers for ARL Broadcast forward control */\n+#define AN8855_BCF\t\t\t0x102000bc\n+\n+/* Registers for port address age disable */\n+#define AN8855_AGDIS\t\t\t0x102000c0\n+\n+/* Registers for mirror port control */\n+#define AN8855_MIR\t\t\t0x102000cc\n+#define AN8855_MIRROR_EN\t\tBIT(7)\n+#define AN8855_MIRROR_PORT\t\tGENMASK(4, 0)\n+\n+/* Registers for BPDU and PAE frame control*/\n+#define AN8855_BPC\t\t\t0x102000d0\n+#define AN8855_BPDU_MANG_FR\t\tBIT(14)\n+#define AN8855_BPDU_BPDU_FR\t\tBIT(12)\n+#define AN8855_BPDU_EG_TAG\t\tGENMASK(11, 9)\n+#define AN8855_BPDU_LKY_VLAN\t\tBIT(8)\n+#define AN8855_BPDU_PRI_HIGH\t\tBIT(7)\n+#define AN8855_BPDU_MIR\t\tGENMASK(4, 3)\n+#define AN8855_BPDU_PORT_FW\t\tGENMASK(2, 0)\n+\n+/* Registers for IP Unknown Multicast Forward control */\n+#define AN8855_UNIPMF\t\t\t0x102000dc\n+\n+enum an8855_bpdu_port_fw {\n+\tAN8855_BPDU_FOLLOW_MFC = 0,\n+\tAN8855_BPDU_CPU_EXCLUDE = 4,\n+\tAN8855_BPDU_CPU_INCLUDE = 5,\n+\tAN8855_BPDU_CPU_ONLY = 6,\n+\tAN8855_BPDU_DROP = 7,\n+};\n+\n+/* Register for address table control */\n+#define AN8855_ATC\t\t\t0x10200300\n+#define AN8855_ATC_BUSY\t\tBIT(31)\n+#define AN8855_ATC_HASH\t\tGENMASK(24, 16)\n+#define AN8855_ATC_HIT\t\tGENMASK(15, 12)\n+#define AN8855_ATC_MAT_MASK\t\tGENMASK(11, 7)\n+#define AN8855_ATC_MAT(x)\t\tFIELD_PREP(AN8855_ATC_MAT_MASK, x)\n+#define AN8855_ATC_SAT\t\tGENMASK(5, 4)\n+#define AN8855_ATC_CMD\t\tGENMASK(2, 0)\n+\n+enum an8855_fdb_mat_cmds {\n+\tAN8855_FDB_MAT_ALL = 0,\n+\tAN8855_FDB_MAT_MAC, /* All MAC address */\n+\tAN8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */\n+\tAN8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */\n+\tAN8855_FDB_MAT_DIP, /* All DIP/GA address */\n+\tAN8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */\n+\tAN8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */\n+\tAN8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */\n+\tAN8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */\n+\tAN8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */\n+\tAN8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */\n+\tAN8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */\n+\tAN8855_FDB_MAT_MAC_PORT, /* All MAC address with port */\n+\tAN8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */\n+\tAN8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */\n+\tAN8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */\n+\tAN8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */\n+\t/* All MAC address with MAC type (dynamic or static) with CVID */\n+\tAN8855_FDB_MAT_MAC_TYPE_CVID,\n+\t/* All MAC address with MAC type (dynamic or static) with Filter ID */\n+\tAN8855_FDB_MAT_MAC_TYPE_FID,\n+\t/* All MAC address with MAC type (dynamic or static) with port */\n+\tAN8855_FDB_MAT_MAC_TYPE_PORT,\n+};\n+\n+/* Registers for address table access */\n+#define AN8855_ATA1\t\t\t0x10200304\n+#define AN8855_ATA1_MAC0\t\tGENMASK(31, 24)\n+#define AN8855_ATA1_MAC1\t\tGENMASK(23, 16)\n+#define AN8855_ATA1_MAC2\t\tGENMASK(15, 8)\n+#define AN8855_ATA1_MAC3\t\tGENMASK(7, 0)\n+#define AN8855_ATA2\t\t\t0x10200308\n+#define AN8855_ATA2_MAC4\t\tGENMASK(31, 24)\n+#define AN8855_ATA2_MAC5\t\tGENMASK(23, 16)\n+#define AN8855_ATA2_UNAUTH\t\tBIT(10)\n+#define AN8855_ATA2_TYPE\t\tBIT(9) /* 1: dynamic, 0: static */\n+#define AN8855_ATA2_AGE\t\tGENMASK(8, 0)\n+\n+/* Register for address table write data */\n+#define AN8855_ATWD\t\t\t0x10200324\n+#define AN8855_ATWD_FID\t\tGENMASK(31, 28)\n+#define AN8855_ATWD_VID\t\tGENMASK(27, 16)\n+#define AN8855_ATWD_IVL\t\tBIT(15)\n+#define AN8855_ATWD_EG_TAG\t\tGENMASK(14, 12)\n+#define AN8855_ATWD_SA_MIR\t\tGENMASK(9, 8)\n+#define AN8855_ATWD_SA_FWD\t\tGENMASK(7, 5)\n+#define AN8855_ATWD_UPRI\t\tGENMASK(4, 2)\n+#define AN8855_ATWD_LEAKY\t\tBIT(1)\n+#define AN8855_ATWD_VLD_MASK\t\tBIT(0) /* vid LOAD */\n+#define AN8855_ATWD2\t\t\t0x10200328\n+#define AN8855_ATWD2_PORT\t\tGENMASK(7, 0)\n+\n+/* Registers for table search read address */\n+#define AN8855_ATRDS\t\t\t0x10200330\n+#define AN8855_ATRD_SEL\t\tGENMASK(1, 0)\n+#define AN8855_ATRD0\t\t\t0x10200334\n+#define AN8855_ATRD0_FID\t\tGENMASK(28, 25)\n+#define AN8855_ATRD0_VID\t\tGENMASK(21, 10)\n+#define AN8855_ATRD0_IVL\t\tBIT(9)\n+#define AN8855_ATRD0_TYPE\t\tGENMASK(4, 3)\n+#define AN8855_ATRD0_ARP\t\tGENMASK(2, 1)\n+#define AN8855_ATRD0_LIVE\t\tBIT(0)\n+#define AN8855_ATRD1\t\t\t0x10200338\n+#define AN8855_ATRD1_MAC4\t\tGENMASK(31, 24)\n+#define AN8855_ATRD1_MAC5\t\tGENMASK(23, 16)\n+#define AN8855_ATRD1_AGING\t\tGENMASK(11, 3)\n+#define AN8855_ATRD2\t\t\t0x1020033c\n+#define AN8855_ATRD2_MAC0\t\tGENMASK(31, 24)\n+#define AN8855_ATRD2_MAC1\t\tGENMASK(23, 16)\n+#define AN8855_ATRD2_MAC2\t\tGENMASK(15, 8)\n+#define AN8855_ATRD2_MAC3\t\tGENMASK(7, 0)\n+#define AN8855_ATRD3\t\t\t0x10200340\n+#define AN8855_ATRD3_PORTMASK\t\tGENMASK(7, 0)\n+\n+enum an8855_fdb_type {\n+\tAN8855_MAC_TB_TY_MAC = 0,\n+\tAN8855_MAC_TB_TY_DIP = 1,\n+\tAN8855_MAC_TB_TY_DIP_SIP = 2,\n+};\n+\n+/* Register for vlan table control */\n+#define AN8855_VTCR\t\t\t0x10200600\n+#define AN8855_VTCR_BUSY\t\tBIT(31)\n+#define AN8855_VTCR_FUNC\t\tGENMASK(15, 12)\n+#define AN8855_VTCR_VID\t\tGENMASK(11, 0)\n+\n+enum an8855_vlan_cmd {\n+\t/* Read/Write the specified VID entry from VAWD register based\n+\t * on VID.\n+\t */\n+\tAN8855_VTCR_RD_VID = 0,\n+\tAN8855_VTCR_WR_VID = 1,\n+};\n+\n+/* Register for setup vlan write data */\n+#define AN8855_VAWD0\t\t\t0x10200604\n+/* VLAN Member Control */\n+#define AN8855_VA0_PORT\t\tGENMASK(31, 26)\n+/* Egress Tag Control */\n+#define AN8855_VA0_ETAG\t\tGENMASK(23, 12)\n+#define AN8855_VA0_ETAG_PORT\t\tGENMASK(13, 12)\n+#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2)\n+#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT \u003c\u003c \\\n+\t\t\t\t\t\tAN8855_VA0_ETAG_PORT_SHIFT(port))\n+#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) \u003c\u003c \\\n+\t\t\t\t\t\tAN8855_VA0_ETAG_PORT_SHIFT(port))\n+#define AN8855_VA0_EG_CON\t\tBIT(11)\n+#define AN8855_VA0_VTAG_EN\t\tBIT(10) /* Per VLAN Egress Tag Control */\n+#define AN8855_VA0_IVL_MAC\t\tBIT(5) /* Independent VLAN Learning */\n+#define\t AN8855_VA0_FID\t\tGENMASK(4, 1)\n+#define AN8855_VA0_VLAN_VALID\t\tBIT(0) /* VLAN Entry Valid */\n+#define AN8855_VAWD1\t\t\t0x10200608\n+#define AN8855_VA1_PORT_STAG\t\tBIT(1)\n+\n+enum an8855_fid {\n+\tAN8855_FID_STANDALONE = 0,\n+\tAN8855_FID_BRIDGED = 1,\n+};\n+\n+/* Same register field of VAWD0 */\n+#define AN8855_VARD0\t\t\t0x10200618\n+\n+enum an8855_vlan_egress_attr {\n+\tAN8855_VLAN_EGRESS_UNTAG = 0,\n+\tAN8855_VLAN_EGRESS_TAG = 2,\n+\tAN8855_VLAN_EGRESS_STACK = 3,\n+};\n+\n+/* Register for port STP state control */\n+#define AN8855_SSP\t\t\t0x10208000\n+#define AN8855_SSP_P(x)\t\t\t(AN8855_SSP + ((x) * 0x200))\n+/* Up to 16 FID supported, each with the same mask */\n+#define\t AN8855_FID_PST\t\tGENMASK(1, 0)\n+#define AN8855_FID_PST_SHIFT(fid)\t(2 * (fid))\n+#define AN8855_FID_PST_MASK(fid)\t(AN8855_FID_PST \u003c\u003c \\\n+\t\t\t\t\t\tAN8855_FID_PST_SHIFT(fid))\n+#define AN8855_FID_PST_VAL(fid, val)\t(FIELD_PREP(AN8855_FID_PST, (val)) \u003c\u003c \\\n+\t\t\t\t\t\tAN8855_FID_PST_SHIFT(fid))\n+\n+enum an8855_stp_state {\n+\tAN8855_STP_DISABLED = 0,\n+\tAN8855_STP_BLOCKING = 1,\n+\tAN8855_STP_LISTENING = AN8855_STP_BLOCKING,\n+\tAN8855_STP_LEARNING = 2,\n+\tAN8855_STP_FORWARDING = 3\n+};\n+\n+/* Register for port control */\n+#define AN8855_PCR\t\t\t0x10208004\n+#define AN8855_PCR_P(x)\t\t\t(AN8855_PCR + ((x) * 0x200))\n+#define AN8855_EG_TAG\t\t\tGENMASK(29, 28)\n+#define AN8855_PORT_PRI\t\tGENMASK(26, 24)\n+#define AN8855_PORT_TX_MIR\t\tBIT(20)\n+#define AN8855_PORT_RX_MIR\t\tBIT(16)\n+#define AN8855_PORT_VLAN\t\tGENMASK(1, 0)\n+\n+enum an8855_port_mode {\n+\t/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */\n+\tAN8855_PORT_MATRIX_MODE = 0,\n+\n+\t/* Fallback Mode: Forward received frames with ingress ports that do\n+\t * not belong to the VLAN member. Frames whose VID is not listed on\n+\t * the VLAN table are forwarded by the PCR_MATRIX members.\n+\t */\n+\tAN8855_PORT_FALLBACK_MODE = 1,\n+\n+\t/* Check Mode: Forward received frames whose ingress do not\n+\t * belong to the VLAN member. Discard frames if VID ismiddes on the\n+\t * VLAN table.\n+\t */\n+\tAN8855_PORT_CHECK_MODE = 2,\n+\n+\t/* Security Mode: Discard any frame due to ingress membership\n+\t * violation or VID missed on the VLAN table.\n+\t */\n+\tAN8855_PORT_SECURITY_MODE = 3,\n+};\n+\n+/* Register for port security control */\n+#define AN8855_PSC\t\t\t0x1020800c\n+#define AN8855_PSC_P(x)\t\t\t(AN8855_PSC + ((x) * 0x200))\n+#define AN8855_SA_DIS\t\t\tBIT(4)\n+\n+/* Register for port vlan control */\n+#define AN8855_PVC\t\t\t0x10208010\n+#define AN8855_PVC_P(x)\t\t\t(AN8855_PVC + ((x) * 0x200))\n+#define AN8855_PORT_SPEC_REPLACE_MODE\tBIT(11)\n+#define AN8855_PVC_EG_TAG\t\tGENMASK(10, 8)\n+#define AN8855_VLAN_ATTR\t\tGENMASK(7, 6)\n+#define AN8855_PORT_SPEC_TAG\t\tBIT(5)\n+#define AN8855_ACC_FRM\t\tGENMASK(1, 0)\n+\n+enum an8855_vlan_port_eg_tag {\n+\tAN8855_VLAN_EG_DISABLED = 0,\n+\tAN8855_VLAN_EG_CONSISTENT = 1,\n+\tAN8855_VLAN_EG_UNTAGGED = 4,\n+\tAN8855_VLAN_EG_SWAP = 5,\n+\tAN8855_VLAN_EG_TAGGED = 6,\n+\tAN8855_VLAN_EG_STACK = 7,\n+};\n+\n+enum an8855_vlan_port_attr {\n+\tAN8855_VLAN_USER = 0,\n+\tAN8855_VLAN_STACK = 1,\n+\tAN8855_VLAN_TRANSPARENT = 3,\n+};\n+\n+enum an8855_vlan_port_acc_frm {\n+\tAN8855_VLAN_ACC_ALL = 0,\n+\tAN8855_VLAN_ACC_TAGGED = 1,\n+\tAN8855_VLAN_ACC_UNTAGGED = 2,\n+};\n+\n+#define AN8855_PPBV1\t\t\t0x10208014\n+#define AN8855_PPBV1_P(x)\t\t(AN8855_PPBV1 + ((x) * 0x200))\n+#define AN8855_PPBV_G0_PORT_VID\tGENMASK(11, 0)\n+\n+#define AN8855_PORTMATRIX\t\t0x10208044\n+#define AN8855_PORTMATRIX_P(x)\t\t(AN8855_PORTMATRIX + ((x) * 0x200))\n+#define AN8855_PORTMATRIX_MASK\tGENMASK(5, 0)\n+/* Port matrix without the CPU port that should never be removed */\n+#define AN8855_USER_PORTMATRIX\tGENMASK(4, 0)\n+\n+/* Register for port PVID */\n+#define AN8855_PVID\t\t\t0x10208048\n+#define AN8855_PVID_P(x)\t\t(AN8855_PVID + ((x) * 0x200))\n+#define AN8855_G0_PORT_VID\t\tGENMASK(11, 0)\n+\n+/* Register for port MAC control register */\n+#define AN8855_PMCR_P(x)\t\t(0x10210000 + ((x) * 0x200))\n+#define AN8855_PMCR_FORCE_MODE\tBIT(31)\n+#define AN8855_PMCR_FORCE_SPEED\tGENMASK(30, 28)\n+#define AN8855_PMCR_FORCE_SPEED_5000\tFIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4)\n+#define AN8855_PMCR_FORCE_SPEED_2500\tFIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3)\n+#define AN8855_PMCR_FORCE_SPEED_1000\tFIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2)\n+#define AN8855_PMCR_FORCE_SPEED_100\tFIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)\n+#define AN8855_PMCR_FORCE_SPEED_10\tFIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x0)\n+#define AN8855_PMCR_FORCE_FDX\t\tBIT(25)\n+#define AN8855_PMCR_FORCE_LNK\t\tBIT(24)\n+#define AN8855_PMCR_IFG_XMIT\t\tGENMASK(21, 20)\n+#define AN8855_PMCR_EXT_PHY\t\tBIT(19)\n+#define AN8855_PMCR_MAC_MODE\t\tBIT(18)\n+#define AN8855_PMCR_TX_EN\t\tBIT(16)\n+#define AN8855_PMCR_RX_EN\t\tBIT(15)\n+#define AN8855_PMCR_BACKOFF_EN\tBIT(12)\n+#define AN8855_PMCR_BACKPR_EN\t\tBIT(11)\n+#define AN8855_PMCR_FORCE_EEE5G\tBIT(9)\n+#define AN8855_PMCR_FORCE_EEE2P5G\tBIT(8)\n+#define AN8855_PMCR_FORCE_EEE1G\tBIT(7)\n+#define AN8855_PMCR_FORCE_EEE100\tBIT(6)\n+#define AN8855_PMCR_RX_FC_EN\t\tBIT(5)\n+#define AN8855_PMCR_TX_FC_EN\t\tBIT(4)\n+\n+#define AN8855_PMSR_P(x)\t\t(0x10210010 + (x) * 0x200)\n+#define AN8855_PMSR_SPEED\t\tGENMASK(30, 28)\n+#define AN8855_PMSR_SPEED_5000\tFIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4)\n+#define AN8855_PMSR_SPEED_2500\tFIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3)\n+#define AN8855_PMSR_SPEED_1000\tFIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2)\n+#define AN8855_PMSR_SPEED_100\t\tFIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1)\n+#define AN8855_PMSR_SPEED_10\t\tFIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0)\n+#define AN8855_PMSR_DPX\t\tBIT(25)\n+#define AN8855_PMSR_LNK\t\tBIT(24)\n+#define AN8855_PMSR_EEE1G\t\tBIT(7)\n+#define AN8855_PMSR_EEE100M\t\tBIT(6)\n+#define AN8855_PMSR_RX_FC\t\tBIT(5)\n+#define AN8855_PMSR_TX_FC\t\tBIT(4)\n+\n+#define AN8855_PMEEECR_P(x)\t\t(0x10210004 + (x) * 0x200)\n+#define AN8855_LPI_MODE_EN\t\tBIT(31)\n+#define AN8855_WAKEUP_TIME_2500\tGENMASK(23, 16)\n+#define AN8855_WAKEUP_TIME_1000\tGENMASK(15, 8)\n+#define AN8855_WAKEUP_TIME_100\tGENMASK(7, 0)\n+#define AN8855_PMEEECR2_P(x)\t\t(0x10210008 + (x) * 0x200)\n+#define AN8855_WAKEUP_TIME_5000\tGENMASK(7, 0)\n+\n+#define AN8855_GMACCR\t\t\t0x10213e00\n+#define AN8855_MAX_RX_JUMBO\t\tGENMASK(7, 4)\n+/* 2K for 0x0, 0x1, 0x2 */\n+#define AN8855_MAX_RX_JUMBO_2K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0)\n+#define AN8855_MAX_RX_JUMBO_3K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3)\n+#define AN8855_MAX_RX_JUMBO_4K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4)\n+#define AN8855_MAX_RX_JUMBO_5K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5)\n+#define AN8855_MAX_RX_JUMBO_6K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6)\n+#define AN8855_MAX_RX_JUMBO_7K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7)\n+#define AN8855_MAX_RX_JUMBO_8K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8)\n+#define AN8855_MAX_RX_JUMBO_9K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)\n+#define AN8855_MAX_RX_JUMBO_12K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)\n+#define AN8855_MAX_RX_JUMBO_15K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)\n+#define AN8855_MAX_RX_JUMBO_16K\tFIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)\n+#define AN8855_MAX_RX_PKT_LEN\t\tGENMASK(1, 0)\n+#define AN8855_MAX_RX_PKT_1518_1522\tFIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0)\n+#define AN8855_MAX_RX_PKT_1536\tFIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1)\n+#define AN8855_MAX_RX_PKT_1552\tFIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2)\n+#define AN8855_MAX_RX_PKT_JUMBO\tFIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3)\n+\n+#define AN8855_CKGCR\t\t\t0x10213e1c\n+#define AN8855_LPI_TXIDLE_THD_MASK\tGENMASK(31, 14)\n+#define AN8855_CKG_LNKDN_PORT_STOP\tBIT(1)\n+#define AN8855_CKG_LNKDN_GLB_STOP\tBIT(0)\n+\n+/* Register for MIB */\n+#define AN8855_MIB_COUNTER\t\t0x10214000\n+#define AN8855_PORT_MIB_COUNTER(x)\t(AN8855_MIB_COUNTER + (x) * 0x200)\n+/* Each define is an offset of AN8855_PORT_MIB_COUNTER */\n+#define AN8855_PORT_MIB_TX_DROP\t(AN8855_MIB_COUNTER + 0x00)\n+#define AN8855_PORT_MIB_TX_CRC_ERR\t(AN8855_MIB_COUNTER + 0x04)\n+#define AN8855_PORT_MIB_TX_UNICAST\t(AN8855_MIB_COUNTER + 0x08)\n+#define AN8855_PORT_MIB_TX_MULTICAST\t(AN8855_MIB_COUNTER + 0x0c)\n+#define AN8855_PORT_MIB_TX_BROADCAST\t(AN8855_MIB_COUNTER + 0x10)\n+#define AN8855_PORT_MIB_TX_COLLISION\t(AN8855_MIB_COUNTER + 0x14)\n+#define AN8855_PORT_MIB_TX_SINGLE_COLLISION (AN8855_MIB_COUNTER + 0x18)\n+#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION (AN8855_MIB_COUNTER + 0x1c)\n+#define AN8855_PORT_MIB_TX_DEFERRED\t(AN8855_MIB_COUNTER + 0x20)\n+#define AN8855_PORT_MIB_TX_LATE_COLLISION (AN8855_MIB_COUNTER + 0x24)\n+#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION (AN8855_MIB_COUNTER + 0x28)\n+#define AN8855_PORT_MIB_TX_PAUSE\t(AN8855_MIB_COUNTER + 0x2c)\n+#define AN8855_PORT_MIB_TX_PKT_SZ_64\t(AN8855_MIB_COUNTER + 0x30)\n+#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0x34)\n+#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0x38)\n+#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0x3c)\n+#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0x40)\n+#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0x44)\n+#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0x48)\n+#define AN8855_PORT_MIB_TX_BYTES_LOW\t(AN8855_MIB_COUNTER + 0x4c) /* 64 bytes */\n+#define AN8855_PORT_MIB_TX_BYTES_HIGH\t(AN8855_MIB_COUNTER + 0x50)\n+#define AN8855_PORT_MIB_TX_OVERSIZE_DROP (AN8855_MIB_COUNTER + 0x54)\n+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0x58) /* 64 bytes */\n+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0x5c)\n+#define AN8855_PORT_MIB_RX_DROP\t(AN8855_MIB_COUNTER + 0x80)\n+#define AN8855_PORT_MIB_RX_FILTERING\t(AN8855_MIB_COUNTER + 0x84)\n+#define AN8855_PORT_MIB_RX_UNICAST\t(AN8855_MIB_COUNTER + 0x88)\n+#define AN8855_PORT_MIB_RX_MULTICAST\t(AN8855_MIB_COUNTER + 0x8c)\n+#define AN8855_PORT_MIB_RX_BROADCAST\t(AN8855_MIB_COUNTER + 0x90)\n+#define AN8855_PORT_MIB_RX_ALIGN_ERR\t(AN8855_MIB_COUNTER + 0x94)\n+#define AN8855_PORT_MIB_RX_CRC_ERR\t(AN8855_MIB_COUNTER + 0x98)\n+#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR (AN8855_MIB_COUNTER + 0x9c)\n+#define AN8855_PORT_MIB_RX_FRAG_ERR\t(AN8855_MIB_COUNTER + 0xa0)\n+#define AN8855_PORT_MIB_RX_OVER_SZ_ERR (AN8855_MIB_COUNTER + 0xa4)\n+#define AN8855_PORT_MIB_RX_JABBER_ERR\t(AN8855_MIB_COUNTER + 0xa8)\n+#define AN8855_PORT_MIB_RX_PAUSE\t(AN8855_MIB_COUNTER + 0xac)\n+#define AN8855_PORT_MIB_RX_PKT_SZ_64\t(AN8855_MIB_COUNTER + 0xb0)\n+#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0xb4)\n+#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0xb8)\n+#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0xbc)\n+#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0xc0)\n+#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0xc4)\n+#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0xc8)\n+#define AN8855_PORT_MIB_RX_BYTES_LOW\t(AN8855_MIB_COUNTER + 0xcc) /* 64 bytes */\n+#define AN8855_PORT_MIB_RX_BYTES_HIGH\t(AN8855_MIB_COUNTER + 0xd0)\n+#define AN8855_PORT_MIB_RX_CTRL_DROP\t(AN8855_MIB_COUNTER + 0xd4)\n+#define AN8855_PORT_MIB_RX_INGRESS_DROP (AN8855_MIB_COUNTER + 0xd8)\n+#define AN8855_PORT_MIB_RX_ARL_DROP\t(AN8855_MIB_COUNTER + 0xdc)\n+#define AN8855_PORT_MIB_FLOW_CONTROL_DROP (AN8855_MIB_COUNTER + 0xe0)\n+#define AN8855_PORT_MIB_WRED_DROP\t(AN8855_MIB_COUNTER + 0xe4)\n+#define AN8855_PORT_MIB_MIRROR_DROP\t(AN8855_MIB_COUNTER + 0xe8)\n+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0xec) /* 64 bytes */\n+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0xf0)\n+#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP (AN8855_MIB_COUNTER + 0xf4)\n+#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP (AN8855_MIB_COUNTER + 0xf8)\n+#define AN8855_PORT_MIB_PORT_CONTROL_DROP (AN8855_MIB_COUNTER + 0xfc)\n+#define AN8855_MIB_CCR\t\t\t0x10213e30\n+#define AN8855_CCR_MIB_ENABLE\t\tBIT(31)\n+#define AN8855_CCR_RX_OCT_CNT_GOOD\tBIT(7)\n+#define AN8855_CCR_RX_OCT_CNT_BAD\tBIT(6)\n+#define AN8855_CCR_TX_OCT_CNT_GOOD\tBIT(5)\n+#define AN8855_CCR_TX_OCT_CNT_BAD\tBIT(4)\n+#define AN8855_CCR_RX_OCT_CNT_GOOD_2\tBIT(3)\n+#define AN8855_CCR_RX_OCT_CNT_BAD_2\tBIT(2)\n+#define AN8855_CCR_TX_OCT_CNT_GOOD_2\tBIT(1)\n+#define AN8855_CCR_TX_OCT_CNT_BAD_2\tBIT(0)\n+#define AN8855_CCR_MIB_ACTIVATE\t(AN8855_CCR_MIB_ENABLE | \\\n+\t\t\t\t\t AN8855_CCR_RX_OCT_CNT_GOOD | \\\n+\t\t\t\t\t AN8855_CCR_RX_OCT_CNT_BAD | \\\n+\t\t\t\t\t AN8855_CCR_TX_OCT_CNT_GOOD | \\\n+\t\t\t\t\t AN8855_CCR_TX_OCT_CNT_BAD | \\\n+\t\t\t\t\t AN8855_CCR_RX_OCT_CNT_BAD_2 | \\\n+\t\t\t\t\t AN8855_CCR_TX_OCT_CNT_BAD_2)\n+#define AN8855_MIB_CLR\t\t\t0x10213e34\n+#define AN8855_MIB_PORT6_CLR\t\tBIT(6)\n+#define AN8855_MIB_PORT5_CLR\t\tBIT(5)\n+#define AN8855_MIB_PORT4_CLR\t\tBIT(4)\n+#define AN8855_MIB_PORT3_CLR\t\tBIT(3)\n+#define AN8855_MIB_PORT2_CLR\t\tBIT(2)\n+#define AN8855_MIB_PORT1_CLR\t\tBIT(1)\n+#define AN8855_MIB_PORT0_CLR\t\tBIT(0)\n+\n+/* HSGMII/SGMII Configuration register */\n+/*\tAN8855_HSGMII_AN_CSR_BASE\t0x10220000 */\n+#define AN8855_SGMII_REG_AN0\t\t0x10220000\n+/* AN8855_SGMII_AN_ENABLE\tBMCR_ANENABLE */\n+/* AN8855_SGMII_AN_RESTART\tBMCR_ANRESTART */\n+#define AN8855_SGMII_REG_AN_13\t\t0x10220034\n+#define AN8855_SGMII_REMOTE_FAULT_DIS\tBIT(8)\n+#define AN8855_SGMII_IF_MODE\t\tGENMASK(5, 0)\n+#define AN8855_SGMII_REG_AN_FORCE_CL37\t0x10220060\n+#define AN8855_RG_FORCE_AN_DONE\tBIT(0)\n+\n+/*\tAN8855_HSGMII_CSR_PCS_BASE\t0x10220000 */\n+#define AN8855_RG_HSGMII_PCS_CTROL_1\t0x10220a00\n+#define AN8855_RG_TBI_10B_MODE\tBIT(30)\n+#define AN8855_RG_AN_SGMII_MODE_FORCE\t0x10220a24\n+#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4)\n+#define AN8855_RG_FORCE_CUR_SGMII_SEL\tBIT(0)\n+\n+/*\tAN8855_MULTI_SGMII_CSR_BASE\t0x10224000 */\n+#define AN8855_SGMII_STS_CTRL_0\t\t0x10224018\n+#define AN8855_RG_LINK_MODE_P0\tGENMASK(5, 4)\n+#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3)\n+#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2)\n+#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1)\n+#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0)\n+#define AN8855_RG_FORCE_SPD_MODE_P0\tBIT(2)\n+#define AN8855_MSG_RX_CTRL_0\t\t0x10224100\n+#define AN8855_MSG_RX_LIK_STS_0\t\t0x10224514\n+#define AN8855_RG_DPX_STS_P3\t\tBIT(24)\n+#define AN8855_RG_DPX_STS_P2\t\tBIT(16)\n+#define AN8855_RG_EEE1G_STS_P1\tBIT(12)\n+#define AN8855_RG_DPX_STS_P1\t\tBIT(8)\n+#define AN8855_RG_TXFC_STS_P0\t\tBIT(2)\n+#define AN8855_RG_RXFC_STS_P0\t\tBIT(1)\n+#define AN8855_RG_DPX_STS_P0\t\tBIT(0)\n+#define AN8855_MSG_RX_LIK_STS_2\t\t0x1022451c\n+#define AN8855_RG_RXFC_AN_BYPASS_P3\tBIT(11)\n+#define AN8855_RG_RXFC_AN_BYPASS_P2\tBIT(10)\n+#define AN8855_RG_RXFC_AN_BYPASS_P1\tBIT(9)\n+#define AN8855_RG_TXFC_AN_BYPASS_P3\tBIT(7)\n+#define AN8855_RG_TXFC_AN_BYPASS_P2\tBIT(6)\n+#define AN8855_RG_TXFC_AN_BYPASS_P1\tBIT(5)\n+#define AN8855_RG_DPX_AN_BYPASS_P3\tBIT(3)\n+#define AN8855_RG_DPX_AN_BYPASS_P2\tBIT(2)\n+#define AN8855_RG_DPX_AN_BYPASS_P1\tBIT(1)\n+#define AN8855_RG_DPX_AN_BYPASS_P0\tBIT(0)\n+#define AN8855_PHY_RX_FORCE_CTRL_0\t0x10224520\n+#define AN8855_RG_FORCE_TXC_SEL\tBIT(4)\n+\n+/*\tAN8855_XFI_CSR_PCS_BASE\t\t0x10225000 */\n+#define AN8855_RG_USXGMII_AN_CONTROL_0\t0x10225bf8\n+\n+/*\tAN8855_MULTI_PHY_RA_CSR_BASE\t0x10226000 */\n+#define AN8855_RG_RATE_ADAPT_CTRL_0\t0x10226000\n+#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27)\n+#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26)\n+#define AN8855_RG_RATE_ADAPT_RX_EN\tBIT(4)\n+#define AN8855_RG_RATE_ADAPT_TX_EN\tBIT(0)\n+#define AN8855_RATE_ADP_P0_CTRL_0\t0x10226100\n+#define AN8855_RG_P0_DIS_MII_MODE\tBIT(31)\n+#define AN8855_RG_P0_MII_MODE\t\tBIT(28)\n+#define AN8855_RG_P0_MII_RA_RX_EN\tBIT(3)\n+#define AN8855_RG_P0_MII_RA_TX_EN\tBIT(2)\n+#define AN8855_RG_P0_MII_RA_RX_MODE\tBIT(1)\n+#define AN8855_RG_P0_MII_RA_TX_MODE\tBIT(0)\n+#define AN8855_MII_RA_AN_ENABLE\t\t0x10226300\n+#define AN8855_RG_P0_RA_AN_EN\t\tBIT(0)\n+\n+/*\tAN8855_QP_DIG_CSR_BASE\t\t0x1022a000 */\n+#define AN8855_QP_CK_RST_CTRL_4\t\t0x1022a310\n+#define AN8855_QP_DIG_MODE_CTRL_0\t0x1022a324\n+#define AN8855_RG_SGMII_MODE\t\tGENMASK(5, 4)\n+#define AN8855_RG_SGMII_AN_EN\t\tBIT(0)\n+#define AN8855_QP_DIG_MODE_CTRL_1\t0x1022a330\n+#define AN8855_RG_TPHY_SPEED\t\tGENMASK(3, 2)\n+\n+/*\tAN8855_SERDES_WRAPPER_BASE\t0x1022c000 */\n+#define AN8855_USGMII_CTRL_0\t\t0x1022c000\n+\n+/*\tAN8855_QP_PMA_TOP_BASE\t\t0x1022e000 */\n+#define AN8855_PON_RXFEDIG_CTRL_0\t0x1022e100\n+#define AN8855_RG_QP_EQ_RX500M_CK_SEL\tBIT(12)\n+#define AN8855_PON_RXFEDIG_CTRL_9\t0x1022e124\n+#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT\tGENMASK(2, 0)\n+\n+#define AN8855_SS_LCPLL_PWCTL_SETTING_2\t0x1022e208\n+#define AN8855_RG_NCPO_ANA_MSB\tGENMASK(17, 16)\n+#define AN8855_SS_LCPLL_TDC_FLT_2\t0x1022e230\n+#define AN8855_RG_LCPLL_NCPO_VALUE\tGENMASK(30, 0)\n+#define AN8855_SS_LCPLL_TDC_FLT_5\t0x1022e23c\n+#define AN8855_RG_LCPLL_NCPO_CHG\tBIT(24)\n+#define AN8855_SS_LCPLL_TDC_PCW_1\t0x1022e248\n+#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)\n+#define AN8855_INTF_CTRL_8\t\t0x1022e320\n+#define AN8855_INTF_CTRL_9\t\t0x1022e324\n+#define AN8855_INTF_CTRL_10\t\t0x1022e328\n+#define AN8855_RG_DA_QP_TX_FIR_C2_SEL\tBIT(29)\n+#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24)\n+#define AN8855_RG_DA_QP_TX_FIR_C1_SEL\tBIT(21)\n+#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16)\n+#define AN8855_INTF_CTRL_11\t\t0x1022e32c\n+#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6)\n+#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0)\n+#define AN8855_PLL_CTRL_0\t\t0x1022e400\n+#define AN8855_RG_PHYA_AUTO_INIT\tBIT(0)\n+#define AN8855_PLL_CTRL_2\t\t0x1022e408\n+#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30)\n+#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29)\n+#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28)\n+#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27)\n+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26)\n+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24)\n+#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22)\n+#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20)\n+#define AN8855_RG_DA_QP_PLL_IR_INTF\tGENMASK(19, 16)\n+#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14)\n+#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12)\n+#define AN8855_RG_DA_QP_PLL_BR_INTF\tGENMASK(10, 8)\n+#define AN8855_RG_DA_QP_PLL_BPD_INTF\tGENMASK(7, 6)\n+#define AN8855_RG_DA_QP_PLL_BPA_INTF\tGENMASK(4, 2)\n+#define AN8855_RG_DA_QP_PLL_BC_INTF\tGENMASK(1, 0)\n+#define AN8855_PLL_CTRL_3\t\t0x1022e40c\n+#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16)\n+#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0)\n+#define AN8855_PLL_CTRL_4\t\t0x1022e410\n+#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)\n+#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2)\n+#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0)\n+#define AN8855_PLL_CK_CTRL_0\t\t0x1022e414\n+#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9)\n+#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8)\n+#define AN8855_RX_DLY_0\t\t\t0x1022e614\n+#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8)\n+#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0)\n+#define AN8855_RX_CTRL_2\t\t0x1022e630\n+#define AN8855_RG_QP_RX_EQ_EN_H_DLY\tGENMASK(28, 16)\n+#define AN8855_RX_CTRL_5\t\t0x1022e63c\n+#define AN8855_RG_FREDET_CHK_CYCLE\tGENMASK(29, 10)\n+#define AN8855_RX_CTRL_6\t\t0x1022e640\n+#define AN8855_RG_FREDET_GOLDEN_CYCLE\tGENMASK(19, 0)\n+#define AN8855_RX_CTRL_7\t\t0x1022e644\n+#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0)\n+#define AN8855_RX_CTRL_8\t\t0x1022e648\n+#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16)\n+#define AN8855_RG_DA_QP_LEQOS_EN_TIME\tGENMASK(14, 0)\n+#define AN8855_RX_CTRL_26\t\t0x1022e690\n+#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26)\n+#define AN8855_RG_LINK_NE_EN\t\tBIT(24)\n+#define AN8855_RG_LINK_ERRO_EN\tBIT(23)\n+#define AN8855_RX_CTRL_42\t\t0x1022e6d0\n+#define AN8855_RG_QP_EQ_EN_DLY\tGENMASK(12, 0)\n+\n+/*\tAN8855_QP_ANA_CSR_BASE\t\t0x1022f000 */\n+#define AN8855_RG_QP_RX_DAC_EN\t\t0x1022f000\n+#define AN8855_RG_QP_SIGDET_HF\tGENMASK(17, 16)\n+#define AN8855_RG_QP_RXAFE_RESERVE\t0x1022f004\n+#define AN8855_RG_QP_CDR_PD_10B_EN\tBIT(11)\n+#define AN8855_RG_QP_CDR_LPF_BOT_LIM\t0x1022f008\n+#define AN8855_RG_QP_CDR_LPF_KP_GAIN\tGENMASK(26, 24)\n+#define AN8855_RG_QP_CDR_LPF_KI_GAIN\tGENMASK(22, 20)\n+#define AN8855_RG_QP_CDR_LPF_MJV_LIM\t0x1022f00c\n+#define AN8855_RG_QP_CDR_LPF_RATIO\tGENMASK(5, 4)\n+#define AN8855_RG_QP_CDR_LPF_SETVALUE\t0x1022f014\n+#define AN8855_RG_QP_CDR_PR_BUF_IN_SR\tGENMASK(31, 29)\n+#define AN8855_RG_QP_CDR_PR_BETA_SEL\tGENMASK(28, 25)\n+#define AN8855_RG_QP_CDR_PR_CKREF_DIV1\t0x1022f018\n+#define AN8855_RG_QP_CDR_PR_KBAND_DIV\tGENMASK(26, 24)\n+#define AN8855_RG_QP_CDR_PR_DAC_BAND\tGENMASK(12, 8)\n+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c\n+#define AN8855_RG_QP_CDR_PR_XFICK_EN\tBIT(30)\n+#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6)\n+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0)\n+#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020\n+#define AN8855_RG_QP_CDR_PHYCK_SEL\tGENMASK(17, 16)\n+#define AN8855_RG_QP_CDR_PHYCK_RSTB\tBIT(13)\n+#define AN8855_RG_QP_CDR_PHYCK_DIV\tGENMASK(12, 6)\n+#define AN8855_RG_QP_TX_MODE\t\t0x1022f028\n+#define AN8855_RG_QP_TX_RESERVE\tGENMASK(31, 16)\n+#define AN8855_RG_QP_TX_MODE_16B_EN\tBIT(0)\n+#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c\n+#define AN8855_RG_QP_PLL_SDM_ORD\t0x1022f040\n+#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4)\n+#define AN8855_RG_QP_PLL_SSC_TRI_EN\tBIT(3)\n+\n+/*\tAN8855_ETHER_SYS_BASE\t\t0x1028c800 */\n+#define AN8855_RG_GPHY_AFE_PWD\t\t0x1028c840\n+#define AN8855_RG_GPHY_SMI_ADDR\t\t0x1028c848\n+\n+struct an8855_priv {\n+\tstruct dsa_switch *ds;\n+\tstruct regmap *regmap;\n+\t/* Protect ATU or VLAN table access */\n+\tstruct mutex reg_mutex;\n+\n+\tstruct phylink_pcs pcs;\n+\n+\tstruct mt7530_port ports[AN8855_NUM_PORTS];\n+\tu32 tx_lpi_timer_ports[AN8855_NUM_PORTS];\n+\n+\tstruct mt7530_lib_priv lib_priv;\n+};\n+\n+#endif /* __AN8855_H */\ndiff --git a/drivers/net/dsa/mt7530-lib.c b/drivers/net/dsa/mt7530-lib.c\nnew file mode 100644\nindex 0000000000000..cf474faf8ed6a\n--- /dev/null\n+++ b/drivers/net/dsa/mt7530-lib.c\n@@ -0,0 +1,1156 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+\n+#include \u003clinux/device.h\u003e\n+#include \u003clinux/if_bridge.h\u003e\n+#include \u003clinux/module.h\u003e\n+#include \u003clinux/regmap.h\u003e\n+#include \u003cnet/dsa.h\u003e\n+\n+#include \"mt7530-lib.h\"\n+\n+void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv)\n+{\n+\tregmap_field_write(priv-\u003efields[MT7530_CCR_MIB_ENABLE], 0);\n+\tregmap_field_write(priv-\u003efields[MT7530_CCR_RX_OCT_CNT_GOOD], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_CCR_RX_OCT_CNT_BAD], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_CCR_TX_OCT_CNT_GOOD], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_CCR_TX_OCT_CNT_BAD], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_CCR_MIB_ENABLE], 1);\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_mib_reset);\n+\n+/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)\n+ * of the Open Systems Interconnection basic reference model (OSI/RM) are\n+ * described; the medium access control (MAC) and logical link control (LLC)\n+ * sublayers. The MAC sublayer is the one facing the physical layer.\n+ *\n+ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A\n+ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports\n+ * of the Bridge, at least two Ports, and higher layer entities with at least a\n+ * Spanning Tree Protocol Entity included.\n+ *\n+ * Each Bridge Port also functions as an end station and shall provide the MAC\n+ * Service to an LLC Entity. Each instance of the MAC Service is provided to a\n+ * distinct LLC Entity that supports protocol identification, multiplexing, and\n+ * demultiplexing, for protocol data unit (PDU) transmission and reception by\n+ * one or more higher layer entities.\n+ *\n+ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC\n+ * Entity associated with each Bridge Port is modeled as being directly\n+ * connected to the attached Local Area Network (LAN).\n+ *\n+ * On the switch with CPU port architecture, CPU port functions as Management\n+ * Port, and the Management Port functionality is provided by software which\n+ * functions as an end station. Software is connected to an IEEE 802 LAN that is\n+ * wholly contained within the system that incorporates the Bridge. Software\n+ * provides access to the LLC Entity associated with each Bridge Port by the\n+ * value of the source port field on the special tag on the frame received by\n+ * software.\n+ *\n+ * We call frames that carry control information to determine the active\n+ * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,\n+ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration\n+ * Protocol Data Units (MVRPDUs), and frames from other link constrained\n+ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and\n+ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not\n+ * forwarded by a Bridge. Permanently configured entries in the filtering\n+ * database (FDB) ensure that such frames are discarded by the Forwarding\n+ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:\n+ *\n+ * Each of the reserved MAC addresses specified in Table 8-1\n+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be\n+ * permanently configured in the FDB in C-VLAN components and ERs.\n+ *\n+ * Each of the reserved MAC addresses specified in Table 8-2\n+ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently\n+ * configured in the FDB in S-VLAN components.\n+ *\n+ * Each of the reserved MAC addresses specified in Table 8-3\n+ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in\n+ * TPMR components.\n+ *\n+ * The FDB entries for reserved MAC addresses shall specify filtering for all\n+ * Bridge Ports and all VIDs. Management shall not provide the capability to\n+ * modify or remove entries for reserved MAC addresses.\n+ *\n+ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of\n+ * propagation of PDUs within a Bridged Network, as follows:\n+ *\n+ * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no\n+ * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)\n+ * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.\n+ * PDUs transmitted using this destination address, or any other addresses\n+ * that appear in Table 8-1, Table 8-2, and Table 8-3\n+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can\n+ * therefore travel no further than those stations that can be reached via a\n+ * single individual LAN from the originating station.\n+ *\n+ * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an\n+ * address that no conformant S-VLAN component, C-VLAN component, or MAC\n+ * Bridge can forward; however, this address is relayed by a TPMR component.\n+ * PDUs using this destination address, or any of the other addresses that\n+ * appear in both Table 8-1 and Table 8-2 but not in Table 8-3\n+ * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by\n+ * any TPMRs but will propagate no further than the nearest S-VLAN component,\n+ * C-VLAN component, or MAC Bridge.\n+ *\n+ * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address\n+ * that no conformant C-VLAN component, MAC Bridge can forward; however, it is\n+ * relayed by TPMR components and S-VLAN components. PDUs using this\n+ * destination address, or any of the other addresses that appear in Table 8-1\n+ * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),\n+ * will be relayed by TPMR components and S-VLAN components but will propagate\n+ * no further than the nearest C-VLAN component or MAC Bridge.\n+ *\n+ * Because the LLC Entity associated with each Bridge Port is provided via CPU\n+ * port, we must not filter these frames but forward them to CPU port.\n+ *\n+ * In a Bridge, the transmission Port is majorly decided by ingress and egress\n+ * rules, FDB, and spanning tree Port State functions of the Forwarding Process.\n+ * For link-local frames, only CPU port should be designated as destination port\n+ * in the FDB, and the other functions of the Forwarding Process must not\n+ * interfere with the decision of the transmission Port. We call this process\n+ * trapping frames to CPU port.\n+ *\n+ * Therefore, on the switch with CPU port architecture, link-local frames must\n+ * be trapped to CPU port, and certain link-local frames received by a Port of a\n+ * Bridge comprising a TPMR component or an S-VLAN component must be excluded\n+ * from it.\n+ *\n+ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port\n+ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the\n+ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port\n+ * doesn't count) of this architecture will either function as a standard MAC\n+ * Bridge or a standard VLAN Bridge.\n+ *\n+ * Therefore, a Bridge of this architecture can only comprise S-VLAN components,\n+ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,\n+ * we don't need to relay PDUs using the destination addresses specified on the\n+ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge\n+ * section where they must be relayed by TPMR components.\n+ *\n+ * One option to trap link-local frames to CPU port is to add static FDB entries\n+ * with CPU port designated as destination port. However, because that\n+ * Independent VLAN Learning (IVL) is being used on every VID, each entry only\n+ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC\n+ * Bridge component or a C-VLAN component, there would have to be 16 times 4096\n+ * entries. This switch intellectual property can only hold a maximum of 2048\n+ * entries. Using this option, there also isn't a mechanism to prevent\n+ * link-local frames from being discarded when the spanning tree Port State of\n+ * the reception Port is discarding.\n+ *\n+ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4\n+ * registers. Whilst this applies to every VID, it doesn't contain all of the\n+ * reserved MAC addresses without affecting the remaining Standard Group MAC\n+ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the\n+ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination\n+ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF\n+ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.\n+ * The latter option provides better but not complete conformance.\n+ *\n+ * This switch intellectual property also does not provide a mechanism to trap\n+ * link-local frames with specific destination addresses to CPU port by Bridge,\n+ * to conform to the filtering rules for the distinct Bridge components.\n+ *\n+ * Therefore, regardless of the type of the Bridge component, link-local frames\n+ * with these destination addresses will be trapped to CPU port:\n+ *\n+ * 01-80-C2-00-00-[00,01,02,03,0E]\n+ *\n+ * In a Bridge comprising a MAC Bridge component or a C-VLAN component:\n+ *\n+ * Link-local frames with these destination addresses won't be trapped to CPU\n+ * port which won't conform to IEEE Std 802.1Q-2022:\n+ *\n+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]\n+ *\n+ * In a Bridge comprising an S-VLAN component:\n+ *\n+ * Link-local frames with these destination addresses will be trapped to CPU\n+ * port which won't conform to IEEE Std 802.1Q-2022:\n+ *\n+ * 01-80-C2-00-00-00\n+ *\n+ * Link-local frames with these destination addresses won't be trapped to CPU\n+ * port which won't conform to IEEE Std 802.1Q-2022:\n+ *\n+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A]\n+ *\n+ * To trap link-local frames to CPU port as conformant as this switch\n+ * intellectual property can allow, link-local frames are made to be regarded as\n+ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual\n+ * property only lets the frames regarded as BPDUs bypass the spanning tree Port\n+ * State function of the Forwarding Process.\n+ *\n+ * The only remaining interference is the ingress rules. When the reception Port\n+ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.\n+ * There doesn't seem to be a mechanism on the switch intellectual property to\n+ * have link-local frames bypass this function of the Forwarding Process.\n+ */\n+void mt7530_lib_trap_frames(struct mt7530_lib_priv *priv)\n+{\n+\t/* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress\n+\t * them with the EG_TAG attribute set to disabled (system default)\n+\t * so that any VLAN tags in the frame are not modified by the\n+\t * switch egress VLAN tag processing. This preserves VLAN tags\n+\t * for reception on VLAN sub-interfaces.\n+\t */\n+\tregmap_field_write(priv-\u003efields[MT7530_BPDU_EG_TAG],\n+\t\t\t MT7530_VLAN_EG_DISABLED);\n+\tregmap_field_write(priv-\u003efields[MT7530_BPDU_PORT_FW],\n+\t\t\t TO_CPU_FW_CPU_ONLY);\n+\tregmap_field_write(priv-\u003efields[MT7530_PAE_BPDU_FR], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_PAE_EG_TAG],\n+\t\t\t MT7530_VLAN_EG_DISABLED);\n+\tregmap_field_write(priv-\u003efields[MT7530_PAE_PORT_FW],\n+\t\t\t TO_CPU_FW_CPU_ONLY);\n+\n+\t/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and\n+\t * egress them with EG_TAG disabled.\n+\t */\n+\tregmap_field_write(priv-\u003efields[MT7530_R01_BPDU_FR], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_R01_EG_TAG],\n+\t\t\t MT7530_VLAN_EG_DISABLED);\n+\tregmap_field_write(priv-\u003efields[MT7530_R01_PORT_FW],\n+\t\t\t TO_CPU_FW_CPU_ONLY);\n+\tregmap_field_write(priv-\u003efields[MT7530_R02_BPDU_FR], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_R02_EG_TAG],\n+\t\t\t MT7530_VLAN_EG_DISABLED);\n+\tregmap_field_write(priv-\u003efields[MT7530_R02_PORT_FW],\n+\t\t\t TO_CPU_FW_CPU_ONLY);\n+\n+\t/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and\n+\t * egress them with EG_TAG disabled.\n+\t */\n+\tregmap_field_write(priv-\u003efields[MT7530_R03_BPDU_FR], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_R03_EG_TAG],\n+\t\t\t MT7530_VLAN_EG_DISABLED);\n+\tregmap_field_write(priv-\u003efields[MT7530_R03_PORT_FW],\n+\t\t\t TO_CPU_FW_CPU_ONLY);\n+\tregmap_field_write(priv-\u003efields[MT7530_R0E_BPDU_FR], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_R0E_EG_TAG],\n+\t\t\t MT7530_VLAN_EG_DISABLED);\n+\tregmap_field_write(priv-\u003efields[MT7530_R0E_PORT_FW],\n+\t\t\t TO_CPU_FW_CPU_ONLY);\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_trap_frames);\n+\n+static void mt7530_update_port_member(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t const struct net_device *bridge_dev,\n+\t\t\t\t bool join) __must_hold(priv-\u003ereg_mutex)\n+{\n+\tstruct dsa_port *dp = dsa_to_port(priv-\u003eds, port), *other_dp;\n+\tstruct mt7530_port *p = \u0026priv-\u003eports[port], *other_p;\n+\tstruct dsa_port *cpu_dp = dp-\u003ecpu_dp;\n+\tu32 port_bitmap = BIT(cpu_dp-\u003eindex);\n+\tint other_port;\n+\tbool isolated;\n+\n+\tdsa_switch_for_each_user_port(other_dp, priv-\u003eds) {\n+\t\tother_port = other_dp-\u003eindex;\n+\t\tother_p = \u0026priv-\u003eports[other_port];\n+\n+\t\tif (dp == other_dp)\n+\t\t\tcontinue;\n+\n+\t\t/* Add/remove this port to/from the port matrix of the other\n+\t\t * ports in the same bridge. If the port is disabled, port\n+\t\t * matrix is kept and not being setup until the port becomes\n+\t\t * enabled.\n+\t\t */\n+\t\tif (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev))\n+\t\t\tcontinue;\n+\n+\t\tisolated = p-\u003eisolated \u0026\u0026 other_p-\u003eisolated;\n+\n+\t\tif (join \u0026\u0026 !isolated) {\n+\t\t\tother_p-\u003epm |= BIT(port);\n+\t\t\tport_bitmap |= BIT(other_port);\n+\t\t} else {\n+\t\t\tother_p-\u003epm \u0026= ~BIT(port);\n+\t\t}\n+\n+\t\tif (other_p-\u003eenable)\n+\t\t\tregmap_fields_write(priv-\u003efields[MT7530_PCR_MATRIX],\n+\t\t\t\t\t other_port, other_p-\u003epm);\n+\t}\n+\n+\t/* Add/remove the all other ports to this port matrix. For !join\n+\t * (leaving the bridge), only the CPU port will remain in the port matrix\n+\t * of this port.\n+\t */\n+\tp-\u003epm = port_bitmap;\n+\tif (priv-\u003eports[port].enable)\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PCR_MATRIX],\n+\t\t\t\t port, port_bitmap);\n+}\n+\n+void mt7530_lib_read_port_stats(struct regmap_field *low,\n+\t\t\t\tstruct regmap_field *high,\n+\t\t\t\tint port, uint64_t *data)\n+{\n+\tu32 val = 0;\n+\n+\tregmap_fields_read(low, port, \u0026val);\n+\t*data = val;\n+\n+\tif (high) {\n+\t\tval = 0;\n+\t\tregmap_fields_read(high, port, \u0026val);\n+\t\t*data |= (u64)val \u003c\u003c 32;\n+\t}\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_read_port_stats);\n+\n+void mt7530_lib_get_eth_mac_stats(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t struct ethtool_eth_mac_stats *mac_stats)\n+{\n+\t/* MIB counter doesn't provide a FramesTransmittedOK but instead\n+\t * provide stats for Unicast, Broadcast and Multicast frames separately.\n+\t * To simulate a global frame counter, read Unicast and addition Multicast\n+\t * and Broadcast later\n+\t */\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_UNICAST], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eFramesTransmittedOK);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_SINGLE_COLLISION], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eSingleCollisionFrames);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_MULTIPLE_COLLISION], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eMultipleCollisionFrames);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_UNICAST], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eFramesReceivedOK);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_BYTES_LOW],\n+\t\t\t\t priv-\u003efields[MT7530_MIB_TX_BYTES_HIGH], port,\n+\t\t\t\t \u0026mac_stats-\u003eOctetsTransmittedOK);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_ALIGN_ERR], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eAlignmentErrors);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_DEFERRED], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eFramesWithDeferredXmissions);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_LATE_COLLISION], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eLateCollisions);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_EXCESSIVE_COLLISION], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eFramesAbortedDueToXSColls);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_BYTES_LOW],\n+\t\t\t\t priv-\u003efields[MT7530_MIB_RX_BYTES_HIGH], port,\n+\t\t\t\t \u0026mac_stats-\u003eOctetsReceivedOK);\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_MULTICAST], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eMulticastFramesXmittedOK);\n+\tmac_stats-\u003eFramesTransmittedOK += mac_stats-\u003eMulticastFramesXmittedOK;\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_BROADCAST], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eBroadcastFramesXmittedOK);\n+\tmac_stats-\u003eFramesTransmittedOK += mac_stats-\u003eBroadcastFramesXmittedOK;\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_MULTICAST], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eMulticastFramesReceivedOK);\n+\tmac_stats-\u003eFramesReceivedOK += mac_stats-\u003eMulticastFramesReceivedOK;\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_BROADCAST], NULL, port,\n+\t\t\t\t \u0026mac_stats-\u003eBroadcastFramesReceivedOK);\n+\tmac_stats-\u003eFramesReceivedOK += mac_stats-\u003eBroadcastFramesReceivedOK;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_get_eth_mac_stats);\n+\n+void mt7530_lib_get_rmon_stats(struct mt7530_lib_priv *priv, int port,\n+\t\t\t struct ethtool_rmon_stats *rmon_stats,\n+\t\t\t const struct ethtool_rmon_hist_range **ranges,\n+\t\t\t const struct mt7530_rmon_hist *ranges_info)\n+{\n+\tint i;\n+\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_UNDER_SIZE_ERR], NULL, port,\n+\t\t\t\t \u0026rmon_stats-\u003eundersize_pkts);\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_OVER_SZ_ERR], NULL, port,\n+\t\t\t\t \u0026rmon_stats-\u003eoversize_pkts);\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_FRAG_ERR], NULL, port,\n+\t\t\t\t \u0026rmon_stats-\u003efragments);\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_JABBER_ERR], NULL, port,\n+\t\t\t\t \u0026rmon_stats-\u003ejabbers);\n+\n+\tfor (i = 0; i \u003c ranges_info-\u003enum_ranges; i++) {\n+\t\tunsigned int field = ranges_info-\u003eranges_fields[i];\n+\t\tunsigned int field_tx = ranges_info-\u003eranges_tx_fields[i];\n+\n+\t\tmt7530_lib_read_port_stats(priv-\u003efields[field], NULL, port,\n+\t\t\t\t\t \u0026rmon_stats-\u003ehist[i]);\n+\t\tmt7530_lib_read_port_stats(priv-\u003efields[field_tx], NULL, port,\n+\t\t\t\t\t \u0026rmon_stats-\u003ehist_tx[i]);\n+\t}\n+\n+\t*ranges = ranges_info-\u003eranges;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_get_rmon_stats);\n+\n+void mt7530_lib_get_eth_ctrl_stats(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t struct ethtool_eth_ctrl_stats *ctrl_stats)\n+{\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_TX_PAUSE], NULL, port,\n+\t\t\t\t \u0026ctrl_stats-\u003eMACControlFramesTransmitted);\n+\tmt7530_lib_read_port_stats(priv-\u003efields[MT7530_MIB_RX_PAUSE], NULL, port,\n+\t\t\t\t \u0026ctrl_stats-\u003eMACControlFramesReceived);\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_get_eth_ctrl_stats);\n+\n+int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,\n+\t\t u32 mat, u32 *rsp)\n+{\n+\tu32 val;\n+\tint ret;\n+\n+\tret = regmap_field_write(priv-\u003efields[MT7530_ATC_MAT], mat);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_field_write(priv-\u003efields[MT7530_ATC_CMD], cmd);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_field_write(priv-\u003efields[MT7530_ATC_BUSY], 1);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_field_read_poll_timeout(priv-\u003efields[MT7530_ATC_BUSY],\n+\t\t\t\t\t val, !val, 20, 20000);\n+\tif (ret \u003c 0) {\n+\t\tdev_err(priv-\u003edev, \"reset timeout\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (priv-\u003efields[MT7530_ATC_INVALID]) {\n+\t\tregmap_field_read(priv-\u003efields[MT7530_ATC_INVALID], \u0026val);\n+\t\tif (cmd == MT7530_FDB_READ \u0026\u0026 val)\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rsp)\n+\t\tregmap_field_read(priv-\u003efields[__MT7530_ATC], rsp);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_fdb_cmd);\n+\n+static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,\n+\t\t\t\t u8 port_mask, const u8 *mac,\n+\t\t\t\t u8 aging, u8 type)\n+{\n+\t/* Clear ATWD registers from previous access */\n+\tregmap_field_write(priv-\u003efields[__MT7530_ATWD1], 0);\n+\tregmap_field_write(priv-\u003efields[__MT7530_ATWD2], 0);\n+\tregmap_field_write(priv-\u003efields[__MT7530_ATWD3], 0);\n+\tif (priv-\u003efields[__MT7530_ATWD4])\n+\t\tregmap_field_write(priv-\u003efields[__MT7530_ATWD4], 0);\n+\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_CVID], vid);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_IVL], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_FID], FID_BRIDGED);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_AGE_TIMER], aging);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_PORT_MAP], port_mask);\n+\t/* STATIC_ENT indicate that entry is static wouldn't\n+\t * be aged out and STATIC_EMP specified as erasing an\n+\t * entry\n+\t */\n+\tif (priv-\u003efields[MT7530_ATWD_ENT_STATUS])\n+\t\tregmap_field_write(priv-\u003efields[MT7530_ATWD_ENT_STATUS], type);\n+\tif (priv-\u003efields[AN8855_ATWD_TYPE]) {\n+\t\t/* Default to static entry (0) */\n+\t\tregmap_field_write(priv-\u003efields[AN8855_ATWD_TYPE], 0);\n+\t}\n+\tif (priv-\u003efields[AN8855_ATWD_VLD]) {\n+\t\t/* Load entry if STATIC_ENT */\n+\t\tregmap_field_write(priv-\u003efields[AN8855_ATWD_VLD],\n+\t\t\t\t type == STATIC_ENT);\n+\t}\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_MAC_BYTE_5], mac[5]);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_MAC_BYTE_4], mac[4]);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_MAC_BYTE_3], mac[3]);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_MAC_BYTE_2], mac[2]);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_MAC_BYTE_1], mac[1]);\n+\tregmap_field_write(priv-\u003efields[MT7530_ATWD_MAC_BYTE_0], mac[0]);\n+}\n+\n+void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb)\n+{\n+\tu32 val = 0;\n+\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_CVID], \u0026val);\n+\tfdb-\u003evid = val;\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_AGE_TIMER], \u0026val);\n+\tfdb-\u003eaging = val;\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_PORT_MAP], \u0026val);\n+\tfdb-\u003eport_mask = val;\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_MAC_BYTE_5], \u0026val);\n+\tfdb-\u003emac[5] = val;\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_MAC_BYTE_4], \u0026val);\n+\tfdb-\u003emac[4] = val;\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_MAC_BYTE_3], \u0026val);\n+\tfdb-\u003emac[3] = val;\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_MAC_BYTE_2], \u0026val);\n+\tfdb-\u003emac[2] = val;\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_MAC_BYTE_1], \u0026val);\n+\tfdb-\u003emac[1] = val;\n+\tregmap_field_read(priv-\u003efields[MT7530_ATRD_MAC_BYTE_0], \u0026val);\n+\tfdb-\u003emac[0] = val;\n+\tif (priv-\u003efields[MT7530_ATWD_ENT_STATUS]) {\n+\t\tregmap_field_read(priv-\u003efields[MT7530_ATRD_ENT_STATUS], \u0026val);\n+\t\tfdb-\u003enoarp = val == STATIC_ENT;\n+\t}\n+\tif (priv-\u003efields[AN8855_ATRD_ARP]) {\n+\t\tregmap_field_read(priv-\u003efields[AN8855_ATRD_ARP], \u0026val);\n+\t\tfdb-\u003enoarp = !!val;\n+\t}\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read);\n+\n+void mt7530_lib_port_fast_age(struct mt7530_lib_priv *priv, int port)\n+{\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\n+\t/* Flush all non-static MAC address entries */\n+\tmt7530_lib_fdb_cmd(priv, MT7530_FDB_FLUSH,\n+\t\t\t ATC_MAT_NON_STATIC_MAC, NULL);\n+\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_fast_age);\n+\n+int mt7530_lib_port_fdb_add(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const unsigned char *addr, u16 vid,\n+\t\t\t struct dsa_db db)\n+{\n+\tu8 port_mask = BIT(port);\n+\tint ret;\n+\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\tmt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);\n+\tret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,\n+\t\t\t\t ATC_MAT_MACTAB, NULL);\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+\n+\treturn ret;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_fdb_add);\n+\n+int mt7530_lib_port_fdb_del(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const unsigned char *addr, u16 vid,\n+\t\t\t struct dsa_db db)\n+{\n+\tu8 port_mask = BIT(port);\n+\tint ret;\n+\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\tmt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);\n+\tret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,\n+\t\t\t\t ATC_MAT_MACTAB, NULL);\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+\n+\treturn ret;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_fdb_del);\n+\n+int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const struct switchdev_obj_port_mdb *mdb,\n+\t\t\t struct dsa_db db)\n+{\n+\tconst u8 *addr = mdb-\u003eaddr;\n+\tu16 vid = mdb-\u003evid;\n+\tu8 port_mask = 0;\n+\tu32 val;\n+\tint ret;\n+\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\n+\tmt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);\n+\tif (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,\n+\t\t\t\tATC_MAT_MACTAB, NULL)) {\n+\t\tregmap_field_read(priv-\u003efields[MT7530_ATRD_PORT_MAP],\n+\t\t\t\t \u0026val);\n+\t\tport_mask = val;\n+\t}\n+\n+\tport_mask |= BIT(port);\n+\tmt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);\n+\tret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,\n+\t\t\t\t ATC_MAT_MACTAB, NULL);\n+\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+\n+\treturn ret;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_mdb_add);\n+\n+int mt7530_lib_port_mdb_del(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const struct switchdev_obj_port_mdb *mdb,\n+\t\t\t struct dsa_db db)\n+{\n+\tconst u8 *addr = mdb-\u003eaddr;\n+\tu16 vid = mdb-\u003evid;\n+\tu8 port_mask = 0;\n+\tu32 val;\n+\tint ret;\n+\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\n+\tmt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);\n+\tif (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,\n+\t\t\t\tATC_MAT_MACTAB, NULL)) {\n+\t\tregmap_field_read(priv-\u003efields[MT7530_ATRD_PORT_MAP],\n+\t\t\t\t \u0026val);\n+\t\tport_mask = val;\n+\t}\n+\n+\tport_mask \u0026= ~BIT(port);\n+\tmt7530_lib_fdb_write(priv, vid, port_mask, addr, -1,\n+\t\t\t port_mask ? STATIC_ENT : STATIC_EMP);\n+\tret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,\n+\t\t\t\t ATC_MAT_MACTAB, NULL);\n+\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+\n+\treturn ret;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_mdb_del);\n+\n+int mt7530_lib_port_mirror_add(struct mt7530_lib_priv *priv, int port,\n+\t\t\t struct dsa_mall_mirror_tc_entry *mirror,\n+\t\t\t bool ingress, struct netlink_ext_ack *extack)\n+{\n+\tu32 monitor_port, val = 0;\n+\tint ret;\n+\n+\t/* Check for existent entry */\n+\tif ((ingress ? priv-\u003emirror_rx : priv-\u003emirror_tx) \u0026 BIT(port))\n+\t\treturn -EEXIST;\n+\n+\tregmap_field_read(priv-\u003efields[MT7530_MIRROR_EN], \u0026val);\n+\tret = regmap_field_read(priv-\u003efields[MT7530_MIRROR_PORT], \u0026monitor_port);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* MT7530 only supports one monitor port */\n+\tif (val \u0026\u0026 monitor_port != mirror-\u003eto_local_port)\n+\t\treturn -EEXIST;\n+\n+\tregmap_field_write(priv-\u003efields[MT7530_MIRROR_PORT],\n+\t\t\t mirror-\u003eto_local_port);\n+\tregmap_field_write(priv-\u003efields[MT7530_MIRROR_EN], 1);\n+\n+\tif (ingress) {\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PCR_PORT_RX_MIR], port, 1);\n+\t\tpriv-\u003emirror_rx |= BIT(port);\n+\t} else {\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PCR_PORT_TX_MIR], port, 1);\n+\t\tpriv-\u003emirror_tx |= BIT(port);\n+\t}\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_mirror_add);\n+\n+void mt7530_lib_port_mirror_del(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\tstruct dsa_mall_mirror_tc_entry *mirror)\n+{\n+\tif (mirror-\u003eingress) {\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PCR_PORT_RX_MIR], port, 0);\n+\t\tpriv-\u003emirror_rx \u0026= ~BIT(port);\n+\t} else {\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PCR_PORT_TX_MIR], port, 0);\n+\t\tpriv-\u003emirror_tx \u0026= ~BIT(port);\n+\t}\n+\n+\tif (!priv-\u003emirror_rx \u0026\u0026 !priv-\u003emirror_tx)\n+\t\tregmap_field_write(priv-\u003efields[MT7530_MIRROR_EN], 0);\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_mirror_del);\n+\n+int mt7530_lib_port_change_mtu(struct mt7530_lib_priv *priv, int port, int new_mtu)\n+{\n+\tint length;\n+\n+\t/* When a new MTU is set, DSA always set the CPU port's MTU to the\n+\t * largest MTU of the user ports. Because the switch only has a global\n+\t * RX length register, only allowing CPU port here is enough.\n+\t */\n+\tif (!dsa_is_cpu_port(priv-\u003eds, port))\n+\t\treturn 0;\n+\n+\t/* RX length also includes Ethernet header, MTK tag, and FCS length */\n+\tlength = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;\n+\tif (length \u003c= 1522) {\n+\t\tregmap_field_write(priv-\u003efields[MT7530_GMACCR_MAX_RX_PKT_LEN],\n+\t\t\t\t MAX_RX_PKT_LEN_1522);\n+\t} else if (length \u003c= 1536) {\n+\t\tregmap_field_write(priv-\u003efields[MT7530_GMACCR_MAX_RX_PKT_LEN],\n+\t\t\t\t MAX_RX_PKT_LEN_1536);\n+\t} else if (length \u003c= 1552) {\n+\t\tregmap_field_write(priv-\u003efields[MT7530_GMACCR_MAX_RX_PKT_LEN],\n+\t\t\t\t MAX_RX_PKT_LEN_1552);\n+\t} else {\n+\t\tregmap_field_write(priv-\u003efields[MT7530_GMACCR_MAX_RX_JUMBO],\n+\t\t\t\t DIV_ROUND_UP(length, 1024));\n+\t\tregmap_field_write(priv-\u003efields[MT7530_GMACCR_MAX_RX_PKT_LEN],\n+\t\t\t\t MAX_RX_PKT_LEN_JUMBO);\n+\t}\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_change_mtu);\n+\n+void mt7530_lib_stp_state_set(struct mt7530_lib_priv *priv, int port, u8 state)\n+{\n+\tu32 stp_state;\n+\n+\tswitch (state) {\n+\tcase BR_STATE_DISABLED:\n+\t\tstp_state = MT7530_STP_DISABLED;\n+\t\tbreak;\n+\tcase BR_STATE_BLOCKING:\n+\t\tstp_state = MT7530_STP_BLOCKING;\n+\t\tbreak;\n+\tcase BR_STATE_LISTENING:\n+\t\tstp_state = MT7530_STP_LISTENING;\n+\t\tbreak;\n+\tcase BR_STATE_LEARNING:\n+\t\tstp_state = MT7530_STP_LEARNING;\n+\t\tbreak;\n+\tcase BR_STATE_FORWARDING:\n+\tdefault:\n+\t\tstp_state = MT7530_STP_FORWARDING;\n+\t\tbreak;\n+\t}\n+\n+\tregmap_fields_update_bits(priv-\u003efields[MT7530_SSP_FID_PST],\n+\t\t\t\t port, FID_PST_MASK(FID_BRIDGED),\n+\t\t\t\t FID_PST(FID_BRIDGED, stp_state));\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_stp_state_set);\n+\n+int mt7530_lib_port_bridge_flags(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t struct switchdev_brport_flags flags,\n+\t\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tstruct dsa_switch *ds = priv-\u003eds;\n+\n+\tif (flags.mask \u0026 BR_LEARNING)\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PSC_SA_DIS],\n+\t\t\t\t port, !(flags.val \u0026 BR_LEARNING));\n+\n+\tif (flags.mask \u0026 BR_FLOOD)\n+\t\tregmap_field_update_bits(priv-\u003efields[MT7530_UNU_FFP],\n+\t\t\t\t\t BIT(port),\n+\t\t\t\t\t flags.val \u0026 BR_FLOOD ? BIT(port) : 0);\n+\n+\tif (flags.mask \u0026 BR_MCAST_FLOOD)\n+\t\tregmap_field_update_bits(priv-\u003efields[MT7530_UNM_FFP],\n+\t\t\t\t\t BIT(port),\n+\t\t\t\t\t flags.val \u0026 BR_MCAST_FLOOD ? BIT(port) : 0);\n+\n+\tif (flags.mask \u0026 BR_BCAST_FLOOD)\n+\t\tregmap_field_update_bits(priv-\u003efields[MT7530_BC_FFP],\n+\t\t\t\t\t BIT(port),\n+\t\t\t\t\t flags.val \u0026 BR_BCAST_FLOOD ? BIT(port) : 0);\n+\n+\tif (flags.mask \u0026 BR_ISOLATED) {\n+\t\tstruct dsa_port *dp = dsa_to_port(ds, port);\n+\t\tstruct net_device *bridge_dev = dsa_port_bridge_dev_get(dp);\n+\n+\t\tpriv-\u003eports[port].isolated = !!(flags.val \u0026 BR_ISOLATED);\n+\n+\t\tmutex_lock(priv-\u003ereg_mutex);\n+\t\tmt7530_update_port_member(priv, port, bridge_dev, true);\n+\t\tmutex_unlock(priv-\u003ereg_mutex);\n+\t}\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_flags);\n+\n+int mt7530_lib_port_bridge_join(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\tstruct dsa_bridge bridge, bool *tx_fwd_offload,\n+\t\t\t\tstruct netlink_ext_ack *extack)\n+{\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\n+\tmt7530_update_port_member(priv, port, bridge.dev, true);\n+\n+\t/* Set to fallback mode for independent VLAN learning */\n+\tregmap_fields_write(priv-\u003efields[MT7530_PCR_PORT_VLAN],\n+\t\t\t port, MT7530_PORT_FALLBACK_MODE);\n+\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_join);\n+\n+void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t struct dsa_bridge bridge)\n+{\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\n+\tmt7530_update_port_member(priv, port, bridge.dev, false);\n+\n+\t/* When a port is removed from the bridge, the port would be set up\n+\t * back to the default as is at initial boot which is a VLAN-unaware\n+\t * port.\n+\t */\n+\tregmap_fields_write(priv-\u003efields[MT7530_PCR_PORT_VLAN],\n+\t\t\t port, MT7530_PORT_MATRIX_MODE);\n+\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_leave);\n+\n+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,\n+\t\t\t u16 pvid)\n+{\n+\tregmap_fields_write(priv-\u003efields[MT7530_PPBV1_G0_PORT_VID],\n+\t\t\t port, pvid);\n+\tif (priv-\u003efields[AN8855_PVID_G0_PORT_VID])\n+\t\tregmap_fields_write(priv-\u003efields[AN8855_PVID_G0_PORT_VID],\n+\t\t\t\t port, pvid);\n+}\n+EXPORT_SYMBOL_GPL(mt7530_port_set_pvid);\n+\n+static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)\n+{\n+\tstruct dsa_switch *ds = priv-\u003eds;\n+\tbool all_user_ports_removed = true;\n+\tint i;\n+\n+\t/* This is called after .port_bridge_leave when leaving a VLAN-aware\n+\t * bridge. Don't set standalone ports to fallback mode.\n+\t */\n+\tif (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PCR_PORT_VLAN],\n+\t\t\t\t port, MT7530_PORT_FALLBACK_MODE);\n+\n+\tregmap_fields_write(priv-\u003efields[MT7530_PVC_VLAN_ATTR],\n+\t\t\t port, MT7530_VLAN_TRANSPARENT);\n+\tregmap_fields_write(priv-\u003efields[MT7530_PVC_EG_TAG],\n+\t\t\t port, MT7530_VLAN_EG_CONSISTENT);\n+\tregmap_fields_write(priv-\u003efields[MT7530_PVC_ACC_FRM],\n+\t\t\t port, MT7530_VLAN_ACC_ALL);\n+\n+\tmt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);\n+\n+\tfor (i = 0; i \u003c priv-\u003eds-\u003enum_ports; i++) {\n+\t\tif (i == port)\n+\t\t\tcontinue;\n+\t\tif (dsa_is_user_port(ds, i) \u0026\u0026\n+\t\t dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {\n+\t\t\tall_user_ports_removed = false;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* CPU port also does the same thing until all user ports belonging to\n+\t * the CPU port get out of VLAN filtering mode.\n+\t */\n+\tif (all_user_ports_removed) {\n+\t\tmutex_lock(priv-\u003ereg_mutex);\n+\t\tmt7530_lib_setup_vlan0(priv);\n+\t\tmutex_unlock(priv-\u003ereg_mutex);\n+\t}\n+}\n+\n+static void mt7530_port_set_vlan_aware(struct mt7530_lib_priv *priv, int port)\n+{\n+\tstruct dsa_switch *ds = priv-\u003eds;\n+\n+\t/* Trapped into security mode allows packet forwarding through VLAN\n+\t * table lookup.\n+\t */\n+\tif (dsa_is_user_port(ds, port)) {\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PCR_PORT_VLAN],\n+\t\t\t\t port, MT7530_PORT_SECURITY_MODE);\n+\t\tmt7530_port_set_pvid(priv, port, priv-\u003eports[port].pvid);\n+\n+\t\t/* Only accept tagged frames if PVID is not set */\n+\t\tif (!priv-\u003eports[port].pvid)\n+\t\t\tregmap_fields_write(priv-\u003efields[MT7530_PVC_ACC_FRM],\n+\t\t\t\t\t port, MT7530_VLAN_ACC_TAGGED);\n+\n+\t\t/* Set the port as a user port which is to be able to recognize\n+\t\t * VID from incoming packets before fetching entry within the\n+\t\t * VLAN table.\n+\t\t */\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PVC_VLAN_ATTR],\n+\t\t\t\t port, MT7530_VLAN_USER);\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PVC_EG_TAG],\n+\t\t\t\t port, MT7530_VLAN_EG_DISABLED);\n+\t} else {\n+\t\t/* Also set CPU ports to the \"user\" VLAN port attribute, to\n+\t\t * allow VLAN classification, but keep the EG_TAG attribute as\n+\t\t * \"consistent\" (i.o.w. don't change its value) for packets\n+\t\t * received by the switch from the CPU, so that tagged packets\n+\t\t * are forwarded to user ports as tagged, and untagged as\n+\t\t * untagged.\n+\t\t */\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PVC_VLAN_ATTR],\n+\t\t\t\t port, MT7530_VLAN_USER);\n+\t}\n+}\n+\n+int mt7530_lib_port_vlan_filtering(struct mt7530_lib_priv *priv, int port, bool vlan_filtering,\n+\t\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tstruct dsa_switch *ds = priv-\u003eds;\n+\tstruct dsa_port *cpu_dp, *dp;\n+\n+\tdp = dsa_to_port(ds, port);\n+\tcpu_dp = dp-\u003ecpu_dp;\n+\n+\tif (vlan_filtering) {\n+\t\t/* The port is being kept as VLAN-unaware port when bridge is\n+\t\t * set up with vlan_filtering not being set, Otherwise, the\n+\t\t * port and the corresponding CPU port is required the setup\n+\t\t * for becoming a VLAN-aware port.\n+\t\t */\n+\t\tmt7530_port_set_vlan_aware(priv, port);\n+\t\tmt7530_port_set_vlan_aware(priv, cpu_dp-\u003eindex);\n+\t} else {\n+\t\tmt7530_port_set_vlan_unaware(priv, port);\n+\t}\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_filtering);\n+\n+static int mt7530_vlan_cmd(struct mt7530_lib_priv *priv, enum mt7530_vlan_cmd cmd,\n+\t\t\t u16 vid)\n+{\n+\tu32 val;\n+\tint ret;\n+\n+\tret = regmap_field_write(priv-\u003efields[MT7530_VTCR_FUNC], cmd);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_field_write(priv-\u003efields[MT7530_VTCR_VID], vid);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_field_write(priv-\u003efields[MT7530_VTCR_BUSY], 1);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_field_read_poll_timeout(priv-\u003efields[MT7530_VTCR_BUSY],\n+\t\t\t\t\t val, !val, 20, 20000);\n+\tif (ret \u003c 0) {\n+\t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (priv-\u003efields[MT7530_VTCR_INVALID]) {\n+\t\tregmap_field_read(priv-\u003efields[MT7530_VTCR_INVALID], \u0026val);\n+\t\tif (val) {\n+\t\t\tdev_err(priv-\u003edev, \"read VTCR invalid\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void mt7530_hw_vlan_add(struct mt7530_lib_priv *priv,\n+\t\t\t struct mt7530_hw_vlan_entry *entry)\n+{\n+\tstruct dsa_port *dp = dsa_to_port(priv-\u003eds, entry-\u003eport);\n+\tu8 new_members;\n+\tu32 val;\n+\n+\tnew_members = entry-\u003eold_members | BIT(entry-\u003eport);\n+\n+\t/* Validate the entry with independent learning, create egress tag per\n+\t * VLAN and joining the port as one of the port members.\n+\t */\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_IVL_MAC], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_VTAG_EN], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_PORT_MEM],\n+\t\t\t new_members);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_FID],\n+\t\t\t FID_BRIDGED);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_VLAN_VALID], 1);\n+\n+\t/* Decide whether adding tag or not for those outgoing packets from the\n+\t * port inside the VLAN.\n+\t * CPU port is always taken as a tagged port for serving more than one\n+\t * VLANs across and also being applied with egress type stack mode for\n+\t * that VLAN tags would be appended after hardware special tag used as\n+\t * DSA tag.\n+\t */\n+\tif (dsa_port_is_cpu(dp))\n+\t\tval = MT7530_VLAN_EGRESS_STACK;\n+\telse if (entry-\u003euntagged)\n+\t\tval = MT7530_VLAN_EGRESS_UNTAG;\n+\telse\n+\t\tval = MT7530_VLAN_EGRESS_TAG;\n+\tregmap_field_update_bits(priv-\u003efields[MT7530_VAWD_ETAG],\n+\t\t\t\t ETAG_CTRL_P_MASK(entry-\u003eport),\n+\t\t\t\t ETAG_CTRL_P(entry-\u003eport, val));\n+}\n+\n+static void mt7530_hw_vlan_del(struct mt7530_lib_priv *priv,\n+\t\t\t struct mt7530_hw_vlan_entry *entry)\n+{\n+\tu8 new_members;\n+\tu32 val;\n+\n+\tnew_members = entry-\u003eold_members \u0026 ~BIT(entry-\u003eport);\n+\n+\tregmap_field_read(priv-\u003efields[MT7530_VAWD_VLAN_VALID], \u0026val);\n+\tif (!val) {\n+\t\tdev_err(priv-\u003edev,\n+\t\t\t\"Cannot be deleted due to invalid entry\\n\");\n+\t\treturn;\n+\t}\n+\n+\tif (new_members) {\n+\t\tregmap_field_write(priv-\u003efields[MT7530_VAWD_IVL_MAC], 1);\n+\t\tregmap_field_write(priv-\u003efields[MT7530_VAWD_VTAG_EN], 1);\n+\t\tregmap_field_write(priv-\u003efields[MT7530_VAWD_PORT_MEM],\n+\t\t\t\t new_members);\n+\t\tregmap_field_write(priv-\u003efields[MT7530_VAWD_VLAN_VALID], 1);\n+\t} else {\n+\t\tregmap_field_write(priv-\u003efields[__MT7530_VAWD1], 0);\n+\t\tregmap_field_write(priv-\u003efields[__MT7530_VAWD2], 0);\n+\t}\n+}\n+\n+static void mt7530_hw_vlan_update(struct mt7530_lib_priv *priv, u16 vid,\n+\t\t\t\t struct mt7530_hw_vlan_entry *entry,\n+\t\t\t\t mt7530_vlan_op vlan_op)\n+{\n+\tu32 val = 0;\n+\n+\t/* Fetch entry */\n+\tmt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);\n+\n+\tregmap_field_read(priv-\u003efields[MT7530_VAWD_PORT_MEM], \u0026val);\n+\tentry-\u003eold_members = val;\n+\n+\t/* Manipulate entry */\n+\tvlan_op(priv, entry);\n+\n+\t/* Flush result to hardware */\n+\tmt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);\n+}\n+\n+int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const struct switchdev_obj_port_vlan *vlan,\n+\t\t\t struct netlink_ext_ack *extack)\n+{\n+\tbool untagged = vlan-\u003eflags \u0026 BRIDGE_VLAN_INFO_UNTAGGED;\n+\tbool pvid = vlan-\u003eflags \u0026 BRIDGE_VLAN_INFO_PVID;\n+\tstruct mt7530_hw_vlan_entry new_entry;\n+\tstruct dsa_switch *ds = priv-\u003eds;\n+\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\n+\t/* VID 0 is managed exclusively by mt7530_lib_setup_vlan0() for\n+\t * VLAN-unaware bridge operation. Don't let the bridge overwrite\n+\t * its EG_CON flag with VTAG_EN and corrupt PORT_MEM.\n+\t */\n+\tif (vlan-\u003evid == 0)\n+\t\tgoto skip_vlan_table;\n+\n+\tmt7530_hw_vlan_entry_init(\u0026new_entry, port, untagged);\n+\tmt7530_hw_vlan_update(priv, vlan-\u003evid, \u0026new_entry, mt7530_hw_vlan_add);\n+\n+skip_vlan_table:\n+\n+\tif (pvid) {\n+\t\tpriv-\u003eports[port].pvid = vlan-\u003evid;\n+\n+\t\t/* Accept all frames if PVID is set */\n+\t\tregmap_fields_write(priv-\u003efields[MT7530_PVC_ACC_FRM],\n+\t\t\t\t port, MT7530_VLAN_ACC_ALL);\n+\n+\t\t/* Only configure PVID if VLAN filtering is enabled */\n+\t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n+\t\t\tmt7530_port_set_pvid(priv, port, vlan-\u003evid);\n+\t} else if (vlan-\u003evid \u0026\u0026 priv-\u003eports[port].pvid == vlan-\u003evid) {\n+\t\t/* This VLAN is overwritten without PVID, so unset it */\n+\t\tpriv-\u003eports[port].pvid = G0_PORT_VID_DEF;\n+\n+\t\t/* Only accept tagged frames if the port is VLAN-aware */\n+\t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n+\t\t\tregmap_fields_write(priv-\u003efields[MT7530_PVC_ACC_FRM],\n+\t\t\t\t\t port, MT7530_VLAN_ACC_TAGGED);\n+\n+\t\tmt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);\n+\t}\n+\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_add);\n+\n+int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const struct switchdev_obj_port_vlan *vlan)\n+{\n+\tstruct mt7530_hw_vlan_entry target_entry;\n+\tstruct dsa_switch *ds = priv-\u003eds;\n+\n+\tmutex_lock(priv-\u003ereg_mutex);\n+\n+\t/* VID 0 is managed exclusively by mt7530_lib_setup_vlan0(). */\n+\tif (vlan-\u003evid == 0)\n+\t\tgoto skip_vlan_table;\n+\n+\tmt7530_hw_vlan_entry_init(\u0026target_entry, port, 0);\n+\tmt7530_hw_vlan_update(priv, vlan-\u003evid, \u0026target_entry,\n+\t\t\t mt7530_hw_vlan_del);\n+\n+skip_vlan_table:\n+\t/* PVID is being restored to the default whenever the PVID port\n+\t * is being removed from the VLAN.\n+\t */\n+\tif (priv-\u003eports[port].pvid == vlan-\u003evid) {\n+\t\tpriv-\u003eports[port].pvid = G0_PORT_VID_DEF;\n+\n+\t\t/* Only accept tagged frames if the port is VLAN-aware */\n+\t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n+\t\t\tregmap_fields_write(priv-\u003efields[MT7530_PVC_ACC_FRM],\n+\t\t\t\t\t port, MT7530_VLAN_ACC_TAGGED);\n+\n+\t\tmt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);\n+\t}\n+\n+\tmutex_unlock(priv-\u003ereg_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_del);\n+\n+int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv)\n+{\n+\t/* Clear VAWD registers from previous access */\n+\tregmap_field_write(priv-\u003efields[__MT7530_VAWD1], 0);\n+\tregmap_field_write(priv-\u003efields[__MT7530_VAWD2], 0);\n+\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_IVL_MAC], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_VTAG_EN], 0);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_EG_CON], 1);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_PORT_MEM],\n+\t\t\t MT7530_ALL_MEMBERS);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_FID],\n+\t\t\t FID_BRIDGED);\n+\tregmap_field_write(priv-\u003efields[MT7530_VAWD_VLAN_VALID], 1);\n+\tregmap_field_write(priv-\u003efields[__MT7530_VAWD2], 0);\n+\n+\treturn mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);\n+}\n+EXPORT_SYMBOL_GPL(mt7530_lib_setup_vlan0);\n+\n+MODULE_AUTHOR(\"Christian Marangi \u003cansuelsmth@gmail.com\u003e\");\n+MODULE_DESCRIPTION(\"Library Driver for Mediatek MT7530 Based Switch\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/net/dsa/mt7530-lib.h b/drivers/net/dsa/mt7530-lib.h\nnew file mode 100644\nindex 0000000000000..1465eb49f4cb2\n--- /dev/null\n+++ b/drivers/net/dsa/mt7530-lib.h\n@@ -0,0 +1,413 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+#ifndef __MT7530_LIB_H\n+#define __MT7530_LIB_H\n+\n+#define G0_PORT_VID_DEF\t\t\t0\n+#define MT7530_ALL_MEMBERS\t\t0xff\n+\n+#define MTK_HDR_LEN\t4\n+#define MT7530_MAX_MTU\t(15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)\n+\n+/* MT7530_ATA1 */\n+#define STATIC_EMP\t\t\t0\n+#define STATIC_ENT\t\t\t3\n+\n+#define ATC_MAT_MACTAB\t\t\t0\n+#define ATC_MAT_NON_STATIC_MAC\t\t4\n+\n+enum mt7530_fdb_cmd {\n+\tMT7530_FDB_READ\t= 0,\n+\tMT7530_FDB_WRITE = 1,\n+\tMT7530_FDB_FLUSH = 2,\n+\tMT7530_FDB_START = 4,\n+\tMT7530_FDB_NEXT = 5,\n+};\n+\n+enum mt7530_max_rx_pkt_len {\n+\tMAX_RX_PKT_LEN_1522 = 0,\n+\tMAX_RX_PKT_LEN_1536 = 1,\n+\tMAX_RX_PKT_LEN_1552 = 2,\n+\tMAX_RX_PKT_LEN_JUMBO = 3,\n+};\n+\n+#define FID_PST(fid, state)\t\t(((state) \u0026 0x3) \u003c\u003c ((fid) * 2))\n+#define FID_PST_MASK(fid)\t\tFID_PST(fid, 0x3)\n+\n+enum mt7530_stp_state {\n+\tMT7530_STP_DISABLED = 0,\n+\tMT7530_STP_BLOCKING = 1,\n+\tMT7530_STP_LISTENING = 1,\n+\tMT7530_STP_LEARNING = 2,\n+\tMT7530_STP_FORWARDING = 3\n+};\n+\n+/* Egress Tag Control */\n+#define ETAG_CTRL_P(p, x)\t\t(((x) \u0026 0x3) \u003c\u003c ((p) \u003c\u003c 1))\n+#define ETAG_CTRL_P_MASK(p)\t\tETAG_CTRL_P(p, 3)\n+\n+enum mt753x_to_cpu_fw {\n+\tTO_CPU_FW_SYSTEM_DEFAULT,\n+\tTO_CPU_FW_CPU_EXCLUDE = 4,\n+\tTO_CPU_FW_CPU_INCLUDE = 5,\n+\tTO_CPU_FW_CPU_ONLY = 6,\n+\tTO_CPU_FW_DROP = 7,\n+};\n+\n+enum mt7530_port_mode {\n+\t/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */\n+\tMT7530_PORT_MATRIX_MODE = 0,\n+\n+\t/* Fallback Mode: Forward received frames with ingress ports that do\n+\t * not belong to the VLAN member. Frames whose VID is not listed on\n+\t * the VLAN table are forwarded by the PCR_MATRIX members.\n+\t */\n+\tMT7530_PORT_FALLBACK_MODE = 1,\n+\n+\t/* Security Mode: Discard any frame due to ingress membership\n+\t * violation or VID missed on the VLAN table.\n+\t */\n+\tMT7530_PORT_SECURITY_MODE = 3,\n+};\n+\n+enum mt7530_vlan_port_acc_frm {\n+\tMT7530_VLAN_ACC_ALL = 0,\n+\tMT7530_VLAN_ACC_TAGGED = 1,\n+\tMT7530_VLAN_ACC_UNTAGGED = 2,\n+};\n+\n+enum mt7530_vlan_port_eg_tag {\n+\tMT7530_VLAN_EG_DISABLED = 0,\n+\tMT7530_VLAN_EG_CONSISTENT = 1,\n+\tMT7530_VLAN_EG_UNTAGGED = 4,\n+};\n+\n+enum mt7530_vlan_port_attr {\n+\tMT7530_VLAN_USER = 0,\n+\tMT7530_VLAN_TRANSPARENT = 3,\n+};\n+\n+enum mt7530_fid {\n+\tFID_STANDALONE = 0,\n+\tFID_BRIDGED = 1,\n+};\n+\n+enum mt7530_vlan_egress_attr {\n+\tMT7530_VLAN_EGRESS_UNTAG = 0,\n+\tMT7530_VLAN_EGRESS_TAG = 2,\n+\tMT7530_VLAN_EGRESS_STACK = 3,\n+};\n+\n+enum mt7530_vlan_cmd {\n+\t/* Read/Write the specified VID entry from VAWD register based\n+\t * on VID.\n+\t */\n+\tMT7530_VTCR_RD_VID = 0,\n+\tMT7530_VTCR_WR_VID = 1,\n+};\n+\n+enum mt7530_regmap_field {\n+\tMT7530_MIRROR_EN,\n+\tMT7530_MIRROR_PORT,\n+\n+\tMT7530_UNU_FFP,\n+\tMT7530_UNM_FFP,\n+\tMT7530_BC_FFP,\n+\n+\tMT7530_CCR_MIB_ENABLE,\n+\tMT7530_CCR_RX_OCT_CNT_GOOD,\n+\tMT7530_CCR_RX_OCT_CNT_BAD,\n+\tMT7530_CCR_TX_OCT_CNT_GOOD,\n+\tMT7530_CCR_TX_OCT_CNT_BAD,\n+\n+\tMT7530_BPDU_EG_TAG,\n+\tMT7530_BPDU_PORT_FW,\n+\tMT7530_PAE_BPDU_FR,\n+\tMT7530_PAE_EG_TAG,\n+\tMT7530_PAE_PORT_FW,\n+\tMT7530_R01_BPDU_FR,\n+\tMT7530_R01_EG_TAG,\n+\tMT7530_R01_PORT_FW,\n+\tMT7530_R02_BPDU_FR,\n+\tMT7530_R02_EG_TAG,\n+\tMT7530_R02_PORT_FW,\n+\tMT7530_R03_BPDU_FR,\n+\tMT7530_R03_EG_TAG,\n+\tMT7530_R03_PORT_FW,\n+\tMT7530_R0E_BPDU_FR,\n+\tMT7530_R0E_EG_TAG,\n+\tMT7530_R0E_PORT_FW,\n+\n+\tMT7530_VAWD_IVL_MAC,\n+\tMT7530_VAWD_EG_CON,\n+\tMT7530_VAWD_VTAG_EN,\n+\tMT7530_VAWD_PORT_MEM,\n+\tMT7530_VAWD_FID,\n+\tMT7530_VAWD_VLAN_VALID,\n+\t__MT7530_VAWD1,\n+\n+\tMT7530_VAWD_ETAG,\n+\t__MT7530_VAWD2,\n+\n+\tMT7530_VTCR_BUSY,\n+\tMT7530_VTCR_FUNC,\n+\tMT7530_VTCR_VID,\n+\tMT7530_VTCR_INVALID,\n+\n+\tMT7530_ATWD_CVID,\n+\tMT7530_ATWD_IVL,\n+\tMT7530_ATWD_FID,\n+\tMT7530_ATWD_AGE_TIMER,\n+\tMT7530_ATWD_PORT_MAP,\n+\tMT7530_ATWD_ENT_STATUS,\n+\tAN8855_ATWD_TYPE,\n+\tAN8855_ATWD_VLD,\n+\tMT7530_ATWD_MAC_BYTE_5,\n+\tMT7530_ATWD_MAC_BYTE_4,\n+\tMT7530_ATWD_MAC_BYTE_3,\n+\tMT7530_ATWD_MAC_BYTE_2,\n+\tMT7530_ATWD_MAC_BYTE_1,\n+\tMT7530_ATWD_MAC_BYTE_0,\n+\n+\t__MT7530_ATWD1,\n+\t__MT7530_ATWD2,\n+\t__MT7530_ATWD3,\n+\t__MT7530_ATWD4,\n+\n+\tMT7530_ATRD_CVID,\n+\tMT7530_ATRD_AGE_TIMER,\n+\tMT7530_ATRD_PORT_MAP,\n+\tMT7530_ATRD_ENT_STATUS,\n+\tAN8855_ATRD_ARP,\n+\tMT7530_ATRD_MAC_BYTE_5,\n+\tMT7530_ATRD_MAC_BYTE_4,\n+\tMT7530_ATRD_MAC_BYTE_3,\n+\tMT7530_ATRD_MAC_BYTE_2,\n+\tMT7530_ATRD_MAC_BYTE_1,\n+\tMT7530_ATRD_MAC_BYTE_0,\n+\n+\tMT7530_ATC_BUSY,\n+\tMT7530_ATC_MAT,\n+\tMT7530_ATC_INVALID,\n+\tMT7530_ATC_CMD,\n+\t__MT7530_ATC,\n+\n+\tMT7530_SSP_FID_PST,\n+\n+\tMT7530_PCR_PORT_TX_MIR,\n+\tMT7530_PCR_PORT_RX_MIR,\n+\tMT7530_PCR_PORT_VLAN,\n+\tMT7530_PCR_MATRIX,\n+\n+\tMT7530_PSC_SA_DIS,\n+\n+\tMT7530_PVC_EG_TAG,\n+\tMT7530_PVC_VLAN_ATTR,\n+\tMT7530_PVC_ACC_FRM,\n+\n+\tMT7530_PPBV1_G0_PORT_VID,\n+\tAN8855_PVID_G0_PORT_VID,\n+\n+\tMT7530_GMACCR_MAX_RX_JUMBO,\n+\tMT7530_GMACCR_MAX_RX_PKT_LEN,\n+\n+\tMT7530_MIB_TX_DROP,\n+\tMT7530_MIB_TX_CRC_ERR,\n+\tMT7530_MIB_TX_UNICAST,\n+\tMT7530_MIB_TX_MULTICAST,\n+\tMT7530_MIB_TX_BROADCAST,\n+\tMT7530_MIB_TX_COLLISION,\n+\tMT7530_MIB_TX_SINGLE_COLLISION,\n+\tMT7530_MIB_TX_MULTIPLE_COLLISION,\n+\tMT7530_MIB_TX_DEFERRED,\n+\tMT7530_MIB_TX_LATE_COLLISION,\n+\tMT7530_MIB_TX_EXCESSIVE_COLLISION,\n+\tMT7530_MIB_TX_PAUSE,\n+\tMT7530_MIB_TX_PKT_SZ_64,\n+\tMT7530_MIB_TX_PKT_SZ_65_TO_127,\n+\tMT7530_MIB_TX_PKT_SZ_128_TO_255,\n+\tMT7530_MIB_TX_PKT_SZ_256_TO_511,\n+\tMT7530_MIB_TX_PKT_SZ_512_TO_1023,\n+\tMT7530_MIB_TX_PKT_SZ_1024_TO_MAX,\n+\tAN8855_MIB_TX_PKT_SZ_1024_TO_1518,\n+\tAN8855_MIB_TX_PKT_SZ_1519_TO_MAX,\n+\tMT7530_MIB_TX_BYTES_LOW,\n+\tMT7530_MIB_TX_BYTES_HIGH,\n+\tAN8855_MIB_TX_OVERSIZE_DROP,\n+\tAN8855_MIB_TX_BAD_PKT_BYTES_LOW,\n+\tAN8855_MIB_TX_BAD_PKT_BYTES_HIGH,\n+\tMT7530_MIB_RX_DROP,\n+\tMT7530_MIB_RX_FILTERING,\n+\tMT7530_MIB_RX_UNICAST,\n+\tMT7530_MIB_RX_MULTICAST,\n+\tMT7530_MIB_RX_BROADCAST,\n+\tMT7530_MIB_RX_ALIGN_ERR,\n+\tMT7530_MIB_RX_CRC_ERR,\n+\tMT7530_MIB_RX_UNDER_SIZE_ERR,\n+\tMT7530_MIB_RX_FRAG_ERR,\n+\tMT7530_MIB_RX_OVER_SZ_ERR,\n+\tMT7530_MIB_RX_JABBER_ERR,\n+\tMT7530_MIB_RX_PAUSE,\n+\tMT7530_MIB_RX_PKT_SZ_64,\n+\tMT7530_MIB_RX_PKT_SZ_65_TO_127,\n+\tMT7530_MIB_RX_PKT_SZ_128_TO_255,\n+\tMT7530_MIB_RX_PKT_SZ_256_TO_511,\n+\tMT7530_MIB_RX_PKT_SZ_512_TO_1023,\n+\tMT7530_MIB_RX_PKT_SZ_1024_TO_MAX,\n+\tAN8855_MIB_RX_PKT_SZ_1024_TO_1518,\n+\tAN8855_MIB_RX_PKT_SZ_1519_TO_MAX,\n+\tMT7530_MIB_RX_BYTES_LOW,\n+\tMT7530_MIB_RX_BYTES_HIGH,\n+\tMT7530_MIB_RX_CTRL_DROP,\n+\tMT7530_MIB_RX_INGRESS_DROP,\n+\tMT7530_MIB_RX_ARL_DROP,\n+\tAN8855_MIB_FLOW_CONTROL_DROP,\n+\tAN8855_MIB_WRED_DROP,\n+\tAN8855_MIB_MIRROR_DROP,\n+\tAN8855_MIB_RX_BAD_PKT_BYTES_LOW,\n+\tAN8855_MIB_RX_BAD_PKT_BYTES_HIGH,\n+\tAN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP,\n+\tAN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP,\n+\tAN8855_MIB_PORT_CONTROL_DROP,\n+\n+\tMT7530_FIELD_MAX,\n+};\n+\n+struct mt7530_fdb {\n+\tu16 vid;\n+\tu8 port_mask;\n+\tu8 aging;\n+\tu8 mac[6];\n+\tbool noarp;\n+};\n+\n+struct mt7530_hw_vlan_entry {\n+\tint port;\n+\tu8 old_members;\n+\tbool untagged;\n+};\n+\n+static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,\n+\t\t\t\t\t int port, bool untagged)\n+{\n+\te-\u003eport = port;\n+\te-\u003euntagged = untagged;\n+}\n+\n+#define MIB_DESC(_fl, _fh, _n)\t\\\n+\t{\t\t\t\\\n+\t\t.field_low = (_fl),\t\\\n+\t\t.field_high = (_fh),\t\\\n+\t\t.name = (_n),\t\\\n+\t}\n+\n+struct mt7530_mib_desc {\n+\tint field_low;\n+\tint field_high;\n+\tconst char *name;\n+};\n+\n+struct mt7530_rmon_hist {\n+\tunsigned int *ranges_fields;\n+\tunsigned int *ranges_tx_fields;\n+\tconst struct ethtool_rmon_hist_range *ranges;\n+\tunsigned int num_ranges;\n+};\n+\n+struct mt7530_reg_field {\n+\tunsigned int id;\n+\tconst struct reg_field field;\n+};\n+\n+/* struct mt7530_port -\tThis is the main data structure for holding the state\n+ *\t\t\tof the port.\n+ * @enable:\tThe status used for show port is enabled or not.\n+ * @pm:\t\tThe matrix used to show all connections with the port.\n+ * @pvid:\tThe VLAN specified is to be considered a PVID at ingress. Any\n+ *\t\tuntagged frames will be assigned to the related VLAN.\n+ * @sgmii_pcs:\tPointer to PCS instance for SerDes ports\n+ * @stats:\tCached port statistics for MDIO-connected switches\n+ */\n+struct mt7530_port {\n+\tbool enable;\n+\tbool isolated;\n+\tu32 pm;\n+\tu16 pvid;\n+\tstruct phylink_pcs *sgmii_pcs;\n+\tstruct rtnl_link_stats64 stats;\n+};\n+\n+struct mt7530_lib_priv {\n+\tstruct device *dev;\n+\tstruct dsa_switch *ds;\n+\tstruct regmap *regmap;\n+\tstruct regmap_field *fields[MT7530_FIELD_MAX];\n+\n+\tu8 mirror_rx;\n+\tu8 mirror_tx;\n+\n+\tstruct mt7530_port *ports;\n+\tstruct mutex *reg_mutex;\n+};\n+\n+typedef void (*mt7530_vlan_op)(struct mt7530_lib_priv *,\n+\t\t\t struct mt7530_hw_vlan_entry *);\n+\n+void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv);\n+void mt7530_lib_trap_frames(struct mt7530_lib_priv *priv);\n+\n+void mt7530_lib_read_port_stats(struct regmap_field *low,\n+\t\t\t\tstruct regmap_field *high,\n+\t\t\t\tint port, uint64_t *data);\n+void mt7530_lib_get_eth_mac_stats(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t struct ethtool_eth_mac_stats *mac_stats);\n+void mt7530_lib_get_rmon_stats(struct mt7530_lib_priv *priv, int port,\n+\t\t\t struct ethtool_rmon_stats *rmon_stats,\n+\t\t\t const struct ethtool_rmon_hist_range **ranges,\n+\t\t\t const struct mt7530_rmon_hist *ranges_info);\n+void mt7530_lib_get_eth_ctrl_stats(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t struct ethtool_eth_ctrl_stats *ctrl_stats);\n+int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,\n+\t\t u32 mat, u32 *rsp);\n+void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb);\n+void mt7530_lib_port_fast_age(struct mt7530_lib_priv *priv, int port);\n+int mt7530_lib_port_fdb_add(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const unsigned char *addr, u16 vid,\n+\t\t\t struct dsa_db db);\n+int mt7530_lib_port_fdb_del(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const unsigned char *addr, u16 vid,\n+\t\t\t struct dsa_db db);\n+int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const struct switchdev_obj_port_mdb *mdb,\n+\t\t\t struct dsa_db db);\n+int mt7530_lib_port_mdb_del(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const struct switchdev_obj_port_mdb *mdb,\n+\t\t\t struct dsa_db db);\n+void mt7530_lib_port_mirror_del(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\tstruct dsa_mall_mirror_tc_entry *mirror);\n+int mt7530_lib_port_mirror_add(struct mt7530_lib_priv *priv, int port,\n+\t\t\t struct dsa_mall_mirror_tc_entry *mirror,\n+\t\t\t bool ingress, struct netlink_ext_ack *extack);\n+int mt7530_lib_port_change_mtu(struct mt7530_lib_priv *priv, int port, int new_mtu);\n+void mt7530_lib_stp_state_set(struct mt7530_lib_priv *priv, int port, u8 state);\n+int mt7530_lib_port_bridge_flags(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t struct switchdev_brport_flags flags,\n+\t\t\t\t struct netlink_ext_ack *extack);\n+int mt7530_lib_port_bridge_join(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\tstruct dsa_bridge bridge, bool *tx_fwd_offload,\n+\t\t\t\tstruct netlink_ext_ack *extack);\n+void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,\n+\t\t\t\t struct dsa_bridge bridge);\n+int mt7530_lib_port_vlan_filtering(struct mt7530_lib_priv *priv, int port, bool vlan_filtering,\n+\t\t\t\t struct netlink_ext_ack *extack);\n+int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const struct switchdev_obj_port_vlan *vlan,\n+\t\t\t struct netlink_ext_ack *extack);\n+int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,\n+\t\t\t const struct switchdev_obj_port_vlan *vlan);\n+\n+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,\n+\t\t\t u16 pvid);\n+int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv);\n+\n+#endif /* __MT7530_LIB_H */\n+\ndiff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c\nindex 24ef54f3db2a6..38fde73e56459 100644\n--- a/drivers/net/dsa/mt7530-mdio.c\n+++ b/drivers/net/dsa/mt7530-mdio.c\n@@ -218,6 +218,10 @@ mt7530_probe(struct mdio_device *mdiodev)\n \tif (IS_ERR(priv-\u003eregmap))\n \t\treturn PTR_ERR(priv-\u003eregmap);\n \n+\tret = mt7530_setup_lib_priv(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tif (priv-\u003eid == ID_MT7531)\n \t\tpriv-\u003ecreate_sgmii = mt7531_create_sgmii;\n \ndiff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mt7530-mmio.c\nindex cf3bdb23a2d54..2dcb2bb545b9b 100644\n--- a/drivers/net/dsa/mt7530-mmio.c\n+++ b/drivers/net/dsa/mt7530-mmio.c\n@@ -61,6 +61,10 @@ mt7988_probe(struct platform_device *pdev)\n \tif (IS_ERR(priv-\u003eregmap))\n \t\treturn PTR_ERR(priv-\u003eregmap);\n \n+\tret = mt7530_setup_lib_priv(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \treturn dsa_register_switch(priv-\u003eds);\n }\n \ndiff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c\nindex 14692497e1a61..5470f049c6d88 100644\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -24,10 +24,163 @@\n #include \u003cnet/pkt_cls.h\u003e\n \n #include \"mt7530.h\"\n+#include \"mt7530-lib.h\"\n \n #define MT7530_STATS_POLL_INTERVAL\t(1 * HZ)\n #define MT7530_STATS_RATE_LIMIT\t\t(HZ / 10)\n \n+static const struct mt7530_reg_field mt753x_fields[] = {\n+\t{ MT7530_BC_FFP, REG_FIELD(MT753X_MFC, 24, 31) },\n+\t{ MT7530_UNM_FFP, REG_FIELD(MT753X_MFC, 16, 23) },\n+\t{ MT7530_UNU_FFP, REG_FIELD(MT753X_MFC, 8, 15) },\n+\n+\t{ MT7530_CCR_MIB_ENABLE, REG_FIELD(MT7530_MIB_CCR, 31, 31) },\n+\t{ MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(MT7530_MIB_CCR, 7, 7) },\n+\t{ MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(MT7530_MIB_CCR, 6, 6) },\n+\t{ MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(MT7530_MIB_CCR, 5, 5) },\n+\t{ MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(MT7530_MIB_CCR, 4, 4) },\n+\n+\t{ MT7530_BPDU_EG_TAG, REG_FIELD(MT753X_BPC, 6, 8) },\n+\t{ MT7530_BPDU_PORT_FW, REG_FIELD(MT753X_BPC, 0, 2) },\n+\t{ MT7530_PAE_BPDU_FR, REG_FIELD(MT753X_BPC, 25, 25) },\n+\t{ MT7530_PAE_EG_TAG, REG_FIELD(MT753X_BPC, 22, 24) },\n+\t{ MT7530_PAE_PORT_FW, REG_FIELD(MT753X_BPC, 16, 18) },\n+\t{ MT7530_R01_BPDU_FR, REG_FIELD(MT753X_RGAC1, 9, 9) },\n+\t{ MT7530_R01_EG_TAG, REG_FIELD(MT753X_RGAC1, 6, 8) },\n+\t{ MT7530_R01_PORT_FW, REG_FIELD(MT753X_RGAC1, 0, 2) },\n+\t{ MT7530_R02_BPDU_FR, REG_FIELD(MT753X_RGAC1, 25, 25) },\n+\t{ MT7530_R02_EG_TAG, REG_FIELD(MT753X_RGAC1, 22, 24) },\n+\t{ MT7530_R02_PORT_FW, REG_FIELD(MT753X_RGAC1, 16, 18) },\n+\t{ MT7530_R03_BPDU_FR, REG_FIELD(MT753X_RGAC2, 9, 9) },\n+\t{ MT7530_R03_EG_TAG, REG_FIELD(MT753X_RGAC2, 6, 8) },\n+\t{ MT7530_R03_PORT_FW, REG_FIELD(MT753X_RGAC2, 0, 2) },\n+\t{ MT7530_R0E_BPDU_FR, REG_FIELD(MT753X_RGAC2, 25, 25) },\n+\t{ MT7530_R0E_EG_TAG, REG_FIELD(MT753X_RGAC2, 22, 24) },\n+\t{ MT7530_R0E_PORT_FW, REG_FIELD(MT753X_RGAC2, 16, 18) },\n+\n+\t{ MT7530_VAWD_IVL_MAC, REG_FIELD(MT7530_VAWD1, 30, 30) },\n+\t{ MT7530_VAWD_EG_CON, REG_FIELD(MT7530_VAWD1, 29, 29) },\n+\t{ MT7530_VAWD_VTAG_EN, REG_FIELD(MT7530_VAWD1, 28, 28) },\n+\t{ MT7530_VAWD_PORT_MEM, REG_FIELD(MT7530_VAWD1, 16, 23) },\n+\t{ MT7530_VAWD_FID, REG_FIELD(MT7530_VAWD1, 1, 3) },\n+\t{ MT7530_VAWD_VLAN_VALID, REG_FIELD(MT7530_VAWD1, 0, 0) },\n+\t{ __MT7530_VAWD1, REG_FIELD(MT7530_VAWD1, 0, 31) },\n+\n+\t{ MT7530_VAWD_ETAG, REG_FIELD(MT7530_VAWD2, 0, 15) },\n+\t{ __MT7530_VAWD2, REG_FIELD(MT7530_VAWD2, 0, 31) },\n+\n+\t{ MT7530_VTCR_BUSY, REG_FIELD(MT7530_VTCR, 31, 31) },\n+\t{ MT7530_VTCR_INVALID, REG_FIELD(MT7530_VTCR, 16, 16) },\n+\t{ MT7530_VTCR_FUNC, REG_FIELD(MT7530_VTCR, 12, 15) },\n+\t{ MT7530_VTCR_VID, REG_FIELD(MT7530_VTCR, 0, 11) },\n+\n+\t{ MT7530_ATWD_CVID, REG_FIELD(MT7530_ATA2, 0, 11), },\n+\t{ MT7530_ATWD_IVL, REG_FIELD(MT7530_ATA2, 15, 15), },\n+\t{ MT7530_ATWD_FID, REG_FIELD(MT7530_ATA2, 12, 14), },\n+\t{ MT7530_ATWD_AGE_TIMER, REG_FIELD(MT7530_ATWD, 24, 31), },\n+\t{ MT7530_ATWD_PORT_MAP, REG_FIELD(MT7530_ATWD, 4, 11), },\n+\t{ MT7530_ATWD_ENT_STATUS, REG_FIELD(MT7530_ATWD, 2, 3), },\n+\t{ MT7530_ATWD_MAC_BYTE_5, REG_FIELD(MT7530_ATA2, 16, 23), },\n+\t{ MT7530_ATWD_MAC_BYTE_4, REG_FIELD(MT7530_ATA2, 24, 31), },\n+\t{ MT7530_ATWD_MAC_BYTE_3, REG_FIELD(MT7530_ATA1, 0, 7), },\n+\t{ MT7530_ATWD_MAC_BYTE_2, REG_FIELD(MT7530_ATA1, 8, 15), },\n+\t{ MT7530_ATWD_MAC_BYTE_1, REG_FIELD(MT7530_ATA1, 16, 23), },\n+\t{ MT7530_ATWD_MAC_BYTE_0, REG_FIELD(MT7530_ATA1, 24, 31), },\n+\n+\t{ __MT7530_ATWD1, REG_FIELD(MT7530_ATWD, 0, 31), },\n+\t{ __MT7530_ATWD2, REG_FIELD(MT7530_ATA1, 0, 31), },\n+\t{ __MT7530_ATWD3, REG_FIELD(MT7530_ATA2, 0, 31), },\n+\n+\t{ MT7530_ATRD_CVID, REG_FIELD(MT7530_TSRA2, 0, 11), },\n+\t{ MT7530_ATRD_AGE_TIMER, REG_FIELD(MT7530_ATRD, 24, 31), },\n+\t{ MT7530_ATRD_PORT_MAP, REG_FIELD(MT7530_ATRD, 4, 11), },\n+\t{ MT7530_ATRD_ENT_STATUS, REG_FIELD(MT7530_ATRD, 2, 3), },\n+\t{ MT7530_ATRD_MAC_BYTE_5, REG_FIELD(MT7530_TSRA2, 16, 23), },\n+\t{ MT7530_ATRD_MAC_BYTE_4, REG_FIELD(MT7530_TSRA2, 24, 31), },\n+\t{ MT7530_ATRD_MAC_BYTE_3, REG_FIELD(MT7530_TSRA1, 0, 7), },\n+\t{ MT7530_ATRD_MAC_BYTE_2, REG_FIELD(MT7530_TSRA1, 8, 15), },\n+\t{ MT7530_ATRD_MAC_BYTE_1, REG_FIELD(MT7530_TSRA1, 16, 23), },\n+\t{ MT7530_ATRD_MAC_BYTE_0, REG_FIELD(MT7530_TSRA1, 24, 31), },\n+\n+\t{ MT7530_ATC_BUSY, REG_FIELD(MT7530_ATC, 15, 15), },\n+\t{ MT7530_ATC_INVALID, REG_FIELD(MT7530_ATC, 12, 12), },\n+\t{ MT7530_ATC_MAT, REG_FIELD(MT7530_ATC, 8, 11), },\n+\t{ MT7530_ATC_CMD, REG_FIELD(MT7530_ATC, 0, 2), },\n+\t{ __MT7530_ATC, REG_FIELD(MT7530_ATC, 0, 31), },\n+\n+\t{ MT7530_SSP_FID_PST, REG_FIELD_ID(MT7530_SSP, 0, 15, MT7530_NUM_PORTS, 0x100) },\n+\n+\t{ MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(MT7530_PCR, 9, 9, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(MT7530_PCR, 8, 8, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_PCR_PORT_VLAN, REG_FIELD_ID(MT7530_PCR, 0, 1, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_PCR_MATRIX, REG_FIELD_ID(MT7530_PCR, 16, 23, MT7530_NUM_PORTS, 0x100) },\n+\n+\t{ MT7530_PSC_SA_DIS, REG_FIELD_ID(MT7530_PSC, 4, 4, MT7530_NUM_PORTS, 0x100) },\n+\n+\t{ MT7530_PVC_EG_TAG, REG_FIELD_ID(MT7530_PVC, 8, 10, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(MT7530_PVC, 6, 7, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_PVC_ACC_FRM, REG_FIELD_ID(MT7530_PVC, 0, 1, MT7530_NUM_PORTS, 0x100) },\n+\n+\t{ MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(MT7530_PPBV1, 0, 11, MT7530_NUM_PORTS, 0x100) },\n+\n+\t{ MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(MT7530_GMACCR, 2, 5) },\n+\t{ MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(MT7530_GMACCR, 0, 1) },\n+\n+\t{ MT7530_MIB_TX_DROP, REG_FIELD_ID(MT7530_PORT_MIB_TX_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(MT7530_PORT_MIB_TX_CRC_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_UNICAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_UNICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_MULTICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_BROADCAST, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_SINGLE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(MT7530_PORT_MIB_TX_DEFERRED, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_LATE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_PAUSE, REG_FIELD_ID(MT7530_PORT_MIB_TX_PAUSE, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_64, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_PKT_SZ_1024_TO_MAX, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(MT7530_PORT_MIB_TX_BYTES_LOW, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(MT7530_PORT_MIB_TX_BYTES_HIGH, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_FILTERING, REG_FIELD_ID(MT7530_PORT_MIB_RX_FILTERING, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_UNICAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_UNICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_MULTICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_BROADCAST, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_ALIGN_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_CRC_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_FRAG_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_OVER_SZ_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_JABBER_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_PAUSE, REG_FIELD_ID(MT7530_PORT_MIB_RX_PAUSE, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_64, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_PKT_SZ_1024_TO_MAX, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(MT7530_PORT_MIB_RX_BYTES_LOW, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(MT7530_PORT_MIB_RX_BYTES_HIGH, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_CTRL_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_INGRESS_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+\t{ MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_ARL_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },\n+};\n+\n+static const struct mt7530_reg_field mt7530_fields[] = {\n+\t{ MT7530_MIRROR_EN, REG_FIELD(MT753X_MFC, 3, 3) },\n+\t{ MT7530_MIRROR_PORT, REG_FIELD(MT753X_MFC, 0, 2) },\n+};\n+\n+static const struct mt7530_reg_field mt7531_fields[] = {\n+\t{ MT7530_MIRROR_EN, REG_FIELD(MT7531_CFC, 19, 19) },\n+\t{ MT7530_MIRROR_PORT, REG_FIELD(MT7531_CFC, 16, 18) },\n+};\n+\n static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)\n {\n \treturn container_of(pcs, struct mt753x_pcs, pcs);\n@@ -35,15 +188,15 @@ static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)\n \n /* String, offset, and register size in bytes if different from 4 bytes */\n static const struct mt7530_mib_desc mt7530_mib[] = {\n-\tMIB_DESC(1, MT7530_PORT_MIB_TX_DROP, \"TxDrop\"),\n-\tMIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, \"TxCrcErr\"),\n-\tMIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, \"TxCollision\"),\n-\tMIB_DESC(1, MT7530_PORT_MIB_RX_DROP, \"RxDrop\"),\n-\tMIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, \"RxFiltering\"),\n-\tMIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, \"RxCrcErr\"),\n-\tMIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, \"RxCtrlDrop\"),\n-\tMIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, \"RxIngressDrop\"),\n-\tMIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, \"RxArlDrop\"),\n+\tMIB_DESC(MT7530_MIB_TX_DROP, -1, \"TxDrop\"),\n+\tMIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, \"TxCrcErr\"),\n+\tMIB_DESC(MT7530_MIB_TX_COLLISION, -1, \"TxCollision\"),\n+\tMIB_DESC(MT7530_MIB_RX_DROP, -1, \"RxDrop\"),\n+\tMIB_DESC(MT7530_MIB_RX_FILTERING, -1, \"RxFiltering\"),\n+\tMIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, \"RxCrcErr\"),\n+\tMIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, \"RxCtrlDrop\"),\n+\tMIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, \"RxIngressDrop\"),\n+\tMIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, \"RxArlDrop\"),\n };\n \n static void\n@@ -154,115 +307,11 @@ core_clear(struct mt7530_priv *priv, u32 reg, u32 val)\n \tcore_rmw(priv, reg, val, 0);\n }\n \n-static int\n-mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)\n-{\n-\tu32 val;\n-\tint ret;\n-\n-\t/* Set the command operating upon the MAC address entries */\n-\tval = ATC_BUSY | ATC_MAT(0) | cmd;\n-\tret = regmap_write(priv-\u003eregmap, MT7530_ATC, val);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = regmap_read_poll_timeout(priv-\u003eregmap, MT7530_ATC, val,\n-\t\t\t\t !(val \u0026 ATC_BUSY), 20, 20000);\n-\tif (!ret)\n-\t\tret = regmap_read(priv-\u003eregmap, MT7530_ATC, \u0026val);\n-\n-\tif (ret \u003c 0) {\n-\t\tdev_err(priv-\u003edev, \"reset timeout\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\t/* Additional sanity for read command if the specified\n-\t * entry is invalid\n-\t */\n-\tif ((cmd == MT7530_FDB_READ) \u0026\u0026 (val \u0026 ATC_INVALID))\n-\t\treturn -EINVAL;\n-\n-\tif (rsp)\n-\t\t*rsp = val;\n-\n-\treturn 0;\n-}\n-\n static void mt7530_port_fast_age(struct dsa_switch *ds, int port)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tu32 val;\n-\tint ret;\n-\n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\n-\t/* Flush all non-static MAC address entries */\n-\tval = ATC_BUSY | ATC_MAT_NON_STATIC_MAC | MT7530_FDB_FLUSH;\n-\tret = regmap_write(priv-\u003eregmap, MT7530_ATC, val);\n-\tif (!ret)\n-\t\tret = regmap_read_poll_timeout(priv-\u003eregmap, MT7530_ATC, val,\n-\t\t\t\t\t !(val \u0026 ATC_BUSY), 20, 20000);\n-\tif (ret \u003c 0)\n-\t\tdev_err(priv-\u003edev, \"fast age failed: %d\\n\", ret);\n-\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-}\n-\n-static void\n-mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)\n-{\n-\tu32 reg[3];\n-\tint i;\n-\n-\t/* Read from ARL table into an array */\n-\tfor (i = 0; i \u003c 3; i++) {\n-\t\tregmap_read(priv-\u003eregmap, MT7530_TSRA1 + (i * 4),\n-\t\t\t \u0026reg[i]);\n-\n-\t\tdev_dbg(priv-\u003edev, \"%s(%d) reg[%d]=0x%x\\n\",\n-\t\t\t__func__, __LINE__, i, reg[i]);\n-\t}\n \n-\tfdb-\u003evid = FIELD_GET(CVID_MASK, reg[1]);\n-\tfdb-\u003eaging = FIELD_GET(AGE_TIMER_MASK, reg[2]);\n-\tfdb-\u003eport_mask = FIELD_GET(PORT_MAP_MASK, reg[2]);\n-\tfdb-\u003emac[0] = FIELD_GET(MAC_BYTE_0_MASK, reg[0]);\n-\tfdb-\u003emac[1] = FIELD_GET(MAC_BYTE_1_MASK, reg[0]);\n-\tfdb-\u003emac[2] = FIELD_GET(MAC_BYTE_2_MASK, reg[0]);\n-\tfdb-\u003emac[3] = FIELD_GET(MAC_BYTE_3_MASK, reg[0]);\n-\tfdb-\u003emac[4] = FIELD_GET(MAC_BYTE_4_MASK, reg[1]);\n-\tfdb-\u003emac[5] = FIELD_GET(MAC_BYTE_5_MASK, reg[1]);\n-\tfdb-\u003enoarp = FIELD_GET(ENT_STATUS_MASK, reg[2]) == STATIC_ENT;\n-}\n-\n-static void\n-mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,\n-\t\t u8 port_mask, const u8 *mac,\n-\t\t u8 aging, u8 type)\n-{\n-\tu32 reg[3] = { 0 };\n-\tint i;\n-\n-\treg[1] |= FIELD_PREP(CVID_MASK, vid);\n-\treg[1] |= ATA2_IVL;\n-\treg[1] |= ATA2_FID(FID_BRIDGED);\n-\treg[2] |= FIELD_PREP(AGE_TIMER_MASK, aging);\n-\treg[2] |= FIELD_PREP(PORT_MAP_MASK, port_mask);\n-\t/* STATIC_ENT indicate that entry is static wouldn't\n-\t * be aged out and STATIC_EMP specified as erasing an\n-\t * entry\n-\t */\n-\treg[2] |= FIELD_PREP(ENT_STATUS_MASK, type);\n-\treg[1] |= FIELD_PREP(MAC_BYTE_5_MASK, mac[5]);\n-\treg[1] |= FIELD_PREP(MAC_BYTE_4_MASK, mac[4]);\n-\treg[0] |= FIELD_PREP(MAC_BYTE_3_MASK, mac[3]);\n-\treg[0] |= FIELD_PREP(MAC_BYTE_2_MASK, mac[2]);\n-\treg[0] |= FIELD_PREP(MAC_BYTE_1_MASK, mac[1]);\n-\treg[0] |= FIELD_PREP(MAC_BYTE_0_MASK, mac[0]);\n-\n-\t/* Write array into the ARL table */\n-\tfor (i = 0; i \u003c 3; i++)\n-\t\tregmap_write(priv-\u003eregmap, MT7530_ATA1 + (i * 4), reg[i]);\n+\tmt7530_lib_port_fast_age(\u0026priv-\u003elib_priv, port);\n }\n \n /* Set up switch core clock for MT7530 */\n@@ -449,15 +498,6 @@ mt7531_pll_setup(struct mt7530_priv *priv)\n \tusleep_range(25, 35);\n }\n \n-static void\n-mt7530_mib_reset(struct dsa_switch *ds)\n-{\n-\tstruct mt7530_priv *priv = ds-\u003epriv;\n-\n-\tregmap_write(priv-\u003eregmap, MT7530_MIB_CCR, CCR_MIB_FLUSH);\n-\tregmap_write(priv-\u003eregmap, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);\n-}\n-\n static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)\n {\n \treturn mdiobus_read_nested(priv-\u003ebus, port, regnum);\n@@ -702,34 +742,25 @@ mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,\n \t\tethtool_puts(\u0026data, mt7530_mib[i].name);\n }\n \n-static void\n-mt7530_read_port_stats(struct mt7530_priv *priv, int port,\n-\t\t u32 offset, u8 size, uint64_t *data)\n-{\n-\tu32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset;\n-\n-\tregmap_read(priv-\u003eregmap, reg, \u0026val);\n-\t*data = val;\n-\n-\tif (size == 2) {\n-\t\tregmap_read(priv-\u003eregmap, reg + 4, \u0026val);\n-\t\t*data |= (u64)val \u003c\u003c 32;\n-\t}\n-}\n-\n static void\n mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,\n \t\t\t uint64_t *data)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \tconst struct mt7530_mib_desc *mib;\n+\tstruct mt7530_lib_priv *lib_priv;\n \tint i;\n \n+\tlib_priv = \u0026priv-\u003elib_priv;\n \tfor (i = 0; i \u003c ARRAY_SIZE(mt7530_mib); i++) {\n+\t\tstruct regmap_field *high = NULL;\n \t\tmib = \u0026mt7530_mib[i];\n \n-\t\tmt7530_read_port_stats(priv, port, mib-\u003eoffset, mib-\u003esize,\n-\t\t\t\t data + i);\n+\t\tif (mib-\u003efield_high != -1)\n+\t\t\thigh = lib_priv-\u003efields[mib-\u003efield_high];\n+\n+\t\tmt7530_lib_read_port_stats(lib_priv-\u003efields[mib-\u003efield_low],\n+\t\t\t\t\t high, port, data + i);\n \t}\n }\n \n@@ -747,54 +778,7 @@ static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port,\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\t/* MIB counter doesn't provide a FramesTransmittedOK but instead\n-\t * provide stats for Unicast, Broadcast and Multicast frames separately.\n-\t * To simulate a global frame counter, read Unicast and addition Multicast\n-\t * and Broadcast later\n-\t */\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,\n-\t\t\t \u0026mac_stats-\u003eFramesTransmittedOK);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1,\n-\t\t\t \u0026mac_stats-\u003eSingleCollisionFrames);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1,\n-\t\t\t \u0026mac_stats-\u003eMultipleCollisionFrames);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,\n-\t\t\t \u0026mac_stats-\u003eFramesReceivedOK);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,\n-\t\t\t \u0026mac_stats-\u003eOctetsTransmittedOK);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1,\n-\t\t\t \u0026mac_stats-\u003eAlignmentErrors);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1,\n-\t\t\t \u0026mac_stats-\u003eFramesWithDeferredXmissions);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1,\n-\t\t\t \u0026mac_stats-\u003eLateCollisions);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1,\n-\t\t\t \u0026mac_stats-\u003eFramesAbortedDueToXSColls);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,\n-\t\t\t \u0026mac_stats-\u003eOctetsReceivedOK);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,\n-\t\t\t \u0026mac_stats-\u003eMulticastFramesXmittedOK);\n-\tmac_stats-\u003eFramesTransmittedOK += mac_stats-\u003eMulticastFramesXmittedOK;\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,\n-\t\t\t \u0026mac_stats-\u003eBroadcastFramesXmittedOK);\n-\tmac_stats-\u003eFramesTransmittedOK += mac_stats-\u003eBroadcastFramesXmittedOK;\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,\n-\t\t\t \u0026mac_stats-\u003eMulticastFramesReceivedOK);\n-\tmac_stats-\u003eFramesReceivedOK += mac_stats-\u003eMulticastFramesReceivedOK;\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,\n-\t\t\t \u0026mac_stats-\u003eBroadcastFramesReceivedOK);\n-\tmac_stats-\u003eFramesReceivedOK += mac_stats-\u003eBroadcastFramesReceivedOK;\n+\treturn mt7530_lib_get_eth_mac_stats(\u0026priv-\u003elib_priv, port, mac_stats);\n }\n \n static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = {\n@@ -807,53 +791,41 @@ static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = {\n \t{}\n };\n \n+static const struct mt7530_rmon_hist mt7530_rmon_hist_info = {\n+\t.ranges_fields = (unsigned int []){\n+\t\tMT7530_MIB_RX_PKT_SZ_64,\n+\t\tMT7530_MIB_RX_PKT_SZ_65_TO_127,\n+\t\tMT7530_MIB_RX_PKT_SZ_128_TO_255,\n+\t\tMT7530_MIB_RX_PKT_SZ_256_TO_511,\n+\t\tMT7530_MIB_RX_PKT_SZ_512_TO_1023,\n+\t\tMT7530_MIB_RX_PKT_SZ_1024_TO_MAX,\n+\t},\n+\t.ranges_tx_fields = (unsigned int []){\n+\t\tMT7530_MIB_TX_PKT_SZ_64,\n+\t\tMT7530_MIB_TX_PKT_SZ_65_TO_127,\n+\t\tMT7530_MIB_TX_PKT_SZ_128_TO_255,\n+\t\tMT7530_MIB_TX_PKT_SZ_256_TO_511,\n+\t\tMT7530_MIB_TX_PKT_SZ_512_TO_1023,\n+\t\tMT7530_MIB_TX_PKT_SZ_1024_TO_MAX,\n+\t},\n+\t.ranges = mt7530_rmon_ranges,\n+\t.num_ranges = ARRAY_SIZE(mt7530_rmon_ranges) - 1,\n+};\n+\n static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port,\n \t\t\t\t struct ethtool_rmon_stats *rmon_stats,\n \t\t\t\t const struct ethtool_rmon_hist_range **ranges)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1,\n-\t\t\t \u0026rmon_stats-\u003eundersize_pkts);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1,\n-\t\t\t \u0026rmon_stats-\u003eoversize_pkts);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1,\n-\t\t\t \u0026rmon_stats-\u003efragments);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1,\n-\t\t\t \u0026rmon_stats-\u003ejabbers);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist[0]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist[1]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist[2]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist[3]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist[4]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist[5]);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist_tx[0]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist_tx[1]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist_tx[2]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist_tx[3]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist_tx[4]);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1,\n-\t\t\t \u0026rmon_stats-\u003ehist_tx[5]);\n-\n-\t*ranges = mt7530_rmon_ranges;\n+\treturn mt7530_lib_get_rmon_stats(\u0026priv-\u003elib_priv, port, rmon_stats, ranges,\n+\t\t\t\t\t \u0026mt7530_rmon_hist_info);\n }\n \n static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port,\n \t\t\t\t struct rtnl_link_stats64 *storage)\n {\n+\tstruct mt7530_lib_priv *lib_priv = \u0026priv-\u003elib_priv;\n \tuint64_t data;\n \n \t/* MIB counter doesn't provide a FramesTransmittedOK but instead\n@@ -861,38 +833,40 @@ static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port,\n \t * To simulate a global frame counter, read Unicast and addition Multicast\n \t * and Broadcast later\n \t */\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,\n-\t\t\t \u0026storage-\u003erx_packets);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,\n-\t\t\t \u0026storage-\u003emulticast);\n-\tstorage-\u003erx_packets += storage-\u003emulticast;\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,\n-\t\t\t \u0026data);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_RX_UNICAST],\n+\t\t\t\t NULL, port, \u0026storage-\u003erx_packets);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_RX_MULTICAST],\n+\t\t\t\t NULL, port, \u0026data);\n+\tstorage-\u003erx_packets += data;\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_RX_BROADCAST],\n+\t\t\t\t NULL, port, \u0026data);\n \tstorage-\u003erx_packets += data;\n \n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,\n-\t\t\t \u0026storage-\u003etx_packets);\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,\n-\t\t\t \u0026data);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_TX_UNICAST],\n+\t\t\t\t NULL, port, \u0026storage-\u003etx_packets);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_TX_MULTICAST],\n+\t\t\t\t NULL, port, \u0026data);\n \tstorage-\u003etx_packets += data;\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,\n-\t\t\t \u0026data);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_TX_BROADCAST],\n+\t\t\t\t NULL, port, \u0026data);\n \tstorage-\u003etx_packets += data;\n \n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,\n-\t\t\t \u0026storage-\u003erx_bytes);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_RX_BYTES_LOW],\n+\t\t\t\t lib_priv-\u003efields[MT7530_MIB_RX_BYTES_HIGH], port,\n+\t\t\t\t \u0026storage-\u003erx_bytes);\n \n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,\n-\t\t\t \u0026storage-\u003etx_bytes);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_TX_BYTES_LOW],\n+\t\t\t\t lib_priv-\u003efields[MT7530_MIB_TX_BYTES_HIGH], port,\n+\t\t\t\t \u0026storage-\u003etx_bytes);\n \n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1,\n-\t\t\t \u0026storage-\u003erx_dropped);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_RX_DROP],\n+\t\t\t\t NULL, port, \u0026storage-\u003erx_dropped);\n \n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1,\n-\t\t\t \u0026storage-\u003etx_dropped);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_TX_DROP],\n+\t\t\t\t NULL, port, \u0026storage-\u003etx_dropped);\n \n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1,\n-\t\t\t \u0026storage-\u003erx_crc_errors);\n+\tmt7530_lib_read_port_stats(lib_priv-\u003efields[MT7530_MIB_RX_CRC_ERR],\n+\t\t\t\t NULL, port, \u0026storage-\u003erx_crc_errors);\n }\n \n static void mt7530_stats_refresh(struct mt7530_priv *priv)\n@@ -948,11 +922,7 @@ static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port,\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1,\n-\t\t\t \u0026ctrl_stats-\u003eMACControlFramesTransmitted);\n-\n-\tmt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1,\n-\t\t\t \u0026ctrl_stats-\u003eMACControlFramesReceived);\n+\tmt7530_lib_get_eth_ctrl_stats(\u0026priv-\u003elib_priv, port, ctrl_stats);\n }\n \n static int\n@@ -1073,214 +1043,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)\n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n }\n \n-/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)\n- * of the Open Systems Interconnection basic reference model (OSI/RM) are\n- * described; the medium access control (MAC) and logical link control (LLC)\n- * sublayers. The MAC sublayer is the one facing the physical layer.\n- *\n- * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A\n- * Bridge component comprises a MAC Relay Entity for interconnecting the Ports\n- * of the Bridge, at least two Ports, and higher layer entities with at least a\n- * Spanning Tree Protocol Entity included.\n- *\n- * Each Bridge Port also functions as an end station and shall provide the MAC\n- * Service to an LLC Entity. Each instance of the MAC Service is provided to a\n- * distinct LLC Entity that supports protocol identification, multiplexing, and\n- * demultiplexing, for protocol data unit (PDU) transmission and reception by\n- * one or more higher layer entities.\n- *\n- * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC\n- * Entity associated with each Bridge Port is modeled as being directly\n- * connected to the attached Local Area Network (LAN).\n- *\n- * On the switch with CPU port architecture, CPU port functions as Management\n- * Port, and the Management Port functionality is provided by software which\n- * functions as an end station. Software is connected to an IEEE 802 LAN that is\n- * wholly contained within the system that incorporates the Bridge. Software\n- * provides access to the LLC Entity associated with each Bridge Port by the\n- * value of the source port field on the special tag on the frame received by\n- * software.\n- *\n- * We call frames that carry control information to determine the active\n- * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,\n- * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration\n- * Protocol Data Units (MVRPDUs), and frames from other link constrained\n- * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and\n- * Link Layer Discovery Protocol (LLDP), link-local frames. They are not\n- * forwarded by a Bridge. Permanently configured entries in the filtering\n- * database (FDB) ensure that such frames are discarded by the Forwarding\n- * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:\n- *\n- * Each of the reserved MAC addresses specified in Table 8-1\n- * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be\n- * permanently configured in the FDB in C-VLAN components and ERs.\n- *\n- * Each of the reserved MAC addresses specified in Table 8-2\n- * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently\n- * configured in the FDB in S-VLAN components.\n- *\n- * Each of the reserved MAC addresses specified in Table 8-3\n- * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in\n- * TPMR components.\n- *\n- * The FDB entries for reserved MAC addresses shall specify filtering for all\n- * Bridge Ports and all VIDs. Management shall not provide the capability to\n- * modify or remove entries for reserved MAC addresses.\n- *\n- * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of\n- * propagation of PDUs within a Bridged Network, as follows:\n- *\n- * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no\n- * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)\n- * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.\n- * PDUs transmitted using this destination address, or any other addresses\n- * that appear in Table 8-1, Table 8-2, and Table 8-3\n- * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can\n- * therefore travel no further than those stations that can be reached via a\n- * single individual LAN from the originating station.\n- *\n- * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an\n- * address that no conformant S-VLAN component, C-VLAN component, or MAC\n- * Bridge can forward; however, this address is relayed by a TPMR component.\n- * PDUs using this destination address, or any of the other addresses that\n- * appear in both Table 8-1 and Table 8-2 but not in Table 8-3\n- * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by\n- * any TPMRs but will propagate no further than the nearest S-VLAN component,\n- * C-VLAN component, or MAC Bridge.\n- *\n- * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address\n- * that no conformant C-VLAN component, MAC Bridge can forward; however, it is\n- * relayed by TPMR components and S-VLAN components. PDUs using this\n- * destination address, or any of the other addresses that appear in Table 8-1\n- * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),\n- * will be relayed by TPMR components and S-VLAN components but will propagate\n- * no further than the nearest C-VLAN component or MAC Bridge.\n- *\n- * Because the LLC Entity associated with each Bridge Port is provided via CPU\n- * port, we must not filter these frames but forward them to CPU port.\n- *\n- * In a Bridge, the transmission Port is majorly decided by ingress and egress\n- * rules, FDB, and spanning tree Port State functions of the Forwarding Process.\n- * For link-local frames, only CPU port should be designated as destination port\n- * in the FDB, and the other functions of the Forwarding Process must not\n- * interfere with the decision of the transmission Port. We call this process\n- * trapping frames to CPU port.\n- *\n- * Therefore, on the switch with CPU port architecture, link-local frames must\n- * be trapped to CPU port, and certain link-local frames received by a Port of a\n- * Bridge comprising a TPMR component or an S-VLAN component must be excluded\n- * from it.\n- *\n- * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port\n- * MAC Relay (TPMR) component as a TPMR component supports only a subset of the\n- * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port\n- * doesn't count) of this architecture will either function as a standard MAC\n- * Bridge or a standard VLAN Bridge.\n- *\n- * Therefore, a Bridge of this architecture can only comprise S-VLAN components,\n- * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,\n- * we don't need to relay PDUs using the destination addresses specified on the\n- * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge\n- * section where they must be relayed by TPMR components.\n- *\n- * One option to trap link-local frames to CPU port is to add static FDB entries\n- * with CPU port designated as destination port. However, because that\n- * Independent VLAN Learning (IVL) is being used on every VID, each entry only\n- * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC\n- * Bridge component or a C-VLAN component, there would have to be 16 times 4096\n- * entries. This switch intellectual property can only hold a maximum of 2048\n- * entries. Using this option, there also isn't a mechanism to prevent\n- * link-local frames from being discarded when the spanning tree Port State of\n- * the reception Port is discarding.\n- *\n- * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4\n- * registers. Whilst this applies to every VID, it doesn't contain all of the\n- * reserved MAC addresses without affecting the remaining Standard Group MAC\n- * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the\n- * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination\n- * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF\n- * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.\n- * The latter option provides better but not complete conformance.\n- *\n- * This switch intellectual property also does not provide a mechanism to trap\n- * link-local frames with specific destination addresses to CPU port by Bridge,\n- * to conform to the filtering rules for the distinct Bridge components.\n- *\n- * Therefore, regardless of the type of the Bridge component, link-local frames\n- * with these destination addresses will be trapped to CPU port:\n- *\n- * 01-80-C2-00-00-[00,01,02,03,0E]\n- *\n- * In a Bridge comprising a MAC Bridge component or a C-VLAN component:\n- *\n- * Link-local frames with these destination addresses won't be trapped to CPU\n- * port which won't conform to IEEE Std 802.1Q-2022:\n- *\n- * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]\n- *\n- * In a Bridge comprising an S-VLAN component:\n- *\n- * Link-local frames with these destination addresses will be trapped to CPU\n- * port which won't conform to IEEE Std 802.1Q-2022:\n- *\n- * 01-80-C2-00-00-00\n- *\n- * Link-local frames with these destination addresses won't be trapped to CPU\n- * port which won't conform to IEEE Std 802.1Q-2022:\n- *\n- * 01-80-C2-00-00-[04,05,06,07,08,09,0A]\n- *\n- * To trap link-local frames to CPU port as conformant as this switch\n- * intellectual property can allow, link-local frames are made to be regarded as\n- * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual\n- * property only lets the frames regarded as BPDUs bypass the spanning tree Port\n- * State function of the Forwarding Process.\n- *\n- * The only remaining interference is the ingress rules. When the reception Port\n- * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.\n- * There doesn't seem to be a mechanism on the switch intellectual property to\n- * have link-local frames bypass this function of the Forwarding Process.\n- */\n-static void\n-mt753x_trap_frames(struct mt7530_priv *priv)\n-{\n-\t/* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress\n-\t * them with the EG_TAG attribute set to disabled (system default)\n-\t * so that any VLAN tags in the frame are not modified by the\n-\t * switch egress VLAN tag processing. This preserves VLAN tags\n-\t * for reception on VLAN sub-interfaces.\n-\t */\n-\tregmap_update_bits(priv-\u003eregmap, MT753X_BPC,\n-\t\t\t PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |\n-\t\t\t\t BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,\n-\t\t\t PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t\t PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |\n-\t\t\t\t BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t\t TO_CPU_FW_CPU_ONLY);\n-\n-\t/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and\n-\t * egress them with EG_TAG disabled.\n-\t */\n-\tregmap_update_bits(priv-\u003eregmap, MT753X_RGAC1,\n-\t\t\t R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |\n-\t\t\t\t R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,\n-\t\t\t R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t\t R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |\n-\t\t\t\t R01_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t\t TO_CPU_FW_CPU_ONLY);\n-\n-\t/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and\n-\t * egress them with EG_TAG disabled.\n-\t */\n-\tregmap_update_bits(priv-\u003eregmap, MT753X_RGAC2,\n-\t\t\t R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |\n-\t\t\t\t R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,\n-\t\t\t R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t\t R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |\n-\t\t\t\t R03_EG_TAG(MT7530_VLAN_EG_DISABLED) |\n-\t\t\t\t TO_CPU_FW_CPU_ONLY);\n-}\n-\n static void\n mt753x_cpu_port_enable(struct dsa_switch *ds, int port)\n {\n@@ -1329,11 +1091,11 @@ mt7530_port_enable(struct dsa_switch *ds, int port,\n \tif (dsa_port_is_user(dp)) {\n \t\tstruct dsa_port *cpu_dp = dp-\u003ecpu_dp;\n \n-\t\tpriv-\u003eports[port].pm |= PCR_MATRIX(BIT(cpu_dp-\u003eindex));\n+\t\tpriv-\u003eports[port].pm |= BIT(cpu_dp-\u003eindex);\n \t}\n \tpriv-\u003eports[port].enable = true;\n \tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port), PCR_MATRIX_MASK,\n-\t\t\t priv-\u003eports[port].pm);\n+\t\t\t PCR_MATRIX(priv-\u003eports[port].pm));\n \n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n@@ -1378,36 +1140,8 @@ static int\n mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tint length;\n-\tu32 val;\n-\n-\t/* When a new MTU is set, DSA always set the CPU port's MTU to the\n-\t * largest MTU of the user ports. Because the switch only has a global\n-\t * RX length register, only allowing CPU port here is enough.\n-\t */\n-\tif (!dsa_is_cpu_port(ds, port))\n-\t\treturn 0;\n-\n-\tregmap_read(priv-\u003eregmap, MT7530_GMACCR, \u0026val);\n-\tval \u0026= ~MAX_RX_PKT_LEN_MASK;\n-\n-\t/* RX length also includes Ethernet header, MTK tag, and FCS length */\n-\tlength = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;\n-\tif (length \u003c= 1522) {\n-\t\tval |= MAX_RX_PKT_LEN_1522;\n-\t} else if (length \u003c= 1536) {\n-\t\tval |= MAX_RX_PKT_LEN_1536;\n-\t} else if (length \u003c= 1552) {\n-\t\tval |= MAX_RX_PKT_LEN_1552;\n-\t} else {\n-\t\tval \u0026= ~MAX_RX_JUMBO_MASK;\n-\t\tval |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));\n-\t\tval |= MAX_RX_PKT_LEN_JUMBO;\n-\t}\n-\n-\tregmap_write(priv-\u003eregmap, MT7530_GMACCR, val);\n \n-\treturn 0;\n+\treturn mt7530_lib_port_change_mtu(\u0026priv-\u003elib_priv, port, new_mtu);\n }\n \n static int\n@@ -1420,81 +1154,8 @@ static void\n mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tu32 stp_state;\n \n-\tswitch (state) {\n-\tcase BR_STATE_DISABLED:\n-\t\tstp_state = MT7530_STP_DISABLED;\n-\t\tbreak;\n-\tcase BR_STATE_BLOCKING:\n-\t\tstp_state = MT7530_STP_BLOCKING;\n-\t\tbreak;\n-\tcase BR_STATE_LISTENING:\n-\t\tstp_state = MT7530_STP_LISTENING;\n-\t\tbreak;\n-\tcase BR_STATE_LEARNING:\n-\t\tstp_state = MT7530_STP_LEARNING;\n-\t\tbreak;\n-\tcase BR_STATE_FORWARDING:\n-\tdefault:\n-\t\tstp_state = MT7530_STP_FORWARDING;\n-\t\tbreak;\n-\t}\n-\n-\tregmap_update_bits(priv-\u003eregmap, MT7530_SSP_P(port),\n-\t\t\t FID_PST_MASK(FID_BRIDGED),\n-\t\t\t FID_PST(FID_BRIDGED, stp_state));\n-}\n-\n-static void mt7530_update_port_member(struct mt7530_priv *priv, int port,\n-\t\t\t\t const struct net_device *bridge_dev,\n-\t\t\t\t bool join) __must_hold(\u0026priv-\u003ereg_mutex)\n-{\n-\tstruct dsa_port *dp = dsa_to_port(priv-\u003eds, port), *other_dp;\n-\tstruct mt7530_port *p = \u0026priv-\u003eports[port], *other_p;\n-\tstruct dsa_port *cpu_dp = dp-\u003ecpu_dp;\n-\tu32 port_bitmap = BIT(cpu_dp-\u003eindex);\n-\tint other_port;\n-\tbool isolated;\n-\n-\tdsa_switch_for_each_user_port(other_dp, priv-\u003eds) {\n-\t\tother_port = other_dp-\u003eindex;\n-\t\tother_p = \u0026priv-\u003eports[other_port];\n-\n-\t\tif (dp == other_dp)\n-\t\t\tcontinue;\n-\n-\t\t/* Add/remove this port to/from the port matrix of the other\n-\t\t * ports in the same bridge. If the port is disabled, port\n-\t\t * matrix is kept and not being setup until the port becomes\n-\t\t * enabled.\n-\t\t */\n-\t\tif (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev))\n-\t\t\tcontinue;\n-\n-\t\tisolated = p-\u003eisolated \u0026\u0026 other_p-\u003eisolated;\n-\n-\t\tif (join \u0026\u0026 !isolated) {\n-\t\t\tother_p-\u003epm |= PCR_MATRIX(BIT(port));\n-\t\t\tport_bitmap |= BIT(other_port);\n-\t\t} else {\n-\t\t\tother_p-\u003epm \u0026= ~PCR_MATRIX(BIT(port));\n-\t\t}\n-\n-\t\tif (other_p-\u003eenable)\n-\t\t\tregmap_update_bits(priv-\u003eregmap,\n-\t\t\t\t\t MT7530_PCR_P(other_port),\n-\t\t\t\t\t PCR_MATRIX_MASK, other_p-\u003epm);\n-\t}\n-\n-\t/* Add/remove the all other ports to this port matrix. For !join\n-\t * (leaving the bridge), only the CPU port will remain in the port matrix\n-\t * of this port.\n-\t */\n-\tp-\u003epm = PCR_MATRIX(port_bitmap);\n-\tif (priv-\u003eports[port].enable)\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n-\t\t\t\t PCR_MATRIX_MASK, p-\u003epm);\n+\tmt7530_lib_stp_state_set(\u0026priv-\u003elib_priv, port, state);\n }\n \n static int\n@@ -1516,37 +1177,8 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int port,\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\tif (flags.mask \u0026 BR_LEARNING)\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PSC_P(port), SA_DIS,\n-\t\t\t\t flags.val \u0026 BR_LEARNING ? 0 : SA_DIS);\n-\n-\tif (flags.mask \u0026 BR_FLOOD)\n-\t\tregmap_update_bits(priv-\u003eregmap, MT753X_MFC,\n-\t\t\t\t UNU_FFP(BIT(port)),\n-\t\t\t\t flags.val \u0026 BR_FLOOD ? UNU_FFP(BIT(port)) : 0);\n-\n-\tif (flags.mask \u0026 BR_MCAST_FLOOD)\n-\t\tregmap_update_bits(priv-\u003eregmap, MT753X_MFC,\n-\t\t\t\t UNM_FFP(BIT(port)),\n-\t\t\t\t flags.val \u0026 BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);\n-\n-\tif (flags.mask \u0026 BR_BCAST_FLOOD)\n-\t\tregmap_update_bits(priv-\u003eregmap, MT753X_MFC,\n-\t\t\t\t BC_FFP(BIT(port)),\n-\t\t\t\t flags.val \u0026 BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);\n-\n-\tif (flags.mask \u0026 BR_ISOLATED) {\n-\t\tstruct dsa_port *dp = dsa_to_port(ds, port);\n-\t\tstruct net_device *bridge_dev = dsa_port_bridge_dev_get(dp);\n-\n-\t\tpriv-\u003eports[port].isolated = !!(flags.val \u0026 BR_ISOLATED);\n-\n-\t\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\t\tmt7530_update_port_member(priv, port, bridge_dev, true);\n-\t\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\t}\n-\n-\treturn 0;\n+\treturn mt7530_lib_port_bridge_flags(\u0026priv-\u003elib_priv, port, flags,\n+\t\t\t\t\t extack);\n }\n \n static int\n@@ -1556,151 +1188,8 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int port,\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\n-\tmt7530_update_port_member(priv, port, bridge.dev, true);\n-\n-\t/* Set to fallback mode for independent VLAN learning */\n-\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n-\t\t\t PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE);\n-\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\n-\treturn 0;\n-}\n-\n-static int\n-mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)\n-{\n-\tu32 val;\n-\tint ret;\n-\n-\tval = VTCR_BUSY | VTCR_FUNC(cmd) | VTCR_VID(vid);\n-\tret = regmap_write(priv-\u003eregmap, MT7530_VTCR, val);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = regmap_read_poll_timeout(priv-\u003eregmap, MT7530_VTCR, val,\n-\t\t\t\t !(val \u0026 VTCR_BUSY), 20, 20000);\n-\tif (!ret)\n-\t\tret = regmap_read(priv-\u003eregmap, MT7530_VTCR, \u0026val);\n-\n-\tif (ret \u003c 0) {\n-\t\tdev_err(priv-\u003edev, \"poll timeout\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\tif (val \u0026 VTCR_INVALID) {\n-\t\tdev_err(priv-\u003edev, \"read VTCR invalid\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-mt7530_setup_vlan0(struct mt7530_priv *priv)\n-{\n-\tu32 val;\n-\n-\t/* Validate the entry with independent learning, keep the original\n-\t * ingress tag attribute.\n-\t */\n-\tval = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |\n-\t VLAN_VALID;\n-\tregmap_write(priv-\u003eregmap, MT7530_VAWD1, val);\n-\tregmap_write(priv-\u003eregmap, MT7530_VAWD2, 0);\n-\n-\treturn mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);\n-}\n-\n-static void\n-mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)\n-{\n-\tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tbool all_user_ports_removed = true;\n-\tint i;\n-\n-\t/* This is called after .port_bridge_leave when leaving a VLAN-aware\n-\t * bridge. Don't set standalone ports to fallback mode.\n-\t */\n-\tif (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n-\t\t\t\t PCR_PORT_VLAN_MASK,\n-\t\t\t\t MT7530_PORT_FALLBACK_MODE);\n-\n-\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n-\t\t\t VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,\n-\t\t\t VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |\n-\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |\n-\t\t\t MT7530_VLAN_ACC_ALL);\n-\n-\t/* Set PVID to 0 */\n-\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n-\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n-\n-\tfor (i = 0; i \u003c priv-\u003eds-\u003enum_ports; i++) {\n-\t\tif (i == port)\n-\t\t\tcontinue;\n-\t\tif (dsa_is_user_port(ds, i) \u0026\u0026\n-\t\t dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {\n-\t\t\tall_user_ports_removed = false;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\t/* CPU port also does the same thing until all user ports belonging to\n-\t * the CPU port get out of VLAN filtering mode.\n-\t */\n-\tif (all_user_ports_removed) {\n-\t\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\t\tmt7530_setup_vlan0(priv);\n-\t\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\t}\n-}\n-\n-static void\n-mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)\n-{\n-\tstruct mt7530_priv *priv = ds-\u003epriv;\n-\n-\t/* Trapped into security mode allows packet forwarding through VLAN\n-\t * table lookup.\n-\t */\n-\tif (dsa_is_user_port(ds, port)) {\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n-\t\t\t\t PCR_PORT_VLAN_MASK,\n-\t\t\t\t MT7530_PORT_SECURITY_MODE);\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n-\t\t\t\t G0_PORT_VID_MASK,\n-\t\t\t\t G0_PORT_VID(priv-\u003eports[port].pvid));\n-\n-\t\t/* Only accept tagged frames if PVID is not set */\n-\t\tif (!priv-\u003eports[port].pvid)\n-\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n-\t\t\t\t\t ACC_FRM_MASK,\n-\t\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n-\n-\t\t/* Set the port as a user port which is to be able to recognize\n-\t\t * VID from incoming packets before fetching entry within the\n-\t\t * VLAN table.\n-\t\t */\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n-\t\t\t\t VLAN_ATTR_MASK | PVC_EG_TAG_MASK,\n-\t\t\t\t VLAN_ATTR(MT7530_VLAN_USER) |\n-\t\t\t\t PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));\n-\t} else {\n-\t\t/* Also set CPU ports to the \"user\" VLAN port attribute, to\n-\t\t * allow VLAN classification, but keep the EG_TAG attribute as\n-\t\t * \"consistent\" (i.o.w. don't change its value) for packets\n-\t\t * received by the switch from the CPU, so that tagged packets\n-\t\t * are forwarded to user ports as tagged, and untagged as\n-\t\t * untagged.\n-\t\t */\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n-\t\t\t\t VLAN_ATTR_MASK,\n-\t\t\t\t VLAN_ATTR(MT7530_VLAN_USER));\n-\t}\n+\treturn mt7530_lib_port_bridge_join(\u0026priv-\u003elib_priv, port, bridge,\n+\t\t\t\t\t tx_fwd_offload, extack);\n }\n \n static void\n@@ -1709,18 +1198,7 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int port,\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\n-\tmt7530_update_port_member(priv, port, bridge.dev, false);\n-\n-\t/* When a port is removed from the bridge, the port would be set up\n-\t * back to the default as is at initial boot which is a VLAN-unaware\n-\t * port.\n-\t */\n-\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n-\t\t\t PCR_PORT_VLAN_MASK, MT7530_PORT_MATRIX_MODE);\n-\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n+\treturn mt7530_lib_port_bridge_leave(\u0026priv-\u003elib_priv, port, bridge);\n }\n \n static int\n@@ -1729,15 +1207,8 @@ mt7530_port_fdb_add(struct dsa_switch *ds, int port,\n \t\t struct dsa_db db)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tint ret;\n-\tu8 port_mask = BIT(port);\n \n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\tmt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);\n-\tret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\n-\treturn ret;\n+\treturn mt7530_lib_port_fdb_add(\u0026priv-\u003elib_priv, port, addr, vid, db);\n }\n \n static int\n@@ -1746,15 +1217,8 @@ mt7530_port_fdb_del(struct dsa_switch *ds, int port,\n \t\t struct dsa_db db)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tint ret;\n-\tu8 port_mask = BIT(port);\n \n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\tmt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);\n-\tret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\n-\treturn ret;\n+\treturn mt7530_lib_port_fdb_del(\u0026priv-\u003elib_priv, port, addr, vid, db);\n }\n \n static int\n@@ -1769,13 +1233,14 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,\n \n \tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n-\tret = mt7530_fdb_cmd(priv, MT7530_FDB_START, \u0026rsp);\n+\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_START,\n+\t\t\t\t ATC_MAT_MACTAB, \u0026rsp);\n \tif (ret \u003c 0)\n \t\tgoto err;\n \n \tdo {\n \t\tif (rsp \u0026 ATC_SRCH_HIT) {\n-\t\t\tmt7530_fdb_read(priv, \u0026_fdb);\n+\t\t\tmt7530_lib_fdb_read(\u0026priv-\u003elib_priv, \u0026_fdb);\n \t\t\tif (_fdb.port_mask \u0026 BIT(port)) {\n \t\t\t\tret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,\n \t\t\t\t\t data);\n@@ -1785,7 +1250,8 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,\n \t\t}\n \t} while (--cnt \u0026\u0026\n \t\t !(rsp \u0026 ATC_SRCH_END) \u0026\u0026\n-\t\t !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, \u0026rsp));\n+\t\t !mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_NEXT,\n+\t\t\t\t ATC_MAT_MACTAB, \u0026rsp));\n err:\n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n@@ -1798,27 +1264,8 @@ mt7530_port_mdb_add(struct dsa_switch *ds, int port,\n \t\t struct dsa_db db)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tconst u8 *addr = mdb-\u003eaddr;\n-\tu16 vid = mdb-\u003evid;\n-\tu8 port_mask = 0;\n-\tu32 val;\n-\tint ret;\n \n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\n-\tmt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);\n-\tif (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {\n-\t\tregmap_read(priv-\u003eregmap, MT7530_ATRD, \u0026val);\n-\t\tport_mask = FIELD_GET(PORT_MAP_MASK, val);\n-\t}\n-\n-\tport_mask |= BIT(port);\n-\tmt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);\n-\tret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);\n-\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\n-\treturn ret;\n+\treturn mt7530_lib_port_mdb_add(\u0026priv-\u003elib_priv, port, mdb, db);\n }\n \n static int\n@@ -1827,132 +1274,19 @@ mt7530_port_mdb_del(struct dsa_switch *ds, int port,\n \t\t struct dsa_db db)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tconst u8 *addr = mdb-\u003eaddr;\n-\tu16 vid = mdb-\u003evid;\n-\tu8 port_mask = 0;\n-\tu32 val;\n-\tint ret;\n \n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\n-\tmt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);\n-\tif (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {\n-\t\tregmap_read(priv-\u003eregmap, MT7530_ATRD, \u0026val);\n-\t\tport_mask = FIELD_GET(PORT_MAP_MASK, val);\n-\t}\n-\n-\tport_mask \u0026= ~BIT(port);\n-\tmt7530_fdb_write(priv, vid, port_mask, addr, -1,\n-\t\t\t port_mask ? STATIC_ENT : STATIC_EMP);\n-\tret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);\n-\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\n-\treturn ret;\n+\treturn mt7530_lib_port_mdb_del(\u0026priv-\u003elib_priv, port, mdb, db);\n }\n \n static int\n mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,\n \t\t\t struct netlink_ext_ack *extack)\n {\n-\tstruct dsa_port *dp = dsa_to_port(ds, port);\n-\tstruct dsa_port *cpu_dp = dp-\u003ecpu_dp;\n-\n-\tif (vlan_filtering) {\n-\t\t/* The port is being kept as VLAN-unaware port when bridge is\n-\t\t * set up with vlan_filtering not being set, Otherwise, the\n-\t\t * port and the corresponding CPU port is required the setup\n-\t\t * for becoming a VLAN-aware port.\n-\t\t */\n-\t\tmt7530_port_set_vlan_aware(ds, port);\n-\t\tmt7530_port_set_vlan_aware(ds, cpu_dp-\u003eindex);\n-\t} else {\n-\t\tmt7530_port_set_vlan_unaware(ds, port);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void\n-mt7530_hw_vlan_add(struct mt7530_priv *priv,\n-\t\t struct mt7530_hw_vlan_entry *entry)\n-{\n-\tstruct dsa_port *dp = dsa_to_port(priv-\u003eds, entry-\u003eport);\n-\tu8 new_members;\n-\tu32 val;\n-\n-\tnew_members = entry-\u003eold_members | BIT(entry-\u003eport);\n-\n-\t/* Validate the entry with independent learning, create egress tag per\n-\t * VLAN and joining the port as one of the port members.\n-\t */\n-\tval = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |\n-\t VLAN_VALID;\n-\tregmap_write(priv-\u003eregmap, MT7530_VAWD1, val);\n-\n-\t/* Decide whether adding tag or not for those outgoing packets from the\n-\t * port inside the VLAN.\n-\t * CPU port is always taken as a tagged port for serving more than one\n-\t * VLANs across and also being applied with egress type stack mode for\n-\t * that VLAN tags would be appended after hardware special tag used as\n-\t * DSA tag.\n-\t */\n-\tif (dsa_port_is_cpu(dp))\n-\t\tval = MT7530_VLAN_EGRESS_STACK;\n-\telse if (entry-\u003euntagged)\n-\t\tval = MT7530_VLAN_EGRESS_UNTAG;\n-\telse\n-\t\tval = MT7530_VLAN_EGRESS_TAG;\n-\tregmap_update_bits(priv-\u003eregmap, MT7530_VAWD2,\n-\t\t\t ETAG_CTRL_P_MASK(entry-\u003eport),\n-\t\t\t ETAG_CTRL_P(entry-\u003eport, val));\n-}\n-\n-static void\n-mt7530_hw_vlan_del(struct mt7530_priv *priv,\n-\t\t struct mt7530_hw_vlan_entry *entry)\n-{\n-\tu8 new_members;\n-\tu32 val;\n-\n-\tnew_members = entry-\u003eold_members \u0026 ~BIT(entry-\u003eport);\n-\n-\tregmap_read(priv-\u003eregmap, MT7530_VAWD1, \u0026val);\n-\tif (!(val \u0026 VLAN_VALID)) {\n-\t\tdev_err(priv-\u003edev,\n-\t\t\t\"Cannot be deleted due to invalid entry\\n\");\n-\t\treturn;\n-\t}\n-\n-\tif (new_members) {\n-\t\tval = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |\n-\t\t VLAN_VALID;\n-\t\tregmap_write(priv-\u003eregmap, MT7530_VAWD1, val);\n-\t} else {\n-\t\tregmap_write(priv-\u003eregmap, MT7530_VAWD1, 0);\n-\t\tregmap_write(priv-\u003eregmap, MT7530_VAWD2, 0);\n-\t}\n-}\n-\n-static void\n-mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,\n-\t\t struct mt7530_hw_vlan_entry *entry,\n-\t\t mt7530_vlan_op vlan_op)\n-{\n-\tu32 val;\n-\n-\t/* Fetch entry */\n-\tmt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);\n-\n-\tregmap_read(priv-\u003eregmap, MT7530_VAWD1, \u0026val);\n-\n-\tentry-\u003eold_members = FIELD_GET(PORT_MEM_MASK, val);\n-\n-\t/* Manipulate entry */\n-\tvlan_op(priv, entry);\n+\tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\t/* Flush result to hardware */\n-\tmt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);\n+\treturn mt7530_lib_port_vlan_filtering(\u0026priv-\u003elib_priv, port,\n+\t\t\t\t\t vlan_filtering,\n+\t\t\t\t\t extack);\n }\n \n static int\n@@ -1960,94 +1294,18 @@ mt7530_port_vlan_add(struct dsa_switch *ds, int port,\n \t\t const struct switchdev_obj_port_vlan *vlan,\n \t\t struct netlink_ext_ack *extack)\n {\n-\tbool untagged = vlan-\u003eflags \u0026 BRIDGE_VLAN_INFO_UNTAGGED;\n-\tbool pvid = vlan-\u003eflags \u0026 BRIDGE_VLAN_INFO_PVID;\n-\tstruct mt7530_hw_vlan_entry new_entry;\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\n-\t/* VID 0 is managed exclusively by mt7530_setup_vlan0() for\n-\t * VLAN-unaware bridge operation. Don't let the bridge overwrite\n-\t * its EG_CON flag with VTAG_EN and corrupt PORT_MEM.\n-\t */\n-\tif (vlan-\u003evid == 0)\n-\t\tgoto skip_vlan_table;\n-\n-\tmt7530_hw_vlan_entry_init(\u0026new_entry, port, untagged);\n-\tmt7530_hw_vlan_update(priv, vlan-\u003evid, \u0026new_entry, mt7530_hw_vlan_add);\n-\n-skip_vlan_table:\n-\n-\tif (pvid) {\n-\t\tpriv-\u003eports[port].pvid = vlan-\u003evid;\n-\n-\t\t/* Accept all frames if PVID is set */\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n-\t\t\t\t ACC_FRM_MASK, MT7530_VLAN_ACC_ALL);\n-\n-\t\t/* Only configure PVID if VLAN filtering is enabled */\n-\t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n-\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n-\t\t\t\t\t G0_PORT_VID_MASK,\n-\t\t\t\t\t G0_PORT_VID(vlan-\u003evid));\n-\t} else if (vlan-\u003evid \u0026\u0026 priv-\u003eports[port].pvid == vlan-\u003evid) {\n-\t\t/* This VLAN is overwritten without PVID, so unset it */\n-\t\tpriv-\u003eports[port].pvid = G0_PORT_VID_DEF;\n-\n-\t\t/* Only accept tagged frames if the port is VLAN-aware */\n-\t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n-\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n-\t\t\t\t\t ACC_FRM_MASK,\n-\t\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n-\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n-\t\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n-\t}\n-\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\n-\treturn 0;\n+\treturn mt7530_lib_port_vlan_add(\u0026priv-\u003elib_priv, port, vlan, extack);\n }\n \n static int\n mt7530_port_vlan_del(struct dsa_switch *ds, int port,\n \t\t const struct switchdev_obj_port_vlan *vlan)\n {\n-\tstruct mt7530_hw_vlan_entry target_entry;\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n \n-\tmutex_lock(\u0026priv-\u003ereg_mutex);\n-\n-\t/* VID 0 is managed exclusively by mt7530_setup_vlan0(). */\n-\tif (vlan-\u003evid == 0)\n-\t\tgoto skip_vlan_table;\n-\n-\tmt7530_hw_vlan_entry_init(\u0026target_entry, port, 0);\n-\tmt7530_hw_vlan_update(priv, vlan-\u003evid, \u0026target_entry,\n-\t\t\t mt7530_hw_vlan_del);\n-\n-skip_vlan_table:\n-\t/* PVID is being restored to the default whenever the PVID port\n-\t * is being removed from the VLAN.\n-\t */\n-\tif (priv-\u003eports[port].pvid == vlan-\u003evid) {\n-\t\tpriv-\u003eports[port].pvid = G0_PORT_VID_DEF;\n-\n-\t\t/* Only accept tagged frames if the port is VLAN-aware */\n-\t\tif (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))\n-\t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(port),\n-\t\t\t\t\t ACC_FRM_MASK,\n-\t\t\t\t\t MT7530_VLAN_ACC_TAGGED);\n-\n-\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(port),\n-\t\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n-\t}\n-\n-\n-\tmutex_unlock(\u0026priv-\u003ereg_mutex);\n-\n-\treturn 0;\n+\treturn mt7530_lib_port_vlan_del(\u0026priv-\u003elib_priv, port, vlan);\n }\n \n static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,\n@@ -2055,60 +1313,16 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,\n \t\t\t\t bool ingress, struct netlink_ext_ack *extack)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tint monitor_port;\n-\tu32 val;\n-\n-\t/* Check for existent entry */\n-\tif ((ingress ? priv-\u003emirror_rx : priv-\u003emirror_tx) \u0026 BIT(port))\n-\t\treturn -EEXIST;\n-\n-\tregmap_read(priv-\u003eregmap, MT753X_MIRROR_REG(priv-\u003eid), \u0026val);\n-\n-\t/* MT7530 only supports one monitor port */\n-\tmonitor_port = MT753X_MIRROR_PORT_GET(priv-\u003eid, val);\n-\tif (val \u0026 MT753X_MIRROR_EN(priv-\u003eid) \u0026\u0026\n-\t monitor_port != mirror-\u003eto_local_port)\n-\t\treturn -EEXIST;\n-\n-\tval |= MT753X_MIRROR_EN(priv-\u003eid);\n-\tval \u0026= ~MT753X_MIRROR_PORT_MASK(priv-\u003eid);\n-\tval |= MT753X_MIRROR_PORT_SET(priv-\u003eid, mirror-\u003eto_local_port);\n-\tregmap_write(priv-\u003eregmap, MT753X_MIRROR_REG(priv-\u003eid), val);\n \n-\tregmap_read(priv-\u003eregmap, MT7530_PCR_P(port), \u0026val);\n-\tif (ingress) {\n-\t\tval |= PORT_RX_MIR;\n-\t\tpriv-\u003emirror_rx |= BIT(port);\n-\t} else {\n-\t\tval |= PORT_TX_MIR;\n-\t\tpriv-\u003emirror_tx |= BIT(port);\n-\t}\n-\tregmap_write(priv-\u003eregmap, MT7530_PCR_P(port), val);\n-\n-\treturn 0;\n+\treturn mt7530_lib_port_mirror_add(\u0026priv-\u003elib_priv, port, mirror, ingress, extack);\n }\n \n static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,\n \t\t\t\t struct dsa_mall_mirror_tc_entry *mirror)\n {\n \tstruct mt7530_priv *priv = ds-\u003epriv;\n-\tu32 val;\n \n-\tregmap_read(priv-\u003eregmap, MT7530_PCR_P(port), \u0026val);\n-\tif (mirror-\u003eingress) {\n-\t\tval \u0026= ~PORT_RX_MIR;\n-\t\tpriv-\u003emirror_rx \u0026= ~BIT(port);\n-\t} else {\n-\t\tval \u0026= ~PORT_TX_MIR;\n-\t\tpriv-\u003emirror_tx \u0026= ~BIT(port);\n-\t}\n-\tregmap_write(priv-\u003eregmap, MT7530_PCR_P(port), val);\n-\n-\tif (!priv-\u003emirror_rx \u0026\u0026 !priv-\u003emirror_tx) {\n-\t\tregmap_read(priv-\u003eregmap, MT753X_MIRROR_REG(priv-\u003eid), \u0026val);\n-\t\tval \u0026= ~MT753X_MIRROR_EN(priv-\u003eid);\n-\t\tregmap_write(priv-\u003eregmap, MT753X_MIRROR_REG(priv-\u003eid), val);\n-\t}\n+\tmt7530_lib_port_mirror_del(\u0026priv-\u003elib_priv, port, mirror);\n }\n \n static enum dsa_tag_protocol\n@@ -2492,10 +1706,10 @@ mt7530_setup(struct dsa_switch *ds)\n \tif ((val \u0026 MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)\n \t\tmt7530_pll_setup(priv);\n \n-\tmt753x_trap_frames(priv);\n+\tmt7530_lib_trap_frames(\u0026priv-\u003elib_priv);\n \n \t/* Enable and reset MIB counters */\n-\tmt7530_mib_reset(ds);\n+\tmt7530_lib_mib_reset(\u0026priv-\u003elib_priv);\n \n \tfor (i = 0; i \u003c priv-\u003eds-\u003enum_ports; i++) {\n \t\t/* Clear link settings and enable force mode to force link down\n@@ -2519,7 +1733,8 @@ mt7530_setup(struct dsa_switch *ds)\n \n \t\t\t/* Set default PVID to 0 on all user ports */\n \t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(i),\n-\t\t\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n+\t\t\t\t\t G0_PORT_VID_MASK,\n+\t\t\t\t\t G0_PORT_VID(G0_PORT_VID_DEF));\n \t\t}\n \t\t/* Enable consistent egress tag */\n \t\tregmap_update_bits(priv-\u003eregmap, MT7530_PVC_P(i),\n@@ -2531,7 +1746,7 @@ mt7530_setup(struct dsa_switch *ds)\n \tregmap_set_bits(priv-\u003eregmap, MT753X_AGC, LOCAL_EN);\n \n \t/* Setup VLAN ID 0 for VLAN-unaware bridges */\n-\tret = mt7530_setup_vlan0(priv);\n+\tret = mt7530_lib_setup_vlan0(\u0026priv-\u003elib_priv);\n \tif (ret)\n \t\treturn ret;\n \n@@ -2590,7 +1805,8 @@ mt7530_setup(struct dsa_switch *ds)\n #endif /* CONFIG_GPIOLIB */\n \n \t/* Flush the FDB table */\n-\tret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);\n+\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_FLUSH,\n+\t\t\t\t ATC_MAT_MACTAB, NULL);\n \tif (ret \u003c 0)\n \t\treturn ret;\n \n@@ -2609,10 +1825,10 @@ mt7531_setup_common(struct dsa_switch *ds)\n \tds-\u003eageing_time_min = 2 * 1000;\n \tds-\u003eageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000;\n \n-\tmt753x_trap_frames(priv);\n+\tmt7530_lib_trap_frames(\u0026priv-\u003elib_priv);\n \n \t/* Enable and reset MIB counters */\n-\tmt7530_mib_reset(ds);\n+\tmt7530_lib_mib_reset(\u0026priv-\u003elib_priv);\n \n \t/* Disable flooding on all ports */\n \tregmap_clear_bits(priv-\u003eregmap, MT753X_MFC,\n@@ -2643,7 +1859,8 @@ mt7531_setup_common(struct dsa_switch *ds)\n \n \t\t\t/* Set default PVID to 0 on all user ports */\n \t\t\tregmap_update_bits(priv-\u003eregmap, MT7530_PPBV1_P(i),\n-\t\t\t\t\t G0_PORT_VID_MASK, G0_PORT_VID_DEF);\n+\t\t\t\t\t G0_PORT_VID_MASK,\n+\t\t\t\t\t G0_PORT_VID(G0_PORT_VID_DEF));\n \t\t}\n \n \t\t/* Enable consistent egress tag */\n@@ -2661,12 +1878,13 @@ mt7531_setup_common(struct dsa_switch *ds)\n \t\t\t CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN);\n \n \t/* Flush the FDB table */\n-\tret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);\n+\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_FLUSH,\n+\t\t\t\t ATC_MAT_MACTAB, NULL);\n \tif (ret \u003c 0)\n \t\treturn ret;\n \n \t/* Setup VLAN ID 0 for VLAN-unaware bridges */\n-\treturn mt7530_setup_vlan0(priv);\n+\treturn mt7530_lib_setup_vlan0(\u0026priv-\u003elib_priv);\n }\n \n static int\n@@ -3281,11 +2499,12 @@ mt753x_port_change_conduit(struct dsa_switch *ds, int port,\n \tmutex_lock(\u0026priv-\u003ereg_mutex);\n \n \t/* dp-\u003ecpu_dp still points to the old CPU port */\n-\tpriv-\u003eports[port].pm \u0026= ~PCR_MATRIX(BIT(dp-\u003ecpu_dp-\u003eindex));\n-\tpriv-\u003eports[port].pm |= PCR_MATRIX(BIT(new_cpu_dp-\u003eindex));\n+\tpriv-\u003eports[port].pm \u0026= ~BIT(dp-\u003ecpu_dp-\u003eindex);\n+\tpriv-\u003eports[port].pm |= BIT(new_cpu_dp-\u003eindex);\n \tif (priv-\u003eports[port].enable)\n \t\tregmap_update_bits(priv-\u003eregmap, MT7530_PCR_P(port),\n-\t\t\t\t PCR_MATRIX_MASK, priv-\u003eports[port].pm);\n+\t\t\t\t PCR_MATRIX_MASK,\n+\t\t\t\t PCR_MATRIX(priv-\u003eports[port].pm));\n \n \tmutex_unlock(\u0026priv-\u003ereg_mutex);\n \n@@ -3456,6 +2675,8 @@ static const struct phylink_mac_ops mt753x_phylink_mac_ops = {\n const struct mt753x_info mt753x_table[] = {\n \t[ID_MT7621] = {\n \t\t.id = ID_MT7621,\n+\t\t.reg_fields = mt7530_fields,\n+\t\t.num_reg_fields = ARRAY_SIZE(mt7530_fields),\n \t\t.pcs_ops = \u0026mt7530_pcs_ops,\n \t\t.sw_setup = mt7530_setup,\n \t\t.phy_read_c22 = mt7530_phy_read_c22,\n@@ -3467,6 +2688,8 @@ const struct mt753x_info mt753x_table[] = {\n \t},\n \t[ID_MT7530] = {\n \t\t.id = ID_MT7530,\n+\t\t.reg_fields = mt7530_fields,\n+\t\t.num_reg_fields = ARRAY_SIZE(mt7530_fields),\n \t\t.pcs_ops = \u0026mt7530_pcs_ops,\n \t\t.sw_setup = mt7530_setup,\n \t\t.phy_read_c22 = mt7530_phy_read_c22,\n@@ -3478,6 +2701,8 @@ const struct mt753x_info mt753x_table[] = {\n \t},\n \t[ID_MT7531] = {\n \t\t.id = ID_MT7531,\n+\t\t.reg_fields = mt7531_fields,\n+\t\t.num_reg_fields = ARRAY_SIZE(mt7531_fields),\n \t\t.pcs_ops = \u0026mt7530_pcs_ops,\n \t\t.sw_setup = mt7531_setup,\n \t\t.phy_read_c22 = mt7531_ind_c22_phy_read,\n@@ -3489,6 +2714,8 @@ const struct mt753x_info mt753x_table[] = {\n \t},\n \t[ID_MT7988] = {\n \t\t.id = ID_MT7988,\n+\t\t.reg_fields = mt7531_fields,\n+\t\t.num_reg_fields = ARRAY_SIZE(mt7531_fields),\n \t\t.pcs_ops = \u0026mt7530_pcs_ops,\n \t\t.sw_setup = mt7988_setup,\n \t\t.phy_read_c22 = mt7531_ind_c22_phy_read,\n@@ -3499,6 +2726,8 @@ const struct mt753x_info mt753x_table[] = {\n \t},\n \t[ID_EN7581] = {\n \t\t.id = ID_EN7581,\n+\t\t.reg_fields = mt7531_fields,\n+\t\t.num_reg_fields = ARRAY_SIZE(mt7531_fields),\n \t\t.pcs_ops = \u0026mt7530_pcs_ops,\n \t\t.sw_setup = mt7988_setup,\n \t\t.phy_read_c22 = mt7531_ind_c22_phy_read,\n@@ -3509,6 +2738,8 @@ const struct mt753x_info mt753x_table[] = {\n \t},\n \t[ID_AN7583] = {\n \t\t.id = ID_AN7583,\n+\t\t.reg_fields = mt7531_fields,\n+\t\t.num_reg_fields = ARRAY_SIZE(mt7531_fields),\n \t\t.pcs_ops = \u0026mt7530_pcs_ops,\n \t\t.sw_setup = mt7988_setup,\n \t\t.phy_read_c22 = mt7531_ind_c22_phy_read,\n@@ -3519,6 +2750,8 @@ const struct mt753x_info mt753x_table[] = {\n \t},\n \t[ID_EN7528] = {\n \t\t.id = ID_EN7528,\n+\t\t.reg_fields = mt7531_fields,\n+\t\t.num_reg_fields = ARRAY_SIZE(mt7531_fields),\n \t\t.pcs_ops = \u0026mt7530_pcs_ops,\n \t\t.sw_setup = mt7988_setup,\n \t\t.phy_read_c22 = mt7531_ind_c22_phy_read,\n@@ -3576,6 +2809,47 @@ mt7530_remove_common(struct mt7530_priv *priv)\n }\n EXPORT_SYMBOL_GPL(mt7530_remove_common);\n \n+int mt7530_setup_lib_priv(struct mt7530_priv *priv)\n+{\n+\tstruct mt7530_lib_priv *lib_priv = \u0026priv-\u003elib_priv;\n+\tint i;\n+\n+\tlib_priv-\u003edev = priv-\u003edev;\n+\tlib_priv-\u003eds = priv-\u003eds;\n+\tlib_priv-\u003eregmap = priv-\u003eregmap;\n+\tlib_priv-\u003eports = priv-\u003eports;\n+\tlib_priv-\u003ereg_mutex = \u0026priv-\u003ereg_mutex;\n+\n+\tfor (i = 0; i \u003c ARRAY_SIZE(mt753x_fields); i++) {\n+\t\tconst struct mt7530_reg_field *reg_field;\n+\t\tstruct regmap_field *field;\n+\n+\t\treg_field = \u0026mt753x_fields[i];\n+\t\tfield = devm_regmap_field_alloc(priv-\u003edev, priv-\u003eregmap,\n+\t\t\t\t\t\treg_field-\u003efield);\n+\t\tif (IS_ERR(field))\n+\t\t\treturn PTR_ERR(field);\n+\n+\t\tlib_priv-\u003efields[reg_field-\u003eid] = field;\n+\t}\n+\n+\tfor (i = 0; i \u003c priv-\u003einfo-\u003enum_reg_fields; i++) {\n+\t\tconst struct mt7530_reg_field *reg_field;\n+\t\tstruct regmap_field *field;\n+\n+\t\treg_field = \u0026priv-\u003einfo-\u003ereg_fields[i];\n+\t\tfield = devm_regmap_field_alloc(priv-\u003edev, priv-\u003eregmap,\n+\t\t\t\t\t\treg_field-\u003efield);\n+\t\tif (IS_ERR(field))\n+\t\t\treturn PTR_ERR(field);\n+\n+\t\tlib_priv-\u003efields[reg_field-\u003eid] = field;\n+\t}\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(mt7530_setup_lib_priv);\n+\n MODULE_AUTHOR(\"Sean Wang \u003csean.wang@mediatek.com\u003e\");\n MODULE_DESCRIPTION(\"Driver for Mediatek MT7530 Switch\");\n MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h\nindex 2bbbe617b52ee..50a12e10893d8 100644\n--- a/drivers/net/dsa/mt7530.h\n+++ b/drivers/net/dsa/mt7530.h\n@@ -7,14 +7,11 @@\n #define __MT7530_H\n \n #include \u003clinux/bitfield.h\u003e\n+#include \"mt7530-lib.h\"\n \n #define MT7530_NUM_PORTS\t\t7\n #define MT7530_NUM_PHYS\t\t\t5\n #define MT7530_NUM_FDB_RECORDS\t\t2048\n-#define MT7530_ALL_MEMBERS\t\t0xff\n-\n-#define MTK_HDR_LEN\t4\n-#define MT7530_MAX_MTU\t(15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)\n \n enum mt753x_id {\n \tID_MT7530 = 0,\n@@ -135,18 +132,8 @@ enum mt753x_id {\n #define R03_EG_TAG(x)\t\t\tFIELD_PREP(R03_EG_TAG_MASK, x)\n #define R03_PORT_FW_MASK\t\tGENMASK(2, 0)\n \n-enum mt753x_to_cpu_fw {\n-\tTO_CPU_FW_SYSTEM_DEFAULT,\n-\tTO_CPU_FW_CPU_EXCLUDE = 4,\n-\tTO_CPU_FW_CPU_INCLUDE = 5,\n-\tTO_CPU_FW_CPU_ONLY = 6,\n-\tTO_CPU_FW_DROP = 7,\n-};\n-\n /* Registers for address table access */\n #define MT7530_ATA1\t\t\t0x74\n-#define STATIC_EMP\t\t\t0\n-#define STATIC_ENT\t\t\t3\n #define MT7530_ATA2\t\t\t0x78\n #define ATA2_IVL\t\t\tBIT(15)\n #define ATA2_FID_MASK\t\t\tGENMASK(14, 12)\n@@ -165,16 +152,6 @@ enum mt753x_to_cpu_fw {\n #define ATC_INVALID\t\t\tBIT(12)\n #define ATC_MAT_MASK\t\t\tGENMASK(11, 8)\n #define ATC_MAT(x)\t\t\tFIELD_PREP(ATC_MAT_MASK, x)\n-#define ATC_MAT_MACTAB\t\t\tATC_MAT(0)\n-#define ATC_MAT_NON_STATIC_MAC\t\tATC_MAT(4)\n-\n-enum mt7530_fdb_cmd {\n-\tMT7530_FDB_READ\t= 0,\n-\tMT7530_FDB_WRITE = 1,\n-\tMT7530_FDB_FLUSH = 2,\n-\tMT7530_FDB_START = 4,\n-\tMT7530_FDB_NEXT = 5,\n-};\n \n /* Registers for table search read address */\n #define MT7530_TSRA1\t\t\t0x84\n@@ -202,14 +179,6 @@ enum mt7530_fdb_cmd {\n #define VTCR_VID_MASK\t\t\tGENMASK(11, 0)\n #define VTCR_VID(x)\t\t\tFIELD_PREP(VTCR_VID_MASK, x)\n \n-enum mt7530_vlan_cmd {\n-\t/* Read/Write the specified VID entry from VAWD register based\n-\t * on VID.\n-\t */\n-\tMT7530_VTCR_RD_VID = 0,\n-\tMT7530_VTCR_WR_VID = 1,\n-};\n-\n /* Register for setup vlan and acl write data */\n #define MT7530_VAWD1\t\t\t0x94\n #define PORT_STAG\t\t\tBIT(31)\n@@ -228,21 +197,7 @@ enum mt7530_vlan_cmd {\n /* VLAN Entry Valid */\n #define VLAN_VALID\t\t\tBIT(0)\n \n-enum mt7530_fid {\n-\tFID_STANDALONE = 0,\n-\tFID_BRIDGED = 1,\n-};\n-\n #define MT7530_VAWD2\t\t\t0x98\n-/* Egress Tag Control */\n-#define ETAG_CTRL_P(p, x)\t\t(((x) \u0026 0x3) \u003c\u003c ((p) \u003c\u003c 1))\n-#define ETAG_CTRL_P_MASK(p)\t\tETAG_CTRL_P(p, 3)\n-\n-enum mt7530_vlan_egress_attr {\n-\tMT7530_VLAN_EGRESS_UNTAG = 0,\n-\tMT7530_VLAN_EGRESS_TAG = 2,\n-\tMT7530_VLAN_EGRESS_STACK = 3,\n-};\n \n /* Register for address age control */\n #define MT7530_AAC\t\t\t0xa0\n@@ -270,40 +225,16 @@ enum mt7530_vlan_egress_attr {\n #define EGR_BC_CRC_IPG_PREAMBLE\t0x18\t/* crc + ipg + preamble */\n \n /* Register for port STP state control */\n-#define MT7530_SSP_P(x)\t\t\t(0x2000 + ((x) * 0x100))\n-#define FID_PST(fid, state)\t\t(((state) \u0026 0x3) \u003c\u003c ((fid) * 2))\n-#define FID_PST_MASK(fid)\t\tFID_PST(fid, 0x3)\n-\n-enum mt7530_stp_state {\n-\tMT7530_STP_DISABLED = 0,\n-\tMT7530_STP_BLOCKING = 1,\n-\tMT7530_STP_LISTENING = 1,\n-\tMT7530_STP_LEARNING = 2,\n-\tMT7530_STP_FORWARDING = 3\n-};\n+#define MT7530_SSP\t\t\t0x2000\n+#define MT7530_SSP_P(x)\t\t\t(MT7530_SSP + ((x) * 0x100))\n \n /* Register for port control */\n-#define MT7530_PCR_P(x)\t\t\t(0x2004 + ((x) * 0x100))\n+#define MT7530_PCR\t\t\t0x2004\n+#define MT7530_PCR_P(x)\t\t\t(MT7530_PCR + ((x) * 0x100))\n #define PORT_TX_MIR\t\t\tBIT(9)\n #define PORT_RX_MIR\t\t\tBIT(8)\n #define PCR_PORT_VLAN_MASK\t\tGENMASK(1, 0)\n \n-enum mt7530_port_mode {\n-\t/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */\n-\tMT7530_PORT_MATRIX_MODE = 0,\n-\n-\t/* Fallback Mode: Forward received frames with ingress ports that do\n-\t * not belong to the VLAN member. Frames whose VID is not listed on\n-\t * the VLAN table are forwarded by the PCR_MATRIX members.\n-\t */\n-\tMT7530_PORT_FALLBACK_MODE = 1,\n-\n-\t/* Security Mode: Discard any frame due to ingress membership\n-\t * violation or VID missed on the VLAN table.\n-\t */\n-\tMT7530_PORT_SECURITY_MODE = 3,\n-};\n-\n #define PCR_MATRIX_MASK\t\tGENMASK(23, 16)\n #define PCR_MATRIX(x)\t\t\tFIELD_PREP(PCR_MATRIX_MASK, x)\n #define PORT_PRI_MASK\t\t\tGENMASK(26, 24)\n@@ -313,11 +244,13 @@ enum mt7530_port_mode {\n #define PCR_MATRIX_CLR\t\t\tPCR_MATRIX(0)\n \n /* Register for port security control */\n-#define MT7530_PSC_P(x)\t\t\t(0x200c + ((x) * 0x100))\n+#define MT7530_PSC\t\t\t0x200c\n+#define MT7530_PSC_P(x)\t\t\t(MT7530_PSC + ((x) * 0x100))\n #define SA_DIS\t\t\t\tBIT(4)\n \n /* Register for port vlan control */\n-#define MT7530_PVC_P(x)\t\t\t(0x2010 + ((x) * 0x100))\n+#define MT7530_PVC\t\t\t0x2010\n+#define MT7530_PVC_P(x)\t\t\t(MT7530_PVC + ((x) * 0x100))\n #define PORT_SPEC_TAG\t\t\tBIT(5)\n #define PVC_EG_TAG_MASK\t\tGENMASK(10, 8)\n #define PVC_EG_TAG(x)\t\t\tFIELD_PREP(PVC_EG_TAG_MASK, x)\n@@ -325,31 +258,14 @@ enum mt7530_port_mode {\n #define VLAN_ATTR(x)\t\t\tFIELD_PREP(VLAN_ATTR_MASK, x)\n #define ACC_FRM_MASK\t\t\tGENMASK(1, 0)\n \n-enum mt7530_vlan_port_eg_tag {\n-\tMT7530_VLAN_EG_DISABLED = 0,\n-\tMT7530_VLAN_EG_CONSISTENT = 1,\n-\tMT7530_VLAN_EG_UNTAGGED = 4,\n-};\n-\n-enum mt7530_vlan_port_attr {\n-\tMT7530_VLAN_USER = 0,\n-\tMT7530_VLAN_TRANSPARENT = 3,\n-};\n-\n-enum mt7530_vlan_port_acc_frm {\n-\tMT7530_VLAN_ACC_ALL = 0,\n-\tMT7530_VLAN_ACC_TAGGED = 1,\n-\tMT7530_VLAN_ACC_UNTAGGED = 2,\n-};\n-\n #define STAG_VPID_MASK\t\t\tGENMASK(31, 16)\n #define STAG_VPID(x)\t\t\tFIELD_PREP(STAG_VPID_MASK, x)\n \n /* Register for port port-and-protocol based vlan 1 control */\n+#define MT7530_PPBV1\t\t\t0x2014\n #define MT7530_PPBV1_P(x)\t\t(0x2014 + ((x) * 0x100))\n #define G0_PORT_VID_MASK\t\tGENMASK(11, 0)\n #define G0_PORT_VID(x)\t\t\tFIELD_PREP(G0_PORT_VID_MASK, x)\n-#define G0_PORT_VID_DEF\t\tG0_PORT_VID(0)\n \n /* Register for port MAC control register */\n #define MT753X_PMCR_P(x)\t\t(0x3000 + ((x) * 0x100))\n@@ -427,55 +343,54 @@ enum mt7530_vlan_port_acc_frm {\n #define MAX_RX_JUMBO_MASK\t\tGENMASK(5, 2)\n #define MAX_RX_JUMBO(x)\t\tFIELD_PREP(MAX_RX_JUMBO_MASK, x)\n #define MAX_RX_PKT_LEN_MASK\t\tGENMASK(1, 0)\n-#define MAX_RX_PKT_LEN_1522\t\t0x0\n-#define MAX_RX_PKT_LEN_1536\t\t0x1\n-#define MAX_RX_PKT_LEN_1552\t\t0x2\n-#define MAX_RX_PKT_LEN_JUMBO\t\t0x3\n \n /* Register for MIB */\n-#define MT7530_PORT_MIB_COUNTER(x)\t(0x4000 + (x) * 0x100)\n+#define MT7530_MIB_COUNTER\t\t0x4000\n+#define MT7530_PORT_MIB_COUNTER(x)\t(MT7530_MIB_COUNTER + (x) * 0x100)\n /* Each define is an offset of MT7530_PORT_MIB_COUNTER */\n-#define MT7530_PORT_MIB_TX_DROP\t0x00\n-#define MT7530_PORT_MIB_TX_CRC_ERR\t0x04\n-#define MT7530_PORT_MIB_TX_UNICAST\t0x08\n-#define MT7530_PORT_MIB_TX_MULTICAST\t0x0c\n-#define MT7530_PORT_MIB_TX_BROADCAST\t0x10\n-#define MT7530_PORT_MIB_TX_COLLISION\t0x14\n-#define MT7530_PORT_MIB_TX_SINGLE_COLLISION 0x18\n-#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c\n-#define MT7530_PORT_MIB_TX_DEFERRED\t0x20\n-#define MT7530_PORT_MIB_TX_LATE_COLLISION 0x24\n-#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28\n-#define MT7530_PORT_MIB_TX_PAUSE\t0x2c\n-#define MT7530_PORT_MIB_TX_PKT_SZ_64\t0x30\n-#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34\n-#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38\n-#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3c\n-#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40\n-#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX 0x44\n-#define MT7530_PORT_MIB_TX_BYTES\t0x48 /* 64 bytes */\n-#define MT7530_PORT_MIB_RX_DROP\t0x60\n-#define MT7530_PORT_MIB_RX_FILTERING\t0x64\n-#define MT7530_PORT_MIB_RX_UNICAST\t0x68\n-#define MT7530_PORT_MIB_RX_MULTICAST\t0x6c\n-#define MT7530_PORT_MIB_RX_BROADCAST\t0x70\n-#define MT7530_PORT_MIB_RX_ALIGN_ERR\t0x74\n-#define MT7530_PORT_MIB_RX_CRC_ERR\t0x78\n-#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR 0x7c\n-#define MT7530_PORT_MIB_RX_FRAG_ERR\t0x80\n-#define MT7530_PORT_MIB_RX_OVER_SZ_ERR 0x84\n-#define MT7530_PORT_MIB_RX_JABBER_ERR\t0x88\n-#define MT7530_PORT_MIB_RX_PAUSE\t0x8c\n-#define MT7530_PORT_MIB_RX_PKT_SZ_64\t0x90\n-#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 0x94\n-#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 0x98\n-#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 0x9c\n-#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xa0\n-#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX 0xa4\n-#define MT7530_PORT_MIB_RX_BYTES\t0xa8 /* 64 bytes */\n-#define MT7530_PORT_MIB_RX_CTRL_DROP\t0xb0\n-#define MT7530_PORT_MIB_RX_INGRESS_DROP 0xb4\n-#define MT7530_PORT_MIB_RX_ARL_DROP\t0xb8\n+#define MT7530_PORT_MIB_TX_DROP\t(MT7530_MIB_COUNTER + 0x00)\n+#define MT7530_PORT_MIB_TX_CRC_ERR\t(MT7530_MIB_COUNTER + 0x04)\n+#define MT7530_PORT_MIB_TX_UNICAST\t(MT7530_MIB_COUNTER + 0x08)\n+#define MT7530_PORT_MIB_TX_MULTICAST\t(MT7530_MIB_COUNTER + 0x0c)\n+#define MT7530_PORT_MIB_TX_BROADCAST\t(MT7530_MIB_COUNTER + 0x10)\n+#define MT7530_PORT_MIB_TX_COLLISION\t(MT7530_MIB_COUNTER + 0x14)\n+#define MT7530_PORT_MIB_TX_SINGLE_COLLISION (MT7530_MIB_COUNTER + 0x18)\n+#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION (MT7530_MIB_COUNTER + 0x1c)\n+#define MT7530_PORT_MIB_TX_DEFERRED\t(MT7530_MIB_COUNTER + 0x20)\n+#define MT7530_PORT_MIB_TX_LATE_COLLISION (MT7530_MIB_COUNTER + 0x24)\n+#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION (MT7530_MIB_COUNTER + 0x28)\n+#define MT7530_PORT_MIB_TX_PAUSE\t(MT7530_MIB_COUNTER + 0x2c)\n+#define MT7530_PORT_MIB_TX_PKT_SZ_64\t(MT7530_MIB_COUNTER + 0x30)\n+#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 (MT7530_MIB_COUNTER + 0x34)\n+#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 (MT7530_MIB_COUNTER + 0x38)\n+#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 (MT7530_MIB_COUNTER + 0x3c)\n+#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 (MT7530_MIB_COUNTER + 0x40)\n+#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX (MT7530_MIB_COUNTER + 0x44)\n+#define MT7530_PORT_MIB_TX_BYTES_LOW\t(MT7530_MIB_COUNTER + 0x48) /* 64 bytes */\n+#define MT7530_PORT_MIB_TX_BYTES_HIGH\t(MT7530_MIB_COUNTER + 0x4c)\n+#define MT7530_PORT_MIB_RX_DROP\t(MT7530_MIB_COUNTER + 0x60)\n+#define MT7530_PORT_MIB_RX_FILTERING\t(MT7530_MIB_COUNTER + 0x64)\n+#define MT7530_PORT_MIB_RX_UNICAST\t(MT7530_MIB_COUNTER + 0x68)\n+#define MT7530_PORT_MIB_RX_MULTICAST\t(MT7530_MIB_COUNTER + 0x6c)\n+#define MT7530_PORT_MIB_RX_BROADCAST\t(MT7530_MIB_COUNTER + 0x70)\n+#define MT7530_PORT_MIB_RX_ALIGN_ERR\t(MT7530_MIB_COUNTER + 0x74)\n+#define MT7530_PORT_MIB_RX_CRC_ERR\t(MT7530_MIB_COUNTER + 0x78)\n+#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR (MT7530_MIB_COUNTER + 0x7c)\n+#define MT7530_PORT_MIB_RX_FRAG_ERR\t(MT7530_MIB_COUNTER + 0x80)\n+#define MT7530_PORT_MIB_RX_OVER_SZ_ERR (MT7530_MIB_COUNTER + 0x84)\n+#define MT7530_PORT_MIB_RX_JABBER_ERR\t(MT7530_MIB_COUNTER + 0x88)\n+#define MT7530_PORT_MIB_RX_PAUSE\t(MT7530_MIB_COUNTER + 0x8c)\n+#define MT7530_PORT_MIB_RX_PKT_SZ_64\t(MT7530_MIB_COUNTER + 0x90)\n+#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 (MT7530_MIB_COUNTER + 0x94)\n+#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 (MT7530_MIB_COUNTER + 0x98)\n+#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 (MT7530_MIB_COUNTER + 0x9c)\n+#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 (MT7530_MIB_COUNTER + 0xa0)\n+#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX (MT7530_MIB_COUNTER + 0xa4)\n+#define MT7530_PORT_MIB_RX_BYTES_LOW\t(MT7530_MIB_COUNTER + 0xa8) /* 64 bytes */\n+#define MT7530_PORT_MIB_RX_BYTES_HIGH\t(MT7530_MIB_COUNTER + 0xac)\n+#define MT7530_PORT_MIB_RX_CTRL_DROP\t(MT7530_MIB_COUNTER + 0xb0)\n+#define MT7530_PORT_MIB_RX_INGRESS_DROP (MT7530_MIB_COUNTER + 0xb4)\n+#define MT7530_PORT_MIB_RX_ARL_DROP\t(MT7530_MIB_COUNTER + 0xb8)\n #define MT7530_MIB_CCR\t\t\t0x4fe0\n #define CCR_MIB_ENABLE\t\t\tBIT(31)\n #define CCR_RX_OCT_CNT_GOOD\t\tBIT(7)\n@@ -794,45 +709,6 @@ enum mt7531_xtal_fsel {\n #define REG_GSWCK_EN\t\t\tBIT(0)\n #define REG_TRGMIICK_EN\t\tBIT(1)\n \n-#define MIB_DESC(_s, _o, _n)\t\\\n-\t{\t\t\t\\\n-\t\t.size = (_s),\t\\\n-\t\t.offset = (_o),\t\\\n-\t\t.name = (_n),\t\\\n-\t}\n-\n-struct mt7530_mib_desc {\n-\tunsigned int size;\n-\tunsigned int offset;\n-\tconst char *name;\n-};\n-\n-struct mt7530_fdb {\n-\tu16 vid;\n-\tu8 port_mask;\n-\tu8 aging;\n-\tu8 mac[6];\n-\tbool noarp;\n-};\n-\n-/* struct mt7530_port -\tThis is the main data structure for holding the state\n- *\t\t\tof the port.\n- * @enable:\tThe status used for show port is enabled or not.\n- * @pm:\t\tThe matrix used to show all connections with the port.\n- * @pvid:\tThe VLAN specified is to be considered a PVID at ingress. Any\n- *\t\tuntagged frames will be assigned to the related VLAN.\n- * @sgmii_pcs:\tPointer to PCS instance for SerDes ports\n- * @stats:\tCached port statistics for MDIO-connected switches\n- */\n-struct mt7530_port {\n-\tbool enable;\n-\tbool isolated;\n-\tu32 pm;\n-\tu16 pvid;\n-\tstruct phylink_pcs *sgmii_pcs;\n-\tstruct rtnl_link_stats64 stats;\n-};\n-\n /* Port 5 mode definitions of the MT7530 switch */\n enum mt7530_p5_mode {\n \tGMAC5,\n@@ -864,6 +740,9 @@ struct mt753x_pcs {\n struct mt753x_info {\n \tenum mt753x_id id;\n \n+\tconst struct mt7530_reg_field *reg_fields;\n+\tunsigned int num_reg_fields;\n+\n \tconst struct phylink_pcs_ops *pcs_ops;\n \n \tint (*sw_setup)(struct dsa_switch *ds);\n@@ -921,8 +800,6 @@ struct mt7530_priv {\n \tbool\t\t\tmcm;\n \tenum mt7530_p5_mode\tp5_mode;\n \tbool\t\t\tp5_sgmii;\n-\tu8\t\t\tmirror_rx;\n-\tu8\t\t\tmirror_tx;\n \tstruct mt7530_port\tports[MT7530_NUM_PORTS];\n \tstruct mt753x_pcs\tpcs[MT7530_NUM_PORTS];\n \t/* protect among processes for registers access*/\n@@ -934,24 +811,10 @@ struct mt7530_priv {\n \tspinlock_t stats_lock; /* protects cached stats counters */\n \tstruct delayed_work stats_work;\n \tunsigned long stats_last;\n-};\n \n-struct mt7530_hw_vlan_entry {\n-\tint port;\n-\tu8 old_members;\n-\tbool untagged;\n+\tstruct mt7530_lib_priv lib_priv;\n };\n \n-static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,\n-\t\t\t\t\t int port, bool untagged)\n-{\n-\te-\u003eport = port;\n-\te-\u003euntagged = untagged;\n-}\n-\n-typedef void (*mt7530_vlan_op)(struct mt7530_priv *,\n-\t\t\t struct mt7530_hw_vlan_entry *);\n-\n struct mt7530_hw_stats {\n \tconst char\t*string;\n \tu16\t\treg;\n@@ -960,6 +823,7 @@ struct mt7530_hw_stats {\n \n int mt7530_probe_common(struct mt7530_priv *priv);\n void mt7530_remove_common(struct mt7530_priv *priv);\n+int mt7530_setup_lib_priv(struct mt7530_priv *priv);\n \n extern const struct mt753x_info mt753x_table[];\n \ndiff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig\nindex d3835597e3795..eca2ce135c86b 100644\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -96,6 +96,12 @@ config AIR_AN8801_PHY\n \thelp\n \t Currently supports the Airoha AN8801R PHY.\n \n+config AIR_AN8855_PHY\n+\ttristate \"Airoha AN8855 Internal Gigabit PHY\"\n+\tdepends on NVMEM || !NVMEM\n+\thelp\n+\t Currently supports the internal Airoha AN8855 Switch PHY.\n+\n config AIR_EN8811H_PHY\n \ttristate \"Airoha EN8811H 2.5 Gigabit PHY\"\n \tselect AIR_NET_PHYLIB\ndiff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile\nindex 49575fa185223..b4222c4be4f52 100644\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -31,6 +31,7 @@ obj-$(CONFIG_ADIN_PHY)\t\t+= adin.o\n obj-$(CONFIG_ADIN1100_PHY)\t+= adin1100.o\n obj-$(CONFIG_ADIN1140_PHY)\t+= adin1140-phy.o\n obj-$(CONFIG_AIR_AN8801_PHY)\t+= air_an8801.o\n+obj-$(CONFIG_AIR_AN8855_PHY)\t+= air_an8855.o\n obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o\n obj-$(CONFIG_AIR_NET_PHYLIB)\t+= air_phy_lib.o\n obj-$(CONFIG_AMD_PHY)\t\t+= amd.o\ndiff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c\nnew file mode 100644\nindex 0000000000000..bc22256fd5f95\n--- /dev/null\n+++ b/drivers/net/phy/air_an8855.c\n@@ -0,0 +1,275 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2024 Christian Marangi \u003cansuelsmth@gmail.com\u003e\n+ */\n+\n+#include \u003clinux/bitfield.h\u003e\n+#include \u003clinux/module.h\u003e\n+#include \u003clinux/nvmem-consumer.h\u003e\n+#include \u003clinux/of.h\u003e\n+#include \u003clinux/phy.h\u003e\n+\n+#define AN8855_PHY_SELECT_PAGE\t\t\t0x1f\n+#define AN8855_PHY_PAGE\t\t\tGENMASK(2, 0)\n+#define AN8855_PHY_PAGE_STANDARD\t\tFIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)\n+#define AN8855_PHY_PAGE_EXTENDED_1\t\tFIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)\n+\n+/* MII Registers Page 1 */\n+#define AN8855_PHY_EXT_REG_14\t\t\t0x14\n+#define AN8855_PHY_EN_DOWN_SHIFT\t\tBIT(4)\n+\n+/* R50 Calibration regs in MDIO_MMD_VEND1 */\n+#define AN8855_PHY_R50OHM_RSEL_TX_AB\t\t0x174\n+#define AN8855_PHY_R50OHM_RSEL_TX_A_EN\t\tBIT(15)\n+#define AN8855_PHY_R50OHM_RSEL_TX_A\t\tGENMASK(14, 8)\n+#define AN8855_PHY_R50OHM_RSEL_TX_B_EN\t\tBIT(7)\n+#define AN8855_PHY_R50OHM_RSEL_TX_B\t\tGENMASK(6, 0)\n+#define AN8855_PHY_R50OHM_RSEL_TX_CD\t\t0x175\n+#define AN8855_PHY_R50OHM_RSEL_TX_C_EN\t\tBIT(15)\n+#define AN8855_PHY_R50OHM_RSEL_TX_C\t\tGENMASK(14, 8)\n+#define AN8855_PHY_R50OHM_RSEL_TX_D_EN\t\tBIT(7)\n+#define AN8855_PHY_R50OHM_RSEL_TX_D\t\tGENMASK(6, 0)\n+\n+#define AN8855_SWITCH_EFUSE_R50O\t\tGENMASK(30, 24)\n+\n+/* PHY TX PAIR DELAY SELECT Register */\n+#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE\t\t0x013\n+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE GENMASK(14, 12)\n+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_B_GBE GENMASK(10, 8)\n+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE GENMASK(6, 4)\n+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_D_GBE GENMASK(2, 0)\n+/* PHY ADC Register */\n+#define AN8855_PHY_RXADC_CTRL\t\t\t0x0d8\n+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_A\tBIT(12)\n+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_B\tBIT(8)\n+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_C\tBIT(4)\n+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_D\tBIT(0)\n+#define AN8855_PHY_RXADC_REV_0\t\t\t0x0d9\n+#define AN8855_PHY_RG_AD_RESERVE0_A\t\tGENMASK(15, 8)\n+#define AN8855_PHY_RG_AD_RESERVE0_B\t\tGENMASK(7, 0)\n+#define AN8855_PHY_RXADC_REV_1\t\t\t0x0da\n+#define AN8855_PHY_RG_AD_RESERVE0_C\t\tGENMASK(15, 8)\n+#define AN8855_PHY_RG_AD_RESERVE0_D\t\tGENMASK(7, 0)\n+\n+#define AN8855_PHY_ID\t\t\t\t0xc0ff0410\n+\n+struct air_an8855_priv {\n+\tbool needs_calibration;\n+\tu8 calibration_data[4];\n+};\n+\n+static const u8 dsa_r50ohm_table[] = {\n+\t127, 127, 127, 127, 127, 127, 127, 127, 127, 127,\n+\t127, 127, 127, 127, 127, 127, 127, 126, 122, 117,\n+\t112, 109, 104, 101, 97, 94, 90, 88, 84, 80,\n+\t78, 74, 72, 68, 66, 64, 61, 58, 56, 53,\n+\t51, 48, 47, 44, 42, 40, 38, 36, 34, 32,\n+\t31, 28, 27, 24, 24, 22, 20, 18, 16, 16,\n+\t14, 12, 11, 9\n+};\n+\n+static int an8855_get_r50ohm_val(struct device *dev, const char *calib_name,\n+\t\t\t\t u8 *dest)\n+{\n+\tu32 shift_sel, val;\n+\tint ret;\n+\tint i;\n+\n+\tret = nvmem_cell_read_u32(dev, calib_name, \u0026val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tshift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val);\n+\tfor (i = 0; i \u003c ARRAY_SIZE(dsa_r50ohm_table); i++)\n+\t\tif (dsa_r50ohm_table[i] == shift_sel)\n+\t\t\tbreak;\n+\n+\tif (i \u003c 8 || i \u003e= ARRAY_SIZE(dsa_r50ohm_table))\n+\t\t*dest = dsa_r50ohm_table[25];\n+\telse\n+\t\t*dest = dsa_r50ohm_table[i - 8];\n+\n+\treturn 0;\n+}\n+\n+static int an8855_probe(struct phy_device *phydev)\n+{\n+\tstruct device *dev = \u0026phydev-\u003emdio.dev;\n+\tstruct air_an8855_priv *priv;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv-\u003eneeds_calibration = of_property_present(dev-\u003eof_node,\n+\t\t\t\t\t\t \"nvmem-cells\");\n+\n+\tif (priv-\u003eneeds_calibration) {\n+\t\tint ret;\n+\n+\t\tret = an8855_get_r50ohm_val(dev, \"tx_a\", \u0026priv-\u003ecalibration_data[0]);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = an8855_get_r50ohm_val(dev, \"tx_b\", \u0026priv-\u003ecalibration_data[1]);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = an8855_get_r50ohm_val(dev, \"tx_c\", \u0026priv-\u003ecalibration_data[2]);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = an8855_get_r50ohm_val(dev, \"tx_d\", \u0026priv-\u003ecalibration_data[3]);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tphydev-\u003epriv = priv;\n+\n+\treturn 0;\n+}\n+\n+static int an8855_get_downshift(struct phy_device *phydev, u8 *data)\n+{\n+\tint val;\n+\n+\tval = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);\n+\tif (val \u003c 0)\n+\t\treturn val;\n+\n+\t*data = val \u0026 AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :\n+\t\t\t\t\t\t DOWNSHIFT_DEV_DISABLE;\n+\n+\treturn 0;\n+}\n+\n+static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)\n+{\n+\tu16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;\n+\n+\treturn phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,\n+\t\t\t\tAN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,\n+\t\t\t\tds);\n+}\n+\n+static int an8855_config_init(struct phy_device *phydev)\n+{\n+\tstruct air_an8855_priv *priv = phydev-\u003epriv;\n+\tint ret;\n+\n+\t/* Enable HW auto downshift */\n+\tret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (priv-\u003eneeds_calibration) {\n+\t\tret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_AB,\n+\t\t\t\t AN8855_PHY_R50OHM_RSEL_TX_A_EN | AN8855_PHY_R50OHM_RSEL_TX_A |\n+\t\t\t\t AN8855_PHY_R50OHM_RSEL_TX_B_EN | AN8855_PHY_R50OHM_RSEL_TX_B,\n+\t\t\t\t AN8855_PHY_R50OHM_RSEL_TX_A_EN |\n+\t\t\t\t FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A,\n+\t\t\t\t\t\tpriv-\u003ecalibration_data[0]) |\n+\t\t\t\t AN8855_PHY_R50OHM_RSEL_TX_B_EN |\n+\t\t\t\t FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B,\n+\t\t\t\t\t\tpriv-\u003ecalibration_data[1]));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_CD,\n+\t\t\t\t AN8855_PHY_R50OHM_RSEL_TX_C_EN | AN8855_PHY_R50OHM_RSEL_TX_C |\n+\t\t\t\t AN8855_PHY_R50OHM_RSEL_TX_D_EN | AN8855_PHY_R50OHM_RSEL_TX_D,\n+\t\t\t\t AN8855_PHY_R50OHM_RSEL_TX_C_EN |\n+\t\t\t\t FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C,\n+\t\t\t\t\t\tpriv-\u003ecalibration_data[2]) |\n+\t\t\t\t AN8855_PHY_R50OHM_RSEL_TX_D_EN |\n+\t\t\t\t FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D,\n+\t\t\t\t\t\tpriv-\u003ecalibration_data[3]));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Apply values to reduce signal noise */\n+\tret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,\n+\t\t\t AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE |\n+\t\t\t AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE,\n+\t\t\t FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE, 0x4) |\n+\t\t\t FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE, 0x4));\n+\tif (ret)\n+\t\treturn ret;\n+\tret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL,\n+\t\t\t AN8855_PHY_RG_AD_SAMPLE_PHSEL_A |\n+\t\t\t AN8855_PHY_RG_AD_SAMPLE_PHSEL_C);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0,\n+\t\t\t FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1));\n+\tif (ret)\n+\t\treturn ret;\n+\tret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1,\n+\t\t\t FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int an8855_get_tunable(struct phy_device *phydev,\n+\t\t\t struct ethtool_tunable *tuna, void *data)\n+{\n+\tswitch (tuna-\u003eid) {\n+\tcase ETHTOOL_PHY_DOWNSHIFT:\n+\t\treturn an8855_get_downshift(phydev, data);\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+}\n+\n+static int an8855_set_tunable(struct phy_device *phydev,\n+\t\t\t struct ethtool_tunable *tuna, const void *data)\n+{\n+\tswitch (tuna-\u003eid) {\n+\tcase ETHTOOL_PHY_DOWNSHIFT:\n+\t\treturn an8855_set_downshift(phydev, *(const u8 *)data);\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+}\n+\n+static int an8855_read_page(struct phy_device *phydev)\n+{\n+\treturn __phy_read(phydev, AN8855_PHY_SELECT_PAGE);\n+}\n+\n+static int an8855_write_page(struct phy_device *phydev, int page)\n+{\n+\treturn __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page);\n+}\n+\n+static struct phy_driver an8855_driver[] = {\n+{\n+\tPHY_ID_MATCH_EXACT(AN8855_PHY_ID),\n+\t.name\t\t\t= \"Airoha AN8855 internal PHY\",\n+\t/* PHY_GBIT_FEATURES */\n+\t.flags\t\t\t= PHY_IS_INTERNAL,\n+\t.probe\t\t\t= an8855_probe,\n+\t.config_init\t\t= an8855_config_init,\n+\t.soft_reset\t\t= genphy_soft_reset,\n+\t.get_tunable\t\t= an8855_get_tunable,\n+\t.set_tunable\t\t= an8855_set_tunable,\n+\t.suspend\t\t= genphy_suspend,\n+\t.resume\t\t\t= genphy_resume,\n+\t.read_page\t\t= an8855_read_page,\n+\t.write_page\t\t= an8855_write_page,\n+}, };\n+\n+module_phy_driver(an8855_driver);\n+\n+static struct mdio_device_id __maybe_unused an8855_tbl[] = {\n+\t{ PHY_ID_MATCH_EXACT(AN8855_PHY_ID) },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(mdio, an8855_tbl);\n+\n+MODULE_DESCRIPTION(\"Airoha AN8855 PHY driver\");\n+MODULE_AUTHOR(\"Christian Marangi \u003cansuelsmth@gmail.com\u003e\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/include/net/dsa.h b/include/net/dsa.h\nindex 7507d632e7c6d..c5659e9ab6d35 100644\n--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -61,6 +61,7 @@ struct tc_action;\n #define DSA_TAG_PROTO_NETC_VALUE\t\t33\n #define DSA_TAG_PROTO_KSZ8463_VALUE\t\t34\n #define DSA_TAG_PROTO_MT7628_VALUE\t\t35\n+#define DSA_TAG_PROTO_AIROHA_VALUE\t\t36\n \n enum dsa_tag_protocol {\n \tDSA_TAG_PROTO_NONE\t\t= DSA_TAG_PROTO_NONE_VALUE,\n@@ -75,6 +76,7 @@ enum dsa_tag_protocol {\n \tDSA_TAG_PROTO_KSZ9893\t\t= DSA_TAG_PROTO_KSZ9893_VALUE,\n \tDSA_TAG_PROTO_LAN9303\t\t= DSA_TAG_PROTO_LAN9303_VALUE,\n \tDSA_TAG_PROTO_MTK\t\t= DSA_TAG_PROTO_MTK_VALUE,\n+\tDSA_TAG_PROTO_AIROHA\t\t= DSA_TAG_PROTO_AIROHA_VALUE,\n \tDSA_TAG_PROTO_QCA\t\t= DSA_TAG_PROTO_QCA_VALUE,\n \tDSA_TAG_PROTO_TRAILER\t\t= DSA_TAG_PROTO_TRAILER_VALUE,\n \tDSA_TAG_PROTO_8021Q\t\t= DSA_TAG_PROTO_8021Q_VALUE,\ndiff --git a/net/dsa/Kconfig b/net/dsa/Kconfig\nindex 23b4b74004ed5..07ad0f13416ed 100644\n--- a/net/dsa/Kconfig\n+++ b/net/dsa/Kconfig\n@@ -24,6 +24,13 @@ config NET_DSA_TAG_NONE\n \t Say Y or M if you want to enable support for switches which don't tag\n \t frames over the CPU port.\n \n+config NET_DSA_TAG_AIROHA\n+\ttristate \"Tag driver for Airoha switches\"\n+\tselect NET_DSA_TAG_MTK_COMMON\n+\thelp\n+\t Say Y or M if you want to enable support for tagging frames for\n+\t Airoha switches.\n+\n config NET_DSA_TAG_AR9331\n \ttristate \"Tag driver for Atheros AR9331 SoC with built-in switch\"\n \thelp\n@@ -104,8 +111,12 @@ config NET_DSA_TAG_MT7628\n \t Say Y or M if you want to enable support for tagging frames for the\n \t switch embedded in the MT7628 SoC.\n \n+config NET_DSA_TAG_MTK_COMMON\n+\ttristate\n+\n config NET_DSA_TAG_MTK\n \ttristate \"Tag driver for Mediatek switches\"\n+\tselect NET_DSA_TAG_MTK_COMMON\n \thelp\n \t Say Y or M if you want to enable support for tagging frames for\n \t Mediatek switches.\ndiff --git a/net/dsa/Makefile b/net/dsa/Makefile\nindex d15bcf5c68f02..57739a488a6a3 100644\n--- a/net/dsa/Makefile\n+++ b/net/dsa/Makefile\n@@ -28,7 +28,7 @@ obj-$(CONFIG_NET_DSA_TAG_HELLCREEK) += tag_hellcreek.o\n obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o\n obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o\n obj-$(CONFIG_NET_DSA_TAG_MT7628) += tag_mt7628.o\n-obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o\n+obj-$(CONFIG_NET_DSA_TAG_MTK_COMMON) += tag_mtk.o\n obj-$(CONFIG_NET_DSA_TAG_MXL_862XX) += tag_mxl862xx.o\n obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o\n obj-$(CONFIG_NET_DSA_TAG_NETC) += tag_netc.o\ndiff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c\nindex c7dc7731675ec..f8087d768da6d 100644\n--- a/net/dsa/tag_mtk.c\n+++ b/net/dsa/tag_mtk.c\n@@ -11,6 +11,7 @@\n #include \"tag.h\"\n \n #define MTK_NAME\t\t\"mtk\"\n+#define AIROHA_NAME\t\t\"airoha\"\n \n #define MTK_HDR_LEN\t\t4\n #define MTK_HDR_XMIT_UNTAGGED\t\t0\n@@ -18,6 +19,9 @@\n #define MTK_HDR_XMIT_TAGGED_TPID_88A8\t2\n #define MTK_HDR_RECV_SOURCE_PORT_MASK\tGENMASK(2, 0)\n #define MTK_HDR_XMIT_DP_BIT_MASK\tGENMASK(5, 0)\n+/* AN8855 doesn't support SA_DIS and Leaky VLAN\n+ * control in tag as these bits doesn't exist.\n+ */\n #define MTK_HDR_XMIT_SA_DIS\t\tBIT(6)\n \n static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,\n@@ -99,6 +103,7 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, struct net_device *dev)\n \treturn skb;\n }\n \n+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)\n static const struct dsa_device_ops mtk_netdev_ops = {\n \t.name\t\t= MTK_NAME,\n \t.proto\t\t= DSA_TAG_PROTO_MTK,\n@@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops = {\n \t.needed_headroom = MTK_HDR_LEN,\n };\n \n-MODULE_DESCRIPTION(\"DSA tag driver for Mediatek switches\");\n-MODULE_LICENSE(\"GPL\");\n+DSA_TAG_DRIVER(mtk_netdev_ops);\n MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);\n+#endif\n \n-module_dsa_tag_driver(mtk_netdev_ops);\n+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)\n+static const struct dsa_device_ops airoha_netdev_ops = {\n+\t.name\t\t= AIROHA_NAME,\n+\t.proto\t\t= DSA_TAG_PROTO_AIROHA,\n+\t.xmit\t\t= mtk_tag_xmit,\n+\t.rcv\t\t= mtk_tag_rcv,\n+\t.needed_headroom = MTK_HDR_LEN,\n+};\n+\n+DSA_TAG_DRIVER(airoha_netdev_ops);\n+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);\n+#endif\n+\n+static struct dsa_tag_driver *dsa_tag_driver_array[] =\t{\n+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)\n+\t\u0026DSA_TAG_DRIVER_NAME(mtk_netdev_ops),\n+#endif\n+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)\n+\t\u0026DSA_TAG_DRIVER_NAME(airoha_netdev_ops),\n+#endif\n+};\n+\n+module_dsa_tag_drivers(dsa_tag_driver_array);\n+\n+MODULE_DESCRIPTION(\"DSA tag driver for Mediatek switches\");\n+MODULE_LICENSE(\"GPL\");\n"
} |
| 2/1 | 2026/09/15 16:36 | agent | patch-evaluator |
3mModel:core Args: null Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch series introduces driver support for the Airoha AN8855 Switch SoC (including MFD core over MDIO, internal PHY, and DSA switch platform driver) and refactors the MediaTek MT7530 DSA switch driver into a shared library (mt7530-lib.c). These drivers target physical network switch and PHY ASICs used on embedded networking hardware (probed via MDIO and Device Tree) which are not emulated in standard virtualized environments (QEMU/KVM or GCE). Consequently, the modified executable code is structurally unreachable for fuzzing.",
"WorthFuzzing": false
}Instruction: You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.
IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.
================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.
- REACHABILITY IS THE PRIMARY GATE:
Fuzzing can only discover bugs in code that can actually execute in standard virtualized
environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
regardless of whether it adds assertions or complex logic.
- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
Patch authors routinely label changes as "cleanups", "refactorings", or state
"No functional change intended". Do NOT take these claims at face value.
Code refactorings that rearrange logic, introduce helper functions, or alter state management
in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
If reachable executable code is modified or refactored, it MUST be fuzzed.
- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
Even if the author believes the invariant always holds, fuzzing is essential to verify whether
an unusual sequence of operations can violate it.
================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:
- Non-kernel and non-executable changes:
* Modifications to Documentation/, comments, or spelling fixes.
* User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
that do not affect the compiled kernel image (vmlinux) or kernel modules.
* Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
that do not alter control flow or data structures.
* Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
* Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
* Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
physical PCI hot-unplug or manual sysfs driver unbinding.
* Code paths exclusive to architectures other than the target architecture.
================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
* Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
* Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
* Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
* Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).
================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:
- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
Do NOT list generic, ubiquitous functions called by almost every program in the corpus
(including, but not limited to: general memory allocators and deallocators, page fault
and trap handlers, or core synchronization primitives; this is not an exhaustive list).
Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
which severely dilutes fuzzing effort away from the actual changes.
- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
List functions that specifically implement the logic being added or altered, or direct API entrypoints
for the subsystem feature under review.
- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).
================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.
Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.
Prompt: Target architecture: amd64
For your convenience, here is the diff of the changes:
commit 9c831e43060ed04707e416562042cde176308d6d
Author: syz-cluster <triage@syzkaller.com>
Date: Tue Sep 15 16:36:38 2026 +0000
syz-cluster: applied patch under review
diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
new file mode 100644
index 0000000000000..48127e956c965
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch SoC
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 Switch is a SoC that expose various peripherals like an
+ Ethernet Switch, a NVMEM provider and Ethernet PHYs.
+
+ It does also support i2c and timers but those are not currently
+ supported/used.
+
+properties:
+ compatible:
+ const: airoha,an8855
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ efuse:
+ type: object
+ $ref: /schemas/nvmem/airoha,an8855-efuse.yaml
+ description: EFUSE exposed by the Airoha AN8855 SoC
+
+ ethernet-switch:
+ type: object
+ $ref: /schemas/net/dsa/airoha,an8855-switch.yaml
+ description: Switch exposed by the Airoha AN8855 SoC
+
+ mdio:
+ type: object
+ $ref: /schemas/net/mdio.yaml#
+ description: MDIO exposed by the Airoha AN8855 SoC
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - mdio
+ - ethernet-switch
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ soc@1 {
+ compatible = "airoha,an8855";
+ reg = <1>;
+
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ efuse {
+ compatible = "airoha,an8855-efuse";
+
+ #nvmem-cell-cells = <0>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
+ reg = <0xc 0x4>;
+ };
+
+ shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
+ reg = <0x10 0x4>;
+ };
+
+ shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
+ reg = <0x14 0x4>;
+ };
+
+ shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
+ reg = <0x18 0x4>;
+ };
+
+ shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
+ reg = <0x1c 0x4>;
+ };
+
+ shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
+ reg = <0x20 0x4>;
+ };
+
+ shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
+ reg = <0x24 0x4>;
+ };
+
+ shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
+ reg = <0x28 0x4>;
+ };
+ };
+ };
+
+ ethernet-switch {
+ compatible = "airoha,an8855-switch";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy1>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy2>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ nvmem-cells = <&shift_sel_port0_tx_a>,
+ <&shift_sel_port0_tx_b>,
+ <&shift_sel_port0_tx_c>,
+ <&shift_sel_port0_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+
+ internal_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+
+ nvmem-cells = <&shift_sel_port1_tx_a>,
+ <&shift_sel_port1_tx_b>,
+ <&shift_sel_port1_tx_c>,
+ <&shift_sel_port1_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
new file mode 100644
index 0000000000000..d2f86116badf4
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8855-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch Internal PHY
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal
+ PHYs on the MDIO bus.
+
+ Each PHY might need to be calibrated to correctly work with the
+ use of the eFUSE provided by the Switch SoC.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-idc0ff.0410
+ required:
+ - compatible
+
+properties:
+ reg:
+ maxItems: 1
+
+ nvmem-cells:
+ items:
+ - description: phandle to SoC eFUSE tx_a
+ - description: phandle to SoC eFUSE tx_b
+ - description: phandle to SoC eFUSE tx_c
+ - description: phandle to SoC eFUSE tx_d
+
+ nvmem-cell-names:
+ items:
+ - const: tx_a
+ - const: tx_b
+ - const: tx_c
+ - const: tx_d
+
+required:
+ - compatible
+ - reg
+
+dependentRequired:
+ nvmem-cells: [ nvmem-cell-names ]
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c45";
+
+ reg = <1>;
+ };
+
+ ethernet-phy@2 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c45";
+
+ reg = <2>;
+
+ nvmem-cells = <&shift_sel_port0_tx_a>,
+ <&shift_sel_port0_tx_b>,
+ <&shift_sel_port0_tx_c>,
+ <&shift_sel_port0_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
new file mode 100644
index 0000000000000..5ad9b9e139831
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Gigabit Switch
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 is a 5-port Gigabit Switch.
+
+ It does expose the 5 Internal PHYs on the MDIO bus and each port
+ can access the Switch register space by configuring the PHY page.
+
+$ref: dsa.yaml#/$defs/ethernet-ports
+
+properties:
+ compatible:
+ const: airoha,an8855-switch
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ ethernet-switch {
+ compatible = "airoha,an8855-switch";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy1>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy2>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy3>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy4>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy5>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 0e04d92d1b098..afe9d363ddf4a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -759,6 +759,22 @@ S: Maintained
F: Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
F: drivers/net/ethernet/airoha/
+AIROHA AN8855 DSA DRIVER
+M: Christian Marangi <ansuelsmth@gmail.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
+F: Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
+F: Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
+F: Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
+F: drivers/mfd/airoha-an8855.c
+F: drivers/net/dsa/an8855.c
+F: drivers/net/dsa/an8855.h
+F: drivers/net/phy/air_an8855.c
+F: drivers/nvmem/an8855-efuse.c
+
AIROHA PCIE PHY DRIVER
M: Lorenzo Bianconi <lorenzo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index e4fd4572472f9..afbdcec0fce8f 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR
using regmap_mmio accesses for ARM32 parts and SMC calls to
EL3 for ARM64 parts.
+config MFD_AIROHA_AN8855
+ tristate "Airoha AN8855 Switch Core"
+ select MFD_CORE
+ select REGMAP
+ select PHYLIB
+ select MDIO_REGMAP
+ depends on NETDEVICES && OF
+ help
+ Support for the Airoha AN8855 Switch Core. This is an SoC
+ that provides various peripherals, to count, i2c, an Ethrnet
+ Switch, a CPU timer, GPIO, eFUSE.
+
+ Currently it provides a DSA switch and a NVMEM provider.
+
config MFD_ACT8945A
tristate "Active-semi ACT8945A"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 72d3944b0ad8e..484127dba2ad7 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o
+obj-$(CONFIG_MFD_AIROHA_AN8855) += airoha-an8855.o
obj-$(CONFIG_MFD_ACT8945A) += act8945a.o
obj-$(CONFIG_MFD_SM501) += sm501.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o
diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c
new file mode 100644
index 0000000000000..2b3b5f4a5a21e
--- /dev/null
+++ b/drivers/mfd/airoha-an8855.c
@@ -0,0 +1,557 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Core driver for Airoha AN8855 Switch
+ *
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/fwnode_mdio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mfd/core.h>
+#include <linux/mdio.h>
+#include <linux/mdio/mdio-regmap.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+
+/* Register for HW trap status */
+#define AN8855_HWTRAP 0x1000009c
+
+/*
+ * Register of the Switch ID
+ * (called Project ID in Documentation)
+ */
+#define AN8855_CREV 0x10005000
+#define AN8855_ID 0x8855 /* Switch ID */
+
+/* Register for GPHY Power Down
+ * Used to Toggle the Gigabit PHY power and enable them.
+ */
+#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
+
+/* MII Registers */
+#define AN8855_PHY_SELECT_PAGE 0x1f
+#define AN8855_PHY_PAGE GENMASK(2, 0)
+#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
+
+/* MII Registers Page 4 */
+#define AN8855_PBUS_MODE 0x10
+#define AN8855_PBUS_MODE_ADDR_FIXED 0x0
+#define AN8855_PBUS_MODE_ADDR_INCR BIT(15)
+#define AN8855_PBUS_WR_ADDR_HIGH 0x11
+#define AN8855_PBUS_WR_ADDR_LOW 0x12
+#define AN8855_PBUS_WR_DATA_HIGH 0x13
+#define AN8855_PBUS_WR_DATA_LOW 0x14
+#define AN8855_PBUS_RD_ADDR_HIGH 0x15
+#define AN8855_PBUS_RD_ADDR_LOW 0x16
+#define AN8855_PBUS_RD_DATA_HIGH 0x17
+#define AN8855_PBUS_RD_DATA_LOW 0x18
+
+#define AN8855_MAX_PHY_PORT 5
+
+struct an8855_core_priv {
+ struct mii_bus *bus;
+ struct mii_bus *phy_bus;
+ unsigned int switch_addr;
+ u16 current_page;
+};
+
+struct an8855_phy_priv {
+ u8 addr;
+ struct an8855_core_priv *core;
+};
+
+struct an8855_phy_bus {
+ struct mii_bus *bus;
+ struct fwnode_handle *node;
+ u8 addr;
+};
+
+static const struct mfd_cell an8855_cells[] = {
+ MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0,
+ "airoha,an8855-efuse"),
+ MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0,
+ "airoha,an8855-switch"),
+};
+
+static int an8855_mii_set_page(struct an8855_core_priv *priv, u8 addr,
+ u8 page) __must_hold(&priv->bus->mdio_lock)
+{
+ struct mii_bus *bus = priv->bus;
+ int ret;
+
+ ret = __mdiobus_write(bus, addr, AN8855_PHY_SELECT_PAGE, page);
+ if (ret) {
+ dev_err_ratelimited(&bus->dev, "failed to set mii page\n");
+ return ret;
+ }
+
+ /* Cache current page if next MII read/write is for Switch page */
+ priv->current_page = page;
+ return 0;
+}
+
+static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,
+ u32 *val) __must_hold(&bus->mdio_lock)
+{
+ int lo, hi, ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+ AN8855_PBUS_MODE_ADDR_FIXED);
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,
+ upper_16_bits(reg));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,
+ lower_16_bits(reg));
+ if (ret)
+ goto err;
+
+ hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);
+ if (hi < 0) {
+ ret = hi;
+ goto err;
+ }
+
+ lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);
+ if (lo < 0) {
+ ret = lo;
+ goto err;
+ }
+
+ *val = ((u32)hi << 16) | lo;
+
+ return 0;
+err:
+ dev_err_ratelimited(&bus->dev, "failed to read register\n");
+ return ret;
+}
+
+/*
+ * Protect concurrent access to phy page if switch address also
+ * expose a PHY.
+ */
+static void an8855_regmap_lock(struct an8855_core_priv *priv)
+{
+ if (priv->phy_bus)
+ mutex_lock(&priv->phy_bus->mdio_lock);
+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+}
+
+static void an8855_regmap_unlock(struct an8855_core_priv *priv)
+{
+ mutex_unlock(&priv->bus->mdio_lock);
+ if (priv->phy_bus)
+ mutex_unlock(&priv->phy_bus->mdio_lock);
+}
+
+static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct an8855_core_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret < 0)
+ goto exit;
+
+ ret = an8855_mii_read32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,
+ u32 val) __must_hold(&bus->mdio_lock)
+{
+ int ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+ AN8855_PBUS_MODE_ADDR_FIXED);
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,
+ upper_16_bits(reg));
+ if (ret)
+ goto err;
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,
+ lower_16_bits(reg));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,
+ upper_16_bits(val));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,
+ lower_16_bits(val));
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ dev_err_ratelimited(&bus->dev,
+ "failed to write an8855 register\n");
+ return ret;
+}
+
+static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)
+{
+ struct an8855_core_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret)
+ goto exit;
+
+ ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,
+ uint32_t write_val)
+{
+ struct an8855_core_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ u32 val;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret)
+ goto exit;
+
+ ret = an8855_mii_read32(bus, addr, reg, &val);
+ if (ret < 0)
+ goto exit;
+
+ val &= ~mask;
+ val |= write_val & mask;
+ ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static const struct regmap_range an8855_readable_ranges[] = {
+ regmap_reg_range(0x10000000, 0x10000fff), /* SCU */
+ regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */
+ regmap_reg_range(0x10002000, 0x10002fff), /* MCU */
+ regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */
+ regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */
+ regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */
+ regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
+ regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
+ regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
+ regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */
+ regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */
+ regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */
+ regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */
+ regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */
+ regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */
+ regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */
+ regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */
+ regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */
+ regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */
+ regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */
+ regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */
+ regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */
+ regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */
+ regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */
+ regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */
+ regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */
+ regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */
+};
+
+static const struct regmap_access_table an8855_readable_table = {
+ .yes_ranges = an8855_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),
+};
+
+static const struct regmap_config an8855_regmap_config = {
+ .name = "switch",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0xbfffffff,
+ .reg_read = an8855_regmap_read,
+ .reg_write = an8855_regmap_write,
+ .reg_update_bits = an8855_regmap_update_bits,
+ .disable_locking = true,
+ .rd_table = &an8855_readable_table,
+};
+
+static int an8855_regmap_phy_reset_page(struct an8855_core_priv *priv,
+ int phy) __must_hold(&priv->bus->mdio_lock)
+{
+ /* Check PHY page only for addr shared with switch */
+ if (phy != priv->switch_addr)
+ return 0;
+
+ /* Don't restore page if it's not set to Switch page */
+ if (priv->current_page != AN8855_PHY_PAGE_EXTENDED_4)
+ return 0;
+
+ /*
+ * Restore page to 0, PHY might change page right after but that
+ * will be ignored as it won't be a switch page.
+ */
+ return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
+}
+
+static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct an8855_phy_priv *priv = ctx;
+ struct an8855_core_priv *core_priv;
+ u32 addr = priv->addr;
+ struct mii_bus *bus;
+ int ret;
+
+ core_priv = priv->core;
+ bus = core_priv->bus;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_regmap_phy_reset_page(core_priv, addr);
+ if (ret)
+ goto exit;
+
+ ret = __mdiobus_read(bus, addr, reg);
+ if (ret >= 0)
+ *val = ret;
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val)
+{
+ struct an8855_phy_priv *priv = ctx;
+ struct an8855_core_priv *core_priv;
+ u32 addr = priv->addr;
+ struct mii_bus *bus;
+ int ret;
+
+ core_priv = priv->core;
+ bus = core_priv->bus;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_regmap_phy_reset_page(core_priv, addr);
+ if (ret)
+ goto exit;
+
+ ret = __mdiobus_write(bus, addr, reg, val);
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret;
+}
+
+static const struct regmap_config an8855_phy_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 16,
+ .reg_read = an8855_regmap_phy_read,
+ .reg_write = an8855_regmap_phy_write,
+ .disable_locking = true,
+ .max_register = 0x1f,
+};
+
+static int an8855_read_switch_id(struct device *dev, struct regmap *regmap)
+{
+ u32 id;
+ int ret;
+
+ ret = regmap_read(regmap, AN8855_CREV, &id);
+ if (ret)
+ return ret;
+
+ if (id != AN8855_ID) {
+ dev_err(dev, "Detected Switch ID %x but %x was expected\n",
+ id, AN8855_ID);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int an8855_phy_bus_register(struct device *dev, struct an8855_core_priv *priv,
+ struct device_node *phy_np,
+ struct an8855_phy_bus *phy_bus_info)
+{
+ struct mdio_regmap_config mrc = { };
+ struct an8855_phy_priv *phy_priv;
+ struct regmap *regmap;
+ u32 addr, phy_offset;
+ struct mii_bus *bus;
+ int ret;
+
+ ret = of_property_read_u32(phy_np, "reg", &addr);
+ if (ret)
+ return ret;
+
+ phy_offset = addr - priv->switch_addr;
+ if (phy_offset >= AN8855_MAX_PHY_PORT)
+ return -EINVAL;
+
+ phy_priv = devm_kzalloc(dev, sizeof(*phy_priv), GFP_KERNEL);
+ if (!phy_priv)
+ return -ENOMEM;
+
+ phy_priv->addr = addr;
+ phy_priv->core = priv;
+
+ regmap = devm_regmap_init(dev, NULL, phy_priv, &an8855_phy_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "phy%d regmap initialization failed\n",
+ addr);
+
+ mrc.regmap = regmap;
+ mrc.parent = dev;
+ mrc.valid_addr = addr;
+ snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-phy%d", priv->bus->id, addr);
+
+ bus = devm_mdio_regmap_register(dev, &mrc);
+ if (IS_ERR(bus))
+ return PTR_ERR(bus);
+
+ if (addr == priv->switch_addr)
+ priv->phy_bus = bus;
+
+ phy_bus_info->bus = bus;
+ phy_bus_info->addr = addr;
+ phy_bus_info->node = of_fwnode_handle(phy_np);
+
+ return 0;
+}
+
+static int an8855_mdio_register(struct device *dev, struct an8855_core_priv *priv,
+ struct an8855_phy_bus *phy_bus_infos)
+{
+ struct device_node *mdio_np;
+ int ret = 0;
+ int i = 0;
+
+ mdio_np = of_get_child_by_name(dev->of_node, "mdio");
+ if (!mdio_np)
+ return -ENODEV;
+
+ for_each_available_child_of_node_scoped(mdio_np, phy_np) {
+ if (i >= AN8855_MAX_PHY_PORT)
+ return -EINVAL;
+
+ ret = an8855_phy_bus_register(dev, priv, phy_np,
+ &phy_bus_infos[i]);
+ if (ret)
+ break;
+
+ i++;
+ }
+
+ of_node_put(mdio_np);
+ return ret ? ret : i;
+}
+
+static int an8855_core_probe(struct mdio_device *mdiodev)
+{
+ struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { };
+ struct device *dev = &mdiodev->dev;
+ struct an8855_core_priv *priv;
+ struct regmap *regmap;
+ int num_phys;
+ int i, ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->bus = mdiodev->bus;
+ priv->switch_addr = mdiodev->addr;
+ /* No DMA for mdiobus, mute warning for DMA mask not set */
+ dev->dma_mask = &dev->coherent_dma_mask;
+
+ /* Register virtual MDIO for each PHY */
+ num_phys = an8855_mdio_register(dev, priv, phy_bus_infos);
+ if (num_phys < 0)
+ return num_phys;
+
+ regmap = devm_regmap_init(dev, NULL, priv, &an8855_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "regmap initialization failed\n");
+
+ /* Reset PHY page for switch address */
+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_mii_set_page(priv, priv->switch_addr,
+ AN8855_PHY_PAGE_STANDARD);
+ mutex_unlock(&priv->bus->mdio_lock);
+ if (ret)
+ return ret;
+
+ ret = an8855_read_switch_id(dev, regmap);
+ if (ret)
+ return ret;
+
+ /* Release global PHY power down */
+ ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
+ if (ret)
+ return ret;
+
+ /* Register PHYs */
+ for (i = 0; i < num_phys; i++) {
+ ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,
+ phy_bus_infos[i].node,
+ phy_bus_infos[i].addr);
+ if (ret)
+ return ret;
+ }
+
+ return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,
+ ARRAY_SIZE(an8855_cells), NULL, 0,
+ NULL);
+}
+
+static const struct of_device_id an8855_core_of_match[] = {
+ { .compatible = "airoha,an8855" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_core_of_match);
+
+static struct mdio_driver an8855_core_driver = {
+ .probe = an8855_core_probe,
+ .mdiodrv.driver = {
+ .name = "an8855",
+ .of_match_table = an8855_core_of_match,
+ },
+};
+mdio_module_driver(an8855_core_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 8d8edcf89f107..161331535061e 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -24,12 +24,25 @@ config NET_DSA_LOOP
This enables support for a fake mock-up switch chip which
exercises the DSA APIs.
+config NET_DSA_AN8855
+ tristate "Airoha AN8855 Ethernet switch support"
+ depends on MFD_AIROHA_AN8855 || COMPILE_TEST
+ depends on NET_DSA
+ select NET_DSA_TAG_AIROHA
+ help
+ This enables support for the Ethernet switch inside the
+ Airoha AN8855 chip.
+
source "drivers/net/dsa/hirschmann/Kconfig"
source "drivers/net/dsa/lantiq/Kconfig"
+config NET_DSA_MT7530_LIB
+ tristate
+
config NET_DSA_MT7530
tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
+ select NET_DSA_MT7530_LIB
select NET_DSA_TAG_MTK
select REGMAP_IRQ
imply NET_DSA_MT7530_MDIO
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index df849cd0e640e..9ec109da3c414 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -1,9 +1,11 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_NET_DSA_AN8855) += an8855.o
obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm-sf2.o
bcm-sf2-objs := bcm_sf2.o bcm_sf2_cfp.o
obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o
obj-$(CONFIG_NET_DSA_KS8995) += ks8995.o
obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
+obj-$(CONFIG_NET_DSA_MT7530_LIB) += mt7530-lib.o
obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o
diff --git a/drivers/net/dsa/an8855.c b/drivers/net/dsa/an8855.c
new file mode 100644
index 0000000000000..e3cd4bd80c6aa
--- /dev/null
+++ b/drivers/net/dsa/an8855.c
@@ -0,0 +1,1740 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Airoha AN8855 DSA Switch driver
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/bitfield.h>
+#include <linux/ethtool.h>
+#include <linux/etherdevice.h>
+#include <linux/if_bridge.h>
+#include <linux/iopoll.h>
+#include <linux/netdevice.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <net/dsa.h>
+
+#include "an8855.h"
+#include "mt7530-lib.h"
+
+static const struct mt7530_reg_field an8855_fields[] = {
+ { MT7530_BC_FFP, REG_FIELD(AN8855_BCF, 0, 7) },
+ { MT7530_UNM_FFP, REG_FIELD(AN8855_UNMF, 0, 7) },
+ { MT7530_UNU_FFP, REG_FIELD(AN8855_UNUF, 0, 7) },
+
+ { MT7530_CCR_MIB_ENABLE, REG_FIELD(AN8855_MIB_CCR, 31, 31) },
+ { MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 7, 7) },
+ { MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 6, 6) },
+ { MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 5, 5) },
+ { MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 4, 4) },
+
+ { MT7530_BPDU_EG_TAG, REG_FIELD(AN8855_BPC, 9, 11) },
+ { MT7530_BPDU_PORT_FW, REG_FIELD(AN8855_BPC, 0, 2) },
+ { MT7530_PAE_BPDU_FR, REG_FIELD(AN8855_PAC, 28, 28) },
+ { MT7530_PAE_EG_TAG, REG_FIELD(AN8855_PAC, 25, 27) },
+ { MT7530_PAE_PORT_FW, REG_FIELD(AN8855_PAC, 16, 18) },
+ { MT7530_R01_BPDU_FR, REG_FIELD(AN8855_RGAC1, 12, 12) },
+ { MT7530_R01_EG_TAG, REG_FIELD(AN8855_RGAC1, 9, 11) },
+ { MT7530_R01_PORT_FW, REG_FIELD(AN8855_RGAC1, 0, 2) },
+ { MT7530_R02_BPDU_FR, REG_FIELD(AN8855_RGAC1, 28, 28) },
+ { MT7530_R02_EG_TAG, REG_FIELD(AN8855_RGAC1, 25, 27) },
+ { MT7530_R02_PORT_FW, REG_FIELD(AN8855_RGAC1, 16, 18) },
+ { MT7530_R03_BPDU_FR, REG_FIELD(AN8855_RGAC2, 12, 12) },
+ { MT7530_R03_EG_TAG, REG_FIELD(AN8855_RGAC2, 9, 11) },
+ { MT7530_R03_PORT_FW, REG_FIELD(AN8855_RGAC2, 0, 2) },
+ { MT7530_R0E_BPDU_FR, REG_FIELD(AN8855_RGAC2, 28, 28) },
+ { MT7530_R0E_EG_TAG, REG_FIELD(AN8855_RGAC2, 25, 27) },
+ { MT7530_R0E_PORT_FW, REG_FIELD(AN8855_RGAC2, 16, 18) },
+
+ { MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) },
+ { MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) },
+ { MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) },
+ { MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) },
+ { MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) },
+ { MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) },
+ { __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) },
+
+ { MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) },
+ { __MT7530_VAWD2, REG_FIELD(AN8855_VAWD1, 0, 31) },
+
+ { MT7530_VTCR_BUSY, REG_FIELD(AN8855_VTCR, 31, 31) },
+ { MT7530_VTCR_FUNC, REG_FIELD(AN8855_VTCR, 12, 15) },
+ { MT7530_VTCR_VID, REG_FIELD(AN8855_VTCR, 0, 11) },
+
+ { MT7530_ATWD_CVID, REG_FIELD(AN8855_ATWD, 16, 27), },
+ { MT7530_ATWD_IVL, REG_FIELD(AN8855_ATWD, 15, 15), },
+ { MT7530_ATWD_FID, REG_FIELD(AN8855_ATWD, 28, 31), },
+ { MT7530_ATWD_AGE_TIMER, REG_FIELD(AN8855_ATA2, 0, 8), },
+ { MT7530_ATWD_PORT_MAP, REG_FIELD(AN8855_ATWD2, 0, 7), },
+ { AN8855_ATWD_TYPE, REG_FIELD(AN8855_ATA2, 9, 9), },
+ { AN8855_ATWD_VLD, REG_FIELD(AN8855_ATWD, 0, 0), },
+ { MT7530_ATWD_MAC_BYTE_5, REG_FIELD(AN8855_ATA2, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_4, REG_FIELD(AN8855_ATA2, 24, 31), },
+ { MT7530_ATWD_MAC_BYTE_3, REG_FIELD(AN8855_ATA1, 0, 7), },
+ { MT7530_ATWD_MAC_BYTE_2, REG_FIELD(AN8855_ATA1, 8, 15), },
+ { MT7530_ATWD_MAC_BYTE_1, REG_FIELD(AN8855_ATA1, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_0, REG_FIELD(AN8855_ATA1, 24, 31), },
+
+ { __MT7530_ATWD1, REG_FIELD(AN8855_ATWD, 0, 31), },
+ { __MT7530_ATWD2, REG_FIELD(AN8855_ATWD2, 0, 31), },
+ { __MT7530_ATWD3, REG_FIELD(AN8855_ATA1, 0, 31), },
+ { __MT7530_ATWD4, REG_FIELD(AN8855_ATA2, 0, 31), },
+
+ { MT7530_ATRD_CVID, REG_FIELD(AN8855_ATRD0, 10, 21), },
+ { MT7530_ATRD_AGE_TIMER, REG_FIELD(AN8855_ATRD1, 3, 11), },
+ { MT7530_ATRD_PORT_MAP, REG_FIELD(AN8855_ATRD3, 0, 7), },
+ { AN8855_ATRD_ARP, REG_FIELD(AN8855_ATRD0, 1, 2), },
+ { MT7530_ATRD_MAC_BYTE_5, REG_FIELD(AN8855_ATRD1, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_4, REG_FIELD(AN8855_ATRD1, 24, 31), },
+ { MT7530_ATRD_MAC_BYTE_3, REG_FIELD(AN8855_ATRD2, 0, 7), },
+ { MT7530_ATRD_MAC_BYTE_2, REG_FIELD(AN8855_ATRD2, 8, 15), },
+ { MT7530_ATRD_MAC_BYTE_1, REG_FIELD(AN8855_ATRD2, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_0, REG_FIELD(AN8855_ATRD2, 24, 31), },
+
+ { MT7530_ATC_BUSY, REG_FIELD(AN8855_ATC, 31, 31), },
+ { MT7530_ATC_MAT, REG_FIELD(AN8855_ATC, 7, 11), },
+ { MT7530_ATC_CMD, REG_FIELD(AN8855_ATC, 0, 2), },
+ { __MT7530_ATC, REG_FIELD(AN8855_ATC, 0, 31), },
+
+ { MT7530_MIRROR_EN, REG_FIELD(AN8855_MIR, 7, 7) },
+ { MT7530_MIRROR_PORT, REG_FIELD(AN8855_MIR, 0, 4) },
+
+ { MT7530_SSP_FID_PST, REG_FIELD_ID(AN8855_SSP, 0, 15, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(AN8855_PCR, 20, 20, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(AN8855_PCR, 16, 16, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PCR_PORT_VLAN, REG_FIELD_ID(AN8855_PCR, 0, 1, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PCR_MATRIX, REG_FIELD_ID(AN8855_PORTMATRIX, 0, 5, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PSC_SA_DIS, REG_FIELD_ID(AN8855_PSC, 4, 4, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PVC_EG_TAG, REG_FIELD_ID(AN8855_PVC, 8, 10, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(AN8855_PVC, 6, 7, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PVC_ACC_FRM, REG_FIELD_ID(AN8855_PVC, 0, 1, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(AN8855_PPBV1, 0, 11, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_PVID_G0_PORT_VID, REG_FIELD_ID(AN8855_PVID, 0, 11, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(AN8855_GMACCR, 4, 7) },
+ { MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(AN8855_GMACCR, 0, 1) },
+
+ { MT7530_MIB_TX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_TX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_SINGLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(AN8855_PORT_MIB_TX_DEFERRED, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_LATE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_TX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_OVERSIZE_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_OVERSIZE_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_FILTERING, REG_FIELD_ID(AN8855_PORT_MIB_RX_FILTERING, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_ALIGN_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_FRAG_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_OVER_SZ_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_JABBER_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_RX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_CTRL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_INGRESS_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_ARL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_FLOW_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_FLOW_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_WRED_DROP, REG_FIELD_ID(AN8855_PORT_MIB_WRED_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_MIRROR_DROP, REG_FIELD_ID(AN8855_PORT_MIB_MIRROR_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_PORT_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_PORT_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+};
+
+static const struct mt7530_mib_desc an8855_mib[] = {
+ MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
+ MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
+ MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
+ MIB_DESC(AN8855_MIB_TX_OVERSIZE_DROP, -1, "TxOversizeDrop"),
+ MIB_DESC(AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, "TxBadPktBytes"),
+ MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
+ MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
+ MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),
+ MIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, "RxCtrlDrop"),
+ MIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, "RxIngressDrop"),
+ MIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, "RxArlDrop"),
+ MIB_DESC(AN8855_MIB_FLOW_CONTROL_DROP, -1, "FlowControlDrop"),
+ MIB_DESC(AN8855_MIB_WRED_DROP, -1, "WredDrop"),
+ MIB_DESC(AN8855_MIB_MIRROR_DROP, -1, "MirrorDrop"),
+ MIB_DESC(AN8855_MIB_RX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, "RxBadPktBytes"),
+ MIB_DESC(AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, -1, "RxsFlowSamplingPktDrop"),
+ MIB_DESC(AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, -1, "RxsFlowTotalPktDrop"),
+ MIB_DESC(AN8855_MIB_PORT_CONTROL_DROP, -1, "PortControlDrop"),
+};
+
+static void
+an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
+{
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct an8855_priv *priv = ds->priv;
+ bool learning = false;
+ int ret;
+
+ mt7530_lib_stp_state_set(&priv->lib_priv, port, state);
+
+ switch (state) {
+ case BR_STATE_LEARNING:
+ case BR_STATE_FORWARDING:
+ learning = dp->learning;
+ fallthrough;
+ default:
+ break;
+ }
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS,
+ learning ? 0 : AN8855_SA_DIS);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to update learn reg: %d\n", ret);
+}
+
+static void an8855_port_fast_age(struct dsa_switch *ds, int port)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Set to clean Dynamic entry */
+ ret = regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE);
+ if (ret) {
+ dev_err(priv->ds->dev, "failed to update ATA2 reg: %d\n", ret);
+ goto exit;
+ }
+
+ /* Set Port */
+ ret = regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+ if (ret) {
+ dev_err(priv->ds->dev, "failed to update ATWD2 reg: %d\n", ret);
+ goto exit;
+ }
+
+ /* Flush Dynamic entry at port */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ AN8855_FDB_MAT_MAC_TYPE_PORT, NULL);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to send FDB cmd: %d\n", ret);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
+ BR_BCAST_FLOOD | BR_ISOLATED))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int an8855_port_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_flags(&priv->lib_priv, port, flags,
+ extack);
+}
+
+static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 age_count, age_unit, val;
+
+ /* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */
+ val = msecs / AN8855_L2_AGING_MS_CONSTANT;
+
+ /* Derive the count unit */
+ age_unit = DIV_ROUND_UP(val, FIELD_MAX(AN8855_AGE_CNT) + 1) - 1;
+ if (age_unit > FIELD_MAX(AN8855_AGE_UNIT))
+ age_unit = FIELD_MAX(AN8855_AGE_UNIT);
+
+ /* Get the count in unit, age_unit is always incremented by 1 internally */
+ age_count = DIV_ROUND_UP(val, age_unit + 1) - 1;
+
+ return regmap_update_bits(priv->regmap, AN8855_AAC,
+ AN8855_AGE_CNT | AN8855_AGE_UNIT,
+ FIELD_PREP(AN8855_AGE_CNT, age_count) |
+ FIELD_PREP(AN8855_AGE_UNIT, age_unit));
+}
+
+static int an8855_port_bridge_join(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge,
+ bool *tx_fwd_offload,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_join(&priv->lib_priv, port, bridge,
+ tx_fwd_offload, extack);
+}
+
+static void an8855_port_bridge_leave(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_leave(&priv->lib_priv, port, bridge);
+}
+
+static int an8855_port_fdb_add(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_fdb_add(&priv->lib_priv, port, addr, vid, db);
+}
+
+static int an8855_port_fdb_del(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_fdb_del(&priv->lib_priv, port, addr, vid, db);
+}
+
+static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,
+ dsa_fdb_dump_cb_t *cb, void *data)
+{
+ struct an8855_priv *priv = ds->priv;
+ int banks, count = 0;
+ u32 rsp;
+ int ret;
+ int i;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Load search port */
+ ret = regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+ if (ret)
+ goto exit;
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
+ AN8855_FDB_MAT_MAC_PORT, &rsp);
+ if (ret < 0)
+ goto exit;
+
+ do {
+ /* From response get the number of banks to read, exit if 0 */
+ banks = FIELD_GET(AN8855_ATC_HIT, rsp);
+ if (!banks)
+ break;
+
+ /* Each banks have 4 entry */
+ for (i = 0; i < 4; i++) {
+ struct mt7530_fdb _fdb = { };
+
+ count++;
+
+ /* Check if bank is present */
+ if (!(banks & BIT(i)))
+ continue;
+
+ /* Select bank entry index */
+ ret = regmap_write(priv->regmap, AN8855_ATRDS,
+ FIELD_PREP(AN8855_ATRD_SEL, i));
+ if (ret)
+ break;
+ /* wait 1ms for the bank entry to be filled */
+ usleep_range(1000, 1500);
+ mt7530_lib_fdb_read(&priv->lib_priv, &_fdb);
+
+ ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data);
+ if (ret < 0)
+ break;
+ }
+
+ /* Stop if reached max FDB number */
+ if (ret < 0 || count >= AN8855_NUM_FDB_RECORDS)
+ break;
+
+ /* Read next bank */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT,
+ AN8855_FDB_MAT_MAC_PORT, &rsp);
+ if (ret < 0)
+ break;
+ } while (true);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+ return ret;
+}
+
+static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port,
+ bool vlan_filtering,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_filtering(&priv->lib_priv, port,
+ vlan_filtering,
+ extack);
+}
+
+static int an8855_port_vlan_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_add(&priv->lib_priv, port, vlan, extack);
+}
+
+static int an8855_port_vlan_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_del(&priv->lib_priv, port, vlan);
+}
+
+static int an8855_port_mdb_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mdb_add(&priv->lib_priv, port, mdb, db);
+}
+
+static int an8855_port_mdb_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mdb_del(&priv->lib_priv, port, mdb, db);
+}
+
+static int an8855_port_change_mtu(struct dsa_switch *ds, int port,
+ int new_mtu)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu);
+}
+
+static int an8855_port_max_mtu(struct dsa_switch *ds, int port)
+{
+ return AN8855_MAX_MTU;
+}
+
+static void an8855_get_strings(struct dsa_switch *ds, int port,
+ u32 stringset, uint8_t *data)
+{
+ int i;
+
+ if (stringset != ETH_SS_STATS)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++)
+ ethtool_puts(&data, an8855_mib[i].name);
+}
+
+static void an8855_get_ethtool_stats(struct dsa_switch *ds, int port,
+ uint64_t *data)
+{
+ struct an8855_priv *priv = ds->priv;
+ const struct mt7530_mib_desc *mib;
+ struct mt7530_lib_priv *lib_priv;
+ int i;
+
+ lib_priv = &priv->lib_priv;
+ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) {
+ struct regmap_field *high = NULL;
+
+ mib = &an8855_mib[i];
+ if (mib->field_high != -1)
+ high = lib_priv->fields[mib->field_high];
+
+ mt7530_lib_read_port_stats(lib_priv->fields[mib->field_low],
+ high, port, data + i);
+ }
+}
+
+static int an8855_get_sset_count(struct dsa_switch *ds, int port,
+ int sset)
+{
+ if (sset != ETH_SS_STATS)
+ return -EOPNOTSUPP;
+
+ return ARRAY_SIZE(an8855_mib);
+}
+
+static void an8855_get_eth_mac_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_mac_stats *mac_stats)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_get_eth_mac_stats(&priv->lib_priv, port, mac_stats);
+}
+
+static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {
+ { 0, 64 },
+ { 65, 127 },
+ { 128, 255 },
+ { 256, 511 },
+ { 512, 1023 },
+ { 1024, 1518 },
+ { 1519, AN8855_MAX_MTU },
+ {}
+};
+
+static const struct mt7530_rmon_hist an8855_rmon_hist_info = {
+ .ranges_fields = (unsigned int []){
+ MT7530_MIB_RX_PKT_SZ_64,
+ MT7530_MIB_RX_PKT_SZ_65_TO_127,
+ MT7530_MIB_RX_PKT_SZ_128_TO_255,
+ MT7530_MIB_RX_PKT_SZ_256_TO_511,
+ MT7530_MIB_RX_PKT_SZ_512_TO_1023,
+ AN8855_MIB_RX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_RX_PKT_SZ_1519_TO_MAX,
+ },
+ .ranges_tx_fields = (unsigned int []){
+ MT7530_MIB_TX_PKT_SZ_64,
+ MT7530_MIB_TX_PKT_SZ_65_TO_127,
+ MT7530_MIB_TX_PKT_SZ_128_TO_255,
+ MT7530_MIB_TX_PKT_SZ_256_TO_511,
+ MT7530_MIB_TX_PKT_SZ_512_TO_1023,
+ AN8855_MIB_TX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_TX_PKT_SZ_1519_TO_MAX,
+ },
+ .ranges = an8855_rmon_ranges,
+ .num_ranges = ARRAY_SIZE(an8855_rmon_ranges) - 1,
+};
+
+static void an8855_get_rmon_stats(struct dsa_switch *ds, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_get_rmon_stats(&priv->lib_priv, port, rmon_stats, ranges,
+ &an8855_rmon_hist_info);
+}
+
+static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ mt7530_lib_get_eth_ctrl_stats(&priv->lib_priv, port, ctrl_stats);
+}
+
+static int an8855_port_mirror_add(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mirror_add(&priv->lib_priv, port, mirror, ingress, extack);
+}
+
+static void an8855_port_mirror_del(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ mt7530_lib_port_mirror_del(&priv->lib_priv, port, mirror);
+}
+
+static int an8855_port_enable(struct dsa_switch *ds, int port,
+ struct phy_device *phy)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ priv->ports[port].enable = true;
+ ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ mutex_unlock(&priv->reg_mutex);
+
+ return ret;
+}
+
+static void an8855_port_disable(struct dsa_switch *ds, int port)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ priv->ports[port].enable = false;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to disable port: %d\n", ret);
+}
+
+static int an8855_set_mac_eee(struct dsa_switch *ds, int port,
+ struct ethtool_keee *e)
+{
+ if (e->tx_lpi_timer > 0xFFF)
+ return -EINVAL;
+
+ return 0;
+}
+
+static enum dsa_tag_protocol an8855_get_tag_protocol(struct dsa_switch *ds,
+ int port,
+ enum dsa_tag_protocol mp)
+{
+ return DSA_TAG_PROTO_AIROHA;
+}
+
+static int an8855_setup(struct dsa_switch *ds)
+{
+ struct an8855_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ int ret;
+
+ /* Enable and reset MIB counters */
+ mt7530_lib_mib_reset(&priv->lib_priv);
+
+ dsa_switch_for_each_user_port(dp, ds) {
+ /* Disable MAC by default on all user ports */
+ an8855_port_disable(ds, dp->index);
+
+ /* Individual user ports get connected to CPU port only */
+ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index),
+ FIELD_PREP(AN8855_PORTMATRIX_MASK, BIT(AN8855_CPU_PORT)));
+ if (ret)
+ return ret;
+
+ /* Disable Broadcast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Disable Unknown Unicast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Disable Unknown Multicast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Set default PVID to on all user ports */
+ mt7530_port_set_pvid(&priv->lib_priv, dp->index, AN8855_PORT_VID_DEFAULT);
+ }
+
+ /* Enable Airoha header mode on the cpu port */
+ ret = regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT),
+ AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG);
+ if (ret)
+ return ret;
+
+ /* Unknown multicast frame forwarding to the cpu port */
+ ret = regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Set CPU port number */
+ ret = regmap_update_bits(priv->regmap, AN8855_MFC,
+ AN8855_CPU_EN | AN8855_CPU_PORT_IDX,
+ AN8855_CPU_EN |
+ FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* CPU port gets connected to all user ports of
+ * the switch.
+ */
+ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT),
+ FIELD_PREP(AN8855_PORTMATRIX_MASK, dsa_user_ports(ds)));
+ if (ret)
+ return ret;
+
+ /* CPU port is set to fallback mode to let untagged
+ * frames pass through.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT),
+ AN8855_PORT_VLAN,
+ FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE));
+ if (ret)
+ return ret;
+
+ /* Enable Broadcast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Enable Unknown Unicast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Enable Unknown Multicast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Setup Trap special frame to CPU rules */
+ mt7530_lib_trap_frames(&priv->lib_priv);
+
+ dsa_switch_for_each_port(dp, ds) {
+ /* Disable Learning on all ports.
+ * Learning on CPU is disabled for fdb isolation and handled by
+ * assisted_learning_on_cpu_port.
+ */
+ ret = regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index),
+ AN8855_SA_DIS);
+ if (ret)
+ return ret;
+
+ /* Enable consistent egress tag (for VLAN unware VLAN-passthrough) */
+ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index),
+ AN8855_PVC_EG_TAG,
+ FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT));
+ if (ret)
+ return ret;
+ }
+
+ /* Setup VLAN for Default PVID */
+ ret = mt7530_lib_setup_vlan0(&priv->lib_priv);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_CKGCR,
+ AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP);
+ if (ret)
+ return ret;
+
+ /* Flush the FDB table */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ AN8855_FDB_MAT_ALL, NULL);
+ if (ret < 0)
+ return ret;
+
+ /* Set min a max ageing value supported */
+ ds->ageing_time_min = AN8855_L2_AGING_MS_CONSTANT;
+ ds->ageing_time_max = FIELD_MAX(AN8855_AGE_CNT) *
+ FIELD_MAX(AN8855_AGE_UNIT) *
+ AN8855_L2_AGING_MS_CONSTANT;
+
+ /* User reported problem with WiFi roaming and
+ * ethernet port. Enabling assisted learning fix
+ * the issue.
+ */
+ ds->assisted_learning_on_cpu_port = true;
+
+ return 0;
+}
+
+static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return &priv->pcs;
+ default:
+ return NULL;
+ }
+}
+
+static void an8855_phylink_mac_config(struct phylink_config *config,
+ unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ struct an8855_priv *priv;
+ int port = dp->index;
+
+ priv = ds->priv;
+
+ /* Nothing to configure for internal ports */
+ if (port != 5)
+ return;
+
+ mutex_lock(&priv->reg_mutex);
+ regmap_update_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE |
+ AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN,
+ FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) |
+ AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN |
+ AN8855_PMCR_BACKPR_EN);
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 reg = 0;
+ int ret;
+
+ switch (port) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
+ case 5:
+ phy_interface_set_rgmii(config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ break;
+ }
+
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
+
+ ret = regmap_read(priv->regmap, AN8855_CKGCR, ®);
+ if (ret)
+ dev_err(ds->dev, "failed to read EEE LPI timer\n");
+
+ memcpy(config->lpi_interfaces, config->supported_interfaces,
+ sizeof(config->lpi_interfaces));
+ config->lpi_capabilities = MAC_100FD | MAC_1000FD;
+ /* Global LPI TXIDLE Threshold, default 60ms (unit 2us) */
+ config->lpi_timer_default = FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) *
+ AN8855_TX_LPI_UNIT;
+
+ config->eee_enabled_default = true;
+}
+
+static void an8855_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* With autoneg just disable TX/RX else also force link down */
+ if (phylink_autoneg_inband(mode)) {
+ regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ } else {
+ regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN |
+ AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK,
+ AN8855_PMCR_FORCE_MODE);
+ }
+
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_mac_link_up(struct phylink_config *config,
+ struct phy_device *phydev, unsigned int mode,
+ phy_interface_t interface, int speed,
+ int duplex, bool tx_pause, bool rx_pause)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+ int port = dp->index;
+ u32 reg = 0;
+
+ mutex_lock(&priv->reg_mutex);
+
+ regmap_read(priv->regmap, AN8855_PMCR_P(port), ®);
+ if (phylink_autoneg_inband(mode)) {
+ reg &= ~AN8855_PMCR_FORCE_MODE;
+ } else {
+ reg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK;
+
+ reg &= ~AN8855_PMCR_FORCE_SPEED;
+ switch (speed) {
+ case SPEED_10:
+ reg |= AN8855_PMCR_FORCE_SPEED_10;
+ break;
+ case SPEED_100:
+ reg |= AN8855_PMCR_FORCE_SPEED_100;
+ break;
+ case SPEED_1000:
+ reg |= AN8855_PMCR_FORCE_SPEED_1000;
+ break;
+ case SPEED_2500:
+ reg |= AN8855_PMCR_FORCE_SPEED_2500;
+ break;
+ case SPEED_5000:
+ dev_err(priv->ds->dev, "Missing support for 5G speed. Aborting...\n");
+ goto exit;
+ }
+
+ reg &= ~AN8855_PMCR_FORCE_FDX;
+ if (duplex == DUPLEX_FULL)
+ reg |= AN8855_PMCR_FORCE_FDX;
+
+ reg &= ~AN8855_PMCR_RX_FC_EN;
+ if (rx_pause || dsa_port_is_cpu(dp))
+ reg |= AN8855_PMCR_RX_FC_EN;
+
+ reg &= ~AN8855_PMCR_TX_FC_EN;
+ if (tx_pause || dsa_port_is_cpu(dp))
+ reg |= AN8855_PMCR_TX_FC_EN;
+ }
+
+ reg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN;
+
+ regmap_write(priv->regmap, AN8855_PMCR_P(port), reg);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_mac_disable_tx_lpi(struct phylink_config *config)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+ int port = dp->index;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_FORCE_EEE1G |
+ AN8855_PMCR_FORCE_EEE100);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to disable EEE for port %d\n",
+ port);
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMEEECR_P(port),
+ AN8855_LPI_MODE_EN);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to disable LPI for port %d\n",
+ port);
+}
+
+static int an8855_phylink_mac_enable_tx_lpi(struct phylink_config *config,
+ u32 timer, bool tx_clock_stop)
+{
+ struct an8855_priv *priv;
+ struct dsa_switch *ds;
+ struct dsa_port *dp;
+ int port;
+ u32 val;
+ int ret;
+
+ dp = dsa_phylink_to_port(config);
+ port = dp->index;
+ ds = dp->ds;
+ priv = ds->priv;
+
+ /* TX LPI timer is global, find the highest timer
+ * across all port.
+ * If requested timer is 0, set to enter LPI immediately
+ * for the single port.
+ */
+ if (timer) {
+ int i;
+
+ /* Save requested timer and search the highest one */
+ mutex_lock(&priv->reg_mutex);
+ priv->tx_lpi_timer_ports[dp->index] = timer;
+ for (i = 0; i < AN8855_NUM_PORTS; i++) {
+ if (!priv->ports[i].enable)
+ continue;
+
+ if (i == dp->index)
+ continue;
+
+ if (timer < priv->tx_lpi_timer_ports[i])
+ timer = priv->tx_lpi_timer_ports[i];
+ }
+ mutex_unlock(&priv->reg_mutex);
+
+ timer /= AN8855_TX_LPI_UNIT;
+ if (FIELD_FIT(AN8855_LPI_TXIDLE_THD_MASK, timer))
+ val = FIELD_PREP(AN8855_LPI_TXIDLE_THD_MASK, timer);
+ else
+ val = AN8855_LPI_TXIDLE_THD_MASK;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_CKGCR,
+ AN8855_LPI_TXIDLE_THD_MASK, val);
+ if (ret) {
+ dev_err(dp->ds->dev, "failed to set global LPI timer\n");
+ return ret;
+ }
+ } else {
+ ret = regmap_set_bits(priv->regmap, AN8855_PMEEECR_P(port),
+ AN8855_LPI_MODE_EN);
+ if (ret) {
+ dev_err(dp->ds->dev, "failed to enable LPI for port %d\n",
+ port);
+ return ret;
+ }
+ }
+
+ mutex_lock(&priv->reg_mutex);
+ ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_FORCE_EEE1G |
+ AN8855_PMCR_FORCE_EEE100);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to enable EEE for port %d\n",
+ port);
+
+ return ret;
+}
+
+static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* SGMII can be configured to use inband with AN result */
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
+
+ /* inband is not supported in 2500-baseX and must be disabled */
+ return LINK_INBAND_DISABLE;
+}
+
+static void an8855_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+ u32 val;
+ int ret;
+
+ ret = regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val);
+ if (ret < 0) {
+ state->link = false;
+ return;
+ }
+
+ state->link = !!(val & AN8855_PMSR_LNK);
+ state->an_complete = state->link;
+ state->duplex = (val & AN8855_PMSR_DPX) ? DUPLEX_FULL :
+ DUPLEX_HALF;
+
+ switch (val & AN8855_PMSR_SPEED) {
+ case AN8855_PMSR_SPEED_10:
+ state->speed = SPEED_10;
+ break;
+ case AN8855_PMSR_SPEED_100:
+ state->speed = SPEED_100;
+ break;
+ case AN8855_PMSR_SPEED_1000:
+ state->speed = SPEED_1000;
+ break;
+ case AN8855_PMSR_SPEED_2500:
+ state->speed = SPEED_2500;
+ break;
+ case AN8855_PMSR_SPEED_5000:
+ dev_err(priv->ds->dev, "Switch doesn't support 5G speed. Setting Unknown.\n");
+ fallthrough;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ break;
+ }
+
+ if (val & AN8855_PMSR_RX_FC)
+ state->pause |= MLO_PAUSE_RX;
+ if (val & AN8855_PMSR_TX_FC)
+ state->pause |= MLO_PAUSE_TX;
+}
+
+static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+ u32 val;
+ int ret;
+
+ /* TX FIR - improve TX EYE */
+ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10,
+ AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C2_FORCE |
+ AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C1_FORCE,
+ AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) |
+ AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x0;
+ else
+ val = 0xd;
+ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11,
+ AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C0B_FORCE,
+ AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val));
+ if (ret)
+ return ret;
+
+ /* RX CDR - improve RX Jitter Tolerance */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x5;
+ else
+ val = 0x6;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM,
+ AN8855_RG_QP_CDR_LPF_KP_GAIN |
+ AN8855_RG_QP_CDR_LPF_KI_GAIN,
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) |
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val));
+ if (ret)
+ return ret;
+
+ /* PLL */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x1;
+ else
+ val = 0x0;
+ ret = regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1,
+ AN8855_RG_TPHY_SPEED,
+ FIELD_PREP(AN8855_RG_TPHY_SPEED, val));
+ if (ret)
+ return ret;
+
+ /* PLL - LPF */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+ AN8855_RG_DA_QP_PLL_FBKSEL_INTF |
+ AN8855_RG_DA_QP_PLL_BR_INTF |
+ AN8855_RG_DA_QP_PLL_BPD_INTF |
+ AN8855_RG_DA_QP_PLL_BPA_INTF |
+ AN8855_RG_DA_QP_PLL_BC_INTF,
+ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1));
+ if (ret)
+ return ret;
+
+ /* PLL - ICO */
+ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4,
+ AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF);
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - CHP */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x6;
+ else
+ val = 0x4;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_IR_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val));
+ if (ret)
+ return ret;
+
+ /* PLL - PFD */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF |
+ AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF |
+ AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1));
+ if (ret)
+ return ret;
+
+ /* PLL - POSTDIV */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF |
+ AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF |
+ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF,
+ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - SDM */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_SDM_IFM_INTF);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2,
+ AN8855_RG_NCPO_ANA_MSB,
+ FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x7a000000;
+ else
+ val = 0x48000000;
+ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2,
+ FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val));
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1,
+ FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5,
+ AN8855_RG_LCPLL_NCPO_CHG);
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+ AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - SS */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+ AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4,
+ AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+ AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0));
+ if (ret)
+ return ret;
+
+ /* PLL - TDC */
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+ AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+ AN8855_RG_QP_PLL_SSC_TRI_EN);
+ if (ret)
+ return ret;
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+ AN8855_RG_QP_PLL_SSC_PHASE_INI);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN,
+ AN8855_RG_QP_SIGDET_HF,
+ FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2));
+ if (ret)
+ return ret;
+
+ /* TCL Disable (only for Co-SIM) */
+ ret = regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0,
+ AN8855_RG_QP_EQ_RX500M_CK_SEL);
+ if (ret)
+ return ret;
+
+ /* TX Init */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x4;
+ else
+ val = 0x0;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE,
+ AN8855_RG_QP_TX_RESERVE |
+ AN8855_RG_QP_TX_MODE_16B_EN,
+ FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val));
+ if (ret)
+ return ret;
+
+ /* RX Control/Init */
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE,
+ AN8855_RG_QP_CDR_PD_10B_EN);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x1;
+ else
+ val = 0x2;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM,
+ AN8855_RG_QP_CDR_LPF_RATIO,
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE,
+ AN8855_RG_QP_CDR_PR_BUF_IN_SR |
+ AN8855_RG_QP_CDR_PR_BETA_SEL,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) |
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0xf;
+ else
+ val = 0xc;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+ AN8855_RG_QP_CDR_PR_DAC_BAND,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+ AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE |
+ AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF,
+ AN8855_RG_QP_CDR_PHYCK_SEL |
+ AN8855_RG_QP_CDR_PHYCK_RSTB |
+ AN8855_RG_QP_CDR_PHYCK_DIV,
+ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) |
+ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+ AN8855_RG_QP_CDR_PR_XFICK_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+ AN8855_RG_QP_CDR_PR_KBAND_DIV,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26,
+ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+ AN8855_RG_LINK_NE_EN |
+ AN8855_RG_LINK_ERRO_EN,
+ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+ AN8855_RG_LINK_ERRO_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_DLY_0,
+ AN8855_RG_QP_RX_SAOSC_EN_H_DLY |
+ AN8855_RG_QP_RX_PI_CAL_EN_H_DLY,
+ FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) |
+ FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42,
+ AN8855_RG_QP_EQ_EN_DLY,
+ FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2,
+ AN8855_RG_QP_RX_EQ_EN_H_DLY,
+ FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9,
+ AN8855_RG_QP_EQ_LEQOSC_DLYCNT,
+ FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8,
+ AN8855_RG_DA_QP_SAOSC_DONE_TIME |
+ AN8855_RG_DA_QP_LEQOS_EN_TIME,
+ FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) |
+ FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff));
+ if (ret)
+ return ret;
+
+ /* Frequency meter */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x10;
+ else
+ val = 0x28;
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5,
+ AN8855_RG_FREDET_CHK_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6,
+ AN8855_RG_FREDET_GOLDEN_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7,
+ AN8855_RG_FREDET_TOLERATE_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0,
+ AN8855_RG_PHYA_AUTO_INIT);
+ if (ret)
+ return ret;
+
+ /* PCS Init */
+ if (interface == PHY_INTERFACE_MODE_SGMII &&
+ neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) {
+ ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0,
+ AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1,
+ AN8855_RG_TBI_10B_MODE);
+ if (ret)
+ return ret;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* Set AN Ability - Interrupt */
+ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37,
+ AN8855_RG_FORCE_AN_DONE);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13,
+ AN8855_SGMII_REMOTE_FAULT_DIS |
+ AN8855_SGMII_IF_MODE,
+ AN8855_SGMII_REMOTE_FAULT_DIS |
+ FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb));
+ if (ret)
+ return ret;
+ }
+
+ /* Rate Adaption - GMII path config. */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_DIS_MII_MODE);
+ if (ret)
+ return ret;
+ } else {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ ret = regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE,
+ AN8855_RG_P0_RA_AN_EN);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE,
+ AN8855_RG_FORCE_CUR_SGMII_MODE |
+ AN8855_RG_FORCE_CUR_SGMII_SEL,
+ AN8855_RG_FORCE_CUR_SGMII_SEL);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_MII_RA_RX_EN |
+ AN8855_RG_P0_MII_RA_TX_EN |
+ AN8855_RG_P0_MII_RA_RX_MODE |
+ AN8855_RG_P0_MII_RA_TX_MODE);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_MII_MODE);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0,
+ AN8855_RG_RATE_ADAPT_RX_BYPASS |
+ AN8855_RG_RATE_ADAPT_TX_BYPASS |
+ AN8855_RG_RATE_ADAPT_RX_EN |
+ AN8855_RG_RATE_ADAPT_TX_EN);
+ if (ret)
+ return ret;
+
+ /* Disable AN if not in autoneg */
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE,
+ neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE :
+ 0);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ /* Follow SDK init flow with restarting AN after AN enable */
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0,
+ BMCR_ANRESTART);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0,
+ AN8855_RG_FORCE_TXC_SEL);
+ if (ret)
+ return ret;
+ }
+ }
+
+ /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX ||
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = AN8855_RG_LINK_MODE_P0_SPEED_2500;
+ else
+ val = AN8855_RG_LINK_MODE_P0_SPEED_1000;
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0,
+ AN8855_RG_LINK_MODE_P0 |
+ AN8855_RG_FORCE_SPD_MODE_P0,
+ val | AN8855_RG_FORCE_SPD_MODE_P0);
+ if (ret)
+ return ret;
+ }
+
+ /* bypass flow control to MAC */
+ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0,
+ AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 |
+ AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 |
+ AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0);
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2,
+ AN8855_RG_RXFC_AN_BYPASS_P3 |
+ AN8855_RG_RXFC_AN_BYPASS_P2 |
+ AN8855_RG_RXFC_AN_BYPASS_P1 |
+ AN8855_RG_TXFC_AN_BYPASS_P3 |
+ AN8855_RG_TXFC_AN_BYPASS_P2 |
+ AN8855_RG_TXFC_AN_BYPASS_P1 |
+ AN8855_RG_DPX_AN_BYPASS_P3 |
+ AN8855_RG_DPX_AN_BYPASS_P2 |
+ AN8855_RG_DPX_AN_BYPASS_P1 |
+ AN8855_RG_DPX_AN_BYPASS_P0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void an8855_pcs_an_restart(struct phylink_pcs *pcs)
+{
+}
+
+static const struct phylink_pcs_ops an8855_pcs_ops = {
+ .pcs_inband_caps = an8855_pcs_inband_caps,
+ .pcs_get_state = an8855_pcs_get_state,
+ .pcs_config = an8855_pcs_config,
+ .pcs_an_restart = an8855_pcs_an_restart,
+};
+
+static const struct phylink_mac_ops an8855_phylink_mac_ops = {
+ .mac_select_pcs = an8855_phylink_mac_select_pcs,
+ .mac_config = an8855_phylink_mac_config,
+ .mac_link_down = an8855_phylink_mac_link_down,
+ .mac_link_up = an8855_phylink_mac_link_up,
+ .mac_disable_tx_lpi = an8855_phylink_mac_disable_tx_lpi,
+ .mac_enable_tx_lpi = an8855_phylink_mac_enable_tx_lpi,
+};
+
+static const struct dsa_switch_ops an8855_switch_ops = {
+ .get_tag_protocol = an8855_get_tag_protocol,
+ .setup = an8855_setup,
+ .phylink_get_caps = an8855_phylink_get_caps,
+ .get_strings = an8855_get_strings,
+ .get_ethtool_stats = an8855_get_ethtool_stats,
+ .get_sset_count = an8855_get_sset_count,
+ .get_eth_mac_stats = an8855_get_eth_mac_stats,
+ .get_eth_ctrl_stats = an8855_get_eth_ctrl_stats,
+ .get_rmon_stats = an8855_get_rmon_stats,
+ .port_enable = an8855_port_enable,
+ .port_disable = an8855_port_disable,
+ .set_ageing_time = an8855_set_ageing_time,
+ .port_bridge_join = an8855_port_bridge_join,
+ .port_bridge_leave = an8855_port_bridge_leave,
+ .port_fast_age = an8855_port_fast_age,
+ .port_stp_state_set = an8855_port_stp_state_set,
+ .port_pre_bridge_flags = an8855_port_pre_bridge_flags,
+ .port_bridge_flags = an8855_port_bridge_flags,
+ .port_vlan_filtering = an8855_port_vlan_filtering,
+ .port_vlan_add = an8855_port_vlan_add,
+ .port_vlan_del = an8855_port_vlan_del,
+ .port_fdb_add = an8855_port_fdb_add,
+ .port_fdb_del = an8855_port_fdb_del,
+ .port_fdb_dump = an8855_port_fdb_dump,
+ .port_mdb_add = an8855_port_mdb_add,
+ .port_mdb_del = an8855_port_mdb_del,
+ .port_change_mtu = an8855_port_change_mtu,
+ .port_max_mtu = an8855_port_max_mtu,
+ .port_mirror_add = an8855_port_mirror_add,
+ .port_mirror_del = an8855_port_mirror_del,
+ .support_eee = dsa_supports_eee,
+ .set_mac_eee = an8855_set_mac_eee,
+};
+
+static int an8855_setup_lib_priv(struct an8855_priv *priv)
+{
+ struct mt7530_lib_priv *lib_priv = &priv->lib_priv;
+ int i;
+
+ lib_priv->dev = priv->ds->dev;
+ lib_priv->ds = priv->ds;
+ lib_priv->regmap = priv->regmap;
+ lib_priv->ports = priv->ports;
+ lib_priv->reg_mutex = &priv->reg_mutex;
+
+ for (i = 0; i < ARRAY_SIZE(an8855_fields); i++) {
+ const struct mt7530_reg_field *reg_field;
+ struct regmap_field *field;
+
+ reg_field = &an8855_fields[i];
+ field = devm_regmap_field_alloc(priv->ds->dev, priv->regmap,
+ reg_field->field);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ lib_priv->fields[reg_field->id] = field;
+ }
+
+ return 0;
+}
+
+static int an8855_switch_probe(struct platform_device *pdev)
+{
+ struct an8855_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ /* Get regmap from MFD */
+ priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!priv->regmap)
+ return -ENOENT;
+
+ priv->ds = devm_kzalloc(&pdev->dev, sizeof(*priv->ds), GFP_KERNEL);
+ if (!priv->ds)
+ return -ENOMEM;
+
+ priv->ds->dev = &pdev->dev;
+ priv->ds->num_ports = AN8855_NUM_PORTS;
+ priv->ds->priv = priv;
+ priv->ds->ops = &an8855_switch_ops;
+ ret = devm_mutex_init(&pdev->dev, &priv->reg_mutex);
+ if (ret)
+ return ret;
+ priv->ds->phylink_mac_ops = &an8855_phylink_mac_ops;
+
+ priv->pcs.ops = &an8855_pcs_ops;
+ priv->pcs.poll = true;
+
+ ret = an8855_setup_lib_priv(priv);
+ if (ret)
+ return ret;
+
+ dev_set_drvdata(&pdev->dev, priv);
+
+ return dsa_register_switch(priv->ds);
+}
+
+static void an8855_switch_remove(struct platform_device *pdev)
+{
+ struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_unregister_switch(priv->ds);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+}
+
+static void an8855_switch_shutdown(struct platform_device *pdev)
+{
+ struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(priv->ds);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+}
+
+static const struct of_device_id an8855_switch_of_match[] = {
+ { .compatible = "airoha,an8855-switch" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_switch_of_match);
+
+static struct platform_driver an8855_switch_driver = {
+ .probe = an8855_switch_probe,
+ .remove = an8855_switch_remove,
+ .shutdown = an8855_switch_shutdown,
+ .driver = {
+ .name = "an8855-switch",
+ .of_match_table = an8855_switch_of_match,
+ },
+};
+module_platform_driver(an8855_switch_driver);
+
+MODULE_AUTHOR("Min Yao <min.yao@airoha.com>");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/an8855.h b/drivers/net/dsa/an8855.h
new file mode 100644
index 0000000000000..85003e5684509
--- /dev/null
+++ b/drivers/net/dsa/an8855.h
@@ -0,0 +1,755 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#ifndef __AN8855_H
+#define __AN8855_H
+
+#include <linux/bitfield.h>
+
+#include "mt7530-lib.h"
+
+#define AN8855_NUM_PORTS 6
+#define AN8855_CPU_PORT 5
+#define AN8855_NUM_FDB_RECORDS 2048
+#define AN8855_GPHY_SMI_ADDR_DEFAULT 1
+#define AN8855_PORT_VID_DEFAULT 0
+
+#define MTK_TAG_LEN 4
+#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN)
+
+#define AN8855_L2_AGING_MS_CONSTANT 1024
+
+#define AN8855_TX_LPI_UNIT 2 /* us */
+
+/* AN8855_SCU 0x10000000 */
+#define AN8855_RG_GPIO_LED_MODE 0x10000054
+#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4)))
+#define AN8855_RG_INTB_MODE 0x10000080
+#define AN8855_RG_RGMII_TXCK_C 0x100001d0
+
+#define AN8855_PKG_SEL 0x10000094
+#define AN8855_PAG_SEL_AN8855H 0x2
+
+#define AN8855_RG_GPIO_L_INV 0x10000010
+#define AN8855_RG_GPIO_CTRL 0x1000a300
+#define AN8855_RG_GPIO_DATA 0x1000a304
+#define AN8855_RG_GPIO_OE 0x1000a314
+
+/* Register for system reset */
+#define AN8855_RST_CTRL 0x100050c0
+#define AN8855_SYS_CTRL_SYS_RST BIT(31)
+
+#define AN8855_INT_MASK 0x100050f0
+#define AN8855_INT_SYS BIT(15)
+
+#define AN8855_RG_CLK_CPU_ICG 0x10005034
+#define AN8855_MCU_ENABLE BIT(3)
+
+#define AN8855_RG_TIMER_CTL 0x1000a100
+#define AN8855_WDOG_ENABLE BIT(25)
+
+#define AN8855_RG_GDMP_RAM 0x10010000
+
+/* Registers to mac forward control for unknown frames */
+#define AN8855_MFC 0x10200010
+#define AN8855_CPU_EN BIT(15)
+#define AN8855_CPU_PORT_IDX GENMASK(12, 8)
+
+#define AN8855_PAC 0x10200024
+#define AN8855_TAG_PAE_MANG_FR BIT(30)
+#define AN8855_TAG_PAE_BPDU_FR BIT(28)
+#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25)
+#define AN8855_TAG_PAE_LKY_VLAN BIT(24)
+#define AN8855_TAG_PAE_PRI_HIGH BIT(23)
+#define AN8855_TAG_PAE_MIR GENMASK(20, 19)
+#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16)
+#define AN8855_PAE_MANG_FR BIT(14)
+#define AN8855_PAE_BPDU_FR BIT(12)
+#define AN8855_PAE_EG_TAG GENMASK(11, 9)
+#define AN8855_PAE_LKY_VLAN BIT(8)
+#define AN8855_PAE_PRI_HIGH BIT(7)
+#define AN8855_PAE_MIR GENMASK(4, 3)
+#define AN8855_PAE_PORT_FW GENMASK(2, 0)
+
+#define AN8855_RGAC1 0x10200028
+#define AN8855_R02_MANG_FR BIT(30)
+#define AN8855_R02_BPDU_FR BIT(28)
+#define AN8855_R02_EG_TAG GENMASK(27, 25)
+#define AN8855_R02_LKY_VLAN BIT(24)
+#define AN8855_R02_PRI_HIGH BIT(23)
+#define AN8855_R02_MIR GENMASK(20, 19)
+#define AN8855_R02_PORT_FW GENMASK(18, 16)
+#define AN8855_R01_MANG_FR BIT(14)
+#define AN8855_R01_BPDU_FR BIT(12)
+#define AN8855_R01_EG_TAG GENMASK(11, 9)
+#define AN8855_R01_LKY_VLAN BIT(8)
+#define AN8855_R01_PRI_HIGH BIT(7)
+#define AN8855_R01_MIR GENMASK(4, 3)
+#define AN8855_R01_PORT_FW GENMASK(2, 0)
+
+#define AN8855_RGAC2 0x1020002c
+#define AN8855_R0E_MANG_FR BIT(30)
+#define AN8855_R0E_BPDU_FR BIT(28)
+#define AN8855_R0E_EG_TAG GENMASK(27, 25)
+#define AN8855_R0E_LKY_VLAN BIT(24)
+#define AN8855_R0E_PRI_HIGH BIT(23)
+#define AN8855_R0E_MIR GENMASK(20, 19)
+#define AN8855_R0E_PORT_FW GENMASK(18, 16)
+#define AN8855_R03_MANG_FR BIT(14)
+#define AN8855_R03_BPDU_FR BIT(12)
+#define AN8855_R03_EG_TAG GENMASK(11, 9)
+#define AN8855_R03_LKY_VLAN BIT(8)
+#define AN8855_R03_PRI_HIGH BIT(7)
+#define AN8855_R03_MIR GENMASK(4, 3)
+#define AN8855_R03_PORT_FW GENMASK(2, 0)
+
+#define AN8855_AAC 0x102000a0
+#define AN8855_MAC_AUTO_FLUSH BIT(28)
+/* Control Address Table Age time.
+ * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT
+ */
+#define AN8855_AGE_CNT GENMASK(20, 12)
+/* Value in seconds. Value is always incremented of 1 */
+#define AN8855_AGE_UNIT GENMASK(10, 0)
+
+/* Registers for ARL Unknown Unicast Forward control */
+#define AN8855_UNUF 0x102000b4
+
+/* Registers for ARL Unknown Multicast Forward control */
+#define AN8855_UNMF 0x102000b8
+
+/* Registers for ARL Broadcast forward control */
+#define AN8855_BCF 0x102000bc
+
+/* Registers for port address age disable */
+#define AN8855_AGDIS 0x102000c0
+
+/* Registers for mirror port control */
+#define AN8855_MIR 0x102000cc
+#define AN8855_MIRROR_EN BIT(7)
+#define AN8855_MIRROR_PORT GENMASK(4, 0)
+
+/* Registers for BPDU and PAE frame control*/
+#define AN8855_BPC 0x102000d0
+#define AN8855_BPDU_MANG_FR BIT(14)
+#define AN8855_BPDU_BPDU_FR BIT(12)
+#define AN8855_BPDU_EG_TAG GENMASK(11, 9)
+#define AN8855_BPDU_LKY_VLAN BIT(8)
+#define AN8855_BPDU_PRI_HIGH BIT(7)
+#define AN8855_BPDU_MIR GENMASK(4, 3)
+#define AN8855_BPDU_PORT_FW GENMASK(2, 0)
+
+/* Registers for IP Unknown Multicast Forward control */
+#define AN8855_UNIPMF 0x102000dc
+
+enum an8855_bpdu_port_fw {
+ AN8855_BPDU_FOLLOW_MFC = 0,
+ AN8855_BPDU_CPU_EXCLUDE = 4,
+ AN8855_BPDU_CPU_INCLUDE = 5,
+ AN8855_BPDU_CPU_ONLY = 6,
+ AN8855_BPDU_DROP = 7,
+};
+
+/* Register for address table control */
+#define AN8855_ATC 0x10200300
+#define AN8855_ATC_BUSY BIT(31)
+#define AN8855_ATC_HASH GENMASK(24, 16)
+#define AN8855_ATC_HIT GENMASK(15, 12)
+#define AN8855_ATC_MAT_MASK GENMASK(11, 7)
+#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x)
+#define AN8855_ATC_SAT GENMASK(5, 4)
+#define AN8855_ATC_CMD GENMASK(2, 0)
+
+enum an8855_fdb_mat_cmds {
+ AN8855_FDB_MAT_ALL = 0,
+ AN8855_FDB_MAT_MAC, /* All MAC address */
+ AN8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */
+ AN8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */
+ AN8855_FDB_MAT_DIP, /* All DIP/GA address */
+ AN8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */
+ AN8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */
+ AN8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */
+ AN8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */
+ AN8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */
+ AN8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */
+ AN8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */
+ AN8855_FDB_MAT_MAC_PORT, /* All MAC address with port */
+ AN8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */
+ AN8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */
+ AN8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */
+ AN8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */
+ /* All MAC address with MAC type (dynamic or static) with CVID */
+ AN8855_FDB_MAT_MAC_TYPE_CVID,
+ /* All MAC address with MAC type (dynamic or static) with Filter ID */
+ AN8855_FDB_MAT_MAC_TYPE_FID,
+ /* All MAC address with MAC type (dynamic or static) with port */
+ AN8855_FDB_MAT_MAC_TYPE_PORT,
+};
+
+/* Registers for address table access */
+#define AN8855_ATA1 0x10200304
+#define AN8855_ATA1_MAC0 GENMASK(31, 24)
+#define AN8855_ATA1_MAC1 GENMASK(23, 16)
+#define AN8855_ATA1_MAC2 GENMASK(15, 8)
+#define AN8855_ATA1_MAC3 GENMASK(7, 0)
+#define AN8855_ATA2 0x10200308
+#define AN8855_ATA2_MAC4 GENMASK(31, 24)
+#define AN8855_ATA2_MAC5 GENMASK(23, 16)
+#define AN8855_ATA2_UNAUTH BIT(10)
+#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */
+#define AN8855_ATA2_AGE GENMASK(8, 0)
+
+/* Register for address table write data */
+#define AN8855_ATWD 0x10200324
+#define AN8855_ATWD_FID GENMASK(31, 28)
+#define AN8855_ATWD_VID GENMASK(27, 16)
+#define AN8855_ATWD_IVL BIT(15)
+#define AN8855_ATWD_EG_TAG GENMASK(14, 12)
+#define AN8855_ATWD_SA_MIR GENMASK(9, 8)
+#define AN8855_ATWD_SA_FWD GENMASK(7, 5)
+#define AN8855_ATWD_UPRI GENMASK(4, 2)
+#define AN8855_ATWD_LEAKY BIT(1)
+#define AN8855_ATWD_VLD_MASK BIT(0) /* vid LOAD */
+#define AN8855_ATWD2 0x10200328
+#define AN8855_ATWD2_PORT GENMASK(7, 0)
+
+/* Registers for table search read address */
+#define AN8855_ATRDS 0x10200330
+#define AN8855_ATRD_SEL GENMASK(1, 0)
+#define AN8855_ATRD0 0x10200334
+#define AN8855_ATRD0_FID GENMASK(28, 25)
+#define AN8855_ATRD0_VID GENMASK(21, 10)
+#define AN8855_ATRD0_IVL BIT(9)
+#define AN8855_ATRD0_TYPE GENMASK(4, 3)
+#define AN8855_ATRD0_ARP GENMASK(2, 1)
+#define AN8855_ATRD0_LIVE BIT(0)
+#define AN8855_ATRD1 0x10200338
+#define AN8855_ATRD1_MAC4 GENMASK(31, 24)
+#define AN8855_ATRD1_MAC5 GENMASK(23, 16)
+#define AN8855_ATRD1_AGING GENMASK(11, 3)
+#define AN8855_ATRD2 0x1020033c
+#define AN8855_ATRD2_MAC0 GENMASK(31, 24)
+#define AN8855_ATRD2_MAC1 GENMASK(23, 16)
+#define AN8855_ATRD2_MAC2 GENMASK(15, 8)
+#define AN8855_ATRD2_MAC3 GENMASK(7, 0)
+#define AN8855_ATRD3 0x10200340
+#define AN8855_ATRD3_PORTMASK GENMASK(7, 0)
+
+enum an8855_fdb_type {
+ AN8855_MAC_TB_TY_MAC = 0,
+ AN8855_MAC_TB_TY_DIP = 1,
+ AN8855_MAC_TB_TY_DIP_SIP = 2,
+};
+
+/* Register for vlan table control */
+#define AN8855_VTCR 0x10200600
+#define AN8855_VTCR_BUSY BIT(31)
+#define AN8855_VTCR_FUNC GENMASK(15, 12)
+#define AN8855_VTCR_VID GENMASK(11, 0)
+
+enum an8855_vlan_cmd {
+ /* Read/Write the specified VID entry from VAWD register based
+ * on VID.
+ */
+ AN8855_VTCR_RD_VID = 0,
+ AN8855_VTCR_WR_VID = 1,
+};
+
+/* Register for setup vlan write data */
+#define AN8855_VAWD0 0x10200604
+/* VLAN Member Control */
+#define AN8855_VA0_PORT GENMASK(31, 26)
+/* Egress Tag Control */
+#define AN8855_VA0_ETAG GENMASK(23, 12)
+#define AN8855_VA0_ETAG_PORT GENMASK(13, 12)
+#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2)
+#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \
+ AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \
+ AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define AN8855_VA0_EG_CON BIT(11)
+#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */
+#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */
+#define AN8855_VA0_FID GENMASK(4, 1)
+#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */
+#define AN8855_VAWD1 0x10200608
+#define AN8855_VA1_PORT_STAG BIT(1)
+
+enum an8855_fid {
+ AN8855_FID_STANDALONE = 0,
+ AN8855_FID_BRIDGED = 1,
+};
+
+/* Same register field of VAWD0 */
+#define AN8855_VARD0 0x10200618
+
+enum an8855_vlan_egress_attr {
+ AN8855_VLAN_EGRESS_UNTAG = 0,
+ AN8855_VLAN_EGRESS_TAG = 2,
+ AN8855_VLAN_EGRESS_STACK = 3,
+};
+
+/* Register for port STP state control */
+#define AN8855_SSP 0x10208000
+#define AN8855_SSP_P(x) (AN8855_SSP + ((x) * 0x200))
+/* Up to 16 FID supported, each with the same mask */
+#define AN8855_FID_PST GENMASK(1, 0)
+#define AN8855_FID_PST_SHIFT(fid) (2 * (fid))
+#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \
+ AN8855_FID_PST_SHIFT(fid))
+#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \
+ AN8855_FID_PST_SHIFT(fid))
+
+enum an8855_stp_state {
+ AN8855_STP_DISABLED = 0,
+ AN8855_STP_BLOCKING = 1,
+ AN8855_STP_LISTENING = AN8855_STP_BLOCKING,
+ AN8855_STP_LEARNING = 2,
+ AN8855_STP_FORWARDING = 3
+};
+
+/* Register for port control */
+#define AN8855_PCR 0x10208004
+#define AN8855_PCR_P(x) (AN8855_PCR + ((x) * 0x200))
+#define AN8855_EG_TAG GENMASK(29, 28)
+#define AN8855_PORT_PRI GENMASK(26, 24)
+#define AN8855_PORT_TX_MIR BIT(20)
+#define AN8855_PORT_RX_MIR BIT(16)
+#define AN8855_PORT_VLAN GENMASK(1, 0)
+
+enum an8855_port_mode {
+ /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
+ AN8855_PORT_MATRIX_MODE = 0,
+
+ /* Fallback Mode: Forward received frames with ingress ports that do
+ * not belong to the VLAN member. Frames whose VID is not listed on
+ * the VLAN table are forwarded by the PCR_MATRIX members.
+ */
+ AN8855_PORT_FALLBACK_MODE = 1,
+
+ /* Check Mode: Forward received frames whose ingress do not
+ * belong to the VLAN member. Discard frames if VID ismiddes on the
+ * VLAN table.
+ */
+ AN8855_PORT_CHECK_MODE = 2,
+
+ /* Security Mode: Discard any frame due to ingress membership
+ * violation or VID missed on the VLAN table.
+ */
+ AN8855_PORT_SECURITY_MODE = 3,
+};
+
+/* Register for port security control */
+#define AN8855_PSC 0x1020800c
+#define AN8855_PSC_P(x) (AN8855_PSC + ((x) * 0x200))
+#define AN8855_SA_DIS BIT(4)
+
+/* Register for port vlan control */
+#define AN8855_PVC 0x10208010
+#define AN8855_PVC_P(x) (AN8855_PVC + ((x) * 0x200))
+#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11)
+#define AN8855_PVC_EG_TAG GENMASK(10, 8)
+#define AN8855_VLAN_ATTR GENMASK(7, 6)
+#define AN8855_PORT_SPEC_TAG BIT(5)
+#define AN8855_ACC_FRM GENMASK(1, 0)
+
+enum an8855_vlan_port_eg_tag {
+ AN8855_VLAN_EG_DISABLED = 0,
+ AN8855_VLAN_EG_CONSISTENT = 1,
+ AN8855_VLAN_EG_UNTAGGED = 4,
+ AN8855_VLAN_EG_SWAP = 5,
+ AN8855_VLAN_EG_TAGGED = 6,
+ AN8855_VLAN_EG_STACK = 7,
+};
+
+enum an8855_vlan_port_attr {
+ AN8855_VLAN_USER = 0,
+ AN8855_VLAN_STACK = 1,
+ AN8855_VLAN_TRANSPARENT = 3,
+};
+
+enum an8855_vlan_port_acc_frm {
+ AN8855_VLAN_ACC_ALL = 0,
+ AN8855_VLAN_ACC_TAGGED = 1,
+ AN8855_VLAN_ACC_UNTAGGED = 2,
+};
+
+#define AN8855_PPBV1 0x10208014
+#define AN8855_PPBV1_P(x) (AN8855_PPBV1 + ((x) * 0x200))
+#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0)
+
+#define AN8855_PORTMATRIX 0x10208044
+#define AN8855_PORTMATRIX_P(x) (AN8855_PORTMATRIX + ((x) * 0x200))
+#define AN8855_PORTMATRIX_MASK GENMASK(5, 0)
+/* Port matrix without the CPU port that should never be removed */
+#define AN8855_USER_PORTMATRIX GENMASK(4, 0)
+
+/* Register for port PVID */
+#define AN8855_PVID 0x10208048
+#define AN8855_PVID_P(x) (AN8855_PVID + ((x) * 0x200))
+#define AN8855_G0_PORT_VID GENMASK(11, 0)
+
+/* Register for port MAC control register */
+#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200))
+#define AN8855_PMCR_FORCE_MODE BIT(31)
+#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28)
+#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4)
+#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3)
+#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2)
+#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
+#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x0)
+#define AN8855_PMCR_FORCE_FDX BIT(25)
+#define AN8855_PMCR_FORCE_LNK BIT(24)
+#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20)
+#define AN8855_PMCR_EXT_PHY BIT(19)
+#define AN8855_PMCR_MAC_MODE BIT(18)
+#define AN8855_PMCR_TX_EN BIT(16)
+#define AN8855_PMCR_RX_EN BIT(15)
+#define AN8855_PMCR_BACKOFF_EN BIT(12)
+#define AN8855_PMCR_BACKPR_EN BIT(11)
+#define AN8855_PMCR_FORCE_EEE5G BIT(9)
+#define AN8855_PMCR_FORCE_EEE2P5G BIT(8)
+#define AN8855_PMCR_FORCE_EEE1G BIT(7)
+#define AN8855_PMCR_FORCE_EEE100 BIT(6)
+#define AN8855_PMCR_RX_FC_EN BIT(5)
+#define AN8855_PMCR_TX_FC_EN BIT(4)
+
+#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200)
+#define AN8855_PMSR_SPEED GENMASK(30, 28)
+#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4)
+#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3)
+#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2)
+#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1)
+#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0)
+#define AN8855_PMSR_DPX BIT(25)
+#define AN8855_PMSR_LNK BIT(24)
+#define AN8855_PMSR_EEE1G BIT(7)
+#define AN8855_PMSR_EEE100M BIT(6)
+#define AN8855_PMSR_RX_FC BIT(5)
+#define AN8855_PMSR_TX_FC BIT(4)
+
+#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200)
+#define AN8855_LPI_MODE_EN BIT(31)
+#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16)
+#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8)
+#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0)
+#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200)
+#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0)
+
+#define AN8855_GMACCR 0x10213e00
+#define AN8855_MAX_RX_JUMBO GENMASK(7, 4)
+/* 2K for 0x0, 0x1, 0x2 */
+#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0)
+#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3)
+#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4)
+#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5)
+#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6)
+#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7)
+#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8)
+#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
+#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
+#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
+#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)
+#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0)
+#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0)
+#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1)
+#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2)
+#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3)
+
+#define AN8855_CKGCR 0x10213e1c
+#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14)
+#define AN8855_CKG_LNKDN_PORT_STOP BIT(1)
+#define AN8855_CKG_LNKDN_GLB_STOP BIT(0)
+
+/* Register for MIB */
+#define AN8855_MIB_COUNTER 0x10214000
+#define AN8855_PORT_MIB_COUNTER(x) (AN8855_MIB_COUNTER + (x) * 0x200)
+/* Each define is an offset of AN8855_PORT_MIB_COUNTER */
+#define AN8855_PORT_MIB_TX_DROP (AN8855_MIB_COUNTER + 0x00)
+#define AN8855_PORT_MIB_TX_CRC_ERR (AN8855_MIB_COUNTER + 0x04)
+#define AN8855_PORT_MIB_TX_UNICAST (AN8855_MIB_COUNTER + 0x08)
+#define AN8855_PORT_MIB_TX_MULTICAST (AN8855_MIB_COUNTER + 0x0c)
+#define AN8855_PORT_MIB_TX_BROADCAST (AN8855_MIB_COUNTER + 0x10)
+#define AN8855_PORT_MIB_TX_COLLISION (AN8855_MIB_COUNTER + 0x14)
+#define AN8855_PORT_MIB_TX_SINGLE_COLLISION (AN8855_MIB_COUNTER + 0x18)
+#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION (AN8855_MIB_COUNTER + 0x1c)
+#define AN8855_PORT_MIB_TX_DEFERRED (AN8855_MIB_COUNTER + 0x20)
+#define AN8855_PORT_MIB_TX_LATE_COLLISION (AN8855_MIB_COUNTER + 0x24)
+#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION (AN8855_MIB_COUNTER + 0x28)
+#define AN8855_PORT_MIB_TX_PAUSE (AN8855_MIB_COUNTER + 0x2c)
+#define AN8855_PORT_MIB_TX_PKT_SZ_64 (AN8855_MIB_COUNTER + 0x30)
+#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0x34)
+#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0x38)
+#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0x3c)
+#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0x40)
+#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0x44)
+#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0x48)
+#define AN8855_PORT_MIB_TX_BYTES_LOW (AN8855_MIB_COUNTER + 0x4c) /* 64 bytes */
+#define AN8855_PORT_MIB_TX_BYTES_HIGH (AN8855_MIB_COUNTER + 0x50)
+#define AN8855_PORT_MIB_TX_OVERSIZE_DROP (AN8855_MIB_COUNTER + 0x54)
+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0x58) /* 64 bytes */
+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0x5c)
+#define AN8855_PORT_MIB_RX_DROP (AN8855_MIB_COUNTER + 0x80)
+#define AN8855_PORT_MIB_RX_FILTERING (AN8855_MIB_COUNTER + 0x84)
+#define AN8855_PORT_MIB_RX_UNICAST (AN8855_MIB_COUNTER + 0x88)
+#define AN8855_PORT_MIB_RX_MULTICAST (AN8855_MIB_COUNTER + 0x8c)
+#define AN8855_PORT_MIB_RX_BROADCAST (AN8855_MIB_COUNTER + 0x90)
+#define AN8855_PORT_MIB_RX_ALIGN_ERR (AN8855_MIB_COUNTER + 0x94)
+#define AN8855_PORT_MIB_RX_CRC_ERR (AN8855_MIB_COUNTER + 0x98)
+#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR (AN8855_MIB_COUNTER + 0x9c)
+#define AN8855_PORT_MIB_RX_FRAG_ERR (AN8855_MIB_COUNTER + 0xa0)
+#define AN8855_PORT_MIB_RX_OVER_SZ_ERR (AN8855_MIB_COUNTER + 0xa4)
+#define AN8855_PORT_MIB_RX_JABBER_ERR (AN8855_MIB_COUNTER + 0xa8)
+#define AN8855_PORT_MIB_RX_PAUSE (AN8855_MIB_COUNTER + 0xac)
+#define AN8855_PORT_MIB_RX_PKT_SZ_64 (AN8855_MIB_COUNTER + 0xb0)
+#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0xb4)
+#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0xb8)
+#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0xbc)
+#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0xc0)
+#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0xc4)
+#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0xc8)
+#define AN8855_PORT_MIB_RX_BYTES_LOW (AN8855_MIB_COUNTER + 0xcc) /* 64 bytes */
+#define AN8855_PORT_MIB_RX_BYTES_HIGH (AN8855_MIB_COUNTER + 0xd0)
+#define AN8855_PORT_MIB_RX_CTRL_DROP (AN8855_MIB_COUNTER + 0xd4)
+#define AN8855_PORT_MIB_RX_INGRESS_DROP (AN8855_MIB_COUNTER + 0xd8)
+#define AN8855_PORT_MIB_RX_ARL_DROP (AN8855_MIB_COUNTER + 0xdc)
+#define AN8855_PORT_MIB_FLOW_CONTROL_DROP (AN8855_MIB_COUNTER + 0xe0)
+#define AN8855_PORT_MIB_WRED_DROP (AN8855_MIB_COUNTER + 0xe4)
+#define AN8855_PORT_MIB_MIRROR_DROP (AN8855_MIB_COUNTER + 0xe8)
+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0xec) /* 64 bytes */
+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0xf0)
+#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP (AN8855_MIB_COUNTER + 0xf4)
+#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP (AN8855_MIB_COUNTER + 0xf8)
+#define AN8855_PORT_MIB_PORT_CONTROL_DROP (AN8855_MIB_COUNTER + 0xfc)
+#define AN8855_MIB_CCR 0x10213e30
+#define AN8855_CCR_MIB_ENABLE BIT(31)
+#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7)
+#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6)
+#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5)
+#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4)
+#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3)
+#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2)
+#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1)
+#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0)
+#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \
+ AN8855_CCR_RX_OCT_CNT_GOOD | \
+ AN8855_CCR_RX_OCT_CNT_BAD | \
+ AN8855_CCR_TX_OCT_CNT_GOOD | \
+ AN8855_CCR_TX_OCT_CNT_BAD | \
+ AN8855_CCR_RX_OCT_CNT_BAD_2 | \
+ AN8855_CCR_TX_OCT_CNT_BAD_2)
+#define AN8855_MIB_CLR 0x10213e34
+#define AN8855_MIB_PORT6_CLR BIT(6)
+#define AN8855_MIB_PORT5_CLR BIT(5)
+#define AN8855_MIB_PORT4_CLR BIT(4)
+#define AN8855_MIB_PORT3_CLR BIT(3)
+#define AN8855_MIB_PORT2_CLR BIT(2)
+#define AN8855_MIB_PORT1_CLR BIT(1)
+#define AN8855_MIB_PORT0_CLR BIT(0)
+
+/* HSGMII/SGMII Configuration register */
+/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */
+#define AN8855_SGMII_REG_AN0 0x10220000
+/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */
+/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */
+#define AN8855_SGMII_REG_AN_13 0x10220034
+#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AN8855_SGMII_IF_MODE GENMASK(5, 0)
+#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060
+#define AN8855_RG_FORCE_AN_DONE BIT(0)
+
+/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */
+#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00
+#define AN8855_RG_TBI_10B_MODE BIT(30)
+#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24
+#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0)
+
+/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */
+#define AN8855_SGMII_STS_CTRL_0 0x10224018
+#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4)
+#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3)
+#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2)
+#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1)
+#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0)
+#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2)
+#define AN8855_MSG_RX_CTRL_0 0x10224100
+#define AN8855_MSG_RX_LIK_STS_0 0x10224514
+#define AN8855_RG_DPX_STS_P3 BIT(24)
+#define AN8855_RG_DPX_STS_P2 BIT(16)
+#define AN8855_RG_EEE1G_STS_P1 BIT(12)
+#define AN8855_RG_DPX_STS_P1 BIT(8)
+#define AN8855_RG_TXFC_STS_P0 BIT(2)
+#define AN8855_RG_RXFC_STS_P0 BIT(1)
+#define AN8855_RG_DPX_STS_P0 BIT(0)
+#define AN8855_MSG_RX_LIK_STS_2 0x1022451c
+#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11)
+#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10)
+#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9)
+#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7)
+#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6)
+#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5)
+#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3)
+#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2)
+#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1)
+#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0)
+#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520
+#define AN8855_RG_FORCE_TXC_SEL BIT(4)
+
+/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */
+#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8
+
+/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */
+#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000
+#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4)
+#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0)
+#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100
+#define AN8855_RG_P0_DIS_MII_MODE BIT(31)
+#define AN8855_RG_P0_MII_MODE BIT(28)
+#define AN8855_RG_P0_MII_RA_RX_EN BIT(3)
+#define AN8855_RG_P0_MII_RA_TX_EN BIT(2)
+#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1)
+#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0)
+#define AN8855_MII_RA_AN_ENABLE 0x10226300
+#define AN8855_RG_P0_RA_AN_EN BIT(0)
+
+/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */
+#define AN8855_QP_CK_RST_CTRL_4 0x1022a310
+#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324
+#define AN8855_RG_SGMII_MODE GENMASK(5, 4)
+#define AN8855_RG_SGMII_AN_EN BIT(0)
+#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330
+#define AN8855_RG_TPHY_SPEED GENMASK(3, 2)
+
+/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */
+#define AN8855_USGMII_CTRL_0 0x1022c000
+
+/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */
+#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100
+#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12)
+#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124
+#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0)
+
+#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208
+#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16)
+#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230
+#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0)
+#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c
+#define AN8855_RG_LCPLL_NCPO_CHG BIT(24)
+#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248
+#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)
+#define AN8855_INTF_CTRL_8 0x1022e320
+#define AN8855_INTF_CTRL_9 0x1022e324
+#define AN8855_INTF_CTRL_10 0x1022e328
+#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29)
+#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24)
+#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21)
+#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16)
+#define AN8855_INTF_CTRL_11 0x1022e32c
+#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6)
+#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0)
+#define AN8855_PLL_CTRL_0 0x1022e400
+#define AN8855_RG_PHYA_AUTO_INIT BIT(0)
+#define AN8855_PLL_CTRL_2 0x1022e408
+#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30)
+#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29)
+#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28)
+#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27)
+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26)
+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24)
+#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22)
+#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20)
+#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16)
+#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14)
+#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12)
+#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8)
+#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6)
+#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2)
+#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0)
+#define AN8855_PLL_CTRL_3 0x1022e40c
+#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16)
+#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0)
+#define AN8855_PLL_CTRL_4 0x1022e410
+#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
+#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2)
+#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0)
+#define AN8855_PLL_CK_CTRL_0 0x1022e414
+#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9)
+#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8)
+#define AN8855_RX_DLY_0 0x1022e614
+#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8)
+#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0)
+#define AN8855_RX_CTRL_2 0x1022e630
+#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16)
+#define AN8855_RX_CTRL_5 0x1022e63c
+#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10)
+#define AN8855_RX_CTRL_6 0x1022e640
+#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_7 0x1022e644
+#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_8 0x1022e648
+#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16)
+#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0)
+#define AN8855_RX_CTRL_26 0x1022e690
+#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26)
+#define AN8855_RG_LINK_NE_EN BIT(24)
+#define AN8855_RG_LINK_ERRO_EN BIT(23)
+#define AN8855_RX_CTRL_42 0x1022e6d0
+#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0)
+
+/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */
+#define AN8855_RG_QP_RX_DAC_EN 0x1022f000
+#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16)
+#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004
+#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11)
+#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008
+#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24)
+#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20)
+#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c
+#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4)
+#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014
+#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29)
+#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25)
+#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c
+#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30)
+#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0)
+#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020
+#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16)
+#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13)
+#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6)
+#define AN8855_RG_QP_TX_MODE 0x1022f028
+#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16)
+#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0)
+#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c
+#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040
+#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4)
+#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3)
+
+/* AN8855_ETHER_SYS_BASE 0x1028c800 */
+#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
+#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848
+
+struct an8855_priv {
+ struct dsa_switch *ds;
+ struct regmap *regmap;
+ /* Protect ATU or VLAN table access */
+ struct mutex reg_mutex;
+
+ struct phylink_pcs pcs;
+
+ struct mt7530_port ports[AN8855_NUM_PORTS];
+ u32 tx_lpi_timer_ports[AN8855_NUM_PORTS];
+
+ struct mt7530_lib_priv lib_priv;
+};
+
+#endif /* __AN8855_H */
diff --git a/drivers/net/dsa/mt7530-lib.c b/drivers/net/dsa/mt7530-lib.c
new file mode 100644
index 0000000000000..cf474faf8ed6a
--- /dev/null
+++ b/drivers/net/dsa/mt7530-lib.c
@@ -0,0 +1,1156 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/device.h>
+#include <linux/if_bridge.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <net/dsa.h>
+
+#include "mt7530-lib.h"
+
+void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv)
+{
+ regmap_field_write(priv->fields[MT7530_CCR_MIB_ENABLE], 0);
+ regmap_field_write(priv->fields[MT7530_CCR_RX_OCT_CNT_GOOD], 1);
+ regmap_field_write(priv->fields[MT7530_CCR_RX_OCT_CNT_BAD], 1);
+ regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_GOOD], 1);
+ regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_BAD], 1);
+ regmap_field_write(priv->fields[MT7530_CCR_MIB_ENABLE], 1);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_mib_reset);
+
+/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
+ * of the Open Systems Interconnection basic reference model (OSI/RM) are
+ * described; the medium access control (MAC) and logical link control (LLC)
+ * sublayers. The MAC sublayer is the one facing the physical layer.
+ *
+ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
+ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
+ * of the Bridge, at least two Ports, and higher layer entities with at least a
+ * Spanning Tree Protocol Entity included.
+ *
+ * Each Bridge Port also functions as an end station and shall provide the MAC
+ * Service to an LLC Entity. Each instance of the MAC Service is provided to a
+ * distinct LLC Entity that supports protocol identification, multiplexing, and
+ * demultiplexing, for protocol data unit (PDU) transmission and reception by
+ * one or more higher layer entities.
+ *
+ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
+ * Entity associated with each Bridge Port is modeled as being directly
+ * connected to the attached Local Area Network (LAN).
+ *
+ * On the switch with CPU port architecture, CPU port functions as Management
+ * Port, and the Management Port functionality is provided by software which
+ * functions as an end station. Software is connected to an IEEE 802 LAN that is
+ * wholly contained within the system that incorporates the Bridge. Software
+ * provides access to the LLC Entity associated with each Bridge Port by the
+ * value of the source port field on the special tag on the frame received by
+ * software.
+ *
+ * We call frames that carry control information to determine the active
+ * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
+ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
+ * Protocol Data Units (MVRPDUs), and frames from other link constrained
+ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
+ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
+ * forwarded by a Bridge. Permanently configured entries in the filtering
+ * database (FDB) ensure that such frames are discarded by the Forwarding
+ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
+ *
+ * Each of the reserved MAC addresses specified in Table 8-1
+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
+ * permanently configured in the FDB in C-VLAN components and ERs.
+ *
+ * Each of the reserved MAC addresses specified in Table 8-2
+ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
+ * configured in the FDB in S-VLAN components.
+ *
+ * Each of the reserved MAC addresses specified in Table 8-3
+ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
+ * TPMR components.
+ *
+ * The FDB entries for reserved MAC addresses shall specify filtering for all
+ * Bridge Ports and all VIDs. Management shall not provide the capability to
+ * modify or remove entries for reserved MAC addresses.
+ *
+ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
+ * propagation of PDUs within a Bridged Network, as follows:
+ *
+ * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
+ * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
+ * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
+ * PDUs transmitted using this destination address, or any other addresses
+ * that appear in Table 8-1, Table 8-2, and Table 8-3
+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
+ * therefore travel no further than those stations that can be reached via a
+ * single individual LAN from the originating station.
+ *
+ * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
+ * address that no conformant S-VLAN component, C-VLAN component, or MAC
+ * Bridge can forward; however, this address is relayed by a TPMR component.
+ * PDUs using this destination address, or any of the other addresses that
+ * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
+ * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
+ * any TPMRs but will propagate no further than the nearest S-VLAN component,
+ * C-VLAN component, or MAC Bridge.
+ *
+ * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
+ * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
+ * relayed by TPMR components and S-VLAN components. PDUs using this
+ * destination address, or any of the other addresses that appear in Table 8-1
+ * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
+ * will be relayed by TPMR components and S-VLAN components but will propagate
+ * no further than the nearest C-VLAN component or MAC Bridge.
+ *
+ * Because the LLC Entity associated with each Bridge Port is provided via CPU
+ * port, we must not filter these frames but forward them to CPU port.
+ *
+ * In a Bridge, the transmission Port is majorly decided by ingress and egress
+ * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
+ * For link-local frames, only CPU port should be designated as destination port
+ * in the FDB, and the other functions of the Forwarding Process must not
+ * interfere with the decision of the transmission Port. We call this process
+ * trapping frames to CPU port.
+ *
+ * Therefore, on the switch with CPU port architecture, link-local frames must
+ * be trapped to CPU port, and certain link-local frames received by a Port of a
+ * Bridge comprising a TPMR component or an S-VLAN component must be excluded
+ * from it.
+ *
+ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
+ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
+ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
+ * doesn't count) of this architecture will either function as a standard MAC
+ * Bridge or a standard VLAN Bridge.
+ *
+ * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
+ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
+ * we don't need to relay PDUs using the destination addresses specified on the
+ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
+ * section where they must be relayed by TPMR components.
+ *
+ * One option to trap link-local frames to CPU port is to add static FDB entries
+ * with CPU port designated as destination port. However, because that
+ * Independent VLAN Learning (IVL) is being used on every VID, each entry only
+ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
+ * Bridge component or a C-VLAN component, there would have to be 16 times 4096
+ * entries. This switch intellectual property can only hold a maximum of 2048
+ * entries. Using this option, there also isn't a mechanism to prevent
+ * link-local frames from being discarded when the spanning tree Port State of
+ * the reception Port is discarding.
+ *
+ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
+ * registers. Whilst this applies to every VID, it doesn't contain all of the
+ * reserved MAC addresses without affecting the remaining Standard Group MAC
+ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
+ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
+ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
+ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
+ * The latter option provides better but not complete conformance.
+ *
+ * This switch intellectual property also does not provide a mechanism to trap
+ * link-local frames with specific destination addresses to CPU port by Bridge,
+ * to conform to the filtering rules for the distinct Bridge components.
+ *
+ * Therefore, regardless of the type of the Bridge component, link-local frames
+ * with these destination addresses will be trapped to CPU port:
+ *
+ * 01-80-C2-00-00-[00,01,02,03,0E]
+ *
+ * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
+ *
+ * Link-local frames with these destination addresses won't be trapped to CPU
+ * port which won't conform to IEEE Std 802.1Q-2022:
+ *
+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
+ *
+ * In a Bridge comprising an S-VLAN component:
+ *
+ * Link-local frames with these destination addresses will be trapped to CPU
+ * port which won't conform to IEEE Std 802.1Q-2022:
+ *
+ * 01-80-C2-00-00-00
+ *
+ * Link-local frames with these destination addresses won't be trapped to CPU
+ * port which won't conform to IEEE Std 802.1Q-2022:
+ *
+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
+ *
+ * To trap link-local frames to CPU port as conformant as this switch
+ * intellectual property can allow, link-local frames are made to be regarded as
+ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
+ * property only lets the frames regarded as BPDUs bypass the spanning tree Port
+ * State function of the Forwarding Process.
+ *
+ * The only remaining interference is the ingress rules. When the reception Port
+ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
+ * There doesn't seem to be a mechanism on the switch intellectual property to
+ * have link-local frames bypass this function of the Forwarding Process.
+ */
+void mt7530_lib_trap_frames(struct mt7530_lib_priv *priv)
+{
+ /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress
+ * them with the EG_TAG attribute set to disabled (system default)
+ * so that any VLAN tags in the frame are not modified by the
+ * switch egress VLAN tag processing. This preserves VLAN tags
+ * for reception on VLAN sub-interfaces.
+ */
+ regmap_field_write(priv->fields[MT7530_BPDU_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_BPDU_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+ regmap_field_write(priv->fields[MT7530_PAE_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_PAE_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_PAE_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and
+ * egress them with EG_TAG disabled.
+ */
+ regmap_field_write(priv->fields[MT7530_R01_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_R01_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_R01_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+ regmap_field_write(priv->fields[MT7530_R02_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_R02_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_R02_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and
+ * egress them with EG_TAG disabled.
+ */
+ regmap_field_write(priv->fields[MT7530_R03_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_R03_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_R03_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+ regmap_field_write(priv->fields[MT7530_R0E_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_R0E_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_R0E_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_trap_frames);
+
+static void mt7530_update_port_member(struct mt7530_lib_priv *priv, int port,
+ const struct net_device *bridge_dev,
+ bool join) __must_hold(priv->reg_mutex)
+{
+ struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp;
+ struct mt7530_port *p = &priv->ports[port], *other_p;
+ struct dsa_port *cpu_dp = dp->cpu_dp;
+ u32 port_bitmap = BIT(cpu_dp->index);
+ int other_port;
+ bool isolated;
+
+ dsa_switch_for_each_user_port(other_dp, priv->ds) {
+ other_port = other_dp->index;
+ other_p = &priv->ports[other_port];
+
+ if (dp == other_dp)
+ continue;
+
+ /* Add/remove this port to/from the port matrix of the other
+ * ports in the same bridge. If the port is disabled, port
+ * matrix is kept and not being setup until the port becomes
+ * enabled.
+ */
+ if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev))
+ continue;
+
+ isolated = p->isolated && other_p->isolated;
+
+ if (join && !isolated) {
+ other_p->pm |= BIT(port);
+ port_bitmap |= BIT(other_port);
+ } else {
+ other_p->pm &= ~BIT(port);
+ }
+
+ if (other_p->enable)
+ regmap_fields_write(priv->fields[MT7530_PCR_MATRIX],
+ other_port, other_p->pm);
+ }
+
+ /* Add/remove the all other ports to this port matrix. For !join
+ * (leaving the bridge), only the CPU port will remain in the port matrix
+ * of this port.
+ */
+ p->pm = port_bitmap;
+ if (priv->ports[port].enable)
+ regmap_fields_write(priv->fields[MT7530_PCR_MATRIX],
+ port, port_bitmap);
+}
+
+void mt7530_lib_read_port_stats(struct regmap_field *low,
+ struct regmap_field *high,
+ int port, uint64_t *data)
+{
+ u32 val = 0;
+
+ regmap_fields_read(low, port, &val);
+ *data = val;
+
+ if (high) {
+ val = 0;
+ regmap_fields_read(high, port, &val);
+ *data |= (u64)val << 32;
+ }
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_read_port_stats);
+
+void mt7530_lib_get_eth_mac_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_eth_mac_stats *mac_stats)
+{
+ /* MIB counter doesn't provide a FramesTransmittedOK but instead
+ * provide stats for Unicast, Broadcast and Multicast frames separately.
+ * To simulate a global frame counter, read Unicast and addition Multicast
+ * and Broadcast later
+ */
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_UNICAST], NULL, port,
+ &mac_stats->FramesTransmittedOK);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_SINGLE_COLLISION], NULL, port,
+ &mac_stats->SingleCollisionFrames);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_MULTIPLE_COLLISION], NULL, port,
+ &mac_stats->MultipleCollisionFrames);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_UNICAST], NULL, port,
+ &mac_stats->FramesReceivedOK);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_BYTES_LOW],
+ priv->fields[MT7530_MIB_TX_BYTES_HIGH], port,
+ &mac_stats->OctetsTransmittedOK);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_ALIGN_ERR], NULL, port,
+ &mac_stats->AlignmentErrors);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_DEFERRED], NULL, port,
+ &mac_stats->FramesWithDeferredXmissions);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_LATE_COLLISION], NULL, port,
+ &mac_stats->LateCollisions);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_EXCESSIVE_COLLISION], NULL, port,
+ &mac_stats->FramesAbortedDueToXSColls);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_BYTES_LOW],
+ priv->fields[MT7530_MIB_RX_BYTES_HIGH], port,
+ &mac_stats->OctetsReceivedOK);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_MULTICAST], NULL, port,
+ &mac_stats->MulticastFramesXmittedOK);
+ mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK;
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_BROADCAST], NULL, port,
+ &mac_stats->BroadcastFramesXmittedOK);
+ mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK;
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_MULTICAST], NULL, port,
+ &mac_stats->MulticastFramesReceivedOK);
+ mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK;
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_BROADCAST], NULL, port,
+ &mac_stats->BroadcastFramesReceivedOK);
+ mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_get_eth_mac_stats);
+
+void mt7530_lib_get_rmon_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges,
+ const struct mt7530_rmon_hist *ranges_info)
+{
+ int i;
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_UNDER_SIZE_ERR], NULL, port,
+ &rmon_stats->undersize_pkts);
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_OVER_SZ_ERR], NULL, port,
+ &rmon_stats->oversize_pkts);
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_FRAG_ERR], NULL, port,
+ &rmon_stats->fragments);
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_JABBER_ERR], NULL, port,
+ &rmon_stats->jabbers);
+
+ for (i = 0; i < ranges_info->num_ranges; i++) {
+ unsigned int field = ranges_info->ranges_fields[i];
+ unsigned int field_tx = ranges_info->ranges_tx_fields[i];
+
+ mt7530_lib_read_port_stats(priv->fields[field], NULL, port,
+ &rmon_stats->hist[i]);
+ mt7530_lib_read_port_stats(priv->fields[field_tx], NULL, port,
+ &rmon_stats->hist_tx[i]);
+ }
+
+ *ranges = ranges_info->ranges;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_get_rmon_stats);
+
+void mt7530_lib_get_eth_ctrl_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats)
+{
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_PAUSE], NULL, port,
+ &ctrl_stats->MACControlFramesTransmitted);
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_PAUSE], NULL, port,
+ &ctrl_stats->MACControlFramesReceived);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_get_eth_ctrl_stats);
+
+int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
+ u32 mat, u32 *rsp)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_ATC_MAT], mat);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_ATC_CMD], cmd);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_ATC_BUSY], 1);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_read_poll_timeout(priv->fields[MT7530_ATC_BUSY],
+ val, !val, 20, 20000);
+ if (ret < 0) {
+ dev_err(priv->dev, "reset timeout\n");
+ return ret;
+ }
+
+ if (priv->fields[MT7530_ATC_INVALID]) {
+ regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
+ if (cmd == MT7530_FDB_READ && val)
+ return -EINVAL;
+ }
+
+ if (rsp)
+ regmap_field_read(priv->fields[__MT7530_ATC], rsp);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_fdb_cmd);
+
+static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
+ u8 port_mask, const u8 *mac,
+ u8 aging, u8 type)
+{
+ /* Clear ATWD registers from previous access */
+ regmap_field_write(priv->fields[__MT7530_ATWD1], 0);
+ regmap_field_write(priv->fields[__MT7530_ATWD2], 0);
+ regmap_field_write(priv->fields[__MT7530_ATWD3], 0);
+ if (priv->fields[__MT7530_ATWD4])
+ regmap_field_write(priv->fields[__MT7530_ATWD4], 0);
+
+ regmap_field_write(priv->fields[MT7530_ATWD_CVID], vid);
+ regmap_field_write(priv->fields[MT7530_ATWD_IVL], 1);
+ regmap_field_write(priv->fields[MT7530_ATWD_FID], FID_BRIDGED);
+ regmap_field_write(priv->fields[MT7530_ATWD_AGE_TIMER], aging);
+ regmap_field_write(priv->fields[MT7530_ATWD_PORT_MAP], port_mask);
+ /* STATIC_ENT indicate that entry is static wouldn't
+ * be aged out and STATIC_EMP specified as erasing an
+ * entry
+ */
+ if (priv->fields[MT7530_ATWD_ENT_STATUS])
+ regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type);
+ if (priv->fields[AN8855_ATWD_TYPE]) {
+ /* Default to static entry (0) */
+ regmap_field_write(priv->fields[AN8855_ATWD_TYPE], 0);
+ }
+ if (priv->fields[AN8855_ATWD_VLD]) {
+ /* Load entry if STATIC_ENT */
+ regmap_field_write(priv->fields[AN8855_ATWD_VLD],
+ type == STATIC_ENT);
+ }
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_5], mac[5]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_4], mac[4]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_3], mac[3]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_2], mac[2]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_1], mac[1]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_0], mac[0]);
+}
+
+void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb)
+{
+ u32 val = 0;
+
+ regmap_field_read(priv->fields[MT7530_ATRD_CVID], &val);
+ fdb->vid = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_AGE_TIMER], &val);
+ fdb->aging = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP], &val);
+ fdb->port_mask = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_5], &val);
+ fdb->mac[5] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_4], &val);
+ fdb->mac[4] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_3], &val);
+ fdb->mac[3] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_2], &val);
+ fdb->mac[2] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_1], &val);
+ fdb->mac[1] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_0], &val);
+ fdb->mac[0] = val;
+ if (priv->fields[MT7530_ATWD_ENT_STATUS]) {
+ regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
+ fdb->noarp = val == STATIC_ENT;
+ }
+ if (priv->fields[AN8855_ATRD_ARP]) {
+ regmap_field_read(priv->fields[AN8855_ATRD_ARP], &val);
+ fdb->noarp = !!val;
+ }
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read);
+
+void mt7530_lib_port_fast_age(struct mt7530_lib_priv *priv, int port)
+{
+ mutex_lock(priv->reg_mutex);
+
+ /* Flush all non-static MAC address entries */
+ mt7530_lib_fdb_cmd(priv, MT7530_FDB_FLUSH,
+ ATC_MAT_NON_STATIC_MAC, NULL);
+
+ mutex_unlock(priv->reg_mutex);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_fast_age);
+
+int mt7530_lib_port_fdb_add(struct mt7530_lib_priv *priv, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ u8 port_mask = BIT(port);
+ int ret;
+
+ mutex_lock(priv->reg_mutex);
+ mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
+ ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
+ ATC_MAT_MACTAB, NULL);
+ mutex_unlock(priv->reg_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_fdb_add);
+
+int mt7530_lib_port_fdb_del(struct mt7530_lib_priv *priv, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ u8 port_mask = BIT(port);
+ int ret;
+
+ mutex_lock(priv->reg_mutex);
+ mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
+ ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
+ ATC_MAT_MACTAB, NULL);
+ mutex_unlock(priv->reg_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_fdb_del);
+
+int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ const u8 *addr = mdb->addr;
+ u16 vid = mdb->vid;
+ u8 port_mask = 0;
+ u32 val;
+ int ret;
+
+ mutex_lock(priv->reg_mutex);
+
+ mt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
+ if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,
+ ATC_MAT_MACTAB, NULL)) {
+ regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP],
+ &val);
+ port_mask = val;
+ }
+
+ port_mask |= BIT(port);
+ mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
+ ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
+ ATC_MAT_MACTAB, NULL);
+
+ mutex_unlock(priv->reg_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_mdb_add);
+
+int mt7530_lib_port_mdb_del(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ const u8 *addr = mdb->addr;
+ u16 vid = mdb->vid;
+ u8 port_mask = 0;
+ u32 val;
+ int ret;
+
+ mutex_lock(priv->reg_mutex);
+
+ mt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
+ if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,
+ ATC_MAT_MACTAB, NULL)) {
+ regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP],
+ &val);
+ port_mask = val;
+ }
+
+ port_mask &= ~BIT(port);
+ mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1,
+ port_mask ? STATIC_ENT : STATIC_EMP);
+ ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
+ ATC_MAT_MACTAB, NULL);
+
+ mutex_unlock(priv->reg_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_mdb_del);
+
+int mt7530_lib_port_mirror_add(struct mt7530_lib_priv *priv, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress, struct netlink_ext_ack *extack)
+{
+ u32 monitor_port, val = 0;
+ int ret;
+
+ /* Check for existent entry */
+ if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
+ return -EEXIST;
+
+ regmap_field_read(priv->fields[MT7530_MIRROR_EN], &val);
+ ret = regmap_field_read(priv->fields[MT7530_MIRROR_PORT], &monitor_port);
+ if (ret)
+ return ret;
+
+ /* MT7530 only supports one monitor port */
+ if (val && monitor_port != mirror->to_local_port)
+ return -EEXIST;
+
+ regmap_field_write(priv->fields[MT7530_MIRROR_PORT],
+ mirror->to_local_port);
+ regmap_field_write(priv->fields[MT7530_MIRROR_EN], 1);
+
+ if (ingress) {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_RX_MIR], port, 1);
+ priv->mirror_rx |= BIT(port);
+ } else {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_TX_MIR], port, 1);
+ priv->mirror_tx |= BIT(port);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_mirror_add);
+
+void mt7530_lib_port_mirror_del(struct mt7530_lib_priv *priv, int port,
+ struct dsa_mall_mirror_tc_entry *mirror)
+{
+ if (mirror->ingress) {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_RX_MIR], port, 0);
+ priv->mirror_rx &= ~BIT(port);
+ } else {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_TX_MIR], port, 0);
+ priv->mirror_tx &= ~BIT(port);
+ }
+
+ if (!priv->mirror_rx && !priv->mirror_tx)
+ regmap_field_write(priv->fields[MT7530_MIRROR_EN], 0);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_mirror_del);
+
+int mt7530_lib_port_change_mtu(struct mt7530_lib_priv *priv, int port, int new_mtu)
+{
+ int length;
+
+ /* When a new MTU is set, DSA always set the CPU port's MTU to the
+ * largest MTU of the user ports. Because the switch only has a global
+ * RX length register, only allowing CPU port here is enough.
+ */
+ if (!dsa_is_cpu_port(priv->ds, port))
+ return 0;
+
+ /* RX length also includes Ethernet header, MTK tag, and FCS length */
+ length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
+ if (length <= 1522) {
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN],
+ MAX_RX_PKT_LEN_1522);
+ } else if (length <= 1536) {
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN],
+ MAX_RX_PKT_LEN_1536);
+ } else if (length <= 1552) {
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN],
+ MAX_RX_PKT_LEN_1552);
+ } else {
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_JUMBO],
+ DIV_ROUND_UP(length, 1024));
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN],
+ MAX_RX_PKT_LEN_JUMBO);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_change_mtu);
+
+void mt7530_lib_stp_state_set(struct mt7530_lib_priv *priv, int port, u8 state)
+{
+ u32 stp_state;
+
+ switch (state) {
+ case BR_STATE_DISABLED:
+ stp_state = MT7530_STP_DISABLED;
+ break;
+ case BR_STATE_BLOCKING:
+ stp_state = MT7530_STP_BLOCKING;
+ break;
+ case BR_STATE_LISTENING:
+ stp_state = MT7530_STP_LISTENING;
+ break;
+ case BR_STATE_LEARNING:
+ stp_state = MT7530_STP_LEARNING;
+ break;
+ case BR_STATE_FORWARDING:
+ default:
+ stp_state = MT7530_STP_FORWARDING;
+ break;
+ }
+
+ regmap_fields_update_bits(priv->fields[MT7530_SSP_FID_PST],
+ port, FID_PST_MASK(FID_BRIDGED),
+ FID_PST(FID_BRIDGED, stp_state));
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_stp_state_set);
+
+int mt7530_lib_port_bridge_flags(struct mt7530_lib_priv *priv, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct dsa_switch *ds = priv->ds;
+
+ if (flags.mask & BR_LEARNING)
+ regmap_fields_write(priv->fields[MT7530_PSC_SA_DIS],
+ port, !(flags.val & BR_LEARNING));
+
+ if (flags.mask & BR_FLOOD)
+ regmap_field_update_bits(priv->fields[MT7530_UNU_FFP],
+ BIT(port),
+ flags.val & BR_FLOOD ? BIT(port) : 0);
+
+ if (flags.mask & BR_MCAST_FLOOD)
+ regmap_field_update_bits(priv->fields[MT7530_UNM_FFP],
+ BIT(port),
+ flags.val & BR_MCAST_FLOOD ? BIT(port) : 0);
+
+ if (flags.mask & BR_BCAST_FLOOD)
+ regmap_field_update_bits(priv->fields[MT7530_BC_FFP],
+ BIT(port),
+ flags.val & BR_BCAST_FLOOD ? BIT(port) : 0);
+
+ if (flags.mask & BR_ISOLATED) {
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp);
+
+ priv->ports[port].isolated = !!(flags.val & BR_ISOLATED);
+
+ mutex_lock(priv->reg_mutex);
+ mt7530_update_port_member(priv, port, bridge_dev, true);
+ mutex_unlock(priv->reg_mutex);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_flags);
+
+int mt7530_lib_port_bridge_join(struct mt7530_lib_priv *priv, int port,
+ struct dsa_bridge bridge, bool *tx_fwd_offload,
+ struct netlink_ext_ack *extack)
+{
+ mutex_lock(priv->reg_mutex);
+
+ mt7530_update_port_member(priv, port, bridge.dev, true);
+
+ /* Set to fallback mode for independent VLAN learning */
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
+ port, MT7530_PORT_FALLBACK_MODE);
+
+ mutex_unlock(priv->reg_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_join);
+
+void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,
+ struct dsa_bridge bridge)
+{
+ mutex_lock(priv->reg_mutex);
+
+ mt7530_update_port_member(priv, port, bridge.dev, false);
+
+ /* When a port is removed from the bridge, the port would be set up
+ * back to the default as is at initial boot which is a VLAN-unaware
+ * port.
+ */
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
+ port, MT7530_PORT_MATRIX_MODE);
+
+ mutex_unlock(priv->reg_mutex);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_leave);
+
+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,
+ u16 pvid)
+{
+ regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+ port, pvid);
+ if (priv->fields[AN8855_PVID_G0_PORT_VID])
+ regmap_fields_write(priv->fields[AN8855_PVID_G0_PORT_VID],
+ port, pvid);
+}
+EXPORT_SYMBOL_GPL(mt7530_port_set_pvid);
+
+static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)
+{
+ struct dsa_switch *ds = priv->ds;
+ bool all_user_ports_removed = true;
+ int i;
+
+ /* This is called after .port_bridge_leave when leaving a VLAN-aware
+ * bridge. Don't set standalone ports to fallback mode.
+ */
+ if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
+ port, MT7530_PORT_FALLBACK_MODE);
+
+ regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR],
+ port, MT7530_VLAN_TRANSPARENT);
+ regmap_fields_write(priv->fields[MT7530_PVC_EG_TAG],
+ port, MT7530_VLAN_EG_CONSISTENT);
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_ALL);
+
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
+
+ for (i = 0; i < priv->ds->num_ports; i++) {
+ if (i == port)
+ continue;
+ if (dsa_is_user_port(ds, i) &&
+ dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
+ all_user_ports_removed = false;
+ break;
+ }
+ }
+
+ /* CPU port also does the same thing until all user ports belonging to
+ * the CPU port get out of VLAN filtering mode.
+ */
+ if (all_user_ports_removed) {
+ mutex_lock(priv->reg_mutex);
+ mt7530_lib_setup_vlan0(priv);
+ mutex_unlock(priv->reg_mutex);
+ }
+}
+
+static void mt7530_port_set_vlan_aware(struct mt7530_lib_priv *priv, int port)
+{
+ struct dsa_switch *ds = priv->ds;
+
+ /* Trapped into security mode allows packet forwarding through VLAN
+ * table lookup.
+ */
+ if (dsa_is_user_port(ds, port)) {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
+ port, MT7530_PORT_SECURITY_MODE);
+ mt7530_port_set_pvid(priv, port, priv->ports[port].pvid);
+
+ /* Only accept tagged frames if PVID is not set */
+ if (!priv->ports[port].pvid)
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_TAGGED);
+
+ /* Set the port as a user port which is to be able to recognize
+ * VID from incoming packets before fetching entry within the
+ * VLAN table.
+ */
+ regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR],
+ port, MT7530_VLAN_USER);
+ regmap_fields_write(priv->fields[MT7530_PVC_EG_TAG],
+ port, MT7530_VLAN_EG_DISABLED);
+ } else {
+ /* Also set CPU ports to the "user" VLAN port attribute, to
+ * allow VLAN classification, but keep the EG_TAG attribute as
+ * "consistent" (i.o.w. don't change its value) for packets
+ * received by the switch from the CPU, so that tagged packets
+ * are forwarded to user ports as tagged, and untagged as
+ * untagged.
+ */
+ regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR],
+ port, MT7530_VLAN_USER);
+ }
+}
+
+int mt7530_lib_port_vlan_filtering(struct mt7530_lib_priv *priv, int port, bool vlan_filtering,
+ struct netlink_ext_ack *extack)
+{
+ struct dsa_switch *ds = priv->ds;
+ struct dsa_port *cpu_dp, *dp;
+
+ dp = dsa_to_port(ds, port);
+ cpu_dp = dp->cpu_dp;
+
+ if (vlan_filtering) {
+ /* The port is being kept as VLAN-unaware port when bridge is
+ * set up with vlan_filtering not being set, Otherwise, the
+ * port and the corresponding CPU port is required the setup
+ * for becoming a VLAN-aware port.
+ */
+ mt7530_port_set_vlan_aware(priv, port);
+ mt7530_port_set_vlan_aware(priv, cpu_dp->index);
+ } else {
+ mt7530_port_set_vlan_unaware(priv, port);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_filtering);
+
+static int mt7530_vlan_cmd(struct mt7530_lib_priv *priv, enum mt7530_vlan_cmd cmd,
+ u16 vid)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_VTCR_FUNC], cmd);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_VTCR_VID], vid);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_VTCR_BUSY], 1);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_read_poll_timeout(priv->fields[MT7530_VTCR_BUSY],
+ val, !val, 20, 20000);
+ if (ret < 0) {
+ dev_err(priv->dev, "poll timeout\n");
+ return ret;
+ }
+
+ if (priv->fields[MT7530_VTCR_INVALID]) {
+ regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val);
+ if (val) {
+ dev_err(priv->dev, "read VTCR invalid\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static void mt7530_hw_vlan_add(struct mt7530_lib_priv *priv,
+ struct mt7530_hw_vlan_entry *entry)
+{
+ struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
+ u8 new_members;
+ u32 val;
+
+ new_members = entry->old_members | BIT(entry->port);
+
+ /* Validate the entry with independent learning, create egress tag per
+ * VLAN and joining the port as one of the port members.
+ */
+ regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM],
+ new_members);
+ regmap_field_write(priv->fields[MT7530_VAWD_FID],
+ FID_BRIDGED);
+ regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1);
+
+ /* Decide whether adding tag or not for those outgoing packets from the
+ * port inside the VLAN.
+ * CPU port is always taken as a tagged port for serving more than one
+ * VLANs across and also being applied with egress type stack mode for
+ * that VLAN tags would be appended after hardware special tag used as
+ * DSA tag.
+ */
+ if (dsa_port_is_cpu(dp))
+ val = MT7530_VLAN_EGRESS_STACK;
+ else if (entry->untagged)
+ val = MT7530_VLAN_EGRESS_UNTAG;
+ else
+ val = MT7530_VLAN_EGRESS_TAG;
+ regmap_field_update_bits(priv->fields[MT7530_VAWD_ETAG],
+ ETAG_CTRL_P_MASK(entry->port),
+ ETAG_CTRL_P(entry->port, val));
+}
+
+static void mt7530_hw_vlan_del(struct mt7530_lib_priv *priv,
+ struct mt7530_hw_vlan_entry *entry)
+{
+ u8 new_members;
+ u32 val;
+
+ new_members = entry->old_members & ~BIT(entry->port);
+
+ regmap_field_read(priv->fields[MT7530_VAWD_VLAN_VALID], &val);
+ if (!val) {
+ dev_err(priv->dev,
+ "Cannot be deleted due to invalid entry\n");
+ return;
+ }
+
+ if (new_members) {
+ regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM],
+ new_members);
+ regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1);
+ } else {
+ regmap_field_write(priv->fields[__MT7530_VAWD1], 0);
+ regmap_field_write(priv->fields[__MT7530_VAWD2], 0);
+ }
+}
+
+static void mt7530_hw_vlan_update(struct mt7530_lib_priv *priv, u16 vid,
+ struct mt7530_hw_vlan_entry *entry,
+ mt7530_vlan_op vlan_op)
+{
+ u32 val = 0;
+
+ /* Fetch entry */
+ mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
+
+ regmap_field_read(priv->fields[MT7530_VAWD_PORT_MEM], &val);
+ entry->old_members = val;
+
+ /* Manipulate entry */
+ vlan_op(priv, entry);
+
+ /* Flush result to hardware */
+ mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
+}
+
+int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
+ bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
+ struct mt7530_hw_vlan_entry new_entry;
+ struct dsa_switch *ds = priv->ds;
+
+ mutex_lock(priv->reg_mutex);
+
+ /* VID 0 is managed exclusively by mt7530_lib_setup_vlan0() for
+ * VLAN-unaware bridge operation. Don't let the bridge overwrite
+ * its EG_CON flag with VTAG_EN and corrupt PORT_MEM.
+ */
+ if (vlan->vid == 0)
+ goto skip_vlan_table;
+
+ mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
+ mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
+
+skip_vlan_table:
+
+ if (pvid) {
+ priv->ports[port].pvid = vlan->vid;
+
+ /* Accept all frames if PVID is set */
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_ALL);
+
+ /* Only configure PVID if VLAN filtering is enabled */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
+ mt7530_port_set_pvid(priv, port, vlan->vid);
+ } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
+ /* This VLAN is overwritten without PVID, so unset it */
+ priv->ports[port].pvid = G0_PORT_VID_DEF;
+
+ /* Only accept tagged frames if the port is VLAN-aware */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_TAGGED);
+
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
+ }
+
+ mutex_unlock(priv->reg_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_add);
+
+int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ struct mt7530_hw_vlan_entry target_entry;
+ struct dsa_switch *ds = priv->ds;
+
+ mutex_lock(priv->reg_mutex);
+
+ /* VID 0 is managed exclusively by mt7530_lib_setup_vlan0(). */
+ if (vlan->vid == 0)
+ goto skip_vlan_table;
+
+ mt7530_hw_vlan_entry_init(&target_entry, port, 0);
+ mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
+ mt7530_hw_vlan_del);
+
+skip_vlan_table:
+ /* PVID is being restored to the default whenever the PVID port
+ * is being removed from the VLAN.
+ */
+ if (priv->ports[port].pvid == vlan->vid) {
+ priv->ports[port].pvid = G0_PORT_VID_DEF;
+
+ /* Only accept tagged frames if the port is VLAN-aware */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_TAGGED);
+
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
+ }
+
+ mutex_unlock(priv->reg_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_del);
+
+int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv)
+{
+ /* Clear VAWD registers from previous access */
+ regmap_field_write(priv->fields[__MT7530_VAWD1], 0);
+ regmap_field_write(priv->fields[__MT7530_VAWD2], 0);
+
+ regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 0);
+ regmap_field_write(priv->fields[MT7530_VAWD_EG_CON], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM],
+ MT7530_ALL_MEMBERS);
+ regmap_field_write(priv->fields[MT7530_VAWD_FID],
+ FID_BRIDGED);
+ regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1);
+ regmap_field_write(priv->fields[__MT7530_VAWD2], 0);
+
+ return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_setup_vlan0);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Library Driver for Mediatek MT7530 Based Switch");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/mt7530-lib.h b/drivers/net/dsa/mt7530-lib.h
new file mode 100644
index 0000000000000..1465eb49f4cb2
--- /dev/null
+++ b/drivers/net/dsa/mt7530-lib.h
@@ -0,0 +1,413 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __MT7530_LIB_H
+#define __MT7530_LIB_H
+
+#define G0_PORT_VID_DEF 0
+#define MT7530_ALL_MEMBERS 0xff
+
+#define MTK_HDR_LEN 4
+#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
+
+/* MT7530_ATA1 */
+#define STATIC_EMP 0
+#define STATIC_ENT 3
+
+#define ATC_MAT_MACTAB 0
+#define ATC_MAT_NON_STATIC_MAC 4
+
+enum mt7530_fdb_cmd {
+ MT7530_FDB_READ = 0,
+ MT7530_FDB_WRITE = 1,
+ MT7530_FDB_FLUSH = 2,
+ MT7530_FDB_START = 4,
+ MT7530_FDB_NEXT = 5,
+};
+
+enum mt7530_max_rx_pkt_len {
+ MAX_RX_PKT_LEN_1522 = 0,
+ MAX_RX_PKT_LEN_1536 = 1,
+ MAX_RX_PKT_LEN_1552 = 2,
+ MAX_RX_PKT_LEN_JUMBO = 3,
+};
+
+#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
+#define FID_PST_MASK(fid) FID_PST(fid, 0x3)
+
+enum mt7530_stp_state {
+ MT7530_STP_DISABLED = 0,
+ MT7530_STP_BLOCKING = 1,
+ MT7530_STP_LISTENING = 1,
+ MT7530_STP_LEARNING = 2,
+ MT7530_STP_FORWARDING = 3
+};
+
+/* Egress Tag Control */
+#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
+#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
+
+enum mt753x_to_cpu_fw {
+ TO_CPU_FW_SYSTEM_DEFAULT,
+ TO_CPU_FW_CPU_EXCLUDE = 4,
+ TO_CPU_FW_CPU_INCLUDE = 5,
+ TO_CPU_FW_CPU_ONLY = 6,
+ TO_CPU_FW_DROP = 7,
+};
+
+enum mt7530_port_mode {
+ /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
+ MT7530_PORT_MATRIX_MODE = 0,
+
+ /* Fallback Mode: Forward received frames with ingress ports that do
+ * not belong to the VLAN member. Frames whose VID is not listed on
+ * the VLAN table are forwarded by the PCR_MATRIX members.
+ */
+ MT7530_PORT_FALLBACK_MODE = 1,
+
+ /* Security Mode: Discard any frame due to ingress membership
+ * violation or VID missed on the VLAN table.
+ */
+ MT7530_PORT_SECURITY_MODE = 3,
+};
+
+enum mt7530_vlan_port_acc_frm {
+ MT7530_VLAN_ACC_ALL = 0,
+ MT7530_VLAN_ACC_TAGGED = 1,
+ MT7530_VLAN_ACC_UNTAGGED = 2,
+};
+
+enum mt7530_vlan_port_eg_tag {
+ MT7530_VLAN_EG_DISABLED = 0,
+ MT7530_VLAN_EG_CONSISTENT = 1,
+ MT7530_VLAN_EG_UNTAGGED = 4,
+};
+
+enum mt7530_vlan_port_attr {
+ MT7530_VLAN_USER = 0,
+ MT7530_VLAN_TRANSPARENT = 3,
+};
+
+enum mt7530_fid {
+ FID_STANDALONE = 0,
+ FID_BRIDGED = 1,
+};
+
+enum mt7530_vlan_egress_attr {
+ MT7530_VLAN_EGRESS_UNTAG = 0,
+ MT7530_VLAN_EGRESS_TAG = 2,
+ MT7530_VLAN_EGRESS_STACK = 3,
+};
+
+enum mt7530_vlan_cmd {
+ /* Read/Write the specified VID entry from VAWD register based
+ * on VID.
+ */
+ MT7530_VTCR_RD_VID = 0,
+ MT7530_VTCR_WR_VID = 1,
+};
+
+enum mt7530_regmap_field {
+ MT7530_MIRROR_EN,
+ MT7530_MIRROR_PORT,
+
+ MT7530_UNU_FFP,
+ MT7530_UNM_FFP,
+ MT7530_BC_FFP,
+
+ MT7530_CCR_MIB_ENABLE,
+ MT7530_CCR_RX_OCT_CNT_GOOD,
+ MT7530_CCR_RX_OCT_CNT_BAD,
+ MT7530_CCR_TX_OCT_CNT_GOOD,
+ MT7530_CCR_TX_OCT_CNT_BAD,
+
+ MT7530_BPDU_EG_TAG,
+ MT7530_BPDU_PORT_FW,
+ MT7530_PAE_BPDU_FR,
+ MT7530_PAE_EG_TAG,
+ MT7530_PAE_PORT_FW,
+ MT7530_R01_BPDU_FR,
+ MT7530_R01_EG_TAG,
+ MT7530_R01_PORT_FW,
+ MT7530_R02_BPDU_FR,
+ MT7530_R02_EG_TAG,
+ MT7530_R02_PORT_FW,
+ MT7530_R03_BPDU_FR,
+ MT7530_R03_EG_TAG,
+ MT7530_R03_PORT_FW,
+ MT7530_R0E_BPDU_FR,
+ MT7530_R0E_EG_TAG,
+ MT7530_R0E_PORT_FW,
+
+ MT7530_VAWD_IVL_MAC,
+ MT7530_VAWD_EG_CON,
+ MT7530_VAWD_VTAG_EN,
+ MT7530_VAWD_PORT_MEM,
+ MT7530_VAWD_FID,
+ MT7530_VAWD_VLAN_VALID,
+ __MT7530_VAWD1,
+
+ MT7530_VAWD_ETAG,
+ __MT7530_VAWD2,
+
+ MT7530_VTCR_BUSY,
+ MT7530_VTCR_FUNC,
+ MT7530_VTCR_VID,
+ MT7530_VTCR_INVALID,
+
+ MT7530_ATWD_CVID,
+ MT7530_ATWD_IVL,
+ MT7530_ATWD_FID,
+ MT7530_ATWD_AGE_TIMER,
+ MT7530_ATWD_PORT_MAP,
+ MT7530_ATWD_ENT_STATUS,
+ AN8855_ATWD_TYPE,
+ AN8855_ATWD_VLD,
+ MT7530_ATWD_MAC_BYTE_5,
+ MT7530_ATWD_MAC_BYTE_4,
+ MT7530_ATWD_MAC_BYTE_3,
+ MT7530_ATWD_MAC_BYTE_2,
+ MT7530_ATWD_MAC_BYTE_1,
+ MT7530_ATWD_MAC_BYTE_0,
+
+ __MT7530_ATWD1,
+ __MT7530_ATWD2,
+ __MT7530_ATWD3,
+ __MT7530_ATWD4,
+
+ MT7530_ATRD_CVID,
+ MT7530_ATRD_AGE_TIMER,
+ MT7530_ATRD_PORT_MAP,
+ MT7530_ATRD_ENT_STATUS,
+ AN8855_ATRD_ARP,
+ MT7530_ATRD_MAC_BYTE_5,
+ MT7530_ATRD_MAC_BYTE_4,
+ MT7530_ATRD_MAC_BYTE_3,
+ MT7530_ATRD_MAC_BYTE_2,
+ MT7530_ATRD_MAC_BYTE_1,
+ MT7530_ATRD_MAC_BYTE_0,
+
+ MT7530_ATC_BUSY,
+ MT7530_ATC_MAT,
+ MT7530_ATC_INVALID,
+ MT7530_ATC_CMD,
+ __MT7530_ATC,
+
+ MT7530_SSP_FID_PST,
+
+ MT7530_PCR_PORT_TX_MIR,
+ MT7530_PCR_PORT_RX_MIR,
+ MT7530_PCR_PORT_VLAN,
+ MT7530_PCR_MATRIX,
+
+ MT7530_PSC_SA_DIS,
+
+ MT7530_PVC_EG_TAG,
+ MT7530_PVC_VLAN_ATTR,
+ MT7530_PVC_ACC_FRM,
+
+ MT7530_PPBV1_G0_PORT_VID,
+ AN8855_PVID_G0_PORT_VID,
+
+ MT7530_GMACCR_MAX_RX_JUMBO,
+ MT7530_GMACCR_MAX_RX_PKT_LEN,
+
+ MT7530_MIB_TX_DROP,
+ MT7530_MIB_TX_CRC_ERR,
+ MT7530_MIB_TX_UNICAST,
+ MT7530_MIB_TX_MULTICAST,
+ MT7530_MIB_TX_BROADCAST,
+ MT7530_MIB_TX_COLLISION,
+ MT7530_MIB_TX_SINGLE_COLLISION,
+ MT7530_MIB_TX_MULTIPLE_COLLISION,
+ MT7530_MIB_TX_DEFERRED,
+ MT7530_MIB_TX_LATE_COLLISION,
+ MT7530_MIB_TX_EXCESSIVE_COLLISION,
+ MT7530_MIB_TX_PAUSE,
+ MT7530_MIB_TX_PKT_SZ_64,
+ MT7530_MIB_TX_PKT_SZ_65_TO_127,
+ MT7530_MIB_TX_PKT_SZ_128_TO_255,
+ MT7530_MIB_TX_PKT_SZ_256_TO_511,
+ MT7530_MIB_TX_PKT_SZ_512_TO_1023,
+ MT7530_MIB_TX_PKT_SZ_1024_TO_MAX,
+ AN8855_MIB_TX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_TX_PKT_SZ_1519_TO_MAX,
+ MT7530_MIB_TX_BYTES_LOW,
+ MT7530_MIB_TX_BYTES_HIGH,
+ AN8855_MIB_TX_OVERSIZE_DROP,
+ AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_TX_BAD_PKT_BYTES_HIGH,
+ MT7530_MIB_RX_DROP,
+ MT7530_MIB_RX_FILTERING,
+ MT7530_MIB_RX_UNICAST,
+ MT7530_MIB_RX_MULTICAST,
+ MT7530_MIB_RX_BROADCAST,
+ MT7530_MIB_RX_ALIGN_ERR,
+ MT7530_MIB_RX_CRC_ERR,
+ MT7530_MIB_RX_UNDER_SIZE_ERR,
+ MT7530_MIB_RX_FRAG_ERR,
+ MT7530_MIB_RX_OVER_SZ_ERR,
+ MT7530_MIB_RX_JABBER_ERR,
+ MT7530_MIB_RX_PAUSE,
+ MT7530_MIB_RX_PKT_SZ_64,
+ MT7530_MIB_RX_PKT_SZ_65_TO_127,
+ MT7530_MIB_RX_PKT_SZ_128_TO_255,
+ MT7530_MIB_RX_PKT_SZ_256_TO_511,
+ MT7530_MIB_RX_PKT_SZ_512_TO_1023,
+ MT7530_MIB_RX_PKT_SZ_1024_TO_MAX,
+ AN8855_MIB_RX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_RX_PKT_SZ_1519_TO_MAX,
+ MT7530_MIB_RX_BYTES_LOW,
+ MT7530_MIB_RX_BYTES_HIGH,
+ MT7530_MIB_RX_CTRL_DROP,
+ MT7530_MIB_RX_INGRESS_DROP,
+ MT7530_MIB_RX_ARL_DROP,
+ AN8855_MIB_FLOW_CONTROL_DROP,
+ AN8855_MIB_WRED_DROP,
+ AN8855_MIB_MIRROR_DROP,
+ AN8855_MIB_RX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_RX_BAD_PKT_BYTES_HIGH,
+ AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP,
+ AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP,
+ AN8855_MIB_PORT_CONTROL_DROP,
+
+ MT7530_FIELD_MAX,
+};
+
+struct mt7530_fdb {
+ u16 vid;
+ u8 port_mask;
+ u8 aging;
+ u8 mac[6];
+ bool noarp;
+};
+
+struct mt7530_hw_vlan_entry {
+ int port;
+ u8 old_members;
+ bool untagged;
+};
+
+static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
+ int port, bool untagged)
+{
+ e->port = port;
+ e->untagged = untagged;
+}
+
+#define MIB_DESC(_fl, _fh, _n) \
+ { \
+ .field_low = (_fl), \
+ .field_high = (_fh), \
+ .name = (_n), \
+ }
+
+struct mt7530_mib_desc {
+ int field_low;
+ int field_high;
+ const char *name;
+};
+
+struct mt7530_rmon_hist {
+ unsigned int *ranges_fields;
+ unsigned int *ranges_tx_fields;
+ const struct ethtool_rmon_hist_range *ranges;
+ unsigned int num_ranges;
+};
+
+struct mt7530_reg_field {
+ unsigned int id;
+ const struct reg_field field;
+};
+
+/* struct mt7530_port - This is the main data structure for holding the state
+ * of the port.
+ * @enable: The status used for show port is enabled or not.
+ * @pm: The matrix used to show all connections with the port.
+ * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
+ * untagged frames will be assigned to the related VLAN.
+ * @sgmii_pcs: Pointer to PCS instance for SerDes ports
+ * @stats: Cached port statistics for MDIO-connected switches
+ */
+struct mt7530_port {
+ bool enable;
+ bool isolated;
+ u32 pm;
+ u16 pvid;
+ struct phylink_pcs *sgmii_pcs;
+ struct rtnl_link_stats64 stats;
+};
+
+struct mt7530_lib_priv {
+ struct device *dev;
+ struct dsa_switch *ds;
+ struct regmap *regmap;
+ struct regmap_field *fields[MT7530_FIELD_MAX];
+
+ u8 mirror_rx;
+ u8 mirror_tx;
+
+ struct mt7530_port *ports;
+ struct mutex *reg_mutex;
+};
+
+typedef void (*mt7530_vlan_op)(struct mt7530_lib_priv *,
+ struct mt7530_hw_vlan_entry *);
+
+void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv);
+void mt7530_lib_trap_frames(struct mt7530_lib_priv *priv);
+
+void mt7530_lib_read_port_stats(struct regmap_field *low,
+ struct regmap_field *high,
+ int port, uint64_t *data);
+void mt7530_lib_get_eth_mac_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_eth_mac_stats *mac_stats);
+void mt7530_lib_get_rmon_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges,
+ const struct mt7530_rmon_hist *ranges_info);
+void mt7530_lib_get_eth_ctrl_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats);
+int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
+ u32 mat, u32 *rsp);
+void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb);
+void mt7530_lib_port_fast_age(struct mt7530_lib_priv *priv, int port);
+int mt7530_lib_port_fdb_add(struct mt7530_lib_priv *priv, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db);
+int mt7530_lib_port_fdb_del(struct mt7530_lib_priv *priv, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db);
+int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db);
+int mt7530_lib_port_mdb_del(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db);
+void mt7530_lib_port_mirror_del(struct mt7530_lib_priv *priv, int port,
+ struct dsa_mall_mirror_tc_entry *mirror);
+int mt7530_lib_port_mirror_add(struct mt7530_lib_priv *priv, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress, struct netlink_ext_ack *extack);
+int mt7530_lib_port_change_mtu(struct mt7530_lib_priv *priv, int port, int new_mtu);
+void mt7530_lib_stp_state_set(struct mt7530_lib_priv *priv, int port, u8 state);
+int mt7530_lib_port_bridge_flags(struct mt7530_lib_priv *priv, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack);
+int mt7530_lib_port_bridge_join(struct mt7530_lib_priv *priv, int port,
+ struct dsa_bridge bridge, bool *tx_fwd_offload,
+ struct netlink_ext_ack *extack);
+void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,
+ struct dsa_bridge bridge);
+int mt7530_lib_port_vlan_filtering(struct mt7530_lib_priv *priv, int port, bool vlan_filtering,
+ struct netlink_ext_ack *extack);
+int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack);
+int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_vlan *vlan);
+
+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,
+ u16 pvid);
+int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv);
+
+#endif /* __MT7530_LIB_H */
+
diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c
index 24ef54f3db2a6..38fde73e56459 100644
--- a/drivers/net/dsa/mt7530-mdio.c
+++ b/drivers/net/dsa/mt7530-mdio.c
@@ -218,6 +218,10 @@ mt7530_probe(struct mdio_device *mdiodev)
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
+ ret = mt7530_setup_lib_priv(priv);
+ if (ret)
+ return ret;
+
if (priv->id == ID_MT7531)
priv->create_sgmii = mt7531_create_sgmii;
diff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mt7530-mmio.c
index cf3bdb23a2d54..2dcb2bb545b9b 100644
--- a/drivers/net/dsa/mt7530-mmio.c
+++ b/drivers/net/dsa/mt7530-mmio.c
@@ -61,6 +61,10 @@ mt7988_probe(struct platform_device *pdev)
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
+ ret = mt7530_setup_lib_priv(priv);
+ if (ret)
+ return ret;
+
return dsa_register_switch(priv->ds);
}
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 14692497e1a61..5470f049c6d88 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -24,10 +24,163 @@
#include <net/pkt_cls.h>
#include "mt7530.h"
+#include "mt7530-lib.h"
#define MT7530_STATS_POLL_INTERVAL (1 * HZ)
#define MT7530_STATS_RATE_LIMIT (HZ / 10)
+static const struct mt7530_reg_field mt753x_fields[] = {
+ { MT7530_BC_FFP, REG_FIELD(MT753X_MFC, 24, 31) },
+ { MT7530_UNM_FFP, REG_FIELD(MT753X_MFC, 16, 23) },
+ { MT7530_UNU_FFP, REG_FIELD(MT753X_MFC, 8, 15) },
+
+ { MT7530_CCR_MIB_ENABLE, REG_FIELD(MT7530_MIB_CCR, 31, 31) },
+ { MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(MT7530_MIB_CCR, 7, 7) },
+ { MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(MT7530_MIB_CCR, 6, 6) },
+ { MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(MT7530_MIB_CCR, 5, 5) },
+ { MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(MT7530_MIB_CCR, 4, 4) },
+
+ { MT7530_BPDU_EG_TAG, REG_FIELD(MT753X_BPC, 6, 8) },
+ { MT7530_BPDU_PORT_FW, REG_FIELD(MT753X_BPC, 0, 2) },
+ { MT7530_PAE_BPDU_FR, REG_FIELD(MT753X_BPC, 25, 25) },
+ { MT7530_PAE_EG_TAG, REG_FIELD(MT753X_BPC, 22, 24) },
+ { MT7530_PAE_PORT_FW, REG_FIELD(MT753X_BPC, 16, 18) },
+ { MT7530_R01_BPDU_FR, REG_FIELD(MT753X_RGAC1, 9, 9) },
+ { MT7530_R01_EG_TAG, REG_FIELD(MT753X_RGAC1, 6, 8) },
+ { MT7530_R01_PORT_FW, REG_FIELD(MT753X_RGAC1, 0, 2) },
+ { MT7530_R02_BPDU_FR, REG_FIELD(MT753X_RGAC1, 25, 25) },
+ { MT7530_R02_EG_TAG, REG_FIELD(MT753X_RGAC1, 22, 24) },
+ { MT7530_R02_PORT_FW, REG_FIELD(MT753X_RGAC1, 16, 18) },
+ { MT7530_R03_BPDU_FR, REG_FIELD(MT753X_RGAC2, 9, 9) },
+ { MT7530_R03_EG_TAG, REG_FIELD(MT753X_RGAC2, 6, 8) },
+ { MT7530_R03_PORT_FW, REG_FIELD(MT753X_RGAC2, 0, 2) },
+ { MT7530_R0E_BPDU_FR, REG_FIELD(MT753X_RGAC2, 25, 25) },
+ { MT7530_R0E_EG_TAG, REG_FIELD(MT753X_RGAC2, 22, 24) },
+ { MT7530_R0E_PORT_FW, REG_FIELD(MT753X_RGAC2, 16, 18) },
+
+ { MT7530_VAWD_IVL_MAC, REG_FIELD(MT7530_VAWD1, 30, 30) },
+ { MT7530_VAWD_EG_CON, REG_FIELD(MT7530_VAWD1, 29, 29) },
+ { MT7530_VAWD_VTAG_EN, REG_FIELD(MT7530_VAWD1, 28, 28) },
+ { MT7530_VAWD_PORT_MEM, REG_FIELD(MT7530_VAWD1, 16, 23) },
+ { MT7530_VAWD_FID, REG_FIELD(MT7530_VAWD1, 1, 3) },
+ { MT7530_VAWD_VLAN_VALID, REG_FIELD(MT7530_VAWD1, 0, 0) },
+ { __MT7530_VAWD1, REG_FIELD(MT7530_VAWD1, 0, 31) },
+
+ { MT7530_VAWD_ETAG, REG_FIELD(MT7530_VAWD2, 0, 15) },
+ { __MT7530_VAWD2, REG_FIELD(MT7530_VAWD2, 0, 31) },
+
+ { MT7530_VTCR_BUSY, REG_FIELD(MT7530_VTCR, 31, 31) },
+ { MT7530_VTCR_INVALID, REG_FIELD(MT7530_VTCR, 16, 16) },
+ { MT7530_VTCR_FUNC, REG_FIELD(MT7530_VTCR, 12, 15) },
+ { MT7530_VTCR_VID, REG_FIELD(MT7530_VTCR, 0, 11) },
+
+ { MT7530_ATWD_CVID, REG_FIELD(MT7530_ATA2, 0, 11), },
+ { MT7530_ATWD_IVL, REG_FIELD(MT7530_ATA2, 15, 15), },
+ { MT7530_ATWD_FID, REG_FIELD(MT7530_ATA2, 12, 14), },
+ { MT7530_ATWD_AGE_TIMER, REG_FIELD(MT7530_ATWD, 24, 31), },
+ { MT7530_ATWD_PORT_MAP, REG_FIELD(MT7530_ATWD, 4, 11), },
+ { MT7530_ATWD_ENT_STATUS, REG_FIELD(MT7530_ATWD, 2, 3), },
+ { MT7530_ATWD_MAC_BYTE_5, REG_FIELD(MT7530_ATA2, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_4, REG_FIELD(MT7530_ATA2, 24, 31), },
+ { MT7530_ATWD_MAC_BYTE_3, REG_FIELD(MT7530_ATA1, 0, 7), },
+ { MT7530_ATWD_MAC_BYTE_2, REG_FIELD(MT7530_ATA1, 8, 15), },
+ { MT7530_ATWD_MAC_BYTE_1, REG_FIELD(MT7530_ATA1, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_0, REG_FIELD(MT7530_ATA1, 24, 31), },
+
+ { __MT7530_ATWD1, REG_FIELD(MT7530_ATWD, 0, 31), },
+ { __MT7530_ATWD2, REG_FIELD(MT7530_ATA1, 0, 31), },
+ { __MT7530_ATWD3, REG_FIELD(MT7530_ATA2, 0, 31), },
+
+ { MT7530_ATRD_CVID, REG_FIELD(MT7530_TSRA2, 0, 11), },
+ { MT7530_ATRD_AGE_TIMER, REG_FIELD(MT7530_ATRD, 24, 31), },
+ { MT7530_ATRD_PORT_MAP, REG_FIELD(MT7530_ATRD, 4, 11), },
+ { MT7530_ATRD_ENT_STATUS, REG_FIELD(MT7530_ATRD, 2, 3), },
+ { MT7530_ATRD_MAC_BYTE_5, REG_FIELD(MT7530_TSRA2, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_4, REG_FIELD(MT7530_TSRA2, 24, 31), },
+ { MT7530_ATRD_MAC_BYTE_3, REG_FIELD(MT7530_TSRA1, 0, 7), },
+ { MT7530_ATRD_MAC_BYTE_2, REG_FIELD(MT7530_TSRA1, 8, 15), },
+ { MT7530_ATRD_MAC_BYTE_1, REG_FIELD(MT7530_TSRA1, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_0, REG_FIELD(MT7530_TSRA1, 24, 31), },
+
+ { MT7530_ATC_BUSY, REG_FIELD(MT7530_ATC, 15, 15), },
+ { MT7530_ATC_INVALID, REG_FIELD(MT7530_ATC, 12, 12), },
+ { MT7530_ATC_MAT, REG_FIELD(MT7530_ATC, 8, 11), },
+ { MT7530_ATC_CMD, REG_FIELD(MT7530_ATC, 0, 2), },
+ { __MT7530_ATC, REG_FIELD(MT7530_ATC, 0, 31), },
+
+ { MT7530_SSP_FID_PST, REG_FIELD_ID(MT7530_SSP, 0, 15, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(MT7530_PCR, 9, 9, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(MT7530_PCR, 8, 8, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PCR_PORT_VLAN, REG_FIELD_ID(MT7530_PCR, 0, 1, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PCR_MATRIX, REG_FIELD_ID(MT7530_PCR, 16, 23, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_PSC_SA_DIS, REG_FIELD_ID(MT7530_PSC, 4, 4, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_PVC_EG_TAG, REG_FIELD_ID(MT7530_PVC, 8, 10, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(MT7530_PVC, 6, 7, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PVC_ACC_FRM, REG_FIELD_ID(MT7530_PVC, 0, 1, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(MT7530_PPBV1, 0, 11, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(MT7530_GMACCR, 2, 5) },
+ { MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(MT7530_GMACCR, 0, 1) },
+
+ { MT7530_MIB_TX_DROP, REG_FIELD_ID(MT7530_PORT_MIB_TX_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(MT7530_PORT_MIB_TX_CRC_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_UNICAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_UNICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_MULTICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_BROADCAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_SINGLE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(MT7530_PORT_MIB_TX_DEFERRED, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_LATE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PAUSE, REG_FIELD_ID(MT7530_PORT_MIB_TX_PAUSE, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_64, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_1024_TO_MAX, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(MT7530_PORT_MIB_TX_BYTES_LOW, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(MT7530_PORT_MIB_TX_BYTES_HIGH, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_FILTERING, REG_FIELD_ID(MT7530_PORT_MIB_RX_FILTERING, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_UNICAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_UNICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_MULTICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_BROADCAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_ALIGN_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_CRC_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_FRAG_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_OVER_SZ_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_JABBER_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PAUSE, REG_FIELD_ID(MT7530_PORT_MIB_RX_PAUSE, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_64, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_1024_TO_MAX, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(MT7530_PORT_MIB_RX_BYTES_LOW, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(MT7530_PORT_MIB_RX_BYTES_HIGH, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_CTRL_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_INGRESS_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_ARL_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+};
+
+static const struct mt7530_reg_field mt7530_fields[] = {
+ { MT7530_MIRROR_EN, REG_FIELD(MT753X_MFC, 3, 3) },
+ { MT7530_MIRROR_PORT, REG_FIELD(MT753X_MFC, 0, 2) },
+};
+
+static const struct mt7530_reg_field mt7531_fields[] = {
+ { MT7530_MIRROR_EN, REG_FIELD(MT7531_CFC, 19, 19) },
+ { MT7530_MIRROR_PORT, REG_FIELD(MT7531_CFC, 16, 18) },
+};
+
static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
{
return container_of(pcs, struct mt753x_pcs, pcs);
@@ -35,15 +188,15 @@ static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
/* String, offset, and register size in bytes if different from 4 bytes */
static const struct mt7530_mib_desc mt7530_mib[] = {
- MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"),
- MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"),
- MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"),
+ MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
+ MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
+ MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
+ MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
+ MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
+ MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),
+ MIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, "RxCtrlDrop"),
+ MIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, "RxIngressDrop"),
+ MIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, "RxArlDrop"),
};
static void
@@ -154,115 +307,11 @@ core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
core_rmw(priv, reg, val, 0);
}
-static int
-mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
-{
- u32 val;
- int ret;
-
- /* Set the command operating upon the MAC address entries */
- val = ATC_BUSY | ATC_MAT(0) | cmd;
- ret = regmap_write(priv->regmap, MT7530_ATC, val);
- if (ret)
- return ret;
-
- ret = regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val,
- !(val & ATC_BUSY), 20, 20000);
- if (!ret)
- ret = regmap_read(priv->regmap, MT7530_ATC, &val);
-
- if (ret < 0) {
- dev_err(priv->dev, "reset timeout\n");
- return ret;
- }
-
- /* Additional sanity for read command if the specified
- * entry is invalid
- */
- if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
- return -EINVAL;
-
- if (rsp)
- *rsp = val;
-
- return 0;
-}
-
static void mt7530_port_fast_age(struct dsa_switch *ds, int port)
{
struct mt7530_priv *priv = ds->priv;
- u32 val;
- int ret;
-
- mutex_lock(&priv->reg_mutex);
-
- /* Flush all non-static MAC address entries */
- val = ATC_BUSY | ATC_MAT_NON_STATIC_MAC | MT7530_FDB_FLUSH;
- ret = regmap_write(priv->regmap, MT7530_ATC, val);
- if (!ret)
- ret = regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val,
- !(val & ATC_BUSY), 20, 20000);
- if (ret < 0)
- dev_err(priv->dev, "fast age failed: %d\n", ret);
-
- mutex_unlock(&priv->reg_mutex);
-}
-
-static void
-mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
-{
- u32 reg[3];
- int i;
-
- /* Read from ARL table into an array */
- for (i = 0; i < 3; i++) {
- regmap_read(priv->regmap, MT7530_TSRA1 + (i * 4),
- ®[i]);
-
- dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
- __func__, __LINE__, i, reg[i]);
- }
- fdb->vid = FIELD_GET(CVID_MASK, reg[1]);
- fdb->aging = FIELD_GET(AGE_TIMER_MASK, reg[2]);
- fdb->port_mask = FIELD_GET(PORT_MAP_MASK, reg[2]);
- fdb->mac[0] = FIELD_GET(MAC_BYTE_0_MASK, reg[0]);
- fdb->mac[1] = FIELD_GET(MAC_BYTE_1_MASK, reg[0]);
- fdb->mac[2] = FIELD_GET(MAC_BYTE_2_MASK, reg[0]);
- fdb->mac[3] = FIELD_GET(MAC_BYTE_3_MASK, reg[0]);
- fdb->mac[4] = FIELD_GET(MAC_BYTE_4_MASK, reg[1]);
- fdb->mac[5] = FIELD_GET(MAC_BYTE_5_MASK, reg[1]);
- fdb->noarp = FIELD_GET(ENT_STATUS_MASK, reg[2]) == STATIC_ENT;
-}
-
-static void
-mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
- u8 port_mask, const u8 *mac,
- u8 aging, u8 type)
-{
- u32 reg[3] = { 0 };
- int i;
-
- reg[1] |= FIELD_PREP(CVID_MASK, vid);
- reg[1] |= ATA2_IVL;
- reg[1] |= ATA2_FID(FID_BRIDGED);
- reg[2] |= FIELD_PREP(AGE_TIMER_MASK, aging);
- reg[2] |= FIELD_PREP(PORT_MAP_MASK, port_mask);
- /* STATIC_ENT indicate that entry is static wouldn't
- * be aged out and STATIC_EMP specified as erasing an
- * entry
- */
- reg[2] |= FIELD_PREP(ENT_STATUS_MASK, type);
- reg[1] |= FIELD_PREP(MAC_BYTE_5_MASK, mac[5]);
- reg[1] |= FIELD_PREP(MAC_BYTE_4_MASK, mac[4]);
- reg[0] |= FIELD_PREP(MAC_BYTE_3_MASK, mac[3]);
- reg[0] |= FIELD_PREP(MAC_BYTE_2_MASK, mac[2]);
- reg[0] |= FIELD_PREP(MAC_BYTE_1_MASK, mac[1]);
- reg[0] |= FIELD_PREP(MAC_BYTE_0_MASK, mac[0]);
-
- /* Write array into the ARL table */
- for (i = 0; i < 3; i++)
- regmap_write(priv->regmap, MT7530_ATA1 + (i * 4), reg[i]);
+ mt7530_lib_port_fast_age(&priv->lib_priv, port);
}
/* Set up switch core clock for MT7530 */
@@ -449,15 +498,6 @@ mt7531_pll_setup(struct mt7530_priv *priv)
usleep_range(25, 35);
}
-static void
-mt7530_mib_reset(struct dsa_switch *ds)
-{
- struct mt7530_priv *priv = ds->priv;
-
- regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_FLUSH);
- regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
-}
-
static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)
{
return mdiobus_read_nested(priv->bus, port, regnum);
@@ -702,34 +742,25 @@ mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
ethtool_puts(&data, mt7530_mib[i].name);
}
-static void
-mt7530_read_port_stats(struct mt7530_priv *priv, int port,
- u32 offset, u8 size, uint64_t *data)
-{
- u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset;
-
- regmap_read(priv->regmap, reg, &val);
- *data = val;
-
- if (size == 2) {
- regmap_read(priv->regmap, reg + 4, &val);
- *data |= (u64)val << 32;
- }
-}
-
static void
mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
uint64_t *data)
{
struct mt7530_priv *priv = ds->priv;
const struct mt7530_mib_desc *mib;
+ struct mt7530_lib_priv *lib_priv;
int i;
+ lib_priv = &priv->lib_priv;
for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
+ struct regmap_field *high = NULL;
mib = &mt7530_mib[i];
- mt7530_read_port_stats(priv, port, mib->offset, mib->size,
- data + i);
+ if (mib->field_high != -1)
+ high = lib_priv->fields[mib->field_high];
+
+ mt7530_lib_read_port_stats(lib_priv->fields[mib->field_low],
+ high, port, data + i);
}
}
@@ -747,54 +778,7 @@ static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- /* MIB counter doesn't provide a FramesTransmittedOK but instead
- * provide stats for Unicast, Broadcast and Multicast frames separately.
- * To simulate a global frame counter, read Unicast and addition Multicast
- * and Broadcast later
- */
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,
- &mac_stats->FramesTransmittedOK);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1,
- &mac_stats->SingleCollisionFrames);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1,
- &mac_stats->MultipleCollisionFrames);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,
- &mac_stats->FramesReceivedOK);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,
- &mac_stats->OctetsTransmittedOK);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1,
- &mac_stats->AlignmentErrors);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1,
- &mac_stats->FramesWithDeferredXmissions);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1,
- &mac_stats->LateCollisions);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1,
- &mac_stats->FramesAbortedDueToXSColls);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,
- &mac_stats->OctetsReceivedOK);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,
- &mac_stats->MulticastFramesXmittedOK);
- mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,
- &mac_stats->BroadcastFramesXmittedOK);
- mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK;
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,
- &mac_stats->MulticastFramesReceivedOK);
- mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,
- &mac_stats->BroadcastFramesReceivedOK);
- mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK;
+ return mt7530_lib_get_eth_mac_stats(&priv->lib_priv, port, mac_stats);
}
static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = {
@@ -807,53 +791,41 @@ static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = {
{}
};
+static const struct mt7530_rmon_hist mt7530_rmon_hist_info = {
+ .ranges_fields = (unsigned int []){
+ MT7530_MIB_RX_PKT_SZ_64,
+ MT7530_MIB_RX_PKT_SZ_65_TO_127,
+ MT7530_MIB_RX_PKT_SZ_128_TO_255,
+ MT7530_MIB_RX_PKT_SZ_256_TO_511,
+ MT7530_MIB_RX_PKT_SZ_512_TO_1023,
+ MT7530_MIB_RX_PKT_SZ_1024_TO_MAX,
+ },
+ .ranges_tx_fields = (unsigned int []){
+ MT7530_MIB_TX_PKT_SZ_64,
+ MT7530_MIB_TX_PKT_SZ_65_TO_127,
+ MT7530_MIB_TX_PKT_SZ_128_TO_255,
+ MT7530_MIB_TX_PKT_SZ_256_TO_511,
+ MT7530_MIB_TX_PKT_SZ_512_TO_1023,
+ MT7530_MIB_TX_PKT_SZ_1024_TO_MAX,
+ },
+ .ranges = mt7530_rmon_ranges,
+ .num_ranges = ARRAY_SIZE(mt7530_rmon_ranges) - 1,
+};
+
static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port,
struct ethtool_rmon_stats *rmon_stats,
const struct ethtool_rmon_hist_range **ranges)
{
struct mt7530_priv *priv = ds->priv;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1,
- &rmon_stats->undersize_pkts);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1,
- &rmon_stats->oversize_pkts);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1,
- &rmon_stats->fragments);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1,
- &rmon_stats->jabbers);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1,
- &rmon_stats->hist[0]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1,
- &rmon_stats->hist[1]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1,
- &rmon_stats->hist[2]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1,
- &rmon_stats->hist[3]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1,
- &rmon_stats->hist[4]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1,
- &rmon_stats->hist[5]);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1,
- &rmon_stats->hist_tx[0]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1,
- &rmon_stats->hist_tx[1]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1,
- &rmon_stats->hist_tx[2]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1,
- &rmon_stats->hist_tx[3]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1,
- &rmon_stats->hist_tx[4]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1,
- &rmon_stats->hist_tx[5]);
-
- *ranges = mt7530_rmon_ranges;
+ return mt7530_lib_get_rmon_stats(&priv->lib_priv, port, rmon_stats, ranges,
+ &mt7530_rmon_hist_info);
}
static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port,
struct rtnl_link_stats64 *storage)
{
+ struct mt7530_lib_priv *lib_priv = &priv->lib_priv;
uint64_t data;
/* MIB counter doesn't provide a FramesTransmittedOK but instead
@@ -861,38 +833,40 @@ static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port,
* To simulate a global frame counter, read Unicast and addition Multicast
* and Broadcast later
*/
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,
- &storage->rx_packets);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,
- &storage->multicast);
- storage->rx_packets += storage->multicast;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,
- &data);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_UNICAST],
+ NULL, port, &storage->rx_packets);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_MULTICAST],
+ NULL, port, &data);
+ storage->rx_packets += data;
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_BROADCAST],
+ NULL, port, &data);
storage->rx_packets += data;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,
- &storage->tx_packets);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,
- &data);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_UNICAST],
+ NULL, port, &storage->tx_packets);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_MULTICAST],
+ NULL, port, &data);
storage->tx_packets += data;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,
- &data);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_BROADCAST],
+ NULL, port, &data);
storage->tx_packets += data;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,
- &storage->rx_bytes);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_BYTES_LOW],
+ lib_priv->fields[MT7530_MIB_RX_BYTES_HIGH], port,
+ &storage->rx_bytes);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,
- &storage->tx_bytes);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_BYTES_LOW],
+ lib_priv->fields[MT7530_MIB_TX_BYTES_HIGH], port,
+ &storage->tx_bytes);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1,
- &storage->rx_dropped);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_DROP],
+ NULL, port, &storage->rx_dropped);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1,
- &storage->tx_dropped);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_DROP],
+ NULL, port, &storage->tx_dropped);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1,
- &storage->rx_crc_errors);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_CRC_ERR],
+ NULL, port, &storage->rx_crc_errors);
}
static void mt7530_stats_refresh(struct mt7530_priv *priv)
@@ -948,11 +922,7 @@ static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1,
- &ctrl_stats->MACControlFramesTransmitted);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1,
- &ctrl_stats->MACControlFramesReceived);
+ mt7530_lib_get_eth_ctrl_stats(&priv->lib_priv, port, ctrl_stats);
}
static int
@@ -1073,214 +1043,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
mutex_unlock(&priv->reg_mutex);
}
-/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
- * of the Open Systems Interconnection basic reference model (OSI/RM) are
- * described; the medium access control (MAC) and logical link control (LLC)
- * sublayers. The MAC sublayer is the one facing the physical layer.
- *
- * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
- * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
- * of the Bridge, at least two Ports, and higher layer entities with at least a
- * Spanning Tree Protocol Entity included.
- *
- * Each Bridge Port also functions as an end station and shall provide the MAC
- * Service to an LLC Entity. Each instance of the MAC Service is provided to a
- * distinct LLC Entity that supports protocol identification, multiplexing, and
- * demultiplexing, for protocol data unit (PDU) transmission and reception by
- * one or more higher layer entities.
- *
- * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
- * Entity associated with each Bridge Port is modeled as being directly
- * connected to the attached Local Area Network (LAN).
- *
- * On the switch with CPU port architecture, CPU port functions as Management
- * Port, and the Management Port functionality is provided by software which
- * functions as an end station. Software is connected to an IEEE 802 LAN that is
- * wholly contained within the system that incorporates the Bridge. Software
- * provides access to the LLC Entity associated with each Bridge Port by the
- * value of the source port field on the special tag on the frame received by
- * software.
- *
- * We call frames that carry control information to determine the active
- * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
- * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
- * Protocol Data Units (MVRPDUs), and frames from other link constrained
- * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
- * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
- * forwarded by a Bridge. Permanently configured entries in the filtering
- * database (FDB) ensure that such frames are discarded by the Forwarding
- * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
- *
- * Each of the reserved MAC addresses specified in Table 8-1
- * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
- * permanently configured in the FDB in C-VLAN components and ERs.
- *
- * Each of the reserved MAC addresses specified in Table 8-2
- * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
- * configured in the FDB in S-VLAN components.
- *
- * Each of the reserved MAC addresses specified in Table 8-3
- * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
- * TPMR components.
- *
- * The FDB entries for reserved MAC addresses shall specify filtering for all
- * Bridge Ports and all VIDs. Management shall not provide the capability to
- * modify or remove entries for reserved MAC addresses.
- *
- * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
- * propagation of PDUs within a Bridged Network, as follows:
- *
- * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
- * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
- * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
- * PDUs transmitted using this destination address, or any other addresses
- * that appear in Table 8-1, Table 8-2, and Table 8-3
- * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
- * therefore travel no further than those stations that can be reached via a
- * single individual LAN from the originating station.
- *
- * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
- * address that no conformant S-VLAN component, C-VLAN component, or MAC
- * Bridge can forward; however, this address is relayed by a TPMR component.
- * PDUs using this destination address, or any of the other addresses that
- * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
- * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
- * any TPMRs but will propagate no further than the nearest S-VLAN component,
- * C-VLAN component, or MAC Bridge.
- *
- * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
- * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
- * relayed by TPMR components and S-VLAN components. PDUs using this
- * destination address, or any of the other addresses that appear in Table 8-1
- * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
- * will be relayed by TPMR components and S-VLAN components but will propagate
- * no further than the nearest C-VLAN component or MAC Bridge.
- *
- * Because the LLC Entity associated with each Bridge Port is provided via CPU
- * port, we must not filter these frames but forward them to CPU port.
- *
- * In a Bridge, the transmission Port is majorly decided by ingress and egress
- * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
- * For link-local frames, only CPU port should be designated as destination port
- * in the FDB, and the other functions of the Forwarding Process must not
- * interfere with the decision of the transmission Port. We call this process
- * trapping frames to CPU port.
- *
- * Therefore, on the switch with CPU port architecture, link-local frames must
- * be trapped to CPU port, and certain link-local frames received by a Port of a
- * Bridge comprising a TPMR component or an S-VLAN component must be excluded
- * from it.
- *
- * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
- * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
- * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
- * doesn't count) of this architecture will either function as a standard MAC
- * Bridge or a standard VLAN Bridge.
- *
- * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
- * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
- * we don't need to relay PDUs using the destination addresses specified on the
- * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
- * section where they must be relayed by TPMR components.
- *
- * One option to trap link-local frames to CPU port is to add static FDB entries
- * with CPU port designated as destination port. However, because that
- * Independent VLAN Learning (IVL) is being used on every VID, each entry only
- * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
- * Bridge component or a C-VLAN component, there would have to be 16 times 4096
- * entries. This switch intellectual property can only hold a maximum of 2048
- * entries. Using this option, there also isn't a mechanism to prevent
- * link-local frames from being discarded when the spanning tree Port State of
- * the reception Port is discarding.
- *
- * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
- * registers. Whilst this applies to every VID, it doesn't contain all of the
- * reserved MAC addresses without affecting the remaining Standard Group MAC
- * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
- * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
- * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
- * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
- * The latter option provides better but not complete conformance.
- *
- * This switch intellectual property also does not provide a mechanism to trap
- * link-local frames with specific destination addresses to CPU port by Bridge,
- * to conform to the filtering rules for the distinct Bridge components.
- *
- * Therefore, regardless of the type of the Bridge component, link-local frames
- * with these destination addresses will be trapped to CPU port:
- *
- * 01-80-C2-00-00-[00,01,02,03,0E]
- *
- * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
- *
- * Link-local frames with these destination addresses won't be trapped to CPU
- * port which won't conform to IEEE Std 802.1Q-2022:
- *
- * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
- *
- * In a Bridge comprising an S-VLAN component:
- *
- * Link-local frames with these destination addresses will be trapped to CPU
- * port which won't conform to IEEE Std 802.1Q-2022:
- *
- * 01-80-C2-00-00-00
- *
- * Link-local frames with these destination addresses won't be trapped to CPU
- * port which won't conform to IEEE Std 802.1Q-2022:
- *
- * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
- *
- * To trap link-local frames to CPU port as conformant as this switch
- * intellectual property can allow, link-local frames are made to be regarded as
- * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
- * property only lets the frames regarded as BPDUs bypass the spanning tree Port
- * State function of the Forwarding Process.
- *
- * The only remaining interference is the ingress rules. When the reception Port
- * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
- * There doesn't seem to be a mechanism on the switch intellectual property to
- * have link-local frames bypass this function of the Forwarding Process.
- */
-static void
-mt753x_trap_frames(struct mt7530_priv *priv)
-{
- /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress
- * them with the EG_TAG attribute set to disabled (system default)
- * so that any VLAN tags in the frame are not modified by the
- * switch egress VLAN tag processing. This preserves VLAN tags
- * for reception on VLAN sub-interfaces.
- */
- regmap_update_bits(priv->regmap, MT753X_BPC,
- PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
- BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
- PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
- BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
-
- /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and
- * egress them with EG_TAG disabled.
- */
- regmap_update_bits(priv->regmap, MT753X_RGAC1,
- R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
- R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
- R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
- R01_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
-
- /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and
- * egress them with EG_TAG disabled.
- */
- regmap_update_bits(priv->regmap, MT753X_RGAC2,
- R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
- R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
- R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
- R03_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
-}
-
static void
mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
{
@@ -1329,11 +1091,11 @@ mt7530_port_enable(struct dsa_switch *ds, int port,
if (dsa_port_is_user(dp)) {
struct dsa_port *cpu_dp = dp->cpu_dp;
- priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
+ priv->ports[port].pm |= BIT(cpu_dp->index);
}
priv->ports[port].enable = true;
regmap_update_bits(priv->regmap, MT7530_PCR_P(port), PCR_MATRIX_MASK,
- priv->ports[port].pm);
+ PCR_MATRIX(priv->ports[port].pm));
mutex_unlock(&priv->reg_mutex);
@@ -1378,36 +1140,8 @@ static int
mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
{
struct mt7530_priv *priv = ds->priv;
- int length;
- u32 val;
-
- /* When a new MTU is set, DSA always set the CPU port's MTU to the
- * largest MTU of the user ports. Because the switch only has a global
- * RX length register, only allowing CPU port here is enough.
- */
- if (!dsa_is_cpu_port(ds, port))
- return 0;
-
- regmap_read(priv->regmap, MT7530_GMACCR, &val);
- val &= ~MAX_RX_PKT_LEN_MASK;
-
- /* RX length also includes Ethernet header, MTK tag, and FCS length */
- length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
- if (length <= 1522) {
- val |= MAX_RX_PKT_LEN_1522;
- } else if (length <= 1536) {
- val |= MAX_RX_PKT_LEN_1536;
- } else if (length <= 1552) {
- val |= MAX_RX_PKT_LEN_1552;
- } else {
- val &= ~MAX_RX_JUMBO_MASK;
- val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
- val |= MAX_RX_PKT_LEN_JUMBO;
- }
-
- regmap_write(priv->regmap, MT7530_GMACCR, val);
- return 0;
+ return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu);
}
static int
@@ -1420,81 +1154,8 @@ static void
mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
{
struct mt7530_priv *priv = ds->priv;
- u32 stp_state;
- switch (state) {
- case BR_STATE_DISABLED:
- stp_state = MT7530_STP_DISABLED;
- break;
- case BR_STATE_BLOCKING:
- stp_state = MT7530_STP_BLOCKING;
- break;
- case BR_STATE_LISTENING:
- stp_state = MT7530_STP_LISTENING;
- break;
- case BR_STATE_LEARNING:
- stp_state = MT7530_STP_LEARNING;
- break;
- case BR_STATE_FORWARDING:
- default:
- stp_state = MT7530_STP_FORWARDING;
- break;
- }
-
- regmap_update_bits(priv->regmap, MT7530_SSP_P(port),
- FID_PST_MASK(FID_BRIDGED),
- FID_PST(FID_BRIDGED, stp_state));
-}
-
-static void mt7530_update_port_member(struct mt7530_priv *priv, int port,
- const struct net_device *bridge_dev,
- bool join) __must_hold(&priv->reg_mutex)
-{
- struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp;
- struct mt7530_port *p = &priv->ports[port], *other_p;
- struct dsa_port *cpu_dp = dp->cpu_dp;
- u32 port_bitmap = BIT(cpu_dp->index);
- int other_port;
- bool isolated;
-
- dsa_switch_for_each_user_port(other_dp, priv->ds) {
- other_port = other_dp->index;
- other_p = &priv->ports[other_port];
-
- if (dp == other_dp)
- continue;
-
- /* Add/remove this port to/from the port matrix of the other
- * ports in the same bridge. If the port is disabled, port
- * matrix is kept and not being setup until the port becomes
- * enabled.
- */
- if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev))
- continue;
-
- isolated = p->isolated && other_p->isolated;
-
- if (join && !isolated) {
- other_p->pm |= PCR_MATRIX(BIT(port));
- port_bitmap |= BIT(other_port);
- } else {
- other_p->pm &= ~PCR_MATRIX(BIT(port));
- }
-
- if (other_p->enable)
- regmap_update_bits(priv->regmap,
- MT7530_PCR_P(other_port),
- PCR_MATRIX_MASK, other_p->pm);
- }
-
- /* Add/remove the all other ports to this port matrix. For !join
- * (leaving the bridge), only the CPU port will remain in the port matrix
- * of this port.
- */
- p->pm = PCR_MATRIX(port_bitmap);
- if (priv->ports[port].enable)
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_MATRIX_MASK, p->pm);
+ mt7530_lib_stp_state_set(&priv->lib_priv, port, state);
}
static int
@@ -1516,37 +1177,8 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- if (flags.mask & BR_LEARNING)
- regmap_update_bits(priv->regmap, MT7530_PSC_P(port), SA_DIS,
- flags.val & BR_LEARNING ? 0 : SA_DIS);
-
- if (flags.mask & BR_FLOOD)
- regmap_update_bits(priv->regmap, MT753X_MFC,
- UNU_FFP(BIT(port)),
- flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
-
- if (flags.mask & BR_MCAST_FLOOD)
- regmap_update_bits(priv->regmap, MT753X_MFC,
- UNM_FFP(BIT(port)),
- flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
-
- if (flags.mask & BR_BCAST_FLOOD)
- regmap_update_bits(priv->regmap, MT753X_MFC,
- BC_FFP(BIT(port)),
- flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
-
- if (flags.mask & BR_ISOLATED) {
- struct dsa_port *dp = dsa_to_port(ds, port);
- struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp);
-
- priv->ports[port].isolated = !!(flags.val & BR_ISOLATED);
-
- mutex_lock(&priv->reg_mutex);
- mt7530_update_port_member(priv, port, bridge_dev, true);
- mutex_unlock(&priv->reg_mutex);
- }
-
- return 0;
+ return mt7530_lib_port_bridge_flags(&priv->lib_priv, port, flags,
+ extack);
}
static int
@@ -1556,151 +1188,8 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- mutex_lock(&priv->reg_mutex);
-
- mt7530_update_port_member(priv, port, bridge.dev, true);
-
- /* Set to fallback mode for independent VLAN learning */
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE);
-
- mutex_unlock(&priv->reg_mutex);
-
- return 0;
-}
-
-static int
-mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
-{
- u32 val;
- int ret;
-
- val = VTCR_BUSY | VTCR_FUNC(cmd) | VTCR_VID(vid);
- ret = regmap_write(priv->regmap, MT7530_VTCR, val);
- if (ret)
- return ret;
-
- ret = regmap_read_poll_timeout(priv->regmap, MT7530_VTCR, val,
- !(val & VTCR_BUSY), 20, 20000);
- if (!ret)
- ret = regmap_read(priv->regmap, MT7530_VTCR, &val);
-
- if (ret < 0) {
- dev_err(priv->dev, "poll timeout\n");
- return ret;
- }
-
- if (val & VTCR_INVALID) {
- dev_err(priv->dev, "read VTCR invalid\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int
-mt7530_setup_vlan0(struct mt7530_priv *priv)
-{
- u32 val;
-
- /* Validate the entry with independent learning, keep the original
- * ingress tag attribute.
- */
- val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
- VLAN_VALID;
- regmap_write(priv->regmap, MT7530_VAWD1, val);
- regmap_write(priv->regmap, MT7530_VAWD2, 0);
-
- return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
-}
-
-static void
-mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
-{
- struct mt7530_priv *priv = ds->priv;
- bool all_user_ports_removed = true;
- int i;
-
- /* This is called after .port_bridge_leave when leaving a VLAN-aware
- * bridge. Don't set standalone ports to fallback mode.
- */
- if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_PORT_VLAN_MASK,
- MT7530_PORT_FALLBACK_MODE);
-
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
- VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
- PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
- MT7530_VLAN_ACC_ALL);
-
- /* Set PVID to 0 */
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
-
- for (i = 0; i < priv->ds->num_ports; i++) {
- if (i == port)
- continue;
- if (dsa_is_user_port(ds, i) &&
- dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
- all_user_ports_removed = false;
- break;
- }
- }
-
- /* CPU port also does the same thing until all user ports belonging to
- * the CPU port get out of VLAN filtering mode.
- */
- if (all_user_ports_removed) {
- mutex_lock(&priv->reg_mutex);
- mt7530_setup_vlan0(priv);
- mutex_unlock(&priv->reg_mutex);
- }
-}
-
-static void
-mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
-{
- struct mt7530_priv *priv = ds->priv;
-
- /* Trapped into security mode allows packet forwarding through VLAN
- * table lookup.
- */
- if (dsa_is_user_port(ds, port)) {
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_PORT_VLAN_MASK,
- MT7530_PORT_SECURITY_MODE);
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK,
- G0_PORT_VID(priv->ports[port].pvid));
-
- /* Only accept tagged frames if PVID is not set */
- if (!priv->ports[port].pvid)
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
-
- /* Set the port as a user port which is to be able to recognize
- * VID from incoming packets before fetching entry within the
- * VLAN table.
- */
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
- VLAN_ATTR(MT7530_VLAN_USER) |
- PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
- } else {
- /* Also set CPU ports to the "user" VLAN port attribute, to
- * allow VLAN classification, but keep the EG_TAG attribute as
- * "consistent" (i.o.w. don't change its value) for packets
- * received by the switch from the CPU, so that tagged packets
- * are forwarded to user ports as tagged, and untagged as
- * untagged.
- */
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- VLAN_ATTR_MASK,
- VLAN_ATTR(MT7530_VLAN_USER));
- }
+ return mt7530_lib_port_bridge_join(&priv->lib_priv, port, bridge,
+ tx_fwd_offload, extack);
}
static void
@@ -1709,18 +1198,7 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- mutex_lock(&priv->reg_mutex);
-
- mt7530_update_port_member(priv, port, bridge.dev, false);
-
- /* When a port is removed from the bridge, the port would be set up
- * back to the default as is at initial boot which is a VLAN-unaware
- * port.
- */
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_PORT_VLAN_MASK, MT7530_PORT_MATRIX_MODE);
-
- mutex_unlock(&priv->reg_mutex);
+ return mt7530_lib_port_bridge_leave(&priv->lib_priv, port, bridge);
}
static int
@@ -1729,15 +1207,8 @@ mt7530_port_fdb_add(struct dsa_switch *ds, int port,
struct dsa_db db)
{
struct mt7530_priv *priv = ds->priv;
- int ret;
- u8 port_mask = BIT(port);
- mutex_lock(&priv->reg_mutex);
- mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
- mutex_unlock(&priv->reg_mutex);
-
- return ret;
+ return mt7530_lib_port_fdb_add(&priv->lib_priv, port, addr, vid, db);
}
static int
@@ -1746,15 +1217,8 @@ mt7530_port_fdb_del(struct dsa_switch *ds, int port,
struct dsa_db db)
{
struct mt7530_priv *priv = ds->priv;
- int ret;
- u8 port_mask = BIT(port);
- mutex_lock(&priv->reg_mutex);
- mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
- mutex_unlock(&priv->reg_mutex);
-
- return ret;
+ return mt7530_lib_port_fdb_del(&priv->lib_priv, port, addr, vid, db);
}
static int
@@ -1769,13 +1233,14 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
mutex_lock(&priv->reg_mutex);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
+ ATC_MAT_MACTAB, &rsp);
if (ret < 0)
goto err;
do {
if (rsp & ATC_SRCH_HIT) {
- mt7530_fdb_read(priv, &_fdb);
+ mt7530_lib_fdb_read(&priv->lib_priv, &_fdb);
if (_fdb.port_mask & BIT(port)) {
ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
data);
@@ -1785,7 +1250,8 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
}
} while (--cnt &&
!(rsp & ATC_SRCH_END) &&
- !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
+ !mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT,
+ ATC_MAT_MACTAB, &rsp));
err:
mutex_unlock(&priv->reg_mutex);
@@ -1798,27 +1264,8 @@ mt7530_port_mdb_add(struct dsa_switch *ds, int port,
struct dsa_db db)
{
struct mt7530_priv *priv = ds->priv;
- const u8 *addr = mdb->addr;
- u16 vid = mdb->vid;
- u8 port_mask = 0;
- u32 val;
- int ret;
- mutex_lock(&priv->reg_mutex);
-
- mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
- if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {
- regmap_read(priv->regmap, MT7530_ATRD, &val);
- port_mask = FIELD_GET(PORT_MAP_MASK, val);
- }
-
- port_mask |= BIT(port);
- mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
-
- mutex_unlock(&priv->reg_mutex);
-
- return ret;
+ return mt7530_lib_port_mdb_add(&priv->lib_priv, port, mdb, db);
}
static int
@@ -1827,132 +1274,19 @@ mt7530_port_mdb_del(struct dsa_switch *ds, int port,
struct dsa_db db)
{
struct mt7530_priv *priv = ds->priv;
- const u8 *addr = mdb->addr;
- u16 vid = mdb->vid;
- u8 port_mask = 0;
- u32 val;
- int ret;
- mutex_lock(&priv->reg_mutex);
-
- mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
- if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {
- regmap_read(priv->regmap, MT7530_ATRD, &val);
- port_mask = FIELD_GET(PORT_MAP_MASK, val);
- }
-
- port_mask &= ~BIT(port);
- mt7530_fdb_write(priv, vid, port_mask, addr, -1,
- port_mask ? STATIC_ENT : STATIC_EMP);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
-
- mutex_unlock(&priv->reg_mutex);
-
- return ret;
+ return mt7530_lib_port_mdb_del(&priv->lib_priv, port, mdb, db);
}
static int
mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
struct netlink_ext_ack *extack)
{
- struct dsa_port *dp = dsa_to_port(ds, port);
- struct dsa_port *cpu_dp = dp->cpu_dp;
-
- if (vlan_filtering) {
- /* The port is being kept as VLAN-unaware port when bridge is
- * set up with vlan_filtering not being set, Otherwise, the
- * port and the corresponding CPU port is required the setup
- * for becoming a VLAN-aware port.
- */
- mt7530_port_set_vlan_aware(ds, port);
- mt7530_port_set_vlan_aware(ds, cpu_dp->index);
- } else {
- mt7530_port_set_vlan_unaware(ds, port);
- }
-
- return 0;
-}
-
-static void
-mt7530_hw_vlan_add(struct mt7530_priv *priv,
- struct mt7530_hw_vlan_entry *entry)
-{
- struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
- u8 new_members;
- u32 val;
-
- new_members = entry->old_members | BIT(entry->port);
-
- /* Validate the entry with independent learning, create egress tag per
- * VLAN and joining the port as one of the port members.
- */
- val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
- VLAN_VALID;
- regmap_write(priv->regmap, MT7530_VAWD1, val);
-
- /* Decide whether adding tag or not for those outgoing packets from the
- * port inside the VLAN.
- * CPU port is always taken as a tagged port for serving more than one
- * VLANs across and also being applied with egress type stack mode for
- * that VLAN tags would be appended after hardware special tag used as
- * DSA tag.
- */
- if (dsa_port_is_cpu(dp))
- val = MT7530_VLAN_EGRESS_STACK;
- else if (entry->untagged)
- val = MT7530_VLAN_EGRESS_UNTAG;
- else
- val = MT7530_VLAN_EGRESS_TAG;
- regmap_update_bits(priv->regmap, MT7530_VAWD2,
- ETAG_CTRL_P_MASK(entry->port),
- ETAG_CTRL_P(entry->port, val));
-}
-
-static void
-mt7530_hw_vlan_del(struct mt7530_priv *priv,
- struct mt7530_hw_vlan_entry *entry)
-{
- u8 new_members;
- u32 val;
-
- new_members = entry->old_members & ~BIT(entry->port);
-
- regmap_read(priv->regmap, MT7530_VAWD1, &val);
- if (!(val & VLAN_VALID)) {
- dev_err(priv->dev,
- "Cannot be deleted due to invalid entry\n");
- return;
- }
-
- if (new_members) {
- val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
- VLAN_VALID;
- regmap_write(priv->regmap, MT7530_VAWD1, val);
- } else {
- regmap_write(priv->regmap, MT7530_VAWD1, 0);
- regmap_write(priv->regmap, MT7530_VAWD2, 0);
- }
-}
-
-static void
-mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
- struct mt7530_hw_vlan_entry *entry,
- mt7530_vlan_op vlan_op)
-{
- u32 val;
-
- /* Fetch entry */
- mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
-
- regmap_read(priv->regmap, MT7530_VAWD1, &val);
-
- entry->old_members = FIELD_GET(PORT_MEM_MASK, val);
-
- /* Manipulate entry */
- vlan_op(priv, entry);
+ struct mt7530_priv *priv = ds->priv;
- /* Flush result to hardware */
- mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
+ return mt7530_lib_port_vlan_filtering(&priv->lib_priv, port,
+ vlan_filtering,
+ extack);
}
static int
@@ -1960,94 +1294,18 @@ mt7530_port_vlan_add(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_vlan *vlan,
struct netlink_ext_ack *extack)
{
- bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
- bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
- struct mt7530_hw_vlan_entry new_entry;
struct mt7530_priv *priv = ds->priv;
- mutex_lock(&priv->reg_mutex);
-
- /* VID 0 is managed exclusively by mt7530_setup_vlan0() for
- * VLAN-unaware bridge operation. Don't let the bridge overwrite
- * its EG_CON flag with VTAG_EN and corrupt PORT_MEM.
- */
- if (vlan->vid == 0)
- goto skip_vlan_table;
-
- mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
- mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
-
-skip_vlan_table:
-
- if (pvid) {
- priv->ports[port].pvid = vlan->vid;
-
- /* Accept all frames if PVID is set */
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- ACC_FRM_MASK, MT7530_VLAN_ACC_ALL);
-
- /* Only configure PVID if VLAN filtering is enabled */
- if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK,
- G0_PORT_VID(vlan->vid));
- } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
- /* This VLAN is overwritten without PVID, so unset it */
- priv->ports[port].pvid = G0_PORT_VID_DEF;
-
- /* Only accept tagged frames if the port is VLAN-aware */
- if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
-
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
- }
-
- mutex_unlock(&priv->reg_mutex);
-
- return 0;
+ return mt7530_lib_port_vlan_add(&priv->lib_priv, port, vlan, extack);
}
static int
mt7530_port_vlan_del(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_vlan *vlan)
{
- struct mt7530_hw_vlan_entry target_entry;
struct mt7530_priv *priv = ds->priv;
- mutex_lock(&priv->reg_mutex);
-
- /* VID 0 is managed exclusively by mt7530_setup_vlan0(). */
- if (vlan->vid == 0)
- goto skip_vlan_table;
-
- mt7530_hw_vlan_entry_init(&target_entry, port, 0);
- mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
- mt7530_hw_vlan_del);
-
-skip_vlan_table:
- /* PVID is being restored to the default whenever the PVID port
- * is being removed from the VLAN.
- */
- if (priv->ports[port].pvid == vlan->vid) {
- priv->ports[port].pvid = G0_PORT_VID_DEF;
-
- /* Only accept tagged frames if the port is VLAN-aware */
- if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
-
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
- }
-
-
- mutex_unlock(&priv->reg_mutex);
-
- return 0;
+ return mt7530_lib_port_vlan_del(&priv->lib_priv, port, vlan);
}
static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
@@ -2055,60 +1313,16 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
bool ingress, struct netlink_ext_ack *extack)
{
struct mt7530_priv *priv = ds->priv;
- int monitor_port;
- u32 val;
-
- /* Check for existent entry */
- if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
- return -EEXIST;
-
- regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val);
-
- /* MT7530 only supports one monitor port */
- monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
- if (val & MT753X_MIRROR_EN(priv->id) &&
- monitor_port != mirror->to_local_port)
- return -EEXIST;
-
- val |= MT753X_MIRROR_EN(priv->id);
- val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
- val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
- regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val);
- regmap_read(priv->regmap, MT7530_PCR_P(port), &val);
- if (ingress) {
- val |= PORT_RX_MIR;
- priv->mirror_rx |= BIT(port);
- } else {
- val |= PORT_TX_MIR;
- priv->mirror_tx |= BIT(port);
- }
- regmap_write(priv->regmap, MT7530_PCR_P(port), val);
-
- return 0;
+ return mt7530_lib_port_mirror_add(&priv->lib_priv, port, mirror, ingress, extack);
}
static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
struct dsa_mall_mirror_tc_entry *mirror)
{
struct mt7530_priv *priv = ds->priv;
- u32 val;
- regmap_read(priv->regmap, MT7530_PCR_P(port), &val);
- if (mirror->ingress) {
- val &= ~PORT_RX_MIR;
- priv->mirror_rx &= ~BIT(port);
- } else {
- val &= ~PORT_TX_MIR;
- priv->mirror_tx &= ~BIT(port);
- }
- regmap_write(priv->regmap, MT7530_PCR_P(port), val);
-
- if (!priv->mirror_rx && !priv->mirror_tx) {
- regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val);
- val &= ~MT753X_MIRROR_EN(priv->id);
- regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val);
- }
+ mt7530_lib_port_mirror_del(&priv->lib_priv, port, mirror);
}
static enum dsa_tag_protocol
@@ -2492,10 +1706,10 @@ mt7530_setup(struct dsa_switch *ds)
if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
mt7530_pll_setup(priv);
- mt753x_trap_frames(priv);
+ mt7530_lib_trap_frames(&priv->lib_priv);
/* Enable and reset MIB counters */
- mt7530_mib_reset(ds);
+ mt7530_lib_mib_reset(&priv->lib_priv);
for (i = 0; i < priv->ds->num_ports; i++) {
/* Clear link settings and enable force mode to force link down
@@ -2519,7 +1733,8 @@ mt7530_setup(struct dsa_switch *ds)
/* Set default PVID to 0 on all user ports */
regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
+ G0_PORT_VID_MASK,
+ G0_PORT_VID(G0_PORT_VID_DEF));
}
/* Enable consistent egress tag */
regmap_update_bits(priv->regmap, MT7530_PVC_P(i),
@@ -2531,7 +1746,7 @@ mt7530_setup(struct dsa_switch *ds)
regmap_set_bits(priv->regmap, MT753X_AGC, LOCAL_EN);
/* Setup VLAN ID 0 for VLAN-unaware bridges */
- ret = mt7530_setup_vlan0(priv);
+ ret = mt7530_lib_setup_vlan0(&priv->lib_priv);
if (ret)
return ret;
@@ -2590,7 +1805,8 @@ mt7530_setup(struct dsa_switch *ds)
#endif /* CONFIG_GPIOLIB */
/* Flush the FDB table */
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ ATC_MAT_MACTAB, NULL);
if (ret < 0)
return ret;
@@ -2609,10 +1825,10 @@ mt7531_setup_common(struct dsa_switch *ds)
ds->ageing_time_min = 2 * 1000;
ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000;
- mt753x_trap_frames(priv);
+ mt7530_lib_trap_frames(&priv->lib_priv);
/* Enable and reset MIB counters */
- mt7530_mib_reset(ds);
+ mt7530_lib_mib_reset(&priv->lib_priv);
/* Disable flooding on all ports */
regmap_clear_bits(priv->regmap, MT753X_MFC,
@@ -2643,7 +1859,8 @@ mt7531_setup_common(struct dsa_switch *ds)
/* Set default PVID to 0 on all user ports */
regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
+ G0_PORT_VID_MASK,
+ G0_PORT_VID(G0_PORT_VID_DEF));
}
/* Enable consistent egress tag */
@@ -2661,12 +1878,13 @@ mt7531_setup_common(struct dsa_switch *ds)
CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN);
/* Flush the FDB table */
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ ATC_MAT_MACTAB, NULL);
if (ret < 0)
return ret;
/* Setup VLAN ID 0 for VLAN-unaware bridges */
- return mt7530_setup_vlan0(priv);
+ return mt7530_lib_setup_vlan0(&priv->lib_priv);
}
static int
@@ -3281,11 +2499,12 @@ mt753x_port_change_conduit(struct dsa_switch *ds, int port,
mutex_lock(&priv->reg_mutex);
/* dp->cpu_dp still points to the old CPU port */
- priv->ports[port].pm &= ~PCR_MATRIX(BIT(dp->cpu_dp->index));
- priv->ports[port].pm |= PCR_MATRIX(BIT(new_cpu_dp->index));
+ priv->ports[port].pm &= ~BIT(dp->cpu_dp->index);
+ priv->ports[port].pm |= BIT(new_cpu_dp->index);
if (priv->ports[port].enable)
regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_MATRIX_MASK, priv->ports[port].pm);
+ PCR_MATRIX_MASK,
+ PCR_MATRIX(priv->ports[port].pm));
mutex_unlock(&priv->reg_mutex);
@@ -3456,6 +2675,8 @@ static const struct phylink_mac_ops mt753x_phylink_mac_ops = {
const struct mt753x_info mt753x_table[] = {
[ID_MT7621] = {
.id = ID_MT7621,
+ .reg_fields = mt7530_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7530_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7530_setup,
.phy_read_c22 = mt7530_phy_read_c22,
@@ -3467,6 +2688,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_MT7530] = {
.id = ID_MT7530,
+ .reg_fields = mt7530_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7530_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7530_setup,
.phy_read_c22 = mt7530_phy_read_c22,
@@ -3478,6 +2701,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_MT7531] = {
.id = ID_MT7531,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7531_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3489,6 +2714,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_MT7988] = {
.id = ID_MT7988,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7988_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3499,6 +2726,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_EN7581] = {
.id = ID_EN7581,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7988_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3509,6 +2738,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_AN7583] = {
.id = ID_AN7583,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7988_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3519,6 +2750,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_EN7528] = {
.id = ID_EN7528,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7988_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3576,6 +2809,47 @@ mt7530_remove_common(struct mt7530_priv *priv)
}
EXPORT_SYMBOL_GPL(mt7530_remove_common);
+int mt7530_setup_lib_priv(struct mt7530_priv *priv)
+{
+ struct mt7530_lib_priv *lib_priv = &priv->lib_priv;
+ int i;
+
+ lib_priv->dev = priv->dev;
+ lib_priv->ds = priv->ds;
+ lib_priv->regmap = priv->regmap;
+ lib_priv->ports = priv->ports;
+ lib_priv->reg_mutex = &priv->reg_mutex;
+
+ for (i = 0; i < ARRAY_SIZE(mt753x_fields); i++) {
+ const struct mt7530_reg_field *reg_field;
+ struct regmap_field *field;
+
+ reg_field = &mt753x_fields[i];
+ field = devm_regmap_field_alloc(priv->dev, priv->regmap,
+ reg_field->field);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ lib_priv->fields[reg_field->id] = field;
+ }
+
+ for (i = 0; i < priv->info->num_reg_fields; i++) {
+ const struct mt7530_reg_field *reg_field;
+ struct regmap_field *field;
+
+ reg_field = &priv->info->reg_fields[i];
+ field = devm_regmap_field_alloc(priv->dev, priv->regmap,
+ reg_field->field);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ lib_priv->fields[reg_field->id] = field;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_setup_lib_priv);
+
MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index 2bbbe617b52ee..50a12e10893d8 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -7,14 +7,11 @@
#define __MT7530_H
#include <linux/bitfield.h>
+#include "mt7530-lib.h"
#define MT7530_NUM_PORTS 7
#define MT7530_NUM_PHYS 5
#define MT7530_NUM_FDB_RECORDS 2048
-#define MT7530_ALL_MEMBERS 0xff
-
-#define MTK_HDR_LEN 4
-#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
enum mt753x_id {
ID_MT7530 = 0,
@@ -135,18 +132,8 @@ enum mt753x_id {
#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
#define R03_PORT_FW_MASK GENMASK(2, 0)
-enum mt753x_to_cpu_fw {
- TO_CPU_FW_SYSTEM_DEFAULT,
- TO_CPU_FW_CPU_EXCLUDE = 4,
- TO_CPU_FW_CPU_INCLUDE = 5,
- TO_CPU_FW_CPU_ONLY = 6,
- TO_CPU_FW_DROP = 7,
-};
-
/* Registers for address table access */
#define MT7530_ATA1 0x74
-#define STATIC_EMP 0
-#define STATIC_ENT 3
#define MT7530_ATA2 0x78
#define ATA2_IVL BIT(15)
#define ATA2_FID_MASK GENMASK(14, 12)
@@ -165,16 +152,6 @@ enum mt753x_to_cpu_fw {
#define ATC_INVALID BIT(12)
#define ATC_MAT_MASK GENMASK(11, 8)
#define ATC_MAT(x) FIELD_PREP(ATC_MAT_MASK, x)
-#define ATC_MAT_MACTAB ATC_MAT(0)
-#define ATC_MAT_NON_STATIC_MAC ATC_MAT(4)
-
-enum mt7530_fdb_cmd {
- MT7530_FDB_READ = 0,
- MT7530_FDB_WRITE = 1,
- MT7530_FDB_FLUSH = 2,
- MT7530_FDB_START = 4,
- MT7530_FDB_NEXT = 5,
-};
/* Registers for table search read address */
#define MT7530_TSRA1 0x84
@@ -202,14 +179,6 @@ enum mt7530_fdb_cmd {
#define VTCR_VID_MASK GENMASK(11, 0)
#define VTCR_VID(x) FIELD_PREP(VTCR_VID_MASK, x)
-enum mt7530_vlan_cmd {
- /* Read/Write the specified VID entry from VAWD register based
- * on VID.
- */
- MT7530_VTCR_RD_VID = 0,
- MT7530_VTCR_WR_VID = 1,
-};
-
/* Register for setup vlan and acl write data */
#define MT7530_VAWD1 0x94
#define PORT_STAG BIT(31)
@@ -228,21 +197,7 @@ enum mt7530_vlan_cmd {
/* VLAN Entry Valid */
#define VLAN_VALID BIT(0)
-enum mt7530_fid {
- FID_STANDALONE = 0,
- FID_BRIDGED = 1,
-};
-
#define MT7530_VAWD2 0x98
-/* Egress Tag Control */
-#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
-#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
-
-enum mt7530_vlan_egress_attr {
- MT7530_VLAN_EGRESS_UNTAG = 0,
- MT7530_VLAN_EGRESS_TAG = 2,
- MT7530_VLAN_EGRESS_STACK = 3,
-};
/* Register for address age control */
#define MT7530_AAC 0xa0
@@ -270,40 +225,16 @@ enum mt7530_vlan_egress_attr {
#define EGR_BC_CRC_IPG_PREAMBLE 0x18 /* crc + ipg + preamble */
/* Register for port STP state control */
-#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
-#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
-#define FID_PST_MASK(fid) FID_PST(fid, 0x3)
-
-enum mt7530_stp_state {
- MT7530_STP_DISABLED = 0,
- MT7530_STP_BLOCKING = 1,
- MT7530_STP_LISTENING = 1,
- MT7530_STP_LEARNING = 2,
- MT7530_STP_FORWARDING = 3
-};
+#define MT7530_SSP 0x2000
+#define MT7530_SSP_P(x) (MT7530_SSP + ((x) * 0x100))
/* Register for port control */
-#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
+#define MT7530_PCR 0x2004
+#define MT7530_PCR_P(x) (MT7530_PCR + ((x) * 0x100))
#define PORT_TX_MIR BIT(9)
#define PORT_RX_MIR BIT(8)
#define PCR_PORT_VLAN_MASK GENMASK(1, 0)
-enum mt7530_port_mode {
- /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
- MT7530_PORT_MATRIX_MODE = 0,
-
- /* Fallback Mode: Forward received frames with ingress ports that do
- * not belong to the VLAN member. Frames whose VID is not listed on
- * the VLAN table are forwarded by the PCR_MATRIX members.
- */
- MT7530_PORT_FALLBACK_MODE = 1,
-
- /* Security Mode: Discard any frame due to ingress membership
- * violation or VID missed on the VLAN table.
- */
- MT7530_PORT_SECURITY_MODE = 3,
-};
-
#define PCR_MATRIX_MASK GENMASK(23, 16)
#define PCR_MATRIX(x) FIELD_PREP(PCR_MATRIX_MASK, x)
#define PORT_PRI_MASK GENMASK(26, 24)
@@ -313,11 +244,13 @@ enum mt7530_port_mode {
#define PCR_MATRIX_CLR PCR_MATRIX(0)
/* Register for port security control */
-#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
+#define MT7530_PSC 0x200c
+#define MT7530_PSC_P(x) (MT7530_PSC + ((x) * 0x100))
#define SA_DIS BIT(4)
/* Register for port vlan control */
-#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
+#define MT7530_PVC 0x2010
+#define MT7530_PVC_P(x) (MT7530_PVC + ((x) * 0x100))
#define PORT_SPEC_TAG BIT(5)
#define PVC_EG_TAG_MASK GENMASK(10, 8)
#define PVC_EG_TAG(x) FIELD_PREP(PVC_EG_TAG_MASK, x)
@@ -325,31 +258,14 @@ enum mt7530_port_mode {
#define VLAN_ATTR(x) FIELD_PREP(VLAN_ATTR_MASK, x)
#define ACC_FRM_MASK GENMASK(1, 0)
-enum mt7530_vlan_port_eg_tag {
- MT7530_VLAN_EG_DISABLED = 0,
- MT7530_VLAN_EG_CONSISTENT = 1,
- MT7530_VLAN_EG_UNTAGGED = 4,
-};
-
-enum mt7530_vlan_port_attr {
- MT7530_VLAN_USER = 0,
- MT7530_VLAN_TRANSPARENT = 3,
-};
-
-enum mt7530_vlan_port_acc_frm {
- MT7530_VLAN_ACC_ALL = 0,
- MT7530_VLAN_ACC_TAGGED = 1,
- MT7530_VLAN_ACC_UNTAGGED = 2,
-};
-
#define STAG_VPID_MASK GENMASK(31, 16)
#define STAG_VPID(x) FIELD_PREP(STAG_VPID_MASK, x)
/* Register for port port-and-protocol based vlan 1 control */
+#define MT7530_PPBV1 0x2014
#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
#define G0_PORT_VID_MASK GENMASK(11, 0)
#define G0_PORT_VID(x) FIELD_PREP(G0_PORT_VID_MASK, x)
-#define G0_PORT_VID_DEF G0_PORT_VID(0)
/* Register for port MAC control register */
#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
@@ -427,55 +343,54 @@ enum mt7530_vlan_port_acc_frm {
#define MAX_RX_JUMBO_MASK GENMASK(5, 2)
#define MAX_RX_JUMBO(x) FIELD_PREP(MAX_RX_JUMBO_MASK, x)
#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
-#define MAX_RX_PKT_LEN_1522 0x0
-#define MAX_RX_PKT_LEN_1536 0x1
-#define MAX_RX_PKT_LEN_1552 0x2
-#define MAX_RX_PKT_LEN_JUMBO 0x3
/* Register for MIB */
-#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
+#define MT7530_MIB_COUNTER 0x4000
+#define MT7530_PORT_MIB_COUNTER(x) (MT7530_MIB_COUNTER + (x) * 0x100)
/* Each define is an offset of MT7530_PORT_MIB_COUNTER */
-#define MT7530_PORT_MIB_TX_DROP 0x00
-#define MT7530_PORT_MIB_TX_CRC_ERR 0x04
-#define MT7530_PORT_MIB_TX_UNICAST 0x08
-#define MT7530_PORT_MIB_TX_MULTICAST 0x0c
-#define MT7530_PORT_MIB_TX_BROADCAST 0x10
-#define MT7530_PORT_MIB_TX_COLLISION 0x14
-#define MT7530_PORT_MIB_TX_SINGLE_COLLISION 0x18
-#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c
-#define MT7530_PORT_MIB_TX_DEFERRED 0x20
-#define MT7530_PORT_MIB_TX_LATE_COLLISION 0x24
-#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28
-#define MT7530_PORT_MIB_TX_PAUSE 0x2c
-#define MT7530_PORT_MIB_TX_PKT_SZ_64 0x30
-#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34
-#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38
-#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3c
-#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40
-#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX 0x44
-#define MT7530_PORT_MIB_TX_BYTES 0x48 /* 64 bytes */
-#define MT7530_PORT_MIB_RX_DROP 0x60
-#define MT7530_PORT_MIB_RX_FILTERING 0x64
-#define MT7530_PORT_MIB_RX_UNICAST 0x68
-#define MT7530_PORT_MIB_RX_MULTICAST 0x6c
-#define MT7530_PORT_MIB_RX_BROADCAST 0x70
-#define MT7530_PORT_MIB_RX_ALIGN_ERR 0x74
-#define MT7530_PORT_MIB_RX_CRC_ERR 0x78
-#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR 0x7c
-#define MT7530_PORT_MIB_RX_FRAG_ERR 0x80
-#define MT7530_PORT_MIB_RX_OVER_SZ_ERR 0x84
-#define MT7530_PORT_MIB_RX_JABBER_ERR 0x88
-#define MT7530_PORT_MIB_RX_PAUSE 0x8c
-#define MT7530_PORT_MIB_RX_PKT_SZ_64 0x90
-#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 0x94
-#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 0x98
-#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 0x9c
-#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xa0
-#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX 0xa4
-#define MT7530_PORT_MIB_RX_BYTES 0xa8 /* 64 bytes */
-#define MT7530_PORT_MIB_RX_CTRL_DROP 0xb0
-#define MT7530_PORT_MIB_RX_INGRESS_DROP 0xb4
-#define MT7530_PORT_MIB_RX_ARL_DROP 0xb8
+#define MT7530_PORT_MIB_TX_DROP (MT7530_MIB_COUNTER + 0x00)
+#define MT7530_PORT_MIB_TX_CRC_ERR (MT7530_MIB_COUNTER + 0x04)
+#define MT7530_PORT_MIB_TX_UNICAST (MT7530_MIB_COUNTER + 0x08)
+#define MT7530_PORT_MIB_TX_MULTICAST (MT7530_MIB_COUNTER + 0x0c)
+#define MT7530_PORT_MIB_TX_BROADCAST (MT7530_MIB_COUNTER + 0x10)
+#define MT7530_PORT_MIB_TX_COLLISION (MT7530_MIB_COUNTER + 0x14)
+#define MT7530_PORT_MIB_TX_SINGLE_COLLISION (MT7530_MIB_COUNTER + 0x18)
+#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION (MT7530_MIB_COUNTER + 0x1c)
+#define MT7530_PORT_MIB_TX_DEFERRED (MT7530_MIB_COUNTER + 0x20)
+#define MT7530_PORT_MIB_TX_LATE_COLLISION (MT7530_MIB_COUNTER + 0x24)
+#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION (MT7530_MIB_COUNTER + 0x28)
+#define MT7530_PORT_MIB_TX_PAUSE (MT7530_MIB_COUNTER + 0x2c)
+#define MT7530_PORT_MIB_TX_PKT_SZ_64 (MT7530_MIB_COUNTER + 0x30)
+#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 (MT7530_MIB_COUNTER + 0x34)
+#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 (MT7530_MIB_COUNTER + 0x38)
+#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 (MT7530_MIB_COUNTER + 0x3c)
+#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 (MT7530_MIB_COUNTER + 0x40)
+#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX (MT7530_MIB_COUNTER + 0x44)
+#define MT7530_PORT_MIB_TX_BYTES_LOW (MT7530_MIB_COUNTER + 0x48) /* 64 bytes */
+#define MT7530_PORT_MIB_TX_BYTES_HIGH (MT7530_MIB_COUNTER + 0x4c)
+#define MT7530_PORT_MIB_RX_DROP (MT7530_MIB_COUNTER + 0x60)
+#define MT7530_PORT_MIB_RX_FILTERING (MT7530_MIB_COUNTER + 0x64)
+#define MT7530_PORT_MIB_RX_UNICAST (MT7530_MIB_COUNTER + 0x68)
+#define MT7530_PORT_MIB_RX_MULTICAST (MT7530_MIB_COUNTER + 0x6c)
+#define MT7530_PORT_MIB_RX_BROADCAST (MT7530_MIB_COUNTER + 0x70)
+#define MT7530_PORT_MIB_RX_ALIGN_ERR (MT7530_MIB_COUNTER + 0x74)
+#define MT7530_PORT_MIB_RX_CRC_ERR (MT7530_MIB_COUNTER + 0x78)
+#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR (MT7530_MIB_COUNTER + 0x7c)
+#define MT7530_PORT_MIB_RX_FRAG_ERR (MT7530_MIB_COUNTER + 0x80)
+#define MT7530_PORT_MIB_RX_OVER_SZ_ERR (MT7530_MIB_COUNTER + 0x84)
+#define MT7530_PORT_MIB_RX_JABBER_ERR (MT7530_MIB_COUNTER + 0x88)
+#define MT7530_PORT_MIB_RX_PAUSE (MT7530_MIB_COUNTER + 0x8c)
+#define MT7530_PORT_MIB_RX_PKT_SZ_64 (MT7530_MIB_COUNTER + 0x90)
+#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 (MT7530_MIB_COUNTER + 0x94)
+#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 (MT7530_MIB_COUNTER + 0x98)
+#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 (MT7530_MIB_COUNTER + 0x9c)
+#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 (MT7530_MIB_COUNTER + 0xa0)
+#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX (MT7530_MIB_COUNTER + 0xa4)
+#define MT7530_PORT_MIB_RX_BYTES_LOW (MT7530_MIB_COUNTER + 0xa8) /* 64 bytes */
+#define MT7530_PORT_MIB_RX_BYTES_HIGH (MT7530_MIB_COUNTER + 0xac)
+#define MT7530_PORT_MIB_RX_CTRL_DROP (MT7530_MIB_COUNTER + 0xb0)
+#define MT7530_PORT_MIB_RX_INGRESS_DROP (MT7530_MIB_COUNTER + 0xb4)
+#define MT7530_PORT_MIB_RX_ARL_DROP (MT7530_MIB_COUNTER + 0xb8)
#define MT7530_MIB_CCR 0x4fe0
#define CCR_MIB_ENABLE BIT(31)
#define CCR_RX_OCT_CNT_GOOD BIT(7)
@@ -794,45 +709,6 @@ enum mt7531_xtal_fsel {
#define REG_GSWCK_EN BIT(0)
#define REG_TRGMIICK_EN BIT(1)
-#define MIB_DESC(_s, _o, _n) \
- { \
- .size = (_s), \
- .offset = (_o), \
- .name = (_n), \
- }
-
-struct mt7530_mib_desc {
- unsigned int size;
- unsigned int offset;
- const char *name;
-};
-
-struct mt7530_fdb {
- u16 vid;
- u8 port_mask;
- u8 aging;
- u8 mac[6];
- bool noarp;
-};
-
-/* struct mt7530_port - This is the main data structure for holding the state
- * of the port.
- * @enable: The status used for show port is enabled or not.
- * @pm: The matrix used to show all connections with the port.
- * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
- * untagged frames will be assigned to the related VLAN.
- * @sgmii_pcs: Pointer to PCS instance for SerDes ports
- * @stats: Cached port statistics for MDIO-connected switches
- */
-struct mt7530_port {
- bool enable;
- bool isolated;
- u32 pm;
- u16 pvid;
- struct phylink_pcs *sgmii_pcs;
- struct rtnl_link_stats64 stats;
-};
-
/* Port 5 mode definitions of the MT7530 switch */
enum mt7530_p5_mode {
GMAC5,
@@ -864,6 +740,9 @@ struct mt753x_pcs {
struct mt753x_info {
enum mt753x_id id;
+ const struct mt7530_reg_field *reg_fields;
+ unsigned int num_reg_fields;
+
const struct phylink_pcs_ops *pcs_ops;
int (*sw_setup)(struct dsa_switch *ds);
@@ -921,8 +800,6 @@ struct mt7530_priv {
bool mcm;
enum mt7530_p5_mode p5_mode;
bool p5_sgmii;
- u8 mirror_rx;
- u8 mirror_tx;
struct mt7530_port ports[MT7530_NUM_PORTS];
struct mt753x_pcs pcs[MT7530_NUM_PORTS];
/* protect among processes for registers access*/
@@ -934,24 +811,10 @@ struct mt7530_priv {
spinlock_t stats_lock; /* protects cached stats counters */
struct delayed_work stats_work;
unsigned long stats_last;
-};
-struct mt7530_hw_vlan_entry {
- int port;
- u8 old_members;
- bool untagged;
+ struct mt7530_lib_priv lib_priv;
};
-static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
- int port, bool untagged)
-{
- e->port = port;
- e->untagged = untagged;
-}
-
-typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
- struct mt7530_hw_vlan_entry *);
-
struct mt7530_hw_stats {
const char *string;
u16 reg;
@@ -960,6 +823,7 @@ struct mt7530_hw_stats {
int mt7530_probe_common(struct mt7530_priv *priv);
void mt7530_remove_common(struct mt7530_priv *priv);
+int mt7530_setup_lib_priv(struct mt7530_priv *priv);
extern const struct mt753x_info mt753x_table[];
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d3835597e3795..eca2ce135c86b 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -96,6 +96,12 @@ config AIR_AN8801_PHY
help
Currently supports the Airoha AN8801R PHY.
+config AIR_AN8855_PHY
+ tristate "Airoha AN8855 Internal Gigabit PHY"
+ depends on NVMEM || !NVMEM
+ help
+ Currently supports the internal Airoha AN8855 Switch PHY.
+
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
select AIR_NET_PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 49575fa185223..b4222c4be4f52 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_ADIN1140_PHY) += adin1140-phy.o
obj-$(CONFIG_AIR_AN8801_PHY) += air_an8801.o
+obj-$(CONFIG_AIR_AN8855_PHY) += air_an8855.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
diff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c
new file mode 100644
index 0000000000000..bc22256fd5f95
--- /dev/null
+++ b/drivers/net/phy/air_an8855.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+
+#define AN8855_PHY_SELECT_PAGE 0x1f
+#define AN8855_PHY_PAGE GENMASK(2, 0)
+#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+
+/* MII Registers Page 1 */
+#define AN8855_PHY_EXT_REG_14 0x14
+#define AN8855_PHY_EN_DOWN_SHIFT BIT(4)
+
+/* R50 Calibration regs in MDIO_MMD_VEND1 */
+#define AN8855_PHY_R50OHM_RSEL_TX_AB 0x174
+#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0)
+#define AN8855_PHY_R50OHM_RSEL_TX_CD 0x175
+#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0)
+
+#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24)
+
+/* PHY TX PAIR DELAY SELECT Register */
+#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE GENMASK(14, 12)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_B_GBE GENMASK(10, 8)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE GENMASK(6, 4)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_D_GBE GENMASK(2, 0)
+/* PHY ADC Register */
+#define AN8855_PHY_RXADC_CTRL 0x0d8
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_A BIT(12)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_B BIT(8)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_C BIT(4)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_D BIT(0)
+#define AN8855_PHY_RXADC_REV_0 0x0d9
+#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8)
+#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0)
+#define AN8855_PHY_RXADC_REV_1 0x0da
+#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8)
+#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0)
+
+#define AN8855_PHY_ID 0xc0ff0410
+
+struct air_an8855_priv {
+ bool needs_calibration;
+ u8 calibration_data[4];
+};
+
+static const u8 dsa_r50ohm_table[] = {
+ 127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
+ 127, 127, 127, 127, 127, 127, 127, 126, 122, 117,
+ 112, 109, 104, 101, 97, 94, 90, 88, 84, 80,
+ 78, 74, 72, 68, 66, 64, 61, 58, 56, 53,
+ 51, 48, 47, 44, 42, 40, 38, 36, 34, 32,
+ 31, 28, 27, 24, 24, 22, 20, 18, 16, 16,
+ 14, 12, 11, 9
+};
+
+static int an8855_get_r50ohm_val(struct device *dev, const char *calib_name,
+ u8 *dest)
+{
+ u32 shift_sel, val;
+ int ret;
+ int i;
+
+ ret = nvmem_cell_read_u32(dev, calib_name, &val);
+ if (ret)
+ return ret;
+
+ shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val);
+ for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++)
+ if (dsa_r50ohm_table[i] == shift_sel)
+ break;
+
+ if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table))
+ *dest = dsa_r50ohm_table[25];
+ else
+ *dest = dsa_r50ohm_table[i - 8];
+
+ return 0;
+}
+
+static int an8855_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct air_an8855_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->needs_calibration = of_property_present(dev->of_node,
+ "nvmem-cells");
+
+ if (priv->needs_calibration) {
+ int ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_b", &priv->calibration_data[1]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_c", &priv->calibration_data[2]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_d", &priv->calibration_data[3]);
+ if (ret)
+ return ret;
+ }
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val;
+
+ val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
+ if (val < 0)
+ return val;
+
+ *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
+ DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
+
+ return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
+ AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
+ ds);
+}
+
+static int an8855_config_init(struct phy_device *phydev)
+{
+ struct air_an8855_priv *priv = phydev->priv;
+ int ret;
+
+ /* Enable HW auto downshift */
+ ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
+ if (ret)
+ return ret;
+
+ if (priv->needs_calibration) {
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_AB,
+ AN8855_PHY_R50OHM_RSEL_TX_A_EN | AN8855_PHY_R50OHM_RSEL_TX_A |
+ AN8855_PHY_R50OHM_RSEL_TX_B_EN | AN8855_PHY_R50OHM_RSEL_TX_B,
+ AN8855_PHY_R50OHM_RSEL_TX_A_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A,
+ priv->calibration_data[0]) |
+ AN8855_PHY_R50OHM_RSEL_TX_B_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B,
+ priv->calibration_data[1]));
+ if (ret)
+ return ret;
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_CD,
+ AN8855_PHY_R50OHM_RSEL_TX_C_EN | AN8855_PHY_R50OHM_RSEL_TX_C |
+ AN8855_PHY_R50OHM_RSEL_TX_D_EN | AN8855_PHY_R50OHM_RSEL_TX_D,
+ AN8855_PHY_R50OHM_RSEL_TX_C_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C,
+ priv->calibration_data[2]) |
+ AN8855_PHY_R50OHM_RSEL_TX_D_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D,
+ priv->calibration_data[3]));
+ if (ret)
+ return ret;
+ }
+
+ /* Apply values to reduce signal noise */
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,
+ AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE |
+ AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE,
+ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE, 0x4) |
+ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE, 0x4));
+ if (ret)
+ return ret;
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL,
+ AN8855_PHY_RG_AD_SAMPLE_PHSEL_A |
+ AN8855_PHY_RG_AD_SAMPLE_PHSEL_C);
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0,
+ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1));
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1,
+ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int an8855_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return an8855_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int an8855_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return an8855_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int an8855_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AN8855_PHY_SELECT_PAGE);
+}
+
+static int an8855_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page);
+}
+
+static struct phy_driver an8855_driver[] = {
+{
+ PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
+ .name = "Airoha AN8855 internal PHY",
+ /* PHY_GBIT_FEATURES */
+ .flags = PHY_IS_INTERNAL,
+ .probe = an8855_probe,
+ .config_init = an8855_config_init,
+ .soft_reset = genphy_soft_reset,
+ .get_tunable = an8855_get_tunable,
+ .set_tunable = an8855_set_tunable,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .read_page = an8855_read_page,
+ .write_page = an8855_write_page,
+}, };
+
+module_phy_driver(an8855_driver);
+
+static struct mdio_device_id __maybe_unused an8855_tbl[] = {
+ { PHY_ID_MATCH_EXACT(AN8855_PHY_ID) },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, an8855_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8855 PHY driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 7507d632e7c6d..c5659e9ab6d35 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -61,6 +61,7 @@ struct tc_action;
#define DSA_TAG_PROTO_NETC_VALUE 33
#define DSA_TAG_PROTO_KSZ8463_VALUE 34
#define DSA_TAG_PROTO_MT7628_VALUE 35
+#define DSA_TAG_PROTO_AIROHA_VALUE 36
enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -75,6 +76,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_KSZ9893 = DSA_TAG_PROTO_KSZ9893_VALUE,
DSA_TAG_PROTO_LAN9303 = DSA_TAG_PROTO_LAN9303_VALUE,
DSA_TAG_PROTO_MTK = DSA_TAG_PROTO_MTK_VALUE,
+ DSA_TAG_PROTO_AIROHA = DSA_TAG_PROTO_AIROHA_VALUE,
DSA_TAG_PROTO_QCA = DSA_TAG_PROTO_QCA_VALUE,
DSA_TAG_PROTO_TRAILER = DSA_TAG_PROTO_TRAILER_VALUE,
DSA_TAG_PROTO_8021Q = DSA_TAG_PROTO_8021Q_VALUE,
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index 23b4b74004ed5..07ad0f13416ed 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -24,6 +24,13 @@ config NET_DSA_TAG_NONE
Say Y or M if you want to enable support for switches which don't tag
frames over the CPU port.
+config NET_DSA_TAG_AIROHA
+ tristate "Tag driver for Airoha switches"
+ select NET_DSA_TAG_MTK_COMMON
+ help
+ Say Y or M if you want to enable support for tagging frames for
+ Airoha switches.
+
config NET_DSA_TAG_AR9331
tristate "Tag driver for Atheros AR9331 SoC with built-in switch"
help
@@ -104,8 +111,12 @@ config NET_DSA_TAG_MT7628
Say Y or M if you want to enable support for tagging frames for the
switch embedded in the MT7628 SoC.
+config NET_DSA_TAG_MTK_COMMON
+ tristate
+
config NET_DSA_TAG_MTK
tristate "Tag driver for Mediatek switches"
+ select NET_DSA_TAG_MTK_COMMON
help
Say Y or M if you want to enable support for tagging frames for
Mediatek switches.
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
index d15bcf5c68f02..57739a488a6a3 100644
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_NET_DSA_TAG_HELLCREEK) += tag_hellcreek.o
obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
obj-$(CONFIG_NET_DSA_TAG_MT7628) += tag_mt7628.o
-obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
+obj-$(CONFIG_NET_DSA_TAG_MTK_COMMON) += tag_mtk.o
obj-$(CONFIG_NET_DSA_TAG_MXL_862XX) += tag_mxl862xx.o
obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o
obj-$(CONFIG_NET_DSA_TAG_NETC) += tag_netc.o
diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
index c7dc7731675ec..f8087d768da6d 100644
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -11,6 +11,7 @@
#include "tag.h"
#define MTK_NAME "mtk"
+#define AIROHA_NAME "airoha"
#define MTK_HDR_LEN 4
#define MTK_HDR_XMIT_UNTAGGED 0
@@ -18,6 +19,9 @@
#define MTK_HDR_XMIT_TAGGED_TPID_88A8 2
#define MTK_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0)
#define MTK_HDR_XMIT_DP_BIT_MASK GENMASK(5, 0)
+/* AN8855 doesn't support SA_DIS and Leaky VLAN
+ * control in tag as these bits doesn't exist.
+ */
#define MTK_HDR_XMIT_SA_DIS BIT(6)
static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,
@@ -99,6 +103,7 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, struct net_device *dev)
return skb;
}
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
static const struct dsa_device_ops mtk_netdev_ops = {
.name = MTK_NAME,
.proto = DSA_TAG_PROTO_MTK,
@@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops = {
.needed_headroom = MTK_HDR_LEN,
};
-MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
-MODULE_LICENSE("GPL");
+DSA_TAG_DRIVER(mtk_netdev_ops);
MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);
+#endif
-module_dsa_tag_driver(mtk_netdev_ops);
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
+static const struct dsa_device_ops airoha_netdev_ops = {
+ .name = AIROHA_NAME,
+ .proto = DSA_TAG_PROTO_AIROHA,
+ .xmit = mtk_tag_xmit,
+ .rcv = mtk_tag_rcv,
+ .needed_headroom = MTK_HDR_LEN,
+};
+
+DSA_TAG_DRIVER(airoha_netdev_ops);
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);
+#endif
+
+static struct dsa_tag_driver *dsa_tag_driver_array[] = {
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
+ &DSA_TAG_DRIVER_NAME(mtk_netdev_ops),
+#endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
+ &DSA_TAG_DRIVER_NAME(airoha_netdev_ops),
+#endif
+};
+
+module_dsa_tag_drivers(dsa_tag_driver_array);
+
+MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
+MODULE_LICENSE("GPL");
|
| 3/2 | 2026/09/15 16:36 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 132861 output: 22 thoughts: 1000 Thoughts: **Evaluating the Patch Series for Fuzzing Worthiness** Okay, here's how I'm approaching this. The goal is to determine if these changes warrant fuzzing effort, essentially maximizing the return on investment in bug discovery. We're looking at overall benefit here – the potential for finding vulnerabilities against the cost of fuzzing time. I need to figure out if these modifications will result in code that is accessible and potentially exploitable within our standard virtualized environments. The instructions are clear: *reachability is king*. First, I need a solid understanding of what's being modified. It looks like it is a suite of updates revolving around Airoha AN8855 support, including Device Tree bindings, driver additions, and some refactoring. Specifically, this seems to be centered on an Airoha AN8855 MDIO driver and an associated Ethernet switch (DSA) driver. The instructions also note that the changes are already applied. The key is reachability in a standard environment, so my initial focus has to be on figuring out if the changes touch code which is capable of execution in a standard GCE or QEMU environment. The instructions give clear guidelines on when to return `WorthFuzzing=false`, and when to return `WorthFuzzing=true`. * I'll quickly scan the file list: Documentation files are, generally, not executable, unless they are used to generate code, and therefore, not directly interesting for fuzzing. * The `MAINTAINERS` file is irrelevant. * The `drivers/mfd` changes (Kconfig, Makefile, and `airoha-an8855.c`) are for Multi-Function Device (MFD) support. I need to determine if MFDs are generally accessible in our virtualized environments. * The `drivers/net/dsa` modifications are related to the Airoha AN8855 switch driver. The presence of Kconfig options like `NET_DSA_AN8855` indicate this is conditionally compiled. I need to understand the dependencies and how this driver is instantiated. * The refactoring of `mt7530.c` into `mt7530-lib.c` is very interesting. That's a strong indicator that changes are not simply feature additions. *This is where I need to dig deeper.* The question is whether the MT7530-related code is reachable. The existing code base provides a clue that MediaTek MT7530 is a physical Ethernet switch SoC (MediaTek MT7530 / MT7621 / MT7988). I need to determine if this can be emulated or if this relies on hardware that is not normally available in the testing environment. I need to confirm if MT7530 is used by a virtual or emulated device. I'll check its callers and any related DSA tagging protocols to understand how it is instantiated and how it is used. I am going to see if `net/dsa/tag_mtk.c` or virtual DSA switches are applicable. I'll leverage tooling (grepper, likely) to trace call paths and determine if any of these components are truly reachable. I need to understand if the refactoring has made any critical code accessible in the fuzzing environment. The DSA tagging protocols will be particularly interesting, since these tag drivers are executed during transmission/reception, if DSA devices are present. I want to confirm whether or not these DSA devices depend on a DSA switch. Ultimately, the question to answer is can it be executed in a virtual environment. |
| 4/2 | 2026/09/15 16:36 | tool | grepper |
0mArgs:{
"Expression": "DSA_TAG_PROTO_MTK"
}Results: {
"Output": "drivers/net/dsa/mt7530.c=1329=mtk_get_tag_protocol(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/mt7530.c-1331-{\ndrivers/net/dsa/mt7530.c:1332:\treturn DSA_TAG_PROTO_MTK;\ndrivers/net/dsa/mt7530.c-1333-}\n--\ndrivers/net/ethernet/airoha/airoha_eth.c=2525=static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev)\n--\ndrivers/net/ethernet/airoha/airoha_eth.c-2534-\ndrivers/net/ethernet/airoha/airoha_eth.c:2535:\tif (dev-\u003edsa_ptr-\u003etag_ops-\u003eproto != DSA_TAG_PROTO_MTK)\ndrivers/net/ethernet/airoha/airoha_eth.c-2536-\t\treturn 0;\n--\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c=3540=static bool mtk_uses_dsa(struct net_device *dev)\n--\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c-3543-\treturn netdev_uses_dsa(dev) \u0026\u0026\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c:3544:\t dev-\u003edsa_ptr-\u003etag_ops-\u003eproto == DSA_TAG_PROTO_MTK;\ndrivers/net/ethernet/mediatek/mtk_eth_soc.c-3545-#else\n--\ndrivers/net/ethernet/mediatek/mtk_ppe.c=738=void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)\n--\ndrivers/net/ethernet/mediatek/mtk_ppe.c-788-\t\tif (!netdev_uses_dsa(skb-\u003edev) ||\ndrivers/net/ethernet/mediatek/mtk_ppe.c:789:\t\t skb-\u003edev-\u003edsa_ptr-\u003etag_ops-\u003eproto != DSA_TAG_PROTO_MTK)\ndrivers/net/ethernet/mediatek/mtk_ppe.c-790-\t\t\tgoto out;\n--\ndrivers/net/ethernet/mediatek/mtk_ppe_offload.c=179=mtk_flow_get_dsa_port(struct net_device **dev)\n--\ndrivers/net/ethernet/mediatek/mtk_ppe_offload.c-187-\ndrivers/net/ethernet/mediatek/mtk_ppe_offload.c:188:\tif (dp-\u003ecpu_dp-\u003etag_ops-\u003eproto != DSA_TAG_PROTO_MTK)\ndrivers/net/ethernet/mediatek/mtk_ppe_offload.c-189-\t\treturn -ENODEV;\n--\ninclude/net/dsa.h=26=struct tc_action;\n--\ninclude/net/dsa.h-36-#define DSA_TAG_PROTO_LAN9303_VALUE\t\t8\ninclude/net/dsa.h:37:#define DSA_TAG_PROTO_MTK_VALUE\t\t\t9\ninclude/net/dsa.h-38-#define DSA_TAG_PROTO_QCA_VALUE\t\t\t10\n--\ninclude/net/dsa.h=66=enum dsa_tag_protocol {\n--\ninclude/net/dsa.h-77-\tDSA_TAG_PROTO_LAN9303\t\t= DSA_TAG_PROTO_LAN9303_VALUE,\ninclude/net/dsa.h:78:\tDSA_TAG_PROTO_MTK\t\t= DSA_TAG_PROTO_MTK_VALUE,\ninclude/net/dsa.h-79-\tDSA_TAG_PROTO_AIROHA\t\t= DSA_TAG_PROTO_AIROHA_VALUE,\n--\nnet/dsa/tag_mtk.c=107=static const struct dsa_device_ops mtk_netdev_ops = {\nnet/dsa/tag_mtk.c-108-\t.name\t\t= MTK_NAME,\nnet/dsa/tag_mtk.c:109:\t.proto\t\t= DSA_TAG_PROTO_MTK,\nnet/dsa/tag_mtk.c-110-\t.xmit\t\t= mtk_tag_xmit,\n--\nnet/dsa/tag_mtk.c=115=DSA_TAG_DRIVER(mtk_netdev_ops);\nnet/dsa/tag_mtk.c:116:MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);\nnet/dsa/tag_mtk.c-117-#endif\n"
} |
| 5/2 | 2026/09/15 16:36 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 135876 output: 32 thoughts: 64 Thoughts: **Investigating DSA Tag Driver Usage and Configuration** Okay, so I'm diving into this DSA stuff, specifically the drivers and how they're used. My immediate questions are: Can the user directly leverage DSA tag drivers? How is the DSA tag protocol actually configured within this framework? And a more specific query: can the `dsa_loop` driver be configured to utilize *any* tagging protocol, or is it locked down? Time to look at the source code. Let's start with `dsa_loop` in `drivers/net/dsa/dsa_loop.c`. That seems like the logical place to begin my investigation into the capabilities and limitations of this area. I need to understand the relationship between the driver, the protocol, and user-level configuration. |
| 6/2 | 2026/09/15 16:36 | tool | grepper |
0mArgs:{
"Expression": "get_tag_protocol",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "drivers/net/dsa/an8855.c=618=static int an8855_set_mac_eee(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/an8855.c-626-\ndrivers/net/dsa/an8855.c:627:static enum dsa_tag_protocol an8855_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/an8855.c-628-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/an8855.c=1595=static const struct dsa_switch_ops an8855_switch_ops = {\ndrivers/net/dsa/an8855.c:1596:\t.get_tag_protocol = an8855_get_tag_protocol,\ndrivers/net/dsa/an8855.c-1597-\t.setup = an8855_setup,\n--\ndrivers/net/dsa/b53/b53_common.c=2478=static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/b53/b53_common.c-2503-\ndrivers/net/dsa/b53/b53_common.c:2504:enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,\ndrivers/net/dsa/b53/b53_common.c-2505-\t\t\t\t\t enum dsa_tag_protocol mprot)\n--\ndrivers/net/dsa/b53/b53_common.c-2534-}\ndrivers/net/dsa/b53/b53_common.c:2535:EXPORT_SYMBOL(b53_get_tag_protocol);\ndrivers/net/dsa/b53/b53_common.c-2536-\n--\ndrivers/net/dsa/b53/b53_common.c=2701=static const struct dsa_switch_ops b53_switch_ops = {\ndrivers/net/dsa/b53/b53_common.c:2702:\t.get_tag_protocol\t= b53_get_tag_protocol,\ndrivers/net/dsa/b53/b53_common.c-2703-\t.setup\t\t\t= b53_setup,\n--\ndrivers/net/dsa/b53/b53_priv.h=547=int b53_mirror_add(struct dsa_switch *ds, int port,\n--\ndrivers/net/dsa/b53/b53_priv.h-549-\t\t struct netlink_ext_ack *extack);\ndrivers/net/dsa/b53/b53_priv.h:550:enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,\ndrivers/net/dsa/b53/b53_priv.h-551-\t\t\t\t\t enum dsa_tag_protocol mprot);\n--\ndrivers/net/dsa/bcm_sf2.c=1222=static const struct dsa_switch_ops bcm_sf2_ops = {\ndrivers/net/dsa/bcm_sf2.c:1223:\t.get_tag_protocol\t= b53_get_tag_protocol,\ndrivers/net/dsa/bcm_sf2.c-1224-\t.setup\t\t\t= bcm_sf2_sw_setup,\n--\ndrivers/net/dsa/dsa_loop.c=334=static const struct dsa_switch_ops dsa_loop_driver = {\ndrivers/net/dsa/dsa_loop.c:335:\t.get_tag_protocol\t= dsa_loop_get_protocol,\ndrivers/net/dsa/dsa_loop.c-336-\t.setup\t\t\t= dsa_loop_setup,\n--\ndrivers/net/dsa/hirschmann/hellcreek.c=227=static void hellcreek_feature_detect(struct hellcreek *hellcreek)\n--\ndrivers/net/dsa/hirschmann/hellcreek.c-239-\ndrivers/net/dsa/hirschmann/hellcreek.c:240:static enum dsa_tag_protocol hellcreek_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/hirschmann/hellcreek.c-241-\t\t\t\t\t\t\tint port,\n--\ndrivers/net/dsa/hirschmann/hellcreek.c=1900=static const struct dsa_switch_ops hellcreek_ds_ops = {\n--\ndrivers/net/dsa/hirschmann/hellcreek.c-1904-\t.get_strings\t = hellcreek_get_strings,\ndrivers/net/dsa/hirschmann/hellcreek.c:1905:\t.get_tag_protocol = hellcreek_get_tag_protocol,\ndrivers/net/dsa/hirschmann/hellcreek.c-1906-\t.get_ts_info\t = hellcreek_get_ts_info,\n--\ndrivers/net/dsa/ks8995.c=530=static enum\ndrivers/net/dsa/ks8995.c:531:dsa_tag_protocol ks8995_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/ks8995.c-532-\t\t\t\t\t int port,\n--\ndrivers/net/dsa/ks8995.c=732=static const struct dsa_switch_ops ks8995_ds_ops = {\ndrivers/net/dsa/ks8995.c:733:\t.get_tag_protocol = ks8995_get_tag_protocol,\ndrivers/net/dsa/ks8995.c-734-\t.setup = ks8995_setup,\n--\ndrivers/net/dsa/lan9303-core.c=867=static int lan9303_check_device(struct lan9303 *chip)\n--\ndrivers/net/dsa/lan9303-core.c-936-\ndrivers/net/dsa/lan9303-core.c:937:static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/lan9303-core.c-938-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/lan9303-core.c=1382=static const struct dsa_switch_ops lan9303_switch_ops = {\ndrivers/net/dsa/lan9303-core.c:1383:\t.get_tag_protocol\t= lan9303_get_tag_protocol,\ndrivers/net/dsa/lan9303-core.c-1384-\t.setup\t\t\t= lan9303_setup,\n--\ndrivers/net/dsa/lantiq/lantiq_gswip_common.c=742=static void gswip_teardown(struct dsa_switch *ds)\n--\ndrivers/net/dsa/lantiq/lantiq_gswip_common.c-748-\ndrivers/net/dsa/lantiq/lantiq_gswip_common.c:749:static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/lantiq/lantiq_gswip_common.c-750-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/lantiq/lantiq_gswip_common.c=1624=static const struct dsa_switch_ops gswip_switch_ops = {\ndrivers/net/dsa/lantiq/lantiq_gswip_common.c:1625:\t.get_tag_protocol\t= gswip_get_tag_protocol,\ndrivers/net/dsa/lantiq/lantiq_gswip_common.c-1626-\t.setup\t\t\t= gswip_setup,\n--\ndrivers/net/dsa/microchip/ksz8.c=2970=static int ksz8_switch_init(struct ksz_device *dev)\n--\ndrivers/net/dsa/microchip/ksz8.c-2978-\ndrivers/net/dsa/microchip/ksz8.c:2979:static enum dsa_tag_protocol ksz8463_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/microchip/ksz8.c-2980-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/microchip/ksz8.c=2986=static int ksz8463_connect_tag_protocol(struct dsa_switch *ds,\n--\ndrivers/net/dsa/microchip/ksz8.c-2999-\ndrivers/net/dsa/microchip/ksz8.c:3000:static enum dsa_tag_protocol ksz87xx_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/microchip/ksz8.c-3001-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/microchip/ksz8.c=3007=static int ksz87xx_connect_tag_protocol(struct dsa_switch *ds,\n--\ndrivers/net/dsa/microchip/ksz8.c-3015-\ndrivers/net/dsa/microchip/ksz8.c:3016:static enum dsa_tag_protocol ksz88xx_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/microchip/ksz8.c-3017-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/microchip/ksz8.c=3114=const struct dsa_switch_ops ksz8463_switch_ops = {\ndrivers/net/dsa/microchip/ksz8.c:3115:\t.get_tag_protocol\t= ksz8463_get_tag_protocol,\ndrivers/net/dsa/microchip/ksz8.c-3116-\t.connect_tag_protocol = ksz8463_connect_tag_protocol,\n--\ndrivers/net/dsa/microchip/ksz8.c=3161=const struct dsa_switch_ops ksz87xx_switch_ops = {\ndrivers/net/dsa/microchip/ksz8.c:3162:\t.get_tag_protocol\t= ksz87xx_get_tag_protocol,\ndrivers/net/dsa/microchip/ksz8.c-3163-\t.connect_tag_protocol = ksz87xx_connect_tag_protocol,\n--\ndrivers/net/dsa/microchip/ksz8.c=3211=const struct dsa_switch_ops ksz88xx_switch_ops = {\ndrivers/net/dsa/microchip/ksz8.c:3212:\t.get_tag_protocol\t= ksz88xx_get_tag_protocol,\ndrivers/net/dsa/microchip/ksz8.c-3213-\t.connect_tag_protocol = ksz88xx_connect_tag_protocol,\n--\ndrivers/net/dsa/microchip/ksz9477.c=1970=static int ksz9477_switch_init(struct ksz_device *dev)\n--\ndrivers/net/dsa/microchip/ksz9477.c-1989-\ndrivers/net/dsa/microchip/ksz9477.c:1990:static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/microchip/ksz9477.c-1991-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/microchip/ksz9477.c=2215=const struct dsa_switch_ops ksz9477_switch_ops = {\ndrivers/net/dsa/microchip/ksz9477.c:2216:\t.get_tag_protocol\t= ksz9477_get_tag_protocol,\ndrivers/net/dsa/microchip/ksz9477.c-2217-\t.connect_tag_protocol = ksz9477_connect_tag_protocol,\n--\ndrivers/net/dsa/microchip/lan937x_main.c=768=static int lan937x_setup(struct dsa_switch *ds)\n--\ndrivers/net/dsa/microchip/lan937x_main.c-907-\ndrivers/net/dsa/microchip/lan937x_main.c:908:static enum dsa_tag_protocol lan937x_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/microchip/lan937x_main.c-909-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/microchip/lan937x_main.c=949=const struct dsa_switch_ops lan937x_switch_ops = {\ndrivers/net/dsa/microchip/lan937x_main.c:950:\t.get_tag_protocol\t= lan937x_get_tag_protocol,\ndrivers/net/dsa/microchip/lan937x_main.c-951-\t.connect_tag_protocol = lan937x_connect_tag_protocol,\n--\ndrivers/net/dsa/motorcomm/chip.c=4104=static enum dsa_tag_protocol\ndrivers/net/dsa/motorcomm/chip.c:4105:yt921x_dsa_get_tag_protocol(struct dsa_switch *ds, int port,\ndrivers/net/dsa/motorcomm/chip.c-4106-\t\t\t enum dsa_tag_protocol m)\n--\ndrivers/net/dsa/motorcomm/chip.c=4607=static const struct dsa_switch_ops yt921x_dsa_switch_ops = {\n--\ndrivers/net/dsa/motorcomm/chip.c-4667-\t/* port */\ndrivers/net/dsa/motorcomm/chip.c:4668:\t.get_tag_protocol\t= yt921x_dsa_get_tag_protocol,\ndrivers/net/dsa/motorcomm/chip.c-4669-\t.phylink_get_caps\t= yt921x_dsa_phylink_get_caps,\n--\ndrivers/net/dsa/mt7530.c=1328=static enum dsa_tag_protocol\ndrivers/net/dsa/mt7530.c:1329:mtk_get_tag_protocol(struct dsa_switch *ds, int port,\ndrivers/net/dsa/mt7530.c-1330-\t\t enum dsa_tag_protocol mp)\n--\ndrivers/net/dsa/mt7530.c=2623=static const struct dsa_switch_ops mt7530_switch_ops = {\ndrivers/net/dsa/mt7530.c:2624:\t.get_tag_protocol\t= mtk_get_tag_protocol,\ndrivers/net/dsa/mt7530.c-2625-\t.setup\t\t\t= mt753x_setup,\n--\ndrivers/net/dsa/mt7628.c=554=static const struct dsa_switch_ops mt7628_switch_ops = {\ndrivers/net/dsa/mt7628.c:555:\t.get_tag_protocol = mt7628_get_tag_proto,\ndrivers/net/dsa/mt7628.c-556-\t.setup = mt7628_setup,\n--\ndrivers/net/dsa/mv88e6060.c=27=static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)\n--\ndrivers/net/dsa/mv88e6060.c-44-\ndrivers/net/dsa/mv88e6060.c:45:static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/mv88e6060.c-46-\t\t\t\t\t\t\tint port,\n--\ndrivers/net/dsa/mv88e6060.c=294=static const struct dsa_switch_ops mv88e6060_switch_ops = {\ndrivers/net/dsa/mv88e6060.c:295:\t.get_tag_protocol = mv88e6060_get_tag_protocol,\ndrivers/net/dsa/mv88e6060.c-296-\t.setup\t\t= mv88e6060_setup,\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=6635=static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)\n--\ndrivers/net/dsa/mv88e6xxx/chip.c-6653-\ndrivers/net/dsa/mv88e6xxx/chip.c:6654:static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/mv88e6xxx/chip.c-6655-\t\t\t\t\t\t\tint port,\n--\ndrivers/net/dsa/mv88e6xxx/chip.c=7195=static const struct dsa_switch_ops mv88e6xxx_switch_ops = {\ndrivers/net/dsa/mv88e6xxx/chip.c:7196:\t.get_tag_protocol\t= mv88e6xxx_get_tag_protocol,\ndrivers/net/dsa/mv88e6xxx/chip.c-7197-\t.change_tag_protocol\t= mv88e6xxx_change_tag_protocol,\n--\ndrivers/net/dsa/mxl862xx/mxl862xx.c=159=static const struct mxl862xx_evlan_rule_desc vid_accept_egress_unaware[] = {\n--\ndrivers/net/dsa/mxl862xx/mxl862xx.c-163-\ndrivers/net/dsa/mxl862xx/mxl862xx.c:164:static enum dsa_tag_protocol mxl862xx_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/mxl862xx/mxl862xx.c-165-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/mxl862xx/mxl862xx.c=2057=static const struct dsa_switch_ops mxl862xx_switch_ops = {\ndrivers/net/dsa/mxl862xx/mxl862xx.c:2058:\t.get_tag_protocol = mxl862xx_get_tag_protocol,\ndrivers/net/dsa/mxl862xx/mxl862xx.c-2059-\t.setup = mxl862xx_setup,\n--\ndrivers/net/dsa/netc/netc_main.c=61=static enum dsa_tag_protocol\ndrivers/net/dsa/netc/netc_main.c:62:netc_get_tag_protocol(struct dsa_switch *ds, int port,\ndrivers/net/dsa/netc/netc_main.c-63-\t\t enum dsa_tag_protocol mprot)\n--\ndrivers/net/dsa/netc/netc_main.c=2403=static const struct dsa_switch_ops netc_switch_ops = {\ndrivers/net/dsa/netc/netc_main.c:2404:\t.get_tag_protocol\t\t= netc_get_tag_protocol,\ndrivers/net/dsa/netc/netc_main.c-2405-\t.setup\t\t\t\t= netc_setup,\n--\ndrivers/net/dsa/ocelot/felix.c=754=static int felix_change_tag_protocol(struct dsa_switch *ds,\n--\ndrivers/net/dsa/ocelot/felix.c-800-\ndrivers/net/dsa/ocelot/felix.c:801:static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/ocelot/felix.c-802-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/ocelot/felix.c=2306=static const struct dsa_switch_ops felix_switch_ops = {\ndrivers/net/dsa/ocelot/felix.c:2307:\t.get_tag_protocol\t\t= felix_get_tag_protocol,\ndrivers/net/dsa/ocelot/felix.c-2308-\t.change_tag_protocol\t\t= felix_change_tag_protocol,\n--\ndrivers/net/dsa/qca/ar9331.c=485=static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)\n--\ndrivers/net/dsa/qca/ar9331.c-495-\ndrivers/net/dsa/qca/ar9331.c:496:static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/qca/ar9331.c-497-\t\t\t\t\t\t\tint port,\n--\ndrivers/net/dsa/qca/ar9331.c=696=static const struct dsa_switch_ops ar9331_sw_ops = {\ndrivers/net/dsa/qca/ar9331.c:697:\t.get_tag_protocol\t= ar9331_sw_get_tag_protocol,\ndrivers/net/dsa/qca/ar9331.c-698-\t.setup\t\t\t= ar9331_sw_setup,\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=1755=static enum dsa_tag_protocol\ndrivers/net/dsa/qca/qca8k-8xxx.c:1756:qca8k_get_tag_protocol(struct dsa_switch *ds, int port,\ndrivers/net/dsa/qca/qca8k-8xxx.c-1757-\t\t enum dsa_tag_protocol mp)\n--\ndrivers/net/dsa/qca/qca8k-8xxx.c=2021=static const struct dsa_switch_ops qca8k_switch_ops = {\ndrivers/net/dsa/qca/qca8k-8xxx.c:2022:\t.get_tag_protocol\t= qca8k_get_tag_protocol,\ndrivers/net/dsa/qca/qca8k-8xxx.c-2023-\t.setup\t\t\t= qca8k_setup,\n--\ndrivers/net/dsa/realtek/rtl8365mb_main.c=1063=static enum dsa_tag_protocol\ndrivers/net/dsa/realtek/rtl8365mb_main.c:1064:rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port,\ndrivers/net/dsa/realtek/rtl8365mb_main.c-1065-\t\t\t enum dsa_tag_protocol mp)\n--\ndrivers/net/dsa/realtek/rtl8365mb_main.c=3285=static const struct dsa_switch_ops rtl8365mb_switch_ops = {\ndrivers/net/dsa/realtek/rtl8365mb_main.c:3286:\t.get_tag_protocol = rtl8365mb_get_tag_protocol,\ndrivers/net/dsa/realtek/rtl8365mb_main.c-3287-\t.change_tag_protocol = rtl8365mb_change_tag_protocol,\n--\ndrivers/net/dsa/realtek/rtl8366rb.c=866=static int rtl8366rb_setup(struct dsa_switch *ds)\n--\ndrivers/net/dsa/realtek/rtl8366rb.c-1129-\ndrivers/net/dsa/realtek/rtl8366rb.c:1130:static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/realtek/rtl8366rb.c-1131-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/realtek/rtl8366rb.c=1787=static const struct dsa_switch_ops rtl8366rb_switch_ops = {\ndrivers/net/dsa/realtek/rtl8366rb.c:1788:\t.get_tag_protocol = rtl8366_get_tag_protocol,\ndrivers/net/dsa/realtek/rtl8366rb.c-1789-\t.setup = rtl8366rb_setup,\n--\ndrivers/net/dsa/rzn1_a5psw.c=81=static void a5psw_reg_rmw(struct a5psw *a5psw, int offset, u32 mask, u32 val)\n--\ndrivers/net/dsa/rzn1_a5psw.c-94-\ndrivers/net/dsa/rzn1_a5psw.c:95:static enum dsa_tag_protocol a5psw_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/rzn1_a5psw.c-96-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/rzn1_a5psw.c=1011=static const struct dsa_switch_ops a5psw_switch_ops = {\ndrivers/net/dsa/rzn1_a5psw.c:1012:\t.get_tag_protocol = a5psw_get_tag_protocol,\ndrivers/net/dsa/rzn1_a5psw.c-1013-\t.setup = a5psw_setup,\n--\ndrivers/net/dsa/sja1105/sja1105_main.c=2355=static enum dsa_tag_protocol\ndrivers/net/dsa/sja1105/sja1105_main.c:2356:sja1105_get_tag_protocol(struct dsa_switch *ds, int port,\ndrivers/net/dsa/sja1105/sja1105_main.c-2357-\t\t\t enum dsa_tag_protocol mp)\n--\ndrivers/net/dsa/sja1105/sja1105_main.c=3143=static const struct dsa_switch_ops sja1105_switch_ops = {\ndrivers/net/dsa/sja1105/sja1105_main.c:3144:\t.get_tag_protocol\t= sja1105_get_tag_protocol,\ndrivers/net/dsa/sja1105/sja1105_main.c-3145-\t.connect_tag_protocol\t= sja1105_connect_tag_protocol,\n--\ndrivers/net/dsa/vitesse-vsc73xx-core.c=662=static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum,\n--\ndrivers/net/dsa/vitesse-vsc73xx-core.c-685-\ndrivers/net/dsa/vitesse-vsc73xx-core.c:686:static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/vitesse-vsc73xx-core.c-687-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/vitesse-vsc73xx-core.c=2218=static const struct dsa_switch_ops vsc73xx_ds_ops = {\ndrivers/net/dsa/vitesse-vsc73xx-core.c:2219:\t.get_tag_protocol = vsc73xx_get_tag_protocol,\ndrivers/net/dsa/vitesse-vsc73xx-core.c-2220-\t.setup = vsc73xx_setup,\n--\ndrivers/net/dsa/xrs700x/xrs700x.c=185=static int xrs700x_setup_regmap_range(struct xrs700x *priv)\n--\ndrivers/net/dsa/xrs700x/xrs700x.c-225-\ndrivers/net/dsa/xrs700x/xrs700x.c:226:static enum dsa_tag_protocol xrs700x_get_tag_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/xrs700x/xrs700x.c-227-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/xrs700x/xrs700x.c=729=static const struct dsa_switch_ops xrs700x_ops = {\ndrivers/net/dsa/xrs700x/xrs700x.c:730:\t.get_tag_protocol\t= xrs700x_get_tag_protocol,\ndrivers/net/dsa/xrs700x/xrs700x.c-731-\t.setup\t\t\t= xrs700x_setup,\n"
} |
| 7/2 | 2026/09/15 16:36 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 143951 output: 35 thoughts: 55 Thoughts: **Investigating the `dsa_loop` Module** Okay, so I'm digging into this `dsa_loop` module, and the code indicates it relies on `dsa_loop_get_protocol`. My immediate thought is, what's *that* doing? I need to understand this dependency. So, I'm heading straight for the source code to get a clearer picture. Let's get into `drivers/net/dsa/dsa_loop.c` and see what's happening under the hood with `dsa_loop_get_protocol`. I'm expecting some protocol-specific details, likely some critical function calls. |
| 8/2 | 2026/09/15 16:37 | tool | grepper |
0mArgs:{
"Expression": "dsa_loop_get_protocol",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "drivers/net/dsa/dsa_loop.c=97=static int dsa_loop_setup_devlink_resources(struct dsa_switch *ds)\n--\ndrivers/net/dsa/dsa_loop.c-124-\ndrivers/net/dsa/dsa_loop.c:125:static enum dsa_tag_protocol dsa_loop_get_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/dsa_loop.c-126-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/dsa_loop.c=334=static const struct dsa_switch_ops dsa_loop_driver = {\ndrivers/net/dsa/dsa_loop.c:335:\t.get_tag_protocol\t= dsa_loop_get_protocol,\ndrivers/net/dsa/dsa_loop.c-336-\t.setup\t\t\t= dsa_loop_setup,\n"
} |
| 9/2 | 2026/09/15 16:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 144429 output: 41 thoughts: 26 Thoughts: Here's a summary of my mental process: **Diving into the DSA Loop** Okay, time to get my hands dirty. I'm thinking I need to understand what's going on within the `drivers/net/dsa/dsa_loop.c` file, specifically around line 125. This likely points to a critical section of the code, maybe a key function or data structure definition related to the DSA loopback driver. I'm expecting to find something fundamental to its operation there. Let's see what's what. |
| 10/2 | 2026/09/15 16:37 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/dsa_loop.c",
"FirstLine": 120,
"LineCount": 40
}Results: {
"Contents": " 120:\tout:\n 121:\t\tdsa_devlink_resources_unregister(ds);\n 122:\t\treturn err;\n 123:\t}\n 124:\t\n 125:\tstatic enum dsa_tag_protocol dsa_loop_get_protocol(struct dsa_switch *ds,\n 126:\t\t\t\t\t\t\t int port,\n 127:\t\t\t\t\t\t\t enum dsa_tag_protocol mp)\n 128:\t{\n 129:\t\tdev_dbg(ds-\u003edev, \"%s: port: %d\\n\", __func__, port);\n 130:\t\n 131:\t\treturn DSA_TAG_PROTO_NONE;\n 132:\t}\n 133:\t\n 134:\tstatic int dsa_loop_setup(struct dsa_switch *ds)\n 135:\t{\n 136:\t\tstruct dsa_loop_priv *ps = ds-\u003epriv;\n 137:\t\tunsigned int i;\n 138:\t\n 139:\t\tfor (i = 0; i \u003c ds-\u003enum_ports; i++)\n 140:\t\t\tmemcpy(ps-\u003eports[i].mib, dsa_loop_mibs,\n 141:\t\t\t sizeof(dsa_loop_mibs));\n 142:\t\n 143:\t\tdev_dbg(ds-\u003edev, \"%s\\n\", __func__);\n 144:\t\n 145:\t\treturn dsa_loop_setup_devlink_resources(ds);\n 146:\t}\n 147:\t\n 148:\tstatic void dsa_loop_teardown(struct dsa_switch *ds)\n 149:\t{\n 150:\t\tdsa_devlink_resources_unregister(ds);\n 151:\t}\n 152:\t\n 153:\tstatic int dsa_loop_get_sset_count(struct dsa_switch *ds, int port, int sset)\n 154:\t{\n 155:\t\tif (sset != ETH_SS_STATS \u0026\u0026 sset != ETH_SS_PHY_STATS)\n 156:\t\t\treturn 0;\n 157:\t\n 158:\t\treturn __DSA_LOOP_CNT_MAX;\n 159:\t}\n"
} |
| 11/2 | 2026/09/15 16:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 145211 output: 36 thoughts: 2051 Thoughts: **Okay, let's break this down.** The initial observation was that `dsa_loop` returned `DSA_TAG_PROTO_NONE`. My immediate thought was to check `net/dsa/tag_mtk.c`, and specifically what changes had occurred there. A quick `git diff` revealed that the core `mtk_tag_xmit` and `mtk_tag_rcv` functions remained untouched. The key change was the addition of `airoha_netdev_ops`, essentially registering it as a new tag driver alongside the existing `mtk_netdev_ops`. This indicated support for a new hardware platform or tag protocol, specifically Airoha's. Next, I looked at the complete set of files modified in this commit to get a broader context. A list of 24 files was provided and my attention focused on several specific drivers: `airoha-an8855.c`, `an8855.c`, `air_an8855.c`, `mt7530-lib.c`, and `mt7530.c`. These file names are likely the most important. I then started to investigate the hardware associated with these drivers. I realized that the Airoha AN8855 is a System-on-a-Chip (SoC) that integrates an Ethernet switch, NVMEM, and Ethernet PHYs. I examined the `airoha-an8855.c` driver. I saw that this is an MDIO driver. Crucially, it matches the device tree compatible string "airoha,an8855". This means it's designed to interface with the AN8855 switch chip via an MDIO bus, common on OpenWrt router boards using MediaTek MT7988. I considered if I could test this in QEMU, but quickly recognized that MDIO and device tree are not standard on x86_64, and especially not emulated in QEMU. Also the `drivers/mfd/Kconfig` specifies it `depends on OF`, meaning it needs real hardware. I moved on to `an8855.c`. This is a switch driver probed using the compatible "airoha,an8855-switch". This driver is registered as an MFD cell by `airoha-an8855.c`, solidifying that the switch driver only functions if the MDIO device is present. `air_an8855.c` is a PHY driver for PHY ID 0xc0ff0410. This driver is only registered when the MDIO bus probes the PHY. Finally, I began to look at `mt7530.c`, `mt7530-lib.c`, `mt7530-mdio.c` and `mt7530-mmio.c`, implying further integration with other hardware, which are probably the actual Ethernet switch chips. |
| 12/2 | 2026/09/15 16:37 | tool | grepper |
0mError:no matches Args: {
"Expression": "module_.*driver",
"PathPrefix": "drivers/net/dsa/mt7530"
}Results: {
"error": "no matches"
} |
| 13/2 | 2026/09/15 16:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 147950 output: 34 thoughts: 43 Thoughts: Here's my summary, as if I were thinking these thoughts: **Analyzing MT7530 Driver Implementations** Okay, so I need to get a handle on the MT7530 driver situation. I'm going to start by diving into the code. Specifically, I want to compare the `drivers/net/dsa/mt7530-mdio.c` and `drivers/net/dsa/mt7530-mmio.c` files. I'm betting there's valuable information, potentially about how they interface with different hardware configurations or different access methods for the MT7530 switch itself. Comparing these two implementations should highlight the core logic and differences between MDIO and MMIO access. That's a good starting point to understand the overall architecture and how these drivers are structured within the larger DSA framework. Let's see what's in there. |
| 14/2 | 2026/09/15 16:37 | tool | grepper |
0mError:no matches Args: {
"Expression": "_driver",
"PathPrefix": "drivers/net/dsa/mt7530"
}Results: {
"error": "no matches"
} |
| 15/2 | 2026/09/15 16:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 148234 output: 45 thoughts: 30 Thoughts: Okay, here's my interpretation of that thought process, assuming I'm a networking expert familiar with driver development: **Diving into the MT7530 MDIO Driver** Alright, I'm taking a look at `drivers/net/dsa/mt7530-mdio.c`. My immediate thought is, "Okay, I'm heading straight to the *end* of the file." This usually indicates I'm after a specific function or data structure, perhaps something like the module's initialization or probe function, or potentially the main structure definition for the MDIO bus interaction. I'm probably trying to quickly grasp the high-level architecture of how this particular driver interfaces with the MT7530 switch and the broader MDIO subsystem. I want to see how it registers itself, how it handles device probing, and get a feel for the control flow. The file's probably substantial, so jumping to the end lets me zoom in on the critical entry points before I get bogged down in the lower-level supporting functions or helper routines. It's a quick way to get the gist of things before a deeper dive. |
| 16/2 | 2026/09/15 16:37 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530-mdio.c",
"FirstLine": 240,
"LineCount": 40
}Results: {
"Contents": " 240:\t\tret = regulator_disable(priv-\u003ecore_pwr);\n 241:\t\tif (ret \u003c 0)\n 242:\t\t\tdev_err(priv-\u003edev,\n 243:\t\t\t\t\"Failed to disable core power: %d\\n\", ret);\n 244:\t\n 245:\t\tret = regulator_disable(priv-\u003eio_pwr);\n 246:\t\tif (ret \u003c 0)\n 247:\t\t\tdev_err(priv-\u003edev, \"Failed to disable io pwr: %d\\n\",\n 248:\t\t\t\tret);\n 249:\t\n 250:\t\tmt7530_remove_common(priv);\n 251:\t\n 252:\t\tfor (i = 0; i \u003c 2; ++i)\n 253:\t\t\tmtk_pcs_lynxi_destroy(priv-\u003eports[5 + i].sgmii_pcs);\n 254:\t}\n 255:\t\n 256:\tstatic void mt7530_shutdown(struct mdio_device *mdiodev)\n 257:\t{\n 258:\t\tstruct mt7530_priv *priv = dev_get_drvdata(\u0026mdiodev-\u003edev);\n 259:\t\n 260:\t\tif (!priv)\n 261:\t\t\treturn;\n 262:\t\n 263:\t\tdsa_switch_shutdown(priv-\u003eds);\n 264:\t\n 265:\t\tdev_set_drvdata(\u0026mdiodev-\u003edev, NULL);\n 266:\t}\n 267:\t\n 268:\tstatic struct mdio_driver mt7530_mdio_driver = {\n 269:\t\t.probe = mt7530_probe,\n 270:\t\t.remove = mt7530_remove,\n 271:\t\t.shutdown = mt7530_shutdown,\n 272:\t\t.mdiodrv.driver = {\n 273:\t\t\t.name = \"mt7530-mdio\",\n 274:\t\t\t.of_match_table = mt7530_of_match,\n 275:\t\t},\n 276:\t};\n 277:\t\n 278:\tmdio_module_driver(mt7530_mdio_driver);\n 279:\t\n"
} |
| 17/2 | 2026/09/15 16:37 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 149168 output: 44 thoughts: 53 Thoughts: Here's my summary, as the expert: **Investigating the MT7530 Driver Structure** Okay, so `mt7530_mdio_driver` is registered as an `mdio_driver`. That's the starting point. The driver is matched via the `mt7530_of_match` table, which is expected. Now, what's interesting is where the device information is found. Is the device MMIO or MDIO based? I need to confirm if `mt7530-mmio.c` provides supplementary information or if it's the main driver. Time to dig in and clarify the architecture. |
| 18/2 | 2026/09/15 16:37 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/mt7530-mmio.c",
"FirstLine": 80,
"LineCount": 40
}Results: {
"Contents": " 80:\t{\n 81:\t\tstruct mt7530_priv *priv = platform_get_drvdata(pdev);\n 82:\t\n 83:\t\tif (!priv)\n 84:\t\t\treturn;\n 85:\t\n 86:\t\tdsa_switch_shutdown(priv-\u003eds);\n 87:\t\n 88:\t\tdev_set_drvdata(\u0026pdev-\u003edev, NULL);\n 89:\t}\n 90:\t\n 91:\tstatic struct platform_driver mt7988_platform_driver = {\n 92:\t\t.probe = mt7988_probe,\n 93:\t\t.remove = mt7988_remove,\n 94:\t\t.shutdown = mt7988_shutdown,\n 95:\t\t.driver = {\n 96:\t\t\t.name = \"mt7530-mmio\",\n 97:\t\t\t.of_match_table = mt7988_of_match,\n 98:\t\t},\n 99:\t};\n 100:\tmodule_platform_driver(mt7988_platform_driver);\n 101:\t\n 102:\tMODULE_AUTHOR(\"Daniel Golle \u003cdaniel@makrotopia.org\u003e\");\n 103:\tMODULE_DESCRIPTION(\"Driver for Mediatek MT7530 Switch (MMIO)\");\n 104:\tMODULE_LICENSE(\"GPL\");\n"
} |
| 19/2 | 2026/09/15 16:37 | llm | patch-evaluator |
1mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 149774 output: 27 thoughts: 164 Thoughts: **My Initial Assessment of the `mt7988_of_match` Driver** Okay, so `mt7988_of_match` is a platform driver, using an OF match table, got it. This makes sense. The key is it handles devices like `mt7530` and `mt7988`. These are MediaTek network router switch ASICs; the `mt7530` is external, and `mt7988` is integrated. They're found in various MediaTek router SoCs, like the MT7621 and MT7988, or connected externally via MDIO. Now, the important caveat. I know from experience that neither `mt7530` nor `AN8855` are emulated by standard QEMU or Google Compute Engine. These platforms are notorious for leaving out low-level hardware details. I need to be sure about this assumption, and verify that these parts are *exclusively* used on actual hardware. Therefore, before I go further down this rabbit hole, I must perform a quick sanity check. Let me dig into the kernel source tree and verify that `mt7530` and `AN8855` aren't being instantiated or configured in any other unexpected locations, outside the standard DSA driver or the device tree files under `arch/arm*/boot/dts`. I can't afford to waste time chasing something that's already handled elsewhere. Let's see what turns up. |
| 20/2 | 2026/09/15 16:38 | tool | grepper |
0mArgs:{
"Expression": "(mt7530|an8855)"
}Results: {
"Output": "\nFull output is too long, showing 500 out of 2756 lines.\nUse more precise expression if possible.\n\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-3----\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml:4:$id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml#\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml=19=properties:\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-20- compatible:\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml:21: const: airoha,an8855\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-22-\n--\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-30- type: object\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml:31: $ref: /schemas/nvmem/airoha,an8855-efuse.yaml\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-32- description: EFUSE exposed by the Airoha AN8855 SoC\n--\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-35- type: object\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml:36: $ref: /schemas/net/dsa/airoha,an8855-switch.yaml\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-37- description: Switch exposed by the Airoha AN8855 SoC\n--\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml=53=examples:\n--\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-61- soc@1 {\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml:62: compatible = \"airoha,an8855\";\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-63- reg = \u003c1\u003e;\n--\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-67- efuse {\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml:68: compatible = \"airoha,an8855-efuse\";\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-69-\n--\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-111- ethernet-switch {\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml:112: compatible = \"airoha,an8855-switch\";\nDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml-113-\n--\nDocumentation/devicetree/bindings/net/airoha,an8855-phy.yaml-3----\nDocumentation/devicetree/bindings/net/airoha,an8855-phy.yaml:4:$id: http://devicetree.org/schemas/net/airoha,an8855-phy.yaml#\nDocumentation/devicetree/bindings/net/airoha,an8855-phy.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml-3----\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml:4:$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml#\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml=20=properties:\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml-21- compatible:\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml:22: const: airoha,an8855-switch\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml-23-\n--\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml=29=examples:\n--\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml-31- ethernet-switch {\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml:32: compatible = \"airoha,an8855-switch\";\nDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml-33-\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-3----\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml:4:$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml=76=properties:\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-80- Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml:81: const: mediatek,mt7530\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-82-\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml=206=$defs:\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-218-\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml:219: mt7530-dsa-port:\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-220- patternProperties:\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml=273=allOf:\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-291- compatible:\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml:292: const: mediatek,mt7530\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-293- then:\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml:294: $ref: \"#/$defs/mt7530-dsa-port\"\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-295- required:\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-313- then:\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml:314: $ref: \"#/$defs/mt7530-dsa-port\"\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-315- required:\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml=335=examples:\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-344- switch@1f {\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml:345: compatible = \"mediatek,mt7530\";\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-346- reg = \u003c0x1f\u003e;\n--\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-405- switch@1f {\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml:406: compatible = \"mediatek,mt7530\";\nDocumentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml-407- reg = \u003c0x1f\u003e;\n--\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml-3----\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml:4:$id: http://devicetree.org/schemas/nvmem/airoha,an8855-efuse.yaml#\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml-5-$schema: http://devicetree.org/meta-schemas/core.yaml#\n--\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml=18=properties:\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml-19- compatible:\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml:20: const: airoha,an8855-efuse\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml-21-\n--\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml=31=examples:\n--\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml-33- efuse {\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml:34: compatible = \"airoha,an8855-efuse\";\nDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml-35-\n--\nMAINTAINERS=767=S:\tMaintained\nMAINTAINERS:768:F:\tDocumentation/devicetree/bindings/mfd/airoha,an8855.yaml\nMAINTAINERS:769:F:\tDocumentation/devicetree/bindings/net/airoha,an8855-phy.yaml\nMAINTAINERS:770:F:\tDocumentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml\nMAINTAINERS:771:F:\tDocumentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml\nMAINTAINERS:772:F:\tdrivers/mfd/airoha-an8855.c\nMAINTAINERS:773:F:\tdrivers/net/dsa/an8855.c\nMAINTAINERS:774:F:\tdrivers/net/dsa/an8855.h\nMAINTAINERS:775:F:\tdrivers/net/phy/air_an8855.c\nMAINTAINERS:776:F:\tdrivers/nvmem/an8855-efuse.c\nMAINTAINERS-777-\n--\nMAINTAINERS=16839=S:\tMaintained\nMAINTAINERS:16840:F:\tdrivers/net/dsa/mt7530-mdio.c\nMAINTAINERS:16841:F:\tdrivers/net/dsa/mt7530-mmio.c\nMAINTAINERS:16842:F:\tdrivers/net/dsa/mt7530.*\nMAINTAINERS-16843-F:\tnet/dsa/tag_mtk.c\n--\narch/arm/boot/dts/mediatek/mt7623a.dtsi=50=\t\tswitch0: switch@1f {\narch/arm/boot/dts/mediatek/mt7623a.dtsi:51:\t\t\tcompatible = \"mediatek,mt7530\";\narch/arm/boot/dts/mediatek/mt7623a.dtsi-52-\t\t\treg = \u003c0x1f\u003e;\n--\narch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts=203=\t\tswitch@1f {\narch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts:204:\t\t\tcompatible = \"mediatek,mt7530\";\narch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts-205-\t\t\treg = \u003c0x1f\u003e;\n--\narch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts=188=\t\tswitch@1f {\narch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts:189:\t\t\tcompatible = \"mediatek,mt7530\";\narch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts-190-\t\t\treg = \u003c0x1f\u003e;\n--\ndrivers/mfd/Makefile=10=obj-$(CONFIG_MFD_88PM886_PMIC)\t+= 88pm886.o\ndrivers/mfd/Makefile:11:obj-$(CONFIG_MFD_AIROHA_AN8855)\t+= airoha-an8855.o\ndrivers/mfd/Makefile-12-obj-$(CONFIG_MFD_ACT8945A)\t+= act8945a.o\n--\ndrivers/mfd/airoha-an8855.c-55-\ndrivers/mfd/airoha-an8855.c:56:struct an8855_core_priv {\ndrivers/mfd/airoha-an8855.c-57-\tstruct mii_bus *bus;\n--\ndrivers/mfd/airoha-an8855.c-62-\ndrivers/mfd/airoha-an8855.c:63:struct an8855_phy_priv {\ndrivers/mfd/airoha-an8855.c-64-\tu8 addr;\ndrivers/mfd/airoha-an8855.c:65:\tstruct an8855_core_priv *core;\ndrivers/mfd/airoha-an8855.c-66-};\ndrivers/mfd/airoha-an8855.c-67-\ndrivers/mfd/airoha-an8855.c:68:struct an8855_phy_bus {\ndrivers/mfd/airoha-an8855.c-69-\tstruct mii_bus *bus;\n--\ndrivers/mfd/airoha-an8855.c-73-\ndrivers/mfd/airoha-an8855.c:74:static const struct mfd_cell an8855_cells[] = {\ndrivers/mfd/airoha-an8855.c:75:\tMFD_CELL_OF(\"an8855-efuse\", NULL, NULL, 0, 0,\ndrivers/mfd/airoha-an8855.c:76:\t\t \"airoha,an8855-efuse\"),\ndrivers/mfd/airoha-an8855.c:77:\tMFD_CELL_OF(\"an8855-switch\", NULL, NULL, 0, 0,\ndrivers/mfd/airoha-an8855.c:78:\t\t \"airoha,an8855-switch\"),\ndrivers/mfd/airoha-an8855.c-79-};\ndrivers/mfd/airoha-an8855.c-80-\ndrivers/mfd/airoha-an8855.c:81:static int an8855_mii_set_page(struct an8855_core_priv *priv, u8 addr,\ndrivers/mfd/airoha-an8855.c-82-\t\t\t u8 page) __must_hold(\u0026priv-\u003ebus-\u003emdio_lock)\n--\ndrivers/mfd/airoha-an8855.c-97-\ndrivers/mfd/airoha-an8855.c:98:static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,\ndrivers/mfd/airoha-an8855.c-99-\t\t\t u32 *val) __must_hold(\u0026bus-\u003emdio_lock)\n--\ndrivers/mfd/airoha-an8855.c-141- */\ndrivers/mfd/airoha-an8855.c:142:static void an8855_regmap_lock(struct an8855_core_priv *priv)\ndrivers/mfd/airoha-an8855.c-143-{\n--\ndrivers/mfd/airoha-an8855.c-148-\ndrivers/mfd/airoha-an8855.c:149:static void an8855_regmap_unlock(struct an8855_core_priv *priv)\ndrivers/mfd/airoha-an8855.c-150-{\n--\ndrivers/mfd/airoha-an8855.c-155-\ndrivers/mfd/airoha-an8855.c:156:static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\ndrivers/mfd/airoha-an8855.c-157-{\ndrivers/mfd/airoha-an8855.c:158:\tstruct an8855_core_priv *priv = ctx;\ndrivers/mfd/airoha-an8855.c-159-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/mfd/airoha-an8855.c-162-\ndrivers/mfd/airoha-an8855.c:163:\tan8855_regmap_lock(priv);\ndrivers/mfd/airoha-an8855.c:164:\tret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);\ndrivers/mfd/airoha-an8855.c-165-\tif (ret \u003c 0)\n--\ndrivers/mfd/airoha-an8855.c-167-\ndrivers/mfd/airoha-an8855.c:168:\tret = an8855_mii_read32(bus, addr, reg, val);\ndrivers/mfd/airoha-an8855.c-169-\ndrivers/mfd/airoha-an8855.c-170-exit:\ndrivers/mfd/airoha-an8855.c:171:\tan8855_regmap_unlock(priv);\ndrivers/mfd/airoha-an8855.c-172-\n--\ndrivers/mfd/airoha-an8855.c-175-\ndrivers/mfd/airoha-an8855.c:176:static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,\ndrivers/mfd/airoha-an8855.c-177-\t\t\t u32 val) __must_hold(\u0026bus-\u003emdio_lock)\n--\ndrivers/mfd/airoha-an8855.c-207-\tdev_err_ratelimited(\u0026bus-\u003edev,\ndrivers/mfd/airoha-an8855.c:208:\t\t\t \"failed to write an8855 register\\n\");\ndrivers/mfd/airoha-an8855.c-209-\treturn ret;\n--\ndrivers/mfd/airoha-an8855.c-211-\ndrivers/mfd/airoha-an8855.c:212:static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)\ndrivers/mfd/airoha-an8855.c-213-{\ndrivers/mfd/airoha-an8855.c:214:\tstruct an8855_core_priv *priv = ctx;\ndrivers/mfd/airoha-an8855.c-215-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/mfd/airoha-an8855.c-218-\ndrivers/mfd/airoha-an8855.c:219:\tan8855_regmap_lock(priv);\ndrivers/mfd/airoha-an8855.c:220:\tret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);\ndrivers/mfd/airoha-an8855.c-221-\tif (ret)\n--\ndrivers/mfd/airoha-an8855.c-223-\ndrivers/mfd/airoha-an8855.c:224:\tret = an8855_mii_write32(bus, addr, reg, val);\ndrivers/mfd/airoha-an8855.c-225-\ndrivers/mfd/airoha-an8855.c-226-exit:\ndrivers/mfd/airoha-an8855.c:227:\tan8855_regmap_unlock(priv);\ndrivers/mfd/airoha-an8855.c-228-\n--\ndrivers/mfd/airoha-an8855.c-231-\ndrivers/mfd/airoha-an8855.c:232:static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,\ndrivers/mfd/airoha-an8855.c-233-\t\t\t\t uint32_t write_val)\ndrivers/mfd/airoha-an8855.c-234-{\ndrivers/mfd/airoha-an8855.c:235:\tstruct an8855_core_priv *priv = ctx;\ndrivers/mfd/airoha-an8855.c-236-\tstruct mii_bus *bus = priv-\u003ebus;\n--\ndrivers/mfd/airoha-an8855.c-240-\ndrivers/mfd/airoha-an8855.c:241:\tan8855_regmap_lock(priv);\ndrivers/mfd/airoha-an8855.c:242:\tret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);\ndrivers/mfd/airoha-an8855.c-243-\tif (ret)\n--\ndrivers/mfd/airoha-an8855.c-245-\ndrivers/mfd/airoha-an8855.c:246:\tret = an8855_mii_read32(bus, addr, reg, \u0026val);\ndrivers/mfd/airoha-an8855.c-247-\tif (ret \u003c 0)\n--\ndrivers/mfd/airoha-an8855.c-251-\tval |= write_val \u0026 mask;\ndrivers/mfd/airoha-an8855.c:252:\tret = an8855_mii_write32(bus, addr, reg, val);\ndrivers/mfd/airoha-an8855.c-253-\ndrivers/mfd/airoha-an8855.c-254-exit:\ndrivers/mfd/airoha-an8855.c:255:\tan8855_regmap_unlock(priv);\ndrivers/mfd/airoha-an8855.c-256-\n--\ndrivers/mfd/airoha-an8855.c-259-\ndrivers/mfd/airoha-an8855.c:260:static const struct regmap_range an8855_readable_ranges[] = {\ndrivers/mfd/airoha-an8855.c-261-\tregmap_reg_range(0x10000000, 0x10000fff), /* SCU */\n--\ndrivers/mfd/airoha-an8855.c-289-\ndrivers/mfd/airoha-an8855.c:290:static const struct regmap_access_table an8855_readable_table = {\ndrivers/mfd/airoha-an8855.c:291:\t.yes_ranges = an8855_readable_ranges,\ndrivers/mfd/airoha-an8855.c:292:\t.n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),\ndrivers/mfd/airoha-an8855.c-293-};\ndrivers/mfd/airoha-an8855.c-294-\ndrivers/mfd/airoha-an8855.c:295:static const struct regmap_config an8855_regmap_config = {\ndrivers/mfd/airoha-an8855.c-296-\t.name = \"switch\",\n--\ndrivers/mfd/airoha-an8855.c-300-\t.max_register = 0xbfffffff,\ndrivers/mfd/airoha-an8855.c:301:\t.reg_read = an8855_regmap_read,\ndrivers/mfd/airoha-an8855.c:302:\t.reg_write = an8855_regmap_write,\ndrivers/mfd/airoha-an8855.c:303:\t.reg_update_bits = an8855_regmap_update_bits,\ndrivers/mfd/airoha-an8855.c-304-\t.disable_locking = true,\ndrivers/mfd/airoha-an8855.c:305:\t.rd_table = \u0026an8855_readable_table,\ndrivers/mfd/airoha-an8855.c-306-};\ndrivers/mfd/airoha-an8855.c-307-\ndrivers/mfd/airoha-an8855.c:308:static int an8855_regmap_phy_reset_page(struct an8855_core_priv *priv,\ndrivers/mfd/airoha-an8855.c-309-\t\t\t\t\tint phy) __must_hold(\u0026priv-\u003ebus-\u003emdio_lock)\n--\ndrivers/mfd/airoha-an8855.c-322-\t */\ndrivers/mfd/airoha-an8855.c:323:\treturn an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);\ndrivers/mfd/airoha-an8855.c-324-}\ndrivers/mfd/airoha-an8855.c-325-\ndrivers/mfd/airoha-an8855.c:326:static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val)\ndrivers/mfd/airoha-an8855.c-327-{\ndrivers/mfd/airoha-an8855.c:328:\tstruct an8855_phy_priv *priv = ctx;\ndrivers/mfd/airoha-an8855.c:329:\tstruct an8855_core_priv *core_priv;\ndrivers/mfd/airoha-an8855.c-330-\tu32 addr = priv-\u003eaddr;\n--\ndrivers/mfd/airoha-an8855.c-337-\tmutex_lock_nested(\u0026bus-\u003emdio_lock, MDIO_MUTEX_NESTED);\ndrivers/mfd/airoha-an8855.c:338:\tret = an8855_regmap_phy_reset_page(core_priv, addr);\ndrivers/mfd/airoha-an8855.c-339-\tif (ret)\n--\ndrivers/mfd/airoha-an8855.c-351-\ndrivers/mfd/airoha-an8855.c:352:static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val)\ndrivers/mfd/airoha-an8855.c-353-{\ndrivers/mfd/airoha-an8855.c:354:\tstruct an8855_phy_priv *priv = ctx;\ndrivers/mfd/airoha-an8855.c:355:\tstruct an8855_core_priv *core_priv;\ndrivers/mfd/airoha-an8855.c-356-\tu32 addr = priv-\u003eaddr;\n--\ndrivers/mfd/airoha-an8855.c-363-\tmutex_lock_nested(\u0026bus-\u003emdio_lock, MDIO_MUTEX_NESTED);\ndrivers/mfd/airoha-an8855.c:364:\tret = an8855_regmap_phy_reset_page(core_priv, addr);\ndrivers/mfd/airoha-an8855.c-365-\tif (ret)\n--\ndrivers/mfd/airoha-an8855.c-375-\ndrivers/mfd/airoha-an8855.c:376:static const struct regmap_config an8855_phy_regmap_config = {\ndrivers/mfd/airoha-an8855.c-377-\t.reg_bits = 16,\ndrivers/mfd/airoha-an8855.c-378-\t.val_bits = 16,\ndrivers/mfd/airoha-an8855.c:379:\t.reg_read = an8855_regmap_phy_read,\ndrivers/mfd/airoha-an8855.c:380:\t.reg_write = an8855_regmap_phy_write,\ndrivers/mfd/airoha-an8855.c-381-\t.disable_locking = true,\n--\ndrivers/mfd/airoha-an8855.c-384-\ndrivers/mfd/airoha-an8855.c:385:static int an8855_read_switch_id(struct device *dev, struct regmap *regmap)\ndrivers/mfd/airoha-an8855.c-386-{\n--\ndrivers/mfd/airoha-an8855.c-402-\ndrivers/mfd/airoha-an8855.c:403:static int an8855_phy_bus_register(struct device *dev, struct an8855_core_priv *priv,\ndrivers/mfd/airoha-an8855.c-404-\t\t\t\t struct device_node *phy_np,\ndrivers/mfd/airoha-an8855.c:405:\t\t\t\t struct an8855_phy_bus *phy_bus_info)\ndrivers/mfd/airoha-an8855.c-406-{\ndrivers/mfd/airoha-an8855.c-407-\tstruct mdio_regmap_config mrc = { };\ndrivers/mfd/airoha-an8855.c:408:\tstruct an8855_phy_priv *phy_priv;\ndrivers/mfd/airoha-an8855.c-409-\tstruct regmap *regmap;\n--\ndrivers/mfd/airoha-an8855.c-428-\ndrivers/mfd/airoha-an8855.c:429:\tregmap = devm_regmap_init(dev, NULL, phy_priv, \u0026an8855_phy_regmap_config);\ndrivers/mfd/airoha-an8855.c-430-\tif (IS_ERR(regmap))\n--\ndrivers/mfd/airoha-an8855.c-453-\ndrivers/mfd/airoha-an8855.c:454:static int an8855_mdio_register(struct device *dev, struct an8855_core_priv *priv,\ndrivers/mfd/airoha-an8855.c:455:\t\t\t\tstruct an8855_phy_bus *phy_bus_infos)\ndrivers/mfd/airoha-an8855.c-456-{\n--\ndrivers/mfd/airoha-an8855.c-468-\ndrivers/mfd/airoha-an8855.c:469:\t\tret = an8855_phy_bus_register(dev, priv, phy_np,\ndrivers/mfd/airoha-an8855.c-470-\t\t\t\t\t \u0026phy_bus_infos[i]);\n--\ndrivers/mfd/airoha-an8855.c-480-\ndrivers/mfd/airoha-an8855.c:481:static int an8855_core_probe(struct mdio_device *mdiodev)\ndrivers/mfd/airoha-an8855.c-482-{\ndrivers/mfd/airoha-an8855.c:483:\tstruct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { };\ndrivers/mfd/airoha-an8855.c-484-\tstruct device *dev = \u0026mdiodev-\u003edev;\ndrivers/mfd/airoha-an8855.c:485:\tstruct an8855_core_priv *priv;\ndrivers/mfd/airoha-an8855.c-486-\tstruct regmap *regmap;\n--\ndrivers/mfd/airoha-an8855.c-499-\t/* Register virtual MDIO for each PHY */\ndrivers/mfd/airoha-an8855.c:500:\tnum_phys = an8855_mdio_register(dev, priv, phy_bus_infos);\ndrivers/mfd/airoha-an8855.c-501-\tif (num_phys \u003c 0)\n--\ndrivers/mfd/airoha-an8855.c-503-\ndrivers/mfd/airoha-an8855.c:504:\tregmap = devm_regmap_init(dev, NULL, priv, \u0026an8855_regmap_config);\ndrivers/mfd/airoha-an8855.c-505-\tif (IS_ERR(regmap))\n--\ndrivers/mfd/airoha-an8855.c-510-\tmutex_lock_nested(\u0026priv-\u003ebus-\u003emdio_lock, MDIO_MUTEX_NESTED);\ndrivers/mfd/airoha-an8855.c:511:\tret = an8855_mii_set_page(priv, priv-\u003eswitch_addr,\ndrivers/mfd/airoha-an8855.c-512-\t\t\t\t AN8855_PHY_PAGE_STANDARD);\n--\ndrivers/mfd/airoha-an8855.c-516-\ndrivers/mfd/airoha-an8855.c:517:\tret = an8855_read_switch_id(dev, regmap);\ndrivers/mfd/airoha-an8855.c-518-\tif (ret)\n--\ndrivers/mfd/airoha-an8855.c-534-\ndrivers/mfd/airoha-an8855.c:535:\treturn devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,\ndrivers/mfd/airoha-an8855.c:536:\t\t\t\t ARRAY_SIZE(an8855_cells), NULL, 0,\ndrivers/mfd/airoha-an8855.c-537-\t\t\t\t NULL);\n--\ndrivers/mfd/airoha-an8855.c-539-\ndrivers/mfd/airoha-an8855.c:540:static const struct of_device_id an8855_core_of_match[] = {\ndrivers/mfd/airoha-an8855.c:541:\t{ .compatible = \"airoha,an8855\" },\ndrivers/mfd/airoha-an8855.c-542-\t{ /* sentinel */ }\ndrivers/mfd/airoha-an8855.c-543-};\ndrivers/mfd/airoha-an8855.c:544:MODULE_DEVICE_TABLE(of, an8855_core_of_match);\ndrivers/mfd/airoha-an8855.c-545-\ndrivers/mfd/airoha-an8855.c:546:static struct mdio_driver an8855_core_driver = {\ndrivers/mfd/airoha-an8855.c:547:\t.probe = an8855_core_probe,\ndrivers/mfd/airoha-an8855.c-548-\t.mdiodrv.driver = {\ndrivers/mfd/airoha-an8855.c:549:\t\t.name = \"an8855\",\ndrivers/mfd/airoha-an8855.c:550:\t\t.of_match_table = an8855_core_of_match,\ndrivers/mfd/airoha-an8855.c-551-\t},\ndrivers/mfd/airoha-an8855.c-552-};\ndrivers/mfd/airoha-an8855.c:553:mdio_module_driver(an8855_core_driver);\ndrivers/mfd/airoha-an8855.c-554-\n--\ndrivers/net/dsa/Makefile-1-# SPDX-License-Identifier: GPL-2.0\ndrivers/net/dsa/Makefile:2:obj-$(CONFIG_NET_DSA_AN8855)\t+= an8855.o\ndrivers/net/dsa/Makefile-3-obj-$(CONFIG_NET_DSA_BCM_SF2)\t+= bcm-sf2.o\n--\ndrivers/net/dsa/Makefile=6=obj-$(CONFIG_NET_DSA_KS8995) \t+= ks8995.o\ndrivers/net/dsa/Makefile:7:obj-$(CONFIG_NET_DSA_MT7530)\t+= mt7530.o\ndrivers/net/dsa/Makefile:8:obj-$(CONFIG_NET_DSA_MT7530_LIB) += mt7530-lib.o\ndrivers/net/dsa/Makefile:9:obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o\ndrivers/net/dsa/Makefile:10:obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o\ndrivers/net/dsa/Makefile-11-obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o\n--\ndrivers/net/dsa/an8855.c-19-\ndrivers/net/dsa/an8855.c:20:#include \"an8855.h\"\ndrivers/net/dsa/an8855.c:21:#include \"mt7530-lib.h\"\ndrivers/net/dsa/an8855.c-22-\ndrivers/net/dsa/an8855.c:23:static const struct mt7530_reg_field an8855_fields[] = {\ndrivers/net/dsa/an8855.c-24-\t{ MT7530_BC_FFP, REG_FIELD(AN8855_BCF, 0, 7) },\n--\ndrivers/net/dsa/an8855.c-182-\ndrivers/net/dsa/an8855.c:183:static const struct mt7530_mib_desc an8855_mib[] = {\ndrivers/net/dsa/an8855.c-184-\tMIB_DESC(MT7530_MIB_TX_DROP, -1, \"TxDrop\"),\n--\ndrivers/net/dsa/an8855.c=206=static void\ndrivers/net/dsa/an8855.c:207:an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)\ndrivers/net/dsa/an8855.c-208-{\ndrivers/net/dsa/an8855.c-209-\tstruct dsa_port *dp = dsa_to_port(ds, port);\ndrivers/net/dsa/an8855.c:210:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-211-\tbool learning = false;\n--\ndrivers/net/dsa/an8855.c-213-\ndrivers/net/dsa/an8855.c:214:\tmt7530_lib_stp_state_set(\u0026priv-\u003elib_priv, port, state);\ndrivers/net/dsa/an8855.c-215-\n--\ndrivers/net/dsa/an8855.c-230-\ndrivers/net/dsa/an8855.c:231:static void an8855_port_fast_age(struct dsa_switch *ds, int port)\ndrivers/net/dsa/an8855.c-232-{\ndrivers/net/dsa/an8855.c:233:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-234-\tint ret;\n--\ndrivers/net/dsa/an8855.c-253-\t/* Flush Dynamic entry at port */\ndrivers/net/dsa/an8855.c:254:\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_FLUSH,\ndrivers/net/dsa/an8855.c-255-\t\t\t\t AN8855_FDB_MAT_MAC_TYPE_PORT, NULL);\n--\ndrivers/net/dsa/an8855.c-262-\ndrivers/net/dsa/an8855.c:263:static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port,\ndrivers/net/dsa/an8855.c-264-\t\t\t\t\tstruct switchdev_brport_flags flags,\n--\ndrivers/net/dsa/an8855.c-273-\ndrivers/net/dsa/an8855.c:274:static int an8855_port_bridge_flags(struct dsa_switch *ds, int port,\ndrivers/net/dsa/an8855.c-275-\t\t\t\t struct switchdev_brport_flags flags,\n--\ndrivers/net/dsa/an8855.c-277-{\ndrivers/net/dsa/an8855.c:278:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-279-\ndrivers/net/dsa/an8855.c:280:\treturn mt7530_lib_port_bridge_flags(\u0026priv-\u003elib_priv, port, flags,\ndrivers/net/dsa/an8855.c-281-\t\t\t\t\t extack);\n--\ndrivers/net/dsa/an8855.c-283-\ndrivers/net/dsa/an8855.c:284:static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)\ndrivers/net/dsa/an8855.c-285-{\ndrivers/net/dsa/an8855.c:286:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-287-\tu32 age_count, age_unit, val;\n--\ndrivers/net/dsa/an8855.c-305-\ndrivers/net/dsa/an8855.c:306:static int an8855_port_bridge_join(struct dsa_switch *ds, int port,\ndrivers/net/dsa/an8855.c-307-\t\t\t\t struct dsa_bridge bridge,\n--\ndrivers/net/dsa/an8855.c-310-{\ndrivers/net/dsa/an8855.c:311:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-312-\ndrivers/net/dsa/an8855.c:313:\treturn mt7530_lib_port_bridge_join(\u0026priv-\u003elib_priv, port, bridge,\ndrivers/net/dsa/an8855.c-314-\t\t\t\t\t tx_fwd_offload, extack);\n--\ndrivers/net/dsa/an8855.c-316-\ndrivers/net/dsa/an8855.c:317:static void an8855_port_bridge_leave(struct dsa_switch *ds, int port,\ndrivers/net/dsa/an8855.c-318-\t\t\t\t struct dsa_bridge bridge)\ndrivers/net/dsa/an8855.c-319-{\ndrivers/net/dsa/an8855.c:320:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-321-\ndrivers/net/dsa/an8855.c:322:\treturn mt7530_lib_port_bridge_leave(\u0026priv-\u003elib_priv, port, bridge);\ndrivers/net/dsa/an8855.c-323-}\ndrivers/net/dsa/an8855.c-324-\ndrivers/net/dsa/an8855.c:325:static int an8855_port_fdb_add(struct dsa_switch *ds, int port,\ndrivers/net/dsa/an8855.c-326-\t\t\t const unsigned char *addr, u16 vid,\n--\ndrivers/net/dsa/an8855.c-328-{\ndrivers/net/dsa/an8855.c:329:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-330-\ndrivers/net/dsa/an8855.c:331:\treturn mt7530_lib_port_fdb_add(\u0026priv-\u003elib_priv, port, addr, vid, db);\ndrivers/net/dsa/an8855.c-332-}\ndrivers/net/dsa/an8855.c-333-\ndrivers/net/dsa/an8855.c:334:static int an8855_port_fdb_del(struct dsa_switch *ds, int port,\ndrivers/net/dsa/an8855.c-335-\t\t\t const unsigned char *addr, u16 vid,\n--\ndrivers/net/dsa/an8855.c-337-{\ndrivers/net/dsa/an8855.c:338:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-339-\ndrivers/net/dsa/an8855.c:340:\treturn mt7530_lib_port_fdb_del(\u0026priv-\u003elib_priv, port, addr, vid, db);\ndrivers/net/dsa/an8855.c-341-}\ndrivers/net/dsa/an8855.c-342-\ndrivers/net/dsa/an8855.c:343:static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,\ndrivers/net/dsa/an8855.c-344-\t\t\t\tdsa_fdb_dump_cb_t *cb, void *data)\ndrivers/net/dsa/an8855.c-345-{\ndrivers/net/dsa/an8855.c:346:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-347-\tint banks, count = 0;\n--\ndrivers/net/dsa/an8855.c-358-\t\tgoto exit;\ndrivers/net/dsa/an8855.c:359:\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_START,\ndrivers/net/dsa/an8855.c-360-\t\t\t\t AN8855_FDB_MAT_MAC_PORT, \u0026rsp);\n--\ndrivers/net/dsa/an8855.c-371-\t\tfor (i = 0; i \u003c 4; i++) {\ndrivers/net/dsa/an8855.c:372:\t\t\tstruct mt7530_fdb _fdb = { };\ndrivers/net/dsa/an8855.c-373-\n--\ndrivers/net/dsa/an8855.c-386-\t\t\tusleep_range(1000, 1500);\ndrivers/net/dsa/an8855.c:387:\t\t\tmt7530_lib_fdb_read(\u0026priv-\u003elib_priv, \u0026_fdb);\ndrivers/net/dsa/an8855.c-388-\n--\ndrivers/net/dsa/an8855.c-398-\t\t/* Read next bank */\ndrivers/net/dsa/an8855.c:399:\t\tret = mt7530_lib_fdb_cmd(\u0026priv-\u003elib_priv, MT7530_FDB_NEXT,\ndrivers/net/dsa/an8855.c-400-\t\t\t\t\t AN8855_FDB_MAT_MAC_PORT, \u0026rsp);\n--\ndrivers/net/dsa/an8855.c-409-\ndrivers/net/dsa/an8855.c:410:static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port,\ndrivers/net/dsa/an8855.c-411-\t\t\t\t bool vlan_filtering,\n--\ndrivers/net/dsa/an8855.c-413-{\ndrivers/net/dsa/an8855.c:414:\tstruct an8855_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/an8855.c-415-\ndrivers/net/dsa/an8855.c:416:\treturn mt7530_lib_port_vlan_filtering(\u0026priv-\u003elib_priv, port,\ndrivers/net/dsa/an8855.c-417-\t\t\t\t\t vlan_filtering,\n\n"
} |
| 21/2 | 2026/09/15 16:38 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 164157 output: 31 thoughts: 106 Thoughts: **Investigating DSA Tagging Protocols** Okay, let's dive back into `net/dsa/tag_mtk.c`. I need to figure out if I can actually test `tag_mtk` or `tag_airoha` without having the physical hardware. I'm not sure if it's possible to emulate their behaviour or if I'm stuck needing physical devices. Next, I'll need to understand how these DSA tagging protocols are selected and bound within the kernel. I need to trace the mechanisms that determine which tag driver is associated with a given network device. How exactly does a net device end up with a specific `dsa_device_ops` (that is, the tag driver operations)? To get a better picture of the overall setup, I'm going to grep the `net/dsa/` directory for instances of both `dsa_tag_driver` and `dsa_device_ops`. This should hopefully give me some leads on how the binding process works. This should give me some insights to trace this through the system. |
| 22/2 | 2026/09/15 16:38 | tool | grepper |
0mArgs:{
"Expression": "dsa_device_ops",
"PathPrefix": "net/dsa/"
}Results: {
"Output": "net/dsa/conduit.c=328=static void dsa_conduit_set_promiscuity(struct net_device *dev, int inc)\nnet/dsa/conduit.c-329-{\nnet/dsa/conduit.c:330:\tconst struct dsa_device_ops *ops = dev-\u003edsa_ptr-\u003etag_ops;\nnet/dsa/conduit.c-331-\n--\nnet/dsa/conduit.c=350=static ssize_t tagging_store(struct device *d, struct device_attribute *attr,\n--\nnet/dsa/conduit.c-352-{\nnet/dsa/conduit.c:353:\tconst struct dsa_device_ops *new_tag_ops, *old_tag_ops;\nnet/dsa/conduit.c-354-\tconst char *end = strchrnul(buf, '\\n'), *name;\n--\nnet/dsa/conduit.c=419=int dsa_conduit_setup(struct net_device *dev, struct dsa_port *cpu_dp)\nnet/dsa/conduit.c-420-{\nnet/dsa/conduit.c:421:\tconst struct dsa_device_ops *tag_ops = cpu_dp-\u003etag_ops;\nnet/dsa/conduit.c-422-\tstruct dsa_switch *ds = cpu_dp-\u003eds;\n--\nnet/dsa/dsa.c=570=static int dsa_switch_setup_tag_protocol(struct dsa_switch *ds)\nnet/dsa/dsa.c-571-{\nnet/dsa/dsa.c:572:\tconst struct dsa_device_ops *tag_ops = ds-\u003edst-\u003etag_ops;\nnet/dsa/dsa.c-573-\tstruct dsa_switch_tree *dst = ds-\u003edst;\n--\nnet/dsa/dsa.c=614=static void dsa_switch_teardown_tag_protocol(struct dsa_switch *ds)\nnet/dsa/dsa.c-615-{\nnet/dsa/dsa.c:616:\tconst struct dsa_device_ops *tag_ops = ds-\u003edst-\u003etag_ops;\nnet/dsa/dsa.c-617-\n--\nnet/dsa/dsa.c=948=static int dsa_tree_bind_tag_proto(struct dsa_switch_tree *dst,\nnet/dsa/dsa.c:949:\t\t\t\t const struct dsa_device_ops *tag_ops)\nnet/dsa/dsa.c-950-{\nnet/dsa/dsa.c:951:\tconst struct dsa_device_ops *old_tag_ops = dst-\u003etag_ops;\nnet/dsa/dsa.c-952-\tstruct dsa_notifier_tag_proto_info info;\n--\nnet/dsa/dsa.c=983=int dsa_tree_change_tag_proto(struct dsa_switch_tree *dst,\nnet/dsa/dsa.c:984:\t\t\t const struct dsa_device_ops *tag_ops,\nnet/dsa/dsa.c:985:\t\t\t const struct dsa_device_ops *old_tag_ops)\nnet/dsa/dsa.c-986-{\n--\nnet/dsa/dsa.c=1155=static int dsa_port_parse_cpu(struct dsa_port *dp, struct net_device *conduit,\n--\nnet/dsa/dsa.c-1157-{\nnet/dsa/dsa.c:1158:\tconst struct dsa_device_ops *tag_ops = NULL;\nnet/dsa/dsa.c-1159-\tstruct dsa_switch *ds = dp-\u003eds;\n--\nnet/dsa/dsa.h=9=struct dsa_db;\nnet/dsa/dsa.h:10:struct dsa_device_ops;\nnet/dsa/dsa.h-11-struct dsa_lag;\n--\nnet/dsa/dsa.h=25=int dsa_tree_change_tag_proto(struct dsa_switch_tree *dst,\nnet/dsa/dsa.h:26:\t\t\t const struct dsa_device_ops *tag_ops,\nnet/dsa/dsa.h:27:\t\t\t const struct dsa_device_ops *old_tag_ops);\nnet/dsa/dsa.h-28-void dsa_tree_conduit_admin_state_change(struct dsa_switch_tree *dst,\n--\nnet/dsa/port.c=1567=void dsa_port_set_tag_protocol(struct dsa_port *cpu_dp,\nnet/dsa/port.c:1568:\t\t\t const struct dsa_device_ops *tag_ops)\nnet/dsa/port.c-1569-{\n--\nnet/dsa/port.h=19=void dsa_port_set_tag_protocol(struct dsa_port *cpu_dp,\nnet/dsa/port.h:20:\t\t\t const struct dsa_device_ops *tag_ops);\nnet/dsa/port.h-21-int dsa_port_set_state(struct dsa_port *dp, u8 state, bool do_fast_age);\n--\nnet/dsa/switch.c=873=static int dsa_switch_change_tag_proto(struct dsa_switch *ds,\n--\nnet/dsa/switch.c-875-{\nnet/dsa/switch.c:876:\tconst struct dsa_device_ops *tag_ops = info-\u003etag_ops;\nnet/dsa/switch.c-877-\tstruct dsa_port *dp, *cpu_dp;\n--\nnet/dsa/switch.c=918=dsa_switch_connect_tag_proto(struct dsa_switch *ds,\n--\nnet/dsa/switch.c-920-{\nnet/dsa/switch.c:921:\tconst struct dsa_device_ops *tag_ops = info-\u003etag_ops;\nnet/dsa/switch.c-922-\tint err;\n--\nnet/dsa/switch.c=947=dsa_switch_disconnect_tag_proto(struct dsa_switch *ds,\n--\nnet/dsa/switch.c-949-{\nnet/dsa/switch.c:950:\tconst struct dsa_device_ops *tag_ops = info-\u003etag_ops;\nnet/dsa/switch.c-951-\n--\nnet/dsa/switch.h=98=struct dsa_notifier_tag_proto_info {\nnet/dsa/switch.h:99:\tconst struct dsa_device_ops *tag_ops;\nnet/dsa/switch.h-100-};\n--\nnet/dsa/tag.c=168=EXPORT_SYMBOL_GPL(dsa_tag_drivers_unregister);\nnet/dsa/tag.c-169-\nnet/dsa/tag.c:170:const char *dsa_tag_protocol_to_str(const struct dsa_device_ops *ops)\nnet/dsa/tag.c-171-{\n--\nnet/dsa/tag.c-177- */\nnet/dsa/tag.c:178:const struct dsa_device_ops *dsa_tag_driver_get_by_name(const char *name)\nnet/dsa/tag.c-179-{\nnet/dsa/tag.c:180:\tconst struct dsa_device_ops *ops = ERR_PTR(-ENOPROTOOPT);\nnet/dsa/tag.c-181-\tstruct dsa_tag_driver *dsa_tag_driver;\n--\nnet/dsa/tag.c-186-\tlist_for_each_entry(dsa_tag_driver, \u0026dsa_tag_drivers_list, list) {\nnet/dsa/tag.c:187:\t\tconst struct dsa_device_ops *tmp = dsa_tag_driver-\u003eops;\nnet/dsa/tag.c-188-\n--\nnet/dsa/tag.c-202-\nnet/dsa/tag.c:203:const struct dsa_device_ops *dsa_tag_driver_get_by_id(int tag_protocol)\nnet/dsa/tag.c-204-{\nnet/dsa/tag.c-205-\tstruct dsa_tag_driver *dsa_tag_driver;\nnet/dsa/tag.c:206:\tconst struct dsa_device_ops *ops;\nnet/dsa/tag.c-207-\tbool found = false;\n--\nnet/dsa/tag.c-231-\nnet/dsa/tag.c:232:void dsa_tag_driver_put(const struct dsa_device_ops *ops)\nnet/dsa/tag.c-233-{\n--\nnet/dsa/tag.h=14=struct dsa_tag_driver {\nnet/dsa/tag.h:15:\tconst struct dsa_device_ops *ops;\nnet/dsa/tag.h-16-\tstruct list_head list;\n--\nnet/dsa/tag.h=20=extern struct packet_type dsa_pack_type;\nnet/dsa/tag.h-21-\nnet/dsa/tag.h:22:const struct dsa_device_ops *dsa_tag_driver_get_by_id(int tag_protocol);\nnet/dsa/tag.h:23:const struct dsa_device_ops *dsa_tag_driver_get_by_name(const char *name);\nnet/dsa/tag.h:24:void dsa_tag_driver_put(const struct dsa_device_ops *ops);\nnet/dsa/tag.h:25:const char *dsa_tag_protocol_to_str(const struct dsa_device_ops *ops);\nnet/dsa/tag.h-26-\nnet/dsa/tag.h:27:static inline int dsa_tag_protocol_overhead(const struct dsa_device_ops *ops)\nnet/dsa/tag.h-28-{\n--\nnet/dsa/tag_ar9331.c=48=static struct sk_buff *ar9331_tag_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_ar9331.c-89-\nnet/dsa/tag_ar9331.c:90:static const struct dsa_device_ops ar9331_netdev_ops = {\nnet/dsa/tag_ar9331.c-91-\t.name\t= AR9331_NAME,\n--\nnet/dsa/tag_brcm.c=203=static struct sk_buff *brcm_tag_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_brcm.c-216-\nnet/dsa/tag_brcm.c:217:static const struct dsa_device_ops brcm_netdev_ops = {\nnet/dsa/tag_brcm.c-218-\t.name\t= BRCM_NAME,\n--\nnet/dsa/tag_brcm.c=276=static struct sk_buff *brcm_leg_tag_xmit(struct sk_buff *skb,\n--\nnet/dsa/tag_brcm.c-310-\nnet/dsa/tag_brcm.c:311:static const struct dsa_device_ops brcm_legacy_netdev_ops = {\nnet/dsa/tag_brcm.c-312-\t.name = BRCM_LEGACY_NAME,\n--\nnet/dsa/tag_brcm.c=324=static struct sk_buff *brcm_leg_fcs_tag_xmit(struct sk_buff *skb,\n--\nnet/dsa/tag_brcm.c-369-\nnet/dsa/tag_brcm.c:370:static const struct dsa_device_ops brcm_legacy_fcs_netdev_ops = {\nnet/dsa/tag_brcm.c-371-\t.name = BRCM_LEGACY_FCS_NAME,\n--\nnet/dsa/tag_brcm.c=391=static struct sk_buff *brcm_tag_rcv_prepend(struct sk_buff *skb,\n--\nnet/dsa/tag_brcm.c-397-\nnet/dsa/tag_brcm.c:398:static const struct dsa_device_ops brcm_prepend_netdev_ops = {\nnet/dsa/tag_brcm.c-399-\t.name\t= BRCM_PREPEND_NAME,\n--\nnet/dsa/tag_dsa.c=341=static struct sk_buff *dsa_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_dsa.c-350-\nnet/dsa/tag_dsa.c:351:static const struct dsa_device_ops dsa_netdev_ops = {\nnet/dsa/tag_dsa.c-352-\t.name\t = DSA_NAME,\n--\nnet/dsa/tag_dsa.c=383=static struct sk_buff *edsa_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_dsa.c-394-\nnet/dsa/tag_dsa.c:395:static const struct dsa_device_ops edsa_netdev_ops = {\nnet/dsa/tag_dsa.c-396-\t.name\t = EDSA_NAME,\n--\nnet/dsa/tag_gswip.c=77=static struct sk_buff *gswip_tag_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_gswip.c-103-\nnet/dsa/tag_gswip.c:104:static const struct dsa_device_ops gswip_netdev_ops = {\nnet/dsa/tag_gswip.c-105-\t.name = GSWIP_NAME,\n--\nnet/dsa/tag_hellcreek.c=42=static struct sk_buff *hellcreek_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_hellcreek.c-65-\nnet/dsa/tag_hellcreek.c:66:static const struct dsa_device_ops hellcreek_netdev_ops = {\nnet/dsa/tag_hellcreek.c-67-\t.name\t = HELLCREEK_NAME,\n--\nnet/dsa/tag_ksz.c=285=static struct sk_buff *ksz9477_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_ksz.c-308-\nnet/dsa/tag_ksz.c:309:static const struct dsa_device_ops ksz9477_netdev_ops = {\nnet/dsa/tag_ksz.c-310-\t.name\t= KSZ9477_NAME,\n--\nnet/dsa/tag_ksz.c=346=static struct sk_buff *ksz8795_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_ksz.c-360-\nnet/dsa/tag_ksz.c:361:static const struct dsa_device_ops ksz8795_netdev_ops = {\nnet/dsa/tag_ksz.c-362-\t.name\t= KSZ8795_NAME,\n--\nnet/dsa/tag_ksz.c=376=static struct sk_buff *ksz9893_xmit(struct sk_buff *skb,\n--\nnet/dsa/tag_ksz.c-386-\nnet/dsa/tag_ksz.c:387:static const struct dsa_device_ops ksz9893_netdev_ops = {\nnet/dsa/tag_ksz.c-388-\t.name\t= KSZ9893_NAME,\n--\nnet/dsa/tag_ksz.c=414=static struct sk_buff *ksz8463_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_ksz.c-450-\nnet/dsa/tag_ksz.c:451:static const struct dsa_device_ops ksz8463_netdev_ops = {\nnet/dsa/tag_ksz.c-452-\t.name\t= KSZ8463_NAME,\n--\nnet/dsa/tag_ksz.c=489=static struct sk_buff *lan937x_xmit(struct sk_buff *skb,\n--\nnet/dsa/tag_ksz.c-521-\nnet/dsa/tag_ksz.c:522:static const struct dsa_device_ops lan937x_netdev_ops = {\nnet/dsa/tag_ksz.c-523-\t.name\t= LAN937X_NAME,\n--\nnet/dsa/tag_lan9303.c=80=static struct sk_buff *lan9303_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_lan9303.c-115-\nnet/dsa/tag_lan9303.c:116:static const struct dsa_device_ops lan9303_netdev_ops = {\nnet/dsa/tag_lan9303.c-117-\t.name = LAN9303_NAME,\n--\nnet/dsa/tag_mt7628.c=56=static struct sk_buff *mt7628_tag_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_mt7628.c-80-\nnet/dsa/tag_mt7628.c:81:static const struct dsa_device_ops mt7628_tag_ops = {\nnet/dsa/tag_mt7628.c-82-\t.name = MT7628_TAG_NAME,\n--\nnet/dsa/tag_mtk.c=73=static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_mtk.c-106-#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)\nnet/dsa/tag_mtk.c:107:static const struct dsa_device_ops mtk_netdev_ops = {\nnet/dsa/tag_mtk.c-108-\t.name\t\t= MTK_NAME,\n--\nnet/dsa/tag_mtk.c=116=MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);\n--\nnet/dsa/tag_mtk.c-119-#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)\nnet/dsa/tag_mtk.c:120:static const struct dsa_device_ops airoha_netdev_ops = {\nnet/dsa/tag_mtk.c-121-\t.name\t\t= AIROHA_NAME,\n--\nnet/dsa/tag_mxl-gsw1xx.c=68=static struct sk_buff *gsw1xx_tag_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_mxl-gsw1xx.c-107-\nnet/dsa/tag_mxl-gsw1xx.c:108:static const struct dsa_device_ops gsw1xx_netdev_ops = {\nnet/dsa/tag_mxl-gsw1xx.c-109-\t.name\t\t\t= GSW1XX_TAG_NAME,\n--\nnet/dsa/tag_mxl862xx.c=59=static struct sk_buff *mxl862_tag_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_mxl862xx.c-103-\nnet/dsa/tag_mxl862xx.c:104:static const struct dsa_device_ops mxl862_netdev_ops = {\nnet/dsa/tag_mxl862xx.c-105-\t.name = MXL862_NAME,\n--\nnet/dsa/tag_netc.c=185=static void netc_flow_dissect(const struct sk_buff *skb, __be16 *proto,\n--\nnet/dsa/tag_netc.c-202-\nnet/dsa/tag_netc.c:203:static const struct dsa_device_ops netc_netdev_ops = {\nnet/dsa/tag_netc.c-204-\t.name\t\t\t= NETC_NAME,\n--\nnet/dsa/tag_none.c=15=static struct sk_buff *dsa_user_notag_xmit(struct sk_buff *skb,\n--\nnet/dsa/tag_none.c-21-\nnet/dsa/tag_none.c:22:static const struct dsa_device_ops none_ops = {\nnet/dsa/tag_none.c-23-\t.name\t= NONE_NAME,\n--\nnet/dsa/tag_ocelot.c=68=static struct sk_buff *ocelot_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_ocelot.c-155-\nnet/dsa/tag_ocelot.c:156:static const struct dsa_device_ops ocelot_netdev_ops = {\nnet/dsa/tag_ocelot.c-157-\t.name\t\t\t= OCELOT_NAME,\n--\nnet/dsa/tag_ocelot.c=166=MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_OCELOT, OCELOT_NAME);\nnet/dsa/tag_ocelot.c-167-\nnet/dsa/tag_ocelot.c:168:static const struct dsa_device_ops seville_netdev_ops = {\nnet/dsa/tag_ocelot.c-169-\t.name\t\t\t= SEVILLE_NAME,\n--\nnet/dsa/tag_ocelot_8021q.c=110=static int ocelot_connect(struct dsa_switch *ds)\n--\nnet/dsa/tag_ocelot_8021q.c-130-\nnet/dsa/tag_ocelot_8021q.c:131:static const struct dsa_device_ops ocelot_8021q_netdev_ops = {\nnet/dsa/tag_ocelot_8021q.c-132-\t.name\t\t\t= OCELOT_8021Q_NAME,\n--\nnet/dsa/tag_qca.c=112=static void qca_tag_disconnect(struct dsa_switch *ds)\n--\nnet/dsa/tag_qca.c-117-\nnet/dsa/tag_qca.c:118:static const struct dsa_device_ops qca_netdev_ops = {\nnet/dsa/tag_qca.c-119-\t.name\t= QCA_NAME,\n--\nnet/dsa/tag_rtl4_a.c=68=static struct sk_buff *rtl4a_tag_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_rtl4_a.c-118-\nnet/dsa/tag_rtl4_a.c:119:static const struct dsa_device_ops rtl4a_netdev_ops = {\nnet/dsa/tag_rtl4_a.c-120-\t.name\t= RTL4_A_NAME,\n--\nnet/dsa/tag_rtl8_4.c=224=static struct sk_buff *rtl8_4t_tag_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_rtl8_4.c-245-/* Ethertype version */\nnet/dsa/tag_rtl8_4.c:246:static const struct dsa_device_ops rtl8_4_netdev_ops = {\nnet/dsa/tag_rtl8_4.c-247-\t.name = \"rtl8_4\",\n--\nnet/dsa/tag_rtl8_4.c=256=MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_RTL8_4, RTL8_4_NAME);\n--\nnet/dsa/tag_rtl8_4.c-258-/* Tail version */\nnet/dsa/tag_rtl8_4.c:259:static const struct dsa_device_ops rtl8_4t_netdev_ops = {\nnet/dsa/tag_rtl8_4.c-260-\t.name = \"rtl8_4t\",\n--\nnet/dsa/tag_rzn1_a5psw.c=71=static struct sk_buff *a5psw_tag_rcv(struct sk_buff *skb,\n--\nnet/dsa/tag_rzn1_a5psw.c-107-\nnet/dsa/tag_rzn1_a5psw.c:108:static const struct dsa_device_ops a5psw_netdev_ops = {\nnet/dsa/tag_rzn1_a5psw.c-109-\t.name\t= A5PSW_NAME,\n--\nnet/dsa/tag_sja1105.c=710=static int sja1105_connect(struct dsa_switch *ds)\n--\nnet/dsa/tag_sja1105.c-735-\nnet/dsa/tag_sja1105.c:736:static const struct dsa_device_ops sja1105_netdev_ops = {\nnet/dsa/tag_sja1105.c-737-\t.name = SJA1105_NAME,\n--\nnet/dsa/tag_sja1105.c=749=MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_SJA1105, SJA1105_NAME);\nnet/dsa/tag_sja1105.c-750-\nnet/dsa/tag_sja1105.c:751:static const struct dsa_device_ops sja1110_netdev_ops = {\nnet/dsa/tag_sja1105.c-752-\t.name = SJA1110_NAME,\n--\nnet/dsa/tag_trailer.c=28=static struct sk_buff *trailer_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_trailer.c-60-\nnet/dsa/tag_trailer.c:61:static const struct dsa_device_ops trailer_netdev_ops = {\nnet/dsa/tag_trailer.c-62-\t.name\t= TRAILER_NAME,\n--\nnet/dsa/tag_vsc73xx_8021q.c=36=vsc73xx_rcv(struct sk_buff *skb, struct net_device *netdev)\n--\nnet/dsa/tag_vsc73xx_8021q.c-55-\nnet/dsa/tag_vsc73xx_8021q.c:56:static const struct dsa_device_ops vsc73xx_8021q_netdev_ops = {\nnet/dsa/tag_vsc73xx_8021q.c-57-\t.name\t\t\t= VSC73XX_8021Q_NAME,\n--\nnet/dsa/tag_xrs700x.c=24=static struct sk_buff *xrs700x_rcv(struct sk_buff *skb, struct net_device *dev)\n--\nnet/dsa/tag_xrs700x.c-54-\nnet/dsa/tag_xrs700x.c:55:static const struct dsa_device_ops xrs700x_netdev_ops = {\nnet/dsa/tag_xrs700x.c-56-\t.name\t= XRS700X_NAME,\n--\nnet/dsa/tag_yt921x.c=84=yt921x_tag_rcv(struct sk_buff *skb, struct net_device *netdev)\n--\nnet/dsa/tag_yt921x.c-160-\nnet/dsa/tag_yt921x.c:161:static const struct dsa_device_ops yt921x_netdev_ops = {\nnet/dsa/tag_yt921x.c-162-\t.name\t= YT921X_TAG_NAME,\n"
} |
| 23/2 | 2026/09/15 16:38 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 172059 output: 37 thoughts: 69 Thoughts: Here's my summary, as if I were thinking it: **Diving into `conduit.c` for Tagging Implementation** Okay, time to get my hands dirty with this tagging stuff. Let's see... the code's pointing me to `net/dsa/conduit.c:350`. Right, let's zoom in on that section and start reading. From lines 345 to 410, that should give me a good chunk of context around that `tagging_store` function. I need to understand how these tags are being handled and stored within the conduit context. I'm especially interested in how this interacts with the device attributes. I want to see if they're doing something clever, or are just following a basic model. Let's see what's happening. |
| 24/2 | 2026/09/15 16:38 | tool | read-file |
0mArgs:{
"File": "net/dsa/conduit.c",
"FirstLine": 345,
"LineCount": 65
}Results: {
"Contents": " 345:\t\n 346:\t\treturn sysfs_emit(buf, \"%s\\n\",\n 347:\t\t\t dsa_tag_protocol_to_str(cpu_dp-\u003etag_ops));\n 348:\t}\n 349:\t\n 350:\tstatic ssize_t tagging_store(struct device *d, struct device_attribute *attr,\n 351:\t\t\t\t const char *buf, size_t count)\n 352:\t{\n 353:\t\tconst struct dsa_device_ops *new_tag_ops, *old_tag_ops;\n 354:\t\tconst char *end = strchrnul(buf, '\\n'), *name;\n 355:\t\tstruct net_device *dev = to_net_dev(d);\n 356:\t\tstruct dsa_port *cpu_dp = dev-\u003edsa_ptr;\n 357:\t\tsize_t len = end - buf;\n 358:\t\tint err;\n 359:\t\n 360:\t\t/* Empty string passed */\n 361:\t\tif (!len)\n 362:\t\t\treturn -ENOPROTOOPT;\n 363:\t\n 364:\t\tname = kstrndup(buf, len, GFP_KERNEL);\n 365:\t\tif (!name)\n 366:\t\t\treturn -ENOMEM;\n 367:\t\n 368:\t\told_tag_ops = cpu_dp-\u003etag_ops;\n 369:\t\tnew_tag_ops = dsa_tag_driver_get_by_name(name);\n 370:\t\tkfree(name);\n 371:\t\t/* Bad tagger name? */\n 372:\t\tif (IS_ERR(new_tag_ops))\n 373:\t\t\treturn PTR_ERR(new_tag_ops);\n 374:\t\n 375:\t\tif (new_tag_ops == old_tag_ops)\n 376:\t\t\t/* Drop the temporarily held duplicate reference, since\n 377:\t\t\t * the DSA switch tree uses this tagger.\n 378:\t\t\t */\n 379:\t\t\tgoto out;\n 380:\t\n 381:\t\terr = dsa_tree_change_tag_proto(cpu_dp-\u003eds-\u003edst, new_tag_ops,\n 382:\t\t\t\t\t\told_tag_ops);\n 383:\t\tif (err) {\n 384:\t\t\t/* On failure the old tagger is restored, so we don't need the\n 385:\t\t\t * driver for the new one.\n 386:\t\t\t */\n 387:\t\t\tdsa_tag_driver_put(new_tag_ops);\n 388:\t\t\treturn err;\n 389:\t\t}\n 390:\t\n 391:\t\t/* On success we no longer need the module for the old tagging protocol\n 392:\t\t */\n 393:\tout:\n 394:\t\tdsa_tag_driver_put(old_tag_ops);\n 395:\t\treturn count;\n 396:\t}\n 397:\tstatic DEVICE_ATTR_RW(tagging);\n 398:\t\n 399:\tstatic struct attribute *dsa_user_attrs[] = {\n 400:\t\t\u0026dev_attr_tagging.attr,\n 401:\t\tNULL\n 402:\t};\n 403:\t\n 404:\tstatic const struct attribute_group dsa_group = {\n 405:\t\t.name\t= \"dsa\",\n 406:\t\t.attrs\t= dsa_user_attrs,\n 407:\t};\n 408:\t\n 409:\tstatic void dsa_conduit_reset_mtu(struct net_device *dev)\n"
} |
| 25/2 | 2026/09/15 16:38 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 173312 output: 37 thoughts: 65 Thoughts: **Analyzing the DSA Tagging Protocol** Okay, let's dive in. I'm looking at `dsa_tree_change_tag_proto` – interesting. The key question is: can the `dsa_loop` mechanism be used to dynamically switch the tagging protocol to either `airoha` or `mtk`? That would be powerful, if feasible. To answer that, I need the definitive reference. Time to crack open the `net/dsa/dsa.c` file. This is where the core logic of the DSA (Distributed Switch Architecture) module lives, so I'll find the implementation of `dsa_tree_change_tag_proto` in there. I'm expecting to find the answer buried somewhere in the implementation details. Let's see what the code reveals. |
| 26/2 | 2026/09/15 16:38 | tool | read-file |
0mArgs:{
"File": "net/dsa/dsa.c",
"FirstLine": 980,
"LineCount": 40
}Results: {
"Contents": " 980:\t * is that all DSA switches within a tree share the same tagger, otherwise\n 981:\t * they would have formed disjoint trees (different \"dsa,member\" values).\n 982:\t */\n 983:\tint dsa_tree_change_tag_proto(struct dsa_switch_tree *dst,\n 984:\t\t\t\t const struct dsa_device_ops *tag_ops,\n 985:\t\t\t\t const struct dsa_device_ops *old_tag_ops)\n 986:\t{\n 987:\t\tstruct dsa_notifier_tag_proto_info info;\n 988:\t\tstruct dsa_port *dp;\n 989:\t\tint err = -EBUSY;\n 990:\t\n 991:\t\tif (!rtnl_trylock())\n 992:\t\t\treturn restart_syscall();\n 993:\t\n 994:\t\t/* At the moment we don't allow changing the tag protocol under\n 995:\t\t * traffic. The rtnl_mutex also happens to serialize concurrent\n 996:\t\t * attempts to change the tagging protocol. If we ever lift the IFF_UP\n 997:\t\t * restriction, there needs to be another mutex which serializes this.\n 998:\t\t */\n 999:\t\tdsa_tree_for_each_user_port(dp, dst) {\n1000:\t\t\tif (dsa_port_to_conduit(dp)-\u003eflags \u0026 IFF_UP)\n1001:\t\t\t\tgoto out_unlock;\n1002:\t\n1003:\t\t\tif (dp-\u003euser-\u003eflags \u0026 IFF_UP)\n1004:\t\t\t\tgoto out_unlock;\n1005:\t\t}\n1006:\t\n1007:\t\t/* Notify the tag protocol change */\n1008:\t\tinfo.tag_ops = tag_ops;\n1009:\t\terr = dsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO, \u0026info);\n1010:\t\tif (err)\n1011:\t\t\tgoto out_unwind_tagger;\n1012:\t\n1013:\t\terr = dsa_tree_bind_tag_proto(dst, tag_ops);\n1014:\t\tif (err)\n1015:\t\t\tgoto out_unwind_tagger;\n1016:\t\n1017:\t\trtnl_unlock();\n1018:\t\n1019:\t\treturn 0;\n"
} |
| 27/2 | 2026/09/15 16:38 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 174224 output: 33 thoughts: 44 Thoughts: Here's my analysis of what I'm thinking, rendered in the first person, as requested: **Deconstructing `dsa_tree_notify` and `DSA_NOTIFIER_TAG_PROTO`** Okay, so I'm looking at this line: `dsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO, &info)`. My immediate thought is, "Let's figure out *exactly* what this `dsa_tree_notify` function is doing, especially when it's called with `DSA_NOTIFIER_TAG_PROTO`." Given the context, I'm assuming `dsa_tree_notify` is likely related to some sort of Data Structure Algorithm (DSA) tree and is likely sending a notification. The `dst` argument is probably the target or destination, and `&info` is likely a pointer to some relevant information. But `DSA_NOTIFIER_TAG_PROTO` – that's the key. I need to understand what that tag signifies. It's almost certainly an enum or a macro, so the next step is crystal clear: I need to quickly search the code base (or documentation, if available) for the definition of `DSA_NOTIFIER_TAG_PROTO`. That should give me the crucial context I need to fully grasp the purpose and impact of this function call. I expect it'll relate to some network protocol-specific event or change within the DSA tree structure. |
| 28/2 | 2026/09/15 16:38 | tool | grepper |
0mArgs:{
"Expression": "DSA_NOTIFIER_TAG_PROTO",
"PathPrefix": "net/dsa/"
}Results: {
"Output": "net/dsa/dsa.c=948=static int dsa_tree_bind_tag_proto(struct dsa_switch_tree *dst,\n--\nnet/dsa/dsa.c-960-\tinfo.tag_ops = tag_ops;\nnet/dsa/dsa.c:961:\terr = dsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO_CONNECT, \u0026info);\nnet/dsa/dsa.c-962-\tif (err \u0026\u0026 err != -EOPNOTSUPP)\n--\nnet/dsa/dsa.c-966-\tinfo.tag_ops = old_tag_ops;\nnet/dsa/dsa.c:967:\tdsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO_DISCONNECT, \u0026info);\nnet/dsa/dsa.c-968-\n--\nnet/dsa/dsa.c-972-\tinfo.tag_ops = tag_ops;\nnet/dsa/dsa.c:973:\tdsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO_DISCONNECT, \u0026info);\nnet/dsa/dsa.c-974-\tdst-\u003etag_ops = old_tag_ops;\n--\nnet/dsa/dsa.c=983=int dsa_tree_change_tag_proto(struct dsa_switch_tree *dst,\n--\nnet/dsa/dsa.c-1008-\tinfo.tag_ops = tag_ops;\nnet/dsa/dsa.c:1009:\terr = dsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO, \u0026info);\nnet/dsa/dsa.c-1010-\tif (err)\n--\nnet/dsa/dsa.c-1022-\tinfo.tag_ops = old_tag_ops;\nnet/dsa/dsa.c:1023:\tdsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO, \u0026info);\nnet/dsa/dsa.c-1024-out_unlock:\n--\nnet/dsa/switch.c=974=static int dsa_switch_event(struct notifier_block *nb,\n--\nnet/dsa/switch.c-1043-\t\tbreak;\nnet/dsa/switch.c:1044:\tcase DSA_NOTIFIER_TAG_PROTO:\nnet/dsa/switch.c-1045-\t\terr = dsa_switch_change_tag_proto(ds, info);\nnet/dsa/switch.c-1046-\t\tbreak;\nnet/dsa/switch.c:1047:\tcase DSA_NOTIFIER_TAG_PROTO_CONNECT:\nnet/dsa/switch.c-1048-\t\terr = dsa_switch_connect_tag_proto(ds, info);\nnet/dsa/switch.c-1049-\t\tbreak;\nnet/dsa/switch.c:1050:\tcase DSA_NOTIFIER_TAG_PROTO_DISCONNECT:\nnet/dsa/switch.c-1051-\t\terr = dsa_switch_disconnect_tag_proto(ds, info);\n--\nnet/dsa/switch.h=10=enum {\n--\nnet/dsa/switch.h-31-\tDSA_NOTIFIER_MTU,\nnet/dsa/switch.h:32:\tDSA_NOTIFIER_TAG_PROTO,\nnet/dsa/switch.h:33:\tDSA_NOTIFIER_TAG_PROTO_CONNECT,\nnet/dsa/switch.h:34:\tDSA_NOTIFIER_TAG_PROTO_DISCONNECT,\nnet/dsa/switch.h-35-\tDSA_NOTIFIER_TAG_8021Q_VLAN_ADD,\n--\nnet/dsa/switch.h=92=struct dsa_notifier_mtu_info {\n--\nnet/dsa/switch.h-96-\nnet/dsa/switch.h:97:/* DSA_NOTIFIER_TAG_PROTO_* */\nnet/dsa/switch.h-98-struct dsa_notifier_tag_proto_info {\n"
} |
| 29/2 | 2026/09/15 16:38 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 175662 output: 36 thoughts: 19 Thoughts: Here's a summary of my thought process, as if I were analyzing that function: **Analyzing `dsa_switch_change_tag_proto`** Okay, let's dive into this `dsa_switch_change_tag_proto` function. My initial thought is to figure out its purpose – what's the core functionality it provides? The naming convention suggests it has something to do with a Digital Signal Analyzer (DSA), potentially a switch, and likely involves changing or manipulating a "tag" or label associated with a protocol. This could mean altering the protocol itself, or merely metadata or configuration related to it. I'll need to look at the surrounding code, the function's arguments, and, if available, any documentation or comments, to get a clear picture. I'm already formulating questions: Is this a critical path function? What are the implications of a change? What potential side effects could arise? My expert eye will be scanning for potential performance bottlenecks or subtle flaws in the logic. Time to get to work! |
| 30/2 | 2026/09/15 16:38 | tool | read-file |
0mArgs:{
"File": "net/dsa/switch.c",
"FirstLine": 870,
"LineCount": 45
}Results: {
"Contents": " 870:\t\treturn 0;\n 871:\t}\n 872:\t\n 873:\tstatic int dsa_switch_change_tag_proto(struct dsa_switch *ds,\n 874:\t\t\t\t\t struct dsa_notifier_tag_proto_info *info)\n 875:\t{\n 876:\t\tconst struct dsa_device_ops *tag_ops = info-\u003etag_ops;\n 877:\t\tstruct dsa_port *dp, *cpu_dp;\n 878:\t\tint err;\n 879:\t\n 880:\t\tif (!ds-\u003eops-\u003echange_tag_protocol)\n 881:\t\t\treturn -EOPNOTSUPP;\n 882:\t\n 883:\t\tASSERT_RTNL();\n 884:\t\n 885:\t\terr = ds-\u003eops-\u003echange_tag_protocol(ds, tag_ops-\u003eproto);\n 886:\t\tif (err)\n 887:\t\t\treturn err;\n 888:\t\n 889:\t\tdsa_switch_for_each_cpu_port(cpu_dp, ds)\n 890:\t\t\tdsa_port_set_tag_protocol(cpu_dp, tag_ops);\n 891:\t\n 892:\t\t/* Now that changing the tag protocol can no longer fail, let's update\n 893:\t\t * the remaining bits which are \"duplicated for faster access\", and the\n 894:\t\t * bits that depend on the tagger, such as the MTU.\n 895:\t\t */\n 896:\t\tdsa_switch_for_each_user_port(dp, ds) {\n 897:\t\t\tstruct net_device *user = dp-\u003euser;\n 898:\t\n 899:\t\t\tdsa_user_setup_tagger(user);\n 900:\t\n 901:\t\t\t/* rtnl_mutex is held in dsa_tree_change_tag_proto */\n 902:\t\t\tdsa_user_change_mtu(user, user-\u003emtu);\n 903:\t\t}\n 904:\t\n 905:\t\treturn 0;\n 906:\t}\n 907:\t\n 908:\t/* We use the same cross-chip notifiers to inform both the tagger side, as well\n 909:\t * as the switch side, of connection and disconnection events.\n 910:\t * Since ds-\u003etagger_data is owned by the tagger, it isn't a hard error if the\n 911:\t * switch side doesn't support connecting to this tagger, and therefore, the\n 912:\t * fact that we don't disconnect the tagger side doesn't constitute a memory\n 913:\t * leak: the tagger will still operate with persistent per-switch memory, just\n 914:\t * with the switch side unconnected to it. What does constitute a hard error is\n"
} |
| 31/2 | 2026/09/15 16:38 | llm | patch-evaluator |
1mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 176682 output: 41 thoughts: 110 Thoughts: **Checking the `change_tag_protocol` Implementation** Okay, so I'm looking at this code and the first thing that jumps out at me is `if (!ds->ops->change_tag_protocol) return -EOPNOTSUPP;`. This screams "check for implementation." Essentially, it's saying "if the `change_tag_protocol` operation isn't supported, bail out with an error." That's standard practice, of course. But this gets me thinking: does `dsa_loop` *actually* provide a way to change the tag protocol? My next move is clear. I need to dive into the `dsa_loop_driver` and see if `change_tag_protocol` is defined there. I'll focus on lines 334 to 350. Actually, to get a better overview I will read lines 325-360 in `drivers/net/dsa/dsa_loop.c`. That should give me the context I need to confirm whether or not this function is available and, if so, how it works within this context. |
| 32/2 | 2026/09/15 16:39 | tool | read-file |
0mArgs:{
"File": "drivers/net/dsa/dsa_loop.c",
"FirstLine": 325,
"LineCount": 35
}Results: {
"Contents": " 325:\t\n 326:\tstatic void dsa_loop_phylink_get_caps(struct dsa_switch *dsa, int port,\n 327:\t\t\t\t\t struct phylink_config *config)\n 328:\t{\n 329:\t\tbitmap_fill(config-\u003esupported_interfaces, PHY_INTERFACE_MODE_MAX);\n 330:\t\t__clear_bit(PHY_INTERFACE_MODE_NA, config-\u003esupported_interfaces);\n 331:\t\tconfig-\u003emac_capabilities = ~0;\n 332:\t}\n 333:\t\n 334:\tstatic const struct dsa_switch_ops dsa_loop_driver = {\n 335:\t\t.get_tag_protocol\t= dsa_loop_get_protocol,\n 336:\t\t.setup\t\t\t= dsa_loop_setup,\n 337:\t\t.teardown\t\t= dsa_loop_teardown,\n 338:\t\t.get_strings\t\t= dsa_loop_get_strings,\n 339:\t\t.get_ethtool_stats\t= dsa_loop_get_ethtool_stats,\n 340:\t\t.get_sset_count\t\t= dsa_loop_get_sset_count,\n 341:\t\t.get_ethtool_phy_stats\t= dsa_loop_get_ethtool_stats,\n 342:\t\t.phy_read\t\t= dsa_loop_phy_read,\n 343:\t\t.phy_write\t\t= dsa_loop_phy_write,\n 344:\t\t.port_bridge_join\t= dsa_loop_port_bridge_join,\n 345:\t\t.port_bridge_leave\t= dsa_loop_port_bridge_leave,\n 346:\t\t.port_stp_state_set\t= dsa_loop_port_stp_state_set,\n 347:\t\t.port_vlan_filtering\t= dsa_loop_port_vlan_filtering,\n 348:\t\t.port_vlan_add\t\t= dsa_loop_port_vlan_add,\n 349:\t\t.port_vlan_del\t\t= dsa_loop_port_vlan_del,\n 350:\t\t.port_change_mtu\t= dsa_loop_port_change_mtu,\n 351:\t\t.port_max_mtu\t\t= dsa_loop_port_max_mtu,\n 352:\t\t.phylink_get_caps\t= dsa_loop_phylink_get_caps,\n 353:\t};\n 354:\t\n 355:\tstatic int dsa_loop_drv_probe(struct mdio_device *mdiodev)\n 356:\t{\n 357:\t\tstruct dsa_loop_pdata *pdata = mdiodev-\u003edev.platform_data;\n 358:\t\tstruct dsa_loop_priv *ps;\n 359:\t\tstruct dsa_switch *ds;\n"
} |
| 33/2 | 2026/09/15 16:39 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 177839 output: 38 thoughts: 289 Thoughts: **My Analysis of the DSA Tag Protocol Implementation** Okay, so `dsa_loop` *definitely* doesn't handle the `change_tag_protocol` functionality. That's a key point. Now, the question is, which drivers *do* implement it? I need to refresh my memory... right, let's see what `grep` turned up before. Ah, yes: * `felix_change_tag_protocol` in `drivers/net/dsa/ocelot/felix.c` * `mv88e6xxx_change_tag_protocol` in `drivers/net/dsa/mv88e6xxx/chip.c` * `rtl8365mb_change_tag_protocol` in `drivers/net/dsa/realtek/rtl8365mb_main.c` Right. None of those are related to mt7530 or an8855, and they all seem to require actual physical hardware. And a quick check confirms it, neither mt7530 or an8855 implement `change_tag_protocol`. So, what are `tag_mtk` and `tag_airoha` even *used* for? Oh, right, just MT7530 / MT7531 / MT7988 / AN8855, and only those chips. Okay, I see. Hang on... what about `tag_mtk.c`? Did `mtk_tag_xmit` or `mtk_tag_rcv` change? Probably, given the focus on those specific chips. I need to read that file from top to bottom to refresh my understanding and ensure that those functions are doing what I expect. Let's dig in. |
| 34/2 | 2026/09/15 16:40 | tool | read-file |
0mArgs:{
"File": "net/dsa/tag_mtk.c",
"FirstLine": 1,
"LineCount": 100
}Results: {
"Contents": " 1:\t// SPDX-License-Identifier: GPL-2.0\n 2:\t/*\n 3:\t * Mediatek DSA Tag support\n 4:\t * Copyright (C) 2017 Landen Chao \u003clanden.chao@mediatek.com\u003e\n 5:\t *\t\t Sean Wang \u003csean.wang@mediatek.com\u003e\n 6:\t */\n 7:\t\n 8:\t#include \u003clinux/etherdevice.h\u003e\n 9:\t#include \u003clinux/if_vlan.h\u003e\n 10:\t\n 11:\t#include \"tag.h\"\n 12:\t\n 13:\t#define MTK_NAME\t\t\"mtk\"\n 14:\t#define AIROHA_NAME\t\t\"airoha\"\n 15:\t\n 16:\t#define MTK_HDR_LEN\t\t4\n 17:\t#define MTK_HDR_XMIT_UNTAGGED\t\t0\n 18:\t#define MTK_HDR_XMIT_TAGGED_TPID_8100\t1\n 19:\t#define MTK_HDR_XMIT_TAGGED_TPID_88A8\t2\n 20:\t#define MTK_HDR_RECV_SOURCE_PORT_MASK\tGENMASK(2, 0)\n 21:\t#define MTK_HDR_XMIT_DP_BIT_MASK\tGENMASK(5, 0)\n 22:\t/* AN8855 doesn't support SA_DIS and Leaky VLAN\n 23:\t * control in tag as these bits doesn't exist.\n 24:\t */\n 25:\t#define MTK_HDR_XMIT_SA_DIS\t\tBIT(6)\n 26:\t\n 27:\tstatic struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,\n 28:\t\t\t\t\t struct net_device *dev)\n 29:\t{\n 30:\t\tstruct dsa_port *dp = dsa_user_to_port(dev);\n 31:\t\tu8 xmit_tpid;\n 32:\t\tu8 *mtk_tag;\n 33:\t\n 34:\t\tskb_set_queue_mapping(skb, dp-\u003eindex);\n 35:\t\n 36:\t\t/* Build the special tag after the MAC Source Address. If VLAN header\n 37:\t\t * is present, it's required that VLAN header and special tag is\n 38:\t\t * being combined. Only in this way we can allow the switch can parse\n 39:\t\t * the both special and VLAN tag at the same time and then look up VLAN\n 40:\t\t * table with VID.\n 41:\t\t */\n 42:\t\tswitch (skb-\u003eprotocol) {\n 43:\t\tcase htons(ETH_P_8021Q):\n 44:\t\t\txmit_tpid = MTK_HDR_XMIT_TAGGED_TPID_8100;\n 45:\t\t\tbreak;\n 46:\t\tcase htons(ETH_P_8021AD):\n 47:\t\t\txmit_tpid = MTK_HDR_XMIT_TAGGED_TPID_88A8;\n 48:\t\t\tbreak;\n 49:\t\tdefault:\n 50:\t\t\txmit_tpid = MTK_HDR_XMIT_UNTAGGED;\n 51:\t\t\tskb_push(skb, MTK_HDR_LEN);\n 52:\t\t\tdsa_alloc_etype_header(skb, MTK_HDR_LEN);\n 53:\t\t}\n 54:\t\n 55:\t\tmtk_tag = dsa_etype_header_pos_tx(skb);\n 56:\t\n 57:\t\t/* Mark tag attribute on special tag insertion to notify hardware\n 58:\t\t * whether that's a combined special tag with 802.1Q header.\n 59:\t\t */\n 60:\t\tmtk_tag[0] = xmit_tpid;\n 61:\t\tmtk_tag[1] = FIELD_PREP(MTK_HDR_XMIT_DP_BIT_MASK,\n 62:\t\t\t\t\tdsa_xmit_port_mask(skb, dev));\n 63:\t\n 64:\t\t/* Tag control information is kept for 802.1Q */\n 65:\t\tif (xmit_tpid == MTK_HDR_XMIT_UNTAGGED) {\n 66:\t\t\tmtk_tag[2] = 0;\n 67:\t\t\tmtk_tag[3] = 0;\n 68:\t\t}\n 69:\t\n 70:\t\treturn skb;\n 71:\t}\n 72:\t\n 73:\tstatic struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, struct net_device *dev)\n 74:\t{\n 75:\t\tu16 hdr;\n 76:\t\tint port;\n 77:\t\t__be16 *phdr;\n 78:\t\n 79:\t\tif (unlikely(!pskb_may_pull(skb, MTK_HDR_LEN))) {\n 80:\t\t\tkfree_skb(skb);\n 81:\t\t\treturn NULL;\n 82:\t\t}\n 83:\t\n 84:\t\tphdr = dsa_etype_header_pos_rx(skb);\n 85:\t\thdr = ntohs(*phdr);\n 86:\t\n 87:\t\t/* Remove MTK tag and recalculate checksum. */\n 88:\t\tskb_pull_rcsum(skb, MTK_HDR_LEN);\n 89:\t\n 90:\t\tdsa_strip_etype_header(skb, MTK_HDR_LEN);\n 91:\t\n 92:\t\t/* Get source port information */\n 93:\t\tport = (hdr \u0026 MTK_HDR_RECV_SOURCE_PORT_MASK);\n 94:\t\n 95:\t\tskb-\u003edev = dsa_conduit_find_user(dev, 0, port);\n 96:\t\tif (!skb-\u003edev) {\n 97:\t\t\tkfree_skb(skb);\n 98:\t\t\treturn NULL;\n 99:\t\t}\n 100:\t\n"
} |
| 35/2 | 2026/09/15 16:40 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 180122 output: 39 thoughts: 26 Thoughts: Okay, here's my attempt at summarizing the thought process, as requested, targeting an expert user and starting with a bolded header: **Diving into `tag_mtk.c` - Lines 101-145** Alright, let's get into the heart of `tag_mtk.c`. I'm going to focus on lines 101 through 145. I know the general architecture, but this section likely contains the meat of a specific function or a critical section of the driver. I'm looking for the core logic; the critical data structures being manipulated, the error conditions being handled (or *not* handled, which is often equally important). I'll be searching for any potential optimization opportunities. Are there any obvious bottlenecks in this section? Redundancies? Memory leaks? Are the comments actually *helpful* or just noise? I expect that these lines represent a crucial step in the process and want to understand it fully. I am specifically looking at the relationships between variables and if there are any hidden assumptions. From previous experience, the most challenging part of these sections are often the edge cases. I'll need to look for those and make sure that this code is able to cope with the various permutations of inputs. |
| 36/2 | 2026/09/15 16:40 | tool | read-file |
0mArgs:{
"File": "net/dsa/tag_mtk.c",
"FirstLine": 101,
"LineCount": 45
}Results: {
"Contents": " 101:\t\tdsa_default_offload_fwd_mark(skb);\n 102:\t\n 103:\t\treturn skb;\n 104:\t}\n 105:\t\n 106:\t#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)\n 107:\tstatic const struct dsa_device_ops mtk_netdev_ops = {\n 108:\t\t.name\t\t= MTK_NAME,\n 109:\t\t.proto\t\t= DSA_TAG_PROTO_MTK,\n 110:\t\t.xmit\t\t= mtk_tag_xmit,\n 111:\t\t.rcv\t\t= mtk_tag_rcv,\n 112:\t\t.needed_headroom = MTK_HDR_LEN,\n 113:\t};\n 114:\t\n 115:\tDSA_TAG_DRIVER(mtk_netdev_ops);\n 116:\tMODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);\n 117:\t#endif\n 118:\t\n 119:\t#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)\n 120:\tstatic const struct dsa_device_ops airoha_netdev_ops = {\n 121:\t\t.name\t\t= AIROHA_NAME,\n 122:\t\t.proto\t\t= DSA_TAG_PROTO_AIROHA,\n 123:\t\t.xmit\t\t= mtk_tag_xmit,\n 124:\t\t.rcv\t\t= mtk_tag_rcv,\n 125:\t\t.needed_headroom = MTK_HDR_LEN,\n 126:\t};\n 127:\t\n 128:\tDSA_TAG_DRIVER(airoha_netdev_ops);\n 129:\tMODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);\n 130:\t#endif\n 131:\t\n 132:\tstatic struct dsa_tag_driver *dsa_tag_driver_array[] =\t{\n 133:\t#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)\n 134:\t\t\u0026DSA_TAG_DRIVER_NAME(mtk_netdev_ops),\n 135:\t#endif\n 136:\t#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)\n 137:\t\t\u0026DSA_TAG_DRIVER_NAME(airoha_netdev_ops),\n 138:\t#endif\n 139:\t};\n 140:\t\n 141:\tmodule_dsa_tag_drivers(dsa_tag_driver_array);\n 142:\t\n 143:\tMODULE_DESCRIPTION(\"DSA tag driver for Mediatek switches\");\n 144:\tMODULE_LICENSE(\"GPL\");\n"
} |
| 37/2 | 2026/09/15 16:40 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 181207 output: 31 thoughts: 288 Thoughts: **My Analysis of the Patch** Okay, so the `mtk_tag_xmit` and `mtk_tag_rcv` functions haven't been touched, that's good. The patch introduces `airoha_netdev_ops`, which reuses them. Now, where is `airoha_netdev_ops` actually *used*? Hmm... It's only used by `drivers/net/dsa/an8855.c`. And that driver defines `an8855_get_tag_protocol` which just returns `DSA_TAG_PROTO_AIROHA`, indicating an Airoha-specific tagging protocol. Aha! `an8855.c` is only loaded if the an8855 hardware switch is present, and that switch is a Multi-Function Device (MFD) child of an an8855 MDIO device. This is starting to make sense. The change is clearly tied to a specific hardware configuration. But wait, I need to be thorough. Are there any other changes? Are there any mock or test facilities I should be aware of related to MDIO or DSA? Can DSA switches be created in userspace without the physical hardware, maybe for testing purposes? Let me check the `net/dsa` directory, specifically looking at `dsa_loop`. How does `dsa_loop` work? I need to understand how it's registered and probed to see if it introduces any test hooks or mock implementations that might be relevant here. Let's dig into that code. |
| 38/2 | 2026/09/15 16:40 | tool | grepper |
0mArgs:{
"Expression": "dsa_loop",
"PathPrefix": "drivers/net/dsa/"
}Results: {
"Output": "drivers/net/dsa/Makefile=4=bcm-sf2-objs\t\t\t:= bcm_sf2.o bcm_sf2_cfp.o\ndrivers/net/dsa/Makefile:5:obj-$(CONFIG_NET_DSA_LOOP)\t+= dsa_loop.o\ndrivers/net/dsa/Makefile-6-obj-$(CONFIG_NET_DSA_KS8995) \t+= ks8995.o\n--\ndrivers/net/dsa/dsa_loop.c-24-\ndrivers/net/dsa/dsa_loop.c:25:struct dsa_loop_vlan {\ndrivers/net/dsa/dsa_loop.c-26-\tu16 members;\n--\ndrivers/net/dsa/dsa_loop.c-29-\ndrivers/net/dsa/dsa_loop.c:30:struct dsa_loop_mib_entry {\ndrivers/net/dsa/dsa_loop.c-31-\tchar name[ETH_GSTRING_LEN];\n--\ndrivers/net/dsa/dsa_loop.c-34-\ndrivers/net/dsa/dsa_loop.c:35:enum dsa_loop_mib_counters {\ndrivers/net/dsa/dsa_loop.c-36-\tDSA_LOOP_PHY_READ_OK,\n--\ndrivers/net/dsa/dsa_loop.c-42-\ndrivers/net/dsa/dsa_loop.c:43:struct dsa_loop_port {\ndrivers/net/dsa/dsa_loop.c:44:\tstruct dsa_loop_mib_entry mib[__DSA_LOOP_CNT_MAX];\ndrivers/net/dsa/dsa_loop.c-45-\tu16 pvid;\n--\ndrivers/net/dsa/dsa_loop.c-48-\ndrivers/net/dsa/dsa_loop.c:49:struct dsa_loop_priv {\ndrivers/net/dsa/dsa_loop.c-50-\tstruct mii_bus\t*bus;\ndrivers/net/dsa/dsa_loop.c-51-\tunsigned int\tport_base;\ndrivers/net/dsa/dsa_loop.c:52:\tstruct dsa_loop_vlan vlans[VLAN_N_VID];\ndrivers/net/dsa/dsa_loop.c-53-\tstruct net_device *netdev;\ndrivers/net/dsa/dsa_loop.c:54:\tstruct dsa_loop_port ports[DSA_MAX_PORTS];\ndrivers/net/dsa/dsa_loop.c-55-};\ndrivers/net/dsa/dsa_loop.c-56-\ndrivers/net/dsa/dsa_loop.c:57:struct dsa_loop_pdata {\ndrivers/net/dsa/dsa_loop.c-58-\t/* Must be first, such that dsa_register_switch() can access this\n--\ndrivers/net/dsa/dsa_loop.c-66-\ndrivers/net/dsa/dsa_loop.c:67:static struct dsa_loop_mib_entry dsa_loop_mibs[] = {\ndrivers/net/dsa/dsa_loop.c-68-\t[DSA_LOOP_PHY_READ_OK]\t= { \"phy_read_ok\", },\n--\ndrivers/net/dsa/dsa_loop.c=75=static struct mdio_device *switch_mdiodev;\ndrivers/net/dsa/dsa_loop.c-76-\ndrivers/net/dsa/dsa_loop.c:77:enum dsa_loop_devlink_resource_id {\ndrivers/net/dsa/dsa_loop.c-78-\tDSA_LOOP_DEVLINK_PARAM_ID_NONE, /* DEVLINK_RESOURCE_ID_PARENT_TOP */\n--\ndrivers/net/dsa/dsa_loop.c-81-\ndrivers/net/dsa/dsa_loop.c:82:static u64 dsa_loop_devlink_vtu_get(void *priv)\ndrivers/net/dsa/dsa_loop.c-83-{\ndrivers/net/dsa/dsa_loop.c:84:\tstruct dsa_loop_priv *ps = priv;\ndrivers/net/dsa/dsa_loop.c-85-\tunsigned int i, count = 0;\ndrivers/net/dsa/dsa_loop.c:86:\tstruct dsa_loop_vlan *vl;\ndrivers/net/dsa/dsa_loop.c-87-\n--\ndrivers/net/dsa/dsa_loop.c-96-\ndrivers/net/dsa/dsa_loop.c:97:static int dsa_loop_setup_devlink_resources(struct dsa_switch *ds)\ndrivers/net/dsa/dsa_loop.c-98-{\ndrivers/net/dsa/dsa_loop.c-99-\tstruct devlink_resource_size_params size_params;\ndrivers/net/dsa/dsa_loop.c:100:\tstruct dsa_loop_priv *ps = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-101-\tint err;\n--\ndrivers/net/dsa/dsa_loop.c-115-\t\t\t\t\t DSA_LOOP_DEVLINK_PARAM_ID_VTU,\ndrivers/net/dsa/dsa_loop.c:116:\t\t\t\t\t dsa_loop_devlink_vtu_get, ps);\ndrivers/net/dsa/dsa_loop.c-117-\n--\ndrivers/net/dsa/dsa_loop.c-124-\ndrivers/net/dsa/dsa_loop.c:125:static enum dsa_tag_protocol dsa_loop_get_protocol(struct dsa_switch *ds,\ndrivers/net/dsa/dsa_loop.c-126-\t\t\t\t\t\t int port,\n--\ndrivers/net/dsa/dsa_loop.c-133-\ndrivers/net/dsa/dsa_loop.c:134:static int dsa_loop_setup(struct dsa_switch *ds)\ndrivers/net/dsa/dsa_loop.c-135-{\ndrivers/net/dsa/dsa_loop.c:136:\tstruct dsa_loop_priv *ps = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-137-\tunsigned int i;\n--\ndrivers/net/dsa/dsa_loop.c-139-\tfor (i = 0; i \u003c ds-\u003enum_ports; i++)\ndrivers/net/dsa/dsa_loop.c:140:\t\tmemcpy(ps-\u003eports[i].mib, dsa_loop_mibs,\ndrivers/net/dsa/dsa_loop.c:141:\t\t sizeof(dsa_loop_mibs));\ndrivers/net/dsa/dsa_loop.c-142-\n--\ndrivers/net/dsa/dsa_loop.c-144-\ndrivers/net/dsa/dsa_loop.c:145:\treturn dsa_loop_setup_devlink_resources(ds);\ndrivers/net/dsa/dsa_loop.c-146-}\ndrivers/net/dsa/dsa_loop.c-147-\ndrivers/net/dsa/dsa_loop.c:148:static void dsa_loop_teardown(struct dsa_switch *ds)\ndrivers/net/dsa/dsa_loop.c-149-{\n--\ndrivers/net/dsa/dsa_loop.c-152-\ndrivers/net/dsa/dsa_loop.c:153:static int dsa_loop_get_sset_count(struct dsa_switch *ds, int port, int sset)\ndrivers/net/dsa/dsa_loop.c-154-{\n--\ndrivers/net/dsa/dsa_loop.c-160-\ndrivers/net/dsa/dsa_loop.c:161:static void dsa_loop_get_strings(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-162-\t\t\t\t u32 stringset, uint8_t *data)\ndrivers/net/dsa/dsa_loop.c-163-{\ndrivers/net/dsa/dsa_loop.c:164:\tstruct dsa_loop_priv *ps = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-165-\tunsigned int i;\n--\ndrivers/net/dsa/dsa_loop.c-173-\ndrivers/net/dsa/dsa_loop.c:174:static void dsa_loop_get_ethtool_stats(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-175-\t\t\t\t uint64_t *data)\ndrivers/net/dsa/dsa_loop.c-176-{\ndrivers/net/dsa/dsa_loop.c:177:\tstruct dsa_loop_priv *ps = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-178-\tunsigned int i;\n--\ndrivers/net/dsa/dsa_loop.c-183-\ndrivers/net/dsa/dsa_loop.c:184:static int dsa_loop_phy_read(struct dsa_switch *ds, int port, int regnum)\ndrivers/net/dsa/dsa_loop.c-185-{\ndrivers/net/dsa/dsa_loop.c:186:\tstruct dsa_loop_priv *ps = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-187-\tstruct mii_bus *bus = ps-\u003ebus;\n--\ndrivers/net/dsa/dsa_loop.c-198-\ndrivers/net/dsa/dsa_loop.c:199:static int dsa_loop_phy_write(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-200-\t\t\t int regnum, u16 value)\ndrivers/net/dsa/dsa_loop.c-201-{\ndrivers/net/dsa/dsa_loop.c:202:\tstruct dsa_loop_priv *ps = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-203-\tstruct mii_bus *bus = ps-\u003ebus;\n--\ndrivers/net/dsa/dsa_loop.c-214-\ndrivers/net/dsa/dsa_loop.c:215:static int dsa_loop_port_bridge_join(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-216-\t\t\t\t struct dsa_bridge bridge,\n--\ndrivers/net/dsa/dsa_loop.c-225-\ndrivers/net/dsa/dsa_loop.c:226:static void dsa_loop_port_bridge_leave(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-227-\t\t\t\t struct dsa_bridge bridge)\n--\ndrivers/net/dsa/dsa_loop.c-232-\ndrivers/net/dsa/dsa_loop.c:233:static void dsa_loop_port_stp_state_set(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-234-\t\t\t\t\tu8 state)\n--\ndrivers/net/dsa/dsa_loop.c-239-\ndrivers/net/dsa/dsa_loop.c:240:static int dsa_loop_port_vlan_filtering(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-241-\t\t\t\t\tbool vlan_filtering,\n--\ndrivers/net/dsa/dsa_loop.c-249-\ndrivers/net/dsa/dsa_loop.c:250:static int dsa_loop_port_vlan_add(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-251-\t\t\t\t const struct switchdev_obj_port_vlan *vlan,\n--\ndrivers/net/dsa/dsa_loop.c-255-\tbool pvid = vlan-\u003eflags \u0026 BRIDGE_VLAN_INFO_PVID;\ndrivers/net/dsa/dsa_loop.c:256:\tstruct dsa_loop_priv *ps = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-257-\tstruct mii_bus *bus = ps-\u003ebus;\ndrivers/net/dsa/dsa_loop.c:258:\tstruct dsa_loop_vlan *vl;\ndrivers/net/dsa/dsa_loop.c-259-\n--\ndrivers/net/dsa/dsa_loop.c-282-\ndrivers/net/dsa/dsa_loop.c:283:static int dsa_loop_port_vlan_del(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-284-\t\t\t\t const struct switchdev_obj_port_vlan *vlan)\n--\ndrivers/net/dsa/dsa_loop.c-286-\tbool untagged = vlan-\u003eflags \u0026 BRIDGE_VLAN_INFO_UNTAGGED;\ndrivers/net/dsa/dsa_loop.c:287:\tstruct dsa_loop_priv *ps = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-288-\tu16 pvid = ps-\u003eports[port].pvid;\ndrivers/net/dsa/dsa_loop.c-289-\tstruct mii_bus *bus = ps-\u003ebus;\ndrivers/net/dsa/dsa_loop.c:290:\tstruct dsa_loop_vlan *vl;\ndrivers/net/dsa/dsa_loop.c-291-\n--\ndrivers/net/dsa/dsa_loop.c-310-\ndrivers/net/dsa/dsa_loop.c:311:static int dsa_loop_port_change_mtu(struct dsa_switch *ds, int port,\ndrivers/net/dsa/dsa_loop.c-312-\t\t\t\t int new_mtu)\ndrivers/net/dsa/dsa_loop.c-313-{\ndrivers/net/dsa/dsa_loop.c:314:\tstruct dsa_loop_priv *priv = ds-\u003epriv;\ndrivers/net/dsa/dsa_loop.c-315-\n--\ndrivers/net/dsa/dsa_loop.c-320-\ndrivers/net/dsa/dsa_loop.c:321:static int dsa_loop_port_max_mtu(struct dsa_switch *ds, int port)\ndrivers/net/dsa/dsa_loop.c-322-{\n--\ndrivers/net/dsa/dsa_loop.c-325-\ndrivers/net/dsa/dsa_loop.c:326:static void dsa_loop_phylink_get_caps(struct dsa_switch *dsa, int port,\ndrivers/net/dsa/dsa_loop.c-327-\t\t\t\t struct phylink_config *config)\n--\ndrivers/net/dsa/dsa_loop.c-333-\ndrivers/net/dsa/dsa_loop.c:334:static const struct dsa_switch_ops dsa_loop_driver = {\ndrivers/net/dsa/dsa_loop.c:335:\t.get_tag_protocol\t= dsa_loop_get_protocol,\ndrivers/net/dsa/dsa_loop.c:336:\t.setup\t\t\t= dsa_loop_setup,\ndrivers/net/dsa/dsa_loop.c:337:\t.teardown\t\t= dsa_loop_teardown,\ndrivers/net/dsa/dsa_loop.c:338:\t.get_strings\t\t= dsa_loop_get_strings,\ndrivers/net/dsa/dsa_loop.c:339:\t.get_ethtool_stats\t= dsa_loop_get_ethtool_stats,\ndrivers/net/dsa/dsa_loop.c:340:\t.get_sset_count\t\t= dsa_loop_get_sset_count,\ndrivers/net/dsa/dsa_loop.c:341:\t.get_ethtool_phy_stats\t= dsa_loop_get_ethtool_stats,\ndrivers/net/dsa/dsa_loop.c:342:\t.phy_read\t\t= dsa_loop_phy_read,\ndrivers/net/dsa/dsa_loop.c:343:\t.phy_write\t\t= dsa_loop_phy_write,\ndrivers/net/dsa/dsa_loop.c:344:\t.port_bridge_join\t= dsa_loop_port_bridge_join,\ndrivers/net/dsa/dsa_loop.c:345:\t.port_bridge_leave\t= dsa_loop_port_bridge_leave,\ndrivers/net/dsa/dsa_loop.c:346:\t.port_stp_state_set\t= dsa_loop_port_stp_state_set,\ndrivers/net/dsa/dsa_loop.c:347:\t.port_vlan_filtering\t= dsa_loop_port_vlan_filtering,\ndrivers/net/dsa/dsa_loop.c:348:\t.port_vlan_add\t\t= dsa_loop_port_vlan_add,\ndrivers/net/dsa/dsa_loop.c:349:\t.port_vlan_del\t\t= dsa_loop_port_vlan_del,\ndrivers/net/dsa/dsa_loop.c:350:\t.port_change_mtu\t= dsa_loop_port_change_mtu,\ndrivers/net/dsa/dsa_loop.c:351:\t.port_max_mtu\t\t= dsa_loop_port_max_mtu,\ndrivers/net/dsa/dsa_loop.c:352:\t.phylink_get_caps\t= dsa_loop_phylink_get_caps,\ndrivers/net/dsa/dsa_loop.c-353-};\ndrivers/net/dsa/dsa_loop.c-354-\ndrivers/net/dsa/dsa_loop.c:355:static int dsa_loop_drv_probe(struct mdio_device *mdiodev)\ndrivers/net/dsa/dsa_loop.c-356-{\ndrivers/net/dsa/dsa_loop.c:357:\tstruct dsa_loop_pdata *pdata = mdiodev-\u003edev.platform_data;\ndrivers/net/dsa/dsa_loop.c:358:\tstruct dsa_loop_priv *ps;\ndrivers/net/dsa/dsa_loop.c-359-\tstruct dsa_switch *ds;\n--\ndrivers/net/dsa/dsa_loop.c-382-\tds-\u003edev = \u0026mdiodev-\u003edev;\ndrivers/net/dsa/dsa_loop.c:383:\tds-\u003eops = \u0026dsa_loop_driver;\ndrivers/net/dsa/dsa_loop.c-384-\tds-\u003epriv = ps;\n--\ndrivers/net/dsa/dsa_loop.c-396-\ndrivers/net/dsa/dsa_loop.c:397:static void dsa_loop_drv_remove(struct mdio_device *mdiodev)\ndrivers/net/dsa/dsa_loop.c-398-{\ndrivers/net/dsa/dsa_loop.c-399-\tstruct dsa_switch *ds = dev_get_drvdata(\u0026mdiodev-\u003edev);\ndrivers/net/dsa/dsa_loop.c:400:\tstruct dsa_loop_priv *ps;\ndrivers/net/dsa/dsa_loop.c-401-\n--\ndrivers/net/dsa/dsa_loop.c-410-\ndrivers/net/dsa/dsa_loop.c:411:static void dsa_loop_drv_shutdown(struct mdio_device *mdiodev)\ndrivers/net/dsa/dsa_loop.c-412-{\n--\ndrivers/net/dsa/dsa_loop.c-422-\ndrivers/net/dsa/dsa_loop.c:423:static struct mdio_driver dsa_loop_drv = {\ndrivers/net/dsa/dsa_loop.c-424-\t.mdiodrv.driver\t= {\n--\ndrivers/net/dsa/dsa_loop.c-426-\t},\ndrivers/net/dsa/dsa_loop.c:427:\t.probe\t= dsa_loop_drv_probe,\ndrivers/net/dsa/dsa_loop.c:428:\t.remove\t= dsa_loop_drv_remove,\ndrivers/net/dsa/dsa_loop.c:429:\t.shutdown = dsa_loop_drv_shutdown,\ndrivers/net/dsa/dsa_loop.c-430-};\ndrivers/net/dsa/dsa_loop.c-431-\ndrivers/net/dsa/dsa_loop.c:432:static int dsa_loop_bus_match(struct device *dev,\ndrivers/net/dsa/dsa_loop.c-433-\t\t\t const struct device_driver *drv)\ndrivers/net/dsa/dsa_loop.c-434-{\ndrivers/net/dsa/dsa_loop.c:435:\treturn drv == \u0026dsa_loop_drv.mdiodrv.driver;\ndrivers/net/dsa/dsa_loop.c-436-}\ndrivers/net/dsa/dsa_loop.c-437-\ndrivers/net/dsa/dsa_loop.c:438:static void dsa_loop_phydevs_unregister(void)\ndrivers/net/dsa/dsa_loop.c-439-{\n--\ndrivers/net/dsa/dsa_loop.c-445-\ndrivers/net/dsa/dsa_loop.c:446:static int __init dsa_loop_create_switch_mdiodev(void)\ndrivers/net/dsa/dsa_loop.c-447-{\ndrivers/net/dsa/dsa_loop.c:448:\tstatic struct dsa_loop_pdata dsa_loop_pdata = {\ndrivers/net/dsa/dsa_loop.c-449-\t\t.cd = {\n--\ndrivers/net/dsa/dsa_loop.c-470-\ndrivers/net/dsa/dsa_loop.c:471:\tswitch_mdiodev-\u003ebus_match = dsa_loop_bus_match;\ndrivers/net/dsa/dsa_loop.c:472:\tswitch_mdiodev-\u003edev.platform_data = \u0026dsa_loop_pdata;\ndrivers/net/dsa/dsa_loop.c-473-\n--\ndrivers/net/dsa/dsa_loop.c-481-\ndrivers/net/dsa/dsa_loop.c:482:static int __init dsa_loop_init(void)\ndrivers/net/dsa/dsa_loop.c-483-{\n--\ndrivers/net/dsa/dsa_loop.c-486-\ndrivers/net/dsa/dsa_loop.c:487:\tret = dsa_loop_create_switch_mdiodev();\ndrivers/net/dsa/dsa_loop.c-488-\tif (ret)\n--\ndrivers/net/dsa/dsa_loop.c-493-\ndrivers/net/dsa/dsa_loop.c:494:\tret = mdio_driver_register(\u0026dsa_loop_drv);\ndrivers/net/dsa/dsa_loop.c-495-\tif (ret) {\ndrivers/net/dsa/dsa_loop.c:496:\t\tdsa_loop_phydevs_unregister();\ndrivers/net/dsa/dsa_loop.c-497-\t\tmdio_device_remove(switch_mdiodev);\n--\ndrivers/net/dsa/dsa_loop.c-502-}\ndrivers/net/dsa/dsa_loop.c:503:module_init(dsa_loop_init);\ndrivers/net/dsa/dsa_loop.c-504-\ndrivers/net/dsa/dsa_loop.c:505:static void __exit dsa_loop_exit(void)\ndrivers/net/dsa/dsa_loop.c-506-{\ndrivers/net/dsa/dsa_loop.c:507:\tmdio_driver_unregister(\u0026dsa_loop_drv);\ndrivers/net/dsa/dsa_loop.c:508:\tdsa_loop_phydevs_unregister();\ndrivers/net/dsa/dsa_loop.c-509-\tmdio_device_remove(switch_mdiodev);\n--\ndrivers/net/dsa/dsa_loop.c-511-}\ndrivers/net/dsa/dsa_loop.c:512:module_exit(dsa_loop_exit);\ndrivers/net/dsa/dsa_loop.c-513-\n"
} |
| 39/2 | 2026/09/15 16:40 | llm | patch-evaluator |
0mModel:gemini-3.8-flash Args: null Results: null Tokens: input: 188403 output: 155 thoughts: 1257 Thoughts: **Fuzzing Verdict: Not Worthy** Okay, so I've got this `dsa_loop` setup, which creates its own `switch_mdiodev` and uses `dsa_loop_driver`, which, from what I can tell, doesn't even bother with changing tag protocols. Makes sense, it's a loopback after all. Then there are all these drivers that got modified: Airoha AN8855, MediaTek MT7530/31/7988, the tag logic... But, hold on. Can any of this actually be tested in a virtualized environment like QEMU? I have to consider this. Let's refer to those instructions. The instructions say to only mark something as worthy if it meets specific criteria. Negative criteria includes "Structurally unreachable hardware." This specifically means vendors’ switches, SmartNICs, or GPU drivers that need special ASIC/PCIe cards that aren't available in standard QEMU. That's a good benchmark. Also important: "Code paths exclusive to architectures other than the target architecture", which does not apply here. So, let's look at the patch itself. We're talking Device Tree bindings, MFD driver for Airoha AN8855, DSA driver, PHY driver, and the MediaTek refactor and Airoha tag ops. And I know I am looking at hardware specific drivers. Now I remember. The Airoha AN8855, the MT7530, all these chips... these are all physical hardware. Specifically embedded router boards. They use MDIO/MMIO buses, Device Tree bindings. They are accessed that way. Standard QEMU/GCE? They don't emulate *any* of this. There's no virtual bus, no software-emulated device that'll instantiate this hardware. So, as far as I can tell, *all* this modified code is "structurally unreachable." It's all hardware I cannot easily access to test. I can't think of any other way to put this, so this seems pretty clear. The worthfuzzing criteria is false, no specific focus symbols, and no special enable configs are required. So let's break this reasoning down: 1. **What the patch does:** Introduces support for physical switch hardware: Airoha AN8855 and MediaTek MT7530/MT7531/MT7988. 2. **Why not worth fuzzing:** The code is hardware drivers for physical ASICs. These communicate over physical buses. We cannot access them or emulate them in a simple setup. Therefore, it is unreachable in standard virtualized environments. This reasoning seems really solid, and I think it all aligns with the instructions, so I can go ahead and call `set-results`. |
| 40/2 | 2026/09/15 16:40 | tool | set-results |
0mArgs:{
"EnableConfigs": [],
"FocusSymbols": [],
"Reasoning": "The patch series introduces driver support for the Airoha AN8855 Switch SoC (including MFD core over MDIO, internal PHY, and DSA switch platform driver) and refactors the MediaTek MT7530 DSA switch driver into a shared library (mt7530-lib.c). These drivers target physical network switch and PHY ASICs used on embedded networking hardware (probed via MDIO and Device Tree) which are not emulated in standard virtualized environments (QEMU/KVM or GCE). Consequently, the modified executable code is structurally unreachable for fuzzing.",
"WorthFuzzing": false
}Results: {
"EnableConfigs": null,
"FocusSymbols": [],
"Reasoning": "The patch series introduces driver support for the Airoha AN8855 Switch SoC (including MFD core over MDIO, internal PHY, and DSA switch platform driver) and refactors the MediaTek MT7530 DSA switch driver into a shared library (mt7530-lib.c). These drivers target physical network switch and PHY ASICs used on embedded networking hardware (probed via MDIO and Device Tree) which are not emulated in standard virtualized environments (QEMU/KVM or GCE). Consequently, the modified executable code is structurally unreachable for fuzzing.",
"WorthFuzzing": false
} |
| 41/1 | 2026/09/15 16:40 | action | If |
0mArgs:{
"WorthFuzzing": false
}Results: null |
| Total Calls | Total Tokens | Avg Tokens | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|
| Total Calls | Total Duration (Seconds) | Avg Duration (Seconds) |
|---|