AI Trajectory


Trajectory: (Expand/Collapse All)
Seq Timestamp Type Name Duration
0/0 2026/10/19 10:54 flow patch-triage
0m Args: 
null

Results: 
{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "KMSANReasoning": "",
  "NeedsKMSAN": false,
  "Reasoning": "The patch modifies only Device Tree documentation and ARM64 DTS files (arch/arm64/boot/dts/qcom/) for the Qualcomm Lemans Draco EVK board. These changes do not modify executable kernel C code and are specific to arm64 hardware, making them completely unreachable on the target amd64 architecture.",
  "WorthFuzzing": false
}
1/1 2026/10/19 10:54 action read-patch-diff
0m Args: 
null

Results: 
{
  "PatchDiff": "commit fd388684dabce6991ed220011eb45c959fa06792\nAuthor: syz-cluster \u003ctriage@syzkaller.com\u003e\nDate:   Mon Oct 19 10:54:28 2026 +0000\n\n    syz-cluster: applied patch under review\n\ndiff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml\nindex 07ef7988b0683..1efd6ea34c3f1 100644\n--- a/Documentation/devicetree/bindings/arm/qcom.yaml\n+++ b/Documentation/devicetree/bindings/arm/qcom.yaml\n@@ -498,6 +498,7 @@ properties:\n       - items:\n           - enum:\n               - qcom,lemans-evk\n+              - qcom,lemans-draco-evk\n               - qcom,qcs9100-ride\n               - qcom,qcs9100-ride-r3\n           - const: qcom,qcs9100\ndiff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile\nindex 4e714251d5e6b..f1713d53af5f6 100644\n--- a/arch/arm64/boot/dts/qcom/Makefile\n+++ b/arch/arm64/boot/dts/qcom/Makefile\n@@ -50,6 +50,11 @@ dtb-$(CONFIG_ARCH_QCOM)\t+= ipq9650-rdp488.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= kaanapali-mtp.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= kaanapali-qrd.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= lemans-evk.dtb\n+dtb-$(CONFIG_ARCH_QCOM)\t+= lemans-draco-evk.dtb\n+\n+lemans-draco-evk-el2-dtbs := lemans-draco-evk.dtb lemans-el2.dtbo\n+\n+dtb-$(CONFIG_ARCH_QCOM)\t+= lemans-draco-evk-el2.dtb\n \n lemans-evk-camera-csi1-imx577-dtbs\t:= lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo\n lemans-evk-camera-dtbs\t:= lemans-evk.dtb lemans-evk-camera.dtbo\ndiff --git a/arch/arm64/boot/dts/qcom/lemans-draco-evk-som.dtsi b/arch/arm64/boot/dts/qcom/lemans-draco-evk-som.dtsi\nnew file mode 100644\nindex 0000000000000..6b7971bcdc934\n--- /dev/null\n+++ b/arch/arm64/boot/dts/qcom/lemans-draco-evk-som.dtsi\n@@ -0,0 +1,401 @@\n+// SPDX-License-Identifier: BSD-3-Clause\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include \u003cdt-bindings/gpio/gpio.h\u003e\n+#include \u003cdt-bindings/regulator/qcom,rpmh-regulator.h\u003e\n+#include \"lemans.dtsi\"\n+#include \"lemans-pmics.dtsi\"\n+\n+/ {\n+\taliases {\n+\t\tserial0 = \u0026uart10;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+};\n+\n+\u0026apps_rsc {\n+\tregulators-0 {\n+\t\tcompatible = \"qcom,pmm8654au-rpmh-regulators\";\n+\t\tqcom,pmic-id = \"a\";\n+\n+\t\tvreg_s4a: smps4 {\n+\t\t\tregulator-name = \"vreg_s4a\";\n+\t\t\tregulator-min-microvolt = \u003c1800000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1816000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_s5a: smps5 {\n+\t\t\tregulator-name = \"vreg_s5a\";\n+\t\t\tregulator-min-microvolt = \u003c1850000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1996000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_s9a: smps9 {\n+\t\t\tregulator-name = \"vreg_s9a\";\n+\t\t\tregulator-min-microvolt = \u003c535000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1120000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l4a: ldo4 {\n+\t\t\tregulator-name = \"vreg_l4a\";\n+\t\t\tregulator-min-microvolt = \u003c788000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1050000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l5a: ldo5 {\n+\t\t\tregulator-name = \"vreg_l5a\";\n+\t\t\tregulator-min-microvolt = \u003c870000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c950000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l6a: ldo6 {\n+\t\t\tregulator-name = \"vreg_l6a\";\n+\t\t\tregulator-min-microvolt = \u003c870000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c970000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l7a: ldo7 {\n+\t\t\tregulator-name = \"vreg_l7a\";\n+\t\t\tregulator-min-microvolt = \u003c720000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c950000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l8a: ldo8 {\n+\t\t\tregulator-name = \"vreg_l8a\";\n+\t\t\tregulator-min-microvolt = \u003c2504000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l9a: ldo9 {\n+\t\t\tregulator-name = \"vreg_l9a\";\n+\t\t\tregulator-min-microvolt = \u003c2970000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c3544000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\t};\n+\n+\tregulators-1 {\n+\t\tcompatible = \"qcom,pmm8654au-rpmh-regulators\";\n+\t\tqcom,pmic-id = \"c\";\n+\n+\t\tvreg_l1c: ldo1 {\n+\t\t\tregulator-name = \"vreg_l1c\";\n+\t\t\tregulator-min-microvolt = \u003c1140000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1260000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l2c: ldo2 {\n+\t\t\tregulator-name = \"vreg_l2c\";\n+\t\t\tregulator-min-microvolt = \u003c900000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1100000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l3c: ldo3 {\n+\t\t\tregulator-name = \"vreg_l3c\";\n+\t\t\tregulator-min-microvolt = \u003c1100000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1300000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l4c: ldo4 {\n+\t\t\tregulator-name = \"vreg_l4c\";\n+\t\t\tregulator-min-microvolt = \u003c1200000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1200000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l5c: ldo5 {\n+\t\t\tregulator-name = \"vreg_l5c\";\n+\t\t\tregulator-min-microvolt = \u003c1100000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1300000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l6c: ldo6 {\n+\t\t\tregulator-name = \"vreg_l6c\";\n+\t\t\tregulator-min-microvolt = \u003c1620000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1980000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l7c: ldo7 {\n+\t\t\tregulator-name = \"vreg_l7c\";\n+\t\t\tregulator-min-microvolt = \u003c1620000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c2000000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l8c: ldo8 {\n+\t\t\tregulator-name = \"vreg_l8c\";\n+\t\t\tregulator-min-microvolt = \u003c2400000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l9c: ldo9 {\n+\t\t\tregulator-name = \"vreg_l9c\";\n+\t\t\tregulator-min-microvolt = \u003c1650000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c2700000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\t};\n+\n+\tregulators-2 {\n+\t\tcompatible = \"qcom,pmm8654au-rpmh-regulators\";\n+\t\tqcom,pmic-id = \"e\";\n+\n+\t\tvreg_s4e: smps4 {\n+\t\t\tregulator-name = \"vreg_s4e\";\n+\t\t\tregulator-min-microvolt = \u003c970000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1520000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_s7e: smps7 {\n+\t\t\tregulator-name = \"vreg_s7e\";\n+\t\t\tregulator-min-microvolt = \u003c1010000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1170000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_s9e: smps9 {\n+\t\t\tregulator-name = \"vreg_s9e\";\n+\t\t\tregulator-min-microvolt = \u003c300000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c570000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l6e: ldo6 {\n+\t\t\tregulator-name = \"vreg_l6e\";\n+\t\t\tregulator-min-microvolt = \u003c1280000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1450000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\n+\t\tvreg_l8e: ldo8 {\n+\t\t\tregulator-name = \"vreg_l8e\";\n+\t\t\tregulator-min-microvolt = \u003c1800000\u003e;\n+\t\t\tregulator-max-microvolt = \u003c1950000\u003e;\n+\t\t\tregulator-initial-mode = \u003cRPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t\tregulator-allow-set-load;\n+\t\t\tregulator-allowed-modes = \u003cRPMH_REGULATOR_MODE_LPM\n+\t\t\t\t\t\t   RPMH_REGULATOR_MODE_HPM\u003e;\n+\t\t};\n+\t};\n+};\n+\n+\u0026gpu {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026gpu_zap_shader {\n+\tfirmware-name = \"qcom/sa8775p/a663_zap.mbn\";\n+};\n+\n+\u0026iris {\n+\tfirmware-name = \"qcom/vpu/vpu30_p4_s6_16mb.mbn\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026pmm8654au_0_pon_resin {\n+\tlinux,code = \u003cKEY_VOLUMEDOWN\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026qupv3_id_0 {\n+\tfirmware-name = \"qcom/sa8775p/qupv3fw.elf\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026qupv3_id_1 {\n+\tfirmware-name = \"qcom/sa8775p/qupv3fw.elf\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026qupv3_id_2 {\n+\tfirmware-name = \"qcom/sa8775p/qupv3fw.elf\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026remoteproc_adsp {\n+\tfirmware-name = \"qcom/sa8775p/adsp.mbn\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026remoteproc_cdsp0 {\n+\tfirmware-name = \"qcom/sa8775p/cdsp0.mbn\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026remoteproc_cdsp1 {\n+\tfirmware-name = \"qcom/sa8775p/cdsp1.mbn\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026remoteproc_gpdsp0 {\n+\tfirmware-name = \"qcom/sa8775p/gpdsp0.mbn\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026remoteproc_gpdsp1 {\n+\tfirmware-name = \"qcom/sa8775p/gpdsp1.mbn\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026sleep_clk {\n+\tclock-frequency = \u003c32768\u003e;\n+};\n+\n+\u0026uart10 {\n+\tcompatible = \"qcom,geni-debug-uart\";\n+\tpinctrl-0 = \u003c\u0026qup_uart10_default\u003e;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026ufs_mem_hc {\n+\treset-gpios = \u003c\u0026tlmm 149 GPIO_ACTIVE_LOW\u003e;\n+\tvcc-supply = \u003c\u0026vreg_l8a\u003e;\n+\tvcc-max-microamp = \u003c1100000\u003e;\n+\tvccq-supply = \u003c\u0026vreg_l4c\u003e;\n+\tvccq-max-microamp = \u003c1200000\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026ufs_mem_phy {\n+\tvdda-phy-supply = \u003c\u0026vreg_l4a\u003e;\n+\tvdda-pll-supply = \u003c\u0026vreg_l1c\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026usb_0 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026usb_0_hsphy {\n+\tvdda-pll-supply = \u003c\u0026vreg_l7a\u003e;\n+\tvdda18-supply = \u003c\u0026vreg_l6c\u003e;\n+\tvdda33-supply = \u003c\u0026vreg_l9a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026usb_0_qmpphy {\n+\tvdda-phy-supply = \u003c\u0026vreg_l1c\u003e;\n+\tvdda-pll-supply = \u003c\u0026vreg_l7a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026usb_1 {\n+\tdr_mode = \"host\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026usb_1_hsphy {\n+\tvdda-pll-supply = \u003c\u0026vreg_l7a\u003e;\n+\tvdda18-supply = \u003c\u0026vreg_l6c\u003e;\n+\tvdda33-supply = \u003c\u0026vreg_l9a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026usb_1_qmpphy {\n+\tvdda-phy-supply = \u003c\u0026vreg_l1c\u003e;\n+\tvdda-pll-supply = \u003c\u0026vreg_l7a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026usb_2 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026usb_2_hsphy {\n+\tvdda-pll-supply = \u003c\u0026vreg_l7a\u003e;\n+\tvdda18-supply = \u003c\u0026vreg_l6c\u003e;\n+\tvdda33-supply = \u003c\u0026vreg_l9a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026xo_board_clk {\n+\tclock-frequency = \u003c38400000\u003e;\n+};\ndiff --git a/arch/arm64/boot/dts/qcom/lemans-draco-evk.dts b/arch/arm64/boot/dts/qcom/lemans-draco-evk.dts\nnew file mode 100644\nindex 0000000000000..5238157ad0029\n--- /dev/null\n+++ b/arch/arm64/boot/dts/qcom/lemans-draco-evk.dts\n@@ -0,0 +1,543 @@\n+// SPDX-License-Identifier: BSD-3-Clause\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+/dts-v1/;\n+\n+#include \u003cdt-bindings/pwm/pwm.h\u003e\n+#include \"lemans-draco-evk-som.dtsi\"\n+\n+/ {\n+\tmodel = \"Qualcomm Technologies, Inc. Lemans Draco EVK\";\n+\tcompatible = \"qcom,lemans-draco-evk\", \"qcom,qcs9100\",\n+\t\t     \"qcom,sa8775p\";\n+\tchassis-type = \"embedded\";\n+\n+\taliases {\n+\t\tethernet0 = \u0026ethernet0;\n+\t\tethernet1 = \u0026ethernet1;\n+\t};\n+\n+\tdp0-connector {\n+\t\tcompatible = \"dp-connector\";\n+\t\tlabel = \"DP0\";\n+\t\ttype = \"full-size\";\n+\n+\t\tdp-pwr-supply = \u003c\u0026vreg_dp0_pwr\u003e;\n+\n+\t\tport {\n+\t\t\tdp0_connector_in: endpoint {\n+\t\t\t\tremote-endpoint = \u003c\u0026mdss0_dp0_out\u003e;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tdp1-connector {\n+\t\tcompatible = \"dp-connector\";\n+\t\tlabel = \"DP1\";\n+\t\ttype = \"full-size\";\n+\n+\t\tdp-pwr-supply = \u003c\u0026vreg_dp1_pwr\u003e;\n+\n+\t\tport {\n+\t\t\tdp1_connector_in: endpoint {\n+\t\t\t\tremote-endpoint = \u003c\u0026mdss0_dp1_out\u003e;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tdp2-connector {\n+\t\tcompatible = \"dp-connector\";\n+\t\tlabel = \"DP2\";\n+\t\ttype = \"full-size\";\n+\n+\t\tdp-pwr-supply = \u003c\u0026vreg_dp2_pwr\u003e;\n+\n+\t\tport {\n+\t\t\tdp2_connector_in: endpoint {\n+\t\t\t\tremote-endpoint = \u003c\u0026mdss1_dp0_out\u003e;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tdp3-connector {\n+\t\tcompatible = \"dp-connector\";\n+\t\tlabel = \"DP3\";\n+\t\ttype = \"full-size\";\n+\n+\t\tdp-pwr-supply = \u003c\u0026vreg_dp3_pwr\u003e;\n+\n+\t\tport {\n+\t\t\tdp3_connector_in: endpoint {\n+\t\t\t\tremote-endpoint = \u003c\u0026mdss1_dp1_out\u003e;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tvreg_dp0_pwr: regulator-dp0-pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"VREG_DP0_PWR_3P3\";\n+\n+\t\tregulator-min-microvolt = \u003c3300000\u003e;\n+\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\n+\t\tgpio = \u003c\u0026expander1 7 GPIO_ACTIVE_HIGH\u003e;\n+\t};\n+\n+\tvreg_dp1_pwr: regulator-dp1-pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"VREG_DP1_PWR_3P3\";\n+\n+\t\tregulator-min-microvolt = \u003c3300000\u003e;\n+\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\n+\t\tgpio = \u003c\u0026expander1 8 GPIO_ACTIVE_HIGH\u003e;\n+\t};\n+\n+\tvreg_dp2_pwr: regulator-dp2-pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"VREG_DP2_PWR_3P3\";\n+\n+\t\tregulator-min-microvolt = \u003c3300000\u003e;\n+\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\n+\t\tgpio = \u003c\u0026expander1 9 GPIO_ACTIVE_HIGH\u003e;\n+\t};\n+\n+\tvreg_dp3_pwr: regulator-dp3-pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"VREG_DP3_PWR_3P3\";\n+\n+\t\tregulator-min-microvolt = \u003c3300000\u003e;\n+\t\tregulator-max-microvolt = \u003c3300000\u003e;\n+\n+\t\tgpio = \u003c\u0026expander1 10 GPIO_ACTIVE_HIGH\u003e;\n+\t};\n+};\n+\n+\u0026i2c2 {\n+\tstatus = \"okay\";\n+\n+\texpander0: gpio@20 {\n+\t\tcompatible = \"ti,tca6416\";\n+\t\treg = \u003c0x20\u003e;\n+\t\t#gpio-cells = \u003c2\u003e;\n+\t\tgpio-controller;\n+\t};\n+\n+\texpander1: gpio@21 {\n+\t\tcompatible = \"ti,tca6416\";\n+\t\treg = \u003c0x21\u003e;\n+\t\t#gpio-cells = \u003c2\u003e;\n+\t\tgpio-controller;\n+\t};\n+\n+\texpander2: gpio@22 {\n+\t\tcompatible = \"ti,tca6416\";\n+\t\treg = \u003c0x22\u003e;\n+\t\t#gpio-cells = \u003c2\u003e;\n+\t\tgpio-controller;\n+\t};\n+\n+\texpander3: gpio@23 {\n+\t\tcompatible = \"ti,tca6416\";\n+\t\treg = \u003c0x23\u003e;\n+\t\t#gpio-cells = \u003c2\u003e;\n+\t\tgpio-controller;\n+\t};\n+\n+\texpander4: gpio@38 {\n+\t\tcompatible = \"nxp,pca9534\";\n+\t\treg = \u003c0x38\u003e;\n+\t\t#gpio-cells = \u003c2\u003e;\n+\t\tgpio-controller;\n+\t};\n+};\n+\n+\u0026tlmm {\n+\n+\tdp2_hot_plug_det: dp2-hot-plug-det-state {\n+\t\tpins = \"gpio104\";\n+\t\tfunction = \"edp2_hot\";\n+\t\tbias-disable;\n+\t};\n+\n+\tdp3_hot_plug_det: dp3-hot-plug-det-state {\n+\t\tpins = \"gpio103\";\n+\t\tfunction = \"edp3_hot\";\n+\t\tbias-disable;\n+\t};\n+\n+\tethernet0_default: ethernet0-default-state {\n+\t\tethernet0_mdc: ethernet0-mdc-pins {\n+\t\t\tpins = \"gpio8\";\n+\t\t\tfunction = \"emac0_mdc\";\n+\t\t\tdrive-strength = \u003c16\u003e;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tethernet0_mdio: ethernet0-mdio-pins {\n+\t\t\tpins = \"gpio9\";\n+\t\t\tfunction = \"emac0_mdio\";\n+\t\t\tdrive-strength = \u003c16\u003e;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+\tethernet1_default: ethernet1-default-state {\n+\t\tethernet1_mdc: ethernet1-mdc-pins {\n+\t\t\tpins = \"gpio20\";\n+\t\t\tfunction = \"emac1_mdc\";\n+\t\t\tdrive-strength = \u003c16\u003e;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tethernet1_mdio: ethernet1-mdio-pins {\n+\t\t\tpins = \"gpio21\";\n+\t\t\tfunction = \"emac1_mdio\";\n+\t\t\tdrive-strength = \u003c16\u003e;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+};\n+\n+\u0026i2c18 {\n+\tstatus = \"okay\";\n+\n+\texpander5: gpio@3c {\n+\t\tcompatible = \"nxp,pca9534\";\n+\t\treg = \u003c0x3c\u003e;\n+\t\t#gpio-cells = \u003c2\u003e;\n+\t\tgpio-controller;\n+\t};\n+\n+\teeprom@50 {\n+\t\tcompatible = \"giantec,gt24c256c\", \"atmel,24c256\";\n+\t\treg = \u003c0x50\u003e;\n+\t\tpagesize = \u003c64\u003e;\n+\n+\t\tnvmem-layout {\n+\t\t\tcompatible = \"fixed-layout\";\n+\t\t\t#address-cells = \u003c1\u003e;\n+\t\t\t#size-cells = \u003c1\u003e;\n+\n+\t\t\tmac_addr0: mac-addr@0 {\n+\t\t\t\treg = \u003c0x0 0x6\u003e;\n+\t\t\t};\n+\n+\t\t\tmac_addr1: mac-addr@6 {\n+\t\t\t\treg = \u003c0x6 0x6\u003e;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+\u0026i2c4 {\n+\tstatus = \"okay\";\n+\n+\tfan_controller: fan@1a {\n+\t\tcompatible = \"ti,amc6821\";\n+\t\treg = \u003c0x1a\u003e;\n+\t\t#pwm-cells = \u003c2\u003e;\n+\n+\t\tfan {\n+\t\t\tpwms = \u003c\u0026fan_controller 40000 PWM_POLARITY_INVERTED\u003e;\n+\t\t};\n+\t};\n+};\n+\n+\u0026qup_i2c4_default {\n+\tdrive-strength = \u003c6\u003e;\n+\tbias-pull-up;\n+};\n+\n+\u0026spi16 {\n+\tstatus = \"okay\";\n+\n+\ttpm@0 {\n+\t\tcompatible = \"st,st33htpm-spi\", \"tcg,tpm_tis-spi\";\n+\t\treg = \u003c0\u003e;\n+\t\tspi-max-frequency = \u003c20000000\u003e;\n+\t};\n+};\n+\n+\u0026mdss0 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss0_dp0 {\n+\tpinctrl-0 = \u003c\u0026dp0_hot_plug_det\u003e;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss0_dp0_out {\n+\tdata-lanes = \u003c0 1 2 3\u003e;\n+\tlink-frequencies = /bits/ 64 \u003c1620000000 2700000000 5400000000 8100000000\u003e;\n+\n+\tremote-endpoint = \u003c\u0026dp0_connector_in\u003e;\n+};\n+\n+\u0026mdss0_dp0_phy {\n+\tvdda-phy-supply = \u003c\u0026vreg_l1c\u003e;\n+\tvdda-pll-supply = \u003c\u0026vreg_l4a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss0_dp1 {\n+\tpinctrl-0 = \u003c\u0026dp1_hot_plug_det\u003e;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss0_dp1_out {\n+\tdata-lanes = \u003c0 1 2 3\u003e;\n+\tlink-frequencies = /bits/ 64 \u003c1620000000 2700000000 5400000000 8100000000\u003e;\n+\n+\tremote-endpoint = \u003c\u0026dp1_connector_in\u003e;\n+};\n+\n+\u0026mdss0_dp1_phy {\n+\tvdda-phy-supply = \u003c\u0026vreg_l1c\u003e;\n+\tvdda-pll-supply = \u003c\u0026vreg_l4a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss1 {\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss1_dp0 {\n+\tpinctrl-0 = \u003c\u0026dp2_hot_plug_det\u003e;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss1_dp0_out {\n+\tdata-lanes = \u003c0 1 2 3\u003e;\n+\tlink-frequencies = /bits/ 64 \u003c1620000000 2700000000 5400000000 8100000000\u003e;\n+\n+\tremote-endpoint = \u003c\u0026dp2_connector_in\u003e;\n+};\n+\n+\u0026mdss1_dp0_phy {\n+\tvdda-phy-supply = \u003c\u0026vreg_l1c\u003e;\n+\tvdda-pll-supply = \u003c\u0026vreg_l4a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss1_dp1 {\n+\tpinctrl-0 = \u003c\u0026dp3_hot_plug_det\u003e;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026mdss1_dp1_out {\n+\tdata-lanes = \u003c0 1 2 3\u003e;\n+\tlink-frequencies = /bits/ 64 \u003c1620000000 2700000000 5400000000 8100000000\u003e;\n+\n+\tremote-endpoint = \u003c\u0026dp3_connector_in\u003e;\n+};\n+\n+\u0026mdss1_dp1_phy {\n+\tvdda-phy-supply = \u003c\u0026vreg_l1c\u003e;\n+\tvdda-pll-supply = \u003c\u0026vreg_l4a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026ethernet0 {\n+\tphy-handle = \u003c\u0026hsgmii_phy0\u003e;\n+\tphy-mode = \"2500base-x\";\n+\n+\tpinctrl-0 = \u003c\u0026ethernet0_default\u003e;\n+\tpinctrl-names = \"default\";\n+\n+\tsnps,mtl-rx-config = \u003c\u0026mtl_rx_setup\u003e;\n+\tsnps,mtl-tx-config = \u003c\u0026mtl_tx_setup\u003e;\n+\n+\tnvmem-cells = \u003c\u0026mac_addr0\u003e;\n+\tnvmem-cell-names = \"mac-address\";\n+\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\n+\t\thsgmii_phy0: ethernet-phy {\n+\t\t\tcompatible = \"ethernet-phy-id004d.d101\";\n+\t\t\treg = \u003c0x1c\u003e;\n+\t\t\treset-gpios = \u003c\u0026pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW\u003e;\n+\t\t\treset-assert-us = \u003c11000\u003e;\n+\t\t\treset-deassert-us = \u003c70000\u003e;\n+\t\t};\n+\t};\n+\n+\tmtl_rx_setup: rx-queues-config {\n+\t\tsnps,rx-queues-to-use = \u003c4\u003e;\n+\t\tsnps,rx-sched-sp;\n+\n+\t\tqueue0 {\n+\t\t\tsnps,dcb-algorithm;\n+\t\t\tsnps,map-to-dma-channel = \u003c0x0\u003e;\n+\t\t\tsnps,route-up;\n+\t\t\tsnps,priority = \u003c0x1\u003e;\n+\t\t};\n+\n+\t\tqueue1 {\n+\t\t\tsnps,dcb-algorithm;\n+\t\t\tsnps,map-to-dma-channel = \u003c0x1\u003e;\n+\t\t\tsnps,route-ptp;\n+\t\t};\n+\n+\t\tqueue2 {\n+\t\t\tsnps,avb-algorithm;\n+\t\t\tsnps,map-to-dma-channel = \u003c0x2\u003e;\n+\t\t\tsnps,route-avcp;\n+\t\t};\n+\n+\t\tqueue3 {\n+\t\t\tsnps,avb-algorithm;\n+\t\t\tsnps,map-to-dma-channel = \u003c0x3\u003e;\n+\t\t\tsnps,priority = \u003c0xc\u003e;\n+\t\t};\n+\t};\n+\n+\tmtl_tx_setup: tx-queues-config {\n+\t\tsnps,tx-queues-to-use = \u003c4\u003e;\n+\n+\t\tqueue0 {\n+\t\t\tsnps,dcb-algorithm;\n+\t\t};\n+\n+\t\tqueue1 {\n+\t\t\tsnps,dcb-algorithm;\n+\t\t};\n+\n+\t\tqueue2 {\n+\t\t\tsnps,avb-algorithm;\n+\t\t\tsnps,send_slope = \u003c0x1000\u003e;\n+\t\t\tsnps,idle_slope = \u003c0x1000\u003e;\n+\t\t\tsnps,high_credit = \u003c0x3e800\u003e;\n+\t\t\tsnps,low_credit = \u003c0xffc18000\u003e;\n+\t\t};\n+\n+\t\tqueue3 {\n+\t\t\tsnps,avb-algorithm;\n+\t\t\tsnps,send_slope = \u003c0x1000\u003e;\n+\t\t\tsnps,idle_slope = \u003c0x1000\u003e;\n+\t\t\tsnps,high_credit = \u003c0x3e800\u003e;\n+\t\t\tsnps,low_credit = \u003c0xffc18000\u003e;\n+\t\t};\n+\t};\n+};\n+\n+\u0026ethernet1 {\n+\tphy-handle = \u003c\u0026hsgmii_phy1\u003e;\n+\tphy-mode = \"2500base-x\";\n+\n+\tpinctrl-0 = \u003c\u0026ethernet1_default\u003e;\n+\tpinctrl-names = \"default\";\n+\n+\tsnps,mtl-rx-config = \u003c\u0026mtl_rx_setup1\u003e;\n+\tsnps,mtl-tx-config = \u003c\u0026mtl_tx_setup1\u003e;\n+\n+\tnvmem-cells = \u003c\u0026mac_addr1\u003e;\n+\tnvmem-cell-names = \"mac-address\";\n+\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t#address-cells = \u003c1\u003e;\n+\t\t#size-cells = \u003c0\u003e;\n+\n+\t\thsgmii_phy1: ethernet-phy {\n+\t\t\tcompatible = \"ethernet-phy-id004d.d101\";\n+\t\t\treg = \u003c0x1c\u003e;\n+\t\t\treset-gpios = \u003c\u0026pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW\u003e;\n+\t\t\treset-assert-us = \u003c11000\u003e;\n+\t\t\treset-deassert-us = \u003c70000\u003e;\n+\t\t};\n+\t};\n+\n+\tmtl_rx_setup1: rx-queues-config {\n+\t\tsnps,rx-queues-to-use = \u003c4\u003e;\n+\t\tsnps,rx-sched-sp;\n+\n+\t\tqueue0 {\n+\t\t\tsnps,dcb-algorithm;\n+\t\t\tsnps,map-to-dma-channel = \u003c0x0\u003e;\n+\t\t\tsnps,route-up;\n+\t\t\tsnps,priority = \u003c0x1\u003e;\n+\t\t};\n+\n+\t\tqueue1 {\n+\t\t\tsnps,dcb-algorithm;\n+\t\t\tsnps,map-to-dma-channel = \u003c0x1\u003e;\n+\t\t\tsnps,route-ptp;\n+\t\t};\n+\n+\t\tqueue2 {\n+\t\t\tsnps,avb-algorithm;\n+\t\t\tsnps,map-to-dma-channel = \u003c0x2\u003e;\n+\t\t\tsnps,route-avcp;\n+\t\t};\n+\n+\t\tqueue3 {\n+\t\t\tsnps,avb-algorithm;\n+\t\t\tsnps,map-to-dma-channel = \u003c0x3\u003e;\n+\t\t\tsnps,priority = \u003c0xc\u003e;\n+\t\t};\n+\t};\n+\n+\tmtl_tx_setup1: tx-queues-config {\n+\t\tsnps,tx-queues-to-use = \u003c4\u003e;\n+\n+\t\tqueue0 {\n+\t\t\tsnps,dcb-algorithm;\n+\t\t};\n+\n+\t\tqueue1 {\n+\t\t\tsnps,dcb-algorithm;\n+\t\t};\n+\n+\t\tqueue2 {\n+\t\t\tsnps,avb-algorithm;\n+\t\t\tsnps,send_slope = \u003c0x1000\u003e;\n+\t\t\tsnps,idle_slope = \u003c0x1000\u003e;\n+\t\t\tsnps,high_credit = \u003c0x3e800\u003e;\n+\t\t\tsnps,low_credit = \u003c0xffc18000\u003e;\n+\t\t};\n+\n+\t\tqueue3 {\n+\t\t\tsnps,avb-algorithm;\n+\t\t\tsnps,send_slope = \u003c0x1000\u003e;\n+\t\t\tsnps,idle_slope = \u003c0x1000\u003e;\n+\t\t\tsnps,high_credit = \u003c0x3e800\u003e;\n+\t\t\tsnps,low_credit = \u003c0xffc18000\u003e;\n+\t\t};\n+\t};\n+};\n+\n+\u0026serdes0 {\n+\tphy-supply = \u003c\u0026vreg_l5a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n+\n+\u0026serdes1 {\n+\tphy-supply = \u003c\u0026vreg_l5a\u003e;\n+\n+\tstatus = \"okay\";\n+};\n"
}
2/1 2026/10/19 10:54 agent patch-evaluator
0m Model: 
core

Args: 
null

Results: 
{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies only Device Tree documentation and ARM64 DTS files (arch/arm64/boot/dts/qcom/) for the Qualcomm Lemans Draco EVK board. These changes do not modify executable kernel C code and are specific to arm64 hardware, making them completely unreachable on the target amd64 architecture.",
  "WorthFuzzing": false
}

Instruction: 
You are an expert Linux kernel maintainer and security engineer.
Your job is to review a provided patch series and evaluate whether it warrants fuzzing with syzkaller.

IMPORTANT: The changes have ALREADY been applied and committed as the HEAD commit in
your workspace. Do NOT rely on internal assumptions. You must actively use your code access
tools to inspect the actual source code, callers, and surrounding context.

================================================================================
1. CORE TRIAGE PHILOSOPHY
================================================================================
The goal of patch fuzzing is to discover crashes, regressions, exposed latent bugs,
and newly triggered assertions introduced by the patch series.

- REACHABILITY IS THE PRIMARY GATE:
  Fuzzing can only discover bugs in code that can actually execute in standard virtualized
  environments (GCE or QEMU, utilizing software-emulated devices like USB gadgets, netdev, tun/tap).
  If the modified code is structurally unreachable (see Section 2), it MUST NOT be fuzzed,
  regardless of whether it adds assertions or complex logic.

- DO NOT BLINDLY TRUST "NO FUNCTIONAL CHANGE" (NFCI) OR "REFACTORING" CLAIMS:
  Patch authors routinely label changes as "cleanups", "refactorings", or state
  "No functional change intended". Do NOT take these claims at face value.
  Code refactorings that rearrange logic, introduce helper functions, or alter state management
  in core subsystems frequently introduce subtle semantic shifts or uncover latent kernel bugs.
  If reachable executable code is modified or refactored, it MUST be fuzzed.

- NEW OR MODIFIED ASSERTIONS IN REACHABLE CODE MUST BE FUZZED:
  When a patch introduces or modifies runtime checks or assertions (e.g., WARN_ON*, VM_WARN_ON*,
  BUG_ON*, lockdep_assert*) in reachable code paths, it enforces new or stricter invariants.
  Even if the author believes the invariant always holds, fuzzing is essential to verify whether
  an unusual sequence of operations can violate it.

================================================================================
2. WHEN TO RETURN WorthFuzzing=false (NEGATIVE CRITERIA)
================================================================================
Return WorthFuzzing=false ONLY IF all modified code falls strictly into one or more of these categories:

- Non-kernel and non-executable changes:
  * Modifications to Documentation/, comments, or spelling fixes.
  * User-space directories, self-tests, samples, or scripts (e.g., tools/, samples/, scripts/, usr/)
    that do not affect the compiled kernel image (vmlinux) or kernel modules.
  * Purely decorative logging (e.g., message strings in pr_err, printk, dev_info) or tracepoints
    that do not alter control flow or data structures.
  * Build system or Kconfig changes that do not alter compiled C logic.
- Structurally unreachable hardware:
  * Vendor-specific PCIe switches, SmartNICs, or GPU drivers (e.g., mlxsw, pds_core, qed,
    ionic, amdgpu) requiring physical ASIC/PCIe cards not emulated in standard QEMU.
- Unreachable execution paths:
  * Driver teardown callbacks (.remove, .shutdown, pci_unregister_driver) executed only during
    physical PCI hot-unplug or manual sysfs driver unbinding.
  * Code paths exclusive to architectures other than the target architecture.

================================================================================
3. WHEN TO RETURN WorthFuzzing=true (POSITIVE CRITERIA)
================================================================================
Return WorthFuzzing=true whenever the patch touches reachable executable code, including:
- Core Subsystems:
  * Any logic modifications in memory management (mm/), synchronization/locking (kernel/locking/),
    BPF, scheduler, core networking, VFS, or syscall handling.
- Refactorings and Code Cleanups:
  * Any restructuring of reachable data structures, helper abstractions, or algorithm flows.
- Runtime Assertions and Defensive Checks:
  * Any introduction or alteration of assertions (WARN_ON*, VM_WARN_ON*, BUG_ON*, etc.) in reachable paths.
- Reachable Drivers and Protocols:
  * Drivers accessible via virtual buses (virtio, USB gadget, loopback, netlink, binder, sockets, etc.).

================================================================================
4. EXTRACTING FocusSymbols (PREVENTING DILUTION)
================================================================================
When WorthFuzzing=true, you must extract specific kernel functions into FocusSymbols to guide the fuzzer:

- AVOID UBIQUITOUS LIFECYCLE HOT-PATHS:
  Do NOT list generic, ubiquitous functions called by almost every program in the corpus
  (including, but not limited to: general memory allocators and deallocators, page fault
  and trap handlers, or core synchronization primitives; this is not an exhaustive list).
  Listing ubiquitous functions causes the fuzzer to classify thousands of unrelated tests as "focused",
  which severely dilutes fuzzing effort away from the actual changes.

- TARGET SPECIFIC FEATURE LOGIC AND ENTRYPOINTS:
  List functions that specifically implement the logic being added or altered, or direct API entrypoints
  for the subsystem feature under review.

- HANDLING STATIC INLINE FUNCTIONS IN HEADERS (.h):
  Compiler-inlined static functions (such as static inlines in mm/*.h or include/linux/*.h) lack
  distinct symbol addresses in vmlinux and cannot be targeted directly by symbol coverage filters.
  If the changes are primarily in static inline helpers, identify non-static, feature-specific caller
  functions in .c files that exercise them (avoiding ubiquitous lifecycle wrappers).

================================================================================
5. IDENTIFYING EnableConfigs
================================================================================
Identify any specific CONFIG_ options required to properly compile and reach the modified code:
- Inspect Kconfig files and #ifdef guards; do not make assumptions.
- Check "depends on" lines in Kconfig to include any non-standard parent subsystem configs needed.
- Strip any 'CONFIG_' prefix (e.g., return "NET_IPV4" instead of "CONFIG_NET_IPV4").
Prefer calling several tools at the same time to save round-trips.


Use set-results tool to provide results of the analysis.
It must be called exactly once before the final reply.
Ignore results of this tool.

Prompt: 
Target architecture: amd64

For your convenience, here is the diff of the changes:
commit fd388684dabce6991ed220011eb45c959fa06792
Author: syz-cluster <triage@syzkaller.com>
Date:   Mon Oct 19 10:54:28 2026 +0000

    syz-cluster: applied patch under review

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 07ef7988b0683..1efd6ea34c3f1 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -498,6 +498,7 @@ properties:
       - items:
           - enum:
               - qcom,lemans-evk
+              - qcom,lemans-draco-evk
               - qcom,qcs9100-ride
               - qcom,qcs9100-ride-r3
           - const: qcom,qcs9100
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4e714251d5e6b..f1713d53af5f6 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -50,6 +50,11 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq9650-rdp488.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= kaanapali-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= kaanapali-qrd.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= lemans-evk.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-draco-evk.dtb
+
+lemans-draco-evk-el2-dtbs := lemans-draco-evk.dtb lemans-el2.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-draco-evk-el2.dtb
 
 lemans-evk-camera-csi1-imx577-dtbs	:= lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
 lemans-evk-camera-dtbs	:= lemans-evk.dtb lemans-evk-camera.dtbo
diff --git a/arch/arm64/boot/dts/qcom/lemans-draco-evk-som.dtsi b/arch/arm64/boot/dts/qcom/lemans-draco-evk-som.dtsi
new file mode 100644
index 0000000000000..6b7971bcdc934
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/lemans-draco-evk-som.dtsi
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "lemans.dtsi"
+#include "lemans-pmics.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart10;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s4a: smps4 {
+			regulator-name = "vreg_s4a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1816000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5a: smps5 {
+			regulator-name = "vreg_s5a";
+			regulator-min-microvolt = <1850000>;
+			regulator-max-microvolt = <1996000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s9a: smps9 {
+			regulator-name = "vreg_s9a";
+			regulator-min-microvolt = <535000>;
+			regulator-max-microvolt = <1120000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4a: ldo4 {
+			regulator-name = "vreg_l4a";
+			regulator-min-microvolt = <788000>;
+			regulator-max-microvolt = <1050000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5a: ldo5 {
+			regulator-name = "vreg_l5a";
+			regulator-min-microvolt = <870000>;
+			regulator-max-microvolt = <950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6a: ldo6 {
+			regulator-name = "vreg_l6a";
+			regulator-min-microvolt = <870000>;
+			regulator-max-microvolt = <970000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a: ldo7 {
+			regulator-name = "vreg_l7a";
+			regulator-min-microvolt = <720000>;
+			regulator-max-microvolt = <950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a: ldo8 {
+			regulator-name = "vreg_l8a";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9a: ldo9 {
+			regulator-name = "vreg_l9a";
+			regulator-min-microvolt = <2970000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <1140000>;
+			regulator-max-microvolt = <1260000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c: ldo2 {
+			regulator-name = "vreg_l2c";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c: ldo3 {
+			regulator-name = "vreg_l3c";
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4c: ldo4 {
+			regulator-name = "vreg_l4c";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5c: ldo5 {
+			regulator-name = "vreg_l5c";
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6c: ldo6 {
+			regulator-name = "vreg_l6c";
+			regulator-min-microvolt = <1620000>;
+			regulator-max-microvolt = <1980000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7c: ldo7 {
+			regulator-name = "vreg_l7c";
+			regulator-min-microvolt = <1620000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <2400000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9c: ldo9 {
+			regulator-name = "vreg_l9c";
+			regulator-min-microvolt = <1650000>;
+			regulator-max-microvolt = <2700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vreg_s4e: smps4 {
+			regulator-name = "vreg_s4e";
+			regulator-min-microvolt = <970000>;
+			regulator-max-microvolt = <1520000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s7e: smps7 {
+			regulator-name = "vreg_s7e";
+			regulator-min-microvolt = <1010000>;
+			regulator-max-microvolt = <1170000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s9e: smps9 {
+			regulator-name = "vreg_s9e";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <570000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6e: ldo6 {
+			regulator-name = "vreg_l6e";
+			regulator-min-microvolt = <1280000>;
+			regulator-max-microvolt = <1450000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8e: ldo8 {
+			regulator-name = "vreg_l8e";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gpu {
+	status = "okay";
+};
+
+&gpu_zap_shader {
+	firmware-name = "qcom/sa8775p/a663_zap.mbn";
+};
+
+&iris {
+	firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn";
+
+	status = "okay";
+};
+
+&pmm8654au_0_pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&qupv3_id_0 {
+	firmware-name = "qcom/sa8775p/qupv3fw.elf";
+
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	firmware-name = "qcom/sa8775p/qupv3fw.elf";
+
+	status = "okay";
+};
+
+&qupv3_id_2 {
+	firmware-name = "qcom/sa8775p/qupv3fw.elf";
+
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sa8775p/adsp.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp0 {
+	firmware-name = "qcom/sa8775p/cdsp0.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp1 {
+	firmware-name = "qcom/sa8775p/cdsp1.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_gpdsp0 {
+	firmware-name = "qcom/sa8775p/gpdsp0.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_gpdsp1 {
+	firmware-name = "qcom/sa8775p/gpdsp1.mbn";
+
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32768>;
+};
+
+&uart10 {
+	compatible = "qcom,geni-debug-uart";
+	pinctrl-0 = <&qup_uart10_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l8a>;
+	vcc-max-microamp = <1100000>;
+	vccq-supply = <&vreg_l4c>;
+	vccq-max-microamp = <1200000>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l4a>;
+	vdda-pll-supply = <&vreg_l1c>;
+
+	status = "okay";
+};
+
+&usb_0 {
+	status = "okay";
+};
+
+&usb_0_hsphy {
+	vdda-pll-supply = <&vreg_l7a>;
+	vdda18-supply = <&vreg_l6c>;
+	vdda33-supply = <&vreg_l9a>;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l7a>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	dr_mode = "host";
+
+	status = "okay";
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l7a>;
+	vdda18-supply = <&vreg_l6c>;
+	vdda33-supply = <&vreg_l9a>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l7a>;
+
+	status = "okay";
+};
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_hsphy {
+	vdda-pll-supply = <&vreg_l7a>;
+	vdda18-supply = <&vreg_l6c>;
+	vdda33-supply = <&vreg_l9a>;
+
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/lemans-draco-evk.dts b/arch/arm64/boot/dts/qcom/lemans-draco-evk.dts
new file mode 100644
index 0000000000000..5238157ad0029
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/lemans-draco-evk.dts
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include "lemans-draco-evk-som.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans Draco EVK";
+	compatible = "qcom,lemans-draco-evk", "qcom,qcs9100",
+		     "qcom,sa8775p";
+	chassis-type = "embedded";
+
+	aliases {
+		ethernet0 = &ethernet0;
+		ethernet1 = &ethernet1;
+	};
+
+	dp0-connector {
+		compatible = "dp-connector";
+		label = "DP0";
+		type = "full-size";
+
+		dp-pwr-supply = <&vreg_dp0_pwr>;
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&mdss0_dp0_out>;
+			};
+		};
+	};
+
+	dp1-connector {
+		compatible = "dp-connector";
+		label = "DP1";
+		type = "full-size";
+
+		dp-pwr-supply = <&vreg_dp1_pwr>;
+
+		port {
+			dp1_connector_in: endpoint {
+				remote-endpoint = <&mdss0_dp1_out>;
+			};
+		};
+	};
+
+	dp2-connector {
+		compatible = "dp-connector";
+		label = "DP2";
+		type = "full-size";
+
+		dp-pwr-supply = <&vreg_dp2_pwr>;
+
+		port {
+			dp2_connector_in: endpoint {
+				remote-endpoint = <&mdss1_dp0_out>;
+			};
+		};
+	};
+
+	dp3-connector {
+		compatible = "dp-connector";
+		label = "DP3";
+		type = "full-size";
+
+		dp-pwr-supply = <&vreg_dp3_pwr>;
+
+		port {
+			dp3_connector_in: endpoint {
+				remote-endpoint = <&mdss1_dp1_out>;
+			};
+		};
+	};
+
+	vreg_dp0_pwr: regulator-dp0-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "VREG_DP0_PWR_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
+	};
+
+	vreg_dp1_pwr: regulator-dp1-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "VREG_DP1_PWR_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&expander1 8 GPIO_ACTIVE_HIGH>;
+	};
+
+	vreg_dp2_pwr: regulator-dp2-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "VREG_DP2_PWR_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&expander1 9 GPIO_ACTIVE_HIGH>;
+	};
+
+	vreg_dp3_pwr: regulator-dp3-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "VREG_DP3_PWR_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&expander1 10 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	expander0: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	expander1: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	expander2: gpio@22 {
+		compatible = "ti,tca6416";
+		reg = <0x22>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	expander3: gpio@23 {
+		compatible = "ti,tca6416";
+		reg = <0x23>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	expander4: gpio@38 {
+		compatible = "nxp,pca9534";
+		reg = <0x38>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+};
+
+&tlmm {
+
+	dp2_hot_plug_det: dp2-hot-plug-det-state {
+		pins = "gpio104";
+		function = "edp2_hot";
+		bias-disable;
+	};
+
+	dp3_hot_plug_det: dp3-hot-plug-det-state {
+		pins = "gpio103";
+		function = "edp3_hot";
+		bias-disable;
+	};
+
+	ethernet0_default: ethernet0-default-state {
+		ethernet0_mdc: ethernet0-mdc-pins {
+			pins = "gpio8";
+			function = "emac0_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		ethernet0_mdio: ethernet0-mdio-pins {
+			pins = "gpio9";
+			function = "emac0_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+
+	ethernet1_default: ethernet1-default-state {
+		ethernet1_mdc: ethernet1-mdc-pins {
+			pins = "gpio20";
+			function = "emac1_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		ethernet1_mdio: ethernet1-mdio-pins {
+			pins = "gpio21";
+			function = "emac1_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+
+};
+
+&i2c18 {
+	status = "okay";
+
+	expander5: gpio@3c {
+		compatible = "nxp,pca9534";
+		reg = <0x3c>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	eeprom@50 {
+		compatible = "giantec,gt24c256c", "atmel,24c256";
+		reg = <0x50>;
+		pagesize = <64>;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mac_addr0: mac-addr@0 {
+				reg = <0x0 0x6>;
+			};
+
+			mac_addr1: mac-addr@6 {
+				reg = <0x6 0x6>;
+			};
+		};
+	};
+};
+
+&i2c4 {
+	status = "okay";
+
+	fan_controller: fan@1a {
+		compatible = "ti,amc6821";
+		reg = <0x1a>;
+		#pwm-cells = <2>;
+
+		fan {
+			pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
+		};
+	};
+};
+
+&qup_i2c4_default {
+	drive-strength = <6>;
+	bias-pull-up;
+};
+
+&spi16 {
+	status = "okay";
+
+	tpm@0 {
+		compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&mdss0 {
+	status = "okay";
+};
+
+&mdss0_dp0 {
+	pinctrl-0 = <&dp0_hot_plug_det>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdss0_dp0_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+	remote-endpoint = <&dp0_connector_in>;
+};
+
+&mdss0_dp0_phy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+
+	status = "okay";
+};
+
+&mdss0_dp1 {
+	pinctrl-0 = <&dp1_hot_plug_det>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdss0_dp1_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+	remote-endpoint = <&dp1_connector_in>;
+};
+
+&mdss0_dp1_phy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+
+	status = "okay";
+};
+
+&mdss1 {
+	status = "okay";
+};
+
+&mdss1_dp0 {
+	pinctrl-0 = <&dp2_hot_plug_det>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdss1_dp0_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+	remote-endpoint = <&dp2_connector_in>;
+};
+
+&mdss1_dp0_phy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+
+	status = "okay";
+};
+
+&mdss1_dp1 {
+	pinctrl-0 = <&dp3_hot_plug_det>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdss1_dp1_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+	remote-endpoint = <&dp3_connector_in>;
+};
+
+&mdss1_dp1_phy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+
+	status = "okay";
+};
+
+&ethernet0 {
+	phy-handle = <&hsgmii_phy0>;
+	phy-mode = "2500base-x";
+
+	pinctrl-0 = <&ethernet0_default>;
+	pinctrl-names = "default";
+
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+
+	nvmem-cells = <&mac_addr0>;
+	nvmem-cell-names = "mac-address";
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		hsgmii_phy0: ethernet-phy {
+			compatible = "ethernet-phy-id004d.d101";
+			reg = <0x1c>;
+			reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
+&ethernet1 {
+	phy-handle = <&hsgmii_phy1>;
+	phy-mode = "2500base-x";
+
+	pinctrl-0 = <&ethernet1_default>;
+	pinctrl-names = "default";
+
+	snps,mtl-rx-config = <&mtl_rx_setup1>;
+	snps,mtl-tx-config = <&mtl_tx_setup1>;
+
+	nvmem-cells = <&mac_addr1>;
+	nvmem-cell-names = "mac-address";
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		hsgmii_phy1: ethernet-phy {
+			compatible = "ethernet-phy-id004d.d101";
+			reg = <0x1c>;
+			reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+
+	mtl_rx_setup1: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup1: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
+&serdes0 {
+	phy-supply = <&vreg_l5a>;
+
+	status = "okay";
+};
+
+&serdes1 {
+	phy-supply = <&vreg_l5a>;
+
+	status = "okay";
+};

3/2 2026/10/19 10:54 llm patch-evaluator
0m Model: 
gemini-3.8-flash

Args: 
null

Results: 
null

Tokens: 
							input: 13710
							output: 99
							thoughts: 573

Thoughts: 
**Analyzing the Patch for Fuzzing Suitability**

Okay, let's break this down. First, the diff targets: `Documentation/devicetree/bindings/arm/qcom.yaml`, the `Makefile` and several `.dtsi` and `.dts` files within `arch/arm64/boot/dts/qcom/`. Right away, I'm noting that these are heavily focused on devicetree bindings and hardware description for Qualcomm ARM64 platforms, specifically the Lemans Draco EVK board. The target architecture, however, is `amd64`.

Considering the "WHEN TO RETURN WorthFuzzing=false" criteria, this screams "not fuzzable" to me. All the changes fall squarely into the categories of non-executable documentation (the YAML file) and devicetree sources which are specific hardware descriptions and are architecture-dependent.

1.  These files are *exclusively* documentation and device tree descriptions. They are not executable code.
2.  The files are specific to the `arm64` architecture, while we're targeting `amd64`. This means this code is unreachable in our current context.
3.  The changes pertain to a specific Qualcomm hardware platform (Lemans Draco EVK), and are specific to that hardware and aren't applicable on the target architecture.

Therefore, this patch doesn't touch any reachable, executable code on `amd64`, or likely any code relevant for kernel fuzzing in the general sense. The "WorthFuzzing" flag *has* to be `false` here.

Let me double-check:
*   `WorthFuzzing`: `false`
*   `EnableConfigs`: `[]` (empty)
*   `FocusSymbols`: `[]` (empty)
*   `Reasoning`: Concise explanation provided above.

Now, let's set up that `set-results` call.

4/2 2026/10/19 10:54 tool set-results
0m Args: 
{
  "EnableConfigs": [],
  "FocusSymbols": [],
  "Reasoning": "The patch modifies only Device Tree documentation and ARM64 DTS files (arch/arm64/boot/dts/qcom/) for the Qualcomm Lemans Draco EVK board. These changes do not modify executable kernel C code and are specific to arm64 hardware, making them completely unreachable on the target amd64 architecture.",
  "WorthFuzzing": false
}

Results: 
{
  "EnableConfigs": null,
  "FocusSymbols": [],
  "Reasoning": "The patch modifies only Device Tree documentation and ARM64 DTS files (arch/arm64/boot/dts/qcom/) for the Qualcomm Lemans Draco EVK board. These changes do not modify executable kernel C code and are specific to arm64 hardware, making them completely unreachable on the target amd64 architecture.",
  "WorthFuzzing": false
}
5/1 2026/10/19 10:54 action If
0m Args: 
{
  "WorthFuzzing": false
}

Results: 
null
LLM Calls Summary:
Total Calls Total Tokens Avg Tokens Total Duration (Seconds) Avg Duration (Seconds)
Tool Calls Summary:
Total Calls Total Duration (Seconds) Avg Duration (Seconds)