Add new compatible string and clock definitions for the Ethernet MAC IP found in MT8189 SoC. Signed-off-by: Louis-Alexis Eyraud --- .../devicetree/bindings/net/mediatek-dwmac.yaml | 77 +++++++++++++++------- 1 file changed, 54 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml index 3aab21b8e8de..000abec023b3 100644 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml @@ -20,13 +20,11 @@ select: enum: - mediatek,mt2712-gmac - mediatek,mt8188-gmac + - mediatek,mt8189-gmac - mediatek,mt8195-gmac required: - compatible -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: @@ -36,6 +34,7 @@ properties: - const: snps,dwmac-4.20a - items: - enum: + - mediatek,mt8189-gmac - mediatek,mt8195-gmac - const: snps,dwmac-5.10a - items: @@ -44,26 +43,6 @@ properties: - const: mediatek,mt8195-gmac - const: snps,dwmac-5.10a - clocks: - minItems: 5 - items: - - description: AXI clock - - description: APB clock - - description: MAC Main clock - - description: PTP clock - - description: RMII reference clock provided by MAC - - description: MAC clock gate - - clock-names: - minItems: 5 - items: - - const: axi - - const: apb - - const: mac_main - - const: ptp_ref - - const: rmii_internal - - const: mac_cg - interrupts: maxItems: 1 @@ -147,6 +126,58 @@ required: - phy-mode - mediatek,pericfg +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2712-gmac + - mediatek,mt8188-gmac + - mediatek,mt8195-gmac + then: + properties: + clocks: + minItems: 5 + items: + - description: AXI clock + - description: APB clock + - description: MAC Main clock + - description: PTP clock + - description: RMII reference clock provided by MAC + - description: MAC clock gate + + clock-names: + minItems: 5 + items: + - const: axi + - const: apb + - const: mac_main + - const: ptp_ref + - const: rmii_internal + - const: mac_cg + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8189-gmac + then: + properties: + clocks: + items: + - description: MAC Main clock + - description: PTP clock + - description: RMII reference clock provided by MAC + + clock-names: + items: + - const: mac_main + - const: ptp_ref + - const: rmii_internal + unevaluatedProperties: false examples: -- 2.55.0 In preparation of newer SoC support, that use like MT8195 the Ethernet control registers from the peripheral configuration syscon but at a different base offset, add a new base offset in the variant platform data to access the PERI_ETH_CTRLx registers and use it in implemented methods. Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 28 +++++++++++++++------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 30ae0dba7fff..0cabab4fd89a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -37,7 +37,9 @@ #define ETH_FINE_DLY_RXC BIT(0) /* Peri Configuration register for mt8195 */ -#define MT8195_PERI_ETH_CTRL0 0xFD0 +#define MT8195_PERI_ETH_CTRL_BASE 0xFD0 + +#define MT8195_PERI_ETH_CTRL0 0x0 #define MT8195_RMII_CLK_SRC_INTERNAL BIT(28) #define MT8195_RMII_CLK_SRC_RXC BIT(27) #define MT8195_ETH_INTF_SEL GENMASK(26, 24) @@ -47,7 +49,7 @@ #define MT8195_DLY_GTXC_ENABLE BIT(5) #define MT8195_DLY_GTXC_STAGES GENMASK(4, 0) -#define MT8195_PERI_ETH_CTRL1 0xFD4 +#define MT8195_PERI_ETH_CTRL1 0x4 #define MT8195_DLY_RXC_INV BIT(25) #define MT8195_DLY_RXC_ENABLE BIT(18) #define MT8195_DLY_RXC_STAGES GENMASK(17, 13) @@ -55,7 +57,7 @@ #define MT8195_DLY_TXC_ENABLE BIT(5) #define MT8195_DLY_TXC_STAGES GENMASK(4, 0) -#define MT8195_PERI_ETH_CTRL2 0xFD8 +#define MT8195_PERI_ETH_CTRL2 0x8 #define MT8195_DLY_RMII_RXC_INV BIT(25) #define MT8195_DLY_RMII_RXC_ENABLE BIT(18) #define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13) @@ -95,6 +97,7 @@ struct mediatek_dwmac_variant { u32 rx_delay_max; u32 tx_delay_max; + u32 peri_eth_ctrl_offset; u8 dma_bit_mask; }; @@ -277,6 +280,7 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, u8 phy_intf_sel) { u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel); + u32 reg_offset = plat->variant->peri_eth_ctrl_offset; if (phy_intf_sel == PHY_INTF_SEL_RMII) { if (plat->rmii_clk_from_mac) @@ -288,7 +292,9 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, /* MT8195 only support external PHY */ intf_val |= MT8195_EXT_PHY_MODE; - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL0, + intf_val); return 0; } @@ -313,8 +319,9 @@ static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) { - struct mac_delay_struct *mac_delay = &plat->mac_delay; u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0; + struct mac_delay_struct *mac_delay = &plat->mac_delay; + u32 reg_offset = plat->variant->peri_eth_ctrl_offset; mt8195_delay_ps2stage(plat); @@ -399,14 +406,18 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) } regmap_update_bits(plat->peri_regmap, - MT8195_PERI_ETH_CTRL0, + reg_offset + MT8195_PERI_ETH_CTRL0, MT8195_RGMII_TXC_PHASE_CTRL | MT8195_DLY_GTXC_INV | MT8195_DLY_GTXC_ENABLE | MT8195_DLY_GTXC_STAGES, gtxc_delay_val); - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL1, + delay_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL2, + rmii_delay_val); mt8195_delay_stage2ps(plat); @@ -421,6 +432,7 @@ static const struct mediatek_dwmac_variant mt8195_gmac_variant = { .rx_delay_max = 9280, .tx_delay_max = 9280, .dma_bit_mask = 35, + .peri_eth_ctrl_offset = MT8195_PERI_ETH_CTRL_BASE, }; static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) -- 2.55.0 In preparation of newer SoC support, rename MT2712 and MT8195 variant methods and sub functions to more generic names. Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 32 +++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 0cabab4fd89a..28e87990b0a1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -110,7 +110,7 @@ static const char * const mt8195_dwmac_clk_l[] = { "axi", "apb", "mac_cg", "mac_main", "ptp_ref" }; -static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat, +static int set_phy_interface_v1(struct mediatek_dwmac_plat_data *plat, u8 phy_intf_sel) { u32 intf_val = phy_intf_sel; @@ -127,7 +127,7 @@ static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat, return 0; } -static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) +static void delay_ps2stage_v1(struct mediatek_dwmac_plat_data *plat) { struct mac_delay_struct *mac_delay = &plat->mac_delay; @@ -152,7 +152,7 @@ static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) } } -static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) +static void delay_stage2ps_v1(struct mediatek_dwmac_plat_data *plat) { struct mac_delay_struct *mac_delay = &plat->mac_delay; @@ -177,12 +177,12 @@ static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) } } -static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat) +static int set_delay_v1(struct mediatek_dwmac_plat_data *plat) { struct mac_delay_struct *mac_delay = &plat->mac_delay; u32 delay_val = 0, fine_val = 0; - mt2712_delay_ps2stage(plat); + delay_ps2stage_v1(plat); switch (plat->phy_mode) { case PHY_INTERFACE_MODE_MII: @@ -261,14 +261,14 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat) regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val); regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val); - mt2712_delay_stage2ps(plat); + delay_stage2ps_v1(plat); return 0; } static const struct mediatek_dwmac_variant mt2712_gmac_variant = { - .dwmac_set_phy_interface = mt2712_set_interface, - .dwmac_set_delay = mt2712_set_delay, + .dwmac_set_phy_interface = set_phy_interface_v1, + .dwmac_set_delay = set_delay_v1, .clk_list = mt2712_dwmac_clk_l, .num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l), .rx_delay_max = 17600, @@ -276,7 +276,7 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = { .dma_bit_mask = 33, }; -static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, +static int set_phy_interface_v2(struct mediatek_dwmac_plat_data *plat, u8 phy_intf_sel) { u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel); @@ -299,7 +299,7 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, return 0; } -static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) +static void delay_ps2stage_v2(struct mediatek_dwmac_plat_data *plat) { struct mac_delay_struct *mac_delay = &plat->mac_delay; @@ -308,7 +308,7 @@ static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) mac_delay->rx_delay /= 290; } -static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) +static void delay_stage2ps_v2(struct mediatek_dwmac_plat_data *plat) { struct mac_delay_struct *mac_delay = &plat->mac_delay; @@ -317,13 +317,13 @@ static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) mac_delay->rx_delay *= 290; } -static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) +static int set_delay_v2(struct mediatek_dwmac_plat_data *plat) { u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0; struct mac_delay_struct *mac_delay = &plat->mac_delay; u32 reg_offset = plat->variant->peri_eth_ctrl_offset; - mt8195_delay_ps2stage(plat); + delay_ps2stage_v2(plat); switch (plat->phy_mode) { case PHY_INTERFACE_MODE_MII: @@ -419,14 +419,14 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) reg_offset + MT8195_PERI_ETH_CTRL2, rmii_delay_val); - mt8195_delay_stage2ps(plat); + delay_stage2ps_v2(plat); return 0; } static const struct mediatek_dwmac_variant mt8195_gmac_variant = { - .dwmac_set_phy_interface = mt8195_set_interface, - .dwmac_set_delay = mt8195_set_delay, + .dwmac_set_phy_interface = set_phy_interface_v2, + .dwmac_set_delay = set_delay_v2, .clk_list = mt8195_dwmac_clk_l, .num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l), .rx_delay_max = 9280, -- 2.55.0 The MT8189 SoC has in the Ethernet control 0 register from the peripheral configuration (pericfg) an additional bit to enable the TX clock signal output. In preparation of MT8189 SoC support, add its definition, use in the set_phy_interface_v2 callback, and a support flag in the platform data. Signed-off-by: Louis-Alexis Eyraud --- drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 28e87990b0a1..bcc0baef3f71 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -36,6 +36,9 @@ #define ETH_FINE_DLY_GTXC BIT(1) #define ETH_FINE_DLY_RXC BIT(0) +/* Peri Configuration register for mt8189 */ +#define MT8189_CTRL0_TXC_OUT_OP BIT(20) + /* Peri Configuration register for mt8195 */ #define MT8195_PERI_ETH_CTRL_BASE 0xFD0 @@ -99,6 +102,7 @@ struct mediatek_dwmac_variant { u32 tx_delay_max; u32 peri_eth_ctrl_offset; u8 dma_bit_mask; + bool use_out_op; }; /* list of clocks required for mac */ @@ -292,6 +296,9 @@ static int set_phy_interface_v2(struct mediatek_dwmac_plat_data *plat, /* MT8195 only support external PHY */ intf_val |= MT8195_EXT_PHY_MODE; + if (plat->variant->use_out_op) + intf_val |= MT8189_CTRL0_TXC_OUT_OP; + regmap_write(plat->peri_regmap, reg_offset + MT8195_PERI_ETH_CTRL0, intf_val); -- 2.55.0 The MT8189 SoC has in the Ethernet control 0 register from the peripheral configuration (pericfg) additional bits to adjust the TX deallocation. In preparation of MT8189 SoC support, add its definition, use in the set_delay_v2 callback, and a support flag in the platform data. Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 25 ++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index bcc0baef3f71..6b0a42b5839f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -37,7 +37,8 @@ #define ETH_FINE_DLY_RXC BIT(0) /* Peri Configuration register for mt8189 */ -#define MT8189_CTRL0_TXC_OUT_OP BIT(20) +#define MT8189_CTRL0_TXC_OUT_OP BIT(20) +#define MT8189_CTRL0_DLY_GTXC_STAGE_FINE GENMASK(11, 6) /* Peri Configuration register for mt8195 */ #define MT8195_PERI_ETH_CTRL_BASE 0xFD0 @@ -103,6 +104,7 @@ struct mediatek_dwmac_variant { u32 peri_eth_ctrl_offset; u8 dma_bit_mask; bool use_out_op; + bool use_stage_fine; }; /* list of clocks required for mac */ @@ -326,9 +328,12 @@ static void delay_stage2ps_v2(struct mediatek_dwmac_plat_data *plat) static int set_delay_v2(struct mediatek_dwmac_plat_data *plat) { - u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0; struct mac_delay_struct *mac_delay = &plat->mac_delay; u32 reg_offset = plat->variant->peri_eth_ctrl_offset; + u32 gtxc_delay_mask = 0; + u32 gtxc_delay_val = 0; + u32 rmii_delay_val = 0; + u32 delay_val = 0; delay_ps2stage_v2(plat); @@ -402,6 +407,9 @@ static int set_delay_v2(struct mediatek_dwmac_plat_data *plat) gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay); gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv); + if (plat->variant->use_stage_fine) + gtxc_delay_val |= MT8189_CTRL0_DLY_GTXC_STAGE_FINE; + delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); @@ -412,12 +420,17 @@ static int set_delay_v2(struct mediatek_dwmac_plat_data *plat) return -EINVAL; } + gtxc_delay_mask = MT8195_RGMII_TXC_PHASE_CTRL | + MT8195_DLY_GTXC_INV | + MT8195_DLY_GTXC_ENABLE | + MT8195_DLY_GTXC_STAGES; + + if (plat->variant->use_stage_fine) + gtxc_delay_mask |= MT8189_CTRL0_DLY_GTXC_STAGE_FINE; + regmap_update_bits(plat->peri_regmap, reg_offset + MT8195_PERI_ETH_CTRL0, - MT8195_RGMII_TXC_PHASE_CTRL | - MT8195_DLY_GTXC_INV | - MT8195_DLY_GTXC_ENABLE | - MT8195_DLY_GTXC_STAGES, + gtxc_delay_mask, gtxc_delay_val); regmap_write(plat->peri_regmap, reg_offset + MT8195_PERI_ETH_CTRL1, -- 2.55.0 Like MT8195 SoC, MT8189 SoC uses the Ethernet control registers from the peripheral configuration (pericfg) but at a different offset. It also needs additional features. Thus, add compatible, clock definitions and specific platform data to support the MT8189 SoC. Signed-off-by: Louis-Alexis Eyraud --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 6b0a42b5839f..e7e336b1f114 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -37,6 +37,8 @@ #define ETH_FINE_DLY_RXC BIT(0) /* Peri Configuration register for mt8189 */ +#define MT8189_PERI_ETH_CTRL_BASE 0x270 + #define MT8189_CTRL0_TXC_OUT_OP BIT(20) #define MT8189_CTRL0_DLY_GTXC_STAGE_FINE GENMASK(11, 6) @@ -116,6 +118,10 @@ static const char * const mt8195_dwmac_clk_l[] = { "axi", "apb", "mac_cg", "mac_main", "ptp_ref" }; +static const char * const mt8189_dwmac_clk_l[] = { + "mac_main", "ptp_ref" +}; + static int set_phy_interface_v1(struct mediatek_dwmac_plat_data *plat, u8 phy_intf_sel) { @@ -444,6 +450,19 @@ static int set_delay_v2(struct mediatek_dwmac_plat_data *plat) return 0; } +static const struct mediatek_dwmac_variant mt8189_gmac_variant = { + .dwmac_set_phy_interface = set_phy_interface_v2, + .dwmac_set_delay = set_delay_v2, + .clk_list = mt8189_dwmac_clk_l, + .num_clks = ARRAY_SIZE(mt8189_dwmac_clk_l), + .dma_bit_mask = 35, + .rx_delay_max = 9280, + .tx_delay_max = 9280, + .peri_eth_ctrl_offset = MT8189_PERI_ETH_CTRL_BASE, + .use_out_op = true, + .use_stage_fine = true, +}; + static const struct mediatek_dwmac_variant mt8195_gmac_variant = { .dwmac_set_phy_interface = set_phy_interface_v2, .dwmac_set_delay = set_delay_v2, @@ -694,6 +713,8 @@ static void mediatek_dwmac_remove(struct platform_device *pdev) static const struct of_device_id mediatek_dwmac_match[] = { { .compatible = "mediatek,mt2712-gmac", .data = &mt2712_gmac_variant }, + { .compatible = "mediatek,mt8189-gmac", + .data = &mt8189_gmac_variant }, { .compatible = "mediatek,mt8195-gmac", .data = &mt8195_gmac_variant }, { } -- 2.55.0